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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.32 98.25 93.31 90.85 86.63 95.50 96.83 91.89


Total test records in report: 1125
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T1023 /workspace/coverage/cover_reg_top/15.edn_intr_test.3594643520 Aug 04 04:33:00 PM PDT 24 Aug 04 04:33:00 PM PDT 24 36730913 ps
T260 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1793001651 Aug 04 04:33:52 PM PDT 24 Aug 04 04:33:54 PM PDT 24 34987061 ps
T1024 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3656544226 Aug 04 04:32:26 PM PDT 24 Aug 04 04:32:28 PM PDT 24 27070727 ps
T1025 /workspace/coverage/cover_reg_top/17.edn_intr_test.2589478010 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:09 PM PDT 24 11339398 ps
T1026 /workspace/coverage/cover_reg_top/4.edn_intr_test.3469587365 Aug 04 04:32:28 PM PDT 24 Aug 04 04:32:29 PM PDT 24 104914720 ps
T1027 /workspace/coverage/cover_reg_top/39.edn_intr_test.3130262036 Aug 04 04:32:53 PM PDT 24 Aug 04 04:32:54 PM PDT 24 12369918 ps
T251 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3048678600 Aug 04 04:32:45 PM PDT 24 Aug 04 04:32:46 PM PDT 24 16639557 ps
T1028 /workspace/coverage/cover_reg_top/2.edn_intr_test.3250902802 Aug 04 04:32:33 PM PDT 24 Aug 04 04:32:34 PM PDT 24 30930069 ps
T271 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2774243694 Aug 04 04:32:24 PM PDT 24 Aug 04 04:32:25 PM PDT 24 32644775 ps
T252 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2182103737 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:27 PM PDT 24 24122063 ps
T1029 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.41315057 Aug 04 04:33:01 PM PDT 24 Aug 04 04:33:02 PM PDT 24 78464803 ps
T1030 /workspace/coverage/cover_reg_top/3.edn_intr_test.3740204121 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:26 PM PDT 24 15001599 ps
T1031 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3733384113 Aug 04 04:32:31 PM PDT 24 Aug 04 04:32:33 PM PDT 24 60684295 ps
T1032 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1692605905 Aug 04 04:33:04 PM PDT 24 Aug 04 04:33:06 PM PDT 24 38295377 ps
T1033 /workspace/coverage/cover_reg_top/5.edn_intr_test.779455379 Aug 04 04:32:22 PM PDT 24 Aug 04 04:32:23 PM PDT 24 12966593 ps
T1034 /workspace/coverage/cover_reg_top/10.edn_intr_test.2773264386 Aug 04 04:32:35 PM PDT 24 Aug 04 04:32:36 PM PDT 24 15867157 ps
T1035 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2770739646 Aug 04 04:32:45 PM PDT 24 Aug 04 04:32:47 PM PDT 24 24384713 ps
T253 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3419335359 Aug 04 04:32:30 PM PDT 24 Aug 04 04:32:34 PM PDT 24 24696995 ps
T1036 /workspace/coverage/cover_reg_top/12.edn_tl_errors.963516965 Aug 04 04:32:48 PM PDT 24 Aug 04 04:32:51 PM PDT 24 80040352 ps
T254 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2602841508 Aug 04 04:32:24 PM PDT 24 Aug 04 04:32:25 PM PDT 24 13229794 ps
T1037 /workspace/coverage/cover_reg_top/1.edn_intr_test.1027523776 Aug 04 04:32:32 PM PDT 24 Aug 04 04:32:34 PM PDT 24 23689510 ps
T288 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1678553886 Aug 04 04:32:38 PM PDT 24 Aug 04 04:32:40 PM PDT 24 81920580 ps
T1038 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4041842886 Aug 04 04:32:36 PM PDT 24 Aug 04 04:32:37 PM PDT 24 202362015 ps
T1039 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2457309986 Aug 04 04:32:57 PM PDT 24 Aug 04 04:32:59 PM PDT 24 157108529 ps
T1040 /workspace/coverage/cover_reg_top/8.edn_tl_errors.4042462512 Aug 04 04:32:36 PM PDT 24 Aug 04 04:32:38 PM PDT 24 532115525 ps
T1041 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.38267206 Aug 04 04:32:26 PM PDT 24 Aug 04 04:32:28 PM PDT 24 27091961 ps
T1042 /workspace/coverage/cover_reg_top/27.edn_intr_test.2297399650 Aug 04 04:32:42 PM PDT 24 Aug 04 04:32:43 PM PDT 24 20473916 ps
T1043 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3871358465 Aug 04 04:32:52 PM PDT 24 Aug 04 04:32:53 PM PDT 24 109225809 ps
T255 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3381481657 Aug 04 04:32:38 PM PDT 24 Aug 04 04:32:40 PM PDT 24 19680093 ps
T283 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1736112568 Aug 04 04:32:53 PM PDT 24 Aug 04 04:32:55 PM PDT 24 255736943 ps
T256 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1204543795 Aug 04 04:32:41 PM PDT 24 Aug 04 04:32:42 PM PDT 24 218290220 ps
T284 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.265548801 Aug 04 04:32:32 PM PDT 24 Aug 04 04:32:35 PM PDT 24 48029118 ps
T1044 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1722383245 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:26 PM PDT 24 23736882 ps
T1045 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3306027200 Aug 04 04:32:54 PM PDT 24 Aug 04 04:32:55 PM PDT 24 74258636 ps
T1046 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3456229495 Aug 04 04:32:42 PM PDT 24 Aug 04 04:32:43 PM PDT 24 21288125 ps
T1047 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2681813074 Aug 04 04:32:55 PM PDT 24 Aug 04 04:32:56 PM PDT 24 44121281 ps
T1048 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1896031931 Aug 04 04:33:02 PM PDT 24 Aug 04 04:33:04 PM PDT 24 91026278 ps
T1049 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.856405104 Aug 04 04:32:30 PM PDT 24 Aug 04 04:32:33 PM PDT 24 293271082 ps
T289 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1580063533 Aug 04 04:32:55 PM PDT 24 Aug 04 04:32:57 PM PDT 24 47644486 ps
T1050 /workspace/coverage/cover_reg_top/20.edn_intr_test.3575385552 Aug 04 04:32:53 PM PDT 24 Aug 04 04:32:54 PM PDT 24 44858644 ps
T1051 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1339770492 Aug 04 04:32:55 PM PDT 24 Aug 04 04:32:56 PM PDT 24 22455119 ps
T1052 /workspace/coverage/cover_reg_top/11.edn_intr_test.3866805103 Aug 04 04:32:34 PM PDT 24 Aug 04 04:32:35 PM PDT 24 14441078 ps
T1053 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1738992945 Aug 04 04:32:40 PM PDT 24 Aug 04 04:32:42 PM PDT 24 77536794 ps
T1054 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3264562963 Aug 04 04:32:38 PM PDT 24 Aug 04 04:32:39 PM PDT 24 46421890 ps
T285 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3680090137 Aug 04 04:32:34 PM PDT 24 Aug 04 04:32:36 PM PDT 24 99612071 ps
T1055 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1957460885 Aug 04 04:32:34 PM PDT 24 Aug 04 04:32:35 PM PDT 24 17510609 ps
T1056 /workspace/coverage/cover_reg_top/35.edn_intr_test.633759218 Aug 04 04:32:45 PM PDT 24 Aug 04 04:32:46 PM PDT 24 22465728 ps
T1057 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2220191886 Aug 04 04:32:48 PM PDT 24 Aug 04 04:32:49 PM PDT 24 42849045 ps
T1058 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3932774752 Aug 04 04:32:59 PM PDT 24 Aug 04 04:33:00 PM PDT 24 48075786 ps
T1059 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.274560553 Aug 04 04:32:58 PM PDT 24 Aug 04 04:33:00 PM PDT 24 33056662 ps
T1060 /workspace/coverage/cover_reg_top/40.edn_intr_test.4147784471 Aug 04 04:33:04 PM PDT 24 Aug 04 04:33:05 PM PDT 24 13955542 ps
T257 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.159673148 Aug 04 04:32:38 PM PDT 24 Aug 04 04:32:39 PM PDT 24 33944460 ps
T1061 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3376266779 Aug 04 04:32:40 PM PDT 24 Aug 04 04:32:41 PM PDT 24 44502514 ps
T1062 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2797190944 Aug 04 04:32:58 PM PDT 24 Aug 04 04:33:00 PM PDT 24 189685780 ps
T1063 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1779847412 Aug 04 04:32:56 PM PDT 24 Aug 04 04:32:57 PM PDT 24 14498259 ps
T258 /workspace/coverage/cover_reg_top/6.edn_csr_rw.405647081 Aug 04 04:32:31 PM PDT 24 Aug 04 04:32:32 PM PDT 24 33709806 ps
T286 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3695585405 Aug 04 04:32:54 PM PDT 24 Aug 04 04:32:56 PM PDT 24 1031981849 ps
T1064 /workspace/coverage/cover_reg_top/37.edn_intr_test.3209213103 Aug 04 04:32:59 PM PDT 24 Aug 04 04:33:00 PM PDT 24 17962324 ps
T1065 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3731038998 Aug 04 04:32:41 PM PDT 24 Aug 04 04:32:42 PM PDT 24 188574485 ps
T1066 /workspace/coverage/cover_reg_top/45.edn_intr_test.2545519212 Aug 04 04:33:02 PM PDT 24 Aug 04 04:33:03 PM PDT 24 14095607 ps
T1067 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1528003531 Aug 04 04:32:39 PM PDT 24 Aug 04 04:32:40 PM PDT 24 100084170 ps
T1068 /workspace/coverage/cover_reg_top/28.edn_intr_test.3390266319 Aug 04 04:33:03 PM PDT 24 Aug 04 04:33:04 PM PDT 24 13969744 ps
T287 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.55106489 Aug 04 04:32:51 PM PDT 24 Aug 04 04:32:53 PM PDT 24 40897282 ps
T1069 /workspace/coverage/cover_reg_top/48.edn_intr_test.2223635170 Aug 04 04:32:55 PM PDT 24 Aug 04 04:32:56 PM PDT 24 38603974 ps
T1070 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2425687561 Aug 04 04:32:33 PM PDT 24 Aug 04 04:32:35 PM PDT 24 51243226 ps
T1071 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2401410868 Aug 04 04:32:56 PM PDT 24 Aug 04 04:32:57 PM PDT 24 86568771 ps
T1072 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1570151457 Aug 04 04:32:59 PM PDT 24 Aug 04 04:33:00 PM PDT 24 105650103 ps
T1073 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2429671637 Aug 04 04:32:35 PM PDT 24 Aug 04 04:32:36 PM PDT 24 23706803 ps
T1074 /workspace/coverage/cover_reg_top/6.edn_intr_test.3368282417 Aug 04 04:32:41 PM PDT 24 Aug 04 04:32:42 PM PDT 24 12692193 ps
T1075 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.416883200 Aug 04 04:32:41 PM PDT 24 Aug 04 04:32:44 PM PDT 24 348737010 ps
T1076 /workspace/coverage/cover_reg_top/43.edn_intr_test.3227594378 Aug 04 04:32:41 PM PDT 24 Aug 04 04:32:41 PM PDT 24 25528490 ps
T1077 /workspace/coverage/cover_reg_top/5.edn_csr_rw.551455170 Aug 04 04:32:35 PM PDT 24 Aug 04 04:32:36 PM PDT 24 19138872 ps
T1078 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.4063525218 Aug 04 04:32:23 PM PDT 24 Aug 04 04:32:28 PM PDT 24 370454235 ps
T1079 /workspace/coverage/cover_reg_top/31.edn_intr_test.1406086033 Aug 04 04:32:43 PM PDT 24 Aug 04 04:32:44 PM PDT 24 42134001 ps
T259 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3617475881 Aug 04 04:32:40 PM PDT 24 Aug 04 04:32:41 PM PDT 24 87970116 ps
T1080 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1587214228 Aug 04 04:32:55 PM PDT 24 Aug 04 04:32:57 PM PDT 24 69907456 ps
T262 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3958374411 Aug 04 04:32:46 PM PDT 24 Aug 04 04:32:48 PM PDT 24 43260596 ps
T1081 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2556458268 Aug 04 04:32:55 PM PDT 24 Aug 04 04:32:57 PM PDT 24 122087825 ps
T261 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1770184521 Aug 04 04:32:35 PM PDT 24 Aug 04 04:32:36 PM PDT 24 29772468 ps
T1082 /workspace/coverage/cover_reg_top/24.edn_intr_test.3389895268 Aug 04 04:33:03 PM PDT 24 Aug 04 04:33:04 PM PDT 24 14634150 ps
T1083 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2032254982 Aug 04 04:32:47 PM PDT 24 Aug 04 04:32:49 PM PDT 24 52193084 ps
T1084 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3063008449 Aug 04 04:32:49 PM PDT 24 Aug 04 04:32:52 PM PDT 24 106216568 ps
T1085 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1287423534 Aug 04 04:32:19 PM PDT 24 Aug 04 04:32:21 PM PDT 24 85519472 ps
T1086 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2315174024 Aug 04 04:32:39 PM PDT 24 Aug 04 04:32:40 PM PDT 24 19627021 ps
T1087 /workspace/coverage/cover_reg_top/30.edn_intr_test.826210250 Aug 04 04:32:52 PM PDT 24 Aug 04 04:32:53 PM PDT 24 15382170 ps
T1088 /workspace/coverage/cover_reg_top/25.edn_intr_test.559915110 Aug 04 04:32:44 PM PDT 24 Aug 04 04:32:45 PM PDT 24 45367348 ps
T1089 /workspace/coverage/cover_reg_top/16.edn_intr_test.1317328800 Aug 04 04:32:53 PM PDT 24 Aug 04 04:32:54 PM PDT 24 35197043 ps
T1090 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3306736820 Aug 04 04:32:55 PM PDT 24 Aug 04 04:32:56 PM PDT 24 102704168 ps
T1091 /workspace/coverage/cover_reg_top/12.edn_intr_test.29853981 Aug 04 04:32:51 PM PDT 24 Aug 04 04:32:52 PM PDT 24 22542234 ps
T1092 /workspace/coverage/cover_reg_top/41.edn_intr_test.353339059 Aug 04 04:33:06 PM PDT 24 Aug 04 04:33:07 PM PDT 24 66921982 ps
T1093 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1341609664 Aug 04 04:32:50 PM PDT 24 Aug 04 04:32:52 PM PDT 24 86054038 ps
T1094 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4103078848 Aug 04 04:32:41 PM PDT 24 Aug 04 04:32:42 PM PDT 24 58347247 ps
T1095 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2813486714 Aug 04 04:32:23 PM PDT 24 Aug 04 04:32:29 PM PDT 24 996728789 ps
T263 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.529914483 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:22 PM PDT 24 23510581 ps
T1096 /workspace/coverage/cover_reg_top/9.edn_intr_test.3824074502 Aug 04 04:32:32 PM PDT 24 Aug 04 04:32:33 PM PDT 24 11975976 ps
T1097 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2936079984 Aug 04 04:32:49 PM PDT 24 Aug 04 04:32:51 PM PDT 24 38073752 ps
T1098 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2899034084 Aug 04 04:32:26 PM PDT 24 Aug 04 04:32:29 PM PDT 24 163430082 ps
T1099 /workspace/coverage/cover_reg_top/49.edn_intr_test.322985713 Aug 04 04:32:50 PM PDT 24 Aug 04 04:32:51 PM PDT 24 32460826 ps
T1100 /workspace/coverage/cover_reg_top/46.edn_intr_test.1866782592 Aug 04 04:32:59 PM PDT 24 Aug 04 04:33:00 PM PDT 24 13765225 ps
T1101 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.271690496 Aug 04 04:32:50 PM PDT 24 Aug 04 04:32:52 PM PDT 24 33501623 ps
T1102 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1930588084 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:19 PM PDT 24 91876489 ps
T1103 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4153665830 Aug 04 04:32:51 PM PDT 24 Aug 04 04:32:52 PM PDT 24 46538146 ps
T1104 /workspace/coverage/cover_reg_top/18.edn_csr_rw.848594892 Aug 04 04:32:51 PM PDT 24 Aug 04 04:32:52 PM PDT 24 60410361 ps
T264 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3230664017 Aug 04 04:32:23 PM PDT 24 Aug 04 04:32:25 PM PDT 24 34987709 ps
T1105 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2455138526 Aug 04 04:32:42 PM PDT 24 Aug 04 04:32:43 PM PDT 24 42204612 ps
T1106 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2188550851 Aug 04 04:32:48 PM PDT 24 Aug 04 04:32:49 PM PDT 24 327405167 ps
T1107 /workspace/coverage/cover_reg_top/19.edn_intr_test.1113436363 Aug 04 04:32:37 PM PDT 24 Aug 04 04:32:38 PM PDT 24 15910056 ps
T1108 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1092891616 Aug 04 04:32:47 PM PDT 24 Aug 04 04:32:51 PM PDT 24 187762418 ps
T1109 /workspace/coverage/cover_reg_top/21.edn_intr_test.2537088206 Aug 04 04:32:47 PM PDT 24 Aug 04 04:32:48 PM PDT 24 42709094 ps
T1110 /workspace/coverage/cover_reg_top/7.edn_intr_test.1980638674 Aug 04 04:32:28 PM PDT 24 Aug 04 04:32:29 PM PDT 24 46255710 ps
T1111 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.921962035 Aug 04 04:32:26 PM PDT 24 Aug 04 04:32:28 PM PDT 24 56651745 ps
T1112 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2702829591 Aug 04 04:32:56 PM PDT 24 Aug 04 04:32:58 PM PDT 24 33841004 ps
T1113 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2025498998 Aug 04 04:33:02 PM PDT 24 Aug 04 04:33:06 PM PDT 24 241210141 ps
T1114 /workspace/coverage/cover_reg_top/0.edn_intr_test.2948992557 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:21 PM PDT 24 133964229 ps
T1115 /workspace/coverage/cover_reg_top/44.edn_intr_test.2695250709 Aug 04 04:32:58 PM PDT 24 Aug 04 04:32:59 PM PDT 24 38821046 ps
T1116 /workspace/coverage/cover_reg_top/47.edn_intr_test.2445280301 Aug 04 04:32:48 PM PDT 24 Aug 04 04:32:49 PM PDT 24 26776367 ps
T1117 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3474661020 Aug 04 04:32:34 PM PDT 24 Aug 04 04:32:39 PM PDT 24 346992716 ps
T1118 /workspace/coverage/cover_reg_top/36.edn_intr_test.3888329017 Aug 04 04:33:04 PM PDT 24 Aug 04 04:33:05 PM PDT 24 19793617 ps
T1119 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1731935728 Aug 04 04:32:56 PM PDT 24 Aug 04 04:32:57 PM PDT 24 34906504 ps
T1120 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1709239635 Aug 04 04:32:54 PM PDT 24 Aug 04 04:32:55 PM PDT 24 20692177 ps
T1121 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2098809494 Aug 04 04:32:55 PM PDT 24 Aug 04 04:32:57 PM PDT 24 138322740 ps
T1122 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3126412422 Aug 04 04:32:34 PM PDT 24 Aug 04 04:32:35 PM PDT 24 11373571 ps
T1123 /workspace/coverage/cover_reg_top/19.edn_tl_errors.4082924096 Aug 04 04:32:42 PM PDT 24 Aug 04 04:32:46 PM PDT 24 944192952 ps
T1124 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.688923179 Aug 04 04:32:32 PM PDT 24 Aug 04 04:32:34 PM PDT 24 21936855 ps
T1125 /workspace/coverage/cover_reg_top/33.edn_intr_test.1760048234 Aug 04 04:32:45 PM PDT 24 Aug 04 04:32:46 PM PDT 24 13843372 ps

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.925410326
Short name T12
Test name
Test status
Simulation time 116863301 ps
CPU time 1.06 seconds
Started Aug 04 05:41:36 PM PDT 24
Finished Aug 04 05:41:37 PM PDT 24
Peak memory 216976 kb
Host smart-0c938ef8-c4f6-4234-943c-f20138ec90fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925410326 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.925410326
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.611012197
Short name T19
Test name
Test status
Simulation time 136890629949 ps
CPU time 724.23 seconds
Started Aug 04 05:41:01 PM PDT 24
Finished Aug 04 05:53:05 PM PDT 24
Peak memory 220176 kb
Host smart-54e67bfe-fd26-414e-9ee1-d6f10eefd7f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611012197 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.611012197
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.edn_genbits.3433271894
Short name T25
Test name
Test status
Simulation time 151981775 ps
CPU time 3.11 seconds
Started Aug 04 05:42:29 PM PDT 24
Finished Aug 04 05:42:32 PM PDT 24
Peak memory 220332 kb
Host smart-7294c68c-9fff-4d74-8a5f-b731bfdc15ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433271894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3433271894
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1593622181
Short name T1
Test name
Test status
Simulation time 42689711 ps
CPU time 1.14 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 219620 kb
Host smart-539cb97c-b843-46bd-a58d-eeadb7e8aee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593622181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1593622181
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/76.edn_alert.2566928143
Short name T3
Test name
Test status
Simulation time 35455089 ps
CPU time 1.25 seconds
Started Aug 04 05:41:57 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 218728 kb
Host smart-b0254073-b23b-4d89-8e99-5fcc634e5208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566928143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.2566928143
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.45044854
Short name T6
Test name
Test status
Simulation time 22822292 ps
CPU time 1.28 seconds
Started Aug 04 05:42:24 PM PDT 24
Finished Aug 04 05:42:26 PM PDT 24
Peak memory 224024 kb
Host smart-7a5b5791-c104-4c39-a229-42a9be2dc22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45044854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.45044854
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3112885650
Short name T22
Test name
Test status
Simulation time 55908928 ps
CPU time 1.15 seconds
Started Aug 04 05:41:52 PM PDT 24
Finished Aug 04 05:41:53 PM PDT 24
Peak memory 218408 kb
Host smart-61459e20-b967-40c2-9e37-67f6e5be218a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112885650 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3112885650
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/106.edn_alert.51158720
Short name T142
Test name
Test status
Simulation time 28676792 ps
CPU time 1.35 seconds
Started Aug 04 05:42:18 PM PDT 24
Finished Aug 04 05:42:19 PM PDT 24
Peak memory 219352 kb
Host smart-62c827ca-866e-4851-96a0-8b61bc0d74d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51158720 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.51158720
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert.2590462941
Short name T300
Test name
Test status
Simulation time 34352768 ps
CPU time 1.3 seconds
Started Aug 04 05:40:54 PM PDT 24
Finished Aug 04 05:40:56 PM PDT 24
Peak memory 220468 kb
Host smart-6316ad77-2beb-44ec-a9ca-25c31a8c4d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590462941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2590462941
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/12.edn_intr.2681672054
Short name T77
Test name
Test status
Simulation time 29961693 ps
CPU time 0.97 seconds
Started Aug 04 05:41:02 PM PDT 24
Finished Aug 04 05:41:13 PM PDT 24
Peak memory 215928 kb
Host smart-4b6c877f-91a2-4c4f-a4ec-ee4f33f3c045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681672054 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2681672054
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2677057991
Short name T544
Test name
Test status
Simulation time 18311404 ps
CPU time 1.02 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:40:46 PM PDT 24
Peak memory 207096 kb
Host smart-c5382936-45c7-4f83-978e-199145e92064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677057991 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2677057991
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/105.edn_alert.4293038294
Short name T16
Test name
Test status
Simulation time 139764903 ps
CPU time 1.22 seconds
Started Aug 04 05:42:14 PM PDT 24
Finished Aug 04 05:42:15 PM PDT 24
Peak memory 221720 kb
Host smart-106005f0-fa24-4c85-9602-7da74b7aacb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293038294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.4293038294
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.296953382
Short name T221
Test name
Test status
Simulation time 258660274 ps
CPU time 4.8 seconds
Started Aug 04 04:32:19 PM PDT 24
Finished Aug 04 04:32:24 PM PDT 24
Peak memory 206780 kb
Host smart-1f5c08f6-1d4b-459c-8898-6250154e1edd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296953382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.296953382
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/4.edn_genbits.110903127
Short name T63
Test name
Test status
Simulation time 84579433 ps
CPU time 1.4 seconds
Started Aug 04 05:40:54 PM PDT 24
Finished Aug 04 05:40:55 PM PDT 24
Peak memory 218648 kb
Host smart-d4b595b0-84ff-47a1-934f-d2f8f23376db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110903127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.110903127
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1941603040
Short name T58
Test name
Test status
Simulation time 42390010 ps
CPU time 0.86 seconds
Started Aug 04 05:40:49 PM PDT 24
Finished Aug 04 05:40:50 PM PDT 24
Peak memory 215196 kb
Host smart-fb3bfece-09a5-4f41-8933-cd5fe537b328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941603040 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1941603040
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2983187333
Short name T8
Test name
Test status
Simulation time 105638022 ps
CPU time 1.13 seconds
Started Aug 04 05:40:44 PM PDT 24
Finished Aug 04 05:40:45 PM PDT 24
Peak memory 216836 kb
Host smart-7f587c43-8a8a-4b91-bc31-d42213049aa7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983187333 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2983187333
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_intr.3046132853
Short name T74
Test name
Test status
Simulation time 72935107 ps
CPU time 0.8 seconds
Started Aug 04 05:41:11 PM PDT 24
Finished Aug 04 05:41:12 PM PDT 24
Peak memory 215564 kb
Host smart-538b26b6-5168-4b88-a7f3-646bd8740471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046132853 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3046132853
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/12.edn_disable.1355726390
Short name T84
Test name
Test status
Simulation time 13929777 ps
CPU time 0.95 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 216424 kb
Host smart-8b6219ef-56f1-4857-8a60-6ffed72e1f4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355726390 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1355726390
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/121.edn_alert.4051926730
Short name T130
Test name
Test status
Simulation time 222042881 ps
CPU time 1.12 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:36 PM PDT 24
Peak memory 218608 kb
Host smart-616a5086-1615-4b57-a57b-535c21cb9fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051926730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.4051926730
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable.3451439067
Short name T91
Test name
Test status
Simulation time 36486715 ps
CPU time 0.87 seconds
Started Aug 04 05:40:58 PM PDT 24
Finished Aug 04 05:40:59 PM PDT 24
Peak memory 216252 kb
Host smart-bc7d0095-4970-48b3-952d-93d8e6403c5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451439067 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3451439067
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable.1251772972
Short name T100
Test name
Test status
Simulation time 11698101 ps
CPU time 0.9 seconds
Started Aug 04 05:41:34 PM PDT 24
Finished Aug 04 05:41:35 PM PDT 24
Peak memory 216336 kb
Host smart-f3d60b31-cb1b-4216-b766-c02407d57912
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251772972 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1251772972
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3381481657
Short name T255
Test name
Test status
Simulation time 19680093 ps
CPU time 0.83 seconds
Started Aug 04 04:32:38 PM PDT 24
Finished Aug 04 04:32:40 PM PDT 24
Peak memory 206216 kb
Host smart-ec331e4f-1242-452b-8d16-81582f579cef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381481657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3381481657
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2544732844
Short name T21
Test name
Test status
Simulation time 75314400643 ps
CPU time 1867.25 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 06:12:54 PM PDT 24
Peak memory 228260 kb
Host smart-f3fee114-08b8-4e8d-82dd-f6a0b3cb39f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544732844 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2544732844
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.edn_alert.233153692
Short name T196
Test name
Test status
Simulation time 21033255 ps
CPU time 1.1 seconds
Started Aug 04 05:42:21 PM PDT 24
Finished Aug 04 05:42:23 PM PDT 24
Peak memory 219488 kb
Host smart-5de4c4e8-7b60-471d-a569-23a418a6886f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233153692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.233153692
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/162.edn_alert.2559494332
Short name T292
Test name
Test status
Simulation time 41731881 ps
CPU time 1.1 seconds
Started Aug 04 05:42:33 PM PDT 24
Finished Aug 04 05:42:34 PM PDT 24
Peak memory 218988 kb
Host smart-ff77a7a8-0cbc-4432-85ec-542ce07a0cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559494332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2559494332
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/52.edn_alert.1185650135
Short name T17
Test name
Test status
Simulation time 78727408 ps
CPU time 1.21 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 219772 kb
Host smart-62eef4aa-6262-4cb7-8fb3-3a911afd1bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185650135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1185650135
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/167.edn_alert.3009142292
Short name T671
Test name
Test status
Simulation time 53311298 ps
CPU time 1.11 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 220092 kb
Host smart-f6d5df2b-1ddc-4108-917f-36af07160987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009142292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.3009142292
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert.3952961416
Short name T204
Test name
Test status
Simulation time 32037270 ps
CPU time 1.34 seconds
Started Aug 04 05:41:37 PM PDT 24
Finished Aug 04 05:41:38 PM PDT 24
Peak memory 215768 kb
Host smart-4c273de2-c6bf-49b0-be81-013d14e9f325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952961416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3952961416
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/49.edn_disable.1750356827
Short name T176
Test name
Test status
Simulation time 15882366 ps
CPU time 0.99 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 215584 kb
Host smart-12c1813c-d886-49d8-9b20-28e2fee8db00
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750356827 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1750356827
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/151.edn_genbits.1744542008
Short name T64
Test name
Test status
Simulation time 28179316 ps
CPU time 1.26 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 217112 kb
Host smart-8c17da25-aa86-4bd6-929f-ea5229932c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744542008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1744542008
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.4129640713
Short name T129
Test name
Test status
Simulation time 29697950 ps
CPU time 1.29 seconds
Started Aug 04 05:42:25 PM PDT 24
Finished Aug 04 05:42:26 PM PDT 24
Peak memory 219832 kb
Host smart-6b7b1944-4fa5-4f83-bfe9-c0457802d8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129640713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.4129640713
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/142.edn_alert.1466043002
Short name T302
Test name
Test status
Simulation time 31760595 ps
CPU time 1.19 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 218532 kb
Host smart-51937f01-1dff-42db-8ac8-6f0b799f70f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466043002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1466043002
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/170.edn_alert.2206058581
Short name T687
Test name
Test status
Simulation time 28300991 ps
CPU time 1.22 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 220720 kb
Host smart-c3b36cf3-21e0-4541-9338-802b2734f19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206058581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2206058581
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/28.edn_genbits.3684738630
Short name T364
Test name
Test status
Simulation time 105098784 ps
CPU time 1.21 seconds
Started Aug 04 05:41:37 PM PDT 24
Finished Aug 04 05:41:39 PM PDT 24
Peak memory 219836 kb
Host smart-d0f770af-0c0e-4cf2-befb-18683d9f5615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684738630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3684738630
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.2870243512
Short name T158
Test name
Test status
Simulation time 44559797 ps
CPU time 1.36 seconds
Started Aug 04 05:42:24 PM PDT 24
Finished Aug 04 05:42:25 PM PDT 24
Peak memory 219864 kb
Host smart-f62568f0-4e7c-4307-b2c0-bce52c454055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870243512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.2870243512
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/60.edn_alert.1162368033
Short name T134
Test name
Test status
Simulation time 67198627 ps
CPU time 1.14 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 218760 kb
Host smart-672574dd-e136-4299-842f-754cec835dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162368033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1162368033
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/0.edn_err.2503012979
Short name T103
Test name
Test status
Simulation time 28929909 ps
CPU time 0.9 seconds
Started Aug 04 05:40:50 PM PDT 24
Finished Aug 04 05:40:51 PM PDT 24
Peak memory 218316 kb
Host smart-82587c01-f7a5-4c5e-8e42-efd42cbfb638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503012979 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2503012979
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3077376386
Short name T975
Test name
Test status
Simulation time 73683773 ps
CPU time 1.25 seconds
Started Aug 04 05:40:51 PM PDT 24
Finished Aug 04 05:40:53 PM PDT 24
Peak memory 216868 kb
Host smart-eb38dee4-3a3b-46c9-93ae-8c3fa70b4e9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077376386 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3077376386
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/136.edn_alert.4112347683
Short name T131
Test name
Test status
Simulation time 95085992 ps
CPU time 1.2 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 215764 kb
Host smart-5af99225-c813-40a6-a550-7a2039719556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112347683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.4112347683
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.1981118407
Short name T929
Test name
Test status
Simulation time 42786756 ps
CPU time 0.86 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 216324 kb
Host smart-b8855414-a46e-4bf5-9a60-c17c263b3d05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981118407 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1981118407
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2285283006
Short name T530
Test name
Test status
Simulation time 112251343 ps
CPU time 0.97 seconds
Started Aug 04 05:41:01 PM PDT 24
Finished Aug 04 05:41:02 PM PDT 24
Peak memory 216816 kb
Host smart-a5bc3c95-83a9-4ff4-ba0e-22536fe8a0fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285283006 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2285283006
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1606085144
Short name T856
Test name
Test status
Simulation time 38903726 ps
CPU time 0.89 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:08 PM PDT 24
Peak memory 219088 kb
Host smart-d391efcc-ec14-410b-9686-23af34f613ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606085144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1606085144
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1108503524
Short name T427
Test name
Test status
Simulation time 42409930 ps
CPU time 1.04 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:08 PM PDT 24
Peak memory 216916 kb
Host smart-d5fc5da9-b283-49c8-b0e8-8cde5e1b2a4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108503524 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1108503524
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.495302741
Short name T153
Test name
Test status
Simulation time 267302884 ps
CPU time 1.09 seconds
Started Aug 04 05:41:09 PM PDT 24
Finished Aug 04 05:41:11 PM PDT 24
Peak memory 217048 kb
Host smart-94023600-f5a8-4462-8c69-437c9b4e0649
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495302741 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.495302741
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2554319248
Short name T964
Test name
Test status
Simulation time 50194599 ps
CPU time 1.57 seconds
Started Aug 04 05:41:19 PM PDT 24
Finished Aug 04 05:41:21 PM PDT 24
Peak memory 216760 kb
Host smart-01f321ec-d6de-43a0-84f5-0783b924256b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554319248 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2554319248
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_disable.3728939099
Short name T83
Test name
Test status
Simulation time 14691789 ps
CPU time 0.89 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 216464 kb
Host smart-52444a4e-d405-48ec-af1a-ec90c3e17cdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728939099 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3728939099
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/60.edn_err.1472160782
Short name T111
Test name
Test status
Simulation time 42085711 ps
CPU time 0.97 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 223820 kb
Host smart-a4b9d7de-f50c-4d68-b2ac-b9be19717796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472160782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1472160782
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/140.edn_genbits.1584507093
Short name T307
Test name
Test status
Simulation time 91338237 ps
CPU time 1.29 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218620 kb
Host smart-2de4e7da-f2ab-4ad0-b5c6-b0fa6cf0be7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584507093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1584507093
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert_test.2133474776
Short name T354
Test name
Test status
Simulation time 16472708 ps
CPU time 1.03 seconds
Started Aug 04 05:40:42 PM PDT 24
Finished Aug 04 05:40:43 PM PDT 24
Peak memory 215156 kb
Host smart-4a4bf3aa-7267-46f0-9da0-49d62c4d37a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133474776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2133474776
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_genbits.3203154888
Short name T48
Test name
Test status
Simulation time 32456057 ps
CPU time 1.32 seconds
Started Aug 04 05:41:32 PM PDT 24
Finished Aug 04 05:41:33 PM PDT 24
Peak memory 217420 kb
Host smart-176f4746-1b93-4670-a8f8-e467d8b7e144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203154888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3203154888
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_genbits.2962308836
Short name T706
Test name
Test status
Simulation time 86394158 ps
CPU time 1.41 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 219200 kb
Host smart-e8468c85-2506-470a-b5c9-86bd482b6230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962308836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2962308836
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_genbits.3359003033
Short name T331
Test name
Test status
Simulation time 93947357 ps
CPU time 1.38 seconds
Started Aug 04 05:40:58 PM PDT 24
Finished Aug 04 05:40:59 PM PDT 24
Peak memory 219796 kb
Host smart-30349d2b-a5a6-40fc-a0ec-4c433a324b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359003033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3359003033
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.2104741978
Short name T596
Test name
Test status
Simulation time 55356536 ps
CPU time 1.14 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 217328 kb
Host smart-f4497cc8-dcad-410f-afa8-fffc825753d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104741978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2104741978
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3910802831
Short name T80
Test name
Test status
Simulation time 21126816 ps
CPU time 1.1 seconds
Started Aug 04 05:41:31 PM PDT 24
Finished Aug 04 05:41:32 PM PDT 24
Peak memory 215936 kb
Host smart-091bcc08-6844-442f-bf42-288d49fe6085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910802831 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3910802831
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/120.edn_genbits.1901233727
Short name T67
Test name
Test status
Simulation time 55613218 ps
CPU time 1.44 seconds
Started Aug 04 05:42:27 PM PDT 24
Finished Aug 04 05:42:28 PM PDT 24
Peak memory 218708 kb
Host smart-7598131a-3a14-4a10-ae1a-003a0d7b403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901233727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1901233727
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.1113814992
Short name T321
Test name
Test status
Simulation time 168542086 ps
CPU time 1.28 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 219976 kb
Host smart-a39ae327-105e-43cb-ab94-a0a4a494f842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113814992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1113814992
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4087885985
Short name T265
Test name
Test status
Simulation time 20029690 ps
CPU time 1.07 seconds
Started Aug 04 04:32:47 PM PDT 24
Finished Aug 04 04:32:48 PM PDT 24
Peak memory 206604 kb
Host smart-974c1da7-d050-46fa-a527-bd73c2c51402
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087885985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.4087885985
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3695585405
Short name T286
Test name
Test status
Simulation time 1031981849 ps
CPU time 2.44 seconds
Started Aug 04 04:32:54 PM PDT 24
Finished Aug 04 04:32:56 PM PDT 24
Peak memory 206828 kb
Host smart-b2ee8318-445e-4195-88fc-66184dea75fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695585405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3695585405
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_stress_all.3780446528
Short name T868
Test name
Test status
Simulation time 127389576 ps
CPU time 2.31 seconds
Started Aug 04 05:40:49 PM PDT 24
Finished Aug 04 05:40:51 PM PDT 24
Peak memory 217328 kb
Host smart-671696b2-0923-4c95-b6dd-aae54f34e040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780446528 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3780446528
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_alert.144891452
Short name T622
Test name
Test status
Simulation time 26801636 ps
CPU time 1.17 seconds
Started Aug 04 05:42:15 PM PDT 24
Finished Aug 04 05:42:16 PM PDT 24
Peak memory 218680 kb
Host smart-fde8f10c-6c4f-4af3-8bab-1ff12274f54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144891452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.144891452
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.55125944
Short name T316
Test name
Test status
Simulation time 168915016 ps
CPU time 1.3 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 218780 kb
Host smart-3cb73d05-a357-4274-84f4-6b9c0c1f47fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55125944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.55125944
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2952092553
Short name T786
Test name
Test status
Simulation time 61773090 ps
CPU time 1.12 seconds
Started Aug 04 05:42:30 PM PDT 24
Finished Aug 04 05:42:31 PM PDT 24
Peak memory 219012 kb
Host smart-8f4dcdd6-7958-48d1-acfd-3cadeef5ffc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952092553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2952092553
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1794509429
Short name T30
Test name
Test status
Simulation time 141583333 ps
CPU time 3.1 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 218552 kb
Host smart-76b50f1e-84d6-422b-a29e-1cea225be4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794509429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1794509429
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.4294676953
Short name T280
Test name
Test status
Simulation time 32096097 ps
CPU time 1.13 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:08 PM PDT 24
Peak memory 216784 kb
Host smart-19c2562d-0816-4714-823f-26e3363ea628
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294676953 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.4294676953
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/213.edn_genbits.3580887312
Short name T317
Test name
Test status
Simulation time 34693765 ps
CPU time 1.31 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 219488 kb
Host smart-16c2e935-1a48-4679-9f46-8fc68825f275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580887312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3580887312
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1639194774
Short name T282
Test name
Test status
Simulation time 48456065 ps
CPU time 1.48 seconds
Started Aug 04 05:42:45 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 219556 kb
Host smart-7dfe367c-42a0-4cd4-84a2-1bab5897b692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639194774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1639194774
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.938662046
Short name T326
Test name
Test status
Simulation time 46041116 ps
CPU time 1.17 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218556 kb
Host smart-9f33ded0-73d9-45b9-ad2d-a7b2287a0ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938662046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.938662046
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3260643304
Short name T584
Test name
Test status
Simulation time 675139108681 ps
CPU time 1589.64 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 06:08:15 PM PDT 24
Peak memory 223728 kb
Host smart-0e7db958-8097-4724-95ac-a253f0888b80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260643304 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3260643304
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.edn_intr.2497706155
Short name T719
Test name
Test status
Simulation time 47938228 ps
CPU time 0.85 seconds
Started Aug 04 05:41:10 PM PDT 24
Finished Aug 04 05:41:11 PM PDT 24
Peak memory 215624 kb
Host smart-37c7233b-a56d-4edc-8aff-1a3f83b3edea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497706155 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2497706155
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/11.edn_disable.1513779027
Short name T203
Test name
Test status
Simulation time 17810369 ps
CPU time 0.87 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 216324 kb
Host smart-d4a8df90-ec25-410f-87b7-4de2b55dee54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513779027 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1513779027
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/70.edn_alert.3772837882
Short name T144
Test name
Test status
Simulation time 367863480 ps
CPU time 1.3 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 219168 kb
Host smart-a14b462b-205b-4c56-8806-fa7554bc13d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772837882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3772837882
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.159673148
Short name T257
Test name
Test status
Simulation time 33944460 ps
CPU time 1.5 seconds
Started Aug 04 04:32:38 PM PDT 24
Finished Aug 04 04:32:39 PM PDT 24
Peak memory 206508 kb
Host smart-7fd56601-6929-46bf-98c0-ce2551a24d78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159673148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.159673148
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1092891616
Short name T1108
Test name
Test status
Simulation time 187762418 ps
CPU time 2.94 seconds
Started Aug 04 04:32:47 PM PDT 24
Finished Aug 04 04:32:51 PM PDT 24
Peak memory 206540 kb
Host smart-7cc22225-0a2b-4818-aefe-2f052992806d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092891616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1092891616
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1746485226
Short name T1021
Test name
Test status
Simulation time 22009028 ps
CPU time 0.84 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 206456 kb
Host smart-a5c6d0d7-f783-4eef-b543-a1ea0094477c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746485226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1746485226
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2556458268
Short name T1081
Test name
Test status
Simulation time 122087825 ps
CPU time 1.47 seconds
Started Aug 04 04:32:55 PM PDT 24
Finished Aug 04 04:32:57 PM PDT 24
Peak memory 223216 kb
Host smart-e604fb71-2403-4f66-91cc-bdf9b8c1c832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556458268 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2556458268
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2948992557
Short name T1114
Test name
Test status
Simulation time 133964229 ps
CPU time 0.82 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 206440 kb
Host smart-9ae904c5-6543-43d8-bc3a-5a0b060ad515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948992557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2948992557
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3656544226
Short name T1024
Test name
Test status
Simulation time 27070727 ps
CPU time 1.79 seconds
Started Aug 04 04:32:26 PM PDT 24
Finished Aug 04 04:32:28 PM PDT 24
Peak memory 214820 kb
Host smart-982da996-1317-468a-a5cc-da3f1e2e8537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656544226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3656544226
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3230664017
Short name T264
Test name
Test status
Simulation time 34987709 ps
CPU time 1.18 seconds
Started Aug 04 04:32:23 PM PDT 24
Finished Aug 04 04:32:25 PM PDT 24
Peak memory 206628 kb
Host smart-b5f93f73-558f-4bc9-a9fd-c70079da3977
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230664017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3230664017
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.4063525218
Short name T1078
Test name
Test status
Simulation time 370454235 ps
CPU time 2.95 seconds
Started Aug 04 04:32:23 PM PDT 24
Finished Aug 04 04:32:28 PM PDT 24
Peak memory 206460 kb
Host smart-bf137512-4946-4f56-8949-ab617d8c81b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063525218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.4063525218
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.271690496
Short name T1101
Test name
Test status
Simulation time 33501623 ps
CPU time 0.92 seconds
Started Aug 04 04:32:50 PM PDT 24
Finished Aug 04 04:32:52 PM PDT 24
Peak memory 206492 kb
Host smart-00cb17dc-23f1-4632-beba-aa95e56856db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271690496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.271690496
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1257133443
Short name T1002
Test name
Test status
Simulation time 145256128 ps
CPU time 1.14 seconds
Started Aug 04 04:32:36 PM PDT 24
Finished Aug 04 04:32:37 PM PDT 24
Peak memory 214876 kb
Host smart-ec29a0ca-c1ca-4bc2-9237-7006ad6c7daa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257133443 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1257133443
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1722383245
Short name T1044
Test name
Test status
Simulation time 23736882 ps
CPU time 0.85 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 206476 kb
Host smart-4078c8fb-d377-4ccf-a950-5dd75597cfba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722383245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1722383245
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1027523776
Short name T1037
Test name
Test status
Simulation time 23689510 ps
CPU time 0.82 seconds
Started Aug 04 04:32:32 PM PDT 24
Finished Aug 04 04:32:34 PM PDT 24
Peak memory 206444 kb
Host smart-9129564f-8e35-4ed4-8875-13f7770672f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027523776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1027523776
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2936079984
Short name T1097
Test name
Test status
Simulation time 38073752 ps
CPU time 1.08 seconds
Started Aug 04 04:32:49 PM PDT 24
Finished Aug 04 04:32:51 PM PDT 24
Peak memory 206796 kb
Host smart-399fa231-34e0-4fe7-bc9a-e85fc5ac9d20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936079984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2936079984
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1697678635
Short name T999
Test name
Test status
Simulation time 213180085 ps
CPU time 2.24 seconds
Started Aug 04 04:32:28 PM PDT 24
Finished Aug 04 04:32:30 PM PDT 24
Peak memory 214888 kb
Host smart-9bed225d-a842-4364-910d-33c278298556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697678635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1697678635
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.265548801
Short name T284
Test name
Test status
Simulation time 48029118 ps
CPU time 1.59 seconds
Started Aug 04 04:32:32 PM PDT 24
Finished Aug 04 04:32:35 PM PDT 24
Peak memory 214740 kb
Host smart-42f94679-baf0-4a2b-8b7b-e2ca5b81bea8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265548801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.265548801
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1731935728
Short name T1119
Test name
Test status
Simulation time 34906504 ps
CPU time 1.04 seconds
Started Aug 04 04:32:56 PM PDT 24
Finished Aug 04 04:32:57 PM PDT 24
Peak memory 206704 kb
Host smart-253c6ec7-74bd-4760-a371-2ed9d1667d90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731935728 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1731935728
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3126412422
Short name T1122
Test name
Test status
Simulation time 11373571 ps
CPU time 0.85 seconds
Started Aug 04 04:32:34 PM PDT 24
Finished Aug 04 04:32:35 PM PDT 24
Peak memory 206416 kb
Host smart-171fcdb1-6f46-4538-b61a-993454cd1bed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126412422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3126412422
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2773264386
Short name T1034
Test name
Test status
Simulation time 15867157 ps
CPU time 0.91 seconds
Started Aug 04 04:32:35 PM PDT 24
Finished Aug 04 04:32:36 PM PDT 24
Peak memory 206464 kb
Host smart-76051c88-ab89-4741-91e0-2d5d93c4f400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773264386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2773264386
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2425687561
Short name T1070
Test name
Test status
Simulation time 51243226 ps
CPU time 0.99 seconds
Started Aug 04 04:32:33 PM PDT 24
Finished Aug 04 04:32:35 PM PDT 24
Peak memory 206656 kb
Host smart-5fd04f6c-5f32-4f9b-9e60-d440f95875b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425687561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2425687561
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2899034084
Short name T1098
Test name
Test status
Simulation time 163430082 ps
CPU time 2.94 seconds
Started Aug 04 04:32:26 PM PDT 24
Finished Aug 04 04:32:29 PM PDT 24
Peak memory 214924 kb
Host smart-3364691b-282f-4643-a1b4-8c4ae723f655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899034084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2899034084
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4103078848
Short name T1094
Test name
Test status
Simulation time 58347247 ps
CPU time 1.07 seconds
Started Aug 04 04:32:41 PM PDT 24
Finished Aug 04 04:32:42 PM PDT 24
Peak memory 223048 kb
Host smart-6edeeb39-ed13-486d-b7dc-90b9f9af2558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103078848 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.4103078848
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3048678600
Short name T251
Test name
Test status
Simulation time 16639557 ps
CPU time 0.97 seconds
Started Aug 04 04:32:45 PM PDT 24
Finished Aug 04 04:32:46 PM PDT 24
Peak memory 206444 kb
Host smart-edfbfcb6-00c9-49a2-8d9f-83bb7a0d0aab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048678600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3048678600
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3866805103
Short name T1052
Test name
Test status
Simulation time 14441078 ps
CPU time 0.91 seconds
Started Aug 04 04:32:34 PM PDT 24
Finished Aug 04 04:32:35 PM PDT 24
Peak memory 206480 kb
Host smart-8b3fc324-dbdc-43cd-b076-78f4a00b4c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866805103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3866805103
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.750779603
Short name T266
Test name
Test status
Simulation time 39244950 ps
CPU time 1.11 seconds
Started Aug 04 04:32:56 PM PDT 24
Finished Aug 04 04:32:57 PM PDT 24
Peak memory 206612 kb
Host smart-2c191cba-f9c5-4407-8b80-2fcb1e3c6365
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750779603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.750779603
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1715468564
Short name T1019
Test name
Test status
Simulation time 152508031 ps
CPU time 2.83 seconds
Started Aug 04 04:32:42 PM PDT 24
Finished Aug 04 04:32:45 PM PDT 24
Peak memory 214940 kb
Host smart-687ef011-22dd-4a02-8329-d879a4bc219c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715468564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1715468564
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.55106489
Short name T287
Test name
Test status
Simulation time 40897282 ps
CPU time 1.56 seconds
Started Aug 04 04:32:51 PM PDT 24
Finished Aug 04 04:32:53 PM PDT 24
Peak memory 206984 kb
Host smart-9d5ac2a0-0ef9-495e-96ce-9285c78de85f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55106489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.55106489
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.799673227
Short name T1005
Test name
Test status
Simulation time 82631201 ps
CPU time 1.24 seconds
Started Aug 04 04:32:37 PM PDT 24
Finished Aug 04 04:32:38 PM PDT 24
Peak memory 216880 kb
Host smart-50c7d644-8564-4137-920d-1d49915a478c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799673227 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.799673227
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2602841508
Short name T254
Test name
Test status
Simulation time 13229794 ps
CPU time 0.88 seconds
Started Aug 04 04:32:24 PM PDT 24
Finished Aug 04 04:32:25 PM PDT 24
Peak memory 206452 kb
Host smart-98f1a3bb-62fc-44dd-9e4c-9e77bb0f952c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602841508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2602841508
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.29853981
Short name T1091
Test name
Test status
Simulation time 22542234 ps
CPU time 0.75 seconds
Started Aug 04 04:32:51 PM PDT 24
Finished Aug 04 04:32:52 PM PDT 24
Peak memory 206320 kb
Host smart-bf17f9de-35cb-4af5-9569-4538cdbf5bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29853981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.29853981
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4041842886
Short name T1038
Test name
Test status
Simulation time 202362015 ps
CPU time 1.06 seconds
Started Aug 04 04:32:36 PM PDT 24
Finished Aug 04 04:32:37 PM PDT 24
Peak memory 206684 kb
Host smart-3a517121-a686-4bf4-91a2-210552837cbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041842886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.4041842886
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.963516965
Short name T1036
Test name
Test status
Simulation time 80040352 ps
CPU time 2.94 seconds
Started Aug 04 04:32:48 PM PDT 24
Finished Aug 04 04:32:51 PM PDT 24
Peak memory 215228 kb
Host smart-d272ddcf-35cc-4022-af60-5910b9ce8b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963516965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.963516965
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2032254982
Short name T1083
Test name
Test status
Simulation time 52193084 ps
CPU time 1.68 seconds
Started Aug 04 04:32:47 PM PDT 24
Finished Aug 04 04:32:49 PM PDT 24
Peak memory 206776 kb
Host smart-5b49b30e-ce11-449b-9016-d63234ab42cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032254982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2032254982
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2455138526
Short name T1105
Test name
Test status
Simulation time 42204612 ps
CPU time 0.93 seconds
Started Aug 04 04:32:42 PM PDT 24
Finished Aug 04 04:32:43 PM PDT 24
Peak memory 206672 kb
Host smart-78beec71-6d5e-4bc8-b9f3-8ffc765021bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455138526 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2455138526
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3264562963
Short name T1054
Test name
Test status
Simulation time 46421890 ps
CPU time 0.88 seconds
Started Aug 04 04:32:38 PM PDT 24
Finished Aug 04 04:32:39 PM PDT 24
Peak memory 206492 kb
Host smart-7f1577bd-96ff-49a3-a862-1c1d172a8145
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264562963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3264562963
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2343102565
Short name T1020
Test name
Test status
Simulation time 15840341 ps
CPU time 0.94 seconds
Started Aug 04 04:33:01 PM PDT 24
Finished Aug 04 04:33:02 PM PDT 24
Peak memory 206784 kb
Host smart-1facb961-d2cf-4820-905b-9320ff63091a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343102565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2343102565
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1709239635
Short name T1120
Test name
Test status
Simulation time 20692177 ps
CPU time 1.05 seconds
Started Aug 04 04:32:54 PM PDT 24
Finished Aug 04 04:32:55 PM PDT 24
Peak memory 206676 kb
Host smart-c222b48f-db76-44a0-b0b6-8c36bea6cd65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709239635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1709239635
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1896031931
Short name T1048
Test name
Test status
Simulation time 91026278 ps
CPU time 2.05 seconds
Started Aug 04 04:33:02 PM PDT 24
Finished Aug 04 04:33:04 PM PDT 24
Peak memory 214808 kb
Host smart-55f178be-7f82-45c5-a5a7-01d2d18d901f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896031931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1896031931
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1736112568
Short name T283
Test name
Test status
Simulation time 255736943 ps
CPU time 2.17 seconds
Started Aug 04 04:32:53 PM PDT 24
Finished Aug 04 04:32:55 PM PDT 24
Peak memory 206676 kb
Host smart-7bfd5492-9e7f-4690-a18e-fdaac8834b8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736112568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1736112568
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3376266779
Short name T1061
Test name
Test status
Simulation time 44502514 ps
CPU time 1.2 seconds
Started Aug 04 04:32:40 PM PDT 24
Finished Aug 04 04:32:41 PM PDT 24
Peak memory 214884 kb
Host smart-c9a78688-6609-4da2-812e-eb3b1a8a6884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376266779 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3376266779
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1206707421
Short name T269
Test name
Test status
Simulation time 36977169 ps
CPU time 0.74 seconds
Started Aug 04 04:32:55 PM PDT 24
Finished Aug 04 04:32:55 PM PDT 24
Peak memory 206260 kb
Host smart-0b911809-92ae-4254-b01a-72690c3e657d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206707421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1206707421
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.333193536
Short name T1014
Test name
Test status
Simulation time 49327122 ps
CPU time 0.8 seconds
Started Aug 04 04:32:42 PM PDT 24
Finished Aug 04 04:32:43 PM PDT 24
Peak memory 206444 kb
Host smart-f385139d-5a53-4b24-b33d-0746fe67dd31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333193536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.333193536
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2429671637
Short name T1073
Test name
Test status
Simulation time 23706803 ps
CPU time 1.11 seconds
Started Aug 04 04:32:35 PM PDT 24
Finished Aug 04 04:32:36 PM PDT 24
Peak memory 206532 kb
Host smart-c6c6dcd6-2725-4950-a243-e814c4665a0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429671637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2429671637
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3474661020
Short name T1117
Test name
Test status
Simulation time 346992716 ps
CPU time 4.66 seconds
Started Aug 04 04:32:34 PM PDT 24
Finished Aug 04 04:32:39 PM PDT 24
Peak memory 214788 kb
Host smart-34b61a83-6d1b-4521-bd43-10edd62ec46a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474661020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3474661020
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.856405104
Short name T1049
Test name
Test status
Simulation time 293271082 ps
CPU time 2.25 seconds
Started Aug 04 04:32:30 PM PDT 24
Finished Aug 04 04:32:33 PM PDT 24
Peak memory 206604 kb
Host smart-76c1e899-9b5c-40fe-a3e4-a497b4673fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856405104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.856405104
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3871358465
Short name T1043
Test name
Test status
Simulation time 109225809 ps
CPU time 1.31 seconds
Started Aug 04 04:32:52 PM PDT 24
Finished Aug 04 04:32:53 PM PDT 24
Peak memory 214988 kb
Host smart-1e833422-f979-4d7e-a287-fb51955ec7b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871358465 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3871358465
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1339770492
Short name T1051
Test name
Test status
Simulation time 22455119 ps
CPU time 0.87 seconds
Started Aug 04 04:32:55 PM PDT 24
Finished Aug 04 04:32:56 PM PDT 24
Peak memory 206500 kb
Host smart-65e757b8-e594-459c-af03-233b000cb4f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339770492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1339770492
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3594643520
Short name T1023
Test name
Test status
Simulation time 36730913 ps
CPU time 0.82 seconds
Started Aug 04 04:33:00 PM PDT 24
Finished Aug 04 04:33:00 PM PDT 24
Peak memory 206492 kb
Host smart-9b0e5a7a-df95-4fac-9032-a84e5492763c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594643520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3594643520
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2315174024
Short name T1086
Test name
Test status
Simulation time 19627021 ps
CPU time 0.98 seconds
Started Aug 04 04:32:39 PM PDT 24
Finished Aug 04 04:32:40 PM PDT 24
Peak memory 206588 kb
Host smart-9802756e-ef5b-401c-97d6-a8f0bdc563f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315174024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2315174024
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2457309986
Short name T1039
Test name
Test status
Simulation time 157108529 ps
CPU time 1.84 seconds
Started Aug 04 04:32:57 PM PDT 24
Finished Aug 04 04:32:59 PM PDT 24
Peak memory 215248 kb
Host smart-4aa71041-7161-41bc-a3db-00c442f28360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457309986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2457309986
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1341609664
Short name T1093
Test name
Test status
Simulation time 86054038 ps
CPU time 1.55 seconds
Started Aug 04 04:32:50 PM PDT 24
Finished Aug 04 04:32:52 PM PDT 24
Peak memory 214900 kb
Host smart-247de4da-e353-464c-9b48-4b70af04d98f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341609664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1341609664
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3731038998
Short name T1065
Test name
Test status
Simulation time 188574485 ps
CPU time 1.03 seconds
Started Aug 04 04:32:41 PM PDT 24
Finished Aug 04 04:32:42 PM PDT 24
Peak memory 214984 kb
Host smart-9f87f4a2-9adb-4805-a25c-cf3fab686816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731038998 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3731038998
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2401410868
Short name T1071
Test name
Test status
Simulation time 86568771 ps
CPU time 0.83 seconds
Started Aug 04 04:32:56 PM PDT 24
Finished Aug 04 04:32:57 PM PDT 24
Peak memory 206260 kb
Host smart-07dfd009-fd4b-48ea-a97c-336b123be22a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401410868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2401410868
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1317328800
Short name T1089
Test name
Test status
Simulation time 35197043 ps
CPU time 0.85 seconds
Started Aug 04 04:32:53 PM PDT 24
Finished Aug 04 04:32:54 PM PDT 24
Peak memory 206460 kb
Host smart-b0e052e6-063f-4b9b-b96c-e8aa3e02d84d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317328800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1317328800
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3440886575
Short name T249
Test name
Test status
Simulation time 13047503 ps
CPU time 0.93 seconds
Started Aug 04 04:32:42 PM PDT 24
Finished Aug 04 04:32:43 PM PDT 24
Peak memory 206608 kb
Host smart-2323c513-c15f-4b19-b6ab-76d7375beb85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440886575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3440886575
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.70467726
Short name T997
Test name
Test status
Simulation time 145781079 ps
CPU time 2.03 seconds
Started Aug 04 04:32:53 PM PDT 24
Finished Aug 04 04:32:55 PM PDT 24
Peak memory 214892 kb
Host smart-01ee722c-489f-4246-b6ad-b9eb8014e415
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70467726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.70467726
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2797190944
Short name T1062
Test name
Test status
Simulation time 189685780 ps
CPU time 2.5 seconds
Started Aug 04 04:32:58 PM PDT 24
Finished Aug 04 04:33:00 PM PDT 24
Peak memory 206636 kb
Host smart-6e629427-267d-4f22-8b04-aeb97809fa67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797190944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2797190944
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.38267206
Short name T1041
Test name
Test status
Simulation time 27091961 ps
CPU time 1.8 seconds
Started Aug 04 04:32:26 PM PDT 24
Finished Aug 04 04:32:28 PM PDT 24
Peak memory 214964 kb
Host smart-dd85cad0-c328-4cdc-9113-5d8d35f375aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38267206 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.38267206
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1779847412
Short name T1063
Test name
Test status
Simulation time 14498259 ps
CPU time 0.87 seconds
Started Aug 04 04:32:56 PM PDT 24
Finished Aug 04 04:32:57 PM PDT 24
Peak memory 206472 kb
Host smart-15c135fa-37f0-43b5-8ecd-1e95e6aa0a45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779847412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1779847412
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2589478010
Short name T1025
Test name
Test status
Simulation time 11339398 ps
CPU time 0.84 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:09 PM PDT 24
Peak memory 206476 kb
Host smart-08f1eea3-4169-4aae-86a4-c3abf94b358e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589478010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2589478010
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1528003531
Short name T1067
Test name
Test status
Simulation time 100084170 ps
CPU time 1.32 seconds
Started Aug 04 04:32:39 PM PDT 24
Finished Aug 04 04:32:40 PM PDT 24
Peak memory 206560 kb
Host smart-072017a9-1eb3-4f60-91b8-f4a3fe32c9a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528003531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1528003531
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1692605905
Short name T1032
Test name
Test status
Simulation time 38295377 ps
CPU time 2.37 seconds
Started Aug 04 04:33:04 PM PDT 24
Finished Aug 04 04:33:06 PM PDT 24
Peak memory 214932 kb
Host smart-09052b81-1181-48eb-90c3-02978a18f763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692605905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1692605905
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1587214228
Short name T1080
Test name
Test status
Simulation time 69907456 ps
CPU time 2.09 seconds
Started Aug 04 04:32:55 PM PDT 24
Finished Aug 04 04:32:57 PM PDT 24
Peak memory 206608 kb
Host smart-e0f473f4-8282-4a59-a2b5-fe2f9f924554
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587214228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1587214228
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1570151457
Short name T1072
Test name
Test status
Simulation time 105650103 ps
CPU time 1.08 seconds
Started Aug 04 04:32:59 PM PDT 24
Finished Aug 04 04:33:00 PM PDT 24
Peak memory 214896 kb
Host smart-5e7ddf15-9c85-4702-9db1-54c59d46c227
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570151457 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1570151457
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.848594892
Short name T1104
Test name
Test status
Simulation time 60410361 ps
CPU time 0.79 seconds
Started Aug 04 04:32:51 PM PDT 24
Finished Aug 04 04:32:52 PM PDT 24
Peak memory 206280 kb
Host smart-7ef1456b-d78d-493f-a86e-8ceaac5bc34b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848594892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.848594892
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2863886509
Short name T1022
Test name
Test status
Simulation time 30035697 ps
CPU time 0.83 seconds
Started Aug 04 04:32:45 PM PDT 24
Finished Aug 04 04:32:46 PM PDT 24
Peak memory 206496 kb
Host smart-fe481285-b961-419e-8609-a0c75ac864c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863886509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2863886509
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2220191886
Short name T1057
Test name
Test status
Simulation time 42849045 ps
CPU time 1.41 seconds
Started Aug 04 04:32:48 PM PDT 24
Finished Aug 04 04:32:49 PM PDT 24
Peak memory 206768 kb
Host smart-b74c0d75-5e6d-41d4-931a-2e644573b1a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220191886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2220191886
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2000696199
Short name T998
Test name
Test status
Simulation time 1079533411 ps
CPU time 2.44 seconds
Started Aug 04 04:32:46 PM PDT 24
Finished Aug 04 04:32:49 PM PDT 24
Peak memory 218724 kb
Host smart-9d9cb850-ec8a-427d-88af-1ca307b572cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000696199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2000696199
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2237875215
Short name T220
Test name
Test status
Simulation time 49730809 ps
CPU time 1.72 seconds
Started Aug 04 04:32:56 PM PDT 24
Finished Aug 04 04:32:58 PM PDT 24
Peak memory 206676 kb
Host smart-68beeaa0-b7d6-44af-8864-104690a28eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237875215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2237875215
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2702829591
Short name T1112
Test name
Test status
Simulation time 33841004 ps
CPU time 1.62 seconds
Started Aug 04 04:32:56 PM PDT 24
Finished Aug 04 04:32:58 PM PDT 24
Peak memory 214844 kb
Host smart-8ab216fc-ad17-4fb3-8d51-11c6e7223e8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702829591 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2702829591
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2914191581
Short name T268
Test name
Test status
Simulation time 12702002 ps
CPU time 0.88 seconds
Started Aug 04 04:32:52 PM PDT 24
Finished Aug 04 04:32:53 PM PDT 24
Peak memory 206592 kb
Host smart-0888be16-b8b0-498d-a90e-717fb3450777
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914191581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2914191581
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1113436363
Short name T1107
Test name
Test status
Simulation time 15910056 ps
CPU time 0.97 seconds
Started Aug 04 04:32:37 PM PDT 24
Finished Aug 04 04:32:38 PM PDT 24
Peak memory 206460 kb
Host smart-eb6ad03d-9ad4-4074-9b19-4ad6f79a6ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113436363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1113436363
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.164939587
Short name T270
Test name
Test status
Simulation time 21021884 ps
CPU time 1.07 seconds
Started Aug 04 04:32:57 PM PDT 24
Finished Aug 04 04:32:59 PM PDT 24
Peak memory 206560 kb
Host smart-9ba8873d-5dc6-4355-9250-b0f9094caf02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164939587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.164939587
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.4082924096
Short name T1123
Test name
Test status
Simulation time 944192952 ps
CPU time 4.2 seconds
Started Aug 04 04:32:42 PM PDT 24
Finished Aug 04 04:32:46 PM PDT 24
Peak memory 223036 kb
Host smart-46b84de7-a872-48c8-a2e6-12c9c8d43ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082924096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.4082924096
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1580063533
Short name T289
Test name
Test status
Simulation time 47644486 ps
CPU time 1.56 seconds
Started Aug 04 04:32:55 PM PDT 24
Finished Aug 04 04:32:57 PM PDT 24
Peak memory 214880 kb
Host smart-f7bd83fb-5379-4545-a05a-bf2fbd9e5779
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580063533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1580063533
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.529914483
Short name T263
Test name
Test status
Simulation time 23510581 ps
CPU time 1.18 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 206484 kb
Host smart-0180cec1-7197-4880-acfd-a5dfe15328da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529914483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.529914483
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2813486714
Short name T1095
Test name
Test status
Simulation time 996728789 ps
CPU time 5.94 seconds
Started Aug 04 04:32:23 PM PDT 24
Finished Aug 04 04:32:29 PM PDT 24
Peak memory 206436 kb
Host smart-686502d0-1ed5-4fea-be0d-9d1c95971733
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813486714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2813486714
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1204543795
Short name T256
Test name
Test status
Simulation time 218290220 ps
CPU time 0.9 seconds
Started Aug 04 04:32:41 PM PDT 24
Finished Aug 04 04:32:42 PM PDT 24
Peak memory 206492 kb
Host smart-49b8d78a-fa9c-46d0-9695-809ced90327d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204543795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1204543795
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.41315057
Short name T1029
Test name
Test status
Simulation time 78464803 ps
CPU time 0.99 seconds
Started Aug 04 04:33:01 PM PDT 24
Finished Aug 04 04:33:02 PM PDT 24
Peak memory 215016 kb
Host smart-51295e5a-0261-4cb6-8334-304863faa4d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41315057 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.41315057
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3419335359
Short name T253
Test name
Test status
Simulation time 24696995 ps
CPU time 0.8 seconds
Started Aug 04 04:32:30 PM PDT 24
Finished Aug 04 04:32:34 PM PDT 24
Peak memory 206228 kb
Host smart-af5e9c18-029c-42c5-bd94-adf034f93d29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419335359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3419335359
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3250902802
Short name T1028
Test name
Test status
Simulation time 30930069 ps
CPU time 0.89 seconds
Started Aug 04 04:32:33 PM PDT 24
Finished Aug 04 04:32:34 PM PDT 24
Peak memory 206400 kb
Host smart-7e4924e5-6dc9-49c8-986d-478465f3d9bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250902802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3250902802
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2681813074
Short name T1047
Test name
Test status
Simulation time 44121281 ps
CPU time 0.91 seconds
Started Aug 04 04:32:55 PM PDT 24
Finished Aug 04 04:32:56 PM PDT 24
Peak memory 206612 kb
Host smart-b1c3a1f1-14f1-43cb-a552-1237d02c6563
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681813074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2681813074
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2025498998
Short name T1113
Test name
Test status
Simulation time 241210141 ps
CPU time 4.14 seconds
Started Aug 04 04:33:02 PM PDT 24
Finished Aug 04 04:33:06 PM PDT 24
Peak memory 214884 kb
Host smart-8032dda9-9fe7-4469-86be-d71a0f08b27d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025498998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2025498998
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1678553886
Short name T288
Test name
Test status
Simulation time 81920580 ps
CPU time 2.26 seconds
Started Aug 04 04:32:38 PM PDT 24
Finished Aug 04 04:32:40 PM PDT 24
Peak memory 214812 kb
Host smart-dfd659d9-09de-4e3f-b02c-cc670822e9f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678553886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1678553886
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3575385552
Short name T1050
Test name
Test status
Simulation time 44858644 ps
CPU time 0.9 seconds
Started Aug 04 04:32:53 PM PDT 24
Finished Aug 04 04:32:54 PM PDT 24
Peak memory 206460 kb
Host smart-185841d9-e86a-4503-8c1a-47a35e0e918d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575385552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3575385552
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2537088206
Short name T1109
Test name
Test status
Simulation time 42709094 ps
CPU time 0.89 seconds
Started Aug 04 04:32:47 PM PDT 24
Finished Aug 04 04:32:48 PM PDT 24
Peak memory 206500 kb
Host smart-5a69de54-4f85-46ae-8e5e-21852bf2ff1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537088206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2537088206
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1724701642
Short name T1001
Test name
Test status
Simulation time 32860108 ps
CPU time 0.78 seconds
Started Aug 04 04:32:50 PM PDT 24
Finished Aug 04 04:32:51 PM PDT 24
Peak memory 206260 kb
Host smart-6a3d2aa7-ee1f-4325-9a0b-ffb4c68eeddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724701642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1724701642
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2106440533
Short name T1018
Test name
Test status
Simulation time 32222382 ps
CPU time 0.86 seconds
Started Aug 04 04:32:58 PM PDT 24
Finished Aug 04 04:32:59 PM PDT 24
Peak memory 206412 kb
Host smart-0bdf52d0-498e-4916-af93-cef5a8ab6c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106440533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2106440533
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3389895268
Short name T1082
Test name
Test status
Simulation time 14634150 ps
CPU time 0.88 seconds
Started Aug 04 04:33:03 PM PDT 24
Finished Aug 04 04:33:04 PM PDT 24
Peak memory 206436 kb
Host smart-396b080e-0423-4db7-97df-9e1b01fbdb8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389895268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3389895268
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.559915110
Short name T1088
Test name
Test status
Simulation time 45367348 ps
CPU time 0.81 seconds
Started Aug 04 04:32:44 PM PDT 24
Finished Aug 04 04:32:45 PM PDT 24
Peak memory 206428 kb
Host smart-a264f6a5-7286-4499-ad33-8e19f825ddd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559915110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.559915110
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1627828616
Short name T1000
Test name
Test status
Simulation time 11635957 ps
CPU time 0.79 seconds
Started Aug 04 04:33:10 PM PDT 24
Finished Aug 04 04:33:11 PM PDT 24
Peak memory 206508 kb
Host smart-39843c70-af2d-4ef5-954f-65d32fc8ef5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627828616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1627828616
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2297399650
Short name T1042
Test name
Test status
Simulation time 20473916 ps
CPU time 0.86 seconds
Started Aug 04 04:32:42 PM PDT 24
Finished Aug 04 04:32:43 PM PDT 24
Peak memory 206556 kb
Host smart-3a7041ea-3daf-4d2f-aa44-cda629b89b8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297399650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2297399650
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3390266319
Short name T1068
Test name
Test status
Simulation time 13969744 ps
CPU time 0.89 seconds
Started Aug 04 04:33:03 PM PDT 24
Finished Aug 04 04:33:04 PM PDT 24
Peak memory 206492 kb
Host smart-c2bf4eb4-e69e-4be9-b291-927f64f9af74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390266319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3390266319
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.98443735
Short name T1016
Test name
Test status
Simulation time 13254216 ps
CPU time 0.83 seconds
Started Aug 04 04:33:01 PM PDT 24
Finished Aug 04 04:33:02 PM PDT 24
Peak memory 206548 kb
Host smart-d88a652a-74ba-47d9-b558-d35ee55263b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98443735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.98443735
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2182103737
Short name T252
Test name
Test status
Simulation time 24122063 ps
CPU time 1.22 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:27 PM PDT 24
Peak memory 206408 kb
Host smart-e8afcb4a-4736-438d-9263-eee6194f8ff6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182103737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2182103737
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1793001651
Short name T260
Test name
Test status
Simulation time 34987061 ps
CPU time 1.89 seconds
Started Aug 04 04:33:52 PM PDT 24
Finished Aug 04 04:33:54 PM PDT 24
Peak memory 206432 kb
Host smart-9e688779-7bd8-46ea-8435-335fd9c6955a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793001651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1793001651
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3617475881
Short name T259
Test name
Test status
Simulation time 87970116 ps
CPU time 0.87 seconds
Started Aug 04 04:32:40 PM PDT 24
Finished Aug 04 04:32:41 PM PDT 24
Peak memory 206552 kb
Host smart-7ce4bd15-86c2-4f4f-af75-fcfb35c717fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617475881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3617475881
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2770739646
Short name T1035
Test name
Test status
Simulation time 24384713 ps
CPU time 1.41 seconds
Started Aug 04 04:32:45 PM PDT 24
Finished Aug 04 04:32:47 PM PDT 24
Peak memory 215072 kb
Host smart-ada98fcb-3a6b-424d-bfae-bbcd5b67fc09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770739646 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2770739646
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1770184521
Short name T261
Test name
Test status
Simulation time 29772468 ps
CPU time 0.82 seconds
Started Aug 04 04:32:35 PM PDT 24
Finished Aug 04 04:32:36 PM PDT 24
Peak memory 206408 kb
Host smart-99435e39-1b21-4721-8f6d-ab94683c4ef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770184521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1770184521
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3740204121
Short name T1030
Test name
Test status
Simulation time 15001599 ps
CPU time 0.89 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 206480 kb
Host smart-615e2ef6-895f-4fcb-b3a5-92d8f176a325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740204121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3740204121
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3733384113
Short name T1031
Test name
Test status
Simulation time 60684295 ps
CPU time 1.09 seconds
Started Aug 04 04:32:31 PM PDT 24
Finished Aug 04 04:32:33 PM PDT 24
Peak memory 206600 kb
Host smart-20f51dff-35b3-4688-9594-484a6e2f22b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733384113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3733384113
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3513670832
Short name T1009
Test name
Test status
Simulation time 128682593 ps
CPU time 4 seconds
Started Aug 04 04:32:22 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 214888 kb
Host smart-33987002-4784-41a7-81b4-060474187281
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513670832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3513670832
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.416883200
Short name T1075
Test name
Test status
Simulation time 348737010 ps
CPU time 2.46 seconds
Started Aug 04 04:32:41 PM PDT 24
Finished Aug 04 04:32:44 PM PDT 24
Peak memory 206972 kb
Host smart-3f716a33-738f-45cb-93fd-373fb63e13f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416883200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.416883200
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.826210250
Short name T1087
Test name
Test status
Simulation time 15382170 ps
CPU time 0.91 seconds
Started Aug 04 04:32:52 PM PDT 24
Finished Aug 04 04:32:53 PM PDT 24
Peak memory 206596 kb
Host smart-d41d42b6-a66a-4c7d-b863-4bf78e6669c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826210250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.826210250
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1406086033
Short name T1079
Test name
Test status
Simulation time 42134001 ps
CPU time 0.88 seconds
Started Aug 04 04:32:43 PM PDT 24
Finished Aug 04 04:32:44 PM PDT 24
Peak memory 206456 kb
Host smart-e3672461-6046-4552-90ae-1c881fef0024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406086033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1406086033
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1988434422
Short name T1003
Test name
Test status
Simulation time 18518428 ps
CPU time 0.89 seconds
Started Aug 04 04:32:58 PM PDT 24
Finished Aug 04 04:32:59 PM PDT 24
Peak memory 206400 kb
Host smart-b3849011-17f2-4d5b-b97a-f516fb5c7cff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988434422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1988434422
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1760048234
Short name T1125
Test name
Test status
Simulation time 13843372 ps
CPU time 0.87 seconds
Started Aug 04 04:32:45 PM PDT 24
Finished Aug 04 04:32:46 PM PDT 24
Peak memory 206504 kb
Host smart-64cdce82-b437-4793-88e3-ccc1f76e1b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760048234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1760048234
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.4054575454
Short name T1011
Test name
Test status
Simulation time 11667211 ps
CPU time 0.85 seconds
Started Aug 04 04:32:53 PM PDT 24
Finished Aug 04 04:32:54 PM PDT 24
Peak memory 206436 kb
Host smart-e31c79ef-7933-4f17-bda5-1b2e0633f4f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054575454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.4054575454
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.633759218
Short name T1056
Test name
Test status
Simulation time 22465728 ps
CPU time 0.83 seconds
Started Aug 04 04:32:45 PM PDT 24
Finished Aug 04 04:32:46 PM PDT 24
Peak memory 206472 kb
Host smart-db1e3ad3-7c46-4791-a337-03a5202ac8fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633759218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.633759218
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3888329017
Short name T1118
Test name
Test status
Simulation time 19793617 ps
CPU time 0.79 seconds
Started Aug 04 04:33:04 PM PDT 24
Finished Aug 04 04:33:05 PM PDT 24
Peak memory 206356 kb
Host smart-f25013d8-c8f5-4c3b-b81d-c0fdaed457f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888329017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3888329017
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3209213103
Short name T1064
Test name
Test status
Simulation time 17962324 ps
CPU time 0.84 seconds
Started Aug 04 04:32:59 PM PDT 24
Finished Aug 04 04:33:00 PM PDT 24
Peak memory 206612 kb
Host smart-5d64a5cc-833d-413f-a3b1-20d28e03a683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209213103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3209213103
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1720903444
Short name T1010
Test name
Test status
Simulation time 17659877 ps
CPU time 0.96 seconds
Started Aug 04 04:32:47 PM PDT 24
Finished Aug 04 04:32:48 PM PDT 24
Peak memory 206464 kb
Host smart-8e3819cd-5d40-4464-af57-f9847d40e04d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720903444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1720903444
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3130262036
Short name T1027
Test name
Test status
Simulation time 12369918 ps
CPU time 0.86 seconds
Started Aug 04 04:32:53 PM PDT 24
Finished Aug 04 04:32:54 PM PDT 24
Peak memory 206484 kb
Host smart-4596c09c-fe85-4f4c-9986-b0be83701850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130262036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3130262036
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3958374411
Short name T262
Test name
Test status
Simulation time 43260596 ps
CPU time 1.16 seconds
Started Aug 04 04:32:46 PM PDT 24
Finished Aug 04 04:32:48 PM PDT 24
Peak memory 206560 kb
Host smart-c3003de8-5095-4c0d-9a29-867680fee992
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958374411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3958374411
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.657896619
Short name T1017
Test name
Test status
Simulation time 366475195 ps
CPU time 2.86 seconds
Started Aug 04 04:33:59 PM PDT 24
Finished Aug 04 04:34:02 PM PDT 24
Peak memory 206440 kb
Host smart-bf450074-78c0-422a-8cc3-41c2580e351f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657896619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.657896619
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2562368242
Short name T250
Test name
Test status
Simulation time 21020623 ps
CPU time 0.99 seconds
Started Aug 04 04:32:40 PM PDT 24
Finished Aug 04 04:32:41 PM PDT 24
Peak memory 206544 kb
Host smart-5e9ed1c6-c084-406d-b047-b506f76159d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562368242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2562368242
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3435735538
Short name T1015
Test name
Test status
Simulation time 16261616 ps
CPU time 1.08 seconds
Started Aug 04 04:33:48 PM PDT 24
Finished Aug 04 04:33:49 PM PDT 24
Peak memory 214888 kb
Host smart-266b4f66-2ebe-453c-817e-8d2fae2e5399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435735538 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3435735538
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1957460885
Short name T1055
Test name
Test status
Simulation time 17510609 ps
CPU time 0.91 seconds
Started Aug 04 04:32:34 PM PDT 24
Finished Aug 04 04:32:35 PM PDT 24
Peak memory 206464 kb
Host smart-fd4b77ea-98f8-4878-b88c-0b0a6cf975eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957460885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1957460885
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3469587365
Short name T1026
Test name
Test status
Simulation time 104914720 ps
CPU time 0.88 seconds
Started Aug 04 04:32:28 PM PDT 24
Finished Aug 04 04:32:29 PM PDT 24
Peak memory 206568 kb
Host smart-bad31caf-f981-49f5-853f-12185552a5b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469587365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3469587365
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.274560553
Short name T1059
Test name
Test status
Simulation time 33056662 ps
CPU time 1.01 seconds
Started Aug 04 04:32:58 PM PDT 24
Finished Aug 04 04:33:00 PM PDT 24
Peak memory 206524 kb
Host smart-fb896bb3-e017-4b8c-909c-a0ed0433abbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274560553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.274560553
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1111134240
Short name T1008
Test name
Test status
Simulation time 29418882 ps
CPU time 2.01 seconds
Started Aug 04 04:32:59 PM PDT 24
Finished Aug 04 04:33:01 PM PDT 24
Peak memory 214912 kb
Host smart-7309a1d7-ecb4-453a-859b-19709ef4b1e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111134240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1111134240
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1738992945
Short name T1053
Test name
Test status
Simulation time 77536794 ps
CPU time 2.01 seconds
Started Aug 04 04:32:40 PM PDT 24
Finished Aug 04 04:32:42 PM PDT 24
Peak memory 206608 kb
Host smart-d45b3018-b63d-4871-9cb1-f657b0e39ca2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738992945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1738992945
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.4147784471
Short name T1060
Test name
Test status
Simulation time 13955542 ps
CPU time 0.87 seconds
Started Aug 04 04:33:04 PM PDT 24
Finished Aug 04 04:33:05 PM PDT 24
Peak memory 206504 kb
Host smart-dddb5cf7-aad7-4d22-9dbc-be29323ba7c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147784471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.4147784471
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.353339059
Short name T1092
Test name
Test status
Simulation time 66921982 ps
CPU time 0.83 seconds
Started Aug 04 04:33:06 PM PDT 24
Finished Aug 04 04:33:07 PM PDT 24
Peak memory 206432 kb
Host smart-2b831751-a7ba-42a8-8e1c-39bff6734ab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353339059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.353339059
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2357883215
Short name T1013
Test name
Test status
Simulation time 11960835 ps
CPU time 0.9 seconds
Started Aug 04 04:32:46 PM PDT 24
Finished Aug 04 04:32:47 PM PDT 24
Peak memory 206492 kb
Host smart-df6dbb98-1105-463e-afde-fb470e607cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357883215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2357883215
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3227594378
Short name T1076
Test name
Test status
Simulation time 25528490 ps
CPU time 0.82 seconds
Started Aug 04 04:32:41 PM PDT 24
Finished Aug 04 04:32:41 PM PDT 24
Peak memory 206476 kb
Host smart-c3ec57d8-deb1-41e5-8f0e-394e26edbc90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227594378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3227594378
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2695250709
Short name T1115
Test name
Test status
Simulation time 38821046 ps
CPU time 0.81 seconds
Started Aug 04 04:32:58 PM PDT 24
Finished Aug 04 04:32:59 PM PDT 24
Peak memory 206208 kb
Host smart-acc25b0f-98f2-4baf-9770-894d0ae7b314
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695250709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2695250709
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2545519212
Short name T1066
Test name
Test status
Simulation time 14095607 ps
CPU time 0.95 seconds
Started Aug 04 04:33:02 PM PDT 24
Finished Aug 04 04:33:03 PM PDT 24
Peak memory 206588 kb
Host smart-b1ba9a72-5ea0-43f8-9b88-c3c87dd388e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545519212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2545519212
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1866782592
Short name T1100
Test name
Test status
Simulation time 13765225 ps
CPU time 0.89 seconds
Started Aug 04 04:32:59 PM PDT 24
Finished Aug 04 04:33:00 PM PDT 24
Peak memory 206604 kb
Host smart-0d12cce5-1bf7-4a18-97c4-383e43d32e47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866782592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1866782592
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2445280301
Short name T1116
Test name
Test status
Simulation time 26776367 ps
CPU time 0.9 seconds
Started Aug 04 04:32:48 PM PDT 24
Finished Aug 04 04:32:49 PM PDT 24
Peak memory 206464 kb
Host smart-6d42c982-1066-4c20-8f84-d641d376cbcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445280301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2445280301
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2223635170
Short name T1069
Test name
Test status
Simulation time 38603974 ps
CPU time 0.87 seconds
Started Aug 04 04:32:55 PM PDT 24
Finished Aug 04 04:32:56 PM PDT 24
Peak memory 206464 kb
Host smart-71e36de0-a3b1-4884-a850-4f1c81cc27ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223635170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2223635170
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.322985713
Short name T1099
Test name
Test status
Simulation time 32460826 ps
CPU time 0.79 seconds
Started Aug 04 04:32:50 PM PDT 24
Finished Aug 04 04:32:51 PM PDT 24
Peak memory 206300 kb
Host smart-950107f9-6cd0-4b53-aba4-83c82ce31a26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322985713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.322985713
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.688923179
Short name T1124
Test name
Test status
Simulation time 21936855 ps
CPU time 1.52 seconds
Started Aug 04 04:32:32 PM PDT 24
Finished Aug 04 04:32:34 PM PDT 24
Peak memory 214796 kb
Host smart-ea12b53a-bcd2-4c68-99fd-8d57ae172cd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688923179 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.688923179
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.551455170
Short name T1077
Test name
Test status
Simulation time 19138872 ps
CPU time 0.86 seconds
Started Aug 04 04:32:35 PM PDT 24
Finished Aug 04 04:32:36 PM PDT 24
Peak memory 206448 kb
Host smart-3a049b3f-0b18-4e4e-85e6-3f6cf4c7fb80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551455170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.551455170
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.779455379
Short name T1033
Test name
Test status
Simulation time 12966593 ps
CPU time 0.87 seconds
Started Aug 04 04:32:22 PM PDT 24
Finished Aug 04 04:32:23 PM PDT 24
Peak memory 206476 kb
Host smart-88a3aa1d-2e73-480f-ba75-158c7044f7f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779455379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.779455379
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1930588084
Short name T1102
Test name
Test status
Simulation time 91876489 ps
CPU time 0.9 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:19 PM PDT 24
Peak memory 206560 kb
Host smart-0605dd66-fea6-4ee6-acf2-d3e1d0ce5fb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930588084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1930588084
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4063377716
Short name T1006
Test name
Test status
Simulation time 104043441 ps
CPU time 1.83 seconds
Started Aug 04 04:33:38 PM PDT 24
Finished Aug 04 04:33:40 PM PDT 24
Peak memory 214880 kb
Host smart-a7d9e491-6393-419f-983e-c8eb236682e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063377716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4063377716
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2188550851
Short name T1106
Test name
Test status
Simulation time 327405167 ps
CPU time 1.43 seconds
Started Aug 04 04:32:48 PM PDT 24
Finished Aug 04 04:32:49 PM PDT 24
Peak memory 214788 kb
Host smart-cd1332d8-22ef-4266-8aa9-b956ca7d0c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188550851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2188550851
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3306736820
Short name T1090
Test name
Test status
Simulation time 102704168 ps
CPU time 1.18 seconds
Started Aug 04 04:32:55 PM PDT 24
Finished Aug 04 04:32:56 PM PDT 24
Peak memory 214920 kb
Host smart-ad779836-766e-41a7-b6fc-5c9891aaf9cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306736820 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3306736820
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.405647081
Short name T258
Test name
Test status
Simulation time 33709806 ps
CPU time 0.79 seconds
Started Aug 04 04:32:31 PM PDT 24
Finished Aug 04 04:32:32 PM PDT 24
Peak memory 206292 kb
Host smart-550662d4-7f45-4f2d-947f-2fb6656768a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405647081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.405647081
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3368282417
Short name T1074
Test name
Test status
Simulation time 12692193 ps
CPU time 0.84 seconds
Started Aug 04 04:32:41 PM PDT 24
Finished Aug 04 04:32:42 PM PDT 24
Peak memory 206464 kb
Host smart-9e893525-c6c1-4bc5-b6c9-b228a867ccef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368282417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3368282417
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1487449099
Short name T248
Test name
Test status
Simulation time 20726192 ps
CPU time 1.15 seconds
Started Aug 04 04:32:23 PM PDT 24
Finished Aug 04 04:32:24 PM PDT 24
Peak memory 206580 kb
Host smart-6f2fb5a1-fcce-46cd-8487-442833448cab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487449099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1487449099
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1287423534
Short name T1085
Test name
Test status
Simulation time 85519472 ps
CPU time 2.34 seconds
Started Aug 04 04:32:19 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 214920 kb
Host smart-5b07d0bd-fcf6-4d68-be1f-048465624c64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287423534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1287423534
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1275056139
Short name T222
Test name
Test status
Simulation time 177324719 ps
CPU time 1.42 seconds
Started Aug 04 04:32:24 PM PDT 24
Finished Aug 04 04:32:25 PM PDT 24
Peak memory 206560 kb
Host smart-5682df22-23b3-47d3-b86f-a243274de046
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275056139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1275056139
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3932774752
Short name T1058
Test name
Test status
Simulation time 48075786 ps
CPU time 0.99 seconds
Started Aug 04 04:32:59 PM PDT 24
Finished Aug 04 04:33:00 PM PDT 24
Peak memory 214888 kb
Host smart-e562c068-f043-4293-bdfe-c59c0fa5b28d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932774752 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3932774752
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.4264818858
Short name T1004
Test name
Test status
Simulation time 23742027 ps
CPU time 0.86 seconds
Started Aug 04 04:32:27 PM PDT 24
Finished Aug 04 04:32:28 PM PDT 24
Peak memory 206460 kb
Host smart-c72d1bc5-c80d-40ad-b302-02d5bbf4174e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264818858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.4264818858
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1980638674
Short name T1110
Test name
Test status
Simulation time 46255710 ps
CPU time 0.78 seconds
Started Aug 04 04:32:28 PM PDT 24
Finished Aug 04 04:32:29 PM PDT 24
Peak memory 206588 kb
Host smart-249d11de-112a-4167-8632-3c97777a06a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980638674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1980638674
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2098809494
Short name T1121
Test name
Test status
Simulation time 138322740 ps
CPU time 1.38 seconds
Started Aug 04 04:32:55 PM PDT 24
Finished Aug 04 04:32:57 PM PDT 24
Peak memory 206608 kb
Host smart-44e4a269-f446-4cf7-9379-7fac97c6337a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098809494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2098809494
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.956683502
Short name T1012
Test name
Test status
Simulation time 79133601 ps
CPU time 1.71 seconds
Started Aug 04 04:32:45 PM PDT 24
Finished Aug 04 04:32:47 PM PDT 24
Peak memory 214880 kb
Host smart-c5777c69-16c4-4f7c-992b-f498b1d88322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956683502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.956683502
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.921962035
Short name T1111
Test name
Test status
Simulation time 56651745 ps
CPU time 1.71 seconds
Started Aug 04 04:32:26 PM PDT 24
Finished Aug 04 04:32:28 PM PDT 24
Peak memory 214844 kb
Host smart-5e7ecdf0-5bca-43b1-b7dd-218e212fbaaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921962035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.921962035
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3456229495
Short name T1046
Test name
Test status
Simulation time 21288125 ps
CPU time 0.87 seconds
Started Aug 04 04:32:42 PM PDT 24
Finished Aug 04 04:32:43 PM PDT 24
Peak memory 206596 kb
Host smart-4c99c33b-d0b0-441d-be48-4ec18034cf96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456229495 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3456229495
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2064255961
Short name T267
Test name
Test status
Simulation time 23070975 ps
CPU time 0.88 seconds
Started Aug 04 04:32:49 PM PDT 24
Finished Aug 04 04:32:50 PM PDT 24
Peak memory 206488 kb
Host smart-0fc01687-f723-40b7-a302-5bcecd6b92bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064255961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2064255961
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1908676838
Short name T1007
Test name
Test status
Simulation time 30676545 ps
CPU time 0.76 seconds
Started Aug 04 04:32:33 PM PDT 24
Finished Aug 04 04:32:34 PM PDT 24
Peak memory 206308 kb
Host smart-85b26ac8-7d13-412d-9c0c-170367c6eaca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908676838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1908676838
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3306027200
Short name T1045
Test name
Test status
Simulation time 74258636 ps
CPU time 1.05 seconds
Started Aug 04 04:32:54 PM PDT 24
Finished Aug 04 04:32:55 PM PDT 24
Peak memory 206684 kb
Host smart-aac224ca-e84b-48ad-b95a-0a56e73b0549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306027200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3306027200
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.4042462512
Short name T1040
Test name
Test status
Simulation time 532115525 ps
CPU time 2.31 seconds
Started Aug 04 04:32:36 PM PDT 24
Finished Aug 04 04:32:38 PM PDT 24
Peak memory 215040 kb
Host smart-3f23dd92-cc5d-4529-aa41-8dfbf2828cc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042462512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.4042462512
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3680090137
Short name T285
Test name
Test status
Simulation time 99612071 ps
CPU time 1.65 seconds
Started Aug 04 04:32:34 PM PDT 24
Finished Aug 04 04:32:36 PM PDT 24
Peak memory 206624 kb
Host smart-35d3c649-e2fe-43f1-b506-57258dc94d09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680090137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3680090137
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4153665830
Short name T1103
Test name
Test status
Simulation time 46538146 ps
CPU time 1.18 seconds
Started Aug 04 04:32:51 PM PDT 24
Finished Aug 04 04:32:52 PM PDT 24
Peak memory 214880 kb
Host smart-cbb03fee-b294-4725-8228-78bc2991da02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153665830 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4153665830
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2568218194
Short name T247
Test name
Test status
Simulation time 14717632 ps
CPU time 0.94 seconds
Started Aug 04 04:32:50 PM PDT 24
Finished Aug 04 04:32:51 PM PDT 24
Peak memory 206492 kb
Host smart-b3b7a366-6895-404f-91eb-e7a875538a70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568218194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2568218194
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3824074502
Short name T1096
Test name
Test status
Simulation time 11975976 ps
CPU time 0.82 seconds
Started Aug 04 04:32:32 PM PDT 24
Finished Aug 04 04:32:33 PM PDT 24
Peak memory 206476 kb
Host smart-bcde7c9c-01fa-4cb0-98c7-88ef51209343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824074502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3824074502
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2774243694
Short name T271
Test name
Test status
Simulation time 32644775 ps
CPU time 0.96 seconds
Started Aug 04 04:32:24 PM PDT 24
Finished Aug 04 04:32:25 PM PDT 24
Peak memory 206556 kb
Host smart-6fe8264c-8426-4069-981a-99d17142d8ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774243694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2774243694
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1033616100
Short name T996
Test name
Test status
Simulation time 62867912 ps
CPU time 2.42 seconds
Started Aug 04 04:32:49 PM PDT 24
Finished Aug 04 04:32:52 PM PDT 24
Peak memory 214996 kb
Host smart-7c672fbe-fd49-4f59-ada8-f55ac081b6b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033616100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1033616100
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3063008449
Short name T1084
Test name
Test status
Simulation time 106216568 ps
CPU time 2.58 seconds
Started Aug 04 04:32:49 PM PDT 24
Finished Aug 04 04:32:52 PM PDT 24
Peak memory 206676 kb
Host smart-633c92e5-a1e1-4ef4-abdb-e56779d3baf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063008449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3063008449
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1908481029
Short name T172
Test name
Test status
Simulation time 26402128 ps
CPU time 1.12 seconds
Started Aug 04 05:40:43 PM PDT 24
Finished Aug 04 05:40:44 PM PDT 24
Peak memory 218740 kb
Host smart-04d1a44f-337a-493d-93fe-3429a10dbcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908481029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1908481029
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.436896720
Short name T86
Test name
Test status
Simulation time 10906114 ps
CPU time 0.87 seconds
Started Aug 04 05:40:50 PM PDT 24
Finished Aug 04 05:40:52 PM PDT 24
Peak memory 216232 kb
Host smart-b8dab840-74a4-4f2a-9b36-a74c8b31bff5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436896720 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.436896720
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3098168104
Short name T376
Test name
Test status
Simulation time 61629839 ps
CPU time 0.96 seconds
Started Aug 04 05:40:44 PM PDT 24
Finished Aug 04 05:40:45 PM PDT 24
Peak memory 218496 kb
Host smart-ce3c17ce-7f77-4a00-bc05-696797374f97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098168104 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3098168104
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_genbits.411324520
Short name T782
Test name
Test status
Simulation time 39768688 ps
CPU time 1.4 seconds
Started Aug 04 05:40:44 PM PDT 24
Finished Aug 04 05:40:46 PM PDT 24
Peak memory 218528 kb
Host smart-d05bd845-163b-4563-8ac3-d337e7895728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411324520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.411324520
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.3131070493
Short name T824
Test name
Test status
Simulation time 27907978 ps
CPU time 1.14 seconds
Started Aug 04 05:40:44 PM PDT 24
Finished Aug 04 05:40:46 PM PDT 24
Peak memory 207088 kb
Host smart-ee2e23d2-20dc-40b7-b098-7bd508df5d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131070493 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3131070493
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.2737026046
Short name T894
Test name
Test status
Simulation time 21345719 ps
CPU time 0.92 seconds
Started Aug 04 05:40:48 PM PDT 24
Finished Aug 04 05:40:49 PM PDT 24
Peak memory 215236 kb
Host smart-c5956467-d747-4c7b-b20e-23f98fe2f54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737026046 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2737026046
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2517029946
Short name T241
Test name
Test status
Simulation time 157257690 ps
CPU time 3.29 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:40:48 PM PDT 24
Peak memory 217176 kb
Host smart-06292e5f-25c1-47e5-995e-1bc39973695e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517029946 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2517029946
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2587149206
Short name T236
Test name
Test status
Simulation time 7591775200 ps
CPU time 107.32 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:42:32 PM PDT 24
Peak memory 218276 kb
Host smart-9b653c11-6a14-4043-a113-d540c7c5b840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587149206 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2587149206
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.517968883
Short name T246
Test name
Test status
Simulation time 32683672 ps
CPU time 1.33 seconds
Started Aug 04 05:40:54 PM PDT 24
Finished Aug 04 05:40:56 PM PDT 24
Peak memory 215696 kb
Host smart-620e81eb-3fdc-4593-bc09-7beb3f2a1964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517968883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.517968883
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1274387151
Short name T711
Test name
Test status
Simulation time 62347526 ps
CPU time 0.95 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:40:46 PM PDT 24
Peak memory 214888 kb
Host smart-8fd7dfc9-ae68-4167-be48-89deb25457f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274387151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1274387151
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2880628663
Short name T604
Test name
Test status
Simulation time 54123500 ps
CPU time 0.83 seconds
Started Aug 04 05:40:53 PM PDT 24
Finished Aug 04 05:40:54 PM PDT 24
Peak memory 216324 kb
Host smart-1b9daa8d-346f-4851-9c99-7e59c839b790
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880628663 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2880628663
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1691823183
Short name T969
Test name
Test status
Simulation time 77554430 ps
CPU time 1.03 seconds
Started Aug 04 05:40:46 PM PDT 24
Finished Aug 04 05:40:47 PM PDT 24
Peak memory 218376 kb
Host smart-d7398915-cdb7-4375-babf-0a978bd1588f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691823183 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1691823183
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2277606719
Short name T812
Test name
Test status
Simulation time 22891466 ps
CPU time 1.2 seconds
Started Aug 04 05:40:42 PM PDT 24
Finished Aug 04 05:40:43 PM PDT 24
Peak memory 218620 kb
Host smart-5a3d2973-084d-4587-b7aa-53b096c4ae72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277606719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2277606719
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.794412041
Short name T678
Test name
Test status
Simulation time 158111867 ps
CPU time 2.84 seconds
Started Aug 04 05:40:47 PM PDT 24
Finished Aug 04 05:40:50 PM PDT 24
Peak memory 215408 kb
Host smart-3254ee67-ae00-4fbf-86b3-5b27994cfb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794412041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.794412041
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2959951180
Short name T120
Test name
Test status
Simulation time 26713296 ps
CPU time 0.93 seconds
Started Aug 04 05:40:42 PM PDT 24
Finished Aug 04 05:40:43 PM PDT 24
Peak memory 215936 kb
Host smart-26260fed-1efc-4ba1-ad41-8a947fba0380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959951180 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2959951180
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3399245534
Short name T679
Test name
Test status
Simulation time 17803391 ps
CPU time 0.96 seconds
Started Aug 04 05:40:52 PM PDT 24
Finished Aug 04 05:40:53 PM PDT 24
Peak memory 207104 kb
Host smart-2986abf3-e5f9-4005-b2b0-2752a2bcfedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399245534 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3399245534
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1441191542
Short name T773
Test name
Test status
Simulation time 41138541 ps
CPU time 0.9 seconds
Started Aug 04 05:40:46 PM PDT 24
Finished Aug 04 05:40:47 PM PDT 24
Peak memory 215296 kb
Host smart-7d0b6d09-ab29-4143-a143-b3a38f7409b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441191542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1441191542
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.116127399
Short name T646
Test name
Test status
Simulation time 32618793713 ps
CPU time 359.28 seconds
Started Aug 04 05:40:43 PM PDT 24
Finished Aug 04 05:46:42 PM PDT 24
Peak memory 217180 kb
Host smart-1d8503ed-36c8-4c74-a72d-78b83729f495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116127399 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.116127399
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.4048254312
Short name T765
Test name
Test status
Simulation time 186304464 ps
CPU time 1.37 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:09 PM PDT 24
Peak memory 215692 kb
Host smart-51cc74a0-1342-4fb7-99f0-7f349644ce14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048254312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.4048254312
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.4014011686
Short name T582
Test name
Test status
Simulation time 36137577 ps
CPU time 0.93 seconds
Started Aug 04 05:41:01 PM PDT 24
Finished Aug 04 05:41:02 PM PDT 24
Peak memory 206764 kb
Host smart-f03bbca2-909e-41cb-8d24-130ac6fa3543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014011686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.4014011686
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1107433809
Short name T92
Test name
Test status
Simulation time 11347373 ps
CPU time 0.92 seconds
Started Aug 04 05:41:00 PM PDT 24
Finished Aug 04 05:41:01 PM PDT 24
Peak memory 216232 kb
Host smart-5ad4ce4d-fc53-49e5-a666-dfedef0f0e11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107433809 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1107433809
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.300561094
Short name T972
Test name
Test status
Simulation time 21151436 ps
CPU time 1.05 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 218780 kb
Host smart-c4ce603a-38c0-4dba-a2b1-7c0ad441aa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300561094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.300561094
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.3813413582
Short name T462
Test name
Test status
Simulation time 20475270 ps
CPU time 1.19 seconds
Started Aug 04 05:40:58 PM PDT 24
Finished Aug 04 05:40:59 PM PDT 24
Peak memory 224000 kb
Host smart-26a71c67-c7cf-45ed-9509-75c9ff28c829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813413582 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3813413582
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.589916200
Short name T722
Test name
Test status
Simulation time 17988101 ps
CPU time 1.05 seconds
Started Aug 04 05:41:02 PM PDT 24
Finished Aug 04 05:41:03 PM PDT 24
Peak memory 215316 kb
Host smart-95eadec0-d19e-4ccf-a47f-347fc3f94369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589916200 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.589916200
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1209158999
Short name T344
Test name
Test status
Simulation time 19008279 ps
CPU time 1 seconds
Started Aug 04 05:41:04 PM PDT 24
Finished Aug 04 05:41:05 PM PDT 24
Peak memory 206860 kb
Host smart-f69cdf30-d431-4ce8-a7f2-1bb6f97c334e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209158999 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1209158999
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_genbits.4289174437
Short name T371
Test name
Test status
Simulation time 67231387 ps
CPU time 1.68 seconds
Started Aug 04 05:42:23 PM PDT 24
Finished Aug 04 05:42:25 PM PDT 24
Peak memory 218700 kb
Host smart-d43e53fd-73a0-4bab-a813-721ca9eb60f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289174437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4289174437
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.1353263058
Short name T992
Test name
Test status
Simulation time 39301549 ps
CPU time 1.11 seconds
Started Aug 04 05:42:15 PM PDT 24
Finished Aug 04 05:42:16 PM PDT 24
Peak memory 220780 kb
Host smart-0f46daa4-8e4a-4907-a4c6-739284aaff94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353263058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.1353263058
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3029022628
Short name T31
Test name
Test status
Simulation time 31805206 ps
CPU time 1.33 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:36 PM PDT 24
Peak memory 217480 kb
Host smart-3e1e72ed-df71-42ee-839a-e42e6b455f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029022628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3029022628
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.858551470
Short name T523
Test name
Test status
Simulation time 91409288 ps
CPU time 1.2 seconds
Started Aug 04 05:42:20 PM PDT 24
Finished Aug 04 05:42:22 PM PDT 24
Peak memory 218516 kb
Host smart-77b3ce68-f116-4576-8b34-9278d107bd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858551470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.858551470
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2889902109
Short name T490
Test name
Test status
Simulation time 88770990 ps
CPU time 1.1 seconds
Started Aug 04 05:42:30 PM PDT 24
Finished Aug 04 05:42:31 PM PDT 24
Peak memory 217384 kb
Host smart-add54bae-df00-4562-985a-b8f4d4ab30a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889902109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2889902109
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2725934241
Short name T550
Test name
Test status
Simulation time 285848764 ps
CPU time 1.1 seconds
Started Aug 04 05:42:23 PM PDT 24
Finished Aug 04 05:42:24 PM PDT 24
Peak memory 217328 kb
Host smart-990ca1b2-b0c2-439f-95ee-2d8dd4f072b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725934241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2725934241
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.1347711119
Short name T507
Test name
Test status
Simulation time 35952012 ps
CPU time 1.09 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 219744 kb
Host smart-5cf98711-833d-4c25-b9e2-5193db360c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347711119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1347711119
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2590834661
Short name T909
Test name
Test status
Simulation time 55172223 ps
CPU time 1.69 seconds
Started Aug 04 05:42:23 PM PDT 24
Finished Aug 04 05:42:24 PM PDT 24
Peak memory 219448 kb
Host smart-6c376a1a-d887-47de-a495-2911a5cb2d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590834661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2590834661
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3492310657
Short name T439
Test name
Test status
Simulation time 52542308 ps
CPU time 1.7 seconds
Started Aug 04 05:42:24 PM PDT 24
Finished Aug 04 05:42:26 PM PDT 24
Peak memory 220032 kb
Host smart-5140f753-a71b-4662-86ad-fad8769fae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492310657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3492310657
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3444048060
Short name T379
Test name
Test status
Simulation time 80535036 ps
CPU time 1.63 seconds
Started Aug 04 05:42:17 PM PDT 24
Finished Aug 04 05:42:18 PM PDT 24
Peak memory 219064 kb
Host smart-ec3f9665-5907-43bf-bf47-363de54bbb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444048060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3444048060
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.370432555
Short name T139
Test name
Test status
Simulation time 46966244 ps
CPU time 1.21 seconds
Started Aug 04 05:42:26 PM PDT 24
Finished Aug 04 05:42:27 PM PDT 24
Peak memory 218788 kb
Host smart-5f506028-0d66-4141-9d5d-51a276f7b4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370432555 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.370432555
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.3311199472
Short name T993
Test name
Test status
Simulation time 49534395 ps
CPU time 1.18 seconds
Started Aug 04 05:42:31 PM PDT 24
Finished Aug 04 05:42:32 PM PDT 24
Peak memory 218492 kb
Host smart-5c95041b-065f-41d3-9302-4aef754f8d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311199472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3311199472
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.119823833
Short name T847
Test name
Test status
Simulation time 24848151 ps
CPU time 1.17 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:36 PM PDT 24
Peak memory 218604 kb
Host smart-f79aa94c-7b37-4b7d-804d-a813b9d82f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119823833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.119823833
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.2339708623
Short name T514
Test name
Test status
Simulation time 98592637 ps
CPU time 1.27 seconds
Started Aug 04 05:42:16 PM PDT 24
Finished Aug 04 05:42:18 PM PDT 24
Peak memory 219888 kb
Host smart-3ed68059-0d15-4cbe-aea7-18d46b716ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339708623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2339708623
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.4002619795
Short name T831
Test name
Test status
Simulation time 44705523 ps
CPU time 1.22 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:36 PM PDT 24
Peak memory 219664 kb
Host smart-61dfa53e-fcf2-4d92-a529-c1042ee3d61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002619795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.4002619795
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3335906247
Short name T15
Test name
Test status
Simulation time 63502143 ps
CPU time 1.19 seconds
Started Aug 04 05:42:28 PM PDT 24
Finished Aug 04 05:42:29 PM PDT 24
Peak memory 219540 kb
Host smart-cccaa45e-f324-4fe9-84ba-595597999a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335906247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3335906247
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.2906833438
Short name T396
Test name
Test status
Simulation time 45068193 ps
CPU time 0.86 seconds
Started Aug 04 05:40:55 PM PDT 24
Finished Aug 04 05:40:56 PM PDT 24
Peak memory 214888 kb
Host smart-f400cfb0-8662-41d9-a51a-b64f8a94d804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906833438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2906833438
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3215872827
Short name T35
Test name
Test status
Simulation time 99913240 ps
CPU time 1.05 seconds
Started Aug 04 05:40:53 PM PDT 24
Finished Aug 04 05:40:54 PM PDT 24
Peak memory 218544 kb
Host smart-1aa9ffb4-a0f2-4384-b39c-aa13d0f112d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215872827 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3215872827
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2046747443
Short name T360
Test name
Test status
Simulation time 20757407 ps
CPU time 1.12 seconds
Started Aug 04 05:41:06 PM PDT 24
Finished Aug 04 05:41:07 PM PDT 24
Peak memory 219896 kb
Host smart-ee8eef00-b999-4e13-92ef-1e70927109df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046747443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2046747443
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1487842709
Short name T565
Test name
Test status
Simulation time 68921331 ps
CPU time 1.22 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 217476 kb
Host smart-1314aa8f-a0ee-4f55-b9a7-e7aba424d867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487842709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1487842709
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1162558486
Short name T37
Test name
Test status
Simulation time 24678999 ps
CPU time 1.1 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 224124 kb
Host smart-d3526f8e-1d26-4add-8729-554678cb0a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162558486 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1162558486
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3660435042
Short name T367
Test name
Test status
Simulation time 23689471 ps
CPU time 0.87 seconds
Started Aug 04 05:41:08 PM PDT 24
Finished Aug 04 05:41:09 PM PDT 24
Peak memory 215228 kb
Host smart-273f0a78-e902-4aa2-bf96-18694876e610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660435042 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3660435042
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2570970949
Short name T843
Test name
Test status
Simulation time 62378306 ps
CPU time 0.88 seconds
Started Aug 04 05:41:02 PM PDT 24
Finished Aug 04 05:41:03 PM PDT 24
Peak memory 206448 kb
Host smart-cafa0a72-03de-4d80-8974-f83d46249298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570970949 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2570970949
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1866587832
Short name T797
Test name
Test status
Simulation time 43774539599 ps
CPU time 488.33 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:49:08 PM PDT 24
Peak memory 221428 kb
Host smart-a28b2fb1-d909-4827-9959-b6217ef75629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866587832 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1866587832
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1267333388
Short name T713
Test name
Test status
Simulation time 80266461 ps
CPU time 1.26 seconds
Started Aug 04 05:42:24 PM PDT 24
Finished Aug 04 05:42:25 PM PDT 24
Peak memory 218572 kb
Host smart-50267cc5-1a9a-4446-9dbe-ee4f61fc1530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267333388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1267333388
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.3489201278
Short name T820
Test name
Test status
Simulation time 42375626 ps
CPU time 1.74 seconds
Started Aug 04 05:42:24 PM PDT 24
Finished Aug 04 05:42:26 PM PDT 24
Peak memory 218372 kb
Host smart-78bfe8be-ada8-4a2a-8d7b-2f12947acd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489201278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3489201278
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.4134291053
Short name T208
Test name
Test status
Simulation time 27755246 ps
CPU time 1.18 seconds
Started Aug 04 05:42:34 PM PDT 24
Finished Aug 04 05:42:35 PM PDT 24
Peak memory 219772 kb
Host smart-76a3f229-afe5-4639-b4f0-7a0685174280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134291053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.4134291053
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.157972865
Short name T33
Test name
Test status
Simulation time 81307607 ps
CPU time 1.21 seconds
Started Aug 04 05:42:23 PM PDT 24
Finished Aug 04 05:42:25 PM PDT 24
Peak memory 217368 kb
Host smart-bab6dfe4-40f6-430f-a6ae-bf34ae74aaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157972865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.157972865
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1114745972
Short name T922
Test name
Test status
Simulation time 234917730 ps
CPU time 1.54 seconds
Started Aug 04 05:42:23 PM PDT 24
Finished Aug 04 05:42:24 PM PDT 24
Peak memory 218784 kb
Host smart-28619f7c-3269-4ee7-92b8-14c60969257d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114745972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1114745972
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.4235705595
Short name T128
Test name
Test status
Simulation time 176367327 ps
CPU time 1.23 seconds
Started Aug 04 05:42:24 PM PDT 24
Finished Aug 04 05:42:25 PM PDT 24
Peak memory 219872 kb
Host smart-256baefd-370f-4c32-8f60-3317c0838ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235705595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.4235705595
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.1108978755
Short name T837
Test name
Test status
Simulation time 185191257 ps
CPU time 1.37 seconds
Started Aug 04 05:42:23 PM PDT 24
Finished Aug 04 05:42:24 PM PDT 24
Peak memory 218856 kb
Host smart-353196ac-3f8d-454d-a31e-cb932796f189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108978755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1108978755
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.1338402678
Short name T859
Test name
Test status
Simulation time 72135995 ps
CPU time 1.08 seconds
Started Aug 04 05:42:32 PM PDT 24
Finished Aug 04 05:42:33 PM PDT 24
Peak memory 218764 kb
Host smart-8ae95447-98e8-4556-8433-dfe61919dc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338402678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1338402678
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.1060324235
Short name T693
Test name
Test status
Simulation time 64526129 ps
CPU time 1.4 seconds
Started Aug 04 05:42:32 PM PDT 24
Finished Aug 04 05:42:33 PM PDT 24
Peak memory 217776 kb
Host smart-a434afe3-2903-4f88-8c6e-7de2924078e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060324235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1060324235
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.559715087
Short name T173
Test name
Test status
Simulation time 114211918 ps
CPU time 1.32 seconds
Started Aug 04 05:42:27 PM PDT 24
Finished Aug 04 05:42:28 PM PDT 24
Peak memory 215764 kb
Host smart-904b576a-7843-4438-a282-b011dc33485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559715087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.559715087
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1315190834
Short name T355
Test name
Test status
Simulation time 87934056 ps
CPU time 1.53 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 217392 kb
Host smart-5f200883-446e-4e3f-9283-6595d51ac398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315190834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1315190834
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.2320851083
Short name T990
Test name
Test status
Simulation time 70847438 ps
CPU time 1.09 seconds
Started Aug 04 05:42:20 PM PDT 24
Finished Aug 04 05:42:21 PM PDT 24
Peak memory 218772 kb
Host smart-0fedcfe4-6d32-4ec9-9b7f-f3a15f07f8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320851083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.2320851083
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.192301201
Short name T53
Test name
Test status
Simulation time 59331398 ps
CPU time 1.23 seconds
Started Aug 04 05:42:26 PM PDT 24
Finished Aug 04 05:42:28 PM PDT 24
Peak memory 218924 kb
Host smart-041dce37-4596-4538-aaf7-7fcf7c7b467c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192301201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.192301201
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.3467904090
Short name T491
Test name
Test status
Simulation time 62610135 ps
CPU time 1.14 seconds
Started Aug 04 05:42:28 PM PDT 24
Finished Aug 04 05:42:29 PM PDT 24
Peak memory 218644 kb
Host smart-e99e551e-cdb7-4e38-9a37-858c36ca547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467904090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.3467904090
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.354213227
Short name T896
Test name
Test status
Simulation time 101013435 ps
CPU time 1.82 seconds
Started Aug 04 05:42:32 PM PDT 24
Finished Aug 04 05:42:34 PM PDT 24
Peak memory 218628 kb
Host smart-8e2fe9c2-a6f9-4520-9982-d6ffe8a92f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354213227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.354213227
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1449769148
Short name T488
Test name
Test status
Simulation time 67095665 ps
CPU time 1.06 seconds
Started Aug 04 05:42:27 PM PDT 24
Finished Aug 04 05:42:28 PM PDT 24
Peak memory 219748 kb
Host smart-3c4d1fd1-18c2-4ced-9d2d-a105ce077f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449769148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1449769148
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3107930270
Short name T793
Test name
Test status
Simulation time 29022396 ps
CPU time 1.2 seconds
Started Aug 04 05:42:20 PM PDT 24
Finished Aug 04 05:42:22 PM PDT 24
Peak memory 218332 kb
Host smart-460a248f-9104-4570-9465-d47d741d6381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107930270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3107930270
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1839330137
Short name T612
Test name
Test status
Simulation time 27581588 ps
CPU time 1.25 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 220484 kb
Host smart-97bc92e8-e4d7-4828-9405-b6144b2c7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839330137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1839330137
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.2543107885
Short name T712
Test name
Test status
Simulation time 32062237 ps
CPU time 1.36 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 218528 kb
Host smart-a432c144-2775-4a06-a3c1-ecbb0dad9804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543107885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2543107885
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1998974923
Short name T928
Test name
Test status
Simulation time 100507251 ps
CPU time 1.43 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 219920 kb
Host smart-d06ee0f0-e130-4c17-b51b-a47f2f82c985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998974923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1998974923
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.4017913067
Short name T814
Test name
Test status
Simulation time 46842326 ps
CPU time 0.99 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 206716 kb
Host smart-d1236c24-c4e8-451b-b745-3ffa9009cc92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017913067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.4017913067
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2752735806
Short name T95
Test name
Test status
Simulation time 73331817 ps
CPU time 1.38 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:41:01 PM PDT 24
Peak memory 216852 kb
Host smart-291407fb-593d-4c6d-94ee-f65eaef78432
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752735806 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2752735806
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3497739961
Short name T788
Test name
Test status
Simulation time 32051422 ps
CPU time 0.89 seconds
Started Aug 04 05:41:00 PM PDT 24
Finished Aug 04 05:41:01 PM PDT 24
Peak memory 218368 kb
Host smart-bc7314fd-2963-4854-8fd2-b2c541e5ff91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497739961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3497739961
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1301888585
Short name T522
Test name
Test status
Simulation time 170116909 ps
CPU time 1.09 seconds
Started Aug 04 05:41:02 PM PDT 24
Finished Aug 04 05:41:03 PM PDT 24
Peak memory 217348 kb
Host smart-e71e7690-0094-48f6-962b-8f28f627ebdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301888585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1301888585
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.1767565143
Short name T688
Test name
Test status
Simulation time 18086227 ps
CPU time 1.08 seconds
Started Aug 04 05:41:02 PM PDT 24
Finished Aug 04 05:41:03 PM PDT 24
Peak memory 215320 kb
Host smart-c0e5c40f-0865-42d9-9ab7-d4c9d8e6f4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767565143 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1767565143
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2822530027
Short name T402
Test name
Test status
Simulation time 280011000 ps
CPU time 3.33 seconds
Started Aug 04 05:41:00 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 215600 kb
Host smart-34bba8bf-56c2-442d-85a6-be6743fc2d77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822530027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2822530027
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.13741994
Short name T580
Test name
Test status
Simulation time 17559725281 ps
CPU time 439.78 seconds
Started Aug 04 05:41:00 PM PDT 24
Finished Aug 04 05:48:20 PM PDT 24
Peak memory 219300 kb
Host smart-e9460708-e9ba-499e-bd45-3df234b29278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13741994 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.13741994
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.2980800122
Short name T277
Test name
Test status
Simulation time 35325292 ps
CPU time 1.08 seconds
Started Aug 04 05:42:25 PM PDT 24
Finished Aug 04 05:42:27 PM PDT 24
Peak memory 219568 kb
Host smart-6698cbac-dce5-4014-af19-784a07a0a108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980800122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2980800122
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.771935934
Short name T577
Test name
Test status
Simulation time 262530151 ps
CPU time 3.52 seconds
Started Aug 04 05:42:32 PM PDT 24
Finished Aug 04 05:42:35 PM PDT 24
Peak memory 219296 kb
Host smart-8310d87c-5e6e-4a47-90d9-bd1e8cab7528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771935934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.771935934
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.4105242991
Short name T963
Test name
Test status
Simulation time 71924947 ps
CPU time 1.12 seconds
Started Aug 04 05:42:31 PM PDT 24
Finished Aug 04 05:42:33 PM PDT 24
Peak memory 220276 kb
Host smart-826bfa8a-c234-4646-8b37-9be3510f2b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105242991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.4105242991
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.601350357
Short name T374
Test name
Test status
Simulation time 20464238 ps
CPU time 1.12 seconds
Started Aug 04 05:42:30 PM PDT 24
Finished Aug 04 05:42:32 PM PDT 24
Peak memory 217252 kb
Host smart-bc1a3aeb-c83a-4bdc-bc16-11f6a3d319b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601350357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.601350357
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.375551307
Short name T566
Test name
Test status
Simulation time 30316407 ps
CPU time 1.3 seconds
Started Aug 04 05:42:34 PM PDT 24
Finished Aug 04 05:42:35 PM PDT 24
Peak memory 219392 kb
Host smart-74cf7ab0-df72-4280-8bfa-74fa803c680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375551307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.375551307
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.5777711
Short name T933
Test name
Test status
Simulation time 86283469 ps
CPU time 1.13 seconds
Started Aug 04 05:42:31 PM PDT 24
Finished Aug 04 05:42:33 PM PDT 24
Peak memory 217268 kb
Host smart-68f2e6d8-52cc-46d6-9275-208b3ef87a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5777711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.5777711
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.1451411730
Short name T133
Test name
Test status
Simulation time 72890612 ps
CPU time 1.18 seconds
Started Aug 04 05:42:27 PM PDT 24
Finished Aug 04 05:42:28 PM PDT 24
Peak memory 219672 kb
Host smart-c3a48f8c-ef3f-4851-a9f3-f71d09e64a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451411730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1451411730
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.1143936359
Short name T422
Test name
Test status
Simulation time 69147219 ps
CPU time 2.41 seconds
Started Aug 04 05:42:25 PM PDT 24
Finished Aug 04 05:42:28 PM PDT 24
Peak memory 215328 kb
Host smart-7d92faf0-76a1-4998-ac01-c0c3d7733a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143936359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1143936359
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.3356366318
Short name T243
Test name
Test status
Simulation time 62321212 ps
CPU time 1.23 seconds
Started Aug 04 05:42:31 PM PDT 24
Finished Aug 04 05:42:32 PM PDT 24
Peak memory 218660 kb
Host smart-e1f8669d-e9ec-4f56-87aa-d962fd5ae100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356366318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3356366318
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.1258531571
Short name T419
Test name
Test status
Simulation time 54255828 ps
CPU time 1.55 seconds
Started Aug 04 05:42:32 PM PDT 24
Finished Aug 04 05:42:33 PM PDT 24
Peak memory 218608 kb
Host smart-cb1ab1d2-d047-4455-a8c9-d608b5006f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258531571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1258531571
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.2989107138
Short name T911
Test name
Test status
Simulation time 24279674 ps
CPU time 1.18 seconds
Started Aug 04 05:42:31 PM PDT 24
Finished Aug 04 05:42:32 PM PDT 24
Peak memory 219580 kb
Host smart-09f495d6-0a39-4652-95cd-cc80337d269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989107138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2989107138
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.3577569365
Short name T940
Test name
Test status
Simulation time 121534666 ps
CPU time 1.2 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 219848 kb
Host smart-efb09a9b-de3a-4f11-90f0-ffa02c4db297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577569365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3577569365
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3911653201
Short name T675
Test name
Test status
Simulation time 26211449 ps
CPU time 1.22 seconds
Started Aug 04 05:42:32 PM PDT 24
Finished Aug 04 05:42:33 PM PDT 24
Peak memory 219964 kb
Host smart-9ca34797-e2e6-45d5-8e68-866abedd4955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911653201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3911653201
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.1409916608
Short name T467
Test name
Test status
Simulation time 28442105 ps
CPU time 1.36 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 217436 kb
Host smart-e6b96017-a697-4603-bdfc-00782c198165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409916608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1409916608
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.1978641263
Short name T559
Test name
Test status
Simulation time 34397616 ps
CPU time 1.12 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 219644 kb
Host smart-22fed427-7e81-4c84-b541-a12e4ccda5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978641263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1978641263
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.2892835238
Short name T737
Test name
Test status
Simulation time 38151869 ps
CPU time 1.11 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 217264 kb
Host smart-e8072022-a7ec-4802-bb09-d12b6a767cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892835238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2892835238
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1938426654
Short name T217
Test name
Test status
Simulation time 62573049 ps
CPU time 1.24 seconds
Started Aug 04 05:41:04 PM PDT 24
Finished Aug 04 05:41:05 PM PDT 24
Peak memory 219220 kb
Host smart-addda187-ec32-432c-921f-ea6c7276900c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938426654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1938426654
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3597710901
Short name T368
Test name
Test status
Simulation time 15912500 ps
CPU time 0.91 seconds
Started Aug 04 05:41:01 PM PDT 24
Finished Aug 04 05:41:02 PM PDT 24
Peak memory 206744 kb
Host smart-1f1f35f3-e920-492a-a8e6-ae2ed75b5b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597710901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3597710901
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3878776330
Short name T830
Test name
Test status
Simulation time 26618525 ps
CPU time 0.82 seconds
Started Aug 04 05:41:05 PM PDT 24
Finished Aug 04 05:41:06 PM PDT 24
Peak memory 216332 kb
Host smart-88431ea3-5654-4b17-b6f1-4f3f5ec9234e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878776330 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3878776330
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3825106559
Short name T727
Test name
Test status
Simulation time 111130400 ps
CPU time 1.17 seconds
Started Aug 04 05:41:01 PM PDT 24
Finished Aug 04 05:41:02 PM PDT 24
Peak memory 217024 kb
Host smart-f805bc8d-22a5-4ef5-8d40-fc808a746b4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825106559 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3825106559
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2830716218
Short name T724
Test name
Test status
Simulation time 56170957 ps
CPU time 0.79 seconds
Started Aug 04 05:41:00 PM PDT 24
Finished Aug 04 05:41:01 PM PDT 24
Peak memory 217964 kb
Host smart-586f51a3-91bc-41cf-baa5-7a1fd61ee487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830716218 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2830716218
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.691415060
Short name T505
Test name
Test status
Simulation time 92635835 ps
CPU time 1.14 seconds
Started Aug 04 05:41:01 PM PDT 24
Finished Aug 04 05:41:02 PM PDT 24
Peak memory 217440 kb
Host smart-2199c3d8-d63c-4bce-9b04-425b2e625cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691415060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.691415060
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.810595626
Short name T59
Test name
Test status
Simulation time 22086770 ps
CPU time 1.11 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 214856 kb
Host smart-d371a183-90d3-4e12-8c24-aa29b42db29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810595626 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.810595626
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.875355489
Short name T498
Test name
Test status
Simulation time 17076276 ps
CPU time 1 seconds
Started Aug 04 05:41:04 PM PDT 24
Finished Aug 04 05:41:06 PM PDT 24
Peak memory 215308 kb
Host smart-c1f82427-42bb-473f-947d-70ded708f500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875355489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.875355489
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1285987335
Short name T481
Test name
Test status
Simulation time 435278083 ps
CPU time 3.15 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:11 PM PDT 24
Peak memory 218696 kb
Host smart-404e2130-49f9-4224-a5b6-6fecf9ad8ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285987335 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1285987335
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3146318851
Short name T231
Test name
Test status
Simulation time 156091071223 ps
CPU time 1776.12 seconds
Started Aug 04 05:41:05 PM PDT 24
Finished Aug 04 06:10:42 PM PDT 24
Peak memory 225668 kb
Host smart-bbd9b7ba-7c50-4922-8ec6-a4f778133146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146318851 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3146318851
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.830043895
Short name T639
Test name
Test status
Simulation time 63546087 ps
CPU time 1.06 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 218804 kb
Host smart-24a7b9a2-f6b8-447e-8a56-04b43d710197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830043895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.830043895
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1391894299
Short name T886
Test name
Test status
Simulation time 79680950 ps
CPU time 0.99 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 217252 kb
Host smart-2b06edd1-168c-46b9-a52a-063453b31feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391894299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1391894299
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.996334741
Short name T985
Test name
Test status
Simulation time 71159133 ps
CPU time 1.09 seconds
Started Aug 04 05:42:32 PM PDT 24
Finished Aug 04 05:42:33 PM PDT 24
Peak memory 220356 kb
Host smart-5ce12188-4c53-4f98-93a6-2485ec1c4f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996334741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.996334741
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.728734158
Short name T517
Test name
Test status
Simulation time 71874105 ps
CPU time 1.89 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 220160 kb
Host smart-404a4a68-2923-4ba1-bd29-21381983ba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728734158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.728734158
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1447260150
Short name T931
Test name
Test status
Simulation time 32138283 ps
CPU time 1.34 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 215676 kb
Host smart-44c86fc8-ba37-4118-a486-129b1a258fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447260150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1447260150
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.530460089
Short name T24
Test name
Test status
Simulation time 152596457 ps
CPU time 1.51 seconds
Started Aug 04 05:42:33 PM PDT 24
Finished Aug 04 05:42:34 PM PDT 24
Peak memory 218752 kb
Host smart-b890619d-d5cd-4d19-98ca-846d895be43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530460089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.530460089
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.2808361116
Short name T974
Test name
Test status
Simulation time 75818256 ps
CPU time 1.19 seconds
Started Aug 04 05:42:43 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 221384 kb
Host smart-cea08c78-f4bb-4c1a-99f4-f549cbb8c397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808361116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2808361116
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.2739567523
Short name T885
Test name
Test status
Simulation time 77957420 ps
CPU time 1.78 seconds
Started Aug 04 05:42:29 PM PDT 24
Finished Aug 04 05:42:31 PM PDT 24
Peak memory 220228 kb
Host smart-60195813-e133-4a92-b22a-2991535d42cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739567523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2739567523
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1816558829
Short name T294
Test name
Test status
Simulation time 28284939 ps
CPU time 1.19 seconds
Started Aug 04 05:42:33 PM PDT 24
Finished Aug 04 05:42:35 PM PDT 24
Peak memory 215704 kb
Host smart-2d54e939-3368-4975-98d6-cf048331087d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816558829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1816558829
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.2648269266
Short name T438
Test name
Test status
Simulation time 90365179 ps
CPU time 1.28 seconds
Started Aug 04 05:42:32 PM PDT 24
Finished Aug 04 05:42:34 PM PDT 24
Peak memory 218928 kb
Host smart-3ceab1ca-c64c-41cd-998f-df071a07395e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648269266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2648269266
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.4220469357
Short name T936
Test name
Test status
Simulation time 141129815 ps
CPU time 1.17 seconds
Started Aug 04 05:42:24 PM PDT 24
Finished Aug 04 05:42:25 PM PDT 24
Peak memory 219120 kb
Host smart-9ab12b74-e39f-43f0-9e13-1c150242b9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220469357 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.4220469357
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.3015170788
Short name T923
Test name
Test status
Simulation time 32810643 ps
CPU time 1.3 seconds
Started Aug 04 05:42:33 PM PDT 24
Finished Aug 04 05:42:34 PM PDT 24
Peak memory 217280 kb
Host smart-664c9c56-def8-47e7-9f2a-83d1524fdeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015170788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3015170788
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3065150525
Short name T917
Test name
Test status
Simulation time 64957327 ps
CPU time 1.35 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 218596 kb
Host smart-451463a1-2abd-4880-9645-0094bd0af00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065150525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3065150525
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2826909604
Short name T186
Test name
Test status
Simulation time 336183696 ps
CPU time 1.25 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 219704 kb
Host smart-fbf71a7a-f777-4b2e-b8f3-6878f2367d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826909604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2826909604
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.501418732
Short name T798
Test name
Test status
Simulation time 97756909 ps
CPU time 1.56 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 218996 kb
Host smart-1bde6ce8-99f5-4638-8feb-72f216c973e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501418732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.501418732
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3909009617
Short name T274
Test name
Test status
Simulation time 87848080 ps
CPU time 1.21 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 218716 kb
Host smart-102bd12f-eda2-426e-90c4-94224eabdca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909009617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3909009617
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.253211006
Short name T539
Test name
Test status
Simulation time 28673907 ps
CPU time 1.27 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 219880 kb
Host smart-e6be411f-b2fd-4657-ad59-f68c658da375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253211006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.253211006
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.991124230
Short name T391
Test name
Test status
Simulation time 67992626 ps
CPU time 1.19 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 220188 kb
Host smart-c368fd6c-d83a-4a36-9a05-6ca20297f84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991124230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.991124230
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2623803585
Short name T689
Test name
Test status
Simulation time 55997271 ps
CPU time 2.04 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 217708 kb
Host smart-e2f23249-5bc1-4bbe-9210-194578069e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623803585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2623803585
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2445472431
Short name T680
Test name
Test status
Simulation time 25851080 ps
CPU time 1.24 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 219656 kb
Host smart-41ef6d74-dff4-4231-8a69-07d446a656a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445472431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2445472431
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.12452101
Short name T542
Test name
Test status
Simulation time 55103553 ps
CPU time 0.92 seconds
Started Aug 04 05:41:01 PM PDT 24
Finished Aug 04 05:41:02 PM PDT 24
Peak memory 214888 kb
Host smart-4f0a4923-6936-4706-9685-0ce343d6fdc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12452101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.12452101
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2622011376
Short name T358
Test name
Test status
Simulation time 46953572 ps
CPU time 1.4 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:14 PM PDT 24
Peak memory 216960 kb
Host smart-5fa97f98-c0dc-45e1-a002-500c41901151
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622011376 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2622011376
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2535223889
Short name T179
Test name
Test status
Simulation time 52946780 ps
CPU time 0.85 seconds
Started Aug 04 05:41:02 PM PDT 24
Finished Aug 04 05:41:03 PM PDT 24
Peak memory 218276 kb
Host smart-77d82d8e-ddee-4c3b-aba4-9f5edc1b67c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535223889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2535223889
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1422571821
Short name T586
Test name
Test status
Simulation time 32725641 ps
CPU time 1.29 seconds
Started Aug 04 05:41:00 PM PDT 24
Finished Aug 04 05:41:01 PM PDT 24
Peak memory 217132 kb
Host smart-cae8d739-13f5-44e6-8f65-698be59e0f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422571821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1422571821
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.394502612
Short name T753
Test name
Test status
Simulation time 34305343 ps
CPU time 0.86 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 215160 kb
Host smart-6ae7f792-4aa9-49d3-a120-f3b1c3b3541b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394502612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.394502612
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.788739592
Short name T476
Test name
Test status
Simulation time 163814766 ps
CPU time 0.92 seconds
Started Aug 04 05:41:00 PM PDT 24
Finished Aug 04 05:41:01 PM PDT 24
Peak memory 215072 kb
Host smart-04985ccf-734b-4414-a346-0fed245e22aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788739592 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.788739592
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2691040919
Short name T744
Test name
Test status
Simulation time 76122696 ps
CPU time 2.01 seconds
Started Aug 04 05:40:56 PM PDT 24
Finished Aug 04 05:40:59 PM PDT 24
Peak memory 220172 kb
Host smart-e233cc61-f223-4f2a-9040-586c4528bb58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691040919 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2691040919
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.4082086011
Short name T397
Test name
Test status
Simulation time 117448631957 ps
CPU time 2610.83 seconds
Started Aug 04 05:40:58 PM PDT 24
Finished Aug 04 06:24:29 PM PDT 24
Peak memory 229776 kb
Host smart-12e332c0-b09c-4217-86c7-c67eff647743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082086011 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.4082086011
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1499230070
Short name T716
Test name
Test status
Simulation time 28182040 ps
CPU time 1.15 seconds
Started Aug 04 05:42:25 PM PDT 24
Finished Aug 04 05:42:26 PM PDT 24
Peak memory 218552 kb
Host smart-672b6634-29d7-4ae8-972f-4536232dd9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499230070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1499230070
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/141.edn_alert.2081103573
Short name T733
Test name
Test status
Simulation time 82597524 ps
CPU time 1.21 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218628 kb
Host smart-6cb2f85e-07ad-4eb5-9ee6-ab3758198c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081103573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2081103573
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1518577298
Short name T531
Test name
Test status
Simulation time 40048773 ps
CPU time 1.44 seconds
Started Aug 04 05:42:30 PM PDT 24
Finished Aug 04 05:42:32 PM PDT 24
Peak memory 218532 kb
Host smart-411900f4-9abb-430e-b914-16ab8bb458dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518577298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1518577298
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1556484598
Short name T164
Test name
Test status
Simulation time 77291044 ps
CPU time 1.02 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 220728 kb
Host smart-11804c40-a383-4f24-9196-a25f695cf1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556484598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1556484598
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.39238316
Short name T829
Test name
Test status
Simulation time 39700767 ps
CPU time 1.02 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 217432 kb
Host smart-87e91e3c-ee0f-4070-8008-5b981a78aefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39238316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.39238316
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.2662649116
Short name T897
Test name
Test status
Simulation time 70051198 ps
CPU time 1.25 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 215684 kb
Host smart-99556bae-59fd-4457-8628-292d3df84124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662649116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.2662649116
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/145.edn_alert.1440815325
Short name T641
Test name
Test status
Simulation time 340180410 ps
CPU time 1.19 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 218636 kb
Host smart-8ea5f172-8000-4dbf-a815-e1ba581a7bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440815325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1440815325
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.3204450575
Short name T411
Test name
Test status
Simulation time 46315343 ps
CPU time 1.28 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 218668 kb
Host smart-a371cbb8-63e2-4ddc-983a-bddaaef3e3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204450575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3204450575
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.3819927774
Short name T36
Test name
Test status
Simulation time 55940186 ps
CPU time 1.27 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 215668 kb
Host smart-1ee478c3-8f2e-4e00-9516-a72e311e04ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819927774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.3819927774
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.3777489067
Short name T409
Test name
Test status
Simulation time 58619044 ps
CPU time 1.34 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 217316 kb
Host smart-00b5e9d8-6d28-4c39-bcb2-bc3b2e63d289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777489067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3777489067
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.2261770013
Short name T781
Test name
Test status
Simulation time 31845391 ps
CPU time 1.3 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 215672 kb
Host smart-63e8e528-d08b-448a-a4a4-22ecad9bc66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261770013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.2261770013
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3490494072
Short name T429
Test name
Test status
Simulation time 70197582 ps
CPU time 2.38 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 220512 kb
Host smart-735c1fcd-9bb9-4d33-9f2c-ed7659b13164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490494072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3490494072
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.1258143545
Short name T442
Test name
Test status
Simulation time 25875357 ps
CPU time 1.2 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 221076 kb
Host smart-317b71ff-8e21-472b-b3d9-901522e83f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258143545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1258143545
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.716999101
Short name T455
Test name
Test status
Simulation time 61408734 ps
CPU time 1.34 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 218864 kb
Host smart-0e2d823d-6f05-4256-8d44-e5e8c39a6788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716999101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.716999101
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.2150680165
Short name T862
Test name
Test status
Simulation time 81804718 ps
CPU time 1.21 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 219604 kb
Host smart-cfe76e0b-6773-44cb-9806-6064fea326be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150680165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.2150680165
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3510230210
Short name T459
Test name
Test status
Simulation time 38672186 ps
CPU time 1.5 seconds
Started Aug 04 05:42:33 PM PDT 24
Finished Aug 04 05:42:35 PM PDT 24
Peak memory 220068 kb
Host smart-0c0b9ea3-0b9a-4c70-9924-88878d2012af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510230210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3510230210
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2440724133
Short name T695
Test name
Test status
Simulation time 28606129 ps
CPU time 1.24 seconds
Started Aug 04 05:41:00 PM PDT 24
Finished Aug 04 05:41:02 PM PDT 24
Peak memory 220928 kb
Host smart-c11c3b04-79de-49a4-bdc3-29f930951d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440724133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2440724133
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1620846330
Short name T758
Test name
Test status
Simulation time 23852259 ps
CPU time 0.88 seconds
Started Aug 04 05:41:04 PM PDT 24
Finished Aug 04 05:41:05 PM PDT 24
Peak memory 206720 kb
Host smart-c08d1375-c2b4-40e3-9348-917104bdac5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620846330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1620846330
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_err.2787354135
Short name T696
Test name
Test status
Simulation time 18076911 ps
CPU time 1.02 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 218416 kb
Host smart-7f5aa837-f653-4b0f-934b-43d16ac4006f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787354135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2787354135
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2549704619
Short name T959
Test name
Test status
Simulation time 76812364 ps
CPU time 1.3 seconds
Started Aug 04 05:41:02 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 217432 kb
Host smart-51b45dd2-c0af-4e26-aeb7-d7f8300e07df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549704619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2549704619
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.2902646972
Short name T454
Test name
Test status
Simulation time 48762238 ps
CPU time 0.91 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 215276 kb
Host smart-680cccdd-e27c-4269-a3cb-b900b8f4dfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902646972 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2902646972
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3008279120
Short name T461
Test name
Test status
Simulation time 1491920395 ps
CPU time 3.09 seconds
Started Aug 04 05:41:01 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 217052 kb
Host smart-f80c936c-b67a-4b40-aa3c-475ef80dd33d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008279120 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3008279120
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3311054594
Short name T833
Test name
Test status
Simulation time 175988149076 ps
CPU time 1177.17 seconds
Started Aug 04 05:40:57 PM PDT 24
Finished Aug 04 06:00:35 PM PDT 24
Peak memory 223384 kb
Host smart-61399220-bd53-40e5-b35d-3544edb3866f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311054594 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3311054594
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.3625933901
Short name T219
Test name
Test status
Simulation time 42440195 ps
CPU time 1.19 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 219944 kb
Host smart-239bf10d-2c60-4878-89b7-68d271155173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625933901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3625933901
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2348054039
Short name T392
Test name
Test status
Simulation time 199033722 ps
CPU time 1.09 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 217436 kb
Host smart-8ed80c65-8b4d-4c20-a817-4c0ab0d7b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348054039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2348054039
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.826484061
Short name T915
Test name
Test status
Simulation time 34621200 ps
CPU time 1.2 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 219644 kb
Host smart-65082ac7-7934-4244-8ee9-596957ef0062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826484061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.826484061
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/152.edn_alert.2084963419
Short name T655
Test name
Test status
Simulation time 74109078 ps
CPU time 1.13 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 218644 kb
Host smart-2a0f37c7-f397-496d-9123-68dd9649330e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084963419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2084963419
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.977997272
Short name T989
Test name
Test status
Simulation time 43804592 ps
CPU time 1.43 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 218512 kb
Host smart-f1fe9e20-101a-4a07-9444-bac3e2cda1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977997272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.977997272
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1336311538
Short name T213
Test name
Test status
Simulation time 25035630 ps
CPU time 1.16 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 215620 kb
Host smart-8282963f-0d70-41f7-adef-30140331ecdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336311538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1336311538
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.2608668955
Short name T380
Test name
Test status
Simulation time 35582476 ps
CPU time 1.41 seconds
Started Aug 04 05:42:32 PM PDT 24
Finished Aug 04 05:42:33 PM PDT 24
Peak memory 217360 kb
Host smart-0135fa5c-d231-4482-81cc-b3f990e49076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608668955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2608668955
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.3719502864
Short name T136
Test name
Test status
Simulation time 137196268 ps
CPU time 1.09 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 220616 kb
Host smart-ca89c2e5-22ce-4def-9551-ceda5ab6e00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719502864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3719502864
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.3428970620
Short name T434
Test name
Test status
Simulation time 64491920 ps
CPU time 1.48 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 218668 kb
Host smart-d7c34e54-a071-41fb-94fc-0fc0aacd70a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428970620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3428970620
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.572797248
Short name T650
Test name
Test status
Simulation time 47196124 ps
CPU time 1.18 seconds
Started Aug 04 05:42:43 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 219736 kb
Host smart-3563bcb1-c6cf-4b51-8de2-5d714ff0a51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572797248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.572797248
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1537430567
Short name T593
Test name
Test status
Simulation time 99017419 ps
CPU time 1.34 seconds
Started Aug 04 05:42:34 PM PDT 24
Finished Aug 04 05:42:35 PM PDT 24
Peak memory 218772 kb
Host smart-76e04ec6-6625-48f0-9e46-b5564674a5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537430567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1537430567
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.4183493820
Short name T160
Test name
Test status
Simulation time 31292988 ps
CPU time 1.33 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 220544 kb
Host smart-cab31d4f-d3bb-4ad3-9bb4-e558397ab141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183493820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.4183493820
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2222980901
Short name T320
Test name
Test status
Simulation time 73200781 ps
CPU time 1.82 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 218440 kb
Host smart-29fbefe8-7ab2-459a-bab6-cf6ff2c49cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222980901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2222980901
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.2861799866
Short name T854
Test name
Test status
Simulation time 23878916 ps
CPU time 1.18 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 219872 kb
Host smart-4bac5793-41f4-465e-a4c3-34ff9b181c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861799866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2861799866
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3065247697
Short name T840
Test name
Test status
Simulation time 131658701 ps
CPU time 1.2 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 217260 kb
Host smart-0c381082-408d-4802-a1f5-b5d0163b6959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065247697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3065247697
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1389433759
Short name T630
Test name
Test status
Simulation time 22781415 ps
CPU time 1.16 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 219968 kb
Host smart-f583fe50-faf1-4144-8421-b657fd248d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389433759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1389433759
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1653570610
Short name T660
Test name
Test status
Simulation time 48371791 ps
CPU time 1.74 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 217528 kb
Host smart-c584a6e9-1d33-490c-a781-67b9b18d3357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653570610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1653570610
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.691592651
Short name T756
Test name
Test status
Simulation time 31582458 ps
CPU time 1.27 seconds
Started Aug 04 05:42:26 PM PDT 24
Finished Aug 04 05:42:27 PM PDT 24
Peak memory 219912 kb
Host smart-cf4580eb-5922-4ab3-863b-0fe83c3920c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691592651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.691592651
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert.3888044603
Short name T573
Test name
Test status
Simulation time 88724762 ps
CPU time 1.23 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:08 PM PDT 24
Peak memory 218496 kb
Host smart-ac26988a-d3d6-4025-a7b4-608065b55656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888044603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3888044603
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.751134242
Short name T805
Test name
Test status
Simulation time 18732439 ps
CPU time 0.98 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:08 PM PDT 24
Peak memory 215148 kb
Host smart-1af559af-eeed-4b01-9e5e-d7935b13ecf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751134242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.751134242
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.89536988
Short name T202
Test name
Test status
Simulation time 47802672 ps
CPU time 0.83 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 216204 kb
Host smart-030324fc-db7f-4c6c-a4b2-96ef072b349b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89536988 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.89536988
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2372043161
Short name T101
Test name
Test status
Simulation time 105223778 ps
CPU time 1.17 seconds
Started Aug 04 05:41:04 PM PDT 24
Finished Aug 04 05:41:05 PM PDT 24
Peak memory 216892 kb
Host smart-e4774422-de90-4e62-900d-5c2ff2325354
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372043161 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2372043161
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_genbits.2904275864
Short name T553
Test name
Test status
Simulation time 59978380 ps
CPU time 1.25 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:05 PM PDT 24
Peak memory 218496 kb
Host smart-2009274e-71b3-4b7b-a8cd-808ede8274c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904275864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2904275864
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3888030639
Short name T640
Test name
Test status
Simulation time 27103626 ps
CPU time 0.92 seconds
Started Aug 04 05:41:04 PM PDT 24
Finished Aug 04 05:41:05 PM PDT 24
Peak memory 215792 kb
Host smart-65cbb20e-ab05-4886-b8ee-216a6239a83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888030639 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3888030639
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1388582479
Short name T927
Test name
Test status
Simulation time 16888868 ps
CPU time 0.97 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 215284 kb
Host smart-b9fb3829-dd5f-4c9e-8095-51dbaac054ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388582479 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1388582479
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3192291806
Short name T875
Test name
Test status
Simulation time 154973297 ps
CPU time 3.49 seconds
Started Aug 04 05:41:06 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 215352 kb
Host smart-580d3d6f-2626-4d18-864c-b116c267992f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192291806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3192291806
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.4133058097
Short name T223
Test name
Test status
Simulation time 36682214239 ps
CPU time 804.23 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:54:28 PM PDT 24
Peak memory 223672 kb
Host smart-f1d9dc64-a3c2-4470-b25f-14c704096261
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133058097 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.4133058097
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.1702999025
Short name T304
Test name
Test status
Simulation time 22292634 ps
CPU time 1.14 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 215724 kb
Host smart-8216ebae-11ba-4c1d-a703-8ac75a0e98d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702999025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.1702999025
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1857069679
Short name T714
Test name
Test status
Simulation time 42716967 ps
CPU time 0.98 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 217184 kb
Host smart-22050cee-2849-4e98-a601-6aa9e3fd31fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857069679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1857069679
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1045904673
Short name T140
Test name
Test status
Simulation time 27173160 ps
CPU time 1.25 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 219764 kb
Host smart-9133f783-c804-4945-8f7a-af70e3790c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045904673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1045904673
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.3405618134
Short name T903
Test name
Test status
Simulation time 139321721 ps
CPU time 2.6 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 217428 kb
Host smart-d99928e6-953e-4544-91d8-9a95ea934be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405618134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3405618134
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.224154333
Short name T502
Test name
Test status
Simulation time 107656851 ps
CPU time 1.03 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 217344 kb
Host smart-29996162-b562-4998-bf4d-0736dea68cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224154333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.224154333
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1581639484
Short name T299
Test name
Test status
Simulation time 43516201 ps
CPU time 1.09 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 218340 kb
Host smart-30916a61-c26d-4aea-a767-ec2f7c11de68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581639484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1581639484
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.3199230746
Short name T416
Test name
Test status
Simulation time 38055745 ps
CPU time 1.46 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 218708 kb
Host smart-4a001e88-9994-48ae-8953-6a7a4308f437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199230746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3199230746
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2457014163
Short name T761
Test name
Test status
Simulation time 151583198 ps
CPU time 1.15 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218388 kb
Host smart-3231411d-2ef8-4d64-bf10-5bff50c0d203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457014163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2457014163
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1730693089
Short name T399
Test name
Test status
Simulation time 79317201 ps
CPU time 1.56 seconds
Started Aug 04 05:42:33 PM PDT 24
Finished Aug 04 05:42:35 PM PDT 24
Peak memory 220096 kb
Host smart-b1943b0b-976d-42cc-bb0b-54a58c647ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730693089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1730693089
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3316910367
Short name T884
Test name
Test status
Simulation time 71318443 ps
CPU time 1.19 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 219876 kb
Host smart-9f8add6d-f616-4248-b6bf-809700848597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316910367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3316910367
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3334378574
Short name T324
Test name
Test status
Simulation time 44377704 ps
CPU time 1.5 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 217196 kb
Host smart-2fd1aed9-8e8d-4fd1-b8a0-506fcbc2dce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334378574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3334378574
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.733935874
Short name T163
Test name
Test status
Simulation time 53170592 ps
CPU time 1.09 seconds
Started Aug 04 05:42:29 PM PDT 24
Finished Aug 04 05:42:30 PM PDT 24
Peak memory 218736 kb
Host smart-8e88e60d-1195-4ff8-9ac6-63710396bf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733935874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.733935874
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.1726161930
Short name T373
Test name
Test status
Simulation time 154891120 ps
CPU time 1.55 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218588 kb
Host smart-87264967-70a5-4f95-9287-39d7608ae74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726161930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1726161930
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1032018014
Short name T893
Test name
Test status
Simulation time 191432102 ps
CPU time 3.45 seconds
Started Aug 04 05:42:32 PM PDT 24
Finished Aug 04 05:42:36 PM PDT 24
Peak memory 220260 kb
Host smart-c18a7d14-9a43-4722-b5e4-106eb30f5ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032018014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1032018014
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.3857730942
Short name T662
Test name
Test status
Simulation time 25088771 ps
CPU time 1.33 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 219840 kb
Host smart-6f6103be-7f77-418e-a487-2e0e42235f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857730942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3857730942
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.603142205
Short name T743
Test name
Test status
Simulation time 73775845 ps
CPU time 1.19 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 219716 kb
Host smart-a330d448-d9f9-4535-a535-8a5205fae7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603142205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.603142205
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2000718088
Short name T759
Test name
Test status
Simulation time 72579259 ps
CPU time 1.09 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 218600 kb
Host smart-19095b5a-6c67-4b0b-a820-dc120e2fc1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000718088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2000718088
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.1632768623
Short name T686
Test name
Test status
Simulation time 82546729 ps
CPU time 1.09 seconds
Started Aug 04 05:42:34 PM PDT 24
Finished Aug 04 05:42:36 PM PDT 24
Peak memory 217296 kb
Host smart-a1a9e742-da2e-4ea0-93e3-fa6215f8957f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632768623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1632768623
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3888866387
Short name T197
Test name
Test status
Simulation time 44004597 ps
CPU time 1.11 seconds
Started Aug 04 05:41:06 PM PDT 24
Finished Aug 04 05:41:08 PM PDT 24
Peak memory 218604 kb
Host smart-48cdcee9-ecfe-40ec-be1a-67ea0e179e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888866387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3888866387
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.242330751
Short name T343
Test name
Test status
Simulation time 21188093 ps
CPU time 1.03 seconds
Started Aug 04 05:41:04 PM PDT 24
Finished Aug 04 05:41:05 PM PDT 24
Peak memory 206736 kb
Host smart-f10804a9-4b25-4c4b-a50a-ed35459ccd28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242330751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.242330751
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3859064820
Short name T813
Test name
Test status
Simulation time 45109253 ps
CPU time 0.79 seconds
Started Aug 04 05:41:08 PM PDT 24
Finished Aug 04 05:41:09 PM PDT 24
Peak memory 216168 kb
Host smart-6d6ecd00-46b7-4ba3-b681-0689914e33f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859064820 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3859064820
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1382001165
Short name T345
Test name
Test status
Simulation time 102021391 ps
CPU time 1.15 seconds
Started Aug 04 05:41:02 PM PDT 24
Finished Aug 04 05:41:03 PM PDT 24
Peak memory 216872 kb
Host smart-4d26068f-6757-4c03-97f7-5684e4de1b01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382001165 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1382001165
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3652518064
Short name T42
Test name
Test status
Simulation time 30772414 ps
CPU time 1.11 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 224236 kb
Host smart-b1fad77f-5a56-4ddb-b049-87982ced3310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652518064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3652518064
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.989741754
Short name T632
Test name
Test status
Simulation time 41305279 ps
CPU time 1.54 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:05 PM PDT 24
Peak memory 218716 kb
Host smart-e54e240c-7d23-4ef0-8d38-4ad114eb1076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989741754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.989741754
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.477474447
Short name T40
Test name
Test status
Simulation time 23107554 ps
CPU time 1.27 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 224072 kb
Host smart-91c2b0ca-64e6-45b2-87a0-ad278125cf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477474447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.477474447
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.536019083
Short name T748
Test name
Test status
Simulation time 22145853 ps
CPU time 0.93 seconds
Started Aug 04 05:41:10 PM PDT 24
Finished Aug 04 05:41:11 PM PDT 24
Peak memory 215304 kb
Host smart-3c4bd9ef-1b96-4328-8bf8-4a4f31ba1de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536019083 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.536019083
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3904368279
Short name T428
Test name
Test status
Simulation time 72885298 ps
CPU time 1.44 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 218752 kb
Host smart-8020d1cc-3eca-4395-82bc-5ba981fa2763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904368279 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3904368279
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3878107787
Short name T510
Test name
Test status
Simulation time 386609876825 ps
CPU time 2122.62 seconds
Started Aug 04 05:41:04 PM PDT 24
Finished Aug 04 06:16:27 PM PDT 24
Peak memory 226392 kb
Host smart-bec2f0df-59c7-4801-92f5-cadd34ccc93e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878107787 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3878107787
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.1672164769
Short name T506
Test name
Test status
Simulation time 129132970 ps
CPU time 1.26 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 218488 kb
Host smart-d1247cf0-2c5b-4b03-a6d9-c34b45f6037d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672164769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1672164769
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1265489551
Short name T661
Test name
Test status
Simulation time 59684907 ps
CPU time 1.24 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 219396 kb
Host smart-debafbfd-8155-42cb-85b2-0f6fb3fddf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265489551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1265489551
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1916992460
Short name T570
Test name
Test status
Simulation time 53409665 ps
CPU time 1.6 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 215312 kb
Host smart-ffb3bfd8-4209-4bae-ba5c-d3a09c90e6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916992460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1916992460
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.2530976795
Short name T168
Test name
Test status
Simulation time 80152672 ps
CPU time 1.25 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 220296 kb
Host smart-08786ea5-c9be-4251-866d-6db7d01a0e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530976795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2530976795
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.4241026405
Short name T278
Test name
Test status
Simulation time 88409623 ps
CPU time 1.26 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 218784 kb
Host smart-21ee4b4a-1102-48be-8e93-44e508e8331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241026405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.4241026405
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3987186543
Short name T858
Test name
Test status
Simulation time 43815613 ps
CPU time 1.24 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 218756 kb
Host smart-ebe2cb03-b971-4231-93e9-0872a02de6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987186543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3987186543
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1969617043
Short name T764
Test name
Test status
Simulation time 39363848 ps
CPU time 1.39 seconds
Started Aug 04 05:42:32 PM PDT 24
Finished Aug 04 05:42:34 PM PDT 24
Peak memory 218560 kb
Host smart-51d11781-b0dd-414f-b678-5744c0a9dafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969617043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1969617043
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.3709627744
Short name T181
Test name
Test status
Simulation time 234231296 ps
CPU time 1.16 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 220308 kb
Host smart-dfae9501-f9fd-4598-ada6-2fe864493ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709627744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3709627744
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3904300731
Short name T649
Test name
Test status
Simulation time 41855334 ps
CPU time 1.07 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 218552 kb
Host smart-1bcd202e-a88f-43fc-a1fc-cf7d2e1c1d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904300731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3904300731
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.4151879843
Short name T547
Test name
Test status
Simulation time 62556814 ps
CPU time 1.14 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 219244 kb
Host smart-cda1208d-8dbe-4f3e-9dd7-c17a921e574b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151879843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.4151879843
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.3067199344
Short name T720
Test name
Test status
Simulation time 50546254 ps
CPU time 1.58 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 219524 kb
Host smart-1af0f48d-af8e-4d8e-abc1-48cda73ed4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067199344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3067199344
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2032272763
Short name T205
Test name
Test status
Simulation time 24719951 ps
CPU time 1.13 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 218608 kb
Host smart-114f194f-b37e-4e46-84b3-3e193c5678f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032272763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2032272763
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.357470454
Short name T381
Test name
Test status
Simulation time 55934835 ps
CPU time 1.91 seconds
Started Aug 04 05:42:33 PM PDT 24
Finished Aug 04 05:42:35 PM PDT 24
Peak memory 218452 kb
Host smart-5d4d0cca-bb6d-4061-b11b-d0ce129f09be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357470454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.357470454
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.930790596
Short name T275
Test name
Test status
Simulation time 29058166 ps
CPU time 1.35 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 218516 kb
Host smart-80fceef8-3121-4b70-a462-0f17a692dd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930790596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.930790596
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.4269766032
Short name T536
Test name
Test status
Simulation time 102825613 ps
CPU time 1.42 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 218932 kb
Host smart-fb1340ce-cb0c-4076-a286-f7562cd8f651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269766032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.4269766032
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3653456739
Short name T465
Test name
Test status
Simulation time 26470217 ps
CPU time 1.14 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 218532 kb
Host smart-67242781-e9de-4afc-b8d1-a176d5d62081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653456739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3653456739
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3103582149
Short name T436
Test name
Test status
Simulation time 133421626 ps
CPU time 1.13 seconds
Started Aug 04 05:42:31 PM PDT 24
Finished Aug 04 05:42:33 PM PDT 24
Peak memory 217388 kb
Host smart-03d04cd6-1aa9-452d-b0bf-76b69fef4673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103582149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3103582149
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2155506651
Short name T464
Test name
Test status
Simulation time 31375199 ps
CPU time 1.1 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 219684 kb
Host smart-3218cfd2-a149-464f-81c5-366da4ab80ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155506651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2155506651
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert.805483113
Short name T478
Test name
Test status
Simulation time 42193756 ps
CPU time 1.25 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:08 PM PDT 24
Peak memory 220292 kb
Host smart-0ccae684-dfbc-4f66-af89-d512485ae1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805483113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.805483113
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2293993764
Short name T926
Test name
Test status
Simulation time 168502241 ps
CPU time 0.97 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:08 PM PDT 24
Peak memory 214952 kb
Host smart-f33f8b24-a3b3-4e55-ad89-3727bf1de313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293993764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2293993764
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2368253111
Short name T359
Test name
Test status
Simulation time 22963392 ps
CPU time 0.86 seconds
Started Aug 04 05:41:09 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 215928 kb
Host smart-c158cb8c-e515-4092-af91-d636880845d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368253111 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2368253111
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.1386914347
Short name T590
Test name
Test status
Simulation time 22311787 ps
CPU time 1.05 seconds
Started Aug 04 05:41:02 PM PDT 24
Finished Aug 04 05:41:03 PM PDT 24
Peak memory 219964 kb
Host smart-f2681c81-5cf8-4042-9f7f-09c914470fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386914347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1386914347
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.589259713
Short name T330
Test name
Test status
Simulation time 22903309 ps
CPU time 1.29 seconds
Started Aug 04 05:41:02 PM PDT 24
Finished Aug 04 05:41:03 PM PDT 24
Peak memory 218840 kb
Host smart-930491e1-9d54-4d2a-af89-fa9a9878202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589259713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.589259713
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2288047301
Short name T489
Test name
Test status
Simulation time 31803464 ps
CPU time 0.83 seconds
Started Aug 04 05:41:06 PM PDT 24
Finished Aug 04 05:41:07 PM PDT 24
Peak memory 215676 kb
Host smart-f425ed1f-8033-4a6c-a0a2-a6f1b386679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288047301 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2288047301
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2060148398
Short name T572
Test name
Test status
Simulation time 17669126 ps
CPU time 1.13 seconds
Started Aug 04 05:41:02 PM PDT 24
Finished Aug 04 05:41:03 PM PDT 24
Peak memory 215308 kb
Host smart-89b6f1fb-2d2f-4914-808f-afd00dd2546c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060148398 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2060148398
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3969909198
Short name T988
Test name
Test status
Simulation time 550706025 ps
CPU time 5.72 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:13 PM PDT 24
Peak memory 215312 kb
Host smart-d0e74f73-7e61-4807-b659-ac352b9726b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969909198 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3969909198
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3527342497
Short name T779
Test name
Test status
Simulation time 110811503672 ps
CPU time 1108.57 seconds
Started Aug 04 05:41:01 PM PDT 24
Finished Aug 04 05:59:30 PM PDT 24
Peak memory 223736 kb
Host smart-2b668123-954d-4268-b14d-ed44900d6a47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527342497 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3527342497
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.185917003
Short name T187
Test name
Test status
Simulation time 65446648 ps
CPU time 1.05 seconds
Started Aug 04 05:42:31 PM PDT 24
Finished Aug 04 05:42:32 PM PDT 24
Peak memory 219704 kb
Host smart-4fa805fa-5397-4a34-864c-21880946641f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185917003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.185917003
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1015190117
Short name T519
Test name
Test status
Simulation time 55588406 ps
CPU time 1.15 seconds
Started Aug 04 05:42:33 PM PDT 24
Finished Aug 04 05:42:34 PM PDT 24
Peak memory 215508 kb
Host smart-440d509a-aadf-4889-90d9-f450f855b163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015190117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1015190117
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.137894349
Short name T667
Test name
Test status
Simulation time 43066437 ps
CPU time 1.16 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 219572 kb
Host smart-7b124a0e-9164-4704-932c-49195611be2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137894349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.137894349
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.311609019
Short name T430
Test name
Test status
Simulation time 35268930 ps
CPU time 1.41 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 218696 kb
Host smart-e50bc721-a9af-456c-b356-4cbffabb815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311609019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.311609019
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3758222495
Short name T297
Test name
Test status
Simulation time 30084083 ps
CPU time 1.17 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 220708 kb
Host smart-2df92edf-e7f2-4a59-a67f-1c6ec8022808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758222495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3758222495
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.3305538356
Short name T340
Test name
Test status
Simulation time 76779719 ps
CPU time 2.67 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 220136 kb
Host smart-58648f5f-1a7f-4267-a42d-89af95d43f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305538356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3305538356
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1461564638
Short name T621
Test name
Test status
Simulation time 44908909 ps
CPU time 1.15 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 220100 kb
Host smart-7237b9ac-83d9-4d68-9016-64908d3e4200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461564638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1461564638
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.1730427599
Short name T932
Test name
Test status
Simulation time 94159530 ps
CPU time 1.38 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 220200 kb
Host smart-8ba5981b-cbc6-4f19-8e76-cd88463545d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730427599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1730427599
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.479913010
Short name T876
Test name
Test status
Simulation time 61101717 ps
CPU time 1.11 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218848 kb
Host smart-e0166400-38e0-4785-a4d3-f644ea9695c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479913010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.479913010
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.1786968062
Short name T943
Test name
Test status
Simulation time 75154946 ps
CPU time 1.16 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 218440 kb
Host smart-5ba96747-eae7-4548-bbc2-d4cb9440bbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786968062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1786968062
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2337580168
Short name T942
Test name
Test status
Simulation time 76191316 ps
CPU time 1.13 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 220140 kb
Host smart-2a43ae09-ffc9-4d1c-9810-3d34bf4913d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337580168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2337580168
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1282728138
Short name T482
Test name
Test status
Simulation time 77930196 ps
CPU time 1.2 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 217712 kb
Host smart-4ff531d9-ac45-4f39-9cd3-35dfdf3d3a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282728138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1282728138
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.3221647390
Short name T432
Test name
Test status
Simulation time 33744448 ps
CPU time 1.14 seconds
Started Aug 04 05:42:34 PM PDT 24
Finished Aug 04 05:42:35 PM PDT 24
Peak memory 219732 kb
Host smart-21f2f3fd-a4c2-4b60-b7a5-8cfb7ad93f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221647390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3221647390
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3368121981
Short name T683
Test name
Test status
Simulation time 154810408 ps
CPU time 1.73 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 220324 kb
Host smart-ba7ca3b0-bf7b-45a2-99b7-defb2d37a4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368121981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3368121981
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.928236676
Short name T189
Test name
Test status
Simulation time 22514196 ps
CPU time 1.13 seconds
Started Aug 04 05:42:45 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 218732 kb
Host smart-9a04f0c4-30a4-4fbc-8998-16e1d6483644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928236676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.928236676
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3813554118
Short name T775
Test name
Test status
Simulation time 44325439 ps
CPU time 1.3 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218504 kb
Host smart-bf29603d-20aa-4d51-9787-0e55c739914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813554118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3813554118
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.841208482
Short name T637
Test name
Test status
Simulation time 71435491 ps
CPU time 1.1 seconds
Started Aug 04 05:42:33 PM PDT 24
Finished Aug 04 05:42:35 PM PDT 24
Peak memory 218608 kb
Host smart-589266c7-10b9-4900-a771-cbfd57ecfc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841208482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.841208482
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3034626512
Short name T383
Test name
Test status
Simulation time 43222477 ps
CPU time 1.15 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 218512 kb
Host smart-fac58d50-f7ab-44a2-9f16-06a6f528f3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034626512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3034626512
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2422289231
Short name T470
Test name
Test status
Simulation time 91306038 ps
CPU time 1.18 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218516 kb
Host smart-0f226c13-6b10-4eeb-ae42-7490761118b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422289231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2422289231
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.3888986887
Short name T825
Test name
Test status
Simulation time 45847596 ps
CPU time 1.08 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 217416 kb
Host smart-738c49ae-d971-4be9-9ac1-252c825fd6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888986887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3888986887
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3859244572
Short name T986
Test name
Test status
Simulation time 76338574 ps
CPU time 1.21 seconds
Started Aug 04 05:41:06 PM PDT 24
Finished Aug 04 05:41:07 PM PDT 24
Peak memory 218748 kb
Host smart-8ce6f06f-f54e-4976-b611-43fdb3886061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859244572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3859244572
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.770839450
Short name T795
Test name
Test status
Simulation time 18692100 ps
CPU time 0.91 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:08 PM PDT 24
Peak memory 206736 kb
Host smart-b7b70fc2-be24-45d7-ae49-93b18dd2ac24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770839450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.770839450
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.4141620443
Short name T401
Test name
Test status
Simulation time 142005903 ps
CPU time 0.84 seconds
Started Aug 04 05:41:06 PM PDT 24
Finished Aug 04 05:41:07 PM PDT 24
Peak memory 216004 kb
Host smart-e33441ca-5c00-4eef-bc51-a17b1c729d7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141620443 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.4141620443
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.1571550467
Short name T979
Test name
Test status
Simulation time 20845305 ps
CPU time 1.17 seconds
Started Aug 04 05:41:06 PM PDT 24
Finished Aug 04 05:41:07 PM PDT 24
Peak memory 229636 kb
Host smart-0f7ba72a-f1c1-47d0-91a4-2a72b32c32be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571550467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1571550467
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2577286982
Short name T66
Test name
Test status
Simulation time 49065080 ps
CPU time 1.17 seconds
Started Aug 04 05:41:10 PM PDT 24
Finished Aug 04 05:41:11 PM PDT 24
Peak memory 217504 kb
Host smart-06d440c9-24a5-4d4e-9b01-efa79255e582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577286982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2577286982
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3069606057
Short name T116
Test name
Test status
Simulation time 27295003 ps
CPU time 0.94 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:08 PM PDT 24
Peak memory 215468 kb
Host smart-28a8f51f-a14a-40b0-92c6-9cbd7a9a41c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069606057 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3069606057
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1160555976
Short name T878
Test name
Test status
Simulation time 45953037 ps
CPU time 0.93 seconds
Started Aug 04 05:41:08 PM PDT 24
Finished Aug 04 05:41:09 PM PDT 24
Peak memory 215276 kb
Host smart-e990ee78-1bfb-4d43-99e2-a08f9fca0322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160555976 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1160555976
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.299160014
Short name T777
Test name
Test status
Simulation time 65775880 ps
CPU time 1.81 seconds
Started Aug 04 05:41:05 PM PDT 24
Finished Aug 04 05:41:06 PM PDT 24
Peak memory 217056 kb
Host smart-411de16a-ba81-4613-8dd6-6fbfb63cd611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299160014 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.299160014
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1610357742
Short name T20
Test name
Test status
Simulation time 13897587513 ps
CPU time 340.11 seconds
Started Aug 04 05:41:08 PM PDT 24
Finished Aug 04 05:46:48 PM PDT 24
Peak memory 217652 kb
Host smart-bd805c7f-bf75-4aa0-a312-8c042dcd9920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610357742 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1610357742
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2765134943
Short name T752
Test name
Test status
Simulation time 23366260 ps
CPU time 1.22 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 218912 kb
Host smart-bb02fc26-98df-48c6-87b7-3e7306c99824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765134943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2765134943
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.1182659519
Short name T451
Test name
Test status
Simulation time 52154818 ps
CPU time 1.67 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 217240 kb
Host smart-1c9030ff-6007-4a51-b8b3-9e132e5acc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182659519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1182659519
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.655806005
Short name T296
Test name
Test status
Simulation time 25975296 ps
CPU time 1.16 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 219940 kb
Host smart-a9e21030-f13d-4f27-86a3-fc73a1a9d6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655806005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.655806005
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2776813621
Short name T499
Test name
Test status
Simulation time 113625062 ps
CPU time 1.39 seconds
Started Aug 04 05:42:32 PM PDT 24
Finished Aug 04 05:42:34 PM PDT 24
Peak memory 218736 kb
Host smart-23019319-93f4-49d2-92b2-24db29ebdde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776813621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2776813621
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2674072757
Short name T162
Test name
Test status
Simulation time 71879245 ps
CPU time 1.11 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 218688 kb
Host smart-0732fa5a-3648-4bed-b995-35897f78bcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674072757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2674072757
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.561952262
Short name T865
Test name
Test status
Simulation time 69892563 ps
CPU time 1.22 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 218468 kb
Host smart-a3aabc49-01e4-4bcd-b188-96f535f1efa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561952262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.561952262
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.3075490241
Short name T995
Test name
Test status
Simulation time 46079507 ps
CPU time 1.15 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 219564 kb
Host smart-975ab3e7-fef2-476e-8060-bd07e9aefb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075490241 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.3075490241
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.882583860
Short name T656
Test name
Test status
Simulation time 43740303 ps
CPU time 1.43 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 218644 kb
Host smart-95715146-5559-4840-bb21-a7e3112aaa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882583860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.882583860
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.844415608
Short name T132
Test name
Test status
Simulation time 53111811 ps
CPU time 1.24 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 215692 kb
Host smart-33d090a2-281f-4ddf-b6c8-ba1ce271a87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844415608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.844415608
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2752262909
Short name T272
Test name
Test status
Simulation time 76555829 ps
CPU time 1.12 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 217456 kb
Host smart-b65459b9-ab18-40c1-bb63-f899f45bf10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752262909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2752262909
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.3722379108
Short name T525
Test name
Test status
Simulation time 80288484 ps
CPU time 1.04 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 218340 kb
Host smart-94913f51-8a0d-41e8-a2d7-819715717c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722379108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3722379108
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3521367789
Short name T426
Test name
Test status
Simulation time 67403355 ps
CPU time 1.46 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 218320 kb
Host smart-7a9fc99f-b75f-480a-ba01-cd89850ca032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521367789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3521367789
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1697965762
Short name T803
Test name
Test status
Simulation time 28621722 ps
CPU time 1.22 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 220756 kb
Host smart-ad83d371-f227-4f00-abc8-62ffe901649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697965762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1697965762
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3900151273
Short name T941
Test name
Test status
Simulation time 42959588 ps
CPU time 1.21 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 218720 kb
Host smart-85b67948-e746-47c6-a9e9-d99803515b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900151273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3900151273
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.513701542
Short name T460
Test name
Test status
Simulation time 28475359 ps
CPU time 1.47 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 220092 kb
Host smart-e54d8bf3-ea83-43c5-874b-0e51c0adfa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513701542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.513701542
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.4055065778
Short name T907
Test name
Test status
Simulation time 60593247 ps
CPU time 1.09 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:36 PM PDT 24
Peak memory 219604 kb
Host smart-4a5cb4c3-cfe1-4138-919c-74151a921de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055065778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4055065778
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.123235083
Short name T994
Test name
Test status
Simulation time 25025434 ps
CPU time 1.13 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 218492 kb
Host smart-4d15c37f-f2fa-4c0d-8659-c505a460aac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123235083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.123235083
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2844761318
Short name T306
Test name
Test status
Simulation time 49659964 ps
CPU time 1.34 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 218728 kb
Host smart-75674f7c-6074-452e-bdfb-346aab98a915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844761318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2844761318
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.3393573371
Short name T809
Test name
Test status
Simulation time 82840979 ps
CPU time 1.16 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 220316 kb
Host smart-91e632c8-f2ee-42a1-9e64-6f731fde6636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393573371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3393573371
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.4013606632
Short name T346
Test name
Test status
Simulation time 55511094 ps
CPU time 1.32 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 217540 kb
Host smart-2002743d-020b-40a1-8432-282a69032fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013606632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4013606632
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.833464207
Short name T51
Test name
Test status
Simulation time 54643216 ps
CPU time 1.23 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:40:46 PM PDT 24
Peak memory 218868 kb
Host smart-01a3bafd-3370-432e-b54d-52b68f1fd615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833464207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.833464207
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3374345305
Short name T723
Test name
Test status
Simulation time 34817498 ps
CPU time 0.92 seconds
Started Aug 04 05:40:41 PM PDT 24
Finished Aug 04 05:40:42 PM PDT 24
Peak memory 206780 kb
Host smart-42c83efb-c6ff-43a7-9ba7-8670ca920264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374345305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3374345305
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2729056825
Short name T528
Test name
Test status
Simulation time 35730563 ps
CPU time 0.88 seconds
Started Aug 04 05:40:44 PM PDT 24
Finished Aug 04 05:40:45 PM PDT 24
Peak memory 216236 kb
Host smart-ac091883-8886-430e-a420-8b7d133738a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729056825 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2729056825
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2008482919
Short name T114
Test name
Test status
Simulation time 195595244 ps
CPU time 1.39 seconds
Started Aug 04 05:40:41 PM PDT 24
Finished Aug 04 05:40:43 PM PDT 24
Peak memory 216892 kb
Host smart-c1385473-922e-45df-af65-5fa42497448f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008482919 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2008482919
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.715290260
Short name T540
Test name
Test status
Simulation time 36036729 ps
CPU time 1.03 seconds
Started Aug 04 05:40:41 PM PDT 24
Finished Aug 04 05:40:42 PM PDT 24
Peak memory 218624 kb
Host smart-f84e2e88-86d0-4e15-b4ce-8dfdde1e3a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715290260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.715290260
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3694729123
Short name T691
Test name
Test status
Simulation time 45995537 ps
CPU time 1.13 seconds
Started Aug 04 05:40:56 PM PDT 24
Finished Aug 04 05:40:58 PM PDT 24
Peak memory 220220 kb
Host smart-8cf86539-aaee-4c54-b911-3ff034b5a274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694729123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3694729123
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2609038971
Short name T556
Test name
Test status
Simulation time 26625141 ps
CPU time 1.05 seconds
Started Aug 04 05:40:48 PM PDT 24
Finished Aug 04 05:40:50 PM PDT 24
Peak memory 224080 kb
Host smart-35cc81e3-cfef-401d-be65-b745f53a0749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609038971 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2609038971
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3360147862
Short name T70
Test name
Test status
Simulation time 28058752 ps
CPU time 0.97 seconds
Started Aug 04 05:40:49 PM PDT 24
Finished Aug 04 05:40:51 PM PDT 24
Peak memory 207076 kb
Host smart-43e98185-6206-479e-8728-e140cb59f5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360147862 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3360147862
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.2396851250
Short name T471
Test name
Test status
Simulation time 24667286 ps
CPU time 0.9 seconds
Started Aug 04 05:40:51 PM PDT 24
Finished Aug 04 05:40:52 PM PDT 24
Peak memory 215284 kb
Host smart-5687f4d5-b3d2-409f-af48-363be2d9e1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396851250 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2396851250
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1175410112
Short name T800
Test name
Test status
Simulation time 670689678 ps
CPU time 4.58 seconds
Started Aug 04 05:40:53 PM PDT 24
Finished Aug 04 05:40:58 PM PDT 24
Peak memory 218524 kb
Host smart-d84e8a7b-00b6-4621-bc27-69e1e13c6e05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175410112 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1175410112
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1313802555
Short name T784
Test name
Test status
Simulation time 195359599914 ps
CPU time 1078.16 seconds
Started Aug 04 05:40:52 PM PDT 24
Finished Aug 04 05:58:51 PM PDT 24
Peak memory 223060 kb
Host smart-5fa12641-da4f-4374-8ff7-f464aa6d0b1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313802555 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1313802555
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2714990461
Short name T904
Test name
Test status
Simulation time 26977531 ps
CPU time 1.22 seconds
Started Aug 04 05:41:09 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 218488 kb
Host smart-1144c9fa-5780-4fbb-a106-62a0ca6d1b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714990461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2714990461
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1977013938
Short name T674
Test name
Test status
Simulation time 66076749 ps
CPU time 0.98 seconds
Started Aug 04 05:41:09 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 206828 kb
Host smart-445fc60f-722a-492b-a965-41c3723b7e2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977013938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1977013938
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.577137832
Short name T408
Test name
Test status
Simulation time 38504609 ps
CPU time 0.85 seconds
Started Aug 04 05:41:08 PM PDT 24
Finished Aug 04 05:41:08 PM PDT 24
Peak memory 215932 kb
Host smart-09a009e2-81a9-42b3-a41e-5b591cbf3282
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577137832 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.577137832
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.394575908
Short name T838
Test name
Test status
Simulation time 41845939 ps
CPU time 1.28 seconds
Started Aug 04 05:41:06 PM PDT 24
Finished Aug 04 05:41:08 PM PDT 24
Peak memory 217092 kb
Host smart-b478ec75-6a39-47a5-9831-65338f36fc0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394575908 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.394575908
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2929648161
Short name T472
Test name
Test status
Simulation time 20561120 ps
CPU time 0.99 seconds
Started Aug 04 05:41:08 PM PDT 24
Finished Aug 04 05:41:09 PM PDT 24
Peak memory 218356 kb
Host smart-89e19b92-c3f0-47b1-ab4d-3d945486365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929648161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2929648161
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2401258299
Short name T751
Test name
Test status
Simulation time 102960916 ps
CPU time 1.17 seconds
Started Aug 04 05:41:08 PM PDT 24
Finished Aug 04 05:41:09 PM PDT 24
Peak memory 217436 kb
Host smart-3221ca65-78bd-42ab-9160-8a83774b2b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401258299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2401258299
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.241728410
Short name T872
Test name
Test status
Simulation time 21557220 ps
CPU time 1.03 seconds
Started Aug 04 05:41:05 PM PDT 24
Finished Aug 04 05:41:06 PM PDT 24
Peak memory 215856 kb
Host smart-896c96a0-5db4-411d-9bca-9a07f7fdfd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241728410 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.241728410
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.4079187693
Short name T694
Test name
Test status
Simulation time 19481329 ps
CPU time 0.98 seconds
Started Aug 04 05:41:08 PM PDT 24
Finished Aug 04 05:41:09 PM PDT 24
Peak memory 215300 kb
Host smart-180d6938-8826-4426-a29e-a7eaf05b630b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079187693 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.4079187693
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2822208625
Short name T918
Test name
Test status
Simulation time 470316070 ps
CPU time 3.13 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:16 PM PDT 24
Peak memory 215364 kb
Host smart-86d95d77-c46b-415b-b411-0d76bc407e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822208625 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2822208625
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.717979241
Short name T228
Test name
Test status
Simulation time 23675045064 ps
CPU time 547.34 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:50:20 PM PDT 24
Peak memory 218272 kb
Host smart-289baa71-7707-4cad-ac63-d1fefa4fba0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717979241 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.717979241
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3336406682
Short name T760
Test name
Test status
Simulation time 25648452 ps
CPU time 1.14 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 217196 kb
Host smart-d4488c1e-00e4-4e73-90fc-43416ecd7859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336406682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3336406682
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3705300513
Short name T405
Test name
Test status
Simulation time 49846454 ps
CPU time 1.84 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 215372 kb
Host smart-c42ed53c-5877-436a-80f7-c24d70871baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705300513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3705300513
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3182462403
Short name T314
Test name
Test status
Simulation time 94215739 ps
CPU time 1.22 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 218708 kb
Host smart-03b685c5-bdc2-445d-af76-4d58f01be75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182462403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3182462403
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1670099848
Short name T966
Test name
Test status
Simulation time 90969056 ps
CPU time 1.93 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 218784 kb
Host smart-27be5750-874a-4c8f-89b2-2b66b2504cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670099848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1670099848
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1081528190
Short name T657
Test name
Test status
Simulation time 151112185 ps
CPU time 3.11 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 217700 kb
Host smart-49c5e159-f0fb-40aa-840b-0c58fcd11ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081528190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1081528190
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3673862963
Short name T730
Test name
Test status
Simulation time 49797926 ps
CPU time 1.63 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 218572 kb
Host smart-0c4573fc-ac68-43ea-9491-a72baf86264d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673862963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3673862963
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3017675311
Short name T495
Test name
Test status
Simulation time 121058670 ps
CPU time 1.47 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 219876 kb
Host smart-bcd8579f-2f8d-4aea-83b3-930004015c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017675311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3017675311
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2525290915
Short name T431
Test name
Test status
Simulation time 31421047 ps
CPU time 1.16 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 217624 kb
Host smart-ba12cff2-b319-4c8b-ba3d-28fdbc088863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525290915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2525290915
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2934228703
Short name T583
Test name
Test status
Simulation time 47207621 ps
CPU time 1.29 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 220156 kb
Host smart-f271dbb5-e553-4474-9a60-868962a0e1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934228703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2934228703
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.4244591679
Short name T924
Test name
Test status
Simulation time 53851105 ps
CPU time 0.95 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 217364 kb
Host smart-ebd2a0ea-d14f-4ee8-bcb4-27ee588281df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244591679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.4244591679
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2027414464
Short name T690
Test name
Test status
Simulation time 71165150 ps
CPU time 1.14 seconds
Started Aug 04 05:41:10 PM PDT 24
Finished Aug 04 05:41:11 PM PDT 24
Peak memory 218856 kb
Host smart-fd5c908c-58da-41d0-956d-adfa0f5099ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027414464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2027414464
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.4013755737
Short name T375
Test name
Test status
Simulation time 16924961 ps
CPU time 0.95 seconds
Started Aug 04 05:41:09 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 206724 kb
Host smart-db43dfb6-b977-423c-ac60-b799085eeda1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013755737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.4013755737
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2266555542
Short name T194
Test name
Test status
Simulation time 21193553 ps
CPU time 0.9 seconds
Started Aug 04 05:41:09 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 216240 kb
Host smart-b474c345-c72a-4bb7-bc81-0b71d956b6d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266555542 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2266555542
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.904902022
Short name T776
Test name
Test status
Simulation time 85138629 ps
CPU time 1.16 seconds
Started Aug 04 05:41:12 PM PDT 24
Finished Aug 04 05:41:13 PM PDT 24
Peak memory 219808 kb
Host smart-bb3ef8fc-f259-466c-9443-ebe1e376c1f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904902022 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.904902022
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.611577030
Short name T912
Test name
Test status
Simulation time 22939171 ps
CPU time 1.14 seconds
Started Aug 04 05:41:13 PM PDT 24
Finished Aug 04 05:41:14 PM PDT 24
Peak memory 218536 kb
Host smart-cbb87aa1-3833-4191-83de-9e52295e9ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611577030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.611577030
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.583355727
Short name T366
Test name
Test status
Simulation time 41049856 ps
CPU time 1.43 seconds
Started Aug 04 05:41:08 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 218652 kb
Host smart-02b9c59a-bb68-4d66-9f13-53ebcbc0bf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583355727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.583355727
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_smoke.354014626
Short name T902
Test name
Test status
Simulation time 46994483 ps
CPU time 0.95 seconds
Started Aug 04 05:41:09 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 215292 kb
Host smart-d357e621-ccca-455e-ba71-637fb97b6905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354014626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.354014626
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2783948215
Short name T239
Test name
Test status
Simulation time 801643954 ps
CPU time 5.49 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:13 PM PDT 24
Peak memory 217208 kb
Host smart-5a773601-50fc-4568-aa82-40135c093d49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783948215 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2783948215
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.386218266
Short name T952
Test name
Test status
Simulation time 124076104240 ps
CPU time 776.01 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:54:03 PM PDT 24
Peak memory 223696 kb
Host smart-7409c59e-75a3-4ffe-9cf9-ac7b07dc6f41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386218266 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.386218266
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2309352809
Short name T908
Test name
Test status
Simulation time 64738538 ps
CPU time 1.62 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 218552 kb
Host smart-d2969494-260d-471e-b22d-aa3f41ffcf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309352809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2309352809
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.119773602
Short name T962
Test name
Test status
Simulation time 52750842 ps
CPU time 1.21 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 219884 kb
Host smart-b0d3067e-02d8-4f9d-b8e5-c34b787552e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119773602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.119773602
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3863592001
Short name T521
Test name
Test status
Simulation time 45210327 ps
CPU time 1.4 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218452 kb
Host smart-700c60be-9717-43bf-8ebd-afe0ff4162bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863592001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3863592001
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.4179396857
Short name T684
Test name
Test status
Simulation time 51099810 ps
CPU time 1.3 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218372 kb
Host smart-d2fcc9ba-bbcc-4eb9-8379-bdbc7d9506a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179396857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4179396857
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2186987912
Short name T863
Test name
Test status
Simulation time 102488820 ps
CPU time 1.44 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 219196 kb
Host smart-3651bb16-434b-4d35-9dcc-fe245cd1e058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186987912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2186987912
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3923489828
Short name T312
Test name
Test status
Simulation time 79651585 ps
CPU time 0.99 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 217216 kb
Host smart-6b62ae88-bfa5-4d0d-b296-4bd37ab3b966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923489828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3923489828
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2104800431
Short name T339
Test name
Test status
Simulation time 96419797 ps
CPU time 1.3 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 220076 kb
Host smart-2f842a51-b84d-445c-8ab6-87ef9ea512de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104800431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2104800431
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2319026437
Short name T919
Test name
Test status
Simulation time 37308915 ps
CPU time 1.23 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 218300 kb
Host smart-09e8f984-19df-421c-a12c-9e92359e12d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319026437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2319026437
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.436424146
Short name T873
Test name
Test status
Simulation time 79534122 ps
CPU time 1.04 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 219744 kb
Host smart-e97900c1-fed7-49b4-8c85-2efc22d7845d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436424146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.436424146
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.98332906
Short name T774
Test name
Test status
Simulation time 36601871 ps
CPU time 1.2 seconds
Started Aug 04 05:41:10 PM PDT 24
Finished Aug 04 05:41:12 PM PDT 24
Peak memory 219680 kb
Host smart-a807fd75-35bd-4a02-a82a-486758de32eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98332906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.98332906
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.994066483
Short name T452
Test name
Test status
Simulation time 39353565 ps
CPU time 0.84 seconds
Started Aug 04 05:41:09 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 206780 kb
Host smart-ded2a336-c0ed-467f-ac0f-bf94395058cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994066483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.994066483
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.4012760003
Short name T201
Test name
Test status
Simulation time 23109544 ps
CPU time 0.82 seconds
Started Aug 04 05:41:09 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 216320 kb
Host smart-5cd94de7-9649-42f7-8f2a-bc90b6a73b5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012760003 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.4012760003
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.3164445671
Short name T209
Test name
Test status
Simulation time 52157567 ps
CPU time 0.84 seconds
Started Aug 04 05:41:09 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 219020 kb
Host smart-e34b3bd7-be12-4b6c-8abc-101529c832c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164445671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3164445671
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3961084830
Short name T533
Test name
Test status
Simulation time 201612020 ps
CPU time 2.82 seconds
Started Aug 04 05:41:12 PM PDT 24
Finished Aug 04 05:41:14 PM PDT 24
Peak memory 220208 kb
Host smart-60306ec2-2d1c-463c-9f87-eb41172fbb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961084830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3961084830
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2738959926
Short name T82
Test name
Test status
Simulation time 22540172 ps
CPU time 1.07 seconds
Started Aug 04 05:41:10 PM PDT 24
Finished Aug 04 05:41:11 PM PDT 24
Peak memory 215876 kb
Host smart-40b8119d-8e6f-4d1b-9255-9a7ee102fb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738959926 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2738959926
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.112224939
Short name T789
Test name
Test status
Simulation time 28354154 ps
CPU time 0.94 seconds
Started Aug 04 05:41:09 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 215244 kb
Host smart-c698c12d-234a-4113-85e6-f63097ed88cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112224939 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.112224939
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4202100547
Short name T501
Test name
Test status
Simulation time 121502623 ps
CPU time 2.72 seconds
Started Aug 04 05:41:14 PM PDT 24
Finished Aug 04 05:41:17 PM PDT 24
Peak memory 217348 kb
Host smart-e46bb682-e870-4067-a11f-863e059171cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202100547 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4202100547
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.840267257
Short name T702
Test name
Test status
Simulation time 108135466852 ps
CPU time 1246.23 seconds
Started Aug 04 05:41:09 PM PDT 24
Finished Aug 04 06:01:56 PM PDT 24
Peak memory 222776 kb
Host smart-9f48af43-d033-448b-b76b-e65b17ce5223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840267257 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.840267257
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1080474072
Short name T595
Test name
Test status
Simulation time 52635267 ps
CPU time 1.56 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 218180 kb
Host smart-2bc5bb40-17df-4c5e-bb83-522c112bfd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080474072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1080474072
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3851132283
Short name T802
Test name
Test status
Simulation time 50895739 ps
CPU time 1.24 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 218664 kb
Host smart-26db6e51-7137-4d99-b6e3-e1ef9d0bf9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851132283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3851132283
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1604542646
Short name T846
Test name
Test status
Simulation time 263576858 ps
CPU time 3.07 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:45 PM PDT 24
Peak memory 219896 kb
Host smart-14597293-6b57-4421-916f-a2d4d4ec5c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604542646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1604542646
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.172601754
Short name T848
Test name
Test status
Simulation time 113308547 ps
CPU time 1.4 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 217296 kb
Host smart-4ffeb8b5-b767-49c5-873c-76aae1df8b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172601754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.172601754
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2518295489
Short name T697
Test name
Test status
Simulation time 47460956 ps
CPU time 1.83 seconds
Started Aug 04 05:42:43 PM PDT 24
Finished Aug 04 05:42:45 PM PDT 24
Peak memory 218724 kb
Host smart-591474a3-1bbe-4d18-b818-f5355c083e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518295489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2518295489
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2548434297
Short name T883
Test name
Test status
Simulation time 550102369 ps
CPU time 3.68 seconds
Started Aug 04 05:42:43 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 220620 kb
Host smart-9047443a-9b9f-4e33-a95f-c9f7bd58fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548434297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2548434297
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1066873222
Short name T698
Test name
Test status
Simulation time 39971376 ps
CPU time 1.14 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 215332 kb
Host smart-2e263127-9eae-430a-a0ad-86ae06be2d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066873222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1066873222
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1689905315
Short name T605
Test name
Test status
Simulation time 94056945 ps
CPU time 1.21 seconds
Started Aug 04 05:42:43 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 217320 kb
Host smart-e9cfa4e3-4bbf-40c3-b71c-d383e10010d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689905315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1689905315
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2882861514
Short name T237
Test name
Test status
Simulation time 64660023 ps
CPU time 1.24 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 215320 kb
Host smart-d4ff2ccf-4f33-4129-9928-c8aa4db5241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882861514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2882861514
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3425120195
Short name T28
Test name
Test status
Simulation time 93591043 ps
CPU time 3.37 seconds
Started Aug 04 05:42:43 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 220324 kb
Host smart-918666ef-5fa8-45b5-b7c6-afc51bf4d5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425120195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3425120195
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1976678960
Short name T448
Test name
Test status
Simulation time 38427244 ps
CPU time 1.14 seconds
Started Aug 04 05:41:10 PM PDT 24
Finished Aug 04 05:41:12 PM PDT 24
Peak memory 220036 kb
Host smart-45b42c38-b6a6-4216-9667-b2d5840c6df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976678960 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1976678960
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3141822290
Short name T658
Test name
Test status
Simulation time 49489138 ps
CPU time 0.92 seconds
Started Aug 04 05:41:15 PM PDT 24
Finished Aug 04 05:41:15 PM PDT 24
Peak memory 206744 kb
Host smart-f1ad30e0-1033-461e-a5e3-e70ddc10c4a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141822290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3141822290
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.4090309474
Short name T750
Test name
Test status
Simulation time 10322466 ps
CPU time 0.88 seconds
Started Aug 04 05:41:19 PM PDT 24
Finished Aug 04 05:41:20 PM PDT 24
Peak memory 216196 kb
Host smart-b149e4f3-b8ad-4516-9f33-1c966e846f7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090309474 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.4090309474
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3442118556
Short name T653
Test name
Test status
Simulation time 173983915 ps
CPU time 1.14 seconds
Started Aug 04 05:41:22 PM PDT 24
Finished Aug 04 05:41:23 PM PDT 24
Peak memory 217020 kb
Host smart-73b6f6fc-a850-437a-9881-a85d16bd0abb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442118556 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3442118556
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.4058406959
Short name T977
Test name
Test status
Simulation time 36028885 ps
CPU time 0.89 seconds
Started Aug 04 05:41:18 PM PDT 24
Finished Aug 04 05:41:19 PM PDT 24
Peak memory 218432 kb
Host smart-c5821422-e710-48fc-9fc9-b166b335be41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058406959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.4058406959
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.4214565917
Short name T473
Test name
Test status
Simulation time 63527273 ps
CPU time 1.34 seconds
Started Aug 04 05:41:10 PM PDT 24
Finished Aug 04 05:41:11 PM PDT 24
Peak memory 217212 kb
Host smart-021f56fe-ed8f-45e4-9696-b96f4355da2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214565917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4214565917
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1275222695
Short name T14
Test name
Test status
Simulation time 37043140 ps
CPU time 0.98 seconds
Started Aug 04 05:41:08 PM PDT 24
Finished Aug 04 05:41:09 PM PDT 24
Peak memory 223924 kb
Host smart-96068a18-016f-4358-8a52-b69d5fc3c248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275222695 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1275222695
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3244634754
Short name T710
Test name
Test status
Simulation time 19772573 ps
CPU time 0.99 seconds
Started Aug 04 05:41:08 PM PDT 24
Finished Aug 04 05:41:09 PM PDT 24
Peak memory 215284 kb
Host smart-81cb5328-1a29-4f15-8a4d-5c0fb364d783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244634754 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3244634754
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.738324049
Short name T242
Test name
Test status
Simulation time 99454850 ps
CPU time 2.4 seconds
Started Aug 04 05:41:10 PM PDT 24
Finished Aug 04 05:41:12 PM PDT 24
Peak memory 217344 kb
Host smart-0e64d8d6-69de-46d6-b3be-99aebcf5a0d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738324049 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.738324049
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2726823751
Short name T425
Test name
Test status
Simulation time 5536096785 ps
CPU time 71.1 seconds
Started Aug 04 05:41:11 PM PDT 24
Finished Aug 04 05:42:23 PM PDT 24
Peak memory 218416 kb
Host smart-96109069-3108-4f78-8549-5fdb50a9696b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726823751 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2726823751
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1271661853
Short name T906
Test name
Test status
Simulation time 45690516 ps
CPU time 1.02 seconds
Started Aug 04 05:42:43 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 217268 kb
Host smart-66beef9e-d2e2-4f38-8314-66ac58c23d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271661853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1271661853
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.117576244
Short name T976
Test name
Test status
Simulation time 57811934 ps
CPU time 1.09 seconds
Started Aug 04 05:42:45 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 217140 kb
Host smart-5c1fc20a-5552-4796-8c99-63ce6f83d7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117576244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.117576244
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.612409949
Short name T378
Test name
Test status
Simulation time 63894035 ps
CPU time 1.1 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 217252 kb
Host smart-112d5db9-a748-43f0-a409-ef4c3c454334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612409949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.612409949
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1204758896
Short name T492
Test name
Test status
Simulation time 61752427 ps
CPU time 1.57 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 218700 kb
Host smart-ecd4544c-fa51-4140-95f5-4aa0849d56c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204758896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1204758896
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1446842099
Short name T415
Test name
Test status
Simulation time 37834259 ps
CPU time 1.43 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 219836 kb
Host smart-3279d03e-be73-4003-8ff7-730f485116a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446842099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1446842099
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1764872053
Short name T978
Test name
Test status
Simulation time 42609670 ps
CPU time 1.36 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 217272 kb
Host smart-f6ab8964-48a3-479d-ab9c-e67164329696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764872053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1764872053
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2097147518
Short name T61
Test name
Test status
Simulation time 48636991 ps
CPU time 1.61 seconds
Started Aug 04 05:42:46 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 217256 kb
Host smart-d4635b4c-0402-4aa7-b3ff-a32c5048b5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097147518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2097147518
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2723010668
Short name T741
Test name
Test status
Simulation time 31786097 ps
CPU time 1.28 seconds
Started Aug 04 05:42:43 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 219736 kb
Host smart-e260d75a-2fc9-47dc-b136-83c22af24be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723010668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2723010668
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2673140484
Short name T635
Test name
Test status
Simulation time 111135212 ps
CPU time 1.63 seconds
Started Aug 04 05:42:43 PM PDT 24
Finished Aug 04 05:42:45 PM PDT 24
Peak memory 218924 kb
Host smart-e20bcf67-4aa0-413d-92a3-603a339fa8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673140484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2673140484
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2503455489
Short name T352
Test name
Test status
Simulation time 126327852 ps
CPU time 1.11 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 217160 kb
Host smart-edeff53b-9d49-411e-94af-4d656f8f48e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503455489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2503455489
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2062455471
Short name T947
Test name
Test status
Simulation time 28986111 ps
CPU time 1.27 seconds
Started Aug 04 05:41:18 PM PDT 24
Finished Aug 04 05:41:19 PM PDT 24
Peak memory 215696 kb
Host smart-d1ed6b50-d939-42cd-b74b-4d57c4a6bc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062455471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2062455471
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3669664781
Short name T49
Test name
Test status
Simulation time 57604921 ps
CPU time 0.86 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 206728 kb
Host smart-1f122b5d-f097-4480-84a0-e50d0b7847d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669664781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3669664781
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1405536232
Short name T721
Test name
Test status
Simulation time 20709490 ps
CPU time 0.89 seconds
Started Aug 04 05:41:35 PM PDT 24
Finished Aug 04 05:41:36 PM PDT 24
Peak memory 216220 kb
Host smart-b616f1a2-832d-4e75-bfce-3e88ed6fabdf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405536232 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1405536232
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3139175507
Short name T598
Test name
Test status
Simulation time 62099963 ps
CPU time 1.22 seconds
Started Aug 04 05:41:30 PM PDT 24
Finished Aug 04 05:41:31 PM PDT 24
Peak memory 217004 kb
Host smart-6e9bb064-f597-4489-ad51-1df53d4b5dc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139175507 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3139175507
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.607089107
Short name T210
Test name
Test status
Simulation time 19696326 ps
CPU time 1.22 seconds
Started Aug 04 05:41:37 PM PDT 24
Finished Aug 04 05:41:39 PM PDT 24
Peak memory 229564 kb
Host smart-009c4560-2eb5-41de-94e2-ce2576a1fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607089107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.607089107
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.3377144753
Short name T842
Test name
Test status
Simulation time 33937651 ps
CPU time 0.93 seconds
Started Aug 04 05:41:20 PM PDT 24
Finished Aug 04 05:41:21 PM PDT 24
Peak memory 215332 kb
Host smart-0f5b1bd0-4d2e-4a8a-a4c6-48f93d48edba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377144753 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3377144753
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1182046965
Short name T50
Test name
Test status
Simulation time 41861556 ps
CPU time 0.87 seconds
Started Aug 04 05:41:18 PM PDT 24
Finished Aug 04 05:41:19 PM PDT 24
Peak memory 215288 kb
Host smart-a39f5b0d-9fec-4b6e-bd8c-ea0b863522fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182046965 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1182046965
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2255923808
Short name T387
Test name
Test status
Simulation time 115748831 ps
CPU time 1.15 seconds
Started Aug 04 05:41:31 PM PDT 24
Finished Aug 04 05:41:32 PM PDT 24
Peak memory 206912 kb
Host smart-95ee5b70-f54f-433c-9ccc-0bf768126d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255923808 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2255923808
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2918601497
Short name T121
Test name
Test status
Simulation time 150280598399 ps
CPU time 861.65 seconds
Started Aug 04 05:41:16 PM PDT 24
Finished Aug 04 05:55:38 PM PDT 24
Peak memory 220960 kb
Host smart-23f49e0b-cf15-4512-9d7e-1bee959ef2cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918601497 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2918601497
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1301500738
Short name T799
Test name
Test status
Simulation time 47203538 ps
CPU time 1.16 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:45 PM PDT 24
Peak memory 218560 kb
Host smart-68078553-dc83-41dd-a5a0-252cf9eb9b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301500738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1301500738
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1778143807
Short name T313
Test name
Test status
Simulation time 46505123 ps
CPU time 1.48 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 218484 kb
Host smart-84e573f5-821e-4a29-ba30-a83cb638b5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778143807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1778143807
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2244794091
Short name T353
Test name
Test status
Simulation time 74581165 ps
CPU time 1.23 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:45 PM PDT 24
Peak memory 215400 kb
Host smart-cf2d8ed8-1aa6-4490-82b5-0a7dbdadf0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244794091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2244794091
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3758197103
Short name T456
Test name
Test status
Simulation time 31171005 ps
CPU time 1.35 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 218432 kb
Host smart-908d15f6-6e6f-4a95-9480-6148b1e52601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758197103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3758197103
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.4166359109
Short name T466
Test name
Test status
Simulation time 55290553 ps
CPU time 1.63 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 218616 kb
Host smart-35fac142-4391-4de7-8365-6906ab834be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166359109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.4166359109
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.330659265
Short name T424
Test name
Test status
Simulation time 52688162 ps
CPU time 1.25 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 215400 kb
Host smart-2acba4c1-54ff-48fe-a3cf-4ee98852a3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330659265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.330659265
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.836433896
Short name T599
Test name
Test status
Simulation time 61368341 ps
CPU time 1.25 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 219620 kb
Host smart-d8b3b8af-14f7-41e0-8d24-6b444ab53da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836433896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.836433896
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1202278663
Short name T571
Test name
Test status
Simulation time 59927762 ps
CPU time 1.43 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 218660 kb
Host smart-794a185d-d491-4ed0-9076-f56f0cccfde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202278663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1202278663
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3998418237
Short name T735
Test name
Test status
Simulation time 30697538 ps
CPU time 1.23 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 218648 kb
Host smart-b8230253-69f4-4540-9935-455e7b4477f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998418237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3998418237
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.4006152890
Short name T406
Test name
Test status
Simulation time 50477118 ps
CPU time 1.25 seconds
Started Aug 04 05:42:38 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 218776 kb
Host smart-abf5d4d2-53fd-4e2b-b50c-855ec2f88a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006152890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.4006152890
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.776240011
Short name T961
Test name
Test status
Simulation time 33938358 ps
CPU time 1.05 seconds
Started Aug 04 05:41:37 PM PDT 24
Finished Aug 04 05:41:38 PM PDT 24
Peak memory 219992 kb
Host smart-bc6efc74-94a6-4fb1-b8d3-8fbd7fdbb05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776240011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.776240011
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.87762144
Short name T362
Test name
Test status
Simulation time 25902296 ps
CPU time 0.8 seconds
Started Aug 04 05:41:18 PM PDT 24
Finished Aug 04 05:41:18 PM PDT 24
Peak memory 206772 kb
Host smart-12983b2a-b6c1-4ea6-99c3-f21bf7744f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87762144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.87762144
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2194528640
Short name T860
Test name
Test status
Simulation time 13725639 ps
CPU time 0.91 seconds
Started Aug 04 05:41:26 PM PDT 24
Finished Aug 04 05:41:27 PM PDT 24
Peak memory 216484 kb
Host smart-942c7260-ca80-42fb-bfab-3244cfc26003
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194528640 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2194528640
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3117540747
Short name T78
Test name
Test status
Simulation time 45395313 ps
CPU time 1.4 seconds
Started Aug 04 05:41:35 PM PDT 24
Finished Aug 04 05:41:37 PM PDT 24
Peak memory 216944 kb
Host smart-a85f38fb-5534-4edb-a10b-eba14986ac3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117540747 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3117540747
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2397132303
Short name T43
Test name
Test status
Simulation time 35012960 ps
CPU time 1.15 seconds
Started Aug 04 05:41:18 PM PDT 24
Finished Aug 04 05:41:19 PM PDT 24
Peak memory 229620 kb
Host smart-0c0c7a36-e1bf-4000-a80f-96aa56d87db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397132303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2397132303
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3612163208
Short name T778
Test name
Test status
Simulation time 73276343 ps
CPU time 1.22 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 219800 kb
Host smart-fd2bf5c9-5881-4c50-a869-1182a205d1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612163208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3612163208
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2880188265
Short name T38
Test name
Test status
Simulation time 24133957 ps
CPU time 1.18 seconds
Started Aug 04 05:41:31 PM PDT 24
Finished Aug 04 05:41:32 PM PDT 24
Peak memory 224076 kb
Host smart-dc8827ad-afe7-4795-a6f5-547662dd3f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880188265 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2880188265
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3403968774
Short name T692
Test name
Test status
Simulation time 37454335 ps
CPU time 0.87 seconds
Started Aug 04 05:41:14 PM PDT 24
Finished Aug 04 05:41:15 PM PDT 24
Peak memory 215276 kb
Host smart-70db9229-5391-4b0c-b859-2896ec414c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403968774 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3403968774
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1400807674
Short name T240
Test name
Test status
Simulation time 168238819 ps
CPU time 3.73 seconds
Started Aug 04 05:41:34 PM PDT 24
Finished Aug 04 05:41:38 PM PDT 24
Peak memory 215372 kb
Host smart-3c09441b-51b4-41d7-9c21-0881406603aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400807674 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1400807674
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3464931516
Short name T446
Test name
Test status
Simulation time 168429225708 ps
CPU time 1053.73 seconds
Started Aug 04 05:41:16 PM PDT 24
Finished Aug 04 05:58:49 PM PDT 24
Peak memory 221388 kb
Host smart-1cca4394-87e7-4574-85f0-e3ec5b8e416c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464931516 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3464931516
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.163517295
Short name T892
Test name
Test status
Simulation time 59705271 ps
CPU time 1.07 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218696 kb
Host smart-889e0411-bf30-4255-8da3-45b7739d22ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163517295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.163517295
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.33021785
Short name T543
Test name
Test status
Simulation time 109729594 ps
CPU time 1.23 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 215320 kb
Host smart-965ace62-e9a2-45f5-a31b-ab3a36f9b2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33021785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.33021785
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.4077971104
Short name T563
Test name
Test status
Simulation time 72502405 ps
CPU time 1.17 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 218572 kb
Host smart-ea2cda87-81c6-4da7-b265-fbbb91f162f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077971104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.4077971104
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1302299115
Short name T806
Test name
Test status
Simulation time 77745007 ps
CPU time 1.31 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:45 PM PDT 24
Peak memory 217440 kb
Host smart-8782bfbc-3763-4ac6-b3c2-e8dd469a3cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302299115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1302299115
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2507234123
Short name T349
Test name
Test status
Simulation time 110074268 ps
CPU time 1.61 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 219008 kb
Host smart-57cf6954-bf1e-441f-ab49-3364dc32231a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507234123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2507234123
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.4229120105
Short name T318
Test name
Test status
Simulation time 144463305 ps
CPU time 2.9 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 219724 kb
Host smart-a0252b63-94af-4289-b70a-b6afbaef0cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229120105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.4229120105
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.860164928
Short name T32
Test name
Test status
Simulation time 1148690359 ps
CPU time 8.43 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:53 PM PDT 24
Peak memory 218552 kb
Host smart-4496e7e5-b385-4f48-970f-6f55d7fda81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860164928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.860164928
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1219322717
Short name T834
Test name
Test status
Simulation time 45698871 ps
CPU time 1.44 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 217412 kb
Host smart-67b003ab-ed90-4a67-bee7-d8f590aad9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219322717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1219322717
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2320795198
Short name T412
Test name
Test status
Simulation time 34485059 ps
CPU time 1.24 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 217240 kb
Host smart-c0d80cb2-2c2c-4aa4-81e9-86c89a19cbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320795198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2320795198
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2023459665
Short name T149
Test name
Test status
Simulation time 44949867 ps
CPU time 1.19 seconds
Started Aug 04 05:41:19 PM PDT 24
Finished Aug 04 05:41:20 PM PDT 24
Peak memory 219344 kb
Host smart-3035e42b-e036-40d9-9f5b-fe104a56b73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023459665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2023459665
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2020978185
Short name T887
Test name
Test status
Simulation time 38121182 ps
CPU time 0.97 seconds
Started Aug 04 05:41:29 PM PDT 24
Finished Aug 04 05:41:31 PM PDT 24
Peak memory 214836 kb
Host smart-e17875c5-9124-4906-9468-c5f35cc77b77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020978185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2020978185
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1222951396
Short name T211
Test name
Test status
Simulation time 11151473 ps
CPU time 0.87 seconds
Started Aug 04 05:41:38 PM PDT 24
Finished Aug 04 05:41:39 PM PDT 24
Peak memory 216264 kb
Host smart-7d645915-45f6-4134-ad64-e91bd8dc3304
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222951396 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1222951396
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.707956473
Short name T500
Test name
Test status
Simulation time 19854418 ps
CPU time 1.11 seconds
Started Aug 04 05:41:18 PM PDT 24
Finished Aug 04 05:41:19 PM PDT 24
Peak memory 218896 kb
Host smart-39329247-d8a6-4d04-b829-040f29d8586c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707956473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.707956473
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.4063144775
Short name T508
Test name
Test status
Simulation time 62672903 ps
CPU time 1.2 seconds
Started Aug 04 05:41:20 PM PDT 24
Finished Aug 04 05:41:21 PM PDT 24
Peak memory 219880 kb
Host smart-4fe5a26e-b937-4c4a-a331-f686161a3891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063144775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.4063144775
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1744176061
Short name T393
Test name
Test status
Simulation time 32676738 ps
CPU time 0.87 seconds
Started Aug 04 05:41:22 PM PDT 24
Finished Aug 04 05:41:22 PM PDT 24
Peak memory 215328 kb
Host smart-86b12781-d485-4585-94f6-a587f9fd24d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744176061 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1744176061
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1115174704
Short name T832
Test name
Test status
Simulation time 19173144 ps
CPU time 1.01 seconds
Started Aug 04 05:41:19 PM PDT 24
Finished Aug 04 05:41:21 PM PDT 24
Peak memory 215268 kb
Host smart-fe1aa9a4-43fc-44f9-bb18-218d80feb86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115174704 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1115174704
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.868382868
Short name T457
Test name
Test status
Simulation time 592445520 ps
CPU time 2.45 seconds
Started Aug 04 05:41:36 PM PDT 24
Finished Aug 04 05:41:39 PM PDT 24
Peak memory 217376 kb
Host smart-1f67cd80-3fa9-4614-a288-d4c572a8282e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868382868 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.868382868
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.4019538779
Short name T226
Test name
Test status
Simulation time 103122857376 ps
CPU time 923.2 seconds
Started Aug 04 05:41:19 PM PDT 24
Finished Aug 04 05:56:43 PM PDT 24
Peak memory 222340 kb
Host smart-c89bdc35-28bb-4d41-8349-706f0bd93f15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019538779 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.4019538779
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.366089606
Short name T338
Test name
Test status
Simulation time 148996163 ps
CPU time 3.23 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 220220 kb
Host smart-76ffdc55-d5c0-4411-9726-64f9e67486d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366089606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.366089606
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2427779424
Short name T27
Test name
Test status
Simulation time 36494671 ps
CPU time 1.31 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 217432 kb
Host smart-31d82b3f-a40a-4365-aed8-dd621bb65e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427779424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2427779424
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1202468751
Short name T347
Test name
Test status
Simulation time 33380883 ps
CPU time 1.52 seconds
Started Aug 04 05:42:48 PM PDT 24
Finished Aug 04 05:42:49 PM PDT 24
Peak memory 217496 kb
Host smart-73eecc55-1ba2-414d-8512-7b1f4bea2a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202468751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1202468751
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1049825186
Short name T311
Test name
Test status
Simulation time 213745355 ps
CPU time 1.1 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 217208 kb
Host smart-9be79e41-e1bb-413c-ab11-96895d77871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049825186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1049825186
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2785044280
Short name T633
Test name
Test status
Simulation time 83440716 ps
CPU time 1.12 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218936 kb
Host smart-12bdeedd-7488-4c84-aba3-a09abd55261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785044280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2785044280
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2070727307
Short name T578
Test name
Test status
Simulation time 37100335 ps
CPU time 1.41 seconds
Started Aug 04 05:42:43 PM PDT 24
Finished Aug 04 05:42:45 PM PDT 24
Peak memory 219864 kb
Host smart-4416d2a4-0775-4d8b-a6a2-cb78c2dd9ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070727307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2070727307
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2780355024
Short name T866
Test name
Test status
Simulation time 314786557 ps
CPU time 2.48 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 219520 kb
Host smart-0a995631-0a80-45be-8387-4ab3fbd797a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780355024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2780355024
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.415360462
Short name T708
Test name
Test status
Simulation time 71817416 ps
CPU time 1.34 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 217508 kb
Host smart-51abad24-e4d9-4ded-b2f9-94f8fb919cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415360462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.415360462
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1735236157
Short name T677
Test name
Test status
Simulation time 26523586 ps
CPU time 1.18 seconds
Started Aug 04 05:42:46 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 217284 kb
Host smart-a17d65d1-8720-46ac-b951-f9ad9d6ec5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735236157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1735236157
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.539926715
Short name T348
Test name
Test status
Simulation time 52507694 ps
CPU time 1.73 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 218572 kb
Host smart-27294e2a-b720-49e2-9f19-9ad94bd97c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539926715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.539926715
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2433527589
Short name T575
Test name
Test status
Simulation time 63948322 ps
CPU time 1.06 seconds
Started Aug 04 05:41:37 PM PDT 24
Finished Aug 04 05:41:38 PM PDT 24
Peak memory 218652 kb
Host smart-f6e5d133-5a2a-479f-a3fa-fe8267845cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433527589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2433527589
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3268772785
Short name T944
Test name
Test status
Simulation time 15669297 ps
CPU time 0.94 seconds
Started Aug 04 05:41:30 PM PDT 24
Finished Aug 04 05:41:31 PM PDT 24
Peak memory 215136 kb
Host smart-123fa1d7-1991-4225-93d4-ec6138e5cfbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268772785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3268772785
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1002978580
Short name T69
Test name
Test status
Simulation time 96895811 ps
CPU time 0.89 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:43 PM PDT 24
Peak memory 216236 kb
Host smart-6f5dd784-612b-4085-9bf7-c273bcc1a661
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002978580 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1002978580
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3331983101
Short name T421
Test name
Test status
Simulation time 72924742 ps
CPU time 1.1 seconds
Started Aug 04 05:41:33 PM PDT 24
Finished Aug 04 05:41:34 PM PDT 24
Peak memory 218392 kb
Host smart-edd7c186-e06d-441d-a626-cd825d04dcf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331983101 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3331983101
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.4064350982
Short name T146
Test name
Test status
Simulation time 27146461 ps
CPU time 1.19 seconds
Started Aug 04 05:41:20 PM PDT 24
Finished Aug 04 05:41:21 PM PDT 24
Peak memory 220452 kb
Host smart-1f29ce09-ea0d-427b-815c-4fb19d57c43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064350982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.4064350982
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2078995497
Short name T739
Test name
Test status
Simulation time 132739825 ps
CPU time 1.38 seconds
Started Aug 04 05:41:20 PM PDT 24
Finished Aug 04 05:41:21 PM PDT 24
Peak memory 218608 kb
Host smart-a3b03bb2-49eb-4151-8e9c-378d1ad0e128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078995497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2078995497
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.396976394
Short name T619
Test name
Test status
Simulation time 31683816 ps
CPU time 0.88 seconds
Started Aug 04 05:41:37 PM PDT 24
Finished Aug 04 05:41:38 PM PDT 24
Peak memory 215764 kb
Host smart-0599fb76-4c7e-4b2e-bf76-1b5c2816d836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396976394 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.396976394
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3709638176
Short name T841
Test name
Test status
Simulation time 19362051 ps
CPU time 0.99 seconds
Started Aug 04 05:41:18 PM PDT 24
Finished Aug 04 05:41:19 PM PDT 24
Peak memory 215332 kb
Host smart-c8a79a3b-6907-4917-a373-ff9e33e945e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709638176 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3709638176
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3752300682
Short name T126
Test name
Test status
Simulation time 231543718 ps
CPU time 4.58 seconds
Started Aug 04 05:41:27 PM PDT 24
Finished Aug 04 05:41:31 PM PDT 24
Peak memory 215296 kb
Host smart-f06666e9-4362-4896-8528-27fcae03a230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752300682 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3752300682
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.4147757247
Short name T234
Test name
Test status
Simulation time 179354313232 ps
CPU time 1945.21 seconds
Started Aug 04 05:41:37 PM PDT 24
Finished Aug 04 06:14:03 PM PDT 24
Peak memory 224884 kb
Host smart-9464cb4d-3069-4769-8080-f59083ac7ed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147757247 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.4147757247
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.138662138
Short name T534
Test name
Test status
Simulation time 93056595 ps
CPU time 1.31 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 217320 kb
Host smart-184588d8-e404-42e9-a198-7cfad82e4d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138662138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.138662138
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2970895497
Short name T305
Test name
Test status
Simulation time 42157117 ps
CPU time 1.5 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:39 PM PDT 24
Peak memory 218540 kb
Host smart-1d5f5286-6b21-4432-8b37-53f34239ce20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970895497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2970895497
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.789166102
Short name T740
Test name
Test status
Simulation time 53112832 ps
CPU time 1.26 seconds
Started Aug 04 05:42:46 PM PDT 24
Finished Aug 04 05:42:48 PM PDT 24
Peak memory 219868 kb
Host smart-35f1dc3c-4b9c-446e-b996-72bf4153851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789166102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.789166102
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.501418474
Short name T390
Test name
Test status
Simulation time 37069734 ps
CPU time 1.27 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 215328 kb
Host smart-2db4129d-11bb-45fa-8c95-d8e7407a5c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501418474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.501418474
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2572467557
Short name T957
Test name
Test status
Simulation time 114706164 ps
CPU time 2.16 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:41 PM PDT 24
Peak memory 218644 kb
Host smart-2c05638f-9d89-42e5-ae7f-0c56c16036e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572467557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2572467557
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.621435290
Short name T651
Test name
Test status
Simulation time 124734403 ps
CPU time 1.53 seconds
Started Aug 04 05:42:36 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 218792 kb
Host smart-53376a02-5524-4e02-b6c2-b82fab935dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621435290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.621435290
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.395897512
Short name T623
Test name
Test status
Simulation time 111875615 ps
CPU time 1.37 seconds
Started Aug 04 05:42:46 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 218636 kb
Host smart-09a84e80-9071-45ec-8236-e44d7c569124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395897512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.395897512
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3600458578
Short name T746
Test name
Test status
Simulation time 123563835 ps
CPU time 1.31 seconds
Started Aug 04 05:42:45 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 220484 kb
Host smart-97780917-c3be-4915-950d-2b2872f34710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600458578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3600458578
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2625034017
Short name T365
Test name
Test status
Simulation time 37941436 ps
CPU time 1.59 seconds
Started Aug 04 05:42:45 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 218564 kb
Host smart-484bf144-fd76-4040-8d6b-d5e952c67520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625034017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2625034017
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3346619057
Short name T592
Test name
Test status
Simulation time 23777438 ps
CPU time 1.24 seconds
Started Aug 04 05:41:19 PM PDT 24
Finished Aug 04 05:41:20 PM PDT 24
Peak memory 215956 kb
Host smart-977ff06b-9b50-44b8-920d-224f3a5c35ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346619057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3346619057
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2157309624
Short name T614
Test name
Test status
Simulation time 48309691 ps
CPU time 0.9 seconds
Started Aug 04 05:41:17 PM PDT 24
Finished Aug 04 05:41:18 PM PDT 24
Peak memory 206676 kb
Host smart-897b3e40-f938-40ed-acbd-74877d1f2904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157309624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2157309624
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1663280440
Short name T65
Test name
Test status
Simulation time 103869073 ps
CPU time 1.26 seconds
Started Aug 04 05:41:18 PM PDT 24
Finished Aug 04 05:41:20 PM PDT 24
Peak memory 219584 kb
Host smart-c451eb32-cb5b-416e-a7e9-ab82b515f200
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663280440 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1663280440
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1059245069
Short name T644
Test name
Test status
Simulation time 43738451 ps
CPU time 1.01 seconds
Started Aug 04 05:41:33 PM PDT 24
Finished Aug 04 05:41:34 PM PDT 24
Peak memory 219928 kb
Host smart-33829cd2-b4fa-40dd-a0c1-c8de170cbe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059245069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1059245069
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_intr.3805287505
Short name T880
Test name
Test status
Simulation time 22908160 ps
CPU time 0.93 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:43 PM PDT 24
Peak memory 215812 kb
Host smart-2ae8336b-e9e4-4008-a69a-39c3b618714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805287505 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3805287505
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.520210390
Short name T372
Test name
Test status
Simulation time 15224214 ps
CPU time 0.95 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 215260 kb
Host smart-51f3bd18-6d90-45e0-a22a-35709f3f362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520210390 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.520210390
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.574015003
Short name T663
Test name
Test status
Simulation time 415507956 ps
CPU time 8.01 seconds
Started Aug 04 05:41:31 PM PDT 24
Finished Aug 04 05:41:39 PM PDT 24
Peak memory 218684 kb
Host smart-3fba6af9-e9d2-4a2b-aa95-5254021e63b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574015003 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.574015003
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1329334973
Short name T224
Test name
Test status
Simulation time 110661038325 ps
CPU time 1890.16 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 06:13:13 PM PDT 24
Peak memory 225372 kb
Host smart-52071b39-575f-4db4-a9ba-aa8fc8ced20c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329334973 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1329334973
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3274576247
Short name T548
Test name
Test status
Simulation time 62542142 ps
CPU time 1.03 seconds
Started Aug 04 05:42:41 PM PDT 24
Finished Aug 04 05:42:42 PM PDT 24
Peak memory 217276 kb
Host smart-a219e960-13ab-4c7b-a1a5-b0c9df3230c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274576247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3274576247
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.4059852707
Short name T895
Test name
Test status
Simulation time 228374910 ps
CPU time 2.26 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 219924 kb
Host smart-1752f81e-d991-465a-a36b-882a04785c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059852707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4059852707
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2549312495
Short name T335
Test name
Test status
Simulation time 88847449 ps
CPU time 1.3 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 218560 kb
Host smart-877ecfd1-ce04-4a83-8e91-7179edc8a1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549312495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2549312495
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2826590906
Short name T485
Test name
Test status
Simulation time 63860449 ps
CPU time 1.04 seconds
Started Aug 04 05:42:46 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 217312 kb
Host smart-a60db84a-20e1-4684-b511-0a86c6a55891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826590906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2826590906
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3958380812
Short name T11
Test name
Test status
Simulation time 35433689 ps
CPU time 1.33 seconds
Started Aug 04 05:42:47 PM PDT 24
Finished Aug 04 05:42:48 PM PDT 24
Peak memory 219928 kb
Host smart-e68bc5ee-60c2-498c-b714-0e499b8b1ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958380812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3958380812
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1509224184
Short name T564
Test name
Test status
Simulation time 73727720 ps
CPU time 1.23 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 218876 kb
Host smart-e17a4212-0f42-42e8-bb80-ae79d28fd4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509224184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1509224184
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3342233313
Short name T377
Test name
Test status
Simulation time 59472712 ps
CPU time 2.26 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 217508 kb
Host smart-8cea9279-535b-44f5-9225-2fa20c997768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342233313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3342233313
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1678177493
Short name T620
Test name
Test status
Simulation time 42417091 ps
CPU time 1.64 seconds
Started Aug 04 05:42:39 PM PDT 24
Finished Aug 04 05:42:40 PM PDT 24
Peak memory 218524 kb
Host smart-9217be86-18e6-4a5e-8051-3ee772505d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678177493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1678177493
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2235595929
Short name T816
Test name
Test status
Simulation time 214862287 ps
CPU time 1.32 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:45 PM PDT 24
Peak memory 217288 kb
Host smart-faad30f9-8f42-4bea-898c-4f98b6cd32d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235595929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2235595929
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.4281113933
Short name T513
Test name
Test status
Simulation time 46140704 ps
CPU time 1.13 seconds
Started Aug 04 05:42:43 PM PDT 24
Finished Aug 04 05:42:45 PM PDT 24
Peak memory 215612 kb
Host smart-115aa0e4-9d27-4cf4-822b-23bfef3f0a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281113933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.4281113933
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2152275649
Short name T279
Test name
Test status
Simulation time 99245886 ps
CPU time 1.27 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 218476 kb
Host smart-6b13d1aa-860a-4ff9-9d18-c81c5f09335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152275649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2152275649
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3282508190
Short name T869
Test name
Test status
Simulation time 151605092 ps
CPU time 0.88 seconds
Started Aug 04 05:41:33 PM PDT 24
Finished Aug 04 05:41:35 PM PDT 24
Peak memory 214900 kb
Host smart-f916f66d-5e0f-4a01-9eab-7097321d700e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282508190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3282508190
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1782460131
Short name T195
Test name
Test status
Simulation time 59581321 ps
CPU time 0.88 seconds
Started Aug 04 05:41:38 PM PDT 24
Finished Aug 04 05:41:39 PM PDT 24
Peak memory 216272 kb
Host smart-9b28e6d3-666a-449f-89aa-e35aba027ec7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782460131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1782460131
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.351148226
Short name T664
Test name
Test status
Simulation time 107277316 ps
CPU time 1.09 seconds
Started Aug 04 05:41:40 PM PDT 24
Finished Aug 04 05:41:41 PM PDT 24
Peak memory 218612 kb
Host smart-0dde92f2-ecf3-48d6-bacd-fd9e2d2b7869
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351148226 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.351148226
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2828890980
Short name T97
Test name
Test status
Simulation time 166985742 ps
CPU time 1.17 seconds
Started Aug 04 05:41:34 PM PDT 24
Finished Aug 04 05:41:35 PM PDT 24
Peak memory 232292 kb
Host smart-3b3035a3-8cac-4a9c-80aa-e31b90051b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828890980 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2828890980
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2415323177
Short name T551
Test name
Test status
Simulation time 63078402 ps
CPU time 1.24 seconds
Started Aug 04 05:41:34 PM PDT 24
Finished Aug 04 05:41:35 PM PDT 24
Peak memory 218996 kb
Host smart-add1295a-9839-4a3e-b974-2e0b98ddc41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415323177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2415323177
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1015241627
Short name T56
Test name
Test status
Simulation time 21965956 ps
CPU time 1.05 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:46 PM PDT 24
Peak memory 215848 kb
Host smart-d74fde84-c6d8-4ba5-abfa-de730e1c504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015241627 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1015241627
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2939313941
Short name T970
Test name
Test status
Simulation time 17924934 ps
CPU time 1.01 seconds
Started Aug 04 05:41:35 PM PDT 24
Finished Aug 04 05:41:36 PM PDT 24
Peak memory 215320 kb
Host smart-cfd59cfc-d948-4b5c-bcdf-8ad9316b2e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939313941 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2939313941
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1165738066
Short name T601
Test name
Test status
Simulation time 787545628 ps
CPU time 5.11 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 217272 kb
Host smart-1b6b0cf1-1b13-42e3-a891-8c706048be07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165738066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1165738066
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3054542913
Short name T229
Test name
Test status
Simulation time 18149426994 ps
CPU time 293.67 seconds
Started Aug 04 05:41:41 PM PDT 24
Finished Aug 04 05:46:35 PM PDT 24
Peak memory 218324 kb
Host smart-68ad87ff-bfb9-41b2-a99b-94210489fa30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054542913 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3054542913
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2172502886
Short name T597
Test name
Test status
Simulation time 49023396 ps
CPU time 1.14 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 217396 kb
Host smart-1087a8e4-f07e-424e-adc2-330cf253101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172502886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2172502886
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.517540581
Short name T295
Test name
Test status
Simulation time 44958481 ps
CPU time 1.2 seconds
Started Aug 04 05:42:46 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 218768 kb
Host smart-f382c41d-d27b-4019-840c-92830ef76c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517540581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.517540581
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.818321086
Short name T731
Test name
Test status
Simulation time 45069096 ps
CPU time 1.23 seconds
Started Aug 04 05:42:46 PM PDT 24
Finished Aug 04 05:42:47 PM PDT 24
Peak memory 220164 kb
Host smart-14a7e77f-43c3-4535-bac4-188ffbb0c736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818321086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.818321086
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.942850249
Short name T587
Test name
Test status
Simulation time 199947001 ps
CPU time 1.11 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 219860 kb
Host smart-6707f538-6cad-439e-9b68-874a8fb046c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942850249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.942850249
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.4266475354
Short name T535
Test name
Test status
Simulation time 64052553 ps
CPU time 1.56 seconds
Started Aug 04 05:42:37 PM PDT 24
Finished Aug 04 05:42:38 PM PDT 24
Peak memory 220332 kb
Host smart-a2c114d1-e302-44a4-8f26-b520be90536d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266475354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.4266475354
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2088321162
Short name T682
Test name
Test status
Simulation time 153629624 ps
CPU time 1.3 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:37 PM PDT 24
Peak memory 215328 kb
Host smart-e8d7e9f2-4aa5-4412-8ba7-36719ae5383b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088321162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2088321162
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3718204269
Short name T835
Test name
Test status
Simulation time 155630626 ps
CPU time 2.98 seconds
Started Aug 04 05:42:40 PM PDT 24
Finished Aug 04 05:42:43 PM PDT 24
Peak memory 220352 kb
Host smart-27e51c33-ac71-421e-8ed5-c64a97e7d455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718204269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3718204269
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2957006035
Short name T453
Test name
Test status
Simulation time 236411817 ps
CPU time 1.32 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:46 PM PDT 24
Peak memory 217296 kb
Host smart-7422dfc7-169f-4a39-9513-0b71e8219aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957006035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2957006035
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3624594961
Short name T520
Test name
Test status
Simulation time 70508871 ps
CPU time 1 seconds
Started Aug 04 05:42:44 PM PDT 24
Finished Aug 04 05:42:45 PM PDT 24
Peak memory 217352 kb
Host smart-46712600-027f-4e8a-9795-97a63dd4954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624594961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3624594961
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.384514570
Short name T329
Test name
Test status
Simulation time 104612710 ps
CPU time 1.59 seconds
Started Aug 04 05:42:42 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 219044 kb
Host smart-cb07a44d-70a3-4b87-9287-100ba9400f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384514570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.384514570
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2035998358
Short name T845
Test name
Test status
Simulation time 33774686 ps
CPU time 1.25 seconds
Started Aug 04 05:40:42 PM PDT 24
Finished Aug 04 05:40:43 PM PDT 24
Peak memory 218696 kb
Host smart-c6367c60-ce95-4d5d-97bc-6c4873d654e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035998358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2035998358
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2531600910
Short name T871
Test name
Test status
Simulation time 30964910 ps
CPU time 0.85 seconds
Started Aug 04 05:40:43 PM PDT 24
Finished Aug 04 05:40:44 PM PDT 24
Peak memory 206484 kb
Host smart-ca8e38e1-838e-4b33-8e69-0cf3d66f0e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531600910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2531600910
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3243050218
Short name T916
Test name
Test status
Simulation time 57704510 ps
CPU time 0.91 seconds
Started Aug 04 05:40:52 PM PDT 24
Finished Aug 04 05:40:53 PM PDT 24
Peak memory 215960 kb
Host smart-43b0e9bb-0b20-476d-af88-dcfe9cc5fbcb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243050218 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3243050218
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1537301385
Short name T361
Test name
Test status
Simulation time 53845013 ps
CPU time 1.11 seconds
Started Aug 04 05:40:50 PM PDT 24
Finished Aug 04 05:40:52 PM PDT 24
Peak memory 217080 kb
Host smart-48376cf7-5c12-4e09-bdc6-be36382f1486
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537301385 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1537301385
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1833438909
Short name T98
Test name
Test status
Simulation time 19125253 ps
CPU time 1.03 seconds
Started Aug 04 05:40:52 PM PDT 24
Finished Aug 04 05:40:54 PM PDT 24
Peak memory 218616 kb
Host smart-13f0a5e2-e542-4ee6-b189-e59103f2a755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833438909 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1833438909
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3668391450
Short name T801
Test name
Test status
Simulation time 66084829 ps
CPU time 1.3 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:40:47 PM PDT 24
Peak memory 218948 kb
Host smart-3735af06-1ed6-422a-9a4d-08c4e22da888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668391450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3668391450
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1368832520
Short name T665
Test name
Test status
Simulation time 24349767 ps
CPU time 0.96 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:40:46 PM PDT 24
Peak memory 215940 kb
Host smart-4df5859a-1284-45cc-b690-7b55691af5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368832520 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1368832520
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1195620653
Short name T561
Test name
Test status
Simulation time 64884040 ps
CPU time 1.02 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 207084 kb
Host smart-4662d9d1-cf95-46bf-bd1b-de39d3c99406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195620653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1195620653
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.2505150888
Short name T569
Test name
Test status
Simulation time 35345939 ps
CPU time 0.9 seconds
Started Aug 04 05:40:56 PM PDT 24
Finished Aug 04 05:40:57 PM PDT 24
Peak memory 215100 kb
Host smart-919d5480-fb05-4336-a25e-0acce67ef18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505150888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2505150888
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1271282953
Short name T474
Test name
Test status
Simulation time 256943791 ps
CPU time 2.99 seconds
Started Aug 04 05:40:52 PM PDT 24
Finished Aug 04 05:40:55 PM PDT 24
Peak memory 215248 kb
Host smart-ccea35c6-6566-4419-b8f6-8671bfe28d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271282953 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1271282953
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1618068181
Short name T494
Test name
Test status
Simulation time 71455270443 ps
CPU time 253.66 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:44:59 PM PDT 24
Peak memory 218192 kb
Host smart-467fd592-b9a4-4c1a-81d9-780c1e334b54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618068181 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1618068181
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert_test.1053111202
Short name T45
Test name
Test status
Simulation time 20508690 ps
CPU time 1 seconds
Started Aug 04 05:41:37 PM PDT 24
Finished Aug 04 05:41:38 PM PDT 24
Peak memory 206800 kb
Host smart-e308dd5b-ab02-4712-b4e6-bd48b1ba3bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053111202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1053111202
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2269390276
Short name T90
Test name
Test status
Simulation time 11257160 ps
CPU time 0.9 seconds
Started Aug 04 05:41:35 PM PDT 24
Finished Aug 04 05:41:36 PM PDT 24
Peak memory 216240 kb
Host smart-3e39153e-0ca8-4899-8407-d0e0a91a4215
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269390276 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2269390276
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3388608516
Short name T169
Test name
Test status
Simulation time 152555650 ps
CPU time 1.13 seconds
Started Aug 04 05:41:38 PM PDT 24
Finished Aug 04 05:41:40 PM PDT 24
Peak memory 218808 kb
Host smart-0d73eb5b-f173-4e58-9930-6727360c1299
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388608516 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3388608516
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3987559173
Short name T138
Test name
Test status
Simulation time 27619792 ps
CPU time 1.25 seconds
Started Aug 04 05:41:38 PM PDT 24
Finished Aug 04 05:41:39 PM PDT 24
Peak memory 220616 kb
Host smart-bfedbcc3-dcb2-451c-83ed-1489da82cbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987559173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3987559173
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2053767828
Short name T395
Test name
Test status
Simulation time 74872471 ps
CPU time 1.07 seconds
Started Aug 04 05:41:27 PM PDT 24
Finished Aug 04 05:41:28 PM PDT 24
Peak memory 217348 kb
Host smart-4ee1583f-5691-496c-91a6-e6bc53cc8815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053767828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2053767828
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_smoke.439334441
Short name T958
Test name
Test status
Simulation time 20730677 ps
CPU time 1.02 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:43 PM PDT 24
Peak memory 215304 kb
Host smart-b7090118-d0ca-4e6d-8cf5-b74c7551aa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439334441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.439334441
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2266603983
Short name T728
Test name
Test status
Simulation time 499415154 ps
CPU time 3.45 seconds
Started Aug 04 05:41:40 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 217080 kb
Host smart-f0db8481-a0df-4350-be1a-e7228c623256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266603983 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2266603983
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3811588880
Short name T227
Test name
Test status
Simulation time 125379890772 ps
CPU time 752.64 seconds
Started Aug 04 05:41:29 PM PDT 24
Finished Aug 04 05:54:02 PM PDT 24
Peak memory 223684 kb
Host smart-91f8904a-d6d1-4d79-8605-197dd39a9dff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811588880 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3811588880
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3567837930
Short name T291
Test name
Test status
Simulation time 24395936 ps
CPU time 1.22 seconds
Started Aug 04 05:41:34 PM PDT 24
Finished Aug 04 05:41:35 PM PDT 24
Peak memory 219700 kb
Host smart-08955ab2-9930-43ab-87a3-bbdbb371bcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567837930 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3567837930
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1807353900
Short name T616
Test name
Test status
Simulation time 125706664 ps
CPU time 0.85 seconds
Started Aug 04 05:41:38 PM PDT 24
Finished Aug 04 05:41:39 PM PDT 24
Peak memory 214696 kb
Host smart-12b8c3b6-ff90-468b-9ac7-c06d42257a6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807353900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1807353900
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3086071160
Short name T215
Test name
Test status
Simulation time 13326226 ps
CPU time 0.92 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 216400 kb
Host smart-6b3885b3-34ff-4350-8351-57182aee6360
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086071160 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3086071160
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.4013674746
Short name T881
Test name
Test status
Simulation time 24029864 ps
CPU time 1.08 seconds
Started Aug 04 05:41:40 PM PDT 24
Finished Aug 04 05:41:41 PM PDT 24
Peak memory 219588 kb
Host smart-4947fcde-2547-49f9-a5e5-3e374e70bf2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013674746 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.4013674746
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1598802480
Short name T159
Test name
Test status
Simulation time 34178748 ps
CPU time 1.04 seconds
Started Aug 04 05:41:33 PM PDT 24
Finished Aug 04 05:41:34 PM PDT 24
Peak memory 229644 kb
Host smart-24b617c7-63c9-41d9-8f38-59531b995ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598802480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1598802480
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1184295751
Short name T925
Test name
Test status
Simulation time 32932439 ps
CPU time 1.43 seconds
Started Aug 04 05:41:35 PM PDT 24
Finished Aug 04 05:41:37 PM PDT 24
Peak memory 219676 kb
Host smart-5eadea1a-96ed-4f13-bf32-274fb42a11d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184295751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1184295751
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.706271604
Short name T882
Test name
Test status
Simulation time 25229034 ps
CPU time 0.98 seconds
Started Aug 04 05:41:30 PM PDT 24
Finished Aug 04 05:41:32 PM PDT 24
Peak memory 215908 kb
Host smart-1a3e1356-7dae-40e6-8755-856d28ed8075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706271604 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.706271604
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3873743864
Short name T588
Test name
Test status
Simulation time 199096026 ps
CPU time 0.91 seconds
Started Aug 04 05:41:31 PM PDT 24
Finished Aug 04 05:41:32 PM PDT 24
Peak memory 215276 kb
Host smart-85dae07e-f8fd-461e-be2e-7cdfab7a623a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873743864 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3873743864
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.944555489
Short name T549
Test name
Test status
Simulation time 1155716713 ps
CPU time 4.9 seconds
Started Aug 04 05:41:37 PM PDT 24
Finished Aug 04 05:41:42 PM PDT 24
Peak memory 215312 kb
Host smart-e7a882a2-be50-4554-82cf-6d5c13f4b8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944555489 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.944555489
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.544353455
Short name T822
Test name
Test status
Simulation time 74643742157 ps
CPU time 1989.45 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 06:14:55 PM PDT 24
Peak memory 228728 kb
Host smart-d67b9261-d43c-4702-b2f1-6fc71f48252d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544353455 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.544353455
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1685395912
Short name T503
Test name
Test status
Simulation time 48491334 ps
CPU time 1.29 seconds
Started Aug 04 05:41:31 PM PDT 24
Finished Aug 04 05:41:33 PM PDT 24
Peak memory 218556 kb
Host smart-ad6a5510-5bd6-4fbb-9509-75ff580f1bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685395912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1685395912
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2349121750
Short name T898
Test name
Test status
Simulation time 19904555 ps
CPU time 0.99 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:46 PM PDT 24
Peak memory 206776 kb
Host smart-fdc39d8b-4c13-45e7-8ff5-af1e71843ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349121750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2349121750
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1393404811
Short name T104
Test name
Test status
Simulation time 101226137 ps
CPU time 0.86 seconds
Started Aug 04 05:41:35 PM PDT 24
Finished Aug 04 05:41:36 PM PDT 24
Peak memory 216124 kb
Host smart-355f72e5-5639-430f-b39a-21e48b986b12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393404811 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1393404811
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.997394580
Short name T874
Test name
Test status
Simulation time 49967763 ps
CPU time 1.41 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 216892 kb
Host smart-1bde2183-3bf2-4e60-95b4-21e6bd258541
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997394580 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.997394580
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3768868942
Short name T648
Test name
Test status
Simulation time 21844403 ps
CPU time 1.08 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 224060 kb
Host smart-92e8ee26-70a7-4563-9df7-b03ebca5efed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768868942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3768868942
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1256941597
Short name T323
Test name
Test status
Simulation time 44876349 ps
CPU time 1.1 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:43 PM PDT 24
Peak memory 217324 kb
Host smart-df1ce3c9-62a9-4aaf-880e-dc8066288ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256941597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1256941597
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.189901684
Short name T81
Test name
Test status
Simulation time 34969430 ps
CPU time 0.86 seconds
Started Aug 04 05:41:41 PM PDT 24
Finished Aug 04 05:41:42 PM PDT 24
Peak memory 215740 kb
Host smart-d6be183e-8184-4a09-b743-298247c8f2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189901684 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.189901684
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1765662344
Short name T626
Test name
Test status
Simulation time 18020832 ps
CPU time 0.96 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 215292 kb
Host smart-2bfe2c4f-fb2c-4969-9928-d8aabaa070c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765662344 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1765662344
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.4115675426
Short name T123
Test name
Test status
Simulation time 207577335 ps
CPU time 4.21 seconds
Started Aug 04 05:41:23 PM PDT 24
Finished Aug 04 05:41:27 PM PDT 24
Peak memory 217148 kb
Host smart-bc12ade8-7d31-4e19-8f2b-8ce1168068c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115675426 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.4115675426
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2405414668
Short name T900
Test name
Test status
Simulation time 49060384739 ps
CPU time 1077.19 seconds
Started Aug 04 05:41:41 PM PDT 24
Finished Aug 04 05:59:39 PM PDT 24
Peak memory 220376 kb
Host smart-5b036b89-a8d9-422a-ab80-888bde19b732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405414668 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2405414668
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1747216645
Short name T703
Test name
Test status
Simulation time 23784892 ps
CPU time 1.13 seconds
Started Aug 04 05:42:12 PM PDT 24
Finished Aug 04 05:42:13 PM PDT 24
Peak memory 215608 kb
Host smart-2ae6daeb-d234-4060-ac64-21cdbb247979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747216645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1747216645
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3470806720
Short name T440
Test name
Test status
Simulation time 169228296 ps
CPU time 0.87 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:43 PM PDT 24
Peak memory 214892 kb
Host smart-ef3e0461-2971-40c0-a495-6bb713ae890b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470806720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3470806720
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2045074274
Short name T218
Test name
Test status
Simulation time 23819893 ps
CPU time 0.84 seconds
Started Aug 04 05:41:38 PM PDT 24
Finished Aug 04 05:41:39 PM PDT 24
Peak memory 216332 kb
Host smart-2f262e72-4642-496d-90c6-30169a7602a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045074274 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2045074274
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3969129033
Short name T99
Test name
Test status
Simulation time 92050099 ps
CPU time 1.24 seconds
Started Aug 04 05:41:33 PM PDT 24
Finished Aug 04 05:41:34 PM PDT 24
Peak memory 216896 kb
Host smart-e39bc458-7783-4a09-932c-ab20fd5fbf10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969129033 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3969129033
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1838711765
Short name T102
Test name
Test status
Simulation time 19934259 ps
CPU time 1.1 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:46 PM PDT 24
Peak memory 218384 kb
Host smart-72a3e5ab-6163-423a-a7b0-20a00e39e9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838711765 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1838711765
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2336635062
Short name T836
Test name
Test status
Simulation time 92124232 ps
CPU time 1.19 seconds
Started Aug 04 05:41:28 PM PDT 24
Finished Aug 04 05:41:29 PM PDT 24
Peak memory 217316 kb
Host smart-5e8ef4e7-de38-488e-9fbb-30c7b30f3623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336635062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2336635062
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.378077026
Short name T654
Test name
Test status
Simulation time 34407574 ps
CPU time 1.06 seconds
Started Aug 04 05:41:41 PM PDT 24
Finished Aug 04 05:41:42 PM PDT 24
Peak memory 224064 kb
Host smart-7f23513c-376a-45d8-93b5-500235f53155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378077026 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.378077026
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3342259565
Short name T982
Test name
Test status
Simulation time 25728380 ps
CPU time 0.91 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 215288 kb
Host smart-06e52c21-d81d-42dd-bae0-fa40c541d83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342259565 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3342259565
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.40809978
Short name T811
Test name
Test status
Simulation time 379200111 ps
CPU time 6.98 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 217076 kb
Host smart-31f39e40-cbdd-4790-be5c-2e6adeb1087b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40809978 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.40809978
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3438874461
Short name T233
Test name
Test status
Simulation time 27522599074 ps
CPU time 614.38 seconds
Started Aug 04 05:41:38 PM PDT 24
Finished Aug 04 05:51:53 PM PDT 24
Peak memory 223712 kb
Host smart-f933fa36-ceb4-4f1f-82c8-515cb1faf1a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438874461 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3438874461
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3336392478
Short name T603
Test name
Test status
Simulation time 321434742 ps
CPU time 1.33 seconds
Started Aug 04 05:41:36 PM PDT 24
Finished Aug 04 05:41:38 PM PDT 24
Peak memory 220792 kb
Host smart-0ff93dc7-9a36-46be-929a-c3f8e9fce44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336392478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3336392478
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1469109931
Short name T937
Test name
Test status
Simulation time 26305961 ps
CPU time 0.88 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:43 PM PDT 24
Peak memory 214844 kb
Host smart-c9840e3d-e1b9-4e66-9922-6f80bfd7ff66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469109931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1469109931
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1611171275
Short name T867
Test name
Test status
Simulation time 15595147 ps
CPU time 0.88 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 215556 kb
Host smart-53a37935-1a93-48ba-9298-99d895f179a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611171275 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1611171275
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.334922527
Short name T106
Test name
Test status
Simulation time 82148492 ps
CPU time 1.12 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 216956 kb
Host smart-1cbc35be-a64b-4580-896f-65280f813c87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334922527 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.334922527
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3026369009
Short name T110
Test name
Test status
Simulation time 75644500 ps
CPU time 1.07 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 219684 kb
Host smart-7852d11b-3798-4579-af53-f59f1037a975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026369009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3026369009
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1463811581
Short name T319
Test name
Test status
Simulation time 22692173 ps
CPU time 1.18 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 219828 kb
Host smart-f7eeeab4-1e1b-409d-9ae5-5ca029748f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463811581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1463811581
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.77213435
Short name T73
Test name
Test status
Simulation time 25403806 ps
CPU time 1.13 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 215868 kb
Host smart-1e63d8b4-058a-4a1b-b58f-e70aba8c8e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77213435 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.77213435
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2702580376
Short name T532
Test name
Test status
Simulation time 16279702 ps
CPU time 1.01 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 215284 kb
Host smart-dc648671-fb28-46ea-9b91-1f052656cdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702580376 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2702580376
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2695392558
Short name T382
Test name
Test status
Simulation time 183742410 ps
CPU time 3.4 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 218464 kb
Host smart-a0ded20c-aeda-4fef-b32e-662092c019c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695392558 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2695392558
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_alert.1225581586
Short name T562
Test name
Test status
Simulation time 94843478 ps
CPU time 1.3 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 220340 kb
Host smart-a5f02951-d45d-41bd-8b74-e52d280a5646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225581586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1225581586
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3196320524
Short name T537
Test name
Test status
Simulation time 52134774 ps
CPU time 0.9 seconds
Started Aug 04 05:41:37 PM PDT 24
Finished Aug 04 05:41:38 PM PDT 24
Peak memory 206724 kb
Host smart-83bbe9ee-49d8-414a-a3d8-75b342031510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196320524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3196320524
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2763211971
Short name T177
Test name
Test status
Simulation time 28660370 ps
CPU time 0.81 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:46 PM PDT 24
Peak memory 215356 kb
Host smart-a32903ef-142f-48cf-bf26-4f99463e8568
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763211971 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2763211971
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.665659118
Short name T948
Test name
Test status
Simulation time 78094022 ps
CPU time 1.07 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 219684 kb
Host smart-4a7d34e9-865f-4f37-958a-3f0c238751b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665659118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.665659118
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2112554976
Short name T449
Test name
Test status
Simulation time 66533716 ps
CPU time 1.85 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 218624 kb
Host smart-808bcea7-ebbe-4bfb-abc8-b47ac10d5c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112554976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2112554976
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.833052226
Short name T76
Test name
Test status
Simulation time 55952625 ps
CPU time 0.84 seconds
Started Aug 04 05:41:41 PM PDT 24
Finished Aug 04 05:41:42 PM PDT 24
Peak memory 215548 kb
Host smart-5f59ce09-dddf-472f-b984-d105984bd608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833052226 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.833052226
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2200619127
Short name T615
Test name
Test status
Simulation time 18780641 ps
CPU time 0.98 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 215272 kb
Host smart-7d0bef88-7c0b-4a26-b92e-4ac3b8c05d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200619127 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2200619127
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2075513365
Short name T545
Test name
Test status
Simulation time 98965826 ps
CPU time 2.44 seconds
Started Aug 04 05:41:40 PM PDT 24
Finished Aug 04 05:41:43 PM PDT 24
Peak memory 218644 kb
Host smart-83923536-624c-4940-84bf-fbaebe90331b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075513365 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2075513365
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.997652075
Short name T666
Test name
Test status
Simulation time 94311240673 ps
CPU time 584.94 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:51:30 PM PDT 24
Peak memory 219780 kb
Host smart-c30b48b7-f1ca-47e0-beaa-1b09bc97d2dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997652075 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.997652075
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.492283335
Short name T276
Test name
Test status
Simulation time 96701066 ps
CPU time 1.24 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 215696 kb
Host smart-3653b869-f771-4900-9bb0-a7cd069fdf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492283335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.492283335
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2582078184
Short name T889
Test name
Test status
Simulation time 52522694 ps
CPU time 0.94 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 206720 kb
Host smart-a906b857-e182-4692-9a8d-1408ca345708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582078184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2582078184
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1238934116
Short name T717
Test name
Test status
Simulation time 17301669 ps
CPU time 0.88 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 216200 kb
Host smart-9df6466b-4708-4711-8e5e-75b8cb258049
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238934116 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1238934116
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3101728838
Short name T437
Test name
Test status
Simulation time 45037266 ps
CPU time 1.3 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 218444 kb
Host smart-97cfc96a-7a7d-4cb7-8d63-508b44f2f231
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101728838 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3101728838
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3436228101
Short name T93
Test name
Test status
Simulation time 35892379 ps
CPU time 1.22 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 232300 kb
Host smart-69d21ffd-926f-4ca3-9e83-30f6e26fb99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436228101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3436228101
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.192693478
Short name T783
Test name
Test status
Simulation time 64930892 ps
CPU time 1.81 seconds
Started Aug 04 05:41:40 PM PDT 24
Finished Aug 04 05:41:42 PM PDT 24
Peak memory 217468 kb
Host smart-31e59046-2221-4971-a522-6a776c48e759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192693478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.192693478
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3739259465
Short name T445
Test name
Test status
Simulation time 23725793 ps
CPU time 1.09 seconds
Started Aug 04 05:41:39 PM PDT 24
Finished Aug 04 05:41:40 PM PDT 24
Peak memory 215708 kb
Host smart-c97e3711-4a7a-4d22-a2c3-25235246342a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739259465 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3739259465
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.262915449
Short name T585
Test name
Test status
Simulation time 40636572 ps
CPU time 0.9 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:46 PM PDT 24
Peak memory 214308 kb
Host smart-cb6e1a18-06cd-4648-b83c-26206eaa81de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262915449 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.262915449
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2300628704
Short name T529
Test name
Test status
Simulation time 150851981 ps
CPU time 3.09 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 217216 kb
Host smart-941b5a23-eeec-442b-bb89-6b5f15797397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300628704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2300628704
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1060211197
Short name T606
Test name
Test status
Simulation time 33406463454 ps
CPU time 745.86 seconds
Started Aug 04 05:41:36 PM PDT 24
Finished Aug 04 05:54:02 PM PDT 24
Peak memory 223752 kb
Host smart-74d05ebb-c5c5-4959-8a09-983b7a94d1aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060211197 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1060211197
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.924551195
Short name T554
Test name
Test status
Simulation time 73617466 ps
CPU time 1.12 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:46 PM PDT 24
Peak memory 219768 kb
Host smart-e5c91634-4525-425a-ab80-c2ccb31fa65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924551195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.924551195
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1406520916
Short name T398
Test name
Test status
Simulation time 15897726 ps
CPU time 0.99 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 206756 kb
Host smart-f0c70ad4-f73f-455f-a4d0-ddc4556e69b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406520916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1406520916
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1643224338
Short name T921
Test name
Test status
Simulation time 16458216 ps
CPU time 0.84 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 216208 kb
Host smart-25fbbc42-abd0-4360-975a-56837053b4e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643224338 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1643224338
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.167674335
Short name T808
Test name
Test status
Simulation time 74333758 ps
CPU time 0.93 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 218320 kb
Host smart-867e998c-8be1-4bad-a448-e2783e3e5f83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167674335 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.167674335
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.4028462386
Short name T190
Test name
Test status
Simulation time 23659427 ps
CPU time 1.01 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 224024 kb
Host smart-7d5c4c9f-8ea5-4db7-b647-a3783d7c7a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028462386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.4028462386
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3841201045
Short name T497
Test name
Test status
Simulation time 70518929 ps
CPU time 1.16 seconds
Started Aug 04 05:41:41 PM PDT 24
Finished Aug 04 05:41:42 PM PDT 24
Peak memory 218420 kb
Host smart-e8f556ae-17c9-44ae-a6e0-9d2d3dce8981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841201045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3841201045
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.380255979
Short name T75
Test name
Test status
Simulation time 33551485 ps
CPU time 0.88 seconds
Started Aug 04 05:41:40 PM PDT 24
Finished Aug 04 05:41:41 PM PDT 24
Peak memory 215616 kb
Host smart-8f403ccd-eeff-42b4-a69c-445a5fd5742d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380255979 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.380255979
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1713439644
Short name T726
Test name
Test status
Simulation time 17841927 ps
CPU time 0.98 seconds
Started Aug 04 05:41:57 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 215144 kb
Host smart-40d1498b-6257-4bc8-902c-87ee04f629be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713439644 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1713439644
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1486237584
Short name T634
Test name
Test status
Simulation time 423408959 ps
CPU time 4.93 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 217224 kb
Host smart-e3c447ec-1a87-4227-8d21-81f08f1899e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486237584 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1486237584
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1645255670
Short name T705
Test name
Test status
Simulation time 268366375866 ps
CPU time 1605.87 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 06:08:33 PM PDT 24
Peak memory 225296 kb
Host smart-64c47868-a310-4c87-8add-418d84859067
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645255670 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1645255670
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3483969772
Short name T410
Test name
Test status
Simulation time 79440345 ps
CPU time 1.2 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:57 PM PDT 24
Peak memory 221708 kb
Host smart-5536218a-ac49-4aeb-9751-3a31654df231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483969772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3483969772
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1439422175
Short name T487
Test name
Test status
Simulation time 16099605 ps
CPU time 0.89 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 206692 kb
Host smart-1632309f-a5e2-4756-9221-99093341fb03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439422175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1439422175
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2399688165
Short name T939
Test name
Test status
Simulation time 11236467 ps
CPU time 0.92 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 216332 kb
Host smart-fb84b63e-c25b-4229-adfb-7d0bce4faa70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399688165 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2399688165
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.4229955083
Short name T511
Test name
Test status
Simulation time 71517289 ps
CPU time 0.98 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 218280 kb
Host smart-0b076d09-3663-48b4-b384-f3e588b7aab1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229955083 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.4229955083
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1876227067
Short name T2
Test name
Test status
Simulation time 48214115 ps
CPU time 0.97 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 218512 kb
Host smart-bc2e3ec0-0ef4-438e-ba4a-fbe23a242b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876227067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1876227067
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2804091663
Short name T336
Test name
Test status
Simulation time 59940511 ps
CPU time 1.62 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 218832 kb
Host smart-3b1fb09e-7800-4b04-977d-1320e5a3817a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804091663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2804091663
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.438340033
Short name T480
Test name
Test status
Simulation time 22006969 ps
CPU time 1.05 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 215560 kb
Host smart-cd32fabf-f398-45a2-97ef-5731c48eb935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438340033 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.438340033
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3872331470
Short name T791
Test name
Test status
Simulation time 59930405 ps
CPU time 0.95 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 215320 kb
Host smart-369964f4-db63-421a-85e2-093677cf2d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872331470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3872331470
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2062543806
Short name T127
Test name
Test status
Simulation time 65316128 ps
CPU time 1.75 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 218492 kb
Host smart-f8c69c6b-9c41-484c-b4c8-30db3b841d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062543806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2062543806
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1262128715
Short name T853
Test name
Test status
Simulation time 400233251021 ps
CPU time 2307.64 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 06:20:12 PM PDT 24
Peak memory 227284 kb
Host smart-1804c7ec-b553-4a89-a044-a9690d8f1752
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262128715 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1262128715
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2350477963
Short name T198
Test name
Test status
Simulation time 32074784 ps
CPU time 1.11 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 219704 kb
Host smart-90d9dc8b-a5f9-4762-936a-f7fa0ce712db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350477963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2350477963
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.4093794703
Short name T423
Test name
Test status
Simulation time 108766741 ps
CPU time 0.9 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 206768 kb
Host smart-b412bc7f-0e31-4328-b19f-c7d4f0d37883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093794703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.4093794703
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1750729090
Short name T193
Test name
Test status
Simulation time 20682534 ps
CPU time 0.85 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 216232 kb
Host smart-bd279e40-bf4d-4b38-8165-55e82f3c71e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750729090 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1750729090
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2501964024
Short name T87
Test name
Test status
Simulation time 27467263 ps
CPU time 1.05 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 216880 kb
Host smart-eda93792-b7db-4c0f-83a2-43b9315e6e7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501964024 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2501964024
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3011550323
Short name T117
Test name
Test status
Simulation time 20552876 ps
CPU time 1.02 seconds
Started Aug 04 05:41:39 PM PDT 24
Finished Aug 04 05:41:40 PM PDT 24
Peak memory 218504 kb
Host smart-23f1d196-875a-40ed-803c-3c5981d647f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011550323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3011550323
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.4211763326
Short name T486
Test name
Test status
Simulation time 58094978 ps
CPU time 1.4 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 218720 kb
Host smart-a18cde23-7047-4cc6-817c-747552240afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211763326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4211763326
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2547601197
Short name T118
Test name
Test status
Simulation time 46129465 ps
CPU time 0.83 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:43 PM PDT 24
Peak memory 215556 kb
Host smart-6dcba9a3-f5df-4271-8282-4031624e7d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547601197 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2547601197
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3776903224
Short name T953
Test name
Test status
Simulation time 26432527 ps
CPU time 0.94 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:46 PM PDT 24
Peak memory 215224 kb
Host smart-563ecb03-a576-4346-9f96-b3954a4ec30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776903224 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3776903224
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3985249776
Short name T493
Test name
Test status
Simulation time 841710238 ps
CPU time 4.77 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 215216 kb
Host smart-0e4ba21c-3059-4a14-9520-6c485bb2a07c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985249776 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3985249776
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2911050951
Short name T617
Test name
Test status
Simulation time 90213068661 ps
CPU time 592.75 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:51:37 PM PDT 24
Peak memory 220548 kb
Host smart-d526d0cc-f88e-44bf-a979-f1ce248904ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911050951 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2911050951
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3332614967
Short name T659
Test name
Test status
Simulation time 44691615 ps
CPU time 1.2 seconds
Started Aug 04 05:40:56 PM PDT 24
Finished Aug 04 05:40:58 PM PDT 24
Peak memory 220996 kb
Host smart-2c24d399-fca3-4a99-8cff-aeb78ea88400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332614967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3332614967
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.862345662
Short name T607
Test name
Test status
Simulation time 24088941 ps
CPU time 0.87 seconds
Started Aug 04 05:40:50 PM PDT 24
Finished Aug 04 05:40:52 PM PDT 24
Peak memory 206744 kb
Host smart-cf3d3599-ed5a-4357-9dc3-20bffce192be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862345662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.862345662
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.691242274
Short name T850
Test name
Test status
Simulation time 21306605 ps
CPU time 0.9 seconds
Started Aug 04 05:40:55 PM PDT 24
Finished Aug 04 05:40:56 PM PDT 24
Peak memory 216524 kb
Host smart-fcbd3633-47d8-4df2-8d8f-837cd204e024
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691242274 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.691242274
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.385914848
Short name T89
Test name
Test status
Simulation time 28937000 ps
CPU time 0.89 seconds
Started Aug 04 05:40:53 PM PDT 24
Finished Aug 04 05:40:54 PM PDT 24
Peak memory 218488 kb
Host smart-fdd94c81-c770-4ac2-a3fd-29617fc32a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385914848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.385914848
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_intr.919765944
Short name T79
Test name
Test status
Simulation time 21835518 ps
CPU time 0.95 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:40:47 PM PDT 24
Peak memory 215948 kb
Host smart-87f3ce4a-4478-42c3-8880-ce5084f5d36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919765944 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.919765944
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2260543012
Short name T71
Test name
Test status
Simulation time 43774082 ps
CPU time 0.96 seconds
Started Aug 04 05:40:40 PM PDT 24
Finished Aug 04 05:40:41 PM PDT 24
Peak memory 207100 kb
Host smart-da62dce3-2d9f-4df2-bd0b-74cf4f071bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260543012 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2260543012
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.2229333043
Short name T738
Test name
Test status
Simulation time 15642779 ps
CPU time 0.98 seconds
Started Aug 04 05:40:51 PM PDT 24
Finished Aug 04 05:40:52 PM PDT 24
Peak memory 215352 kb
Host smart-636ff8f5-4113-4dfa-a0d6-196328981e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229333043 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2229333043
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1582439253
Short name T851
Test name
Test status
Simulation time 316008480 ps
CPU time 5.95 seconds
Started Aug 04 05:40:43 PM PDT 24
Finished Aug 04 05:40:49 PM PDT 24
Peak memory 217484 kb
Host smart-732ca201-f4b9-4d1e-b08a-eefc9c875ae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582439253 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1582439253
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2345726977
Short name T707
Test name
Test status
Simulation time 154858823374 ps
CPU time 1002.39 seconds
Started Aug 04 05:40:55 PM PDT 24
Finished Aug 04 05:57:37 PM PDT 24
Peak memory 224220 kb
Host smart-e1fc491c-12d0-4796-a745-0ecf2936b1b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345726977 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2345726977
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2986144578
Short name T538
Test name
Test status
Simulation time 28399674 ps
CPU time 1.17 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 220556 kb
Host smart-7ecd13fe-0d36-4016-b3d9-f356a7cdccce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986144578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2986144578
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1614456443
Short name T839
Test name
Test status
Simulation time 149788592 ps
CPU time 0.88 seconds
Started Aug 04 05:41:40 PM PDT 24
Finished Aug 04 05:41:41 PM PDT 24
Peak memory 206428 kb
Host smart-32271f0d-bd2a-4f26-b8bd-1c6aa3d97cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614456443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1614456443
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3386732078
Short name T757
Test name
Test status
Simulation time 190330687 ps
CPU time 0.86 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 215936 kb
Host smart-e7a0e0ee-5e01-4b09-a480-408eb695165e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386732078 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3386732078
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1158995833
Short name T171
Test name
Test status
Simulation time 349976007 ps
CPU time 1.19 seconds
Started Aug 04 05:41:41 PM PDT 24
Finished Aug 04 05:41:43 PM PDT 24
Peak memory 216984 kb
Host smart-4e0c2f31-8d71-44c5-96b5-a7f919a53e3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158995833 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1158995833
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.555100523
Short name T175
Test name
Test status
Simulation time 28783285 ps
CPU time 1.32 seconds
Started Aug 04 05:41:35 PM PDT 24
Finished Aug 04 05:41:37 PM PDT 24
Peak memory 225884 kb
Host smart-1b52b49d-7959-4f59-a2ac-937dcd92e116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555100523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.555100523
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2385997682
Short name T54
Test name
Test status
Simulation time 39913021 ps
CPU time 1.51 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 218508 kb
Host smart-80608fbb-2479-4124-a50c-3c18ae85cdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385997682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2385997682
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.960148027
Short name T44
Test name
Test status
Simulation time 22444575 ps
CPU time 0.99 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 215880 kb
Host smart-b559cd45-d7fa-4699-be2c-52c031e7ea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960148027 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.960148027
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3670355625
Short name T608
Test name
Test status
Simulation time 17698472 ps
CPU time 1 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 215372 kb
Host smart-3c14f6ac-65c5-4300-9292-11b6410fdd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670355625 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3670355625
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2285600278
Short name T389
Test name
Test status
Simulation time 276712854 ps
CPU time 3.16 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:51 PM PDT 24
Peak memory 217428 kb
Host smart-ebf92f5f-f16f-474a-b647-6b7087600756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285600278 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2285600278
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1334413369
Short name T557
Test name
Test status
Simulation time 222049851894 ps
CPU time 1074.57 seconds
Started Aug 04 05:41:35 PM PDT 24
Finished Aug 04 05:59:30 PM PDT 24
Peak memory 223860 kb
Host smart-ef8480bc-300a-422b-9b05-e86f361f8e28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334413369 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1334413369
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3048685942
Short name T135
Test name
Test status
Simulation time 25779614 ps
CPU time 1.26 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 219840 kb
Host smart-3ea04164-6593-4d0c-bc1c-a6deab71d11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048685942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3048685942
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2756178285
Short name T504
Test name
Test status
Simulation time 12803033 ps
CPU time 0.9 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 206960 kb
Host smart-407c717c-2b94-4559-ab89-e97d76c53f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756178285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2756178285
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3720942539
Short name T624
Test name
Test status
Simulation time 17022076 ps
CPU time 0.85 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 215956 kb
Host smart-eb1796d4-5d53-4ec4-9736-bbad2a214de9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720942539 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3720942539
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.4241217890
Short name T113
Test name
Test status
Simulation time 66284592 ps
CPU time 1.01 seconds
Started Aug 04 05:41:50 PM PDT 24
Finished Aug 04 05:41:51 PM PDT 24
Peak memory 216880 kb
Host smart-c5bceb23-2b95-4e11-8ecb-88ce50b1f80d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241217890 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.4241217890
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2504580509
Short name T388
Test name
Test status
Simulation time 18893310 ps
CPU time 1.12 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 218472 kb
Host smart-2619728b-7d30-4a76-a74f-7a1d4b0c98b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504580509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2504580509
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3813565224
Short name T518
Test name
Test status
Simulation time 56215308 ps
CPU time 1.52 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 218496 kb
Host smart-e088bdfe-bffb-4544-bd0c-eb0f4974dd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813565224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3813565224
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1747164060
Short name T828
Test name
Test status
Simulation time 33270132 ps
CPU time 0.82 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 215504 kb
Host smart-b60a22f1-1a41-4c0b-93e8-0316a38d64b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747164060 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1747164060
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.4052430632
Short name T350
Test name
Test status
Simulation time 31113233 ps
CPU time 1.04 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:43 PM PDT 24
Peak memory 215276 kb
Host smart-23baf6a2-641c-4aed-9c18-55878779a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052430632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.4052430632
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1977534724
Short name T4
Test name
Test status
Simulation time 162772654 ps
CPU time 1.49 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 217344 kb
Host smart-47a727a2-bd13-45b8-a935-8d01d2253e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977534724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1977534724
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2517871565
Short name T949
Test name
Test status
Simulation time 592025945515 ps
CPU time 2812.54 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 06:28:35 PM PDT 24
Peak memory 232768 kb
Host smart-8d5397c5-93ec-48cb-be43-c229bab818f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517871565 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2517871565
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2803018577
Short name T484
Test name
Test status
Simulation time 32438805 ps
CPU time 1.19 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 218524 kb
Host smart-33f82b21-78a1-4a67-953e-6e29f84adbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803018577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2803018577
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.770016197
Short name T342
Test name
Test status
Simulation time 21075177 ps
CPU time 0.89 seconds
Started Aug 04 05:41:50 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 206716 kb
Host smart-a26b086e-f62e-48ec-a25e-0b2cde92d39a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770016197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.770016197
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1545688791
Short name T980
Test name
Test status
Simulation time 19277760 ps
CPU time 0.84 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 216252 kb
Host smart-c5ab7e09-1c90-4400-b0ea-1579fbf72c9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545688791 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1545688791
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.457759979
Short name T763
Test name
Test status
Simulation time 50247236 ps
CPU time 1.08 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 216964 kb
Host smart-6c9b7a48-7dff-4ae8-a6f1-6a799b7db271
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457759979 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.457759979
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3245232282
Short name T951
Test name
Test status
Simulation time 21014741 ps
CPU time 1.02 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 218656 kb
Host smart-00bde848-1a5c-4f4c-974e-74250325917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245232282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3245232282
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3097154033
Short name T386
Test name
Test status
Simulation time 50948969 ps
CPU time 1.22 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 218560 kb
Host smart-8ee2fa11-2211-416c-ad60-aee26289af2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097154033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3097154033
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2454368323
Short name T877
Test name
Test status
Simulation time 23125371 ps
CPU time 1.22 seconds
Started Aug 04 05:41:54 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 224020 kb
Host smart-149c6974-13a4-43a3-bed4-5b9421595c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454368323 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2454368323
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2299433006
Short name T920
Test name
Test status
Simulation time 47278922 ps
CPU time 0.86 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 215236 kb
Host smart-91440340-206c-495f-9d9f-a5cd4254afe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299433006 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2299433006
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3709717974
Short name T443
Test name
Test status
Simulation time 943823156 ps
CPU time 3.86 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 217204 kb
Host smart-5f684501-0b31-4541-9d1a-7867fb7b7b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709717974 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3709717974
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3447953749
Short name T541
Test name
Test status
Simulation time 27389490649 ps
CPU time 696.85 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:53:22 PM PDT 24
Peak memory 218632 kb
Host smart-09d68228-b5fc-4ef2-a810-5398f3f4cefd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447953749 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3447953749
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2873259708
Short name T647
Test name
Test status
Simulation time 55545646 ps
CPU time 1.33 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 220032 kb
Host smart-80035285-6b84-4a93-949d-1fb18da4733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873259708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2873259708
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1441134256
Short name T52
Test name
Test status
Simulation time 26147463 ps
CPU time 0.91 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:43 PM PDT 24
Peak memory 206732 kb
Host smart-e6abc688-5bc0-4182-a5c6-0e8cc1ace643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441134256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1441134256
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.106034279
Short name T821
Test name
Test status
Simulation time 54188267 ps
CPU time 0.82 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 216256 kb
Host smart-71fbe1d5-af66-45a4-8ddf-4427157feb8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106034279 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.106034279
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1271278488
Short name T968
Test name
Test status
Simulation time 36964664 ps
CPU time 1.3 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 216992 kb
Host smart-67052035-79ab-4682-a262-d9a3d6055ce2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271278488 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1271278488
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1805483892
Short name T39
Test name
Test status
Simulation time 47395815 ps
CPU time 0.99 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 05:41:43 PM PDT 24
Peak memory 223876 kb
Host smart-30d953a2-ef08-4f6b-8b26-c586bcbf072c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805483892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1805483892
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2568495180
Short name T638
Test name
Test status
Simulation time 82430001 ps
CPU time 1.2 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 217324 kb
Host smart-e6d3a316-4dc6-4582-a965-6a5034b4eb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568495180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2568495180
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2040869919
Short name T414
Test name
Test status
Simulation time 37461235 ps
CPU time 0.96 seconds
Started Aug 04 05:41:41 PM PDT 24
Finished Aug 04 05:41:42 PM PDT 24
Peak memory 224044 kb
Host smart-62dbdb18-2c16-4f3e-a608-93d2f94b5def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040869919 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2040869919
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.320787184
Short name T747
Test name
Test status
Simulation time 17932208 ps
CPU time 0.98 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 215212 kb
Host smart-6574c405-ce38-4ad0-acad-9cbde775f0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320787184 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.320787184
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1384253106
Short name T417
Test name
Test status
Simulation time 402056433 ps
CPU time 7.42 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:42:01 PM PDT 24
Peak memory 217232 kb
Host smart-8498e86b-6eda-4ac3-8fb5-e81fa08e2cd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384253106 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1384253106
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3330050333
Short name T450
Test name
Test status
Simulation time 140117284491 ps
CPU time 1799.03 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 06:11:43 PM PDT 24
Peak memory 227484 kb
Host smart-cc2b5d22-6d23-4313-b7c5-e3c5d403814d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330050333 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3330050333
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1016427807
Short name T792
Test name
Test status
Simulation time 180743842 ps
CPU time 1.12 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:53 PM PDT 24
Peak memory 218616 kb
Host smart-e51c081a-a817-43d6-8aa9-90c7bf87e9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016427807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1016427807
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.946191802
Short name T749
Test name
Test status
Simulation time 60737306 ps
CPU time 0.89 seconds
Started Aug 04 05:41:54 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 214904 kb
Host smart-8c6edc8f-90e3-44df-a74a-1e7caf91bf72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946191802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.946191802
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1363720754
Short name T973
Test name
Test status
Simulation time 15992675 ps
CPU time 0.82 seconds
Started Aug 04 05:41:52 PM PDT 24
Finished Aug 04 05:41:53 PM PDT 24
Peak memory 207144 kb
Host smart-94f16618-0744-4317-aafd-c2d8c3bc8335
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363720754 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1363720754
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2967159932
Short name T170
Test name
Test status
Simulation time 53473498 ps
CPU time 1.14 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 216816 kb
Host smart-2e68089a-74fa-49ff-9bee-52e0bfdeb014
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967159932 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2967159932
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.335746460
Short name T579
Test name
Test status
Simulation time 21172917 ps
CPU time 1.08 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 219556 kb
Host smart-0cb583a0-7dc9-4d95-8fc1-e044937a0190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335746460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.335746460
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2400234605
Short name T327
Test name
Test status
Simulation time 82378313 ps
CPU time 1.2 seconds
Started Aug 04 05:41:40 PM PDT 24
Finished Aug 04 05:41:42 PM PDT 24
Peak memory 218620 kb
Host smart-59f02129-1c2a-4e61-b454-cb21336b3723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400234605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2400234605
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.4098094161
Short name T769
Test name
Test status
Simulation time 44097149 ps
CPU time 0.94 seconds
Started Aug 04 05:41:38 PM PDT 24
Finished Aug 04 05:41:39 PM PDT 24
Peak memory 223828 kb
Host smart-99dbc537-8e55-46fa-aa62-59977482301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098094161 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.4098094161
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2122796037
Short name T736
Test name
Test status
Simulation time 27280000 ps
CPU time 1.02 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 215296 kb
Host smart-b3b5b0bd-d229-43d0-852f-1220ecc374b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122796037 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2122796037
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3872608284
Short name T403
Test name
Test status
Simulation time 483972748 ps
CPU time 2.92 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:51 PM PDT 24
Peak memory 220132 kb
Host smart-b3331065-b5ba-4f0d-825b-7522eec8cb5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872608284 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3872608284
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_alert.962790802
Short name T672
Test name
Test status
Simulation time 37297253 ps
CPU time 1.1 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 219436 kb
Host smart-1729d7da-1792-4ccb-b1a3-de60576962eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962790802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.962790802
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3613458513
Short name T700
Test name
Test status
Simulation time 15653641 ps
CPU time 0.97 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 214868 kb
Host smart-a37985ac-0a0a-48de-b9f0-dbacfc17d53d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613458513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3613458513
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3554522620
Short name T987
Test name
Test status
Simulation time 41491571 ps
CPU time 0.79 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 216260 kb
Host smart-20128ee1-ef38-4e76-b550-c7532bef12a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554522620 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3554522620
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.4123097310
Short name T629
Test name
Test status
Simulation time 117357218 ps
CPU time 1.29 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 216736 kb
Host smart-1ae272fa-d818-4ab1-87af-2caf062361e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123097310 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.4123097310
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2566549492
Short name T41
Test name
Test status
Simulation time 19615337 ps
CPU time 1.22 seconds
Started Aug 04 05:41:52 PM PDT 24
Finished Aug 04 05:41:53 PM PDT 24
Peak memory 224032 kb
Host smart-94ff644d-2f17-4847-a579-29a97232cc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566549492 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2566549492
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_intr.3671161448
Short name T594
Test name
Test status
Simulation time 27132878 ps
CPU time 0.94 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:46 PM PDT 24
Peak memory 215528 kb
Host smart-8ac65636-c173-4c79-b9f7-153e5954e9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671161448 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3671161448
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.130365462
Short name T946
Test name
Test status
Simulation time 16311041 ps
CPU time 0.99 seconds
Started Aug 04 05:41:52 PM PDT 24
Finished Aug 04 05:41:53 PM PDT 24
Peak memory 215260 kb
Host smart-8bf0a4b6-65aa-4a11-8d44-0a6094d0690a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130365462 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.130365462
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2475018976
Short name T609
Test name
Test status
Simulation time 405074585 ps
CPU time 4.2 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:51 PM PDT 24
Peak memory 217132 kb
Host smart-c765eddb-d86f-4436-9f4d-8bfa881111f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475018976 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2475018976
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2643145852
Short name T458
Test name
Test status
Simulation time 57238189388 ps
CPU time 790.25 seconds
Started Aug 04 05:41:54 PM PDT 24
Finished Aug 04 05:55:04 PM PDT 24
Peak memory 223708 kb
Host smart-fbd6a10c-d0cb-4df5-bf70-3e1dd79c436f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643145852 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2643145852
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1101128373
Short name T810
Test name
Test status
Simulation time 22864022 ps
CPU time 1.19 seconds
Started Aug 04 05:41:50 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 218696 kb
Host smart-031c8027-199b-4be8-bbbd-c33c37ef6406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101128373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1101128373
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1120833699
Short name T625
Test name
Test status
Simulation time 18904931 ps
CPU time 0.85 seconds
Started Aug 04 05:41:50 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 206520 kb
Host smart-2bbe5f41-52e9-4795-854c-488f2b885726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120833699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1120833699
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1909375249
Short name T180
Test name
Test status
Simulation time 36088422 ps
CPU time 0.82 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 215332 kb
Host smart-dda068d7-3ee0-4316-b006-533bd61cc762
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909375249 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1909375249
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2200767408
Short name T167
Test name
Test status
Simulation time 61354050 ps
CPU time 1.21 seconds
Started Aug 04 05:41:52 PM PDT 24
Finished Aug 04 05:41:53 PM PDT 24
Peak memory 216964 kb
Host smart-da0a9c57-4c62-4c93-8a0a-340f93f51c53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200767408 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2200767408
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1482840426
Short name T5
Test name
Test status
Simulation time 20854434 ps
CPU time 1.11 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 219772 kb
Host smart-cd62244a-cc8a-4ccb-9aec-684b946f135b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482840426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1482840426
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3780938992
Short name T357
Test name
Test status
Simulation time 30205992 ps
CPU time 1.21 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 217340 kb
Host smart-9ac17d59-8399-4b41-b110-d6af832b4ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780938992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3780938992
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3175402614
Short name T755
Test name
Test status
Simulation time 72500611 ps
CPU time 0.91 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 223844 kb
Host smart-bf720025-ab8e-463c-8fc9-8680aae3ba08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175402614 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3175402614
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1409498294
Short name T729
Test name
Test status
Simulation time 51727707 ps
CPU time 0.92 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 215240 kb
Host smart-66f65242-43fc-4360-a5e8-1fae77919137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409498294 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1409498294
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1529285190
Short name T433
Test name
Test status
Simulation time 231983581 ps
CPU time 2.99 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:46 PM PDT 24
Peak memory 219484 kb
Host smart-c15cc370-13b8-4267-9ee2-9e771735e2a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529285190 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1529285190
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2828328168
Short name T618
Test name
Test status
Simulation time 525717326439 ps
CPU time 1606.86 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 06:08:33 PM PDT 24
Peak memory 224292 kb
Host smart-03803e94-3792-4d8d-a7aa-2081766161bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828328168 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2828328168
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3354941310
Short name T888
Test name
Test status
Simulation time 20918476 ps
CPU time 1.26 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 218460 kb
Host smart-fe38ee30-376c-43fe-8835-1e86ac4eb6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354941310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3354941310
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1330228332
Short name T819
Test name
Test status
Simulation time 180877592 ps
CPU time 0.98 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:51 PM PDT 24
Peak memory 206832 kb
Host smart-44a20126-143e-41de-8f51-ea1bf0673243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330228332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1330228332
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2019758977
Short name T546
Test name
Test status
Simulation time 194537648 ps
CPU time 1.24 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 216816 kb
Host smart-0b6e5ee3-49ed-4d30-a277-51d76258d9ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019758977 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2019758977
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2883411465
Short name T754
Test name
Test status
Simulation time 111569735 ps
CPU time 1.06 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 224200 kb
Host smart-8f260031-d8df-4693-8ff7-aa09e4495aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883411465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2883411465
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3963053531
Short name T238
Test name
Test status
Simulation time 74711795 ps
CPU time 1.04 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 215200 kb
Host smart-2b8c6676-6337-4d89-9ede-be4b20c723f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963053531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3963053531
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.480078794
Short name T725
Test name
Test status
Simulation time 27394397 ps
CPU time 1.15 seconds
Started Aug 04 05:41:38 PM PDT 24
Finished Aug 04 05:41:39 PM PDT 24
Peak memory 215508 kb
Host smart-a9410c2d-73c0-43c3-a6fc-f76cab748181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480078794 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.480078794
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3908136897
Short name T857
Test name
Test status
Simulation time 24674866 ps
CPU time 0.92 seconds
Started Aug 04 05:41:54 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 215296 kb
Host smart-7e1c8e89-b20f-4ffd-b46b-944ab8539ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908136897 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3908136897
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3802136714
Short name T768
Test name
Test status
Simulation time 99845714 ps
CPU time 2.32 seconds
Started Aug 04 05:41:59 PM PDT 24
Finished Aug 04 05:42:01 PM PDT 24
Peak memory 217252 kb
Host smart-7018452d-6b8a-4f9d-ad19-50f5d2579c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802136714 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3802136714
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.464773234
Short name T235
Test name
Test status
Simulation time 71601254057 ps
CPU time 1527.14 seconds
Started Aug 04 05:41:50 PM PDT 24
Finished Aug 04 06:07:17 PM PDT 24
Peak memory 222716 kb
Host smart-6f5cd370-c333-4538-ae75-2896e30fac28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464773234 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.464773234
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.226003724
Short name T407
Test name
Test status
Simulation time 47732696 ps
CPU time 1.2 seconds
Started Aug 04 05:41:54 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 221316 kb
Host smart-23bdb625-388d-4183-8cd9-f27ea647b406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226003724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.226003724
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.239998022
Short name T46
Test name
Test status
Simulation time 18499613 ps
CPU time 1.07 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 206752 kb
Host smart-574f2263-410a-4946-8d8e-6b54f00d4a33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239998022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.239998022
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2434499827
Short name T681
Test name
Test status
Simulation time 25387237 ps
CPU time 0.9 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 215956 kb
Host smart-ec5fae3d-1023-428d-a7dc-eb3c8902d66b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434499827 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2434499827
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1616707194
Short name T26
Test name
Test status
Simulation time 54026119 ps
CPU time 0.94 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 216832 kb
Host smart-0f26ce89-8e72-41d9-8d70-cca3cf3c088c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616707194 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1616707194
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.4152459322
Short name T191
Test name
Test status
Simulation time 21429842 ps
CPU time 0.93 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:56 PM PDT 24
Peak memory 218352 kb
Host smart-4f0ce118-f1f0-4ff4-bc30-d3b428d82101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152459322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.4152459322
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.933072245
Short name T475
Test name
Test status
Simulation time 91132644 ps
CPU time 1.24 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 218692 kb
Host smart-b9c98dbd-b993-4eac-adb5-fea3c2bb0208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933072245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.933072245
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3062444571
Short name T119
Test name
Test status
Simulation time 35606171 ps
CPU time 0.84 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 215504 kb
Host smart-bf406926-70f1-4626-bda6-e3a412d090dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062444571 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3062444571
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2862015608
Short name T950
Test name
Test status
Simulation time 73782073 ps
CPU time 0.89 seconds
Started Aug 04 05:41:52 PM PDT 24
Finished Aug 04 05:41:53 PM PDT 24
Peak memory 215300 kb
Host smart-9a53897f-ca57-44fd-9f1d-d1c17b06c20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862015608 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2862015608
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.220669973
Short name T643
Test name
Test status
Simulation time 113273104 ps
CPU time 1.77 seconds
Started Aug 04 05:41:50 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 217172 kb
Host smart-5d69e98c-00dc-45d4-bc84-8dc1bf761622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220669973 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.220669973
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1317348594
Short name T794
Test name
Test status
Simulation time 90485633021 ps
CPU time 1944.23 seconds
Started Aug 04 05:41:42 PM PDT 24
Finished Aug 04 06:14:07 PM PDT 24
Peak memory 226340 kb
Host smart-b1a41768-5a75-4b39-9a1e-f4350a038ae8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317348594 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1317348594
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3703969975
Short name T245
Test name
Test status
Simulation time 28945623 ps
CPU time 1.33 seconds
Started Aug 04 05:41:52 PM PDT 24
Finished Aug 04 05:41:53 PM PDT 24
Peak memory 219420 kb
Host smart-1472fbe3-2846-45c7-9a6c-08973ee04113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703969975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3703969975
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1876647433
Short name T613
Test name
Test status
Simulation time 55184316 ps
CPU time 0.84 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:51 PM PDT 24
Peak memory 206116 kb
Host smart-5d97536d-5fd6-4e74-914d-b5e3955b1b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876647433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1876647433
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_err.2220361417
Short name T147
Test name
Test status
Simulation time 23959799 ps
CPU time 1.29 seconds
Started Aug 04 05:41:54 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 229672 kb
Host smart-b79f27d1-40a2-4de0-9f5f-94b2db898f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220361417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2220361417
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3772423565
Short name T10
Test name
Test status
Simulation time 78419912 ps
CPU time 1.18 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:46 PM PDT 24
Peak memory 218768 kb
Host smart-c1f007fc-bbf2-4268-a846-bc782ec963d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772423565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3772423565
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1540812469
Short name T960
Test name
Test status
Simulation time 21391068 ps
CPU time 1.08 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:51 PM PDT 24
Peak memory 215304 kb
Host smart-f78d041d-f666-4abb-8e99-0d010187517d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540812469 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1540812469
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3520138323
Short name T914
Test name
Test status
Simulation time 18382250 ps
CPU time 1.01 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 207128 kb
Host smart-9cbca0e1-4603-427a-a6c1-a6ff6695d2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520138323 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3520138323
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.4068973798
Short name T627
Test name
Test status
Simulation time 319568400 ps
CPU time 5.95 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 217204 kb
Host smart-97e20ac0-4662-45d4-95cc-8eecb7c1fc73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068973798 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.4068973798
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1644095257
Short name T823
Test name
Test status
Simulation time 77119985421 ps
CPU time 993.22 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:58:25 PM PDT 24
Peak memory 223736 kb
Host smart-c055715b-fcf6-4de5-b16c-c9b14bcaf971
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644095257 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1644095257
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.360969784
Short name T967
Test name
Test status
Simulation time 114060951 ps
CPU time 1.31 seconds
Started Aug 04 05:41:00 PM PDT 24
Finished Aug 04 05:41:01 PM PDT 24
Peak memory 215680 kb
Host smart-91e852f2-eaa5-499f-bb78-5f19660b076c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360969784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.360969784
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3414584339
Short name T879
Test name
Test status
Simulation time 23834814 ps
CPU time 0.91 seconds
Started Aug 04 05:40:51 PM PDT 24
Finished Aug 04 05:40:52 PM PDT 24
Peak memory 206716 kb
Host smart-45f34288-e4c4-4210-9dd7-99818fa208d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414584339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3414584339
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2586713184
Short name T178
Test name
Test status
Simulation time 12025682 ps
CPU time 0.91 seconds
Started Aug 04 05:40:46 PM PDT 24
Finished Aug 04 05:40:47 PM PDT 24
Peak memory 215384 kb
Host smart-d48912c8-6163-4d43-8f2f-15effeb99dce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586713184 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2586713184
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2704317274
Short name T155
Test name
Test status
Simulation time 226358994 ps
CPU time 1.28 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:40:46 PM PDT 24
Peak memory 216788 kb
Host smart-55983aaa-08e5-43b1-9bed-1edad46d3189
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704317274 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2704317274
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.873073949
Short name T152
Test name
Test status
Simulation time 204830749 ps
CPU time 1.08 seconds
Started Aug 04 05:40:58 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 219380 kb
Host smart-ce55b873-8ce3-4eba-9d04-6b022cb0aff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873073949 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.873073949
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3134782142
Short name T815
Test name
Test status
Simulation time 75451501 ps
CPU time 1.28 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:40:46 PM PDT 24
Peak memory 218524 kb
Host smart-cb316de4-3d75-4b4e-ab47-4536290172a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134782142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3134782142
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1455595516
Short name T955
Test name
Test status
Simulation time 20876782 ps
CPU time 1.02 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:40:46 PM PDT 24
Peak memory 215368 kb
Host smart-c5e85259-c252-4a1a-937e-2ec5bf12540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455595516 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1455595516
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.827628864
Short name T745
Test name
Test status
Simulation time 23514708 ps
CPU time 0.97 seconds
Started Aug 04 05:40:55 PM PDT 24
Finished Aug 04 05:40:56 PM PDT 24
Peak memory 207088 kb
Host smart-4af00e67-4132-4a57-9f9e-53757ab5bcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827628864 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.827628864
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1018439235
Short name T527
Test name
Test status
Simulation time 27345803 ps
CPU time 0.92 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:40:46 PM PDT 24
Peak memory 214776 kb
Host smart-957c68fd-b4bf-474e-9bd8-a443d1845315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018439235 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1018439235
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.566100639
Short name T496
Test name
Test status
Simulation time 386046456 ps
CPU time 4.62 seconds
Started Aug 04 05:40:46 PM PDT 24
Finished Aug 04 05:40:50 PM PDT 24
Peak memory 217272 kb
Host smart-323f3681-8332-4414-8fe5-bf0cc75e5507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566100639 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.566100639
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1208821004
Short name T230
Test name
Test status
Simulation time 35696838402 ps
CPU time 757.9 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:53:23 PM PDT 24
Peak memory 218212 kb
Host smart-47ee9415-f35a-4ccb-9a0a-40742f59555d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208821004 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1208821004
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2573481470
Short name T804
Test name
Test status
Simulation time 23912961 ps
CPU time 1.2 seconds
Started Aug 04 05:41:45 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 218532 kb
Host smart-bdf537eb-e1e9-49fc-83ce-e1e8392511f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573481470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2573481470
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.958534373
Short name T732
Test name
Test status
Simulation time 23912627 ps
CPU time 0.92 seconds
Started Aug 04 05:41:56 PM PDT 24
Finished Aug 04 05:41:57 PM PDT 24
Peak memory 218724 kb
Host smart-62530d47-f0fb-4935-b8be-e375b37e9d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958534373 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.958534373
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3912588162
Short name T818
Test name
Test status
Simulation time 44429315 ps
CPU time 1.59 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:53 PM PDT 24
Peak memory 218492 kb
Host smart-31fca879-5363-45e1-af11-488bf6f619ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912588162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3912588162
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2761855245
Short name T199
Test name
Test status
Simulation time 31494930 ps
CPU time 1.2 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:57 PM PDT 24
Peak memory 219712 kb
Host smart-2f1ad4f2-8384-4013-84a2-95be5965d4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761855245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2761855245
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1462276831
Short name T150
Test name
Test status
Simulation time 25356417 ps
CPU time 1.15 seconds
Started Aug 04 05:41:56 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 220700 kb
Host smart-a8580df0-04d4-4c06-8428-1c9e2d5c8b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462276831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1462276831
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4110437068
Short name T785
Test name
Test status
Simulation time 157690166 ps
CPU time 1.59 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 217416 kb
Host smart-0eac5669-fbb5-4334-9b27-471130ff6151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110437068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4110437068
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2595516431
Short name T107
Test name
Test status
Simulation time 26177304 ps
CPU time 0.97 seconds
Started Aug 04 05:41:56 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 219808 kb
Host smart-791c1d61-6dda-4ee5-bca3-07ec162d5d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595516431 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2595516431
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.354795629
Short name T780
Test name
Test status
Simulation time 108225797 ps
CPU time 1.54 seconds
Started Aug 04 05:41:56 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 220220 kb
Host smart-26c69668-ca30-4eac-9784-a98cfacd6e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354795629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.354795629
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2355997662
Short name T441
Test name
Test status
Simulation time 31289020 ps
CPU time 1.05 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 218484 kb
Host smart-9d7c15ea-9aa4-4280-8916-60a3d55e01d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355997662 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2355997662
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.612595236
Short name T938
Test name
Test status
Simulation time 24308294 ps
CPU time 0.94 seconds
Started Aug 04 05:41:50 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 218580 kb
Host smart-ea4d5cac-2da2-4ebd-b47f-44cea39342ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612595236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.612595236
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.59404681
Short name T901
Test name
Test status
Simulation time 98780922 ps
CPU time 1.11 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 217304 kb
Host smart-cd5181da-65e3-4d50-b68c-37c51cbde6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59404681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.59404681
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2973552280
Short name T156
Test name
Test status
Simulation time 43758575 ps
CPU time 1.23 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:48 PM PDT 24
Peak memory 219004 kb
Host smart-61f161f7-1dcb-49f2-b550-296365ac22d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973552280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2973552280
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2999068451
Short name T645
Test name
Test status
Simulation time 29011474 ps
CPU time 0.87 seconds
Started Aug 04 05:41:43 PM PDT 24
Finished Aug 04 05:41:44 PM PDT 24
Peak memory 218376 kb
Host smart-6a0e328c-ffa9-41d7-b848-7e479f0bf106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999068451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2999068451
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1878904618
Short name T628
Test name
Test status
Simulation time 189930984 ps
CPU time 2.59 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 220016 kb
Host smart-27f1e3c9-87e4-45f2-a4b3-57e91851ba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878904618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1878904618
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.4166150758
Short name T934
Test name
Test status
Simulation time 33802012 ps
CPU time 1.16 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 220896 kb
Host smart-5c09e521-2bb6-4f73-baf9-10ac5f521227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166150758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.4166150758
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2527363752
Short name T192
Test name
Test status
Simulation time 19631558 ps
CPU time 0.97 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 218228 kb
Host smart-e325e7df-49d9-495c-9204-71cb3b911b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527363752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2527363752
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.212712805
Short name T309
Test name
Test status
Simulation time 84567434 ps
CPU time 1.23 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 218832 kb
Host smart-6851afb2-42aa-4d63-a53e-6662e5eb8d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212712805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.212712805
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3850301282
Short name T552
Test name
Test status
Simulation time 235000787 ps
CPU time 1.14 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:53 PM PDT 24
Peak memory 219320 kb
Host smart-23659179-eeb1-4dd0-b851-e1fa87bde367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850301282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3850301282
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1225804487
Short name T983
Test name
Test status
Simulation time 23064618 ps
CPU time 1.01 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 223856 kb
Host smart-c15f3258-ddd7-4fdb-b387-b16b65de7544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225804487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1225804487
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3587867779
Short name T512
Test name
Test status
Simulation time 45819793 ps
CPU time 0.96 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:56 PM PDT 24
Peak memory 217424 kb
Host smart-9cd70414-9483-4578-bbdb-5d5848519cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587867779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3587867779
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3344056073
Short name T206
Test name
Test status
Simulation time 110591195 ps
CPU time 1.25 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:51 PM PDT 24
Peak memory 215688 kb
Host smart-45b78bbd-e903-455b-adda-b7f17e81338c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344056073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3344056073
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.53411553
Short name T60
Test name
Test status
Simulation time 20600372 ps
CPU time 1 seconds
Started Aug 04 05:41:52 PM PDT 24
Finished Aug 04 05:41:53 PM PDT 24
Peak memory 218268 kb
Host smart-790f9431-3247-4a45-a331-76583f79be15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53411553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.53411553
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1693874103
Short name T328
Test name
Test status
Simulation time 94778674 ps
CPU time 1.23 seconds
Started Aug 04 05:41:54 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 219828 kb
Host smart-382558bc-ba1e-42ed-bc6d-3e53cd077e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693874103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1693874103
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3183410476
Short name T400
Test name
Test status
Simulation time 24196345 ps
CPU time 1.14 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 218696 kb
Host smart-5b03c643-61e2-4a3a-860e-2cea4194a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183410476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3183410476
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.1183395829
Short name T108
Test name
Test status
Simulation time 18616157 ps
CPU time 1.03 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 218512 kb
Host smart-9c77425c-8fd8-4aff-96ba-caee25851bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183395829 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1183395829
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2548967227
Short name T281
Test name
Test status
Simulation time 110327133 ps
CPU time 1.08 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 217280 kb
Host smart-05ccd3f7-7594-4ddb-9953-5af27fc0a8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548967227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2548967227
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1355874381
Short name T293
Test name
Test status
Simulation time 92940931 ps
CPU time 1.22 seconds
Started Aug 04 05:41:56 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 220840 kb
Host smart-b00454ca-cb1a-4a3c-8130-1e16ff749c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355874381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1355874381
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3122918793
Short name T88
Test name
Test status
Simulation time 21784560 ps
CPU time 0.96 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 218408 kb
Host smart-6248e4f5-a08c-462b-ba1e-ff5a53c35205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122918793 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3122918793
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.920837348
Short name T356
Test name
Test status
Simulation time 97594036 ps
CPU time 1.59 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 218536 kb
Host smart-565ab4af-7a74-45f8-ab62-21821660dc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920837348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.920837348
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2675462123
Short name T273
Test name
Test status
Simulation time 25890405 ps
CPU time 1.2 seconds
Started Aug 04 05:40:54 PM PDT 24
Finished Aug 04 05:40:55 PM PDT 24
Peak memory 220508 kb
Host smart-1ef0c0bd-1945-47ec-925f-814cf2e4fff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675462123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2675462123
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2708657431
Short name T935
Test name
Test status
Simulation time 22079497 ps
CPU time 0.93 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 214868 kb
Host smart-9b30d429-c915-4ca0-b0d3-3b401161062a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708657431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2708657431
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.678588989
Short name T718
Test name
Test status
Simulation time 84459795 ps
CPU time 0.85 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 215924 kb
Host smart-7d6c0b93-15f2-42f5-8ce8-7cdbdd930372
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678588989 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.678588989
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2652559823
Short name T154
Test name
Test status
Simulation time 45955777 ps
CPU time 1.41 seconds
Started Aug 04 05:41:01 PM PDT 24
Finished Aug 04 05:41:02 PM PDT 24
Peak memory 216784 kb
Host smart-ce27e144-5d74-4160-81fc-eafedc8d97c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652559823 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2652559823
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.4069880400
Short name T844
Test name
Test status
Simulation time 41095711 ps
CPU time 1.19 seconds
Started Aug 04 05:40:58 PM PDT 24
Finished Aug 04 05:40:59 PM PDT 24
Peak memory 225856 kb
Host smart-054500df-e8e0-48e7-a955-d36c53e73892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069880400 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.4069880400
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3991836710
Short name T332
Test name
Test status
Simulation time 45871328 ps
CPU time 1.59 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 217384 kb
Host smart-75042852-5f91-4968-8ef6-5eb683e103a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991836710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3991836710
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2356410777
Short name T870
Test name
Test status
Simulation time 23430566 ps
CPU time 1.06 seconds
Started Aug 04 05:40:45 PM PDT 24
Finished Aug 04 05:40:46 PM PDT 24
Peak memory 215540 kb
Host smart-a891343d-5490-4daa-8d36-4e3791cbfc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356410777 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2356410777
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.1804778832
Short name T385
Test name
Test status
Simulation time 44191238 ps
CPU time 0.99 seconds
Started Aug 04 05:40:44 PM PDT 24
Finished Aug 04 05:40:45 PM PDT 24
Peak memory 215260 kb
Host smart-5f0677d5-105c-4bd1-a71f-d8964d8214e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804778832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1804778832
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1248276247
Short name T333
Test name
Test status
Simulation time 797199017 ps
CPU time 2.39 seconds
Started Aug 04 05:40:54 PM PDT 24
Finished Aug 04 05:40:56 PM PDT 24
Peak memory 217172 kb
Host smart-a322b098-065c-4b3f-bf58-08522c78852e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248276247 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1248276247
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3957130653
Short name T232
Test name
Test status
Simulation time 332906625325 ps
CPU time 722.66 seconds
Started Aug 04 05:41:05 PM PDT 24
Finished Aug 04 05:53:08 PM PDT 24
Peak memory 219516 kb
Host smart-20f56577-8acf-4975-9475-6a7ca66e15dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957130653 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3957130653
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_genbits.3847243420
Short name T742
Test name
Test status
Simulation time 25510839 ps
CPU time 1.21 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 218716 kb
Host smart-03f83873-9816-48ca-a2a8-e50f9d9445f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847243420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3847243420
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.2271602394
Short name T827
Test name
Test status
Simulation time 135082477 ps
CPU time 1.22 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 220328 kb
Host smart-e5e35f4d-7712-4500-b0c3-526666c53a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271602394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.2271602394
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_genbits.174340958
Short name T337
Test name
Test status
Simulation time 43966098 ps
CPU time 1.54 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 219836 kb
Host smart-704a55da-9f82-4c07-a4b2-eeb64ab69803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174340958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.174340958
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1402226905
Short name T122
Test name
Test status
Simulation time 38876931 ps
CPU time 1.11 seconds
Started Aug 04 05:41:47 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 220876 kb
Host smart-89f008e1-64bb-4671-9512-c157e662e2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402226905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1402226905
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.330667533
Short name T602
Test name
Test status
Simulation time 99462185 ps
CPU time 1.09 seconds
Started Aug 04 05:41:50 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 224036 kb
Host smart-2f06f08e-f937-438a-9d17-bb239f983bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330667533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.330667533
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2399508944
Short name T817
Test name
Test status
Simulation time 33681851 ps
CPU time 1.12 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 218500 kb
Host smart-d890df4e-72b1-43d7-a943-8bcc1c092772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399508944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2399508944
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2119760268
Short name T477
Test name
Test status
Simulation time 93171018 ps
CPU time 1.13 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 220388 kb
Host smart-c9dc1b3e-157d-48fd-87d9-2cc7599a1381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119760268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2119760268
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.2517408839
Short name T631
Test name
Test status
Simulation time 27885451 ps
CPU time 0.87 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 218184 kb
Host smart-fe891adc-dc0c-4ef2-8953-25c204b0f1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517408839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2517408839
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2182625939
Short name T7
Test name
Test status
Simulation time 137764884 ps
CPU time 3.17 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 217504 kb
Host smart-27ad19fc-23f6-435e-81a9-6f02d4221638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182625939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2182625939
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.255781088
Short name T290
Test name
Test status
Simulation time 112298114 ps
CPU time 1.17 seconds
Started Aug 04 05:41:56 PM PDT 24
Finished Aug 04 05:41:57 PM PDT 24
Peak memory 219148 kb
Host smart-c14c290a-141a-41da-990d-849137e7fce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255781088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.255781088
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.667781617
Short name T463
Test name
Test status
Simulation time 23723673 ps
CPU time 0.91 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 218684 kb
Host smart-4407e012-563a-4d88-abc0-42554e8a6163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667781617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.667781617
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2761497491
Short name T954
Test name
Test status
Simulation time 65619570 ps
CPU time 1.28 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 217208 kb
Host smart-eaae56b1-2850-4d3a-870a-2a235da60795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761497491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2761497491
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.423514270
Short name T766
Test name
Test status
Simulation time 23520092 ps
CPU time 1.25 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:56 PM PDT 24
Peak memory 218972 kb
Host smart-0e93724a-4154-4b2a-96e0-afbe2ddef118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423514270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.423514270
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.3321420777
Short name T96
Test name
Test status
Simulation time 25930476 ps
CPU time 1 seconds
Started Aug 04 05:41:44 PM PDT 24
Finished Aug 04 05:41:45 PM PDT 24
Peak memory 219452 kb
Host smart-538da966-853d-487d-a511-ac063974c92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321420777 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3321420777
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1549239942
Short name T325
Test name
Test status
Simulation time 216871045 ps
CPU time 1.53 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 218932 kb
Host smart-72b2cbce-d86e-44b7-bc85-3b8fb271d511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549239942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1549239942
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1669270877
Short name T298
Test name
Test status
Simulation time 27383126 ps
CPU time 1.26 seconds
Started Aug 04 05:41:46 PM PDT 24
Finished Aug 04 05:41:47 PM PDT 24
Peak memory 219548 kb
Host smart-1218cde3-d3e6-4094-baeb-516781a305ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669270877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1669270877
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1843828665
Short name T855
Test name
Test status
Simulation time 22991498 ps
CPU time 1.04 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:57 PM PDT 24
Peak memory 218516 kb
Host smart-3e450b21-ee8f-461c-86e9-87f671c4864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843828665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1843828665
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.720683241
Short name T516
Test name
Test status
Simulation time 44603740 ps
CPU time 1.44 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:50 PM PDT 24
Peak memory 217392 kb
Host smart-e937f423-d1fb-4a9a-8fe9-5497ef65c3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720683241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.720683241
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2267911981
Short name T185
Test name
Test status
Simulation time 24545585 ps
CPU time 1.17 seconds
Started Aug 04 05:41:48 PM PDT 24
Finished Aug 04 05:41:49 PM PDT 24
Peak memory 219592 kb
Host smart-e5e6d445-d81d-4b96-b7af-4246feb17609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267911981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2267911981
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1372152090
Short name T207
Test name
Test status
Simulation time 36220706 ps
CPU time 0.87 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 218180 kb
Host smart-b0eacbcc-babc-4f1a-9940-379f49031337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372152090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1372152090
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3581370974
Short name T23
Test name
Test status
Simulation time 72161573 ps
CPU time 1.35 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:57 PM PDT 24
Peak memory 217128 kb
Host smart-5d3189ed-0ad7-403e-b9e2-ca437aa89fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581370974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3581370974
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.888873611
Short name T188
Test name
Test status
Simulation time 27877422 ps
CPU time 1.27 seconds
Started Aug 04 05:41:54 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 218588 kb
Host smart-95fa0d47-6305-4a95-bf66-c772fd867453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888873611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.888873611
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.3214774592
Short name T591
Test name
Test status
Simulation time 19916777 ps
CPU time 1.19 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 224048 kb
Host smart-e1608ac0-08d3-46f9-96d7-bfd1009ba4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214774592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3214774592
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2983818299
Short name T55
Test name
Test status
Simulation time 131013122 ps
CPU time 1.54 seconds
Started Aug 04 05:41:50 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 218904 kb
Host smart-0f033fd1-e093-4be5-a765-fca9adc5c3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983818299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2983818299
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1664947225
Short name T567
Test name
Test status
Simulation time 49179812 ps
CPU time 1.19 seconds
Started Aug 04 05:41:50 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 215700 kb
Host smart-496afb8e-7bf5-4279-b348-487bf94c2e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664947225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1664947225
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3822540487
Short name T600
Test name
Test status
Simulation time 44394658 ps
CPU time 0.83 seconds
Started Aug 04 05:41:54 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 218524 kb
Host smart-a8ea546d-d2ee-4f7a-93c3-3ff47698a5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822540487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3822540487
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2319525270
Short name T334
Test name
Test status
Simulation time 36853498 ps
CPU time 1.35 seconds
Started Aug 04 05:41:49 PM PDT 24
Finished Aug 04 05:41:51 PM PDT 24
Peak memory 217388 kb
Host smart-f72861d6-146e-4fcf-b158-a25f504461e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319525270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2319525270
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3793191501
Short name T303
Test name
Test status
Simulation time 25362569 ps
CPU time 1.18 seconds
Started Aug 04 05:40:48 PM PDT 24
Finished Aug 04 05:40:49 PM PDT 24
Peak memory 219708 kb
Host smart-901a4281-60e2-4749-8472-627de30798c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793191501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3793191501
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1921446495
Short name T404
Test name
Test status
Simulation time 28779523 ps
CPU time 0.87 seconds
Started Aug 04 05:40:58 PM PDT 24
Finished Aug 04 05:40:59 PM PDT 24
Peak memory 206728 kb
Host smart-97801d73-4a03-42e4-9b48-a7f75b46f536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921446495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1921446495
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2142757643
Short name T861
Test name
Test status
Simulation time 36150485 ps
CPU time 0.92 seconds
Started Aug 04 05:40:58 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 216144 kb
Host smart-611704dd-1add-4603-bf49-1047be3db1c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142757643 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2142757643
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3949341382
Short name T676
Test name
Test status
Simulation time 28713116 ps
CPU time 1.23 seconds
Started Aug 04 05:40:49 PM PDT 24
Finished Aug 04 05:40:51 PM PDT 24
Peak memory 216784 kb
Host smart-5fcc3830-31bb-4b9d-a74c-18e6da852473
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949341382 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3949341382
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1065316387
Short name T767
Test name
Test status
Simulation time 19223742 ps
CPU time 1.06 seconds
Started Aug 04 05:40:49 PM PDT 24
Finished Aug 04 05:40:50 PM PDT 24
Peak memory 218528 kb
Host smart-09cdaa9b-7562-46da-846a-03cbf9fdd24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065316387 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1065316387
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1192226914
Short name T965
Test name
Test status
Simulation time 133063244 ps
CPU time 1.52 seconds
Started Aug 04 05:40:56 PM PDT 24
Finished Aug 04 05:40:57 PM PDT 24
Peak memory 220136 kb
Host smart-12be35f6-f0f3-4cf9-8e63-b3bdda5e17e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192226914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1192226914
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.508623172
Short name T384
Test name
Test status
Simulation time 40451372 ps
CPU time 0.92 seconds
Started Aug 04 05:40:55 PM PDT 24
Finished Aug 04 05:40:56 PM PDT 24
Peak memory 215548 kb
Host smart-ef458237-1a85-4179-8b5b-dc5c048ecb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508623172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.508623172
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3411269169
Short name T72
Test name
Test status
Simulation time 30632695 ps
CPU time 1.1 seconds
Started Aug 04 05:41:01 PM PDT 24
Finished Aug 04 05:41:02 PM PDT 24
Peak memory 207100 kb
Host smart-6802a8d2-6b35-4c27-b810-4b9c6289a78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411269169 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3411269169
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.4119102774
Short name T734
Test name
Test status
Simulation time 34113034 ps
CPU time 0.87 seconds
Started Aug 04 05:41:07 PM PDT 24
Finished Aug 04 05:41:07 PM PDT 24
Peak memory 215312 kb
Host smart-da0597d9-8c28-4c0f-82b2-b03bb9b6684b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119102774 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.4119102774
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.492335875
Short name T891
Test name
Test status
Simulation time 135858753 ps
CPU time 2.93 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:41:02 PM PDT 24
Peak memory 217184 kb
Host smart-18e932de-d084-40a7-923b-d09666fa5133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492335875 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.492335875
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1177318529
Short name T574
Test name
Test status
Simulation time 93309959446 ps
CPU time 1587.82 seconds
Started Aug 04 05:40:58 PM PDT 24
Finished Aug 04 06:07:26 PM PDT 24
Peak memory 227420 kb
Host smart-64dc02bb-ffd0-4bec-b40d-9688d36e12fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177318529 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1177318529
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2863521879
Short name T137
Test name
Test status
Simulation time 28131052 ps
CPU time 1.35 seconds
Started Aug 04 05:41:57 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 228844 kb
Host smart-faa26452-078d-42fb-b08c-583547a369c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863521879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2863521879
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3239143282
Short name T642
Test name
Test status
Simulation time 157780991 ps
CPU time 1.48 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:56 PM PDT 24
Peak memory 217064 kb
Host smart-e5f90860-3a23-4aed-a045-f2ed5d769ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239143282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3239143282
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.418449832
Short name T905
Test name
Test status
Simulation time 48846028 ps
CPU time 1.19 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 218816 kb
Host smart-4f6b169a-b3e8-40db-8c9b-3f41393df94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418449832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.418449832
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.3197011883
Short name T668
Test name
Test status
Simulation time 20714152 ps
CPU time 0.99 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 224068 kb
Host smart-cb31bf67-6c6a-423e-99c9-a60c17fa6e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197011883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3197011883
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1800439791
Short name T790
Test name
Test status
Simulation time 69310892 ps
CPU time 1.36 seconds
Started Aug 04 05:41:58 PM PDT 24
Finished Aug 04 05:41:59 PM PDT 24
Peak memory 218580 kb
Host smart-5678dc49-3256-49fc-b0d4-afa1dce3f232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800439791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1800439791
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3548130197
Short name T301
Test name
Test status
Simulation time 42100581 ps
CPU time 1.28 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 220104 kb
Host smart-e6416b9e-8796-44aa-9818-70de1a8eb315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548130197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3548130197
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.1593296087
Short name T151
Test name
Test status
Simulation time 39455618 ps
CPU time 1.37 seconds
Started Aug 04 05:42:03 PM PDT 24
Finished Aug 04 05:42:04 PM PDT 24
Peak memory 215384 kb
Host smart-9be69b16-9ef9-4a9a-8b1f-979d7194a239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593296087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1593296087
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2528538048
Short name T322
Test name
Test status
Simulation time 42938894 ps
CPU time 1.59 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:57 PM PDT 24
Peak memory 218500 kb
Host smart-df58802b-e62c-4d4a-92b7-6c74db2de00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528538048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2528538048
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.1632263392
Short name T555
Test name
Test status
Simulation time 44956802 ps
CPU time 1.19 seconds
Started Aug 04 05:41:58 PM PDT 24
Finished Aug 04 05:41:59 PM PDT 24
Peak memory 218784 kb
Host smart-00c0d418-b460-400b-abb5-c64e28d7c75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632263392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.1632263392
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1767320825
Short name T807
Test name
Test status
Simulation time 36840016 ps
CPU time 0.87 seconds
Started Aug 04 05:42:02 PM PDT 24
Finished Aug 04 05:42:03 PM PDT 24
Peak memory 218464 kb
Host smart-7af68d9e-4961-47dc-b530-819c040d439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767320825 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1767320825
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3778120913
Short name T435
Test name
Test status
Simulation time 121470495 ps
CPU time 1.55 seconds
Started Aug 04 05:41:56 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 218632 kb
Host smart-87ec4d3c-7409-40da-ad06-2e4c1249e01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778120913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3778120913
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.4155438327
Short name T945
Test name
Test status
Simulation time 43891715 ps
CPU time 1.18 seconds
Started Aug 04 05:41:58 PM PDT 24
Finished Aug 04 05:41:59 PM PDT 24
Peak memory 218252 kb
Host smart-95e877aa-2844-48c3-af58-46937411ad88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155438327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.4155438327
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3909096052
Short name T166
Test name
Test status
Simulation time 30510849 ps
CPU time 1.07 seconds
Started Aug 04 05:41:58 PM PDT 24
Finished Aug 04 05:41:59 PM PDT 24
Peak memory 229564 kb
Host smart-355c1303-9bf6-47e0-b533-2fb11215965f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909096052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3909096052
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1255697225
Short name T576
Test name
Test status
Simulation time 75662896 ps
CPU time 1.11 seconds
Started Aug 04 05:41:58 PM PDT 24
Finished Aug 04 05:41:59 PM PDT 24
Peak memory 217148 kb
Host smart-c9f5fcb3-5adf-4a45-a012-8121a6d6b560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255697225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1255697225
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.2756395005
Short name T956
Test name
Test status
Simulation time 24455533 ps
CPU time 1.14 seconds
Started Aug 04 05:41:57 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 219392 kb
Host smart-d8c1a21e-500d-467e-8051-ab4b676d8176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756395005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2756395005
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2168123486
Short name T444
Test name
Test status
Simulation time 33870508 ps
CPU time 0.94 seconds
Started Aug 04 05:41:52 PM PDT 24
Finished Aug 04 05:41:53 PM PDT 24
Peak memory 223864 kb
Host smart-e93a3164-0718-4d44-bad6-bea148548ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168123486 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2168123486
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.4116744489
Short name T652
Test name
Test status
Simulation time 32940601 ps
CPU time 1.28 seconds
Started Aug 04 05:41:54 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 217452 kb
Host smart-5994c450-d35d-4ec3-8ce6-a159dab37a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116744489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4116744489
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2188520222
Short name T145
Test name
Test status
Simulation time 25273995 ps
CPU time 1 seconds
Started Aug 04 05:42:04 PM PDT 24
Finished Aug 04 05:42:05 PM PDT 24
Peak memory 219556 kb
Host smart-bd8581cb-1682-44ee-82a7-45b0d2b6008c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188520222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2188520222
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3983104875
Short name T558
Test name
Test status
Simulation time 116724829 ps
CPU time 1.58 seconds
Started Aug 04 05:42:04 PM PDT 24
Finished Aug 04 05:42:06 PM PDT 24
Peak memory 218612 kb
Host smart-b602613c-fbae-4ef3-8faf-9101511fb6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983104875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3983104875
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.3438724943
Short name T479
Test name
Test status
Simulation time 38425364 ps
CPU time 1.06 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:52 PM PDT 24
Peak memory 218340 kb
Host smart-775b9440-83c8-4a5f-9f73-026832a96aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438724943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3438724943
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2880571802
Short name T589
Test name
Test status
Simulation time 19545861 ps
CPU time 1.06 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:56 PM PDT 24
Peak memory 219692 kb
Host smart-e796a563-6103-4fb5-90cc-fe3b4402cbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880571802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2880571802
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3714033914
Short name T413
Test name
Test status
Simulation time 52939119 ps
CPU time 1.8 seconds
Started Aug 04 05:41:51 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 218604 kb
Host smart-ef257ca9-6060-4afc-8cad-9321f71af260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714033914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3714033914
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.9630762
Short name T200
Test name
Test status
Simulation time 52419964 ps
CPU time 1.15 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:54 PM PDT 24
Peak memory 215708 kb
Host smart-ebb8bae3-110c-4134-8ebb-96197f762939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9630762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.9630762
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.313088117
Short name T568
Test name
Test status
Simulation time 27022700 ps
CPU time 1.25 seconds
Started Aug 04 05:41:56 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 220656 kb
Host smart-3d062107-1b92-4106-9105-4f5b5d699018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313088117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.313088117
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.513211350
Short name T483
Test name
Test status
Simulation time 86972407 ps
CPU time 1.31 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:57 PM PDT 24
Peak memory 218788 kb
Host smart-fec20979-3bc6-45ab-9f7a-d6961fbc0adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513211350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.513211350
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1708822954
Short name T670
Test name
Test status
Simulation time 200158116 ps
CPU time 1.14 seconds
Started Aug 04 05:41:58 PM PDT 24
Finished Aug 04 05:41:59 PM PDT 24
Peak memory 219944 kb
Host smart-ef3d73eb-c6a8-4ec0-8a16-a46f64425fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708822954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1708822954
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.292653165
Short name T183
Test name
Test status
Simulation time 30915544 ps
CPU time 1.05 seconds
Started Aug 04 05:41:54 PM PDT 24
Finished Aug 04 05:42:01 PM PDT 24
Peak memory 224084 kb
Host smart-780bdf11-276b-4072-8cf8-40eac44eb444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292653165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.292653165
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1021885632
Short name T308
Test name
Test status
Simulation time 48171309 ps
CPU time 1.76 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:57 PM PDT 24
Peak memory 218620 kb
Host smart-fea9d285-1ab4-459a-9888-2776fd134dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021885632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1021885632
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1349891785
Short name T125
Test name
Test status
Simulation time 25898471 ps
CPU time 1.2 seconds
Started Aug 04 05:40:49 PM PDT 24
Finished Aug 04 05:40:50 PM PDT 24
Peak memory 218552 kb
Host smart-9ad13ba2-7eac-4797-94da-b66026d55a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349891785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1349891785
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2002452471
Short name T560
Test name
Test status
Simulation time 87983688 ps
CPU time 0.87 seconds
Started Aug 04 05:40:58 PM PDT 24
Finished Aug 04 05:40:59 PM PDT 24
Peak memory 206720 kb
Host smart-a493cbfa-7828-42bd-a84e-3917d06f4009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002452471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2002452471
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.848155060
Short name T772
Test name
Test status
Simulation time 20389225 ps
CPU time 0.89 seconds
Started Aug 04 05:40:49 PM PDT 24
Finished Aug 04 05:40:50 PM PDT 24
Peak memory 215376 kb
Host smart-3daf3d63-58ae-4e0e-a048-1a993465af5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848155060 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.848155060
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3795218690
Short name T161
Test name
Test status
Simulation time 42199737 ps
CPU time 0.91 seconds
Started Aug 04 05:40:50 PM PDT 24
Finished Aug 04 05:40:51 PM PDT 24
Peak memory 217216 kb
Host smart-4759cca4-80cd-4958-a2bb-2116180acf26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795218690 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3795218690
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3521866761
Short name T85
Test name
Test status
Simulation time 38864900 ps
CPU time 1.06 seconds
Started Aug 04 05:40:50 PM PDT 24
Finished Aug 04 05:40:51 PM PDT 24
Peak memory 219756 kb
Host smart-5ae0465b-f2a6-465d-b13a-15c791686a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521866761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3521866761
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.657919182
Short name T310
Test name
Test status
Simulation time 177249917 ps
CPU time 3.23 seconds
Started Aug 04 05:40:48 PM PDT 24
Finished Aug 04 05:40:51 PM PDT 24
Peak memory 220108 kb
Host smart-2dde3de2-6f09-42d4-be30-d5a54cf160af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657919182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.657919182
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2978849065
Short name T57
Test name
Test status
Simulation time 42232536 ps
CPU time 0.81 seconds
Started Aug 04 05:40:52 PM PDT 24
Finished Aug 04 05:40:53 PM PDT 24
Peak memory 215508 kb
Host smart-70d6ba0f-1de4-4814-a7d9-81cd7e6e3b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978849065 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2978849065
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.75863167
Short name T581
Test name
Test status
Simulation time 43358953 ps
CPU time 0.91 seconds
Started Aug 04 05:40:56 PM PDT 24
Finished Aug 04 05:40:57 PM PDT 24
Peak memory 207108 kb
Host smart-a154386c-5e20-4a22-8f0b-c6b97ce83e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75863167 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.75863167
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.727025455
Short name T704
Test name
Test status
Simulation time 18171188 ps
CPU time 1.02 seconds
Started Aug 04 05:40:51 PM PDT 24
Finished Aug 04 05:40:52 PM PDT 24
Peak memory 215296 kb
Host smart-8ac6e58f-7ada-4c23-a8e6-4d2e89f3bc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727025455 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.727025455
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3806722997
Short name T418
Test name
Test status
Simulation time 1214046316 ps
CPU time 3.51 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:07 PM PDT 24
Peak memory 217036 kb
Host smart-8cb04c55-a308-43ce-9198-2e53059368f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806722997 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3806722997
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1568967228
Short name T864
Test name
Test status
Simulation time 103035192195 ps
CPU time 1989.39 seconds
Started Aug 04 05:41:02 PM PDT 24
Finished Aug 04 06:14:12 PM PDT 24
Peak memory 227144 kb
Host smart-a6ca6c13-86ed-4d1e-b986-ec7a001144cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568967228 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1568967228
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2664775977
Short name T141
Test name
Test status
Simulation time 199838531 ps
CPU time 1.18 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:56 PM PDT 24
Peak memory 219884 kb
Host smart-ce19adde-66a5-4d2e-8a33-eda44732fbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664775977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2664775977
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3344489755
Short name T981
Test name
Test status
Simulation time 29588559 ps
CPU time 1.28 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:57 PM PDT 24
Peak memory 219524 kb
Host smart-99d26311-c158-462b-8cb9-b2cf1d9b7cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344489755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3344489755
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2227635616
Short name T526
Test name
Test status
Simulation time 41010372 ps
CPU time 1.41 seconds
Started Aug 04 05:41:57 PM PDT 24
Finished Aug 04 05:41:59 PM PDT 24
Peak memory 218648 kb
Host smart-18b2cccf-7a56-49cb-af91-cd708298b773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227635616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2227635616
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.3122713722
Short name T468
Test name
Test status
Simulation time 138382875 ps
CPU time 1.2 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:56 PM PDT 24
Peak memory 220344 kb
Host smart-576bc899-fa42-4a6d-b54e-8d9ae0d5bce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122713722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.3122713722
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1676843121
Short name T524
Test name
Test status
Simulation time 49426636 ps
CPU time 1.3 seconds
Started Aug 04 05:41:56 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 225680 kb
Host smart-3f56a4d3-6359-47eb-b744-dbc66ea2bc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676843121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1676843121
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3207457660
Short name T826
Test name
Test status
Simulation time 350836885 ps
CPU time 1.48 seconds
Started Aug 04 05:42:04 PM PDT 24
Finished Aug 04 05:42:06 PM PDT 24
Peak memory 218804 kb
Host smart-df4472a1-e2a6-4729-bebe-a9ba41927a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207457660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3207457660
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2451327279
Short name T669
Test name
Test status
Simulation time 27827019 ps
CPU time 1.24 seconds
Started Aug 04 05:41:57 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 218384 kb
Host smart-d936f032-1e79-4e2d-9a60-8aa7edc5a1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451327279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2451327279
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.2309899522
Short name T94
Test name
Test status
Simulation time 28140612 ps
CPU time 1.19 seconds
Started Aug 04 05:41:58 PM PDT 24
Finished Aug 04 05:41:59 PM PDT 24
Peak memory 220936 kb
Host smart-155bc62b-1d18-4ed8-a049-a700c0577d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309899522 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2309899522
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.467897877
Short name T394
Test name
Test status
Simulation time 60348414 ps
CPU time 1.04 seconds
Started Aug 04 05:41:59 PM PDT 24
Finished Aug 04 05:42:00 PM PDT 24
Peak memory 217460 kb
Host smart-d40217e6-bca3-4e1e-8c45-da8d768cf00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467897877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.467897877
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3667169373
Short name T709
Test name
Test status
Simulation time 47590571 ps
CPU time 1.22 seconds
Started Aug 04 05:41:59 PM PDT 24
Finished Aug 04 05:42:00 PM PDT 24
Peak memory 219300 kb
Host smart-27dbeba7-8427-440c-b885-77119574348c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667169373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3667169373
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.10139504
Short name T787
Test name
Test status
Simulation time 18699023 ps
CPU time 1.13 seconds
Started Aug 04 05:41:55 PM PDT 24
Finished Aug 04 05:41:56 PM PDT 24
Peak memory 223952 kb
Host smart-dbfa8018-5015-40c7-b1dd-456a76a53f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10139504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.10139504
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3907867618
Short name T315
Test name
Test status
Simulation time 54695416 ps
CPU time 1.92 seconds
Started Aug 04 05:41:57 PM PDT 24
Finished Aug 04 05:41:59 PM PDT 24
Peak memory 218700 kb
Host smart-fd3e5530-070d-4c72-b1b3-6ebe7334c6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907867618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3907867618
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1230322398
Short name T212
Test name
Test status
Simulation time 84996494 ps
CPU time 1.21 seconds
Started Aug 04 05:42:01 PM PDT 24
Finished Aug 04 05:42:03 PM PDT 24
Peak memory 218552 kb
Host smart-12543477-c654-48f6-9b9b-da9d5c249399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230322398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1230322398
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3594238437
Short name T701
Test name
Test status
Simulation time 24489814 ps
CPU time 1.22 seconds
Started Aug 04 05:41:53 PM PDT 24
Finished Aug 04 05:41:55 PM PDT 24
Peak memory 220748 kb
Host smart-657befac-a9cb-4454-ac82-26082f7bd301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594238437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3594238437
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1387219306
Short name T370
Test name
Test status
Simulation time 72263540 ps
CPU time 1.22 seconds
Started Aug 04 05:41:59 PM PDT 24
Finished Aug 04 05:42:00 PM PDT 24
Peak memory 218548 kb
Host smart-e34acf01-39b4-4900-a43e-7f8bf1b12df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387219306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1387219306
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3765605581
Short name T715
Test name
Test status
Simulation time 29168195 ps
CPU time 1.23 seconds
Started Aug 04 05:41:59 PM PDT 24
Finished Aug 04 05:42:00 PM PDT 24
Peak memory 218704 kb
Host smart-53295904-7ca4-4e1e-b459-409a6fb3edb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765605581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3765605581
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1597734547
Short name T109
Test name
Test status
Simulation time 45116306 ps
CPU time 1.28 seconds
Started Aug 04 05:41:54 PM PDT 24
Finished Aug 04 05:41:56 PM PDT 24
Peak memory 225608 kb
Host smart-a5a9fb1b-7488-4f16-92c9-7266519de0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597734547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1597734547
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3149855893
Short name T29
Test name
Test status
Simulation time 63035482 ps
CPU time 2.31 seconds
Started Aug 04 05:42:04 PM PDT 24
Finished Aug 04 05:42:07 PM PDT 24
Peak memory 220212 kb
Host smart-9caa47cf-ceb9-445a-b25e-d51d92d312f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149855893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3149855893
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2634873143
Short name T636
Test name
Test status
Simulation time 87273228 ps
CPU time 1.15 seconds
Started Aug 04 05:42:04 PM PDT 24
Finished Aug 04 05:42:05 PM PDT 24
Peak memory 219332 kb
Host smart-31c93229-e834-4129-a424-b59fdfbe7b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634873143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2634873143
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.1890764070
Short name T174
Test name
Test status
Simulation time 24965783 ps
CPU time 1.05 seconds
Started Aug 04 05:42:04 PM PDT 24
Finished Aug 04 05:42:05 PM PDT 24
Peak memory 224012 kb
Host smart-719b7f07-0db6-4207-851e-6243f3a9f1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890764070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1890764070
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1694587704
Short name T369
Test name
Test status
Simulation time 133872490 ps
CPU time 2.84 seconds
Started Aug 04 05:41:57 PM PDT 24
Finished Aug 04 05:42:00 PM PDT 24
Peak memory 218516 kb
Host smart-9af33d90-a1b2-49e7-ba3a-0ddb973f19c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694587704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1694587704
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.1443376906
Short name T68
Test name
Test status
Simulation time 48698579 ps
CPU time 1.21 seconds
Started Aug 04 05:41:56 PM PDT 24
Finished Aug 04 05:41:57 PM PDT 24
Peak memory 218812 kb
Host smart-cd7a8a11-9043-48df-b400-0b62501d4455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443376906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1443376906
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2894229350
Short name T849
Test name
Test status
Simulation time 21224219 ps
CPU time 1.14 seconds
Started Aug 04 05:42:00 PM PDT 24
Finished Aug 04 05:42:01 PM PDT 24
Peak memory 224024 kb
Host smart-91a1c9cf-e2e9-4a68-bd82-ec427cab14b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894229350 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2894229350
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3912235700
Short name T420
Test name
Test status
Simulation time 51370088 ps
CPU time 1.36 seconds
Started Aug 04 05:42:04 PM PDT 24
Finished Aug 04 05:42:06 PM PDT 24
Peak memory 217448 kb
Host smart-602a5cec-8a4f-49ee-9746-b5ec3f040ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912235700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3912235700
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.2528355819
Short name T143
Test name
Test status
Simulation time 74961773 ps
CPU time 1.07 seconds
Started Aug 04 05:41:58 PM PDT 24
Finished Aug 04 05:41:59 PM PDT 24
Peak memory 218764 kb
Host smart-e3f843d4-0ba1-4faf-8dc9-c515371776a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528355819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2528355819
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3735957816
Short name T184
Test name
Test status
Simulation time 22022936 ps
CPU time 1.01 seconds
Started Aug 04 05:41:57 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 218488 kb
Host smart-60a4ae69-cb33-401e-afee-2275bbf51880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735957816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3735957816
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1916754037
Short name T447
Test name
Test status
Simulation time 81951987 ps
CPU time 1.52 seconds
Started Aug 04 05:41:57 PM PDT 24
Finished Aug 04 05:41:58 PM PDT 24
Peak memory 219024 kb
Host smart-d281a605-6606-4593-9dee-b39043fc4240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916754037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1916754037
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.4022190690
Short name T771
Test name
Test status
Simulation time 25001736 ps
CPU time 1.19 seconds
Started Aug 04 05:42:00 PM PDT 24
Finished Aug 04 05:42:01 PM PDT 24
Peak memory 218852 kb
Host smart-dc5293d9-58ea-4db1-a246-633ea0434d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022190690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.4022190690
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.730265024
Short name T148
Test name
Test status
Simulation time 38257116 ps
CPU time 0.9 seconds
Started Aug 04 05:41:59 PM PDT 24
Finished Aug 04 05:42:00 PM PDT 24
Peak memory 219624 kb
Host smart-84396956-d91b-4ebb-a599-4be438dfa12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730265024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.730265024
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.41672190
Short name T796
Test name
Test status
Simulation time 31440777 ps
CPU time 1.24 seconds
Started Aug 04 05:41:56 PM PDT 24
Finished Aug 04 05:41:57 PM PDT 24
Peak memory 218784 kb
Host smart-b38e295e-aa1a-4357-868e-16392952a348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41672190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.41672190
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.214739656
Short name T469
Test name
Test status
Simulation time 158101668 ps
CPU time 1.1 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 218624 kb
Host smart-725841c0-3e50-4805-9d2b-9722be0398ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214739656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.214739656
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2721471145
Short name T341
Test name
Test status
Simulation time 23675622 ps
CPU time 0.85 seconds
Started Aug 04 05:40:58 PM PDT 24
Finished Aug 04 05:40:59 PM PDT 24
Peak memory 206724 kb
Host smart-8faf01e4-97c3-45a4-8252-56999010de62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721471145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2721471145
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2984603481
Short name T105
Test name
Test status
Simulation time 11409743 ps
CPU time 0.85 seconds
Started Aug 04 05:40:55 PM PDT 24
Finished Aug 04 05:40:56 PM PDT 24
Peak memory 216216 kb
Host smart-a9e76bfb-c4dd-4e91-bff9-a6f07e905089
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984603481 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2984603481
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3934433677
Short name T214
Test name
Test status
Simulation time 95726366 ps
CPU time 1.19 seconds
Started Aug 04 05:41:03 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 219836 kb
Host smart-f18df434-1b08-4443-8ca9-a5efe434a748
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934433677 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3934433677
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.383120722
Short name T363
Test name
Test status
Simulation time 46624722 ps
CPU time 1.03 seconds
Started Aug 04 05:41:00 PM PDT 24
Finished Aug 04 05:41:01 PM PDT 24
Peak memory 219624 kb
Host smart-b75f5edc-063e-4e29-8b35-5c2f33598d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383120722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.383120722
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2523469761
Short name T610
Test name
Test status
Simulation time 37833407 ps
CPU time 1.55 seconds
Started Aug 04 05:40:54 PM PDT 24
Finished Aug 04 05:40:56 PM PDT 24
Peak memory 217548 kb
Host smart-f38adad5-85e2-4848-abe5-243988940d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523469761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2523469761
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3273434101
Short name T515
Test name
Test status
Simulation time 35118973 ps
CPU time 0.88 seconds
Started Aug 04 05:41:00 PM PDT 24
Finished Aug 04 05:41:01 PM PDT 24
Peak memory 215792 kb
Host smart-3cb4db6f-fd3c-4bfe-91c0-408563f1947d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273434101 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3273434101
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.749926431
Short name T770
Test name
Test status
Simulation time 104719816 ps
CPU time 0.94 seconds
Started Aug 04 05:41:06 PM PDT 24
Finished Aug 04 05:41:07 PM PDT 24
Peak memory 207116 kb
Host smart-f50df1a9-8854-4800-a459-75ad5d67a4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749926431 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.749926431
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.198708224
Short name T930
Test name
Test status
Simulation time 19017959 ps
CPU time 1.03 seconds
Started Aug 04 05:40:59 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 215212 kb
Host smart-b663ded2-aa8e-47bb-bbef-54e5861cfbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198708224 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.198708224
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1047471838
Short name T18
Test name
Test status
Simulation time 633943158 ps
CPU time 4.34 seconds
Started Aug 04 05:41:00 PM PDT 24
Finished Aug 04 05:41:04 PM PDT 24
Peak memory 215260 kb
Host smart-8cb067e3-9165-47b1-a0df-8deec740e1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047471838 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1047471838
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3115509110
Short name T225
Test name
Test status
Simulation time 131479790670 ps
CPU time 1586.67 seconds
Started Aug 04 05:40:54 PM PDT 24
Finished Aug 04 06:07:21 PM PDT 24
Peak memory 224696 kb
Host smart-fe05450d-d7a6-4779-a409-855d1bc84bdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115509110 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3115509110
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.4130180032
Short name T216
Test name
Test status
Simulation time 30886818 ps
CPU time 1.26 seconds
Started Aug 04 05:41:59 PM PDT 24
Finished Aug 04 05:42:00 PM PDT 24
Peak memory 220996 kb
Host smart-47d4a565-f6ce-4ad6-980f-1b85e72d9e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130180032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.4130180032
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3188565118
Short name T182
Test name
Test status
Simulation time 33151409 ps
CPU time 1.01 seconds
Started Aug 04 05:42:00 PM PDT 24
Finished Aug 04 05:42:01 PM PDT 24
Peak memory 223888 kb
Host smart-13bd19f9-300c-4b6f-9e59-a5dc5ee93300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188565118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3188565118
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3291922258
Short name T351
Test name
Test status
Simulation time 66430970 ps
CPU time 1.21 seconds
Started Aug 04 05:41:59 PM PDT 24
Finished Aug 04 05:42:01 PM PDT 24
Peak memory 217396 kb
Host smart-3bdf4447-5f29-46a3-96ad-71b0b7529868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291922258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3291922258
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.3820207606
Short name T244
Test name
Test status
Simulation time 43893258 ps
CPU time 1.21 seconds
Started Aug 04 05:42:05 PM PDT 24
Finished Aug 04 05:42:06 PM PDT 24
Peak memory 218704 kb
Host smart-f1b0d210-b31f-467f-94a4-d799f0b01f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820207606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.3820207606
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.1279706912
Short name T112
Test name
Test status
Simulation time 30534709 ps
CPU time 1.11 seconds
Started Aug 04 05:42:13 PM PDT 24
Finished Aug 04 05:42:14 PM PDT 24
Peak memory 224076 kb
Host smart-44b90a12-7282-4943-af0c-e4bae3ea7a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279706912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1279706912
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3930630681
Short name T910
Test name
Test status
Simulation time 343144887 ps
CPU time 4.18 seconds
Started Aug 04 05:42:03 PM PDT 24
Finished Aug 04 05:42:07 PM PDT 24
Peak memory 220412 kb
Host smart-727a5019-7a9e-487b-a0e1-9965b59a3fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930630681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3930630681
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.3620950632
Short name T971
Test name
Test status
Simulation time 43749736 ps
CPU time 1.17 seconds
Started Aug 04 05:42:09 PM PDT 24
Finished Aug 04 05:42:10 PM PDT 24
Peak memory 219756 kb
Host smart-c673533e-0d31-4e39-87f4-0d8c3904c6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620950632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.3620950632
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.1891395112
Short name T991
Test name
Test status
Simulation time 43105568 ps
CPU time 0.86 seconds
Started Aug 04 05:42:35 PM PDT 24
Finished Aug 04 05:42:36 PM PDT 24
Peak memory 218640 kb
Host smart-590487bc-932b-4dc9-8a13-cbc1afaa7204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891395112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1891395112
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.708528406
Short name T62
Test name
Test status
Simulation time 56290050 ps
CPU time 1.09 seconds
Started Aug 04 05:42:02 PM PDT 24
Finished Aug 04 05:42:04 PM PDT 24
Peak memory 217340 kb
Host smart-846c7381-c313-4c03-8d80-abfe727cdcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708528406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.708528406
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2689359508
Short name T762
Test name
Test status
Simulation time 87239836 ps
CPU time 1.19 seconds
Started Aug 04 05:42:08 PM PDT 24
Finished Aug 04 05:42:09 PM PDT 24
Peak memory 218700 kb
Host smart-dd702c5b-69e6-4af8-aa76-0ffd9006637b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689359508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2689359508
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.4221576736
Short name T611
Test name
Test status
Simulation time 74492892 ps
CPU time 1.11 seconds
Started Aug 04 05:42:07 PM PDT 24
Finished Aug 04 05:42:09 PM PDT 24
Peak memory 219832 kb
Host smart-f8197737-7ddc-45b3-be78-6b98601a3d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221576736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.4221576736
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/94.edn_alert.3714452571
Short name T509
Test name
Test status
Simulation time 188119257 ps
CPU time 1.33 seconds
Started Aug 04 05:42:21 PM PDT 24
Finished Aug 04 05:42:23 PM PDT 24
Peak memory 219296 kb
Host smart-98d349fe-fe72-4811-a4f4-0eac6b29a44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714452571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3714452571
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.465506348
Short name T13
Test name
Test status
Simulation time 18422684 ps
CPU time 1.11 seconds
Started Aug 04 05:42:08 PM PDT 24
Finished Aug 04 05:42:09 PM PDT 24
Peak memory 223988 kb
Host smart-79d89543-20ae-4c52-a19f-c4c2a5ee4a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465506348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.465506348
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3987301922
Short name T890
Test name
Test status
Simulation time 80661397 ps
CPU time 1.4 seconds
Started Aug 04 05:42:08 PM PDT 24
Finished Aug 04 05:42:15 PM PDT 24
Peak memory 218736 kb
Host smart-fee93834-da2d-43c3-b3d3-13498549f343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987301922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3987301922
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.903898141
Short name T673
Test name
Test status
Simulation time 148007077 ps
CPU time 1.24 seconds
Started Aug 04 05:42:13 PM PDT 24
Finished Aug 04 05:42:15 PM PDT 24
Peak memory 219712 kb
Host smart-9d9312bf-2221-45ea-bc62-e89dccba8062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903898141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.903898141
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1920742685
Short name T115
Test name
Test status
Simulation time 26119347 ps
CPU time 1.21 seconds
Started Aug 04 05:42:12 PM PDT 24
Finished Aug 04 05:42:13 PM PDT 24
Peak memory 219736 kb
Host smart-c5b05a56-a252-48ce-b33c-9f0b75539886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920742685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1920742685
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2586612925
Short name T913
Test name
Test status
Simulation time 25491738 ps
CPU time 1.13 seconds
Started Aug 04 05:42:15 PM PDT 24
Finished Aug 04 05:42:16 PM PDT 24
Peak memory 217444 kb
Host smart-a600eb39-0247-4496-a069-71a829238073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586612925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2586612925
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.3054958115
Short name T124
Test name
Test status
Simulation time 24058670 ps
CPU time 1.13 seconds
Started Aug 04 05:42:14 PM PDT 24
Finished Aug 04 05:42:15 PM PDT 24
Peak memory 220772 kb
Host smart-0811e6fb-bcf7-482c-85e1-45c6345be6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054958115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.3054958115
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_genbits.3514852214
Short name T852
Test name
Test status
Simulation time 42077082 ps
CPU time 1.62 seconds
Started Aug 04 05:42:26 PM PDT 24
Finished Aug 04 05:42:28 PM PDT 24
Peak memory 215284 kb
Host smart-ed03f4ea-f46a-42b5-8b61-52f716b0a99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514852214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3514852214
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2798792201
Short name T984
Test name
Test status
Simulation time 41054932 ps
CPU time 1.18 seconds
Started Aug 04 05:42:20 PM PDT 24
Finished Aug 04 05:42:21 PM PDT 24
Peak memory 218616 kb
Host smart-e5967355-b301-41a3-ac92-318ea897aee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798792201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2798792201
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.993692743
Short name T165
Test name
Test status
Simulation time 24515478 ps
CPU time 1.22 seconds
Started Aug 04 05:42:11 PM PDT 24
Finished Aug 04 05:42:13 PM PDT 24
Peak memory 219736 kb
Host smart-a49ca6f5-07ca-4cb4-bbb5-01ef0670fad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993692743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.993692743
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.515458613
Short name T34
Test name
Test status
Simulation time 80746930 ps
CPU time 1.07 seconds
Started Aug 04 05:42:28 PM PDT 24
Finished Aug 04 05:42:30 PM PDT 24
Peak memory 217292 kb
Host smart-105c5401-93fc-4b00-af14-c89c5264cf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515458613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.515458613
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.577921230
Short name T157
Test name
Test status
Simulation time 239057658 ps
CPU time 1.28 seconds
Started Aug 04 05:42:24 PM PDT 24
Finished Aug 04 05:42:25 PM PDT 24
Peak memory 219764 kb
Host smart-e454ad1d-e25a-4591-b5d1-818d39284a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577921230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.577921230
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.4088243406
Short name T685
Test name
Test status
Simulation time 18429169 ps
CPU time 1.07 seconds
Started Aug 04 05:42:17 PM PDT 24
Finished Aug 04 05:42:18 PM PDT 24
Peak memory 218208 kb
Host smart-1229c59e-e95c-4bb5-a4a4-309a85178375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088243406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.4088243406
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3441921743
Short name T9
Test name
Test status
Simulation time 38765274 ps
CPU time 1.4 seconds
Started Aug 04 05:42:22 PM PDT 24
Finished Aug 04 05:42:24 PM PDT 24
Peak memory 220012 kb
Host smart-5936f74e-936e-44e1-8385-17b24993a690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441921743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3441921743
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1990224613
Short name T699
Test name
Test status
Simulation time 44091160 ps
CPU time 1.12 seconds
Started Aug 04 05:42:24 PM PDT 24
Finished Aug 04 05:42:25 PM PDT 24
Peak memory 219712 kb
Host smart-9f3f5881-798d-4806-923b-d10daf4d15a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990224613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1990224613
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.1761001443
Short name T899
Test name
Test status
Simulation time 46044203 ps
CPU time 0.85 seconds
Started Aug 04 05:42:34 PM PDT 24
Finished Aug 04 05:42:35 PM PDT 24
Peak memory 218376 kb
Host smart-31474a4d-3d87-48be-9e11-663b7147dc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761001443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1761001443
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3646549681
Short name T47
Test name
Test status
Simulation time 162858713 ps
CPU time 1.26 seconds
Started Aug 04 05:42:23 PM PDT 24
Finished Aug 04 05:42:25 PM PDT 24
Peak memory 218488 kb
Host smart-0422917b-bdf1-426a-bb91-e833e1cb10c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646549681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3646549681
Directory /workspace/99.edn_genbits/latest
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