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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.24 98.25 93.07 91.10 86.05 95.50 96.83 91.89


Total test records in report: 1125
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T275 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4144477567 Aug 05 06:03:25 PM PDT 24 Aug 05 06:03:26 PM PDT 24 37226689 ps
T1014 /workspace/coverage/cover_reg_top/13.edn_intr_test.487749522 Aug 05 06:03:38 PM PDT 24 Aug 05 06:03:39 PM PDT 24 86606401 ps
T263 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2829789012 Aug 05 06:03:19 PM PDT 24 Aug 05 06:03:19 PM PDT 24 93295715 ps
T1015 /workspace/coverage/cover_reg_top/45.edn_intr_test.849023697 Aug 05 06:03:48 PM PDT 24 Aug 05 06:03:49 PM PDT 24 13896519 ps
T276 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2028219916 Aug 05 06:03:30 PM PDT 24 Aug 05 06:03:31 PM PDT 24 122171716 ps
T1016 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.104808332 Aug 05 06:03:33 PM PDT 24 Aug 05 06:03:35 PM PDT 24 119548152 ps
T1017 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1339200377 Aug 05 06:03:30 PM PDT 24 Aug 05 06:03:33 PM PDT 24 94934099 ps
T286 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2763566855 Aug 05 06:03:26 PM PDT 24 Aug 05 06:03:32 PM PDT 24 1326210187 ps
T1018 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3507406820 Aug 05 06:03:23 PM PDT 24 Aug 05 06:03:24 PM PDT 24 32153284 ps
T264 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1897200072 Aug 05 06:03:25 PM PDT 24 Aug 05 06:03:26 PM PDT 24 16341783 ps
T1019 /workspace/coverage/cover_reg_top/12.edn_intr_test.1122222741 Aug 05 06:03:31 PM PDT 24 Aug 05 06:03:32 PM PDT 24 15296193 ps
T1020 /workspace/coverage/cover_reg_top/42.edn_intr_test.3283249761 Aug 05 06:03:50 PM PDT 24 Aug 05 06:03:52 PM PDT 24 24127334 ps
T1021 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1145598715 Aug 05 06:03:24 PM PDT 24 Aug 05 06:03:26 PM PDT 24 43826246 ps
T1022 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4093786350 Aug 05 06:03:35 PM PDT 24 Aug 05 06:03:37 PM PDT 24 78970548 ps
T1023 /workspace/coverage/cover_reg_top/9.edn_intr_test.2868552010 Aug 05 06:03:31 PM PDT 24 Aug 05 06:03:32 PM PDT 24 25276458 ps
T1024 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1362669125 Aug 05 06:03:38 PM PDT 24 Aug 05 06:03:41 PM PDT 24 246501385 ps
T1025 /workspace/coverage/cover_reg_top/17.edn_intr_test.1857554280 Aug 05 06:03:37 PM PDT 24 Aug 05 06:03:38 PM PDT 24 42225000 ps
T1026 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2519627167 Aug 05 06:03:41 PM PDT 24 Aug 05 06:03:42 PM PDT 24 56154473 ps
T1027 /workspace/coverage/cover_reg_top/44.edn_intr_test.166445157 Aug 05 06:03:51 PM PDT 24 Aug 05 06:03:52 PM PDT 24 13545044 ps
T1028 /workspace/coverage/cover_reg_top/46.edn_intr_test.441682306 Aug 05 06:03:49 PM PDT 24 Aug 05 06:03:50 PM PDT 24 11203146 ps
T1029 /workspace/coverage/cover_reg_top/49.edn_intr_test.1654678613 Aug 05 06:03:52 PM PDT 24 Aug 05 06:03:53 PM PDT 24 12157668 ps
T1030 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1505738947 Aug 05 06:03:41 PM PDT 24 Aug 05 06:03:42 PM PDT 24 151198517 ps
T1031 /workspace/coverage/cover_reg_top/38.edn_intr_test.4274957055 Aug 05 06:03:52 PM PDT 24 Aug 05 06:03:53 PM PDT 24 35312189 ps
T1032 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2646028445 Aug 05 06:03:22 PM PDT 24 Aug 05 06:03:23 PM PDT 24 74441107 ps
T1033 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.793069485 Aug 05 06:03:27 PM PDT 24 Aug 05 06:03:34 PM PDT 24 494695611 ps
T1034 /workspace/coverage/cover_reg_top/11.edn_tl_errors.4088299219 Aug 05 06:03:31 PM PDT 24 Aug 05 06:03:33 PM PDT 24 54661451 ps
T288 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.194394079 Aug 05 06:03:40 PM PDT 24 Aug 05 06:03:42 PM PDT 24 166464543 ps
T1035 /workspace/coverage/cover_reg_top/19.edn_intr_test.3864151760 Aug 05 06:03:44 PM PDT 24 Aug 05 06:03:45 PM PDT 24 24387864 ps
T1036 /workspace/coverage/cover_reg_top/8.edn_intr_test.1265078997 Aug 05 06:03:31 PM PDT 24 Aug 05 06:03:32 PM PDT 24 13650218 ps
T1037 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3371175238 Aug 05 06:03:27 PM PDT 24 Aug 05 06:03:29 PM PDT 24 100310169 ps
T1038 /workspace/coverage/cover_reg_top/0.edn_intr_test.3743755687 Aug 05 06:03:20 PM PDT 24 Aug 05 06:03:20 PM PDT 24 61645419 ps
T1039 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1486501232 Aug 05 06:03:26 PM PDT 24 Aug 05 06:03:28 PM PDT 24 37225823 ps
T1040 /workspace/coverage/cover_reg_top/16.edn_intr_test.2140571608 Aug 05 06:03:40 PM PDT 24 Aug 05 06:03:41 PM PDT 24 79331369 ps
T1041 /workspace/coverage/cover_reg_top/20.edn_intr_test.1845897418 Aug 05 06:03:45 PM PDT 24 Aug 05 06:03:47 PM PDT 24 47649329 ps
T1042 /workspace/coverage/cover_reg_top/0.edn_csr_rw.943726203 Aug 05 06:03:19 PM PDT 24 Aug 05 06:03:20 PM PDT 24 13258480 ps
T1043 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.66580971 Aug 05 06:03:44 PM PDT 24 Aug 05 06:03:46 PM PDT 24 21039883 ps
T1044 /workspace/coverage/cover_reg_top/5.edn_csr_rw.4263784501 Aug 05 06:03:27 PM PDT 24 Aug 05 06:03:28 PM PDT 24 11716803 ps
T1045 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1843480974 Aug 05 06:03:31 PM PDT 24 Aug 05 06:03:34 PM PDT 24 44611458 ps
T1046 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1488142631 Aug 05 06:03:41 PM PDT 24 Aug 05 06:03:43 PM PDT 24 24183803 ps
T1047 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3604850484 Aug 05 06:03:27 PM PDT 24 Aug 05 06:03:28 PM PDT 24 90734473 ps
T1048 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2604355227 Aug 05 06:03:22 PM PDT 24 Aug 05 06:03:24 PM PDT 24 133351571 ps
T1049 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3341429539 Aug 05 06:03:25 PM PDT 24 Aug 05 06:03:26 PM PDT 24 43780905 ps
T1050 /workspace/coverage/cover_reg_top/15.edn_intr_test.3640076981 Aug 05 06:03:42 PM PDT 24 Aug 05 06:03:43 PM PDT 24 14241957 ps
T1051 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.359246632 Aug 05 06:03:41 PM PDT 24 Aug 05 06:03:43 PM PDT 24 154333206 ps
T1052 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3534842778 Aug 05 06:03:32 PM PDT 24 Aug 05 06:03:33 PM PDT 24 12693673 ps
T1053 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2496426780 Aug 05 06:03:27 PM PDT 24 Aug 05 06:03:29 PM PDT 24 934622694 ps
T1054 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1863327893 Aug 05 06:03:23 PM PDT 24 Aug 05 06:03:27 PM PDT 24 517593094 ps
T1055 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3574693346 Aug 05 06:03:40 PM PDT 24 Aug 05 06:03:42 PM PDT 24 139148618 ps
T1056 /workspace/coverage/cover_reg_top/34.edn_intr_test.2547494653 Aug 05 06:03:50 PM PDT 24 Aug 05 06:03:51 PM PDT 24 27425368 ps
T1057 /workspace/coverage/cover_reg_top/37.edn_intr_test.985616838 Aug 05 06:03:49 PM PDT 24 Aug 05 06:03:49 PM PDT 24 16627904 ps
T1058 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3150439236 Aug 05 06:03:37 PM PDT 24 Aug 05 06:03:39 PM PDT 24 42337458 ps
T1059 /workspace/coverage/cover_reg_top/31.edn_intr_test.3518015733 Aug 05 06:03:46 PM PDT 24 Aug 05 06:03:47 PM PDT 24 29097985 ps
T1060 /workspace/coverage/cover_reg_top/40.edn_intr_test.814074972 Aug 05 06:03:49 PM PDT 24 Aug 05 06:03:50 PM PDT 24 180169259 ps
T265 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.975313689 Aug 05 06:03:26 PM PDT 24 Aug 05 06:03:27 PM PDT 24 18696193 ps
T1061 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3283432433 Aug 05 06:03:19 PM PDT 24 Aug 05 06:03:21 PM PDT 24 55043926 ps
T1062 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.378228101 Aug 05 06:03:31 PM PDT 24 Aug 05 06:03:33 PM PDT 24 25632757 ps
T1063 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1342889237 Aug 05 06:03:43 PM PDT 24 Aug 05 06:03:44 PM PDT 24 20910230 ps
T1064 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1393788492 Aug 05 06:03:47 PM PDT 24 Aug 05 06:03:49 PM PDT 24 218690003 ps
T1065 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3055146352 Aug 05 06:03:37 PM PDT 24 Aug 05 06:03:39 PM PDT 24 180090090 ps
T266 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3974738081 Aug 05 06:03:24 PM PDT 24 Aug 05 06:03:25 PM PDT 24 27018990 ps
T289 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2493090862 Aug 05 06:03:34 PM PDT 24 Aug 05 06:03:36 PM PDT 24 359162637 ps
T1066 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2608536207 Aug 05 06:03:26 PM PDT 24 Aug 05 06:03:28 PM PDT 24 34114196 ps
T1067 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4141232530 Aug 05 06:03:23 PM PDT 24 Aug 05 06:03:25 PM PDT 24 35209416 ps
T1068 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1610356549 Aug 05 06:03:22 PM PDT 24 Aug 05 06:03:24 PM PDT 24 70578025 ps
T1069 /workspace/coverage/cover_reg_top/1.edn_intr_test.1131891552 Aug 05 06:03:21 PM PDT 24 Aug 05 06:03:22 PM PDT 24 28103302 ps
T267 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3808447584 Aug 05 06:03:25 PM PDT 24 Aug 05 06:03:26 PM PDT 24 37388847 ps
T1070 /workspace/coverage/cover_reg_top/33.edn_intr_test.3548756489 Aug 05 06:03:46 PM PDT 24 Aug 05 06:03:47 PM PDT 24 14587364 ps
T1071 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3057957320 Aug 05 06:03:20 PM PDT 24 Aug 05 06:03:21 PM PDT 24 119629981 ps
T1072 /workspace/coverage/cover_reg_top/36.edn_intr_test.1855799159 Aug 05 06:03:49 PM PDT 24 Aug 05 06:03:51 PM PDT 24 13490965 ps
T1073 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1364381920 Aug 05 06:03:42 PM PDT 24 Aug 05 06:03:43 PM PDT 24 303031274 ps
T1074 /workspace/coverage/cover_reg_top/23.edn_intr_test.1034082468 Aug 05 06:03:47 PM PDT 24 Aug 05 06:03:48 PM PDT 24 34380748 ps
T1075 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3184939366 Aug 05 06:03:25 PM PDT 24 Aug 05 06:03:26 PM PDT 24 34245974 ps
T1076 /workspace/coverage/cover_reg_top/16.edn_tl_errors.4228751359 Aug 05 06:03:41 PM PDT 24 Aug 05 06:03:45 PM PDT 24 144779933 ps
T1077 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2681127939 Aug 05 06:03:39 PM PDT 24 Aug 05 06:03:40 PM PDT 24 15365661 ps
T1078 /workspace/coverage/cover_reg_top/2.edn_intr_test.3319392481 Aug 05 06:03:27 PM PDT 24 Aug 05 06:03:28 PM PDT 24 18807106 ps
T1079 /workspace/coverage/cover_reg_top/29.edn_intr_test.1802464617 Aug 05 06:03:48 PM PDT 24 Aug 05 06:03:49 PM PDT 24 37250298 ps
T1080 /workspace/coverage/cover_reg_top/30.edn_intr_test.3503513380 Aug 05 06:03:45 PM PDT 24 Aug 05 06:03:46 PM PDT 24 115332724 ps
T1081 /workspace/coverage/cover_reg_top/18.edn_intr_test.3757721196 Aug 05 06:03:43 PM PDT 24 Aug 05 06:03:44 PM PDT 24 11768592 ps
T1082 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3298187163 Aug 05 06:03:26 PM PDT 24 Aug 05 06:03:27 PM PDT 24 38862955 ps
T1083 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2940186539 Aug 05 06:03:40 PM PDT 24 Aug 05 06:03:41 PM PDT 24 35976643 ps
T1084 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4210535234 Aug 05 06:03:22 PM PDT 24 Aug 05 06:03:25 PM PDT 24 86284671 ps
T1085 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2526908268 Aug 05 06:03:41 PM PDT 24 Aug 05 06:03:42 PM PDT 24 87624467 ps
T1086 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3390424410 Aug 05 06:03:25 PM PDT 24 Aug 05 06:03:28 PM PDT 24 265946718 ps
T1087 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3405938525 Aug 05 06:03:45 PM PDT 24 Aug 05 06:03:46 PM PDT 24 21512618 ps
T1088 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1514753710 Aug 05 06:03:43 PM PDT 24 Aug 05 06:03:44 PM PDT 24 33113459 ps
T1089 /workspace/coverage/cover_reg_top/32.edn_intr_test.3608415416 Aug 05 06:03:43 PM PDT 24 Aug 05 06:03:45 PM PDT 24 26586827 ps
T268 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3952935734 Aug 05 06:03:22 PM PDT 24 Aug 05 06:03:24 PM PDT 24 78967485 ps
T1090 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1559920138 Aug 05 06:03:43 PM PDT 24 Aug 05 06:03:44 PM PDT 24 18648381 ps
T1091 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3937254114 Aug 05 06:03:36 PM PDT 24 Aug 05 06:03:37 PM PDT 24 13864403 ps
T1092 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1804532467 Aug 05 06:03:32 PM PDT 24 Aug 05 06:03:33 PM PDT 24 53061757 ps
T1093 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3074444120 Aug 05 06:03:37 PM PDT 24 Aug 05 06:03:39 PM PDT 24 74205141 ps
T1094 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4024529313 Aug 05 06:03:25 PM PDT 24 Aug 05 06:03:27 PM PDT 24 127949641 ps
T1095 /workspace/coverage/cover_reg_top/41.edn_intr_test.2880439715 Aug 05 06:03:51 PM PDT 24 Aug 05 06:03:52 PM PDT 24 14335552 ps
T1096 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1810946004 Aug 05 06:03:25 PM PDT 24 Aug 05 06:03:30 PM PDT 24 295846026 ps
T1097 /workspace/coverage/cover_reg_top/6.edn_intr_test.3207710029 Aug 05 06:03:27 PM PDT 24 Aug 05 06:03:28 PM PDT 24 42840272 ps
T1098 /workspace/coverage/cover_reg_top/11.edn_csr_rw.4213752847 Aug 05 06:03:32 PM PDT 24 Aug 05 06:03:33 PM PDT 24 27351925 ps
T1099 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3230827352 Aug 05 06:03:48 PM PDT 24 Aug 05 06:03:49 PM PDT 24 40111949 ps
T1100 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.262055692 Aug 05 06:03:20 PM PDT 24 Aug 05 06:03:23 PM PDT 24 168265568 ps
T1101 /workspace/coverage/cover_reg_top/39.edn_intr_test.1614303768 Aug 05 06:03:50 PM PDT 24 Aug 05 06:03:51 PM PDT 24 13950216 ps
T1102 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1353401110 Aug 05 06:03:40 PM PDT 24 Aug 05 06:03:42 PM PDT 24 23979496 ps
T1103 /workspace/coverage/cover_reg_top/0.edn_tl_errors.890994128 Aug 05 06:03:22 PM PDT 24 Aug 05 06:03:24 PM PDT 24 28871040 ps
T1104 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2834297874 Aug 05 06:03:21 PM PDT 24 Aug 05 06:03:22 PM PDT 24 33961812 ps
T1105 /workspace/coverage/cover_reg_top/28.edn_intr_test.3127816012 Aug 05 06:03:43 PM PDT 24 Aug 05 06:03:45 PM PDT 24 24419546 ps
T1106 /workspace/coverage/cover_reg_top/6.edn_tl_errors.4110814800 Aug 05 06:03:29 PM PDT 24 Aug 05 06:03:32 PM PDT 24 105711324 ps
T1107 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1327214840 Aug 05 06:03:41 PM PDT 24 Aug 05 06:03:42 PM PDT 24 10498498 ps
T269 /workspace/coverage/cover_reg_top/10.edn_csr_rw.712383208 Aug 05 06:03:33 PM PDT 24 Aug 05 06:03:34 PM PDT 24 48698611 ps
T1108 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3794906196 Aug 05 06:03:36 PM PDT 24 Aug 05 06:03:37 PM PDT 24 28951691 ps
T1109 /workspace/coverage/cover_reg_top/3.edn_intr_test.1512911080 Aug 05 06:03:21 PM PDT 24 Aug 05 06:03:22 PM PDT 24 32176584 ps
T1110 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.322130980 Aug 05 06:03:28 PM PDT 24 Aug 05 06:03:29 PM PDT 24 21516863 ps
T1111 /workspace/coverage/cover_reg_top/4.edn_intr_test.2771618729 Aug 05 06:03:27 PM PDT 24 Aug 05 06:03:28 PM PDT 24 16387068 ps
T1112 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1720972763 Aug 05 06:03:47 PM PDT 24 Aug 05 06:03:49 PM PDT 24 58693976 ps
T1113 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2056782111 Aug 05 06:03:20 PM PDT 24 Aug 05 06:03:22 PM PDT 24 31169855 ps
T1114 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3327102471 Aug 05 06:03:38 PM PDT 24 Aug 05 06:03:40 PM PDT 24 65632695 ps
T1115 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2287853844 Aug 05 06:03:29 PM PDT 24 Aug 05 06:03:30 PM PDT 24 13220017 ps
T1116 /workspace/coverage/cover_reg_top/11.edn_intr_test.1987405836 Aug 05 06:03:31 PM PDT 24 Aug 05 06:03:32 PM PDT 24 14323352 ps
T1117 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2329538132 Aug 05 06:03:22 PM PDT 24 Aug 05 06:03:25 PM PDT 24 131933579 ps
T1118 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3250052805 Aug 05 06:03:40 PM PDT 24 Aug 05 06:03:41 PM PDT 24 21730764 ps
T1119 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.353124186 Aug 05 06:03:26 PM PDT 24 Aug 05 06:03:28 PM PDT 24 177492516 ps
T270 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2705881798 Aug 05 06:03:23 PM PDT 24 Aug 05 06:03:24 PM PDT 24 17203557 ps
T1120 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1991350793 Aug 05 06:03:32 PM PDT 24 Aug 05 06:03:33 PM PDT 24 48163006 ps
T1121 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2827079552 Aug 05 06:03:48 PM PDT 24 Aug 05 06:03:50 PM PDT 24 417258362 ps
T1122 /workspace/coverage/cover_reg_top/35.edn_intr_test.2019965288 Aug 05 06:03:50 PM PDT 24 Aug 05 06:03:51 PM PDT 24 13410581 ps
T1123 /workspace/coverage/cover_reg_top/48.edn_intr_test.3390214360 Aug 05 06:03:51 PM PDT 24 Aug 05 06:03:52 PM PDT 24 11414592 ps
T1124 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1792426842 Aug 05 06:03:32 PM PDT 24 Aug 05 06:03:33 PM PDT 24 19550191 ps
T1125 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4115691426 Aug 05 06:03:46 PM PDT 24 Aug 05 06:03:47 PM PDT 24 184967119 ps

Test location /workspace/coverage/default/145.edn_alert.2988936480
Short name T3
Test name
Test status
Simulation time 41824468 ps
CPU time 1.22 seconds
Started Aug 05 06:09:11 PM PDT 24
Finished Aug 05 06:09:13 PM PDT 24
Peak memory 219036 kb
Host smart-705412e9-b356-4fa3-8ae5-724b30806324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988936480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2988936480
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/95.edn_genbits.2693050740
Short name T27
Test name
Test status
Simulation time 67526542 ps
CPU time 1.7 seconds
Started Aug 05 06:08:51 PM PDT 24
Finished Aug 05 06:08:53 PM PDT 24
Peak memory 218912 kb
Host smart-4e56b9be-9f27-4d9b-8ceb-e7e018ca99f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693050740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2693050740
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_stress_all.1016652137
Short name T41
Test name
Test status
Simulation time 1387221029 ps
CPU time 4.73 seconds
Started Aug 05 06:08:13 PM PDT 24
Finished Aug 05 06:08:18 PM PDT 24
Peak memory 215300 kb
Host smart-ab5096fc-ccea-4d8a-8592-c27c732ef642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016652137 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1016652137
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/92.edn_err.4222085198
Short name T8
Test name
Test status
Simulation time 27947872 ps
CPU time 1.28 seconds
Started Aug 05 06:08:57 PM PDT 24
Finished Aug 05 06:08:58 PM PDT 24
Peak memory 220384 kb
Host smart-7f804c36-53dd-4b20-9483-2dd789517573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222085198 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4222085198
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/103.edn_genbits.185738652
Short name T22
Test name
Test status
Simulation time 88975665 ps
CPU time 3.22 seconds
Started Aug 05 06:09:19 PM PDT 24
Finished Aug 05 06:09:22 PM PDT 24
Peak memory 220184 kb
Host smart-1f33cc96-204e-4d97-8959-bc71851ccf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185738652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.185738652
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1522294039
Short name T23
Test name
Test status
Simulation time 33793159522 ps
CPU time 381.1 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:14:03 PM PDT 24
Peak memory 218004 kb
Host smart-c35942bb-b2d3-4300-ae73-e421e2ffba0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522294039 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1522294039
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_err.1821708877
Short name T16
Test name
Test status
Simulation time 21550357 ps
CPU time 1.06 seconds
Started Aug 05 06:08:17 PM PDT 24
Finished Aug 05 06:08:18 PM PDT 24
Peak memory 224092 kb
Host smart-23ba472d-f3c3-4f65-957a-426e1b1b3562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821708877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1821708877
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/192.edn_alert.2809394158
Short name T49
Test name
Test status
Simulation time 72923310 ps
CPU time 1.2 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:28 PM PDT 24
Peak memory 219776 kb
Host smart-18fbc9cf-2e8b-44a9-9a45-6ccb689f6852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809394158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2809394158
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.429742429
Short name T55
Test name
Test status
Simulation time 95815540 ps
CPU time 1.15 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 219764 kb
Host smart-193af00e-a383-487d-a7d4-3bbe618598d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429742429 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.429742429
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_regwen.730335460
Short name T81
Test name
Test status
Simulation time 24651144 ps
CPU time 0.95 seconds
Started Aug 05 06:07:37 PM PDT 24
Finished Aug 05 06:07:38 PM PDT 24
Peak memory 207072 kb
Host smart-23c37fe6-a198-4395-ba1d-76f0f188e6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730335460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.730335460
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/38.edn_intr.3789943506
Short name T5
Test name
Test status
Simulation time 38615313 ps
CPU time 0.86 seconds
Started Aug 05 06:08:27 PM PDT 24
Finished Aug 05 06:08:28 PM PDT 24
Peak memory 215772 kb
Host smart-0b0c20d5-803b-4a25-9ac8-6358845c2684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789943506 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3789943506
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.194394079
Short name T288
Test name
Test status
Simulation time 166464543 ps
CPU time 2.84 seconds
Started Aug 05 06:03:40 PM PDT 24
Finished Aug 05 06:03:42 PM PDT 24
Peak memory 214888 kb
Host smart-0d758fbc-26cf-4d0d-8a05-e0904ea1813e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194394079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.194394079
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/176.edn_alert.3324260099
Short name T37
Test name
Test status
Simulation time 42772040 ps
CPU time 1.13 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:24 PM PDT 24
Peak memory 220348 kb
Host smart-545f6178-f70d-4c03-9178-27ad3cabf3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324260099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3324260099
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3388321449
Short name T97
Test name
Test status
Simulation time 53356044 ps
CPU time 1.57 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 219312 kb
Host smart-2743a26c-1d53-4d0b-a6d8-bfd311a1b9b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388321449 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3388321449
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/72.edn_err.3039600237
Short name T66
Test name
Test status
Simulation time 20142855 ps
CPU time 1.04 seconds
Started Aug 05 06:08:54 PM PDT 24
Finished Aug 05 06:08:55 PM PDT 24
Peak memory 218660 kb
Host smart-2b3d958b-abc1-4bc7-bc9c-b64272b3bc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039600237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3039600237
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/20.edn_alert.3095706410
Short name T157
Test name
Test status
Simulation time 27455840 ps
CPU time 1.19 seconds
Started Aug 05 06:07:59 PM PDT 24
Finished Aug 05 06:08:01 PM PDT 24
Peak memory 219544 kb
Host smart-2d36a16e-b9e9-460a-8447-4b523c10c96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095706410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3095706410
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.762944530
Short name T230
Test name
Test status
Simulation time 373664690738 ps
CPU time 937.94 seconds
Started Aug 05 06:08:17 PM PDT 24
Finished Aug 05 06:23:55 PM PDT 24
Peak memory 223628 kb
Host smart-215ed0df-a461-4581-b780-6cd74f92b981
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762944530 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.762944530
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.4161800003
Short name T71
Test name
Test status
Simulation time 48295075 ps
CPU time 1.14 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:36 PM PDT 24
Peak memory 218840 kb
Host smart-4229bbad-02bf-47fe-b62e-9047e60cbe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161800003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.4161800003
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.4218561028
Short name T29
Test name
Test status
Simulation time 18124697 ps
CPU time 0.88 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 216208 kb
Host smart-a9de95fb-da38-4568-a681-fc1a0683237d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218561028 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.4218561028
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/13.edn_intr.3825726490
Short name T86
Test name
Test status
Simulation time 25558027 ps
CPU time 0.93 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:07:50 PM PDT 24
Peak memory 215784 kb
Host smart-ab8a2e2f-ebf0-4537-ac4d-76c0c64c4684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825726490 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3825726490
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/123.edn_alert.246882737
Short name T33
Test name
Test status
Simulation time 45435010 ps
CPU time 1.22 seconds
Started Aug 05 06:09:20 PM PDT 24
Finished Aug 05 06:09:21 PM PDT 24
Peak memory 218520 kb
Host smart-1ea16d3f-e0f4-4b9d-80e5-460dcd89da54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246882737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.246882737
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.237292130
Short name T257
Test name
Test status
Simulation time 64600250 ps
CPU time 0.84 seconds
Started Aug 05 06:03:19 PM PDT 24
Finished Aug 05 06:03:20 PM PDT 24
Peak memory 206420 kb
Host smart-8a05bfb5-2b69-41f0-afaf-bf353cea8834
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237292130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.237292130
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/89.edn_genbits.233120372
Short name T21
Test name
Test status
Simulation time 175695608 ps
CPU time 2.8 seconds
Started Aug 05 06:09:01 PM PDT 24
Finished Aug 05 06:09:04 PM PDT 24
Peak memory 219964 kb
Host smart-0311eec0-ea31-4a6b-9551-f8d88fcf3ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233120372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.233120372
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1401044842
Short name T24
Test name
Test status
Simulation time 86196876712 ps
CPU time 592.89 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:17:38 PM PDT 24
Peak memory 220492 kb
Host smart-a7d8c4f5-c993-4bc4-9ab7-4d28746cf11c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401044842 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1401044842
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_alert.2510331482
Short name T278
Test name
Test status
Simulation time 244541987 ps
CPU time 1.12 seconds
Started Aug 05 06:08:11 PM PDT 24
Finished Aug 05 06:08:12 PM PDT 24
Peak memory 220620 kb
Host smart-394c9829-da9a-4667-979c-f12d7870b9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510331482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2510331482
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.4225954354
Short name T243
Test name
Test status
Simulation time 78770823 ps
CPU time 1.49 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 219968 kb
Host smart-d106a4ef-5f79-4e7b-80a7-c3a1c141691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225954354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.4225954354
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.838982835
Short name T146
Test name
Test status
Simulation time 130668633 ps
CPU time 1.29 seconds
Started Aug 05 06:09:25 PM PDT 24
Finished Aug 05 06:09:26 PM PDT 24
Peak memory 215700 kb
Host smart-ed4bbd23-6baf-4c2d-bf3d-0f8cccd27562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838982835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.838982835
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3277151586
Short name T131
Test name
Test status
Simulation time 167339102 ps
CPU time 1.12 seconds
Started Aug 05 06:07:41 PM PDT 24
Finished Aug 05 06:07:42 PM PDT 24
Peak memory 216780 kb
Host smart-c9f2eb37-1537-41a2-ab0c-31ff62066f47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277151586 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3277151586
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_alert.4042348972
Short name T124
Test name
Test status
Simulation time 151635750 ps
CPU time 1.19 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 218020 kb
Host smart-f7805f81-2559-48b5-9c4e-4f42e873844f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042348972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.4042348972
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3681698699
Short name T199
Test name
Test status
Simulation time 56657797938 ps
CPU time 1283.42 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:29:08 PM PDT 24
Peak memory 220836 kb
Host smart-295ac988-f652-47ed-9aee-65f0d2cd4a15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681698699 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3681698699
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.edn_alert.3660553795
Short name T80
Test name
Test status
Simulation time 55684268 ps
CPU time 1.13 seconds
Started Aug 05 06:09:17 PM PDT 24
Finished Aug 05 06:09:19 PM PDT 24
Peak memory 221296 kb
Host smart-616af26d-825e-4fc5-853d-fddc1620a25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660553795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.3660553795
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert.1348965865
Short name T298
Test name
Test status
Simulation time 105783499 ps
CPU time 1.12 seconds
Started Aug 05 06:07:47 PM PDT 24
Finished Aug 05 06:07:48 PM PDT 24
Peak memory 218384 kb
Host smart-6f41352d-c413-4086-8402-3b46be174df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348965865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1348965865
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/87.edn_alert.4194961672
Short name T575
Test name
Test status
Simulation time 43080716 ps
CPU time 1.19 seconds
Started Aug 05 06:09:15 PM PDT 24
Finished Aug 05 06:09:17 PM PDT 24
Peak memory 218720 kb
Host smart-82adbeca-eefb-49f2-a86f-8fb22180aef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194961672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.4194961672
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/92.edn_alert.1540376090
Short name T112
Test name
Test status
Simulation time 27691295 ps
CPU time 1.32 seconds
Started Aug 05 06:09:01 PM PDT 24
Finished Aug 05 06:09:02 PM PDT 24
Peak memory 219548 kb
Host smart-e55844a1-6b87-4e51-98b9-ebb5f8747097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540376090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.1540376090
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/30.edn_intr.1382442423
Short name T366
Test name
Test status
Simulation time 35572198 ps
CPU time 0.88 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:08:16 PM PDT 24
Peak memory 215116 kb
Host smart-a19b0165-0921-42b7-8c4f-6326208f518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382442423 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1382442423
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/115.edn_genbits.1543634995
Short name T441
Test name
Test status
Simulation time 147815371 ps
CPU time 1.02 seconds
Started Aug 05 06:09:15 PM PDT 24
Finished Aug 05 06:09:16 PM PDT 24
Peak memory 217156 kb
Host smart-86ce7797-8f84-462a-a3d3-13e66ae564ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543634995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1543634995
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable.2376163970
Short name T205
Test name
Test status
Simulation time 78988403 ps
CPU time 0.85 seconds
Started Aug 05 06:07:40 PM PDT 24
Finished Aug 05 06:07:41 PM PDT 24
Peak memory 216232 kb
Host smart-ea719e6d-ca47-4532-abce-185fdb2357a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376163970 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2376163970
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable.4229453517
Short name T896
Test name
Test status
Simulation time 24800318 ps
CPU time 0.88 seconds
Started Aug 05 06:08:08 PM PDT 24
Finished Aug 05 06:08:09 PM PDT 24
Peak memory 215424 kb
Host smart-618916b1-1289-4534-a8ec-4d244e1c7b89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229453517 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.4229453517
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/24.edn_intr.3211206834
Short name T689
Test name
Test status
Simulation time 30072901 ps
CPU time 0.88 seconds
Started Aug 05 06:08:09 PM PDT 24
Finished Aug 05 06:08:10 PM PDT 24
Peak memory 215800 kb
Host smart-c8476f18-d96e-4275-b303-564b9fb2dad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211206834 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3211206834
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable.3826746909
Short name T961
Test name
Test status
Simulation time 14033065 ps
CPU time 0.9 seconds
Started Aug 05 06:07:24 PM PDT 24
Finished Aug 05 06:07:25 PM PDT 24
Peak memory 216216 kb
Host smart-53234485-f690-48fb-9248-0fbd4a0b6e36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826746909 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3826746909
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1195568452
Short name T792
Test name
Test status
Simulation time 199538303 ps
CPU time 1 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 216976 kb
Host smart-9cbd7077-8c65-4649-9ec6-6b6ec2a6b308
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195568452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1195568452
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.4221558264
Short name T738
Test name
Test status
Simulation time 20602846 ps
CPU time 1.2 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 229584 kb
Host smart-697690d1-d623-4913-be70-e5d43fe7630c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221558264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.4221558264
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/114.edn_alert.2210395405
Short name T163
Test name
Test status
Simulation time 123112287 ps
CPU time 1.12 seconds
Started Aug 05 06:09:13 PM PDT 24
Finished Aug 05 06:09:14 PM PDT 24
Peak memory 219344 kb
Host smart-9fc0683a-08ff-4d0f-8d24-8b8ffb6ffc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210395405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.2210395405
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2186762933
Short name T96
Test name
Test status
Simulation time 43787048 ps
CPU time 1.06 seconds
Started Aug 05 06:07:53 PM PDT 24
Finished Aug 05 06:07:54 PM PDT 24
Peak memory 216732 kb
Host smart-4d6c132b-9ea2-46cd-a802-12d3be936731
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186762933 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2186762933
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_disable.2576723898
Short name T148
Test name
Test status
Simulation time 14273799 ps
CPU time 0.96 seconds
Started Aug 05 06:08:08 PM PDT 24
Finished Aug 05 06:08:09 PM PDT 24
Peak memory 216508 kb
Host smart-73b55da1-8a88-4707-9239-2d4da6ed16db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576723898 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2576723898
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/131.edn_alert.189937072
Short name T108
Test name
Test status
Simulation time 29858438 ps
CPU time 1.34 seconds
Started Aug 05 06:09:15 PM PDT 24
Finished Aug 05 06:09:17 PM PDT 24
Peak memory 220176 kb
Host smart-8c5ff018-ef44-4120-b619-f4236428fc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189937072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.189937072
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable.3756794890
Short name T193
Test name
Test status
Simulation time 12732100 ps
CPU time 0.91 seconds
Started Aug 05 06:07:52 PM PDT 24
Finished Aug 05 06:07:53 PM PDT 24
Peak memory 216524 kb
Host smart-fb050e94-b9eb-4efe-9f33-fb30df1b3ffb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756794890 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3756794890
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.18340667
Short name T188
Test name
Test status
Simulation time 217636245 ps
CPU time 1.07 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 216908 kb
Host smart-c0b50658-ac72-4cf1-81ba-c0951f96157e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18340667 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_dis
able_auto_req_mode.18340667
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/191.edn_alert.2318840009
Short name T929
Test name
Test status
Simulation time 25590473 ps
CPU time 1.18 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 215784 kb
Host smart-c83dbda6-33be-4576-98a1-af66abf2c8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318840009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2318840009
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/24.edn_err.2752480166
Short name T166
Test name
Test status
Simulation time 28610674 ps
CPU time 0.86 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 218088 kb
Host smart-d9c3aaab-882c-4e0d-9646-2bf1b7ddd5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752480166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2752480166
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1264811737
Short name T211
Test name
Test status
Simulation time 98522982 ps
CPU time 1.14 seconds
Started Aug 05 06:07:58 PM PDT 24
Finished Aug 05 06:07:59 PM PDT 24
Peak memory 216972 kb
Host smart-b7eeeb2c-65d3-40a7-8dab-142c103c0696
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264811737 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1264811737
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable.2097193969
Short name T79
Test name
Test status
Simulation time 13897616 ps
CPU time 0.91 seconds
Started Aug 05 06:08:15 PM PDT 24
Finished Aug 05 06:08:16 PM PDT 24
Peak memory 216380 kb
Host smart-82cef364-67eb-4e4c-bd42-2246c9cf296a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097193969 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2097193969
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1821198502
Short name T844
Test name
Test status
Simulation time 45694470 ps
CPU time 1 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 216864 kb
Host smart-c1a03b1c-7823-4f98-acf2-4a2f851807cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821198502 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1821198502
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_alert_test.1898533358
Short name T57
Test name
Test status
Simulation time 144299048 ps
CPU time 0.81 seconds
Started Aug 05 06:08:06 PM PDT 24
Finished Aug 05 06:08:07 PM PDT 24
Peak memory 206316 kb
Host smart-bf3ca014-d557-43c0-99d0-7f9cf2a5ed6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898533358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1898533358
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3005437485
Short name T262
Test name
Test status
Simulation time 17820904 ps
CPU time 0.89 seconds
Started Aug 05 06:03:28 PM PDT 24
Finished Aug 05 06:03:29 PM PDT 24
Peak memory 206588 kb
Host smart-52ecb886-d632-4bfc-9d89-56ceceb3f6bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005437485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3005437485
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/default/156.edn_genbits.1106564027
Short name T322
Test name
Test status
Simulation time 27806652 ps
CPU time 1.26 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 219772 kb
Host smart-c951de4c-5100-41d9-890d-bcb2144d056a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106564027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1106564027
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1691507817
Short name T315
Test name
Test status
Simulation time 85406445 ps
CPU time 1.17 seconds
Started Aug 05 06:09:12 PM PDT 24
Finished Aug 05 06:09:13 PM PDT 24
Peak memory 220064 kb
Host smart-f7da2629-6e2f-43d3-b43e-497163fbe9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691507817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1691507817
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3842217554
Short name T522
Test name
Test status
Simulation time 81934545 ps
CPU time 1.24 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 221868 kb
Host smart-e6b07100-5964-4029-87dc-804a7e0dc1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842217554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3842217554
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/229.edn_genbits.4022903458
Short name T309
Test name
Test status
Simulation time 55041664 ps
CPU time 1.16 seconds
Started Aug 05 06:09:34 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 218784 kb
Host smart-95630920-52e8-45e0-93f1-8e598195e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022903458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.4022903458
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_genbits.387603308
Short name T912
Test name
Test status
Simulation time 469267490 ps
CPU time 1.66 seconds
Started Aug 05 06:08:34 PM PDT 24
Finished Aug 05 06:08:36 PM PDT 24
Peak memory 217528 kb
Host smart-ba145e78-fa1d-4ec6-8f65-d3f30024409d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387603308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.387603308
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.533138841
Short name T332
Test name
Test status
Simulation time 47425350 ps
CPU time 1.38 seconds
Started Aug 05 06:09:15 PM PDT 24
Finished Aug 05 06:09:17 PM PDT 24
Peak memory 220096 kb
Host smart-6283046d-d2ca-42c2-876e-8798d4768ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533138841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.533138841
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2024111062
Short name T283
Test name
Test status
Simulation time 102541703 ps
CPU time 1.09 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 216812 kb
Host smart-c42e6029-8383-44d1-84bd-b9d3806d8d25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024111062 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2024111062
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.2561442850
Short name T324
Test name
Test status
Simulation time 47794512 ps
CPU time 1.59 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:07:47 PM PDT 24
Peak memory 218620 kb
Host smart-76f8e3bd-5d4a-4c20-8c8b-6d2fbc32bd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561442850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2561442850
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3030468261
Short name T39
Test name
Test status
Simulation time 28633125 ps
CPU time 1.24 seconds
Started Aug 05 06:09:07 PM PDT 24
Finished Aug 05 06:09:09 PM PDT 24
Peak memory 219320 kb
Host smart-44beb744-5875-4cfa-b135-d019457a1eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030468261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3030468261
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.2456969006
Short name T303
Test name
Test status
Simulation time 78456815 ps
CPU time 1.29 seconds
Started Aug 05 06:09:15 PM PDT 24
Finished Aug 05 06:09:17 PM PDT 24
Peak memory 218680 kb
Host smart-d8ea5494-018d-42ca-afb6-bed116b0645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456969006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2456969006
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.207650822
Short name T319
Test name
Test status
Simulation time 73754562 ps
CPU time 1.24 seconds
Started Aug 05 06:09:24 PM PDT 24
Finished Aug 05 06:09:25 PM PDT 24
Peak memory 219156 kb
Host smart-7bd91c07-46fd-438d-a29d-7570a25eb01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207650822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.207650822
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2727103077
Short name T317
Test name
Test status
Simulation time 49002618 ps
CPU time 1.74 seconds
Started Aug 05 06:09:15 PM PDT 24
Finished Aug 05 06:09:17 PM PDT 24
Peak memory 218488 kb
Host smart-deaecfb7-e047-489c-90e0-ea906c79fcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727103077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2727103077
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.2946199159
Short name T533
Test name
Test status
Simulation time 97330822 ps
CPU time 1.19 seconds
Started Aug 05 06:09:16 PM PDT 24
Finished Aug 05 06:09:18 PM PDT 24
Peak memory 219964 kb
Host smart-1c69693c-c5ef-46c1-a000-fcd63b83c13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946199159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2946199159
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2753935665
Short name T331
Test name
Test status
Simulation time 89404587 ps
CPU time 1.45 seconds
Started Aug 05 06:09:14 PM PDT 24
Finished Aug 05 06:09:16 PM PDT 24
Peak memory 218936 kb
Host smart-455ac964-ec93-462b-b694-8215933f3bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753935665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2753935665
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_genbits.3391224198
Short name T308
Test name
Test status
Simulation time 46602355 ps
CPU time 1.52 seconds
Started Aug 05 06:07:50 PM PDT 24
Finished Aug 05 06:07:52 PM PDT 24
Peak memory 217248 kb
Host smart-6758f301-2987-4f53-b108-b87df6bfd085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391224198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3391224198
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/290.edn_genbits.3885346104
Short name T69
Test name
Test status
Simulation time 128758746 ps
CPU time 1.69 seconds
Started Aug 05 06:09:53 PM PDT 24
Finished Aug 05 06:09:55 PM PDT 24
Peak memory 220244 kb
Host smart-24bac8a3-0460-45dc-917d-3824beb20216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885346104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3885346104
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1778209221
Short name T87
Test name
Test status
Simulation time 50362080 ps
CPU time 0.79 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 215428 kb
Host smart-a889624f-274b-4dfa-bb3e-009037efd5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778209221 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1778209221
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/39.edn_alert.2676952675
Short name T173
Test name
Test status
Simulation time 24830049 ps
CPU time 1.19 seconds
Started Aug 05 06:08:34 PM PDT 24
Finished Aug 05 06:08:35 PM PDT 24
Peak memory 218520 kb
Host smart-e5f72fe0-be11-4d6f-a146-d58cc418cef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676952675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2676952675
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2604355227
Short name T1048
Test name
Test status
Simulation time 133351571 ps
CPU time 1.68 seconds
Started Aug 05 06:03:22 PM PDT 24
Finished Aug 05 06:03:24 PM PDT 24
Peak memory 206656 kb
Host smart-fc469563-a879-42d1-812b-2be6789d69ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604355227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2604355227
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1610356549
Short name T1068
Test name
Test status
Simulation time 70578025 ps
CPU time 2.01 seconds
Started Aug 05 06:03:22 PM PDT 24
Finished Aug 05 06:03:24 PM PDT 24
Peak memory 206604 kb
Host smart-0f7f0fc6-6500-4120-9c75-571d5d72a1c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610356549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1610356549
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.745623562
Short name T989
Test name
Test status
Simulation time 89578368 ps
CPU time 0.82 seconds
Started Aug 05 06:03:24 PM PDT 24
Finished Aug 05 06:03:25 PM PDT 24
Peak memory 206392 kb
Host smart-321a839c-ec63-40bd-8a5a-2bcee27e133e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745623562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.745623562
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2834297874
Short name T1104
Test name
Test status
Simulation time 33961812 ps
CPU time 1.34 seconds
Started Aug 05 06:03:21 PM PDT 24
Finished Aug 05 06:03:22 PM PDT 24
Peak memory 214972 kb
Host smart-9c987c5e-c17a-4ce2-a7d9-4d82ece9817c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834297874 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2834297874
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.943726203
Short name T1042
Test name
Test status
Simulation time 13258480 ps
CPU time 0.84 seconds
Started Aug 05 06:03:19 PM PDT 24
Finished Aug 05 06:03:20 PM PDT 24
Peak memory 206792 kb
Host smart-cf5ee588-a292-4300-acf8-17a363b10ae9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943726203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.943726203
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3743755687
Short name T1038
Test name
Test status
Simulation time 61645419 ps
CPU time 0.82 seconds
Started Aug 05 06:03:20 PM PDT 24
Finished Aug 05 06:03:20 PM PDT 24
Peak memory 206404 kb
Host smart-a26452d8-6b8a-459f-bfd6-c9b24436e104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743755687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3743755687
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.605975034
Short name T258
Test name
Test status
Simulation time 31563086 ps
CPU time 1.25 seconds
Started Aug 05 06:03:18 PM PDT 24
Finished Aug 05 06:03:20 PM PDT 24
Peak memory 206768 kb
Host smart-dcc3c000-efc6-4e8b-9782-92d73799a62d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605975034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.605975034
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.890994128
Short name T1103
Test name
Test status
Simulation time 28871040 ps
CPU time 1.98 seconds
Started Aug 05 06:03:22 PM PDT 24
Finished Aug 05 06:03:24 PM PDT 24
Peak memory 214932 kb
Host smart-b54207ae-28bd-4a4a-9e76-353576f2a337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890994128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.890994128
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3171510141
Short name T222
Test name
Test status
Simulation time 107165119 ps
CPU time 1.62 seconds
Started Aug 05 06:03:27 PM PDT 24
Finished Aug 05 06:03:29 PM PDT 24
Peak memory 206748 kb
Host smart-9b899299-81c6-4c0a-bcd1-f7e27fb557c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171510141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3171510141
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4002725020
Short name T261
Test name
Test status
Simulation time 66850396 ps
CPU time 1.02 seconds
Started Aug 05 06:03:33 PM PDT 24
Finished Aug 05 06:03:34 PM PDT 24
Peak memory 206584 kb
Host smart-4ca7277e-d399-484c-bc89-98b94f8f5324
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002725020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.4002725020
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.793069485
Short name T1033
Test name
Test status
Simulation time 494695611 ps
CPU time 6.54 seconds
Started Aug 05 06:03:27 PM PDT 24
Finished Aug 05 06:03:34 PM PDT 24
Peak memory 206636 kb
Host smart-9d32bce4-ac09-4c34-b952-4432cba237d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793069485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.793069485
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3057957320
Short name T1071
Test name
Test status
Simulation time 119629981 ps
CPU time 1.48 seconds
Started Aug 05 06:03:20 PM PDT 24
Finished Aug 05 06:03:21 PM PDT 24
Peak memory 217860 kb
Host smart-a0078d15-265c-43a3-846e-dc2b241ada96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057957320 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3057957320
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3919574892
Short name T260
Test name
Test status
Simulation time 36252061 ps
CPU time 0.84 seconds
Started Aug 05 06:03:26 PM PDT 24
Finished Aug 05 06:03:27 PM PDT 24
Peak memory 206400 kb
Host smart-31f1b2f2-3997-4138-8185-339ca74da764
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919574892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3919574892
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1131891552
Short name T1069
Test name
Test status
Simulation time 28103302 ps
CPU time 0.93 seconds
Started Aug 05 06:03:21 PM PDT 24
Finished Aug 05 06:03:22 PM PDT 24
Peak memory 206604 kb
Host smart-d7156b5e-4759-45de-80ca-055cd7450999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131891552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1131891552
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3507406820
Short name T1018
Test name
Test status
Simulation time 32153284 ps
CPU time 1.1 seconds
Started Aug 05 06:03:23 PM PDT 24
Finished Aug 05 06:03:24 PM PDT 24
Peak memory 206720 kb
Host smart-f26a5333-1394-4098-8759-2f0e0cec5a77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507406820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3507406820
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1810946004
Short name T1096
Test name
Test status
Simulation time 295846026 ps
CPU time 4.61 seconds
Started Aug 05 06:03:25 PM PDT 24
Finished Aug 05 06:03:30 PM PDT 24
Peak memory 223168 kb
Host smart-23aa8478-9d68-4ab6-bb6a-8e1033a3c8ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810946004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1810946004
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.262055692
Short name T1100
Test name
Test status
Simulation time 168265568 ps
CPU time 2.48 seconds
Started Aug 05 06:03:20 PM PDT 24
Finished Aug 05 06:03:23 PM PDT 24
Peak memory 206704 kb
Host smart-ff1f0c59-fc9d-4699-a143-e2ecc1a579a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262055692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.262055692
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3794906196
Short name T1108
Test name
Test status
Simulation time 28951691 ps
CPU time 1.39 seconds
Started Aug 05 06:03:36 PM PDT 24
Finished Aug 05 06:03:37 PM PDT 24
Peak memory 223056 kb
Host smart-c6cfd764-4598-4ef4-9eae-9f2e15e91fc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794906196 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3794906196
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.712383208
Short name T269
Test name
Test status
Simulation time 48698611 ps
CPU time 0.81 seconds
Started Aug 05 06:03:33 PM PDT 24
Finished Aug 05 06:03:34 PM PDT 24
Peak memory 206380 kb
Host smart-93777a57-f325-48db-8b72-3047a76b5baa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712383208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.712383208
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3974070440
Short name T992
Test name
Test status
Simulation time 13424681 ps
CPU time 0.88 seconds
Started Aug 05 06:03:38 PM PDT 24
Finished Aug 05 06:03:39 PM PDT 24
Peak memory 206624 kb
Host smart-31e67c5b-20e2-433f-bad5-17e23dc32297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974070440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3974070440
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.104808332
Short name T1016
Test name
Test status
Simulation time 119548152 ps
CPU time 1.39 seconds
Started Aug 05 06:03:33 PM PDT 24
Finished Aug 05 06:03:35 PM PDT 24
Peak memory 206720 kb
Host smart-09bc4e7b-3581-418c-8d3e-8255fb1130d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104808332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.104808332
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2115979641
Short name T1008
Test name
Test status
Simulation time 137559285 ps
CPU time 4.63 seconds
Started Aug 05 06:03:31 PM PDT 24
Finished Aug 05 06:03:36 PM PDT 24
Peak memory 214996 kb
Host smart-c06f79ec-14c8-4622-aea1-05cf52caecf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115979641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2115979641
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2493090862
Short name T289
Test name
Test status
Simulation time 359162637 ps
CPU time 2.56 seconds
Started Aug 05 06:03:34 PM PDT 24
Finished Aug 05 06:03:36 PM PDT 24
Peak memory 214912 kb
Host smart-b3b4edab-f848-4630-b353-cb27af2d1f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493090862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2493090862
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4162303367
Short name T991
Test name
Test status
Simulation time 29433408 ps
CPU time 1.43 seconds
Started Aug 05 06:03:32 PM PDT 24
Finished Aug 05 06:03:34 PM PDT 24
Peak memory 218420 kb
Host smart-a2052750-944e-416a-aebc-31ce5dd61411
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162303367 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.4162303367
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.4213752847
Short name T1098
Test name
Test status
Simulation time 27351925 ps
CPU time 0.86 seconds
Started Aug 05 06:03:32 PM PDT 24
Finished Aug 05 06:03:33 PM PDT 24
Peak memory 206596 kb
Host smart-6b523bfb-ab6d-4773-85dd-535def35cec8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213752847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.4213752847
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1987405836
Short name T1116
Test name
Test status
Simulation time 14323352 ps
CPU time 0.92 seconds
Started Aug 05 06:03:31 PM PDT 24
Finished Aug 05 06:03:32 PM PDT 24
Peak memory 206684 kb
Host smart-4962f956-a47e-42ad-ade3-82f63b68fceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987405836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1987405836
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1792426842
Short name T1124
Test name
Test status
Simulation time 19550191 ps
CPU time 1.2 seconds
Started Aug 05 06:03:32 PM PDT 24
Finished Aug 05 06:03:33 PM PDT 24
Peak memory 206768 kb
Host smart-5a8fc29b-3b5c-4c1c-be6e-7de966cfb02b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792426842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1792426842
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.4088299219
Short name T1034
Test name
Test status
Simulation time 54661451 ps
CPU time 2.24 seconds
Started Aug 05 06:03:31 PM PDT 24
Finished Aug 05 06:03:33 PM PDT 24
Peak memory 215036 kb
Host smart-d70b2da5-6b1d-4305-9325-82cca258f52e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088299219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.4088299219
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4093786350
Short name T1022
Test name
Test status
Simulation time 78970548 ps
CPU time 1.5 seconds
Started Aug 05 06:03:35 PM PDT 24
Finished Aug 05 06:03:37 PM PDT 24
Peak memory 206956 kb
Host smart-733b52c7-7597-4512-a6d3-0dbc80f7c6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093786350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.4093786350
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3074444120
Short name T1093
Test name
Test status
Simulation time 74205141 ps
CPU time 1.14 seconds
Started Aug 05 06:03:37 PM PDT 24
Finished Aug 05 06:03:39 PM PDT 24
Peak memory 214884 kb
Host smart-0d486758-e724-4be9-9af0-dff4390c8cfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074444120 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3074444120
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2810441747
Short name T274
Test name
Test status
Simulation time 65172844 ps
CPU time 0.87 seconds
Started Aug 05 06:03:32 PM PDT 24
Finished Aug 05 06:03:33 PM PDT 24
Peak memory 206572 kb
Host smart-631e1ea7-bb3a-4944-958e-13d3d94d5932
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810441747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2810441747
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1122222741
Short name T1019
Test name
Test status
Simulation time 15296193 ps
CPU time 0.84 seconds
Started Aug 05 06:03:31 PM PDT 24
Finished Aug 05 06:03:32 PM PDT 24
Peak memory 206620 kb
Host smart-0daf4ec3-d5e2-4e1a-8388-2a009149345c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122222741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1122222741
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2028219916
Short name T276
Test name
Test status
Simulation time 122171716 ps
CPU time 1.48 seconds
Started Aug 05 06:03:30 PM PDT 24
Finished Aug 05 06:03:31 PM PDT 24
Peak memory 206780 kb
Host smart-df6e8914-896f-4656-8344-353de6ee83a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028219916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2028219916
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1362669125
Short name T1024
Test name
Test status
Simulation time 246501385 ps
CPU time 2.79 seconds
Started Aug 05 06:03:38 PM PDT 24
Finished Aug 05 06:03:41 PM PDT 24
Peak memory 215012 kb
Host smart-3b10e22d-581f-425a-9415-1a35695a48f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362669125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1362669125
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1991350793
Short name T1120
Test name
Test status
Simulation time 48163006 ps
CPU time 1.56 seconds
Started Aug 05 06:03:32 PM PDT 24
Finished Aug 05 06:03:33 PM PDT 24
Peak memory 214988 kb
Host smart-633c7370-bca5-4ebf-86fe-cbaa09194f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991350793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1991350793
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2526908268
Short name T1085
Test name
Test status
Simulation time 87624467 ps
CPU time 1.65 seconds
Started Aug 05 06:03:41 PM PDT 24
Finished Aug 05 06:03:42 PM PDT 24
Peak memory 214984 kb
Host smart-488a4518-9580-4430-a4e0-5c0db1c7fcbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526908268 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2526908268
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1327214840
Short name T1107
Test name
Test status
Simulation time 10498498 ps
CPU time 0.82 seconds
Started Aug 05 06:03:41 PM PDT 24
Finished Aug 05 06:03:42 PM PDT 24
Peak memory 206568 kb
Host smart-61295552-ee39-48be-a33c-6587234a44d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327214840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1327214840
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.487749522
Short name T1014
Test name
Test status
Simulation time 86606401 ps
CPU time 0.91 seconds
Started Aug 05 06:03:38 PM PDT 24
Finished Aug 05 06:03:39 PM PDT 24
Peak memory 206568 kb
Host smart-114b5267-ca00-457f-ac34-05a483f17135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487749522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.487749522
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2519627167
Short name T1026
Test name
Test status
Simulation time 56154473 ps
CPU time 1.06 seconds
Started Aug 05 06:03:41 PM PDT 24
Finished Aug 05 06:03:42 PM PDT 24
Peak memory 206816 kb
Host smart-46f05d4c-b74f-4b0b-b96f-b4ce08c51514
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519627167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2519627167
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3055146352
Short name T1065
Test name
Test status
Simulation time 180090090 ps
CPU time 2.11 seconds
Started Aug 05 06:03:37 PM PDT 24
Finished Aug 05 06:03:39 PM PDT 24
Peak memory 215068 kb
Host smart-b8a8c24a-c73f-40bf-8811-e94fe78df75f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055146352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3055146352
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3574693346
Short name T1055
Test name
Test status
Simulation time 139148618 ps
CPU time 2.33 seconds
Started Aug 05 06:03:40 PM PDT 24
Finished Aug 05 06:03:42 PM PDT 24
Peak memory 206760 kb
Host smart-ed37bc01-2046-4177-b490-90ab29ef1199
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574693346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3574693346
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.668057073
Short name T1002
Test name
Test status
Simulation time 17040702 ps
CPU time 1.1 seconds
Started Aug 05 06:03:38 PM PDT 24
Finished Aug 05 06:03:39 PM PDT 24
Peak memory 206860 kb
Host smart-74e69ff9-68ba-48e4-b529-4a8b37441fcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668057073 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.668057073
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2681127939
Short name T1077
Test name
Test status
Simulation time 15365661 ps
CPU time 0.99 seconds
Started Aug 05 06:03:39 PM PDT 24
Finished Aug 05 06:03:40 PM PDT 24
Peak memory 206552 kb
Host smart-bd8e162f-86d4-4d99-be51-ac3777ce2d84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681127939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2681127939
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3903213518
Short name T996
Test name
Test status
Simulation time 71237984 ps
CPU time 0.81 seconds
Started Aug 05 06:03:39 PM PDT 24
Finished Aug 05 06:03:40 PM PDT 24
Peak memory 206404 kb
Host smart-aca3c7a1-5ab8-4ad9-a41e-1cc7aa47eb00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903213518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3903213518
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4115691426
Short name T1125
Test name
Test status
Simulation time 184967119 ps
CPU time 1.18 seconds
Started Aug 05 06:03:46 PM PDT 24
Finished Aug 05 06:03:47 PM PDT 24
Peak memory 206792 kb
Host smart-4ce6b671-d3c1-41a8-9632-2e1923eda651
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115691426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.4115691426
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1715766125
Short name T1009
Test name
Test status
Simulation time 323506184 ps
CPU time 2.74 seconds
Started Aug 05 06:03:38 PM PDT 24
Finished Aug 05 06:03:41 PM PDT 24
Peak memory 214984 kb
Host smart-6765f454-f735-4a9d-a302-f6475d5b62e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715766125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1715766125
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3327102471
Short name T1114
Test name
Test status
Simulation time 65632695 ps
CPU time 1.96 seconds
Started Aug 05 06:03:38 PM PDT 24
Finished Aug 05 06:03:40 PM PDT 24
Peak memory 206732 kb
Host smart-f1630240-ab50-4deb-aee5-778cbaef49d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327102471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3327102471
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3491001221
Short name T1012
Test name
Test status
Simulation time 189710723 ps
CPU time 1.29 seconds
Started Aug 05 06:03:42 PM PDT 24
Finished Aug 05 06:03:44 PM PDT 24
Peak memory 215056 kb
Host smart-dbfa519c-90ba-4ddb-907f-e65f8636bd77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491001221 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3491001221
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1353401110
Short name T1102
Test name
Test status
Simulation time 23979496 ps
CPU time 0.97 seconds
Started Aug 05 06:03:40 PM PDT 24
Finished Aug 05 06:03:42 PM PDT 24
Peak memory 206580 kb
Host smart-7233243b-24f1-4ae5-be49-a24a0a07a1e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353401110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1353401110
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3640076981
Short name T1050
Test name
Test status
Simulation time 14241957 ps
CPU time 0.93 seconds
Started Aug 05 06:03:42 PM PDT 24
Finished Aug 05 06:03:43 PM PDT 24
Peak memory 206596 kb
Host smart-f6ff3fda-dcdf-4808-b6b8-56bccc696060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640076981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3640076981
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2325848579
Short name T259
Test name
Test status
Simulation time 116957168 ps
CPU time 1.34 seconds
Started Aug 05 06:03:41 PM PDT 24
Finished Aug 05 06:03:42 PM PDT 24
Peak memory 206756 kb
Host smart-fee0c2e8-1708-40a7-99b4-069ec8f65a3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325848579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2325848579
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3150439236
Short name T1058
Test name
Test status
Simulation time 42337458 ps
CPU time 1.53 seconds
Started Aug 05 06:03:37 PM PDT 24
Finished Aug 05 06:03:39 PM PDT 24
Peak memory 214972 kb
Host smart-abd80b86-cdc7-45ff-8847-ad1c9defb112
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150439236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3150439236
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2905718270
Short name T1011
Test name
Test status
Simulation time 22335402 ps
CPU time 1.13 seconds
Started Aug 05 06:03:40 PM PDT 24
Finished Aug 05 06:03:42 PM PDT 24
Peak memory 214948 kb
Host smart-fa8811fd-afbd-43c6-91ca-a68db68db35f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905718270 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2905718270
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3741420158
Short name T1013
Test name
Test status
Simulation time 13337872 ps
CPU time 0.9 seconds
Started Aug 05 06:03:42 PM PDT 24
Finished Aug 05 06:03:43 PM PDT 24
Peak memory 206576 kb
Host smart-937fcceb-3ed8-434b-b4ac-fe80aeb59bc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741420158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3741420158
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2140571608
Short name T1040
Test name
Test status
Simulation time 79331369 ps
CPU time 0.87 seconds
Started Aug 05 06:03:40 PM PDT 24
Finished Aug 05 06:03:41 PM PDT 24
Peak memory 206416 kb
Host smart-b734a7bd-f037-453a-89ee-492c16a65a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140571608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2140571608
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1488142631
Short name T1046
Test name
Test status
Simulation time 24183803 ps
CPU time 1.17 seconds
Started Aug 05 06:03:41 PM PDT 24
Finished Aug 05 06:03:43 PM PDT 24
Peak memory 206716 kb
Host smart-a868c703-3609-4bbe-964d-b12bbb8d04f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488142631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1488142631
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.4228751359
Short name T1076
Test name
Test status
Simulation time 144779933 ps
CPU time 4.43 seconds
Started Aug 05 06:03:41 PM PDT 24
Finished Aug 05 06:03:45 PM PDT 24
Peak memory 214992 kb
Host smart-b3e7ee30-94fd-4d5f-93af-62cbcd36a221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228751359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.4228751359
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2963266769
Short name T221
Test name
Test status
Simulation time 185558895 ps
CPU time 2.61 seconds
Started Aug 05 06:03:41 PM PDT 24
Finished Aug 05 06:03:44 PM PDT 24
Peak memory 206732 kb
Host smart-97869cef-b34e-4343-a19d-e1b1694dc3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963266769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2963266769
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.66580971
Short name T1043
Test name
Test status
Simulation time 21039883 ps
CPU time 1.24 seconds
Started Aug 05 06:03:44 PM PDT 24
Finished Aug 05 06:03:46 PM PDT 24
Peak memory 214980 kb
Host smart-c9f76089-c6d5-4633-8e1d-b55fcaee45c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66580971 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.66580971
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2940186539
Short name T1083
Test name
Test status
Simulation time 35976643 ps
CPU time 0.84 seconds
Started Aug 05 06:03:40 PM PDT 24
Finished Aug 05 06:03:41 PM PDT 24
Peak memory 206380 kb
Host smart-a1859085-0330-407c-9b2c-b2857a9c4a36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940186539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2940186539
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1857554280
Short name T1025
Test name
Test status
Simulation time 42225000 ps
CPU time 0.89 seconds
Started Aug 05 06:03:37 PM PDT 24
Finished Aug 05 06:03:38 PM PDT 24
Peak memory 206592 kb
Host smart-04c31824-e653-4a11-9591-a454d5e83f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857554280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1857554280
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3250052805
Short name T1118
Test name
Test status
Simulation time 21730764 ps
CPU time 0.9 seconds
Started Aug 05 06:03:40 PM PDT 24
Finished Aug 05 06:03:41 PM PDT 24
Peak memory 206712 kb
Host smart-cff4b3d8-e767-4bf3-8331-9e5044872dd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250052805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3250052805
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.320655362
Short name T1005
Test name
Test status
Simulation time 128186978 ps
CPU time 1.92 seconds
Started Aug 05 06:03:40 PM PDT 24
Finished Aug 05 06:03:42 PM PDT 24
Peak memory 215056 kb
Host smart-b9f23f6c-9765-4fcc-96cd-0d21caf6cd14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320655362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.320655362
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1505738947
Short name T1030
Test name
Test status
Simulation time 151198517 ps
CPU time 1.49 seconds
Started Aug 05 06:03:41 PM PDT 24
Finished Aug 05 06:03:42 PM PDT 24
Peak memory 206780 kb
Host smart-b60aef1c-8d70-4fd0-be27-c152ac5d9d70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505738947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1505738947
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3405938525
Short name T1087
Test name
Test status
Simulation time 21512618 ps
CPU time 1.14 seconds
Started Aug 05 06:03:45 PM PDT 24
Finished Aug 05 06:03:46 PM PDT 24
Peak memory 214960 kb
Host smart-74a21435-15b0-42af-8287-24af69c9c4f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405938525 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3405938525
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1342889237
Short name T1063
Test name
Test status
Simulation time 20910230 ps
CPU time 0.9 seconds
Started Aug 05 06:03:43 PM PDT 24
Finished Aug 05 06:03:44 PM PDT 24
Peak memory 206600 kb
Host smart-3bf740bb-c269-4a9c-b303-19749788389d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342889237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1342889237
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3757721196
Short name T1081
Test name
Test status
Simulation time 11768592 ps
CPU time 0.88 seconds
Started Aug 05 06:03:43 PM PDT 24
Finished Aug 05 06:03:44 PM PDT 24
Peak memory 206600 kb
Host smart-a506862d-8a1b-43a5-94af-8a5a6e6a811c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757721196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3757721196
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.359246632
Short name T1051
Test name
Test status
Simulation time 154333206 ps
CPU time 1.29 seconds
Started Aug 05 06:03:41 PM PDT 24
Finished Aug 05 06:03:43 PM PDT 24
Peak memory 206780 kb
Host smart-8f3d7f40-25f0-41e7-9202-ff802949c9f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359246632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.359246632
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2827079552
Short name T1121
Test name
Test status
Simulation time 417258362 ps
CPU time 1.99 seconds
Started Aug 05 06:03:48 PM PDT 24
Finished Aug 05 06:03:50 PM PDT 24
Peak memory 215060 kb
Host smart-f1900de4-b61e-4e05-a184-fcc8e3d9aa42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827079552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2827079552
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1364381920
Short name T1073
Test name
Test status
Simulation time 303031274 ps
CPU time 1.56 seconds
Started Aug 05 06:03:42 PM PDT 24
Finished Aug 05 06:03:43 PM PDT 24
Peak memory 206784 kb
Host smart-df9749a7-efed-40e1-be58-db68959dfcbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364381920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1364381920
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1514753710
Short name T1088
Test name
Test status
Simulation time 33113459 ps
CPU time 1.53 seconds
Started Aug 05 06:03:43 PM PDT 24
Finished Aug 05 06:03:44 PM PDT 24
Peak memory 214984 kb
Host smart-7f13b7a7-3f98-45d1-b922-5037cdf41b71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514753710 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1514753710
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1559920138
Short name T1090
Test name
Test status
Simulation time 18648381 ps
CPU time 0.82 seconds
Started Aug 05 06:03:43 PM PDT 24
Finished Aug 05 06:03:44 PM PDT 24
Peak memory 206548 kb
Host smart-9dde43c2-6017-44fe-93bb-94ca1d611ffc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559920138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1559920138
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3864151760
Short name T1035
Test name
Test status
Simulation time 24387864 ps
CPU time 0.85 seconds
Started Aug 05 06:03:44 PM PDT 24
Finished Aug 05 06:03:45 PM PDT 24
Peak memory 206408 kb
Host smart-1714801b-bdea-40b0-8dc6-11ed3fcf9538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864151760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3864151760
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3230827352
Short name T1099
Test name
Test status
Simulation time 40111949 ps
CPU time 1.1 seconds
Started Aug 05 06:03:48 PM PDT 24
Finished Aug 05 06:03:49 PM PDT 24
Peak memory 206208 kb
Host smart-09078ba6-9bde-44be-9e06-6119dbdb175e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230827352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3230827352
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1720972763
Short name T1112
Test name
Test status
Simulation time 58693976 ps
CPU time 2.28 seconds
Started Aug 05 06:03:47 PM PDT 24
Finished Aug 05 06:03:49 PM PDT 24
Peak memory 214532 kb
Host smart-98e2dc36-38dd-4f3b-9415-f337cfef646a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720972763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1720972763
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1393788492
Short name T1064
Test name
Test status
Simulation time 218690003 ps
CPU time 1.48 seconds
Started Aug 05 06:03:47 PM PDT 24
Finished Aug 05 06:03:49 PM PDT 24
Peak memory 206260 kb
Host smart-9eade038-4410-4768-ad2e-e5c7ffeb538f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393788492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1393788492
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3952935734
Short name T268
Test name
Test status
Simulation time 78967485 ps
CPU time 1.65 seconds
Started Aug 05 06:03:22 PM PDT 24
Finished Aug 05 06:03:24 PM PDT 24
Peak memory 206576 kb
Host smart-e3291b00-1104-4d4d-8bf5-b6ee2d7c41ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952935734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3952935734
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4210535234
Short name T1084
Test name
Test status
Simulation time 86284671 ps
CPU time 3.22 seconds
Started Aug 05 06:03:22 PM PDT 24
Finished Aug 05 06:03:25 PM PDT 24
Peak memory 206476 kb
Host smart-6bbc99d0-a8e1-4fbb-8f77-b861820da7a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210535234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.4210535234
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3901214766
Short name T990
Test name
Test status
Simulation time 25940463 ps
CPU time 0.87 seconds
Started Aug 05 06:03:23 PM PDT 24
Finished Aug 05 06:03:24 PM PDT 24
Peak memory 206588 kb
Host smart-91746261-0cf4-409d-9239-ec9c930e228d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901214766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3901214766
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2646028445
Short name T1032
Test name
Test status
Simulation time 74441107 ps
CPU time 1.42 seconds
Started Aug 05 06:03:22 PM PDT 24
Finished Aug 05 06:03:23 PM PDT 24
Peak memory 215040 kb
Host smart-0829e896-a88f-4c6b-b8e9-ccb31cd68a43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646028445 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2646028445
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2829789012
Short name T263
Test name
Test status
Simulation time 93295715 ps
CPU time 0.84 seconds
Started Aug 05 06:03:19 PM PDT 24
Finished Aug 05 06:03:19 PM PDT 24
Peak memory 206392 kb
Host smart-b717e057-7837-4bf1-a9a7-7858c28e1b09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829789012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2829789012
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3319392481
Short name T1078
Test name
Test status
Simulation time 18807106 ps
CPU time 0.84 seconds
Started Aug 05 06:03:27 PM PDT 24
Finished Aug 05 06:03:28 PM PDT 24
Peak memory 206436 kb
Host smart-bd150835-5309-4fff-b10b-15defc8a9e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319392481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3319392481
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2056782111
Short name T1113
Test name
Test status
Simulation time 31169855 ps
CPU time 1.36 seconds
Started Aug 05 06:03:20 PM PDT 24
Finished Aug 05 06:03:22 PM PDT 24
Peak memory 206764 kb
Host smart-770de2fd-2af8-4a7c-8c07-546701beceaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056782111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2056782111
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3283432433
Short name T1061
Test name
Test status
Simulation time 55043926 ps
CPU time 2.16 seconds
Started Aug 05 06:03:19 PM PDT 24
Finished Aug 05 06:03:21 PM PDT 24
Peak memory 218664 kb
Host smart-05fd4d91-1ecc-46a3-b21f-9bf05f457adc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283432433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3283432433
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4024529313
Short name T1094
Test name
Test status
Simulation time 127949641 ps
CPU time 2.23 seconds
Started Aug 05 06:03:25 PM PDT 24
Finished Aug 05 06:03:27 PM PDT 24
Peak memory 206720 kb
Host smart-0d1b8380-f679-4fc6-969c-1dead8f91a17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024529313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4024529313
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1845897418
Short name T1041
Test name
Test status
Simulation time 47649329 ps
CPU time 0.89 seconds
Started Aug 05 06:03:45 PM PDT 24
Finished Aug 05 06:03:47 PM PDT 24
Peak memory 206600 kb
Host smart-2a0e7d97-7f46-4a3f-af6a-d318a75451ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845897418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1845897418
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4078767487
Short name T993
Test name
Test status
Simulation time 26331924 ps
CPU time 0.9 seconds
Started Aug 05 06:03:50 PM PDT 24
Finished Aug 05 06:03:51 PM PDT 24
Peak memory 206612 kb
Host smart-db66ccf1-c3f3-4a50-8392-7bc4cc4daa71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078767487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4078767487
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3703156348
Short name T995
Test name
Test status
Simulation time 13959919 ps
CPU time 0.87 seconds
Started Aug 05 06:03:46 PM PDT 24
Finished Aug 05 06:03:47 PM PDT 24
Peak memory 206548 kb
Host smart-f2ce6ca8-bac6-4238-9bf4-2431c043320b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703156348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3703156348
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1034082468
Short name T1074
Test name
Test status
Simulation time 34380748 ps
CPU time 0.79 seconds
Started Aug 05 06:03:47 PM PDT 24
Finished Aug 05 06:03:48 PM PDT 24
Peak memory 205900 kb
Host smart-8526d773-758e-4a09-847c-4c4b4088d6b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034082468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1034082468
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.60085988
Short name T1003
Test name
Test status
Simulation time 15034595 ps
CPU time 0.91 seconds
Started Aug 05 06:03:46 PM PDT 24
Finished Aug 05 06:03:47 PM PDT 24
Peak memory 206592 kb
Host smart-612ca269-a279-40f0-8f4c-0142323f905b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60085988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.60085988
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3991344179
Short name T1001
Test name
Test status
Simulation time 119030775 ps
CPU time 0.87 seconds
Started Aug 05 06:03:49 PM PDT 24
Finished Aug 05 06:03:50 PM PDT 24
Peak memory 206704 kb
Host smart-806e37d5-0d36-45b2-8438-431118efdd4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991344179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3991344179
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2210069400
Short name T1000
Test name
Test status
Simulation time 87799218 ps
CPU time 0.8 seconds
Started Aug 05 06:03:44 PM PDT 24
Finished Aug 05 06:03:45 PM PDT 24
Peak memory 206408 kb
Host smart-4f2c929c-c326-4516-aa3d-640b32aacd23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210069400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2210069400
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2557971168
Short name T997
Test name
Test status
Simulation time 42942616 ps
CPU time 0.86 seconds
Started Aug 05 06:03:45 PM PDT 24
Finished Aug 05 06:03:46 PM PDT 24
Peak memory 206600 kb
Host smart-0c4b3905-00db-4edd-a51a-21312dd43bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557971168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2557971168
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3127816012
Short name T1105
Test name
Test status
Simulation time 24419546 ps
CPU time 0.85 seconds
Started Aug 05 06:03:43 PM PDT 24
Finished Aug 05 06:03:45 PM PDT 24
Peak memory 206588 kb
Host smart-094ba42b-448e-4146-b083-014bc82a194f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127816012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3127816012
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1802464617
Short name T1079
Test name
Test status
Simulation time 37250298 ps
CPU time 0.89 seconds
Started Aug 05 06:03:48 PM PDT 24
Finished Aug 05 06:03:49 PM PDT 24
Peak memory 206616 kb
Host smart-0499edde-1e68-46da-9965-e22f4463018f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802464617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1802464617
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3974738081
Short name T266
Test name
Test status
Simulation time 27018990 ps
CPU time 1.28 seconds
Started Aug 05 06:03:24 PM PDT 24
Finished Aug 05 06:03:25 PM PDT 24
Peak memory 206576 kb
Host smart-af58a9b3-045c-40fb-875d-689de7f09beb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974738081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3974738081
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1863327893
Short name T1054
Test name
Test status
Simulation time 517593094 ps
CPU time 3.51 seconds
Started Aug 05 06:03:23 PM PDT 24
Finished Aug 05 06:03:27 PM PDT 24
Peak memory 206580 kb
Host smart-e4a9d5a6-5ead-4e62-a640-0aca49c1148d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863327893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1863327893
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.592617384
Short name T1004
Test name
Test status
Simulation time 34702316 ps
CPU time 0.85 seconds
Started Aug 05 06:03:21 PM PDT 24
Finished Aug 05 06:03:22 PM PDT 24
Peak memory 206400 kb
Host smart-acae8628-f81d-4e4c-8a2e-24699a99e850
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592617384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.592617384
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4141232530
Short name T1067
Test name
Test status
Simulation time 35209416 ps
CPU time 1.5 seconds
Started Aug 05 06:03:23 PM PDT 24
Finished Aug 05 06:03:25 PM PDT 24
Peak memory 215188 kb
Host smart-dbc9d419-8e79-4098-93eb-aff7128705da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141232530 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.4141232530
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2705881798
Short name T270
Test name
Test status
Simulation time 17203557 ps
CPU time 0.97 seconds
Started Aug 05 06:03:23 PM PDT 24
Finished Aug 05 06:03:24 PM PDT 24
Peak memory 206588 kb
Host smart-119d3703-e398-4ecf-a427-cadacc837d64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705881798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2705881798
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1512911080
Short name T1109
Test name
Test status
Simulation time 32176584 ps
CPU time 0.82 seconds
Started Aug 05 06:03:21 PM PDT 24
Finished Aug 05 06:03:22 PM PDT 24
Peak memory 206416 kb
Host smart-af0ed18e-e491-4292-a2ab-f66e10c38814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512911080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1512911080
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3341429539
Short name T1049
Test name
Test status
Simulation time 43780905 ps
CPU time 1.15 seconds
Started Aug 05 06:03:25 PM PDT 24
Finished Aug 05 06:03:26 PM PDT 24
Peak memory 206708 kb
Host smart-084d5c00-79db-49c6-991e-8ce9a38d2ad3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341429539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3341429539
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2618717523
Short name T1010
Test name
Test status
Simulation time 386024848 ps
CPU time 3.72 seconds
Started Aug 05 06:03:22 PM PDT 24
Finished Aug 05 06:03:26 PM PDT 24
Peak memory 214996 kb
Host smart-9c836c3c-0da4-4489-917a-1678663af5b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618717523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2618717523
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2329538132
Short name T1117
Test name
Test status
Simulation time 131933579 ps
CPU time 3.21 seconds
Started Aug 05 06:03:22 PM PDT 24
Finished Aug 05 06:03:25 PM PDT 24
Peak memory 214920 kb
Host smart-90531de5-54f4-46cd-a914-464d58949017
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329538132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2329538132
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3503513380
Short name T1080
Test name
Test status
Simulation time 115332724 ps
CPU time 0.86 seconds
Started Aug 05 06:03:45 PM PDT 24
Finished Aug 05 06:03:46 PM PDT 24
Peak memory 206536 kb
Host smart-fc3a1f3f-e1cf-4e8b-828e-273181e56444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503513380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3503513380
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3518015733
Short name T1059
Test name
Test status
Simulation time 29097985 ps
CPU time 0.79 seconds
Started Aug 05 06:03:46 PM PDT 24
Finished Aug 05 06:03:47 PM PDT 24
Peak memory 206412 kb
Host smart-6adc41b4-3271-4a48-b286-c524dd88243b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518015733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3518015733
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3608415416
Short name T1089
Test name
Test status
Simulation time 26586827 ps
CPU time 0.93 seconds
Started Aug 05 06:03:43 PM PDT 24
Finished Aug 05 06:03:45 PM PDT 24
Peak memory 206584 kb
Host smart-4b189d8a-7ca1-4891-984a-d2a8af8ff8d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608415416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3608415416
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3548756489
Short name T1070
Test name
Test status
Simulation time 14587364 ps
CPU time 0.89 seconds
Started Aug 05 06:03:46 PM PDT 24
Finished Aug 05 06:03:47 PM PDT 24
Peak memory 206600 kb
Host smart-9aa6ba27-41d1-46d3-a7e2-cc4dbc4df71c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548756489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3548756489
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2547494653
Short name T1056
Test name
Test status
Simulation time 27425368 ps
CPU time 0.78 seconds
Started Aug 05 06:03:50 PM PDT 24
Finished Aug 05 06:03:51 PM PDT 24
Peak memory 206408 kb
Host smart-dddc5921-0f14-47b7-b11a-2c8cbac9ad27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547494653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2547494653
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2019965288
Short name T1122
Test name
Test status
Simulation time 13410581 ps
CPU time 0.89 seconds
Started Aug 05 06:03:50 PM PDT 24
Finished Aug 05 06:03:51 PM PDT 24
Peak memory 206572 kb
Host smart-5a29138b-356b-4a2e-938f-e6163b1c3445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019965288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2019965288
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1855799159
Short name T1072
Test name
Test status
Simulation time 13490965 ps
CPU time 0.88 seconds
Started Aug 05 06:03:49 PM PDT 24
Finished Aug 05 06:03:51 PM PDT 24
Peak memory 206616 kb
Host smart-b3f5a1ed-166b-4a2e-9f5f-183846fabe73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855799159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1855799159
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.985616838
Short name T1057
Test name
Test status
Simulation time 16627904 ps
CPU time 0.79 seconds
Started Aug 05 06:03:49 PM PDT 24
Finished Aug 05 06:03:49 PM PDT 24
Peak memory 206412 kb
Host smart-774ee621-d1df-4099-bc3d-6c0bf121b0ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985616838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.985616838
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.4274957055
Short name T1031
Test name
Test status
Simulation time 35312189 ps
CPU time 0.83 seconds
Started Aug 05 06:03:52 PM PDT 24
Finished Aug 05 06:03:53 PM PDT 24
Peak memory 206600 kb
Host smart-d780a2a2-506a-4090-a3c9-7f659d9bb4e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274957055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.4274957055
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1614303768
Short name T1101
Test name
Test status
Simulation time 13950216 ps
CPU time 0.92 seconds
Started Aug 05 06:03:50 PM PDT 24
Finished Aug 05 06:03:51 PM PDT 24
Peak memory 206656 kb
Host smart-7ffe93ff-1a2c-4556-9e0a-4ca2def0c3a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614303768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1614303768
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3808447584
Short name T267
Test name
Test status
Simulation time 37388847 ps
CPU time 1.48 seconds
Started Aug 05 06:03:25 PM PDT 24
Finished Aug 05 06:03:26 PM PDT 24
Peak memory 206580 kb
Host smart-78e10618-53dc-495b-8f23-6bba8f25cac9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808447584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3808447584
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3390424410
Short name T1086
Test name
Test status
Simulation time 265946718 ps
CPU time 3.67 seconds
Started Aug 05 06:03:25 PM PDT 24
Finished Aug 05 06:03:28 PM PDT 24
Peak memory 206588 kb
Host smart-bf9b696c-aabe-466f-b935-27597c5216de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390424410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3390424410
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.975313689
Short name T265
Test name
Test status
Simulation time 18696193 ps
CPU time 1.03 seconds
Started Aug 05 06:03:26 PM PDT 24
Finished Aug 05 06:03:27 PM PDT 24
Peak memory 206576 kb
Host smart-aa7fa989-b0c1-47b4-ac4f-cc2983b54f03
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975313689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.975313689
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1145598715
Short name T1021
Test name
Test status
Simulation time 43826246 ps
CPU time 1.4 seconds
Started Aug 05 06:03:24 PM PDT 24
Finished Aug 05 06:03:26 PM PDT 24
Peak memory 215060 kb
Host smart-3d09b9ce-c5d5-4c04-a06f-938ad8c63b40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145598715 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1145598715
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3534842778
Short name T1052
Test name
Test status
Simulation time 12693673 ps
CPU time 0.87 seconds
Started Aug 05 06:03:32 PM PDT 24
Finished Aug 05 06:03:33 PM PDT 24
Peak memory 206632 kb
Host smart-d374ad38-83e9-4779-9b26-50deafcfbef4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534842778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3534842778
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2771618729
Short name T1111
Test name
Test status
Simulation time 16387068 ps
CPU time 0.94 seconds
Started Aug 05 06:03:27 PM PDT 24
Finished Aug 05 06:03:28 PM PDT 24
Peak memory 206608 kb
Host smart-0a52c651-1139-4331-b06e-ac9634f5f078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771618729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2771618729
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3184939366
Short name T1075
Test name
Test status
Simulation time 34245974 ps
CPU time 1.08 seconds
Started Aug 05 06:03:25 PM PDT 24
Finished Aug 05 06:03:26 PM PDT 24
Peak memory 206716 kb
Host smart-5cce56f9-d65a-47b1-aaf6-97f71a654915
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184939366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3184939366
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1339200377
Short name T1017
Test name
Test status
Simulation time 94934099 ps
CPU time 3.52 seconds
Started Aug 05 06:03:30 PM PDT 24
Finished Aug 05 06:03:33 PM PDT 24
Peak memory 214988 kb
Host smart-f8db4b73-4433-444c-9066-d3df47be0859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339200377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1339200377
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3255929060
Short name T220
Test name
Test status
Simulation time 206309394 ps
CPU time 2.69 seconds
Started Aug 05 06:03:24 PM PDT 24
Finished Aug 05 06:03:27 PM PDT 24
Peak memory 214916 kb
Host smart-ab9f3bf5-64fe-4dd2-a595-cda77915cb65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255929060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3255929060
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.814074972
Short name T1060
Test name
Test status
Simulation time 180169259 ps
CPU time 0.95 seconds
Started Aug 05 06:03:49 PM PDT 24
Finished Aug 05 06:03:50 PM PDT 24
Peak memory 206592 kb
Host smart-38245c42-9654-49d4-b1bc-499d9ba4416a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814074972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.814074972
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2880439715
Short name T1095
Test name
Test status
Simulation time 14335552 ps
CPU time 0.9 seconds
Started Aug 05 06:03:51 PM PDT 24
Finished Aug 05 06:03:52 PM PDT 24
Peak memory 206596 kb
Host smart-7a03e349-fae0-4578-9451-48bac54429ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880439715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2880439715
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3283249761
Short name T1020
Test name
Test status
Simulation time 24127334 ps
CPU time 0.84 seconds
Started Aug 05 06:03:50 PM PDT 24
Finished Aug 05 06:03:52 PM PDT 24
Peak memory 206596 kb
Host smart-39e4bc0f-5ce7-48fa-b20d-e4cf33a7b9a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283249761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3283249761
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1474414191
Short name T994
Test name
Test status
Simulation time 139018583 ps
CPU time 0.83 seconds
Started Aug 05 06:03:48 PM PDT 24
Finished Aug 05 06:03:49 PM PDT 24
Peak memory 206600 kb
Host smart-e073803d-48a8-44d8-9532-66ce53a674d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474414191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1474414191
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.166445157
Short name T1027
Test name
Test status
Simulation time 13545044 ps
CPU time 0.93 seconds
Started Aug 05 06:03:51 PM PDT 24
Finished Aug 05 06:03:52 PM PDT 24
Peak memory 206608 kb
Host smart-6c7c8d6c-f7af-4aad-9639-0aeba2339c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166445157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.166445157
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.849023697
Short name T1015
Test name
Test status
Simulation time 13896519 ps
CPU time 0.96 seconds
Started Aug 05 06:03:48 PM PDT 24
Finished Aug 05 06:03:49 PM PDT 24
Peak memory 206592 kb
Host smart-9a9ed52f-7da6-44a6-9315-735697f40f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849023697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.849023697
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.441682306
Short name T1028
Test name
Test status
Simulation time 11203146 ps
CPU time 0.88 seconds
Started Aug 05 06:03:49 PM PDT 24
Finished Aug 05 06:03:50 PM PDT 24
Peak memory 206592 kb
Host smart-02d00ee0-36fc-4a3a-b4d4-291b75fd8512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441682306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.441682306
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.4259479358
Short name T998
Test name
Test status
Simulation time 14273676 ps
CPU time 0.89 seconds
Started Aug 05 06:03:51 PM PDT 24
Finished Aug 05 06:03:52 PM PDT 24
Peak memory 206568 kb
Host smart-f7422fb2-0a5e-4fb7-9896-d54c29741cf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259479358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.4259479358
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3390214360
Short name T1123
Test name
Test status
Simulation time 11414592 ps
CPU time 0.87 seconds
Started Aug 05 06:03:51 PM PDT 24
Finished Aug 05 06:03:52 PM PDT 24
Peak memory 206580 kb
Host smart-e1069378-e708-449d-a741-1483748f8d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390214360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3390214360
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1654678613
Short name T1029
Test name
Test status
Simulation time 12157668 ps
CPU time 0.85 seconds
Started Aug 05 06:03:52 PM PDT 24
Finished Aug 05 06:03:53 PM PDT 24
Peak memory 206608 kb
Host smart-e614f7c6-2afd-4d25-b20a-d4eaa0bfa7bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654678613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1654678613
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3298187163
Short name T1082
Test name
Test status
Simulation time 38862955 ps
CPU time 1.21 seconds
Started Aug 05 06:03:26 PM PDT 24
Finished Aug 05 06:03:27 PM PDT 24
Peak memory 214984 kb
Host smart-c47551e7-cec2-4abd-8e3f-41b746e0839a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298187163 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3298187163
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.4263784501
Short name T1044
Test name
Test status
Simulation time 11716803 ps
CPU time 0.85 seconds
Started Aug 05 06:03:27 PM PDT 24
Finished Aug 05 06:03:28 PM PDT 24
Peak memory 206588 kb
Host smart-06d400ae-cdbd-4253-8e8c-7e0d23779a4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263784501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.4263784501
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2467415407
Short name T1007
Test name
Test status
Simulation time 23005039 ps
CPU time 0.87 seconds
Started Aug 05 06:03:27 PM PDT 24
Finished Aug 05 06:03:28 PM PDT 24
Peak memory 206580 kb
Host smart-4020c31f-3a77-423c-bfcb-d5491761bce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467415407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2467415407
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4144477567
Short name T275
Test name
Test status
Simulation time 37226689 ps
CPU time 1.07 seconds
Started Aug 05 06:03:25 PM PDT 24
Finished Aug 05 06:03:26 PM PDT 24
Peak memory 206724 kb
Host smart-2d882a55-aeb8-4dd3-a43f-4d81783b832f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144477567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.4144477567
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.433324125
Short name T999
Test name
Test status
Simulation time 43139330 ps
CPU time 2.91 seconds
Started Aug 05 06:03:26 PM PDT 24
Finished Aug 05 06:03:30 PM PDT 24
Peak memory 215068 kb
Host smart-6b64d028-49e0-401d-82af-02cffd99a9ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433324125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.433324125
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.353124186
Short name T1119
Test name
Test status
Simulation time 177492516 ps
CPU time 1.62 seconds
Started Aug 05 06:03:26 PM PDT 24
Finished Aug 05 06:03:28 PM PDT 24
Peak memory 206724 kb
Host smart-7d642eb4-85a4-4051-b7b8-f6cf0f000c8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353124186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.353124186
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1804532467
Short name T1092
Test name
Test status
Simulation time 53061757 ps
CPU time 1.23 seconds
Started Aug 05 06:03:32 PM PDT 24
Finished Aug 05 06:03:33 PM PDT 24
Peak memory 206844 kb
Host smart-9ed27778-fcb9-4a2c-a2a3-6bbd35cb0526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804532467 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1804532467
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1897200072
Short name T264
Test name
Test status
Simulation time 16341783 ps
CPU time 0.95 seconds
Started Aug 05 06:03:25 PM PDT 24
Finished Aug 05 06:03:26 PM PDT 24
Peak memory 206560 kb
Host smart-bb5b3a6c-621e-4350-b5b4-f528123ecee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897200072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1897200072
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3207710029
Short name T1097
Test name
Test status
Simulation time 42840272 ps
CPU time 0.78 seconds
Started Aug 05 06:03:27 PM PDT 24
Finished Aug 05 06:03:28 PM PDT 24
Peak memory 206412 kb
Host smart-525d7c96-0834-432c-82e3-6949e2f2e042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207710029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3207710029
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.740008139
Short name T271
Test name
Test status
Simulation time 19377158 ps
CPU time 1.14 seconds
Started Aug 05 06:03:25 PM PDT 24
Finished Aug 05 06:03:27 PM PDT 24
Peak memory 206816 kb
Host smart-1fbb8513-dd32-41c9-99ac-a66a21ca5b94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740008139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.740008139
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.4110814800
Short name T1106
Test name
Test status
Simulation time 105711324 ps
CPU time 3 seconds
Started Aug 05 06:03:29 PM PDT 24
Finished Aug 05 06:03:32 PM PDT 24
Peak memory 214996 kb
Host smart-5746fac6-885b-4c44-9e3c-f5621ced00cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110814800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.4110814800
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.4191948703
Short name T287
Test name
Test status
Simulation time 138639559 ps
CPU time 2.89 seconds
Started Aug 05 06:03:24 PM PDT 24
Finished Aug 05 06:03:27 PM PDT 24
Peak memory 206624 kb
Host smart-d7381b74-2cf2-43a0-8d41-20035848289e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191948703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.4191948703
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1486501232
Short name T1039
Test name
Test status
Simulation time 37225823 ps
CPU time 1.49 seconds
Started Aug 05 06:03:26 PM PDT 24
Finished Aug 05 06:03:28 PM PDT 24
Peak memory 215000 kb
Host smart-c459128c-7ebf-401c-8043-869ef47a96aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486501232 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1486501232
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3604850484
Short name T1047
Test name
Test status
Simulation time 90734473 ps
CPU time 0.81 seconds
Started Aug 05 06:03:27 PM PDT 24
Finished Aug 05 06:03:28 PM PDT 24
Peak memory 206384 kb
Host smart-bb4e4efa-f65f-4c60-8c0d-2cac7314e419
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604850484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3604850484
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3264103475
Short name T1006
Test name
Test status
Simulation time 28471023 ps
CPU time 0.93 seconds
Started Aug 05 06:03:26 PM PDT 24
Finished Aug 05 06:03:28 PM PDT 24
Peak memory 206588 kb
Host smart-8e9084f2-2d23-42a5-bc32-4aa55b4af87c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264103475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3264103475
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2287853844
Short name T1115
Test name
Test status
Simulation time 13220017 ps
CPU time 0.93 seconds
Started Aug 05 06:03:29 PM PDT 24
Finished Aug 05 06:03:30 PM PDT 24
Peak memory 206720 kb
Host smart-414d06ed-3472-4afa-91b5-4639a15a2c31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287853844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2287853844
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2608536207
Short name T1066
Test name
Test status
Simulation time 34114196 ps
CPU time 1.87 seconds
Started Aug 05 06:03:26 PM PDT 24
Finished Aug 05 06:03:28 PM PDT 24
Peak memory 215040 kb
Host smart-ea7bf97c-fb8c-4afc-ae8b-6435a17c3e91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608536207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2608536207
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2763566855
Short name T286
Test name
Test status
Simulation time 1326210187 ps
CPU time 6.2 seconds
Started Aug 05 06:03:26 PM PDT 24
Finished Aug 05 06:03:32 PM PDT 24
Peak memory 214912 kb
Host smart-5b419912-df0f-4e73-9bcf-7a5121cb9a19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763566855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2763566855
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.322130980
Short name T1110
Test name
Test status
Simulation time 21516863 ps
CPU time 1.34 seconds
Started Aug 05 06:03:28 PM PDT 24
Finished Aug 05 06:03:29 PM PDT 24
Peak memory 214980 kb
Host smart-7cf7e748-4e13-42f1-b767-f78558895f95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322130980 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.322130980
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1265078997
Short name T1036
Test name
Test status
Simulation time 13650218 ps
CPU time 0.89 seconds
Started Aug 05 06:03:31 PM PDT 24
Finished Aug 05 06:03:32 PM PDT 24
Peak memory 206628 kb
Host smart-814c79ab-1510-4981-9a5d-1ec8bade8cf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265078997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1265078997
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.56303910
Short name T273
Test name
Test status
Simulation time 31167064 ps
CPU time 1.16 seconds
Started Aug 05 06:03:25 PM PDT 24
Finished Aug 05 06:03:27 PM PDT 24
Peak memory 206796 kb
Host smart-7e29ca2f-7074-4261-adcf-e9cf7109443e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56303910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outs
tanding.56303910
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3371175238
Short name T1037
Test name
Test status
Simulation time 100310169 ps
CPU time 2.05 seconds
Started Aug 05 06:03:27 PM PDT 24
Finished Aug 05 06:03:29 PM PDT 24
Peak memory 215028 kb
Host smart-0a920615-be68-4a1e-9c73-ad1c428dcccd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371175238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3371175238
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2496426780
Short name T1053
Test name
Test status
Simulation time 934622694 ps
CPU time 2.39 seconds
Started Aug 05 06:03:27 PM PDT 24
Finished Aug 05 06:03:29 PM PDT 24
Peak memory 206728 kb
Host smart-2085f757-b127-43ab-baa4-d256c1d501d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496426780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2496426780
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.378228101
Short name T1062
Test name
Test status
Simulation time 25632757 ps
CPU time 1.29 seconds
Started Aug 05 06:03:31 PM PDT 24
Finished Aug 05 06:03:33 PM PDT 24
Peak memory 216664 kb
Host smart-e3a1674b-e9ff-4658-b3de-1e61280cf745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378228101 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.378228101
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3937254114
Short name T1091
Test name
Test status
Simulation time 13864403 ps
CPU time 0.91 seconds
Started Aug 05 06:03:36 PM PDT 24
Finished Aug 05 06:03:37 PM PDT 24
Peak memory 206584 kb
Host smart-bf408f4a-2943-474d-8a20-f03137b5e94b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937254114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3937254114
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2868552010
Short name T1023
Test name
Test status
Simulation time 25276458 ps
CPU time 0.87 seconds
Started Aug 05 06:03:31 PM PDT 24
Finished Aug 05 06:03:32 PM PDT 24
Peak memory 206680 kb
Host smart-576fb5aa-5271-45f7-ace4-bc276fb76ab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868552010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2868552010
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1279912970
Short name T272
Test name
Test status
Simulation time 179413217 ps
CPU time 1.03 seconds
Started Aug 05 06:03:31 PM PDT 24
Finished Aug 05 06:03:33 PM PDT 24
Peak memory 206796 kb
Host smart-4ae8f93c-3fa9-41f7-af57-efee9e30ae25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279912970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1279912970
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1843480974
Short name T1045
Test name
Test status
Simulation time 44611458 ps
CPU time 3 seconds
Started Aug 05 06:03:31 PM PDT 24
Finished Aug 05 06:03:34 PM PDT 24
Peak memory 214896 kb
Host smart-34fb12cc-9488-415a-934f-249f5e743eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843480974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1843480974
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4277788102
Short name T285
Test name
Test status
Simulation time 256727596 ps
CPU time 2.38 seconds
Started Aug 05 06:03:33 PM PDT 24
Finished Aug 05 06:03:35 PM PDT 24
Peak memory 206784 kb
Host smart-ff14b3d8-f1d6-4c3c-b4bd-c8762e89bda1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277788102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.4277788102
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.4072169386
Short name T558
Test name
Test status
Simulation time 72441423 ps
CPU time 1.08 seconds
Started Aug 05 06:07:36 PM PDT 24
Finished Aug 05 06:07:37 PM PDT 24
Peak memory 218424 kb
Host smart-17fb6748-6b8b-4201-a375-e0ff95d335a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072169386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.4072169386
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2149042015
Short name T713
Test name
Test status
Simulation time 33320106 ps
CPU time 0.95 seconds
Started Aug 05 06:07:26 PM PDT 24
Finished Aug 05 06:07:27 PM PDT 24
Peak memory 206760 kb
Host smart-297cd7fc-93ed-459c-8063-824e28c1377c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149042015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2149042015
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.1084365046
Short name T117
Test name
Test status
Simulation time 26050676 ps
CPU time 0.95 seconds
Started Aug 05 06:07:27 PM PDT 24
Finished Aug 05 06:07:28 PM PDT 24
Peak memory 218588 kb
Host smart-83d3da75-3a07-4410-a171-67b21c8dd76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084365046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1084365046
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1794346682
Short name T797
Test name
Test status
Simulation time 49078823 ps
CPU time 1.4 seconds
Started Aug 05 06:07:27 PM PDT 24
Finished Aug 05 06:07:29 PM PDT 24
Peak memory 217396 kb
Host smart-f0bd4dbc-c215-41bc-8016-334b10fb29f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794346682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1794346682
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.198305291
Short name T594
Test name
Test status
Simulation time 21435325 ps
CPU time 1.17 seconds
Started Aug 05 06:07:26 PM PDT 24
Finished Aug 05 06:07:27 PM PDT 24
Peak memory 224024 kb
Host smart-bfdc178f-fac1-4389-8d4d-aa717a5e85ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198305291 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.198305291
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3359054519
Short name T816
Test name
Test status
Simulation time 32875232 ps
CPU time 0.86 seconds
Started Aug 05 06:07:27 PM PDT 24
Finished Aug 05 06:07:28 PM PDT 24
Peak memory 206880 kb
Host smart-9f97014c-3d71-4865-833f-3c3f187b16b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359054519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3359054519
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.308995521
Short name T383
Test name
Test status
Simulation time 36916018 ps
CPU time 0.92 seconds
Started Aug 05 06:07:28 PM PDT 24
Finished Aug 05 06:07:29 PM PDT 24
Peak memory 215436 kb
Host smart-d69037c6-228f-4951-8534-3ba26e016c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308995521 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.308995521
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.489192214
Short name T249
Test name
Test status
Simulation time 538575466 ps
CPU time 5.39 seconds
Started Aug 05 06:07:28 PM PDT 24
Finished Aug 05 06:07:33 PM PDT 24
Peak memory 217428 kb
Host smart-f71b7a4d-52f9-445c-8194-2567c8a8909f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489192214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.489192214
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.563882335
Short name T537
Test name
Test status
Simulation time 27149781801 ps
CPU time 620.98 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:18:03 PM PDT 24
Peak memory 217176 kb
Host smart-4d6ae132-b7a3-4105-be7a-6d4632a301a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563882335 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.563882335
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1352866382
Short name T800
Test name
Test status
Simulation time 44776809 ps
CPU time 1.13 seconds
Started Aug 05 06:07:27 PM PDT 24
Finished Aug 05 06:07:28 PM PDT 24
Peak memory 219656 kb
Host smart-679dcfa2-c2c9-421c-913c-fb7a50978453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352866382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1352866382
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1014348570
Short name T812
Test name
Test status
Simulation time 33949402 ps
CPU time 0.95 seconds
Started Aug 05 06:07:33 PM PDT 24
Finished Aug 05 06:07:34 PM PDT 24
Peak memory 206988 kb
Host smart-a96796cd-c295-4462-aa0c-b75f58e18184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014348570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1014348570
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_err.3126234135
Short name T840
Test name
Test status
Simulation time 30818160 ps
CPU time 0.97 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 218592 kb
Host smart-76615362-a8f4-4040-99a6-b0edd065fad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126234135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3126234135
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1134304467
Short name T341
Test name
Test status
Simulation time 59202320 ps
CPU time 1.21 seconds
Started Aug 05 06:07:32 PM PDT 24
Finished Aug 05 06:07:34 PM PDT 24
Peak memory 217436 kb
Host smart-d5c87bdb-952a-4c75-bd1a-ac44e852ad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134304467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1134304467
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.932299384
Short name T909
Test name
Test status
Simulation time 34917420 ps
CPU time 0.9 seconds
Started Aug 05 06:07:33 PM PDT 24
Finished Aug 05 06:07:34 PM PDT 24
Peak memory 215516 kb
Host smart-3e3db2dd-284f-4ff7-8b7a-776f22682fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932299384 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.932299384
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1380003111
Short name T82
Test name
Test status
Simulation time 34932949 ps
CPU time 0.89 seconds
Started Aug 05 06:07:26 PM PDT 24
Finished Aug 05 06:07:27 PM PDT 24
Peak memory 207072 kb
Host smart-4222df34-7a72-4db6-88e1-0594f097421f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380003111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1380003111
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.2741220903
Short name T409
Test name
Test status
Simulation time 24897457 ps
CPU time 0.93 seconds
Started Aug 05 06:07:24 PM PDT 24
Finished Aug 05 06:07:25 PM PDT 24
Peak memory 215268 kb
Host smart-08c753ba-dfe7-4342-b3a0-7fb03103a4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741220903 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2741220903
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3590268442
Short name T178
Test name
Test status
Simulation time 973458870 ps
CPU time 4.07 seconds
Started Aug 05 06:07:34 PM PDT 24
Finished Aug 05 06:07:38 PM PDT 24
Peak memory 217316 kb
Host smart-bcc32477-1b8b-49f4-b80b-caf915ca2855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590268442 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3590268442
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2824403316
Short name T762
Test name
Test status
Simulation time 128674246360 ps
CPU time 832.45 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:21:35 PM PDT 24
Peak memory 222024 kb
Host smart-0ebcc545-b9d2-4493-ae40-d1aa750b9a9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824403316 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2824403316
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.1120973096
Short name T906
Test name
Test status
Simulation time 46829684 ps
CPU time 0.93 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 214848 kb
Host smart-f0fea9ca-bc18-495d-87d1-370d581e6bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120973096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1120973096
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3111737705
Short name T898
Test name
Test status
Simulation time 152040788 ps
CPU time 1.23 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 216956 kb
Host smart-b550a102-5a2d-4ca6-a903-dbb259be5b4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111737705 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3111737705
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_genbits.1471195203
Short name T510
Test name
Test status
Simulation time 68121671 ps
CPU time 1.37 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 217300 kb
Host smart-ee3d9884-b0c4-40eb-aa02-5d94006b8e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471195203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1471195203
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1730609627
Short name T945
Test name
Test status
Simulation time 23011067 ps
CPU time 1.11 seconds
Started Aug 05 06:07:40 PM PDT 24
Finished Aug 05 06:07:41 PM PDT 24
Peak memory 215624 kb
Host smart-830f5f50-c31c-455a-b3db-84f24e29a912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730609627 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1730609627
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1916879359
Short name T62
Test name
Test status
Simulation time 22071057 ps
CPU time 0.92 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 215300 kb
Host smart-4c2005bb-1a55-4812-8604-1047e482507b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916879359 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1916879359
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.724430026
Short name T248
Test name
Test status
Simulation time 29601046 ps
CPU time 1.14 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 206568 kb
Host smart-36a1acca-a183-422d-a6d9-f9826f667207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724430026 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.724430026
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3855301655
Short name T229
Test name
Test status
Simulation time 81439492800 ps
CPU time 141.57 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:10:06 PM PDT 24
Peak memory 219204 kb
Host smart-35ace96e-eedd-4506-86c3-12e9fc275b32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855301655 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3855301655
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.2723662313
Short name T661
Test name
Test status
Simulation time 172334061 ps
CPU time 1.16 seconds
Started Aug 05 06:09:11 PM PDT 24
Finished Aug 05 06:09:12 PM PDT 24
Peak memory 218640 kb
Host smart-5f0aa08c-b074-4089-8738-be3ac1a7fae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723662313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2723662313
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.4143533864
Short name T411
Test name
Test status
Simulation time 351219088 ps
CPU time 2 seconds
Started Aug 05 06:09:08 PM PDT 24
Finished Aug 05 06:09:10 PM PDT 24
Peak memory 218720 kb
Host smart-4774cc0a-7214-4996-8610-27313006317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143533864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4143533864
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.2504841407
Short name T296
Test name
Test status
Simulation time 28436731 ps
CPU time 1.29 seconds
Started Aug 05 06:09:09 PM PDT 24
Finished Aug 05 06:09:11 PM PDT 24
Peak memory 220220 kb
Host smart-cd260ce1-f50d-4fe0-8422-2eb008769efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504841407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2504841407
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3982573151
Short name T32
Test name
Test status
Simulation time 206437205 ps
CPU time 0.97 seconds
Started Aug 05 06:09:11 PM PDT 24
Finished Aug 05 06:09:12 PM PDT 24
Peak memory 217432 kb
Host smart-bb07ee14-59d1-4838-8863-142c4406bf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982573151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3982573151
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.155467096
Short name T982
Test name
Test status
Simulation time 108581277 ps
CPU time 1.15 seconds
Started Aug 05 06:09:05 PM PDT 24
Finished Aug 05 06:09:06 PM PDT 24
Peak memory 219072 kb
Host smart-91c1016b-d88b-4d8d-a083-a1b581606cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155467096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.155467096
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.1134912612
Short name T719
Test name
Test status
Simulation time 43671553 ps
CPU time 1.44 seconds
Started Aug 05 06:09:06 PM PDT 24
Finished Aug 05 06:09:07 PM PDT 24
Peak memory 218484 kb
Host smart-6a11c3f1-ad01-4cf3-8b8f-31bf69b47942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134912612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1134912612
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.1550516542
Short name T733
Test name
Test status
Simulation time 23177196 ps
CPU time 1.14 seconds
Started Aug 05 06:09:06 PM PDT 24
Finished Aug 05 06:09:07 PM PDT 24
Peak memory 219596 kb
Host smart-0d77a39c-943f-4bc1-9b10-8faab760a11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550516542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1550516542
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/104.edn_alert.2129079587
Short name T490
Test name
Test status
Simulation time 81661166 ps
CPU time 1.22 seconds
Started Aug 05 06:09:13 PM PDT 24
Finished Aug 05 06:09:14 PM PDT 24
Peak memory 220808 kb
Host smart-1ab4f921-562c-4985-a001-f6be2542db87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129079587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2129079587
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2143565086
Short name T386
Test name
Test status
Simulation time 94207506 ps
CPU time 3.04 seconds
Started Aug 05 06:09:14 PM PDT 24
Finished Aug 05 06:09:17 PM PDT 24
Peak memory 219988 kb
Host smart-811f1dcf-5121-4977-8f05-11c467a02f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143565086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2143565086
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.3180019430
Short name T394
Test name
Test status
Simulation time 25807703 ps
CPU time 1.23 seconds
Started Aug 05 06:09:13 PM PDT 24
Finished Aug 05 06:09:14 PM PDT 24
Peak memory 219772 kb
Host smart-2df17bce-aa2c-4e27-b2f0-e56d3569c6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180019430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.3180019430
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.1482607611
Short name T364
Test name
Test status
Simulation time 56563667 ps
CPU time 1.47 seconds
Started Aug 05 06:09:05 PM PDT 24
Finished Aug 05 06:09:06 PM PDT 24
Peak memory 218612 kb
Host smart-9d5001c7-4b2c-41aa-9b8a-859c35fed4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482607611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1482607611
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2944192897
Short name T385
Test name
Test status
Simulation time 23022585 ps
CPU time 1.18 seconds
Started Aug 05 06:09:05 PM PDT 24
Finished Aug 05 06:09:06 PM PDT 24
Peak memory 220812 kb
Host smart-775f540a-8205-4e2d-a953-12550f191e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944192897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2944192897
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/107.edn_alert.3605426269
Short name T115
Test name
Test status
Simulation time 36595339 ps
CPU time 1.26 seconds
Started Aug 05 06:09:01 PM PDT 24
Finished Aug 05 06:09:02 PM PDT 24
Peak memory 220840 kb
Host smart-41c6d006-cf8f-44df-8f5e-babeab58164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605426269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3605426269
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.761396555
Short name T679
Test name
Test status
Simulation time 78707724 ps
CPU time 0.96 seconds
Started Aug 05 06:08:54 PM PDT 24
Finished Aug 05 06:08:55 PM PDT 24
Peak memory 215508 kb
Host smart-06c218cf-3e3b-4bf5-8a2f-c6a61b911dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761396555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.761396555
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3656957408
Short name T562
Test name
Test status
Simulation time 74146775 ps
CPU time 1.04 seconds
Started Aug 05 06:09:12 PM PDT 24
Finished Aug 05 06:09:13 PM PDT 24
Peak memory 218836 kb
Host smart-34d649f4-4d0d-4f15-aa9d-2ff1fd84f3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656957408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3656957408
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.955905492
Short name T573
Test name
Test status
Simulation time 32424402 ps
CPU time 1.26 seconds
Started Aug 05 06:09:16 PM PDT 24
Finished Aug 05 06:09:18 PM PDT 24
Peak memory 218312 kb
Host smart-19ec2596-05f2-461b-87a4-eb8ec058a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955905492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.955905492
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.291901142
Short name T692
Test name
Test status
Simulation time 27903760 ps
CPU time 1.22 seconds
Started Aug 05 06:09:18 PM PDT 24
Finished Aug 05 06:09:19 PM PDT 24
Peak memory 220644 kb
Host smart-c876a262-f804-44b8-adf9-30c314e84ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291901142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.291901142
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3947526147
Short name T957
Test name
Test status
Simulation time 107361340 ps
CPU time 1.38 seconds
Started Aug 05 06:09:09 PM PDT 24
Finished Aug 05 06:09:10 PM PDT 24
Peak memory 220284 kb
Host smart-f14fcbec-9474-4791-b6d5-4afa831a85b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947526147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3947526147
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.4292926051
Short name T808
Test name
Test status
Simulation time 33454576 ps
CPU time 0.97 seconds
Started Aug 05 06:07:47 PM PDT 24
Finished Aug 05 06:07:48 PM PDT 24
Peak memory 214984 kb
Host smart-194ef9f8-388a-4332-a4ca-722b101a0f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292926051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4292926051
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2968093619
Short name T755
Test name
Test status
Simulation time 22181904 ps
CPU time 0.86 seconds
Started Aug 05 06:07:51 PM PDT 24
Finished Aug 05 06:07:52 PM PDT 24
Peak memory 215916 kb
Host smart-91d62fef-d816-4333-b5a3-7545040a7b6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968093619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2968093619
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.1774508609
Short name T671
Test name
Test status
Simulation time 29410842 ps
CPU time 1.32 seconds
Started Aug 05 06:07:46 PM PDT 24
Finished Aug 05 06:07:47 PM PDT 24
Peak memory 225668 kb
Host smart-0f474504-00c7-44ac-bab7-dc246051b9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774508609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1774508609
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.290345052
Short name T620
Test name
Test status
Simulation time 21481629 ps
CPU time 1.12 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:07:50 PM PDT 24
Peak memory 215520 kb
Host smart-2c20d511-a110-4e14-b3eb-0a72c299bacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290345052 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.290345052
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1699324237
Short name T463
Test name
Test status
Simulation time 153073075 ps
CPU time 0.92 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 215292 kb
Host smart-5487fb60-d1b1-4d14-95e1-c110ce8d3540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699324237 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1699324237
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3563242918
Short name T701
Test name
Test status
Simulation time 109115856 ps
CPU time 2.8 seconds
Started Aug 05 06:07:40 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 217160 kb
Host smart-55205951-0a09-4f95-8092-f885904bd26e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563242918 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3563242918
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.898470242
Short name T239
Test name
Test status
Simulation time 248678414109 ps
CPU time 1448.82 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:31:54 PM PDT 24
Peak memory 223372 kb
Host smart-5c302644-f906-47d0-96f9-96fb04089539
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898470242 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.898470242
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.3720554506
Short name T720
Test name
Test status
Simulation time 30516730 ps
CPU time 1.26 seconds
Started Aug 05 06:09:11 PM PDT 24
Finished Aug 05 06:09:13 PM PDT 24
Peak memory 215668 kb
Host smart-4a9c14c4-c14c-4d09-9f04-6af39f1a170f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720554506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3720554506
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.3543807053
Short name T404
Test name
Test status
Simulation time 37085961 ps
CPU time 1.37 seconds
Started Aug 05 06:09:08 PM PDT 24
Finished Aug 05 06:09:09 PM PDT 24
Peak memory 217300 kb
Host smart-c2f83442-bb77-41a3-addc-454b32fb8284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543807053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3543807053
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.913609848
Short name T623
Test name
Test status
Simulation time 79756772 ps
CPU time 1.25 seconds
Started Aug 05 06:09:06 PM PDT 24
Finished Aug 05 06:09:07 PM PDT 24
Peak memory 219492 kb
Host smart-bf56d274-cc54-4874-b915-f974f7e906b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913609848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.913609848
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1746404787
Short name T970
Test name
Test status
Simulation time 57645480 ps
CPU time 1.56 seconds
Started Aug 05 06:09:08 PM PDT 24
Finished Aug 05 06:09:10 PM PDT 24
Peak memory 218672 kb
Host smart-340087eb-bb02-4b27-a8b2-d2d06d9b2d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746404787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1746404787
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.1060898130
Short name T847
Test name
Test status
Simulation time 27950149 ps
CPU time 1.2 seconds
Started Aug 05 06:09:04 PM PDT 24
Finished Aug 05 06:09:06 PM PDT 24
Peak memory 219736 kb
Host smart-f7861a1c-4dae-4da5-aecc-b9e70b99e788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060898130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.1060898130
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.163945656
Short name T828
Test name
Test status
Simulation time 265625280 ps
CPU time 1.08 seconds
Started Aug 05 06:09:18 PM PDT 24
Finished Aug 05 06:09:19 PM PDT 24
Peak memory 217408 kb
Host smart-1b10330e-91c2-48f9-a74d-885e3fbc9286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163945656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.163945656
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.603882712
Short name T778
Test name
Test status
Simulation time 102766168 ps
CPU time 1.28 seconds
Started Aug 05 06:09:11 PM PDT 24
Finished Aug 05 06:09:12 PM PDT 24
Peak memory 215660 kb
Host smart-7f46be57-9a5b-43e1-9dd1-958d5115795c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603882712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.603882712
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.1511143621
Short name T988
Test name
Test status
Simulation time 21213586 ps
CPU time 1.07 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:23 PM PDT 24
Peak memory 217216 kb
Host smart-9ed5007b-3202-4154-97e3-3f0f273ab237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511143621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1511143621
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3985370385
Short name T508
Test name
Test status
Simulation time 25616549 ps
CPU time 1.17 seconds
Started Aug 05 06:09:12 PM PDT 24
Finished Aug 05 06:09:13 PM PDT 24
Peak memory 218632 kb
Host smart-3253ac90-c738-44bd-b648-d8e7d491ffcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985370385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3985370385
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.3714889636
Short name T855
Test name
Test status
Simulation time 123627645 ps
CPU time 1.22 seconds
Started Aug 05 06:09:08 PM PDT 24
Finished Aug 05 06:09:10 PM PDT 24
Peak memory 218564 kb
Host smart-57cdb835-80c9-4309-973f-1d62fba89a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714889636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3714889636
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.2078330907
Short name T944
Test name
Test status
Simulation time 274124576 ps
CPU time 1.19 seconds
Started Aug 05 06:09:21 PM PDT 24
Finished Aug 05 06:09:22 PM PDT 24
Peak memory 217324 kb
Host smart-4fcfd585-a0e0-41ba-a6f9-43d161259922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078330907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2078330907
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.895783338
Short name T926
Test name
Test status
Simulation time 28264546 ps
CPU time 1.18 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:32 PM PDT 24
Peak memory 215676 kb
Host smart-1ce52143-cadc-4739-82b3-7447c8b1cbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895783338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.895783338
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.1117202047
Short name T934
Test name
Test status
Simulation time 71741012 ps
CPU time 1.09 seconds
Started Aug 05 06:09:06 PM PDT 24
Finished Aug 05 06:09:07 PM PDT 24
Peak memory 217324 kb
Host smart-9a7934c1-31b0-4649-b083-49c274d5ff8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117202047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1117202047
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1593721462
Short name T916
Test name
Test status
Simulation time 48918950 ps
CPU time 1.29 seconds
Started Aug 05 06:09:14 PM PDT 24
Finished Aug 05 06:09:16 PM PDT 24
Peak memory 219892 kb
Host smart-67428f0b-ae9a-4d0e-b291-056433691fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593721462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1593721462
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.4079314928
Short name T428
Test name
Test status
Simulation time 58583833 ps
CPU time 1.18 seconds
Started Aug 05 06:09:13 PM PDT 24
Finished Aug 05 06:09:14 PM PDT 24
Peak memory 217228 kb
Host smart-b0cbb293-3331-47fe-a35c-510b060a06b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079314928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4079314928
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3119000686
Short name T541
Test name
Test status
Simulation time 40442028 ps
CPU time 1.17 seconds
Started Aug 05 06:09:28 PM PDT 24
Finished Aug 05 06:09:30 PM PDT 24
Peak memory 218372 kb
Host smart-ff74464c-bc64-48b4-9e79-6488c57a9322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119000686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3119000686
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.559031166
Short name T457
Test name
Test status
Simulation time 301208893 ps
CPU time 3.2 seconds
Started Aug 05 06:09:13 PM PDT 24
Finished Aug 05 06:09:16 PM PDT 24
Peak memory 218632 kb
Host smart-8a200704-f195-493b-bf87-eefecd1ce633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559031166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.559031166
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2288215080
Short name T302
Test name
Test status
Simulation time 21300592 ps
CPU time 1.14 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 219692 kb
Host smart-33b78072-8859-4dcc-a7b6-dbf79c2af9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288215080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2288215080
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3421016491
Short name T556
Test name
Test status
Simulation time 15805669 ps
CPU time 0.95 seconds
Started Aug 05 06:07:38 PM PDT 24
Finished Aug 05 06:07:39 PM PDT 24
Peak memory 206704 kb
Host smart-7d2211c2-f7ef-4f49-ac95-e02edcd4952f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421016491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3421016491
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3587725499
Short name T735
Test name
Test status
Simulation time 18078546 ps
CPU time 0.88 seconds
Started Aug 05 06:07:40 PM PDT 24
Finished Aug 05 06:07:41 PM PDT 24
Peak memory 215992 kb
Host smart-a94cc25f-14d8-4d18-a717-ad357f1f71a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587725499 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3587725499
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.822665759
Short name T688
Test name
Test status
Simulation time 21112840 ps
CPU time 1.01 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 218824 kb
Host smart-c1c1702e-4190-4fa2-9111-b473d110646e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822665759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.822665759
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1296047470
Short name T446
Test name
Test status
Simulation time 36345811 ps
CPU time 1.32 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 218516 kb
Host smart-3e737e48-9d37-4ed3-805a-ee53dd9fde38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296047470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1296047470
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.442522196
Short name T519
Test name
Test status
Simulation time 47775194 ps
CPU time 0.92 seconds
Started Aug 05 06:07:53 PM PDT 24
Finished Aug 05 06:07:54 PM PDT 24
Peak memory 215296 kb
Host smart-2151c79a-c60f-437b-b6de-0bca703a0cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442522196 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.442522196
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2023700963
Short name T952
Test name
Test status
Simulation time 278311657 ps
CPU time 3.25 seconds
Started Aug 05 06:07:41 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 215528 kb
Host smart-89b8046b-231b-45a0-b36c-cb88940683ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023700963 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2023700963
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.339728283
Short name T223
Test name
Test status
Simulation time 25423708389 ps
CPU time 537.19 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:16:45 PM PDT 24
Peak memory 218712 kb
Host smart-8d02cfb8-5165-4f42-84c5-ea3e4084390c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339728283 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.339728283
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.464560507
Short name T780
Test name
Test status
Simulation time 27575416 ps
CPU time 1.29 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:24 PM PDT 24
Peak memory 219832 kb
Host smart-f69ec131-e09b-46f3-8043-7ab17a358031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464560507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.464560507
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.1372934283
Short name T506
Test name
Test status
Simulation time 43168340 ps
CPU time 1.12 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:30 PM PDT 24
Peak memory 217228 kb
Host smart-443bf884-3975-4281-b9fd-052bc5c6d6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372934283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1372934283
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.2787789353
Short name T246
Test name
Test status
Simulation time 65598778 ps
CPU time 1.2 seconds
Started Aug 05 06:09:18 PM PDT 24
Finished Aug 05 06:09:19 PM PDT 24
Peak memory 218504 kb
Host smart-b240091a-6b58-48a4-bd5c-317cd9d58bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787789353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.2787789353
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1085716097
Short name T877
Test name
Test status
Simulation time 163061717 ps
CPU time 1.13 seconds
Started Aug 05 06:09:10 PM PDT 24
Finished Aug 05 06:09:11 PM PDT 24
Peak memory 217216 kb
Host smart-44d4441a-d1d0-4c62-91ed-34d8166ec3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085716097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1085716097
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.2056959760
Short name T78
Test name
Test status
Simulation time 35208500 ps
CPU time 1.12 seconds
Started Aug 05 06:09:10 PM PDT 24
Finished Aug 05 06:09:12 PM PDT 24
Peak memory 219696 kb
Host smart-05758de1-4d55-4766-be67-47954044a3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056959760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2056959760
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.1043513914
Short name T734
Test name
Test status
Simulation time 77322010 ps
CPU time 1.23 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 218896 kb
Host smart-ac54f2e6-0967-4c6b-9b96-c0daa1a92804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043513914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1043513914
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.3344233474
Short name T964
Test name
Test status
Simulation time 49791447 ps
CPU time 1.3 seconds
Started Aug 05 06:09:24 PM PDT 24
Finished Aug 05 06:09:25 PM PDT 24
Peak memory 218744 kb
Host smart-646cedaf-4e27-4dd1-8318-1ab3718fc879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344233474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.3344233474
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.3729947784
Short name T841
Test name
Test status
Simulation time 55218167 ps
CPU time 1.96 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:24 PM PDT 24
Peak memory 218484 kb
Host smart-3b935753-e0b7-42d0-a4b6-05d4e51d57f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729947784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3729947784
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.174392587
Short name T608
Test name
Test status
Simulation time 43123017 ps
CPU time 1.12 seconds
Started Aug 05 06:09:13 PM PDT 24
Finished Aug 05 06:09:15 PM PDT 24
Peak memory 219880 kb
Host smart-914139d9-8ad9-4bfc-9238-758a20209dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174392587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.174392587
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.2604966567
Short name T645
Test name
Test status
Simulation time 62626919 ps
CPU time 1.09 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:36 PM PDT 24
Peak memory 218804 kb
Host smart-4eb3f7ee-05d0-4922-aecb-95a5b59de372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604966567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2604966567
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.2699825297
Short name T306
Test name
Test status
Simulation time 38989154 ps
CPU time 1.41 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 218364 kb
Host smart-0f07c3d7-93ff-42e4-b285-de63d67d7616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699825297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2699825297
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.4046631270
Short name T520
Test name
Test status
Simulation time 30182882 ps
CPU time 1.31 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:23 PM PDT 24
Peak memory 218700 kb
Host smart-bd868747-5dec-478f-8e53-9cefa9bacfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046631270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.4046631270
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1843528643
Short name T814
Test name
Test status
Simulation time 72575473 ps
CPU time 1.27 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:23 PM PDT 24
Peak memory 218928 kb
Host smart-49bd8434-851a-4083-9ca5-7cebb7f557b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843528643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1843528643
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3188961077
Short name T663
Test name
Test status
Simulation time 24395127 ps
CPU time 1.18 seconds
Started Aug 05 06:09:16 PM PDT 24
Finished Aug 05 06:09:18 PM PDT 24
Peak memory 215668 kb
Host smart-10c8604b-7071-4293-ba21-c5088040bf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188961077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3188961077
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/129.edn_alert.1220741673
Short name T640
Test name
Test status
Simulation time 39510930 ps
CPU time 1.14 seconds
Started Aug 05 06:09:09 PM PDT 24
Finished Aug 05 06:09:10 PM PDT 24
Peak memory 218668 kb
Host smart-fa84259a-2cc1-42a1-8650-a7fca229215e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220741673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1220741673
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.3543073750
Short name T834
Test name
Test status
Simulation time 91980734 ps
CPU time 1.23 seconds
Started Aug 05 06:09:13 PM PDT 24
Finished Aug 05 06:09:15 PM PDT 24
Peak memory 218996 kb
Host smart-864d3cdc-0429-4940-a0aa-f1455244bd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543073750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3543073750
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3334420288
Short name T641
Test name
Test status
Simulation time 22806387 ps
CPU time 1.14 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:07:49 PM PDT 24
Peak memory 219556 kb
Host smart-385bcf4c-0eb8-4c27-959c-7e83240c2b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334420288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3334420288
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1430390577
Short name T748
Test name
Test status
Simulation time 20669707 ps
CPU time 0.87 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 206764 kb
Host smart-75aef15d-4c68-4990-abd4-b0c3a45d332e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430390577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1430390577
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1364949623
Short name T932
Test name
Test status
Simulation time 32619458 ps
CPU time 1.21 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 216912 kb
Host smart-64fc2dd0-dff4-4093-9afb-9e80a5116dbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364949623 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1364949623
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2307440536
Short name T30
Test name
Test status
Simulation time 33566436 ps
CPU time 0.9 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 218312 kb
Host smart-4fe8b87b-230e-4dfc-9335-940473a4d732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307440536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2307440536
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3414176269
Short name T311
Test name
Test status
Simulation time 49796146 ps
CPU time 1.61 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 218436 kb
Host smart-5fa6ea45-f46d-47fc-b639-8a6a4be7f505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414176269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3414176269
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.2619518489
Short name T371
Test name
Test status
Simulation time 173622295 ps
CPU time 0.96 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 215316 kb
Host smart-d2fc46f9-db81-4519-81e8-9e3c544d0a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619518489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2619518489
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2648586006
Short name T181
Test name
Test status
Simulation time 110624887 ps
CPU time 1.26 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 215296 kb
Host smart-08d0cd31-9574-40d0-bb3b-ba667655c732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648586006 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2648586006
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_alert.3145980999
Short name T849
Test name
Test status
Simulation time 54184886 ps
CPU time 1.12 seconds
Started Aug 05 06:09:03 PM PDT 24
Finished Aug 05 06:09:04 PM PDT 24
Peak memory 218760 kb
Host smart-2d598b8a-1ee0-45d2-8284-adc0ed91a81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145980999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3145980999
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.983208395
Short name T680
Test name
Test status
Simulation time 51140965 ps
CPU time 1.18 seconds
Started Aug 05 06:09:12 PM PDT 24
Finished Aug 05 06:09:13 PM PDT 24
Peak memory 217460 kb
Host smart-ee7c72c0-b085-4fe0-96c7-6813c44b96cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983208395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.983208395
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3253579528
Short name T739
Test name
Test status
Simulation time 65436550 ps
CPU time 1.12 seconds
Started Aug 05 06:09:25 PM PDT 24
Finished Aug 05 06:09:26 PM PDT 24
Peak memory 218708 kb
Host smart-72f1d4e1-3e1a-4abb-b10c-9158583082a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253579528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3253579528
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1459855445
Short name T915
Test name
Test status
Simulation time 41822829 ps
CPU time 1.56 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:24 PM PDT 24
Peak memory 218336 kb
Host smart-04475614-c139-44ce-852d-ca8c90e1ed1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459855445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1459855445
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.365024891
Short name T774
Test name
Test status
Simulation time 30786120 ps
CPU time 1.15 seconds
Started Aug 05 06:09:13 PM PDT 24
Finished Aug 05 06:09:15 PM PDT 24
Peak memory 220072 kb
Host smart-caf8c6a6-f291-4b5a-a1bb-252f3557f760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365024891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.365024891
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.4147784494
Short name T928
Test name
Test status
Simulation time 90652377 ps
CPU time 1.47 seconds
Started Aug 05 06:09:19 PM PDT 24
Finished Aug 05 06:09:20 PM PDT 24
Peak memory 219240 kb
Host smart-377e01e0-0d6c-4f4e-80cf-0a7d5a2abd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147784494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.4147784494
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1881226265
Short name T255
Test name
Test status
Simulation time 28691363 ps
CPU time 1.3 seconds
Started Aug 05 06:09:24 PM PDT 24
Finished Aug 05 06:09:25 PM PDT 24
Peak memory 220676 kb
Host smart-4660a9c4-ac29-49b9-a818-ec484837a835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881226265 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1881226265
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.217194995
Short name T647
Test name
Test status
Simulation time 42682729 ps
CPU time 1.63 seconds
Started Aug 05 06:09:13 PM PDT 24
Finished Aug 05 06:09:14 PM PDT 24
Peak memory 217700 kb
Host smart-29596300-3ab5-46f7-bb74-088f6c7452f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217194995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.217194995
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.811847772
Short name T588
Test name
Test status
Simulation time 73500260 ps
CPU time 1.08 seconds
Started Aug 05 06:09:09 PM PDT 24
Finished Aug 05 06:09:10 PM PDT 24
Peak memory 219960 kb
Host smart-35596fac-25b1-4c91-8199-2adfaebe5b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811847772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.811847772
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.2234190633
Short name T823
Test name
Test status
Simulation time 331551357 ps
CPU time 1.76 seconds
Started Aug 05 06:09:09 PM PDT 24
Finished Aug 05 06:09:11 PM PDT 24
Peak memory 219148 kb
Host smart-1da59e60-1192-43f0-9c42-0080bab56a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234190633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2234190633
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1413701984
Short name T791
Test name
Test status
Simulation time 23365085 ps
CPU time 1.13 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:23 PM PDT 24
Peak memory 220708 kb
Host smart-65543a70-4f90-4449-8e51-35a86b0c5e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413701984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1413701984
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2898660807
Short name T326
Test name
Test status
Simulation time 39311829 ps
CPU time 1.7 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:24 PM PDT 24
Peak memory 218920 kb
Host smart-e4520ae0-8fb5-4aa3-8d24-0fbec4c9a339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898660807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2898660807
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.437761373
Short name T120
Test name
Test status
Simulation time 45048284 ps
CPU time 1.17 seconds
Started Aug 05 06:09:19 PM PDT 24
Finished Aug 05 06:09:20 PM PDT 24
Peak memory 218564 kb
Host smart-d0db6c9d-b4fd-4893-909a-787da1bbaf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437761373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.437761373
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2527186423
Short name T852
Test name
Test status
Simulation time 56484242 ps
CPU time 1.37 seconds
Started Aug 05 06:09:15 PM PDT 24
Finished Aug 05 06:09:17 PM PDT 24
Peak memory 218404 kb
Host smart-be322a3e-1d8f-40a4-b3fa-984959276028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527186423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2527186423
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.917215374
Short name T294
Test name
Test status
Simulation time 27032561 ps
CPU time 1.28 seconds
Started Aug 05 06:09:08 PM PDT 24
Finished Aug 05 06:09:09 PM PDT 24
Peak memory 218728 kb
Host smart-6cc06757-bd05-47b1-acde-cafbbaf2419a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917215374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.917215374
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1126282844
Short name T467
Test name
Test status
Simulation time 126891620 ps
CPU time 2.86 seconds
Started Aug 05 06:09:19 PM PDT 24
Finished Aug 05 06:09:22 PM PDT 24
Peak memory 217572 kb
Host smart-1199ec7e-d644-4ae3-a10d-dcbb7deafef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126282844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1126282844
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.949069290
Short name T218
Test name
Test status
Simulation time 65147390 ps
CPU time 1.09 seconds
Started Aug 05 06:09:24 PM PDT 24
Finished Aug 05 06:09:26 PM PDT 24
Peak memory 218916 kb
Host smart-f788f676-9ed1-44eb-b796-a2824b3edf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949069290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.949069290
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.4251130344
Short name T26
Test name
Test status
Simulation time 37426523 ps
CPU time 1.4 seconds
Started Aug 05 06:09:10 PM PDT 24
Finished Aug 05 06:09:12 PM PDT 24
Peak memory 217304 kb
Host smart-5d527a67-c26a-45a3-a1f2-fa4bcfa96eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251130344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.4251130344
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1559187282
Short name T900
Test name
Test status
Simulation time 27784074 ps
CPU time 1.19 seconds
Started Aug 05 06:07:46 PM PDT 24
Finished Aug 05 06:07:47 PM PDT 24
Peak memory 219548 kb
Host smart-0dd147da-cc4c-4cac-bfca-e8ffc11cacec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559187282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1559187282
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3138822551
Short name T407
Test name
Test status
Simulation time 54894859 ps
CPU time 0.86 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 214684 kb
Host smart-b255ee34-c5b7-4916-ab11-395d6b0fcc75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138822551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3138822551
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1421699382
Short name T845
Test name
Test status
Simulation time 29289057 ps
CPU time 1.11 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:07:50 PM PDT 24
Peak memory 217088 kb
Host smart-ea1c93ce-34ec-4595-8491-d755325b56b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421699382 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1421699382
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3632878236
Short name T208
Test name
Test status
Simulation time 22927361 ps
CPU time 1.04 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 223996 kb
Host smart-fb760a13-4413-4d40-97cf-b11aad99d5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632878236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3632878236
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3893383492
Short name T559
Test name
Test status
Simulation time 38830781 ps
CPU time 1.5 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:07:50 PM PDT 24
Peak memory 218696 kb
Host smart-e5e264f8-ad4c-45c3-8a93-691684d86935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893383492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3893383492
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3743514859
Short name T615
Test name
Test status
Simulation time 51918893 ps
CPU time 1.04 seconds
Started Aug 05 06:08:05 PM PDT 24
Finished Aug 05 06:08:07 PM PDT 24
Peak memory 223824 kb
Host smart-1c05da45-5d7f-497a-9da9-682449daae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743514859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3743514859
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3757819209
Short name T940
Test name
Test status
Simulation time 18650518 ps
CPU time 1.03 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 215284 kb
Host smart-fb7b218a-49dc-401d-9e6a-5be5b6f17472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757819209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3757819209
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.46601810
Short name T582
Test name
Test status
Simulation time 280275062 ps
CPU time 5.81 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:49 PM PDT 24
Peak memory 217304 kb
Host smart-6901ff8d-b8d0-43c6-87cc-86d27eda357d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46601810 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.46601810
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2627656102
Short name T693
Test name
Test status
Simulation time 82423765487 ps
CPU time 603.69 seconds
Started Aug 05 06:07:46 PM PDT 24
Finished Aug 05 06:17:50 PM PDT 24
Peak memory 223840 kb
Host smart-d042fc7a-7dfc-4390-ae80-e2c0f03ffa56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627656102 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2627656102
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.343075004
Short name T565
Test name
Test status
Simulation time 29638810 ps
CPU time 1.23 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 218384 kb
Host smart-c2493aec-7907-4e91-9f72-99b550b75eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343075004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.343075004
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2316693219
Short name T635
Test name
Test status
Simulation time 34620814 ps
CPU time 1.35 seconds
Started Aug 05 06:09:23 PM PDT 24
Finished Aug 05 06:09:25 PM PDT 24
Peak memory 218692 kb
Host smart-af055ec4-39cf-48fd-b7da-098fa5e24985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316693219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2316693219
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2200737807
Short name T483
Test name
Test status
Simulation time 31566416 ps
CPU time 1.3 seconds
Started Aug 05 06:09:11 PM PDT 24
Finished Aug 05 06:09:13 PM PDT 24
Peak memory 215664 kb
Host smart-6eac6c56-ff89-49be-8bdf-34599e69c8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200737807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2200737807
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1310230782
Short name T63
Test name
Test status
Simulation time 217158770 ps
CPU time 1.1 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:23 PM PDT 24
Peak memory 215404 kb
Host smart-a7a0021b-3559-4e65-b234-d819965c13c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310230782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1310230782
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3590339530
Short name T609
Test name
Test status
Simulation time 122727874 ps
CPU time 1.22 seconds
Started Aug 05 06:09:14 PM PDT 24
Finished Aug 05 06:09:15 PM PDT 24
Peak memory 218592 kb
Host smart-42e4acb1-9d56-42d1-8b42-23168420bdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590339530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3590339530
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3758432023
Short name T337
Test name
Test status
Simulation time 74714292 ps
CPU time 2.03 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 220144 kb
Host smart-c682ca5a-e9cd-4f12-9a88-8abd917d994c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758432023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3758432023
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1420021952
Short name T254
Test name
Test status
Simulation time 31956609 ps
CPU time 1.16 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:30 PM PDT 24
Peak memory 219696 kb
Host smart-5b74059f-bcd4-48c8-93d1-f7f3a63afb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420021952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1420021952
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.2211087836
Short name T462
Test name
Test status
Simulation time 63248667 ps
CPU time 1.08 seconds
Started Aug 05 06:09:13 PM PDT 24
Finished Aug 05 06:09:14 PM PDT 24
Peak memory 217352 kb
Host smart-d06294f3-a455-4564-bfc1-fe37e8c01f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211087836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2211087836
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.3833941181
Short name T361
Test name
Test status
Simulation time 26103034 ps
CPU time 1.18 seconds
Started Aug 05 06:09:15 PM PDT 24
Finished Aug 05 06:09:16 PM PDT 24
Peak memory 218684 kb
Host smart-922dfc8d-0b68-4eb0-8c47-d0faa52e1cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833941181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.3833941181
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.251943963
Short name T652
Test name
Test status
Simulation time 48089559 ps
CPU time 1.25 seconds
Started Aug 05 06:09:19 PM PDT 24
Finished Aug 05 06:09:20 PM PDT 24
Peak memory 219824 kb
Host smart-85ad1cf8-122a-4884-9b38-c86f3c0f9290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251943963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.251943963
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1495812604
Short name T107
Test name
Test status
Simulation time 74742084 ps
CPU time 1.18 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:28 PM PDT 24
Peak memory 218424 kb
Host smart-8c58c02c-a95d-4e16-9cee-dc96a4235d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495812604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1495812604
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2712770426
Short name T642
Test name
Test status
Simulation time 243174484 ps
CPU time 1.16 seconds
Started Aug 05 06:09:28 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 217524 kb
Host smart-337fbc3e-d0af-4f4b-8a49-2a08ce276b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712770426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2712770426
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.4121029200
Short name T391
Test name
Test status
Simulation time 69521869 ps
CPU time 1.1 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:38 PM PDT 24
Peak memory 219580 kb
Host smart-fb4ca2e8-dc7e-4d18-9640-2b4f6657732b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121029200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.4121029200
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.4000784886
Short name T650
Test name
Test status
Simulation time 137271560 ps
CPU time 1.76 seconds
Started Aug 05 06:09:15 PM PDT 24
Finished Aug 05 06:09:17 PM PDT 24
Peak memory 220260 kb
Host smart-883f44bc-3ef2-4684-bb46-95c55188b2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000784886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.4000784886
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.4097317674
Short name T143
Test name
Test status
Simulation time 24136263 ps
CPU time 1.21 seconds
Started Aug 05 06:09:14 PM PDT 24
Finished Aug 05 06:09:15 PM PDT 24
Peak memory 219724 kb
Host smart-297238de-0160-47ca-8173-bae116f98b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097317674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.4097317674
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2770101921
Short name T77
Test name
Test status
Simulation time 123837898 ps
CPU time 1.14 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 219836 kb
Host smart-6f4bc3ac-5d15-4f02-9aa3-9b0222349ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770101921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2770101921
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.2944122249
Short name T460
Test name
Test status
Simulation time 41817270 ps
CPU time 1.12 seconds
Started Aug 05 06:09:25 PM PDT 24
Finished Aug 05 06:09:26 PM PDT 24
Peak memory 219548 kb
Host smart-e4dcb6a2-c3ff-4b6d-9857-5459976da210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944122249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.2944122249
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2600826046
Short name T768
Test name
Test status
Simulation time 302295686 ps
CPU time 2.96 seconds
Started Aug 05 06:09:10 PM PDT 24
Finished Aug 05 06:09:13 PM PDT 24
Peak memory 219896 kb
Host smart-c7ec0d60-492d-4fa8-a408-7fb879dab884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600826046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2600826046
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.158811632
Short name T568
Test name
Test status
Simulation time 25490866 ps
CPU time 1.21 seconds
Started Aug 05 06:07:41 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 219360 kb
Host smart-2efe14c6-f080-45df-ae4e-e71685d28487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158811632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.158811632
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.4163255674
Short name T610
Test name
Test status
Simulation time 14956814 ps
CPU time 0.9 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 206820 kb
Host smart-2d5c6aa3-66e2-4bf7-8e67-1086fb4d2211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163255674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.4163255674
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1844990426
Short name T351
Test name
Test status
Simulation time 11752254 ps
CPU time 0.88 seconds
Started Aug 05 06:07:50 PM PDT 24
Finished Aug 05 06:07:52 PM PDT 24
Peak memory 216124 kb
Host smart-90aefca0-4824-42ba-b983-04e892fdab51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844990426 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1844990426
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2563830996
Short name T597
Test name
Test status
Simulation time 23913964 ps
CPU time 1.01 seconds
Started Aug 05 06:07:46 PM PDT 24
Finished Aug 05 06:07:47 PM PDT 24
Peak memory 218516 kb
Host smart-144121f3-914f-4a8d-a811-8f92b1ee638e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563830996 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2563830996
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3908837282
Short name T705
Test name
Test status
Simulation time 24595666 ps
CPU time 1.21 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 218788 kb
Host smart-806abf68-1b1d-4236-9e31-c04e58fbf174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908837282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3908837282
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.148083533
Short name T708
Test name
Test status
Simulation time 195363762 ps
CPU time 2.57 seconds
Started Aug 05 06:07:56 PM PDT 24
Finished Aug 05 06:07:59 PM PDT 24
Peak memory 220132 kb
Host smart-15ba027a-6c48-491f-80aa-ca9d7550d130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148083533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.148083533
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3876112395
Short name T570
Test name
Test status
Simulation time 22642533 ps
CPU time 1.04 seconds
Started Aug 05 06:07:47 PM PDT 24
Finished Aug 05 06:07:48 PM PDT 24
Peak memory 215960 kb
Host smart-16574d97-d62f-44b3-98b4-5426031cf104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876112395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3876112395
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3501550291
Short name T176
Test name
Test status
Simulation time 16826247 ps
CPU time 1 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:07:49 PM PDT 24
Peak memory 215300 kb
Host smart-12b684d4-af26-43b5-9c07-7dd129b59400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501550291 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3501550291
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1921341841
Short name T583
Test name
Test status
Simulation time 1007349322 ps
CPU time 5.03 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:49 PM PDT 24
Peak memory 215300 kb
Host smart-9cfac6e4-ea78-4048-bf67-480cf6a31c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921341841 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1921341841
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2557660519
Short name T233
Test name
Test status
Simulation time 37056028779 ps
CPU time 303.9 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:12:53 PM PDT 24
Peak memory 218464 kb
Host smart-3b9d669f-44fd-4879-a762-5fffa752b7ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557660519 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2557660519
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.409349537
Short name T831
Test name
Test status
Simulation time 77292845 ps
CPU time 1.2 seconds
Started Aug 05 06:09:18 PM PDT 24
Finished Aug 05 06:09:19 PM PDT 24
Peak memory 218784 kb
Host smart-e0a23382-0236-4baa-b20d-e958d8773e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409349537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.409349537
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3139120376
Short name T372
Test name
Test status
Simulation time 43664027 ps
CPU time 1.23 seconds
Started Aug 05 06:09:14 PM PDT 24
Finished Aug 05 06:09:15 PM PDT 24
Peak memory 219084 kb
Host smart-9ef09497-4a1b-4c71-a69f-461843cc607e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139120376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3139120376
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.2680491188
Short name T352
Test name
Test status
Simulation time 31701598 ps
CPU time 1.28 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 219640 kb
Host smart-5b914b44-b1ff-41b3-8d5d-42621a4052a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680491188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.2680491188
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/152.edn_alert.3446054211
Short name T253
Test name
Test status
Simulation time 52976351 ps
CPU time 1.33 seconds
Started Aug 05 06:09:23 PM PDT 24
Finished Aug 05 06:09:24 PM PDT 24
Peak memory 220104 kb
Host smart-e7507426-db4f-4af1-ab34-ac3ffc15c05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446054211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3446054211
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.2735200006
Short name T888
Test name
Test status
Simulation time 45846497 ps
CPU time 1.45 seconds
Started Aug 05 06:09:14 PM PDT 24
Finished Aug 05 06:09:15 PM PDT 24
Peak memory 218704 kb
Host smart-618a6940-c55b-40a4-8a4b-f40164b200ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735200006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2735200006
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2656196354
Short name T639
Test name
Test status
Simulation time 38497540 ps
CPU time 1.11 seconds
Started Aug 05 06:09:16 PM PDT 24
Finished Aug 05 06:09:17 PM PDT 24
Peak memory 219496 kb
Host smart-0237d802-2152-41cb-807c-3908c2a974b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656196354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2656196354
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.170975344
Short name T723
Test name
Test status
Simulation time 56752711 ps
CPU time 2.07 seconds
Started Aug 05 06:09:09 PM PDT 24
Finished Aug 05 06:09:11 PM PDT 24
Peak memory 215280 kb
Host smart-1496387d-e037-44be-a440-adeba8d8ce99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170975344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.170975344
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.2096098482
Short name T725
Test name
Test status
Simulation time 120788215 ps
CPU time 1.26 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:30 PM PDT 24
Peak memory 220852 kb
Host smart-f9597838-8ca6-4a4c-9eec-c0eea5bdc026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096098482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.2096098482
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.2954824639
Short name T759
Test name
Test status
Simulation time 38442873 ps
CPU time 1.18 seconds
Started Aug 05 06:09:19 PM PDT 24
Finished Aug 05 06:09:20 PM PDT 24
Peak memory 217296 kb
Host smart-1f11d451-b45e-4bca-8be5-800dbfc66a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954824639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2954824639
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.488073991
Short name T985
Test name
Test status
Simulation time 29138781 ps
CPU time 1.33 seconds
Started Aug 05 06:09:25 PM PDT 24
Finished Aug 05 06:09:26 PM PDT 24
Peak memory 219780 kb
Host smart-2433be3c-1d20-4e72-9a46-5e5c465dbbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488073991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.488073991
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.680033016
Short name T336
Test name
Test status
Simulation time 111888730 ps
CPU time 1.51 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 219160 kb
Host smart-4a9b6ace-1d18-467f-b1b4-b026ac2927fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680033016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.680033016
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3016459329
Short name T442
Test name
Test status
Simulation time 25876893 ps
CPU time 1.23 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 218504 kb
Host smart-bb440a6e-f8ad-4d4f-b80e-6a607003a477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016459329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3016459329
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/157.edn_alert.4172058724
Short name T299
Test name
Test status
Simulation time 23552387 ps
CPU time 1.16 seconds
Started Aug 05 06:09:25 PM PDT 24
Finished Aug 05 06:09:27 PM PDT 24
Peak memory 219724 kb
Host smart-cabe05ba-aa3a-4db4-a3c0-f56d820c7e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172058724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.4172058724
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3373123837
Short name T535
Test name
Test status
Simulation time 45466069 ps
CPU time 1.49 seconds
Started Aug 05 06:09:19 PM PDT 24
Finished Aug 05 06:09:21 PM PDT 24
Peak memory 218856 kb
Host smart-58f5e486-3e84-4c21-912a-73083a03b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373123837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3373123837
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1245115902
Short name T119
Test name
Test status
Simulation time 28488335 ps
CPU time 1.3 seconds
Started Aug 05 06:09:24 PM PDT 24
Finished Aug 05 06:09:26 PM PDT 24
Peak memory 220884 kb
Host smart-0165f61f-f66c-4fe0-9783-a2d6b24b0f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245115902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1245115902
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.3775825085
Short name T937
Test name
Test status
Simulation time 82361678 ps
CPU time 1.12 seconds
Started Aug 05 06:09:24 PM PDT 24
Finished Aug 05 06:09:25 PM PDT 24
Peak memory 217220 kb
Host smart-b8805d32-5e71-4aab-ab90-0f43b629221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775825085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3775825085
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.1409160632
Short name T731
Test name
Test status
Simulation time 25809068 ps
CPU time 1.23 seconds
Started Aug 05 06:09:21 PM PDT 24
Finished Aug 05 06:09:23 PM PDT 24
Peak memory 218564 kb
Host smart-1da4ebd4-038d-4389-86b6-dd070c2db8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409160632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.1409160632
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.2097528632
Short name T892
Test name
Test status
Simulation time 43461044 ps
CPU time 1.48 seconds
Started Aug 05 06:09:10 PM PDT 24
Finished Aug 05 06:09:12 PM PDT 24
Peak memory 218476 kb
Host smart-9524f48d-e505-4bc3-8e38-22f0b479be57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097528632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2097528632
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3420478673
Short name T477
Test name
Test status
Simulation time 27606358 ps
CPU time 1.28 seconds
Started Aug 05 06:07:50 PM PDT 24
Finished Aug 05 06:07:51 PM PDT 24
Peak memory 218744 kb
Host smart-eda821fc-5e20-4223-b5e8-7fee8aa53d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420478673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3420478673
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2003357967
Short name T529
Test name
Test status
Simulation time 13841282 ps
CPU time 0.92 seconds
Started Aug 05 06:08:11 PM PDT 24
Finished Aug 05 06:08:12 PM PDT 24
Peak memory 206720 kb
Host smart-b9d6b221-5311-496d-950b-e20c24f78cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003357967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2003357967
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3106630346
Short name T604
Test name
Test status
Simulation time 13538030 ps
CPU time 0.93 seconds
Started Aug 05 06:08:03 PM PDT 24
Finished Aug 05 06:08:04 PM PDT 24
Peak memory 216116 kb
Host smart-1d88d7cf-c376-44a2-abc0-bd902375bb8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106630346 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3106630346
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.4110291869
Short name T718
Test name
Test status
Simulation time 32455892 ps
CPU time 1.21 seconds
Started Aug 05 06:07:49 PM PDT 24
Finished Aug 05 06:07:50 PM PDT 24
Peak memory 232248 kb
Host smart-6633515a-8e83-428f-8465-ae6007c32742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110291869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.4110291869
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1209531438
Short name T873
Test name
Test status
Simulation time 31951470 ps
CPU time 1.33 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 220260 kb
Host smart-72251bb0-abbe-43ee-a237-94fda666da2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209531438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1209531438
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1098030137
Short name T43
Test name
Test status
Simulation time 37795147 ps
CPU time 0.98 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 223824 kb
Host smart-9eaab053-42d9-4ef5-87c5-c3867fce653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098030137 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1098030137
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2917398430
Short name T427
Test name
Test status
Simulation time 15361007 ps
CPU time 0.93 seconds
Started Aug 05 06:07:41 PM PDT 24
Finished Aug 05 06:07:42 PM PDT 24
Peak memory 215316 kb
Host smart-f3791465-0e28-4924-903d-144d2e6088a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917398430 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2917398430
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.452459032
Short name T815
Test name
Test status
Simulation time 517630223 ps
CPU time 2.05 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 217280 kb
Host smart-5cf0c8c2-48de-4bae-944c-fb517464c1b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452459032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.452459032
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_alert.3771559150
Short name T168
Test name
Test status
Simulation time 97079130 ps
CPU time 1.17 seconds
Started Aug 05 06:09:12 PM PDT 24
Finished Aug 05 06:09:13 PM PDT 24
Peak memory 218536 kb
Host smart-0635e51f-d836-4650-a66d-65d3ae987c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771559150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3771559150
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3074903594
Short name T348
Test name
Test status
Simulation time 32671769 ps
CPU time 1.16 seconds
Started Aug 05 06:09:16 PM PDT 24
Finished Aug 05 06:09:18 PM PDT 24
Peak memory 217292 kb
Host smart-52f6fd33-2f1e-4ec4-a9e9-f8f4717ff333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074903594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3074903594
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3225495804
Short name T931
Test name
Test status
Simulation time 119956678 ps
CPU time 1.21 seconds
Started Aug 05 06:09:17 PM PDT 24
Finished Aug 05 06:09:18 PM PDT 24
Peak memory 219584 kb
Host smart-72c503c7-a5c9-4373-95df-76cc97c7cba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225495804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3225495804
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.4279536882
Short name T751
Test name
Test status
Simulation time 143907143 ps
CPU time 1.99 seconds
Started Aug 05 06:09:17 PM PDT 24
Finished Aug 05 06:09:19 PM PDT 24
Peak memory 218600 kb
Host smart-95e8725b-5cca-41d7-af01-0a282a95e22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279536882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.4279536882
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.2919787220
Short name T757
Test name
Test status
Simulation time 106982253 ps
CPU time 1.29 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 220652 kb
Host smart-8c063fdd-d3ff-49fa-bc61-486dbcd9a7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919787220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.2919787220
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.48282724
Short name T727
Test name
Test status
Simulation time 101402654 ps
CPU time 1.3 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 218772 kb
Host smart-e5c03326-98db-41c1-865c-ee7492a86ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48282724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.48282724
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2736226834
Short name T14
Test name
Test status
Simulation time 29069505 ps
CPU time 1.27 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 219468 kb
Host smart-4305ac47-8d09-4e80-94f6-d609cb2c1ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736226834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2736226834
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1075277396
Short name T958
Test name
Test status
Simulation time 44552616 ps
CPU time 1.24 seconds
Started Aug 05 06:09:28 PM PDT 24
Finished Aug 05 06:09:30 PM PDT 24
Peak memory 218760 kb
Host smart-6befd804-b221-4d2a-90ab-51c0ee0ecf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075277396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1075277396
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3443978037
Short name T245
Test name
Test status
Simulation time 314602621 ps
CPU time 1.41 seconds
Started Aug 05 06:09:21 PM PDT 24
Finished Aug 05 06:09:23 PM PDT 24
Peak memory 220536 kb
Host smart-8cb4e666-46bd-4bf2-a5e9-f911f8a55e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443978037 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3443978037
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1934971971
Short name T728
Test name
Test status
Simulation time 73461505 ps
CPU time 1.57 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 218724 kb
Host smart-5b8b8804-14f6-409a-b27f-82b9ac4bd0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934971971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1934971971
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3559132468
Short name T291
Test name
Test status
Simulation time 74563857 ps
CPU time 1.14 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 219040 kb
Host smart-5e6314bc-51f4-4d18-8f1f-3c050af33685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559132468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3559132468
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.2049840402
Short name T403
Test name
Test status
Simulation time 45151971 ps
CPU time 1.84 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 218800 kb
Host smart-f886d4c4-8f9f-4de1-93b2-3012b25fbfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049840402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2049840402
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1719155707
Short name T10
Test name
Test status
Simulation time 84897666 ps
CPU time 1.08 seconds
Started Aug 05 06:09:33 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 218372 kb
Host smart-f073a895-8f08-4d6b-a0d7-028ee77b23da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719155707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1719155707
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2937674894
Short name T438
Test name
Test status
Simulation time 140952763 ps
CPU time 1.38 seconds
Started Aug 05 06:09:17 PM PDT 24
Finished Aug 05 06:09:18 PM PDT 24
Peak memory 217252 kb
Host smart-718f4882-bde5-43e6-b9e1-1d0162b5cf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937674894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2937674894
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.147407186
Short name T436
Test name
Test status
Simulation time 90778242 ps
CPU time 1.24 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 219768 kb
Host smart-ff8e5d41-7735-4b08-afa9-94049a0ee73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147407186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.147407186
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1853032864
Short name T764
Test name
Test status
Simulation time 38825539 ps
CPU time 1.15 seconds
Started Aug 05 06:09:33 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 220068 kb
Host smart-beead0eb-4c54-4d3f-8950-91520997600f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853032864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1853032864
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.769448262
Short name T746
Test name
Test status
Simulation time 42228594 ps
CPU time 1.17 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:23 PM PDT 24
Peak memory 218912 kb
Host smart-fbe78b67-3d5f-4c8a-bfa0-9d36a1a369c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769448262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.769448262
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.4084256605
Short name T799
Test name
Test status
Simulation time 35041511 ps
CPU time 1.4 seconds
Started Aug 05 06:09:28 PM PDT 24
Finished Aug 05 06:09:30 PM PDT 24
Peak memory 218544 kb
Host smart-6eeb82db-9b68-4d09-a978-f9b2beb33873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084256605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4084256605
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2665700184
Short name T125
Test name
Test status
Simulation time 26597106 ps
CPU time 1.26 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 218724 kb
Host smart-9ec7d9d6-d0cb-4b14-982d-b7f3f0544b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665700184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2665700184
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.4101151292
Short name T770
Test name
Test status
Simulation time 23737573 ps
CPU time 1 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:07:49 PM PDT 24
Peak memory 206732 kb
Host smart-b45ddf8b-9b59-48fb-b791-7115a7bc0332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101151292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.4101151292
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1146888677
Short name T149
Test name
Test status
Simulation time 20937528 ps
CPU time 0.89 seconds
Started Aug 05 06:07:53 PM PDT 24
Finished Aug 05 06:07:54 PM PDT 24
Peak memory 216244 kb
Host smart-700c2c8f-5832-4f10-9a5b-54e948775813
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146888677 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1146888677
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.413509951
Short name T905
Test name
Test status
Simulation time 41858599 ps
CPU time 1.46 seconds
Started Aug 05 06:07:54 PM PDT 24
Finished Aug 05 06:07:56 PM PDT 24
Peak memory 216884 kb
Host smart-a720cda0-bedb-4d2c-851f-feaabe57130c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413509951 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.413509951
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1649352971
Short name T560
Test name
Test status
Simulation time 33156276 ps
CPU time 0.96 seconds
Started Aug 05 06:07:50 PM PDT 24
Finished Aug 05 06:07:51 PM PDT 24
Peak memory 223804 kb
Host smart-e6f31648-c582-4654-927d-573dce1ab3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649352971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1649352971
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.2024422619
Short name T625
Test name
Test status
Simulation time 27485567 ps
CPU time 0.93 seconds
Started Aug 05 06:07:47 PM PDT 24
Finished Aug 05 06:07:48 PM PDT 24
Peak memory 215320 kb
Host smart-f9e6427e-fa42-44d7-8e13-ac937f24f911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024422619 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2024422619
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2582510677
Short name T566
Test name
Test status
Simulation time 69200374 ps
CPU time 0.96 seconds
Started Aug 05 06:07:47 PM PDT 24
Finished Aug 05 06:07:48 PM PDT 24
Peak memory 215284 kb
Host smart-82183c38-27bb-45d8-9687-789139ffde34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582510677 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2582510677
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1883249144
Short name T187
Test name
Test status
Simulation time 487423468 ps
CPU time 5.99 seconds
Started Aug 05 06:07:49 PM PDT 24
Finished Aug 05 06:07:56 PM PDT 24
Peak memory 218564 kb
Host smart-11e38fd3-6063-4f36-a45f-fdae587a88bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883249144 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1883249144
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3127732025
Short name T456
Test name
Test status
Simulation time 156937842276 ps
CPU time 1087.46 seconds
Started Aug 05 06:07:50 PM PDT 24
Finished Aug 05 06:25:58 PM PDT 24
Peak memory 223156 kb
Host smart-edaed653-8575-4baf-94ff-a7460a4af039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127732025 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3127732025
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2550858077
Short name T214
Test name
Test status
Simulation time 254903874 ps
CPU time 1.45 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 218532 kb
Host smart-93942ea6-0a1c-4d00-89ec-74ea4c0e4a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550858077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2550858077
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.2610782961
Short name T307
Test name
Test status
Simulation time 33933045 ps
CPU time 1.06 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 219848 kb
Host smart-88d13d64-0d15-4a32-af50-7a55ba966ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610782961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2610782961
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1581910503
Short name T874
Test name
Test status
Simulation time 74466777 ps
CPU time 1.17 seconds
Started Aug 05 06:09:28 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 220644 kb
Host smart-8bd2b7c6-b5fe-4b21-a8bc-dc045274c622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581910503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1581910503
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.3205727136
Short name T785
Test name
Test status
Simulation time 54499929 ps
CPU time 1.34 seconds
Started Aug 05 06:09:17 PM PDT 24
Finished Aug 05 06:09:18 PM PDT 24
Peak memory 219984 kb
Host smart-ad96aa98-5fac-46c8-95e2-2585f3146da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205727136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3205727136
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.249086551
Short name T256
Test name
Test status
Simulation time 28538521 ps
CPU time 1.28 seconds
Started Aug 05 06:09:16 PM PDT 24
Finished Aug 05 06:09:18 PM PDT 24
Peak memory 220380 kb
Host smart-07aa91ad-2075-4662-a25c-63bd9dda06aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249086551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.249086551
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.2682319400
Short name T971
Test name
Test status
Simulation time 110613308 ps
CPU time 2.97 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:38 PM PDT 24
Peak memory 219812 kb
Host smart-89ce52dd-e9b6-43c4-b23e-1c4d9d3154af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682319400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2682319400
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3395945101
Short name T687
Test name
Test status
Simulation time 42447954 ps
CPU time 1.23 seconds
Started Aug 05 06:09:25 PM PDT 24
Finished Aug 05 06:09:26 PM PDT 24
Peak memory 219656 kb
Host smart-257760f1-d564-479d-9633-14be197d8e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395945101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3395945101
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1781066845
Short name T743
Test name
Test status
Simulation time 46058733 ps
CPU time 1.57 seconds
Started Aug 05 06:09:25 PM PDT 24
Finished Aug 05 06:09:26 PM PDT 24
Peak memory 218492 kb
Host smart-143f8088-9d18-4536-8c0c-5468a7752537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781066845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1781066845
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.476053436
Short name T858
Test name
Test status
Simulation time 29234840 ps
CPU time 1.2 seconds
Started Aug 05 06:09:25 PM PDT 24
Finished Aug 05 06:09:26 PM PDT 24
Peak memory 218652 kb
Host smart-892371c6-6534-4e1c-9832-5f0539fca9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476053436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.476053436
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3739040008
Short name T766
Test name
Test status
Simulation time 28964718 ps
CPU time 1.38 seconds
Started Aug 05 06:09:21 PM PDT 24
Finished Aug 05 06:09:22 PM PDT 24
Peak memory 217700 kb
Host smart-66197601-5f22-4c26-8ce0-0cd5726e2759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739040008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3739040008
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.4220362188
Short name T694
Test name
Test status
Simulation time 45477110 ps
CPU time 1.13 seconds
Started Aug 05 06:09:33 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 218452 kb
Host smart-7b304040-9a51-4890-8ace-7b820387b51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220362188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.4220362188
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.2301602080
Short name T76
Test name
Test status
Simulation time 138401410 ps
CPU time 1.21 seconds
Started Aug 05 06:09:15 PM PDT 24
Finished Aug 05 06:09:16 PM PDT 24
Peak memory 217348 kb
Host smart-d88eb447-8e99-484e-8088-920568a818c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301602080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2301602080
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2671981707
Short name T425
Test name
Test status
Simulation time 74790454 ps
CPU time 1.1 seconds
Started Aug 05 06:09:19 PM PDT 24
Finished Aug 05 06:09:20 PM PDT 24
Peak memory 217228 kb
Host smart-f072dcb8-ddba-432a-b777-abcc700452af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671981707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2671981707
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.65034545
Short name T405
Test name
Test status
Simulation time 86431374 ps
CPU time 1.2 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 219188 kb
Host smart-797906cd-91b7-493c-99bd-183eba787a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65034545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.65034545
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2437113608
Short name T925
Test name
Test status
Simulation time 160040533 ps
CPU time 1.33 seconds
Started Aug 05 06:09:34 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 218644 kb
Host smart-86bcb1f2-f740-46c7-bca2-a9a90b4c12ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437113608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2437113608
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.4106869534
Short name T590
Test name
Test status
Simulation time 84992082 ps
CPU time 1.11 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 219812 kb
Host smart-609b9d8a-3b3c-45d7-8b5d-b03a453d6743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106869534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.4106869534
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.2357699662
Short name T821
Test name
Test status
Simulation time 89613864 ps
CPU time 2.74 seconds
Started Aug 05 06:09:39 PM PDT 24
Finished Aug 05 06:09:42 PM PDT 24
Peak memory 219940 kb
Host smart-d7eb82d8-556c-4db3-aef7-5fdbe4a7c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357699662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2357699662
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.926935614
Short name T829
Test name
Test status
Simulation time 468575422 ps
CPU time 1.61 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 215672 kb
Host smart-2b3a815e-d9e1-45e4-80e0-e410e521456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926935614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.926935614
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.1117622795
Short name T794
Test name
Test status
Simulation time 55821783 ps
CPU time 1.29 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 218796 kb
Host smart-a955c4fd-4108-4fcf-9d74-cd3ac306987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117622795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1117622795
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.4254457876
Short name T458
Test name
Test status
Simulation time 20320447 ps
CPU time 1.05 seconds
Started Aug 05 06:07:49 PM PDT 24
Finished Aug 05 06:07:50 PM PDT 24
Peak memory 214968 kb
Host smart-aa33831d-7fa4-46e2-80b7-ea537c544d16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254457876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.4254457876
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3598217701
Short name T864
Test name
Test status
Simulation time 23097908 ps
CPU time 0.94 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 216220 kb
Host smart-898786c9-946f-4ed1-b7bb-46b9b4ca5813
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598217701 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3598217701
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2008758540
Short name T98
Test name
Test status
Simulation time 193724354 ps
CPU time 1.07 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:07:49 PM PDT 24
Peak memory 217076 kb
Host smart-54f66a30-6593-4564-b2eb-b490bea55e30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008758540 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2008758540
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2218390132
Short name T904
Test name
Test status
Simulation time 22979879 ps
CPU time 1.14 seconds
Started Aug 05 06:08:07 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 218396 kb
Host smart-f223f8d2-5a74-4d7e-b2b2-20ff3a943b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218390132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2218390132
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2632214636
Short name T969
Test name
Test status
Simulation time 38802092 ps
CPU time 1.39 seconds
Started Aug 05 06:07:57 PM PDT 24
Finished Aug 05 06:07:58 PM PDT 24
Peak memory 217188 kb
Host smart-5c1fa12b-242c-4c44-8ee1-0eb584007a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632214636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2632214636
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.839948470
Short name T697
Test name
Test status
Simulation time 39790712 ps
CPU time 0.85 seconds
Started Aug 05 06:07:49 PM PDT 24
Finished Aug 05 06:07:50 PM PDT 24
Peak memory 215604 kb
Host smart-b7135c0f-9d69-4fea-aa93-dbb85da975f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839948470 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.839948470
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3758270376
Short name T517
Test name
Test status
Simulation time 24074672 ps
CPU time 0.95 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 215276 kb
Host smart-7ba3ffd8-cdee-45e4-9b99-9b56f24ed862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758270376 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3758270376
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.717061719
Short name T624
Test name
Test status
Simulation time 766444538 ps
CPU time 3.32 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:07:52 PM PDT 24
Peak memory 215296 kb
Host smart-eeca67c0-1c79-47c9-9aff-639fb6aa59a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717061719 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.717061719
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.340033547
Short name T234
Test name
Test status
Simulation time 38969996540 ps
CPU time 840.79 seconds
Started Aug 05 06:07:51 PM PDT 24
Finished Aug 05 06:21:52 PM PDT 24
Peak memory 217772 kb
Host smart-b36f1048-1675-4a4e-89ed-7604f1ccf207
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340033547 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.340033547
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.701987449
Short name T553
Test name
Test status
Simulation time 28628488 ps
CPU time 1.26 seconds
Started Aug 05 06:09:20 PM PDT 24
Finished Aug 05 06:09:21 PM PDT 24
Peak memory 219780 kb
Host smart-6b134750-4efd-4c03-a6dc-787eae1c77cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701987449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.701987449
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1613588462
Short name T538
Test name
Test status
Simulation time 181324912 ps
CPU time 1.32 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:32 PM PDT 24
Peak memory 217252 kb
Host smart-97a349d2-667f-4b7e-949c-f0c499f094df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613588462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1613588462
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.2779996160
Short name T776
Test name
Test status
Simulation time 30881962 ps
CPU time 1.27 seconds
Started Aug 05 06:09:26 PM PDT 24
Finished Aug 05 06:09:28 PM PDT 24
Peak memory 218664 kb
Host smart-2e44b6eb-1b4a-41db-bf18-b9bd4a9441f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779996160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2779996160
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2450782021
Short name T454
Test name
Test status
Simulation time 75169979 ps
CPU time 1.07 seconds
Started Aug 05 06:09:41 PM PDT 24
Finished Aug 05 06:09:42 PM PDT 24
Peak memory 219804 kb
Host smart-81e27ecc-6b21-44a1-8944-a54a179cd576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450782021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2450782021
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.2094603270
Short name T837
Test name
Test status
Simulation time 61768804 ps
CPU time 1.32 seconds
Started Aug 05 06:09:26 PM PDT 24
Finished Aug 05 06:09:27 PM PDT 24
Peak memory 219916 kb
Host smart-db5de7c3-a1ce-4f47-91b4-45d7556ecda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094603270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2094603270
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1156312420
Short name T587
Test name
Test status
Simulation time 38882027 ps
CPU time 1.08 seconds
Started Aug 05 06:09:17 PM PDT 24
Finished Aug 05 06:09:19 PM PDT 24
Peak memory 218804 kb
Host smart-07413353-327f-4122-8b44-8c3fd3bc0097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156312420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1156312420
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.4008922293
Short name T485
Test name
Test status
Simulation time 124804287 ps
CPU time 1.15 seconds
Started Aug 05 06:09:25 PM PDT 24
Finished Aug 05 06:09:27 PM PDT 24
Peak memory 218552 kb
Host smart-670afc9d-cc73-4f3f-8dad-bc039ceaea31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008922293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.4008922293
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3201001910
Short name T51
Test name
Test status
Simulation time 24703894 ps
CPU time 1.14 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:36 PM PDT 24
Peak memory 218576 kb
Host smart-928b9fda-f51c-4ac7-b4bc-bb887315d805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201001910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3201001910
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.4201138365
Short name T1
Test name
Test status
Simulation time 55266381 ps
CPU time 1.23 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 217272 kb
Host smart-6596361a-d038-440a-9f2c-993370759988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201138365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.4201138365
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2191471088
Short name T833
Test name
Test status
Simulation time 101160923 ps
CPU time 1.17 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 220700 kb
Host smart-d4686730-913d-48dd-8250-35ce3c653774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191471088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2191471088
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2058255772
Short name T848
Test name
Test status
Simulation time 50095175 ps
CPU time 1.15 seconds
Started Aug 05 06:09:34 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 217372 kb
Host smart-58b23722-acdd-4833-b4b6-e941d3a080b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058255772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2058255772
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2745006472
Short name T507
Test name
Test status
Simulation time 100116949 ps
CPU time 1.2 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 219504 kb
Host smart-1cdd1e06-614b-4ed6-accd-38db920dce01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745006472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2745006472
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.4166316399
Short name T660
Test name
Test status
Simulation time 192958196 ps
CPU time 1.34 seconds
Started Aug 05 06:09:19 PM PDT 24
Finished Aug 05 06:09:20 PM PDT 24
Peak memory 215360 kb
Host smart-782b41d5-11f1-4a8d-9d92-130f27b7d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166316399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4166316399
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1817648971
Short name T2
Test name
Test status
Simulation time 56378556 ps
CPU time 1.24 seconds
Started Aug 05 06:09:26 PM PDT 24
Finished Aug 05 06:09:27 PM PDT 24
Peak memory 219396 kb
Host smart-5bd476b2-d52f-4080-bb5c-d8efba7fd076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817648971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1817648971
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.4272836172
Short name T478
Test name
Test status
Simulation time 25836549 ps
CPU time 1.31 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 218492 kb
Host smart-6f190805-a838-4ccc-84d4-7b087b01fc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272836172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4272836172
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.4031908343
Short name T492
Test name
Test status
Simulation time 75070443 ps
CPU time 1.11 seconds
Started Aug 05 06:09:34 PM PDT 24
Finished Aug 05 06:09:36 PM PDT 24
Peak memory 219592 kb
Host smart-4d777812-c5a2-44de-851e-6792bde1ca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031908343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.4031908343
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.148542966
Short name T824
Test name
Test status
Simulation time 50225597 ps
CPU time 1.64 seconds
Started Aug 05 06:09:26 PM PDT 24
Finished Aug 05 06:09:28 PM PDT 24
Peak memory 218448 kb
Host smart-ebbd07b0-0184-46f5-98c1-b30aa81b9e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148542966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.148542966
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3166823053
Short name T673
Test name
Test status
Simulation time 86315061 ps
CPU time 1.15 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 218520 kb
Host smart-9b900c1d-41f7-45e8-9f51-d18052792091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166823053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3166823053
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2886258470
Short name T444
Test name
Test status
Simulation time 256280093 ps
CPU time 3.48 seconds
Started Aug 05 06:09:25 PM PDT 24
Finished Aug 05 06:09:28 PM PDT 24
Peak memory 220056 kb
Host smart-29c4862f-5cd5-4330-838a-662f3c9dd679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886258470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2886258470
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2535152792
Short name T279
Test name
Test status
Simulation time 31167383 ps
CPU time 1.23 seconds
Started Aug 05 06:07:54 PM PDT 24
Finished Aug 05 06:07:55 PM PDT 24
Peak memory 220840 kb
Host smart-449258ee-59a4-40a2-8978-4953cf323562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535152792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2535152792
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.764620071
Short name T421
Test name
Test status
Simulation time 25828774 ps
CPU time 0.92 seconds
Started Aug 05 06:08:07 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 214824 kb
Host smart-1b75be1e-ae7b-47c6-89df-1922437af212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764620071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.764620071
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.358379429
Short name T390
Test name
Test status
Simulation time 11887808 ps
CPU time 0.87 seconds
Started Aug 05 06:07:50 PM PDT 24
Finished Aug 05 06:07:51 PM PDT 24
Peak memory 216016 kb
Host smart-21263008-3f71-49a5-8bf3-5ec8bae79dec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358379429 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.358379429
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.841733647
Short name T809
Test name
Test status
Simulation time 32938836 ps
CPU time 1.23 seconds
Started Aug 05 06:07:58 PM PDT 24
Finished Aug 05 06:08:00 PM PDT 24
Peak memory 216836 kb
Host smart-cf33f3c1-485b-4903-adac-c40f2a14a04b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841733647 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.841733647
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.4127492121
Short name T134
Test name
Test status
Simulation time 44188218 ps
CPU time 1.3 seconds
Started Aug 05 06:08:00 PM PDT 24
Finished Aug 05 06:08:01 PM PDT 24
Peak memory 225868 kb
Host smart-4416d6c2-9021-4226-8cf7-f64b469af66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127492121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.4127492121
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3787745624
Short name T13
Test name
Test status
Simulation time 53181401 ps
CPU time 1.28 seconds
Started Aug 05 06:07:46 PM PDT 24
Finished Aug 05 06:07:47 PM PDT 24
Peak memory 218840 kb
Host smart-f6b6f37c-fb29-4522-ba34-ef95d8f514a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787745624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3787745624
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2726192745
Short name T678
Test name
Test status
Simulation time 37063023 ps
CPU time 0.88 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:07:49 PM PDT 24
Peak memory 215532 kb
Host smart-1575f17e-d8cb-4778-8a6f-447614e3e0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726192745 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2726192745
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2492378589
Short name T182
Test name
Test status
Simulation time 15214140 ps
CPU time 1.03 seconds
Started Aug 05 06:08:05 PM PDT 24
Finished Aug 05 06:08:06 PM PDT 24
Peak memory 215380 kb
Host smart-937fb2f5-c784-489f-905a-00d2e5da0b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492378589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2492378589
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3827932473
Short name T175
Test name
Test status
Simulation time 542683029 ps
CPU time 5.45 seconds
Started Aug 05 06:08:02 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 215276 kb
Host smart-f56cb243-bce9-47a6-a51b-ac8e365de956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827932473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3827932473
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3969772894
Short name T586
Test name
Test status
Simulation time 263422082765 ps
CPU time 1656.18 seconds
Started Aug 05 06:08:07 PM PDT 24
Finished Aug 05 06:35:43 PM PDT 24
Peak memory 227724 kb
Host smart-d9e631f9-c027-467b-9076-29d85c6f2fa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969772894 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3969772894
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3272990656
Short name T455
Test name
Test status
Simulation time 76341118 ps
CPU time 1.12 seconds
Started Aug 05 06:09:33 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 218732 kb
Host smart-fe2b9391-7d50-4550-a740-04e9496294f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272990656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3272990656
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.2359022212
Short name T304
Test name
Test status
Simulation time 85365818 ps
CPU time 2.93 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:25 PM PDT 24
Peak memory 218596 kb
Host smart-96cbf693-8ece-421d-b4c9-f6d0399c927d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359022212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2359022212
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2284717506
Short name T704
Test name
Test status
Simulation time 95696281 ps
CPU time 1.25 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:36 PM PDT 24
Peak memory 218308 kb
Host smart-34ed57fd-2d48-45e6-b91f-28777b791d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284717506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2284717506
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1291646007
Short name T569
Test name
Test status
Simulation time 38368214 ps
CPU time 1.29 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:24 PM PDT 24
Peak memory 217216 kb
Host smart-e9398f33-9abc-452e-bc93-c8ddd4af96d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291646007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1291646007
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.1001434302
Short name T878
Test name
Test status
Simulation time 25778644 ps
CPU time 1.17 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 218636 kb
Host smart-8afaba94-69fb-4a29-b8d9-b3d3059f4ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001434302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1001434302
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.3692736257
Short name T512
Test name
Test status
Simulation time 62338083 ps
CPU time 1.22 seconds
Started Aug 05 06:09:34 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 218392 kb
Host smart-a5df9737-68d1-4f58-9fd4-6be12e95a183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692736257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3692736257
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.1000030899
Short name T167
Test name
Test status
Simulation time 22358924 ps
CPU time 1.16 seconds
Started Aug 05 06:09:19 PM PDT 24
Finished Aug 05 06:09:20 PM PDT 24
Peak memory 219964 kb
Host smart-0da5695a-d2a4-4782-8aaa-48b1b99d6a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000030899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1000030899
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2378218938
Short name T856
Test name
Test status
Simulation time 35876422 ps
CPU time 1.6 seconds
Started Aug 05 06:09:16 PM PDT 24
Finished Aug 05 06:09:18 PM PDT 24
Peak memory 218324 kb
Host smart-aa36d6f5-1efd-411b-adc3-2c34a732bcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378218938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2378218938
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2695058193
Short name T161
Test name
Test status
Simulation time 68168529 ps
CPU time 1.04 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:28 PM PDT 24
Peak memory 218700 kb
Host smart-8ed5ea24-1ce3-46c5-88e3-54e87b59e2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695058193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2695058193
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.2668915821
Short name T513
Test name
Test status
Simulation time 34315592 ps
CPU time 1.29 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:30 PM PDT 24
Peak memory 218628 kb
Host smart-d286130e-f547-4f68-96c9-38e825f0b9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668915821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2668915821
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.315588607
Short name T295
Test name
Test status
Simulation time 31668181 ps
CPU time 1.34 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:28 PM PDT 24
Peak memory 220160 kb
Host smart-73d4d963-1f74-4b5a-b23a-4b5f765c7c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315588607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.315588607
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2046861874
Short name T835
Test name
Test status
Simulation time 45300508 ps
CPU time 1.12 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 217272 kb
Host smart-f642c59b-3763-44cc-a689-732b9623f1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046861874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2046861874
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.2111361900
Short name T277
Test name
Test status
Simulation time 27219440 ps
CPU time 1.22 seconds
Started Aug 05 06:09:17 PM PDT 24
Finished Aug 05 06:09:18 PM PDT 24
Peak memory 218664 kb
Host smart-9f4bfcdc-10fd-4a99-aeb5-a09d3c9fb095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111361900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.2111361900
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.2867265598
Short name T321
Test name
Test status
Simulation time 62215755 ps
CPU time 2.4 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 220012 kb
Host smart-c311d01e-d99a-404d-b653-698f8ceff6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867265598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2867265598
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.3517852209
Short name T111
Test name
Test status
Simulation time 28571000 ps
CPU time 1.28 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:30 PM PDT 24
Peak memory 218716 kb
Host smart-721fa5b5-dc7e-4be8-aa2e-939629ea2203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517852209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3517852209
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3988068152
Short name T34
Test name
Test status
Simulation time 189939533 ps
CPU time 1.73 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 218608 kb
Host smart-a998352a-d9d1-4f10-8ed8-6c511e8f5644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988068152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3988068152
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2123791673
Short name T159
Test name
Test status
Simulation time 41715401 ps
CPU time 1.11 seconds
Started Aug 05 06:09:18 PM PDT 24
Finished Aug 05 06:09:19 PM PDT 24
Peak memory 218516 kb
Host smart-dc45e8af-6822-4f5d-b227-50fec78aa02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123791673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2123791673
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2754820539
Short name T423
Test name
Test status
Simulation time 94417070 ps
CPU time 1.22 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 215280 kb
Host smart-5ead0e63-1987-47ec-8e16-428e90ead001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754820539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2754820539
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.572653744
Short name T910
Test name
Test status
Simulation time 70618870 ps
CPU time 1.14 seconds
Started Aug 05 06:07:38 PM PDT 24
Finished Aug 05 06:07:39 PM PDT 24
Peak memory 220396 kb
Host smart-09320c82-06a3-45c4-8046-be7af1ac39a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572653744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.572653744
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3119938329
Short name T633
Test name
Test status
Simulation time 15644154 ps
CPU time 0.93 seconds
Started Aug 05 06:07:36 PM PDT 24
Finished Aug 05 06:07:38 PM PDT 24
Peak memory 215152 kb
Host smart-273dcf46-f6e3-4987-bfd4-84a77b08a56c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119938329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3119938329
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.605081609
Short name T377
Test name
Test status
Simulation time 14689267 ps
CPU time 0.93 seconds
Started Aug 05 06:07:27 PM PDT 24
Finished Aug 05 06:07:28 PM PDT 24
Peak memory 216392 kb
Host smart-14de14ec-e543-43cf-a324-7e7f3be50ae4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605081609 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.605081609
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3791317659
Short name T979
Test name
Test status
Simulation time 59334076 ps
CPU time 1.05 seconds
Started Aug 05 06:07:34 PM PDT 24
Finished Aug 05 06:07:36 PM PDT 24
Peak memory 216948 kb
Host smart-ba1f63ad-2b4b-411d-b4b3-9cf8f3864808
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791317659 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3791317659
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2370946926
Short name T924
Test name
Test status
Simulation time 31317276 ps
CPU time 0.98 seconds
Started Aug 05 06:07:27 PM PDT 24
Finished Aug 05 06:07:29 PM PDT 24
Peak memory 223864 kb
Host smart-cc4e34ba-51e7-4532-abdf-473bf095fc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370946926 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2370946926
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1099597156
Short name T426
Test name
Test status
Simulation time 40361473 ps
CPU time 1.25 seconds
Started Aug 05 06:07:40 PM PDT 24
Finished Aug 05 06:07:41 PM PDT 24
Peak memory 217420 kb
Host smart-abf43e69-b481-4b85-86f0-7e58b491b2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099597156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1099597156
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1494435221
Short name T621
Test name
Test status
Simulation time 21482124 ps
CPU time 1.06 seconds
Started Aug 05 06:07:25 PM PDT 24
Finished Aug 05 06:07:26 PM PDT 24
Peak memory 215564 kb
Host smart-1ee773f1-f9c1-48a0-bb14-73124f333581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494435221 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1494435221
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2237977715
Short name T686
Test name
Test status
Simulation time 17404781 ps
CPU time 1 seconds
Started Aug 05 06:07:41 PM PDT 24
Finished Aug 05 06:07:42 PM PDT 24
Peak memory 207088 kb
Host smart-b3ae5890-3d2e-434c-92a8-472c84e3c956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237977715 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2237977715
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.1587480262
Short name T726
Test name
Test status
Simulation time 85236216 ps
CPU time 0.91 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:48 PM PDT 24
Peak memory 207108 kb
Host smart-57144a2b-88ac-4a56-8c91-d7991935a039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587480262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1587480262
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1531031635
Short name T177
Test name
Test status
Simulation time 118501328 ps
CPU time 2.84 seconds
Started Aug 05 06:07:41 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 217192 kb
Host smart-f47377f8-30a7-4b92-995f-66887c8b442c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531031635 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1531031635
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3876620477
Short name T886
Test name
Test status
Simulation time 16843819303 ps
CPU time 371.14 seconds
Started Aug 05 06:07:33 PM PDT 24
Finished Aug 05 06:13:44 PM PDT 24
Peak memory 220248 kb
Host smart-73adcc6a-8ea7-4db6-a0d0-82fb8c8cf94d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876620477 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3876620477
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_disable.1078771121
Short name T136
Test name
Test status
Simulation time 18893841 ps
CPU time 0.89 seconds
Started Aug 05 06:08:10 PM PDT 24
Finished Aug 05 06:08:11 PM PDT 24
Peak memory 215380 kb
Host smart-ddf6e5c4-b8cb-411e-988d-46906bff62c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078771121 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1078771121
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1368477884
Short name T430
Test name
Test status
Simulation time 126915538 ps
CPU time 1.11 seconds
Started Aug 05 06:08:07 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 217024 kb
Host smart-03e2dd8b-4b04-485f-86f7-43f9dcb7e272
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368477884 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1368477884
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3580818300
Short name T44
Test name
Test status
Simulation time 32769582 ps
CPU time 0.97 seconds
Started Aug 05 06:08:13 PM PDT 24
Finished Aug 05 06:08:14 PM PDT 24
Peak memory 223776 kb
Host smart-4391b16a-6672-4b1a-9b48-5e94f01a2cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580818300 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3580818300
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1754603757
Short name T601
Test name
Test status
Simulation time 629574735 ps
CPU time 5.8 seconds
Started Aug 05 06:08:03 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 220128 kb
Host smart-d5142dde-af6d-4201-879e-b7affa5b6219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754603757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1754603757
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1162387697
Short name T907
Test name
Test status
Simulation time 22165120 ps
CPU time 1.16 seconds
Started Aug 05 06:08:00 PM PDT 24
Finished Aug 05 06:08:02 PM PDT 24
Peak memory 215496 kb
Host smart-e62c06b7-1f0f-412b-908a-8242cbbe481a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162387697 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1162387697
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1495336092
Short name T838
Test name
Test status
Simulation time 16544852 ps
CPU time 1 seconds
Started Aug 05 06:08:02 PM PDT 24
Finished Aug 05 06:08:03 PM PDT 24
Peak memory 215276 kb
Host smart-00fcfc8d-22f8-4ded-a47d-31bd3bbae598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495336092 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1495336092
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.753118611
Short name T880
Test name
Test status
Simulation time 620061698 ps
CPU time 3.61 seconds
Started Aug 05 06:07:55 PM PDT 24
Finished Aug 05 06:07:59 PM PDT 24
Peak memory 217416 kb
Host smart-f4c4ef43-bc80-40ba-a0ff-2fa84ef5a254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753118611 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.753118611
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.803005504
Short name T224
Test name
Test status
Simulation time 125628554620 ps
CPU time 1568.68 seconds
Started Aug 05 06:07:50 PM PDT 24
Finished Aug 05 06:34:00 PM PDT 24
Peak memory 224020 kb
Host smart-14886ff8-7958-48fa-af73-7ec5654f90a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803005504 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.803005504
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.4174080186
Short name T320
Test name
Test status
Simulation time 61647738 ps
CPU time 1.54 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 218684 kb
Host smart-525aa152-3c60-4b50-bac1-79cbd1cc20ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174080186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.4174080186
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3446915868
Short name T592
Test name
Test status
Simulation time 42247084 ps
CPU time 1.67 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:32 PM PDT 24
Peak memory 218648 kb
Host smart-26d66814-03f5-4159-8b88-ecfab68cbe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446915868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3446915868
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1327322192
Short name T554
Test name
Test status
Simulation time 53408705 ps
CPU time 1.5 seconds
Started Aug 05 06:09:33 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 218364 kb
Host smart-d61947dc-ce0d-4ad9-8ee0-c9dc9dd1e5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327322192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1327322192
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2566017491
Short name T68
Test name
Test status
Simulation time 52376905 ps
CPU time 1.17 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 217236 kb
Host smart-02e14c61-a48b-4147-a58c-f52149c087e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566017491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2566017491
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2832629023
Short name T345
Test name
Test status
Simulation time 75486949 ps
CPU time 1.56 seconds
Started Aug 05 06:09:28 PM PDT 24
Finished Aug 05 06:09:30 PM PDT 24
Peak memory 218692 kb
Host smart-eae15755-08e5-42da-8f65-9d48803b06ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832629023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2832629023
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2304894142
Short name T416
Test name
Test status
Simulation time 94250607 ps
CPU time 1.37 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 218732 kb
Host smart-e6c5de23-6567-4fac-a680-1c477ec7d791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304894142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2304894142
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1578758022
Short name T452
Test name
Test status
Simulation time 175581883 ps
CPU time 1.27 seconds
Started Aug 05 06:09:25 PM PDT 24
Finished Aug 05 06:09:27 PM PDT 24
Peak memory 218920 kb
Host smart-f29068dc-7b05-4d32-ae48-c03a1f415558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578758022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1578758022
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2816482994
Short name T363
Test name
Test status
Simulation time 37419151 ps
CPU time 1.06 seconds
Started Aug 05 06:09:34 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 217308 kb
Host smart-a13f36ae-9680-449e-be98-7de9b8253c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816482994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2816482994
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1271400417
Short name T516
Test name
Test status
Simulation time 102848602 ps
CPU time 1.25 seconds
Started Aug 05 06:09:20 PM PDT 24
Finished Aug 05 06:09:22 PM PDT 24
Peak memory 217504 kb
Host smart-12eb643d-0cef-4e25-b239-36664314d15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271400417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1271400417
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2635374393
Short name T747
Test name
Test status
Simulation time 44344432 ps
CPU time 1.24 seconds
Started Aug 05 06:09:26 PM PDT 24
Finished Aug 05 06:09:27 PM PDT 24
Peak memory 217196 kb
Host smart-b6341f3d-c824-47ec-8c5f-49196d653719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635374393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2635374393
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2711005392
Short name T872
Test name
Test status
Simulation time 24057442 ps
CPU time 1.13 seconds
Started Aug 05 06:08:06 PM PDT 24
Finished Aug 05 06:08:07 PM PDT 24
Peak memory 215664 kb
Host smart-6fdf0f55-7f0d-4f84-a4e2-be748c750b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711005392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2711005392
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1178062589
Short name T380
Test name
Test status
Simulation time 23067322 ps
CPU time 0.85 seconds
Started Aug 05 06:07:55 PM PDT 24
Finished Aug 05 06:07:56 PM PDT 24
Peak memory 206716 kb
Host smart-4f1bc700-2d09-433c-a49c-25a9d64346d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178062589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1178062589
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2429020958
Short name T960
Test name
Test status
Simulation time 22836675 ps
CPU time 0.82 seconds
Started Aug 05 06:08:00 PM PDT 24
Finished Aug 05 06:08:01 PM PDT 24
Peak memory 216228 kb
Host smart-2c5f5182-5f5a-47f6-b6d0-fca81c0349db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429020958 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2429020958
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3631385011
Short name T191
Test name
Test status
Simulation time 85087105 ps
CPU time 1.19 seconds
Started Aug 05 06:08:06 PM PDT 24
Finished Aug 05 06:08:07 PM PDT 24
Peak memory 216928 kb
Host smart-3b6da7a1-ec41-4f4d-8c93-00ccae2d8d6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631385011 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3631385011
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.4014832080
Short name T110
Test name
Test status
Simulation time 58969441 ps
CPU time 1.04 seconds
Started Aug 05 06:08:09 PM PDT 24
Finished Aug 05 06:08:10 PM PDT 24
Peak memory 220684 kb
Host smart-e084852f-4b71-4464-9eb6-06515566b597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014832080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.4014832080
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3465870301
Short name T832
Test name
Test status
Simulation time 71317015 ps
CPU time 2.75 seconds
Started Aug 05 06:07:57 PM PDT 24
Finished Aug 05 06:08:00 PM PDT 24
Peak memory 220188 kb
Host smart-e9c8aacc-23bc-4089-856f-f7877cc5329b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465870301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3465870301
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2862682467
Short name T822
Test name
Test status
Simulation time 30271721 ps
CPU time 0.86 seconds
Started Aug 05 06:08:02 PM PDT 24
Finished Aug 05 06:08:03 PM PDT 24
Peak memory 215332 kb
Host smart-060f2d6c-0e8e-4bc0-87b9-1fccb0d59b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862682467 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2862682467
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.313464041
Short name T548
Test name
Test status
Simulation time 18988127 ps
CPU time 1.02 seconds
Started Aug 05 06:08:15 PM PDT 24
Finished Aug 05 06:08:16 PM PDT 24
Peak memory 215296 kb
Host smart-b3a6afcb-bde4-4d1c-8dd8-e404878f1828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313464041 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.313464041
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3556322651
Short name T632
Test name
Test status
Simulation time 26214141 ps
CPU time 1.14 seconds
Started Aug 05 06:07:55 PM PDT 24
Finished Aug 05 06:07:56 PM PDT 24
Peak memory 215248 kb
Host smart-5ab02448-5770-4a7f-9675-0adbb8607679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556322651 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3556322651
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2414761739
Short name T899
Test name
Test status
Simulation time 375688361546 ps
CPU time 603.17 seconds
Started Aug 05 06:07:57 PM PDT 24
Finished Aug 05 06:18:01 PM PDT 24
Peak memory 219348 kb
Host smart-532a85ed-c64f-4b3c-bb60-6c131fc8d3e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414761739 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2414761739
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3724537612
Short name T422
Test name
Test status
Simulation time 57178978 ps
CPU time 1.51 seconds
Started Aug 05 06:09:38 PM PDT 24
Finished Aug 05 06:09:40 PM PDT 24
Peak memory 217436 kb
Host smart-ce79bc0e-5245-4d2f-889a-f03fd70d03f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724537612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3724537612
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3668708707
Short name T474
Test name
Test status
Simulation time 118369745 ps
CPU time 0.94 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 217272 kb
Host smart-8b03970a-c02f-4ab5-a032-75368af36495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668708707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3668708707
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3499766634
Short name T532
Test name
Test status
Simulation time 75186057 ps
CPU time 1.48 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 218592 kb
Host smart-382be62d-4a9a-4a83-bcc5-e9a142a90696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499766634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3499766634
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2511856816
Short name T500
Test name
Test status
Simulation time 42697820 ps
CPU time 1.1 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:30 PM PDT 24
Peak memory 218392 kb
Host smart-3637cb23-9f57-4784-82f1-ed0050f068b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511856816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2511856816
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2254786685
Short name T956
Test name
Test status
Simulation time 20320037 ps
CPU time 1.1 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:28 PM PDT 24
Peak memory 217336 kb
Host smart-c5696dac-0ba7-4661-92e3-ffa9e13f9b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254786685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2254786685
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3902636621
Short name T329
Test name
Test status
Simulation time 54703153 ps
CPU time 1.34 seconds
Started Aug 05 06:09:36 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 218740 kb
Host smart-2a546c2f-21a7-46be-88dd-c05f64a17bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902636621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3902636621
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1919933372
Short name T649
Test name
Test status
Simulation time 121930039 ps
CPU time 1.35 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 218420 kb
Host smart-a79ee1d5-9c4c-4837-8402-06d8565dce1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919933372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1919933372
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1008626724
Short name T52
Test name
Test status
Simulation time 45973238 ps
CPU time 1.49 seconds
Started Aug 05 06:09:28 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 218588 kb
Host smart-c5fa255a-cde1-44a2-999e-36e20c461dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008626724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1008626724
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2423164633
Short name T655
Test name
Test status
Simulation time 130011917 ps
CPU time 1.28 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 217504 kb
Host smart-e4e5cebe-b1c3-4776-971a-6b7e5ebb11a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423164633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2423164633
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3134557438
Short name T651
Test name
Test status
Simulation time 40598455 ps
CPU time 1.47 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 219928 kb
Host smart-7d24f152-77ca-4e6a-b6e0-3c7906457447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134557438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3134557438
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3612593894
Short name T140
Test name
Test status
Simulation time 57965009 ps
CPU time 1.16 seconds
Started Aug 05 06:08:07 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 220160 kb
Host smart-a0ce06d2-4657-414a-a315-cc9f607a8734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612593894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3612593894
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3856368282
Short name T819
Test name
Test status
Simulation time 173780510 ps
CPU time 0.87 seconds
Started Aug 05 06:07:58 PM PDT 24
Finished Aug 05 06:07:59 PM PDT 24
Peak memory 206712 kb
Host smart-32ebe10e-c907-4a52-996d-5386f57ff362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856368282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3856368282
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2403693484
Short name T801
Test name
Test status
Simulation time 21456807 ps
CPU time 0.86 seconds
Started Aug 05 06:08:14 PM PDT 24
Finished Aug 05 06:08:15 PM PDT 24
Peak memory 216220 kb
Host smart-cb88b2fa-b0ab-4eb9-ba23-8b90aac944c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403693484 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2403693484
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1165692291
Short name T130
Test name
Test status
Simulation time 27077005 ps
CPU time 1.17 seconds
Started Aug 05 06:08:10 PM PDT 24
Finished Aug 05 06:08:11 PM PDT 24
Peak memory 216932 kb
Host smart-072c3ed1-cd96-4984-b5f9-2b116b94b9b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165692291 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1165692291
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3561099941
Short name T514
Test name
Test status
Simulation time 21245679 ps
CPU time 1.04 seconds
Started Aug 05 06:08:03 PM PDT 24
Finished Aug 05 06:08:05 PM PDT 24
Peak memory 219272 kb
Host smart-ef07fe50-da1e-4a20-8bc5-e30235c02fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561099941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3561099941
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1240973703
Short name T754
Test name
Test status
Simulation time 48620216 ps
CPU time 1.21 seconds
Started Aug 05 06:07:50 PM PDT 24
Finished Aug 05 06:07:52 PM PDT 24
Peak memory 218456 kb
Host smart-ca7f2996-2bd6-4494-942f-8700ddb640a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240973703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1240973703
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1065413732
Short name T737
Test name
Test status
Simulation time 21768174 ps
CPU time 1.09 seconds
Started Aug 05 06:08:17 PM PDT 24
Finished Aug 05 06:08:18 PM PDT 24
Peak memory 215360 kb
Host smart-0ae52ac1-685b-448d-a684-8e377147a54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065413732 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1065413732
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2489151240
Short name T511
Test name
Test status
Simulation time 15617319 ps
CPU time 0.96 seconds
Started Aug 05 06:08:04 PM PDT 24
Finished Aug 05 06:08:05 PM PDT 24
Peak memory 215316 kb
Host smart-ecb28a36-2552-4dea-85bb-b1a006d1fa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489151240 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2489151240
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2837478134
Short name T431
Test name
Test status
Simulation time 943425514 ps
CPU time 5.57 seconds
Started Aug 05 06:08:12 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 217336 kb
Host smart-438d8b65-66dd-49a8-8de9-643bfe950f5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837478134 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2837478134
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3402413278
Short name T236
Test name
Test status
Simulation time 337865054686 ps
CPU time 886.13 seconds
Started Aug 05 06:08:09 PM PDT 24
Finished Aug 05 06:22:56 PM PDT 24
Peak memory 220876 kb
Host smart-21161517-785b-4210-80a3-bd0876565653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402413278 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3402413278
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2495822998
Short name T536
Test name
Test status
Simulation time 73557042 ps
CPU time 1.34 seconds
Started Aug 05 06:09:28 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 218816 kb
Host smart-2c818152-3afe-4c81-9376-79167e7e9925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495822998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2495822998
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2869970891
Short name T869
Test name
Test status
Simulation time 49009342 ps
CPU time 1.18 seconds
Started Aug 05 06:09:26 PM PDT 24
Finished Aug 05 06:09:27 PM PDT 24
Peak memory 217336 kb
Host smart-8514183c-0282-4788-b512-cd0e4ae48f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869970891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2869970891
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.4041889161
Short name T333
Test name
Test status
Simulation time 49882978 ps
CPU time 1.57 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 217244 kb
Host smart-11b94cd5-f668-4812-b7e5-b7ec758e15dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041889161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.4041889161
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2567075360
Short name T857
Test name
Test status
Simulation time 64513656 ps
CPU time 1.23 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 217376 kb
Host smart-faf551ae-bba3-4b48-b5ff-cb7d9d907efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567075360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2567075360
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2497266268
Short name T975
Test name
Test status
Simulation time 50335550 ps
CPU time 1.62 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:32 PM PDT 24
Peak memory 219856 kb
Host smart-e5033eb9-157d-47ce-94fa-95d305f48c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497266268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2497266268
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2006305472
Short name T445
Test name
Test status
Simulation time 57303210 ps
CPU time 1.32 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 217020 kb
Host smart-88dd491d-2a3e-4b2f-bf76-59d721959813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006305472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2006305472
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1043585299
Short name T523
Test name
Test status
Simulation time 52934865 ps
CPU time 1.16 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:32 PM PDT 24
Peak memory 219792 kb
Host smart-f924ae33-5dda-4477-b6b3-577bec37deae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043585299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1043585299
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1627433721
Short name T74
Test name
Test status
Simulation time 41875962 ps
CPU time 1.24 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 218608 kb
Host smart-11b68694-ff4e-4bce-9e51-b336daed0677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627433721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1627433721
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3137637126
Short name T424
Test name
Test status
Simulation time 44211840 ps
CPU time 1.01 seconds
Started Aug 05 06:09:38 PM PDT 24
Finished Aug 05 06:09:39 PM PDT 24
Peak memory 217392 kb
Host smart-d9641725-a308-42c7-a99c-a8880529bfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137637126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3137637126
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.283877114
Short name T563
Test name
Test status
Simulation time 25027336 ps
CPU time 1.14 seconds
Started Aug 05 06:07:56 PM PDT 24
Finished Aug 05 06:07:57 PM PDT 24
Peak memory 215664 kb
Host smart-7b6b269c-ab00-45fd-a6fe-26f6ebf46fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283877114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.283877114
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.259326862
Short name T374
Test name
Test status
Simulation time 46508688 ps
CPU time 0.88 seconds
Started Aug 05 06:08:12 PM PDT 24
Finished Aug 05 06:08:13 PM PDT 24
Peak memory 206748 kb
Host smart-a6fd872c-eaf1-4a6e-a9c7-4bd7848181db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259326862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.259326862
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1129173569
Short name T155
Test name
Test status
Simulation time 33250046 ps
CPU time 0.84 seconds
Started Aug 05 06:07:49 PM PDT 24
Finished Aug 05 06:07:50 PM PDT 24
Peak memory 216232 kb
Host smart-e128ca36-8717-433f-8682-b06b7c2f1d60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129173569 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1129173569
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2639483238
Short name T598
Test name
Test status
Simulation time 34460598 ps
CPU time 1.1 seconds
Started Aug 05 06:08:01 PM PDT 24
Finished Aug 05 06:08:02 PM PDT 24
Peak memory 216776 kb
Host smart-0cc64b11-67e9-496d-a7dd-b66d1cf5c242
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639483238 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2639483238
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.516669221
Short name T94
Test name
Test status
Simulation time 31656568 ps
CPU time 1.19 seconds
Started Aug 05 06:07:54 PM PDT 24
Finished Aug 05 06:07:55 PM PDT 24
Peak memory 217348 kb
Host smart-a426e01b-78b6-490d-835a-895adbe20c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516669221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.516669221
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1079705683
Short name T865
Test name
Test status
Simulation time 93020894 ps
CPU time 1.05 seconds
Started Aug 05 06:08:05 PM PDT 24
Finished Aug 05 06:08:06 PM PDT 24
Peak memory 217124 kb
Host smart-c3a77fea-44e0-460b-b139-af77a36ae82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079705683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1079705683
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.119075563
Short name T410
Test name
Test status
Simulation time 22180488 ps
CPU time 1.08 seconds
Started Aug 05 06:08:17 PM PDT 24
Finished Aug 05 06:08:18 PM PDT 24
Peak memory 215540 kb
Host smart-2ae14c50-f5a6-4059-9ae4-6a764a5550bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119075563 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.119075563
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.4289205660
Short name T550
Test name
Test status
Simulation time 15754119 ps
CPU time 1.02 seconds
Started Aug 05 06:08:00 PM PDT 24
Finished Aug 05 06:08:01 PM PDT 24
Peak memory 215316 kb
Host smart-47250293-b009-4deb-a750-1a3e44a2b623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289205660 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.4289205660
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2121227300
Short name T761
Test name
Test status
Simulation time 276229338 ps
CPU time 5.71 seconds
Started Aug 05 06:07:57 PM PDT 24
Finished Aug 05 06:08:03 PM PDT 24
Peak memory 220428 kb
Host smart-5e80eff2-ffea-4026-92f1-018237e90ed4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121227300 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2121227300
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4202507998
Short name T760
Test name
Test status
Simulation time 14937730674 ps
CPU time 382.19 seconds
Started Aug 05 06:07:55 PM PDT 24
Finished Aug 05 06:14:17 PM PDT 24
Peak memory 223568 kb
Host smart-42a37f36-00d9-4cdc-8f8c-fe4b962cd321
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202507998 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4202507998
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.295041903
Short name T777
Test name
Test status
Simulation time 142830381 ps
CPU time 1.71 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 218456 kb
Host smart-9db5a3e6-2e45-4a47-8937-8dc469002428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295041903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.295041903
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.742538765
Short name T35
Test name
Test status
Simulation time 57689356 ps
CPU time 1.4 seconds
Started Aug 05 06:09:37 PM PDT 24
Finished Aug 05 06:09:39 PM PDT 24
Peak memory 218620 kb
Host smart-8f616b1d-3983-4e92-80f5-6ca47e101d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742538765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.742538765
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1328181562
Short name T539
Test name
Test status
Simulation time 42570526 ps
CPU time 1.44 seconds
Started Aug 05 06:09:55 PM PDT 24
Finished Aug 05 06:09:57 PM PDT 24
Peak memory 219424 kb
Host smart-864b857a-23cc-4a1c-89a8-848a12ec52c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328181562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1328181562
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.354301903
Short name T449
Test name
Test status
Simulation time 88684699 ps
CPU time 1.14 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 219852 kb
Host smart-bbe98322-181e-4d96-86ff-90ba3c45f1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354301903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.354301903
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2154157770
Short name T365
Test name
Test status
Simulation time 59384830 ps
CPU time 1.68 seconds
Started Aug 05 06:09:38 PM PDT 24
Finished Aug 05 06:09:40 PM PDT 24
Peak memory 218764 kb
Host smart-02a232d8-9e44-42cb-87e0-fa353390c0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154157770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2154157770
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1406781164
Short name T648
Test name
Test status
Simulation time 32633695 ps
CPU time 1.44 seconds
Started Aug 05 06:09:36 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 219936 kb
Host smart-727005cf-753b-4191-8958-bee98f355ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406781164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1406781164
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1573873868
Short name T631
Test name
Test status
Simulation time 49865989 ps
CPU time 1.49 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:32 PM PDT 24
Peak memory 218452 kb
Host smart-7d2c662a-d11c-4c61-bcfd-f9ce47d46ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573873868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1573873868
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2211895007
Short name T393
Test name
Test status
Simulation time 123611282 ps
CPU time 1.07 seconds
Started Aug 05 06:09:33 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 217284 kb
Host smart-24d12c4f-f58f-4a4c-aacb-b7972891c20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211895007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2211895007
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.779354174
Short name T576
Test name
Test status
Simulation time 131066594 ps
CPU time 2.08 seconds
Started Aug 05 06:09:23 PM PDT 24
Finished Aug 05 06:09:25 PM PDT 24
Peak memory 219932 kb
Host smart-ffafe54c-358e-4cf1-8314-6141cd96b63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779354174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.779354174
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4219512452
Short name T487
Test name
Test status
Simulation time 29948845 ps
CPU time 1.3 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:30 PM PDT 24
Peak memory 218476 kb
Host smart-0f6cf27b-e67d-44ea-9892-1b82c0ad5130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219512452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4219512452
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.329406680
Short name T790
Test name
Test status
Simulation time 81815620 ps
CPU time 1.17 seconds
Started Aug 05 06:07:49 PM PDT 24
Finished Aug 05 06:07:51 PM PDT 24
Peak memory 218824 kb
Host smart-5a5d78ec-a2f9-4c87-b911-2586262d1e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329406680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.329406680
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1373667287
Short name T811
Test name
Test status
Simulation time 15945508 ps
CPU time 0.93 seconds
Started Aug 05 06:08:09 PM PDT 24
Finished Aug 05 06:08:10 PM PDT 24
Peak memory 214896 kb
Host smart-46eac860-2816-44f1-9b15-2720a9b02282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373667287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1373667287
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1550749179
Short name T147
Test name
Test status
Simulation time 15885929 ps
CPU time 0.87 seconds
Started Aug 05 06:07:49 PM PDT 24
Finished Aug 05 06:07:50 PM PDT 24
Peak memory 216224 kb
Host smart-e52d1fda-3a66-459a-94da-19ab4dfdcbcd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550749179 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1550749179
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2025257936
Short name T198
Test name
Test status
Simulation time 48056121 ps
CPU time 1.48 seconds
Started Aug 05 06:07:55 PM PDT 24
Finished Aug 05 06:07:57 PM PDT 24
Peak memory 216848 kb
Host smart-482e7f1f-e26f-48ea-8622-326bc3a46670
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025257936 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2025257936
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_genbits.3948346566
Short name T20
Test name
Test status
Simulation time 48207569 ps
CPU time 1.19 seconds
Started Aug 05 06:08:12 PM PDT 24
Finished Aug 05 06:08:13 PM PDT 24
Peak memory 219488 kb
Host smart-10e83e7e-c10b-45e8-bd54-9bacb2dcb09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948346566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3948346566
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_smoke.2320458299
Short name T542
Test name
Test status
Simulation time 114862834 ps
CPU time 0.93 seconds
Started Aug 05 06:07:53 PM PDT 24
Finished Aug 05 06:07:54 PM PDT 24
Peak memory 215276 kb
Host smart-b228f762-e890-4dd3-878d-bf39640e7b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320458299 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2320458299
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.4192736137
Short name T669
Test name
Test status
Simulation time 65581586 ps
CPU time 1.62 seconds
Started Aug 05 06:07:50 PM PDT 24
Finished Aug 05 06:07:52 PM PDT 24
Peak memory 218468 kb
Host smart-caa5c359-eb57-4c0e-9d9b-b3cb9afa5059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192736137 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.4192736137
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1492057262
Short name T871
Test name
Test status
Simulation time 34659134857 ps
CPU time 764.09 seconds
Started Aug 05 06:08:04 PM PDT 24
Finished Aug 05 06:20:48 PM PDT 24
Peak memory 223668 kb
Host smart-b2f9474c-f0e6-4879-80e5-bcf754a5fa8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492057262 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1492057262
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1971144979
Short name T323
Test name
Test status
Simulation time 42237640 ps
CPU time 1.26 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 217496 kb
Host smart-45daa141-8d15-47db-b985-d864665df45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971144979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1971144979
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3461398579
Short name T330
Test name
Test status
Simulation time 59413204 ps
CPU time 1.58 seconds
Started Aug 05 06:09:33 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 218560 kb
Host smart-04c8b451-0368-4c8a-b056-b312d4f3c5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461398579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3461398579
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.595959814
Short name T38
Test name
Test status
Simulation time 62241611 ps
CPU time 1.4 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 218576 kb
Host smart-89e9e2bc-8c93-4abc-ab36-b24d0e5dfbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595959814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.595959814
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3946983557
Short name T698
Test name
Test status
Simulation time 43965746 ps
CPU time 1.67 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 219208 kb
Host smart-b5739048-02c2-423a-a836-c3b6c4822d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946983557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3946983557
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.382907092
Short name T920
Test name
Test status
Simulation time 160060666 ps
CPU time 1.19 seconds
Started Aug 05 06:09:45 PM PDT 24
Finished Aug 05 06:09:46 PM PDT 24
Peak memory 220012 kb
Host smart-fef1ba4d-5008-4200-9e20-2ce314d25c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382907092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.382907092
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.944989850
Short name T347
Test name
Test status
Simulation time 206548290 ps
CPU time 1.87 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:32 PM PDT 24
Peak memory 219088 kb
Host smart-833f3f6f-462f-4093-aa68-a84f93e71b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944989850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.944989850
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2561155121
Short name T395
Test name
Test status
Simulation time 123389069 ps
CPU time 1.9 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 218700 kb
Host smart-f73e7239-1bb2-4f2b-a9aa-68e1e3bf7787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561155121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2561155121
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3187117765
Short name T765
Test name
Test status
Simulation time 60258545 ps
CPU time 1.69 seconds
Started Aug 05 06:09:33 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 218652 kb
Host smart-7a502d42-8dba-4c4f-a1a8-62b2169e6e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187117765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3187117765
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3208414061
Short name T486
Test name
Test status
Simulation time 60204275 ps
CPU time 1.05 seconds
Started Aug 05 06:09:36 PM PDT 24
Finished Aug 05 06:09:38 PM PDT 24
Peak memory 219724 kb
Host smart-704ec07e-e377-4c33-92d0-d55d74ec6b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208414061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3208414061
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2381078758
Short name T644
Test name
Test status
Simulation time 47124481 ps
CPU time 1.33 seconds
Started Aug 05 06:09:37 PM PDT 24
Finished Aug 05 06:09:39 PM PDT 24
Peak memory 218796 kb
Host smart-bb0e3a54-89eb-4068-95e2-10c80020a86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381078758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2381078758
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.687303524
Short name T614
Test name
Test status
Simulation time 26446438 ps
CPU time 1.3 seconds
Started Aug 05 06:08:08 PM PDT 24
Finished Aug 05 06:08:14 PM PDT 24
Peak memory 219600 kb
Host smart-fb66f133-7d0b-4e17-9b59-913219b9733d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687303524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.687303524
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.743304924
Short name T611
Test name
Test status
Simulation time 16838021 ps
CPU time 0.95 seconds
Started Aug 05 06:07:55 PM PDT 24
Finished Aug 05 06:07:56 PM PDT 24
Peak memory 206716 kb
Host smart-53e89e4a-35ec-4c8f-8273-a287fdd88bee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743304924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.743304924
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1687325199
Short name T497
Test name
Test status
Simulation time 34694646 ps
CPU time 0.8 seconds
Started Aug 05 06:08:12 PM PDT 24
Finished Aug 05 06:08:13 PM PDT 24
Peak memory 215920 kb
Host smart-78f0821b-8b47-40dc-8f1a-e5d63220ce74
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687325199 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1687325199
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1347742220
Short name T58
Test name
Test status
Simulation time 131042190 ps
CPU time 1.12 seconds
Started Aug 05 06:08:22 PM PDT 24
Finished Aug 05 06:08:23 PM PDT 24
Peak memory 216892 kb
Host smart-4b3aeb6b-0db3-4513-a72f-15e90086137b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347742220 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1347742220
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3525480642
Short name T788
Test name
Test status
Simulation time 75802765 ps
CPU time 1.05 seconds
Started Aug 05 06:08:01 PM PDT 24
Finished Aug 05 06:08:02 PM PDT 24
Peak memory 219708 kb
Host smart-87783288-1640-4127-87fd-565ac2bb8f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525480642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3525480642
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3181214126
Short name T659
Test name
Test status
Simulation time 38377671 ps
CPU time 1.38 seconds
Started Aug 05 06:08:08 PM PDT 24
Finished Aug 05 06:08:09 PM PDT 24
Peak memory 215296 kb
Host smart-3e521490-d456-4fc5-9536-6be1d4cea540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181214126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3181214126
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2230267723
Short name T90
Test name
Test status
Simulation time 22738809 ps
CPU time 0.95 seconds
Started Aug 05 06:08:07 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 216068 kb
Host smart-329b6065-61f1-40d7-99c2-4ef9fe9be745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230267723 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2230267723
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.416135236
Short name T665
Test name
Test status
Simulation time 26322918 ps
CPU time 0.9 seconds
Started Aug 05 06:07:58 PM PDT 24
Finished Aug 05 06:07:59 PM PDT 24
Peak memory 215284 kb
Host smart-66fc078b-c731-4dc7-92a6-2606d1e11d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416135236 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.416135236
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3729915000
Short name T401
Test name
Test status
Simulation time 139338604 ps
CPU time 1.38 seconds
Started Aug 05 06:07:55 PM PDT 24
Finished Aug 05 06:07:57 PM PDT 24
Peak memory 207112 kb
Host smart-135711a3-22dc-441a-936e-784666009f07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729915000 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3729915000
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1145320
Short name T521
Test name
Test status
Simulation time 52438803061 ps
CPU time 1190.01 seconds
Started Aug 05 06:07:58 PM PDT 24
Finished Aug 05 06:27:49 PM PDT 24
Peak memory 220196 kb
Host smart-a3535331-d22e-4571-a95f-4a596c83ba1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145320 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1145320
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2967741674
Short name T591
Test name
Test status
Simulation time 215010996 ps
CPU time 2.6 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 220228 kb
Host smart-e56e43fe-403a-42c4-bcba-c070af49945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967741674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2967741674
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1388432190
Short name T616
Test name
Test status
Simulation time 57298072 ps
CPU time 2.25 seconds
Started Aug 05 06:09:34 PM PDT 24
Finished Aug 05 06:09:36 PM PDT 24
Peak memory 220252 kb
Host smart-fe4f808b-bdcb-4ae5-aefe-2a9a14400169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388432190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1388432190
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2235012022
Short name T922
Test name
Test status
Simulation time 40504371 ps
CPU time 1.43 seconds
Started Aug 05 06:09:37 PM PDT 24
Finished Aug 05 06:09:39 PM PDT 24
Peak memory 217244 kb
Host smart-e2d505e3-0199-4ea5-bf39-2e1590231dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235012022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2235012022
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3567363433
Short name T338
Test name
Test status
Simulation time 112860931 ps
CPU time 1.76 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 219304 kb
Host smart-8b9c52dd-d790-4679-b89b-a7f27028646e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567363433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3567363433
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3585024768
Short name T174
Test name
Test status
Simulation time 41074096 ps
CPU time 1.1 seconds
Started Aug 05 06:09:36 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 218904 kb
Host smart-0c363d66-f633-4ec6-80eb-0d86354b7d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585024768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3585024768
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2674389624
Short name T668
Test name
Test status
Simulation time 27486688 ps
CPU time 1.34 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:36 PM PDT 24
Peak memory 217496 kb
Host smart-f6c7cf17-3625-4618-b440-359e0220c458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674389624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2674389624
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1867892171
Short name T612
Test name
Test status
Simulation time 47333774 ps
CPU time 1.73 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 218580 kb
Host smart-8e5a928c-f750-4148-ad6d-603e5b363bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867892171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1867892171
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3225852741
Short name T712
Test name
Test status
Simulation time 43577235 ps
CPU time 1.2 seconds
Started Aug 05 06:09:39 PM PDT 24
Finished Aug 05 06:09:41 PM PDT 24
Peak memory 220084 kb
Host smart-83657e1e-43f2-4c37-b95e-ffa14702474a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225852741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3225852741
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.906524400
Short name T923
Test name
Test status
Simulation time 69452699 ps
CPU time 1.55 seconds
Started Aug 05 06:09:34 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 218700 kb
Host smart-746e0e2e-9deb-424a-a3dd-935c6eab3698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906524400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.906524400
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3764122546
Short name T392
Test name
Test status
Simulation time 54938586 ps
CPU time 1.18 seconds
Started Aug 05 06:09:36 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 217312 kb
Host smart-63b03f0a-8116-4526-b7ce-41e6be78f56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764122546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3764122546
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.874443314
Short name T133
Test name
Test status
Simulation time 133168343 ps
CPU time 1.16 seconds
Started Aug 05 06:08:06 PM PDT 24
Finished Aug 05 06:08:07 PM PDT 24
Peak memory 218628 kb
Host smart-187ce963-0a9e-411c-a541-a774ca46eb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874443314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.874443314
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2392353739
Short name T983
Test name
Test status
Simulation time 108154392 ps
CPU time 0.9 seconds
Started Aug 05 06:08:15 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 214876 kb
Host smart-d81f795f-a429-4733-b4c8-d8bd477636b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392353739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2392353739
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.342580364
Short name T464
Test name
Test status
Simulation time 13124755 ps
CPU time 1.03 seconds
Started Aug 05 06:08:14 PM PDT 24
Finished Aug 05 06:08:15 PM PDT 24
Peak memory 216104 kb
Host smart-230d2a3b-f794-4b64-a6d4-88a87b1a9b52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342580364 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.342580364
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.1381524086
Short name T116
Test name
Test status
Simulation time 30529218 ps
CPU time 1.15 seconds
Started Aug 05 06:08:12 PM PDT 24
Finished Aug 05 06:08:13 PM PDT 24
Peak memory 224036 kb
Host smart-fd60d254-653a-4d10-823c-ea9afb5025dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381524086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1381524086
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1060131807
Short name T603
Test name
Test status
Simulation time 75464570 ps
CPU time 1.18 seconds
Started Aug 05 06:08:07 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 217176 kb
Host smart-07927db5-5456-4dc9-9dbd-b43c0040bf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060131807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1060131807
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1235311007
Short name T504
Test name
Test status
Simulation time 21254535 ps
CPU time 1.11 seconds
Started Aug 05 06:08:14 PM PDT 24
Finished Aug 05 06:08:15 PM PDT 24
Peak memory 215540 kb
Host smart-18e3b111-01b8-4547-bd6b-ca99a583d79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235311007 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1235311007
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3265242416
Short name T451
Test name
Test status
Simulation time 19024498 ps
CPU time 1.01 seconds
Started Aug 05 06:07:57 PM PDT 24
Finished Aug 05 06:08:03 PM PDT 24
Peak memory 215276 kb
Host smart-f79a1623-0bb4-4bef-b5a9-bf1771061d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265242416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3265242416
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.495530616
Short name T636
Test name
Test status
Simulation time 501718628 ps
CPU time 3.53 seconds
Started Aug 05 06:08:04 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 215204 kb
Host smart-83e57fd4-25e6-4c48-92e4-b859ccb094f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495530616 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.495530616
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1468639147
Short name T572
Test name
Test status
Simulation time 264893983348 ps
CPU time 738.06 seconds
Started Aug 05 06:08:01 PM PDT 24
Finished Aug 05 06:20:20 PM PDT 24
Peak memory 223696 kb
Host smart-eae83f95-921a-4b4b-b186-790cb10fd928
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468639147 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1468639147
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1450296135
Short name T813
Test name
Test status
Simulation time 46639055 ps
CPU time 1.4 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:28 PM PDT 24
Peak memory 218832 kb
Host smart-f1108e61-9adc-4eec-9bd5-e4b1760ec1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450296135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1450296135
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1260021931
Short name T798
Test name
Test status
Simulation time 103477987 ps
CPU time 2.36 seconds
Started Aug 05 06:09:33 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 218612 kb
Host smart-dd426f64-6317-46e9-b572-4a48e46479f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260021931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1260021931
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2773119617
Short name T316
Test name
Test status
Simulation time 43273841 ps
CPU time 1.53 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 218544 kb
Host smart-731dbc1a-58a7-4a39-a557-5c63f9ef384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773119617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2773119617
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1612796921
Short name T843
Test name
Test status
Simulation time 42509325 ps
CPU time 1.18 seconds
Started Aug 05 06:09:52 PM PDT 24
Finished Aug 05 06:09:53 PM PDT 24
Peak memory 218668 kb
Host smart-be2c0d90-bf2e-459e-89d5-7e85d3b55780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612796921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1612796921
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1665873879
Short name T36
Test name
Test status
Simulation time 146045651 ps
CPU time 3.34 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 217588 kb
Host smart-1c0c07c1-853d-4030-8209-cc5ae74c1edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665873879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1665873879
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.646376357
Short name T472
Test name
Test status
Simulation time 39303189 ps
CPU time 1.26 seconds
Started Aug 05 06:09:36 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 217172 kb
Host smart-c04a0a9f-c757-4fde-8d0d-545ceffd3c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646376357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.646376357
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1798593770
Short name T369
Test name
Test status
Simulation time 48542507 ps
CPU time 1.84 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 218448 kb
Host smart-1d24326d-4df8-4bff-959c-ef59d1e9656b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798593770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1798593770
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1283809761
Short name T509
Test name
Test status
Simulation time 63409012 ps
CPU time 1.46 seconds
Started Aug 05 06:09:56 PM PDT 24
Finished Aug 05 06:09:58 PM PDT 24
Peak memory 220072 kb
Host smart-1f8a37a0-6dbf-43c5-949e-2dfc1279ee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283809761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1283809761
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1518018409
Short name T334
Test name
Test status
Simulation time 73721558 ps
CPU time 1.35 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 218824 kb
Host smart-ff963bc1-acb3-4d7f-8688-ad4baf8fc125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518018409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1518018409
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.160796842
Short name T343
Test name
Test status
Simulation time 49938925 ps
CPU time 1.29 seconds
Started Aug 05 06:09:36 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 218284 kb
Host smart-1875713d-96cf-462b-a2d6-77caf9402f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160796842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.160796842
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3638227406
Short name T861
Test name
Test status
Simulation time 24803824 ps
CPU time 1.19 seconds
Started Aug 05 06:08:06 PM PDT 24
Finished Aug 05 06:08:07 PM PDT 24
Peak memory 218720 kb
Host smart-40b25766-9777-4601-8595-36f04db4e506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638227406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3638227406
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2288321844
Short name T420
Test name
Test status
Simulation time 26544671 ps
CPU time 0.86 seconds
Started Aug 05 06:07:59 PM PDT 24
Finished Aug 05 06:08:00 PM PDT 24
Peak memory 206632 kb
Host smart-aa09dbd9-3269-49d8-a0d9-b19288c5a46c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288321844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2288321844
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3887998247
Short name T190
Test name
Test status
Simulation time 12127483 ps
CPU time 0.95 seconds
Started Aug 05 06:08:11 PM PDT 24
Finished Aug 05 06:08:12 PM PDT 24
Peak memory 215580 kb
Host smart-c3e65ee5-1808-4ac2-acba-3b4338bb694f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887998247 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3887998247
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3143986311
Short name T210
Test name
Test status
Simulation time 58207855 ps
CPU time 1.2 seconds
Started Aug 05 06:08:15 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 216860 kb
Host smart-69451f5e-afe1-43e8-a9cc-f1d25774ad46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143986311 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3143986311
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.255656731
Short name T45
Test name
Test status
Simulation time 28113840 ps
CPU time 1.37 seconds
Started Aug 05 06:08:13 PM PDT 24
Finished Aug 05 06:08:15 PM PDT 24
Peak memory 225944 kb
Host smart-e921ae76-3e43-4a56-a4bb-089abdeaa33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255656731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.255656731
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3536343464
Short name T927
Test name
Test status
Simulation time 40403721 ps
CPU time 1.34 seconds
Started Aug 05 06:08:11 PM PDT 24
Finished Aug 05 06:08:13 PM PDT 24
Peak memory 218600 kb
Host smart-74b03875-5775-4b9f-b688-50bee7a67b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536343464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3536343464
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1176908564
Short name T440
Test name
Test status
Simulation time 32703471 ps
CPU time 0.92 seconds
Started Aug 05 06:08:03 PM PDT 24
Finished Aug 05 06:08:04 PM PDT 24
Peak memory 215520 kb
Host smart-9dc2733b-997f-432c-b645-a4ea5036f5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176908564 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1176908564
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.699885590
Short name T468
Test name
Test status
Simulation time 28419197 ps
CPU time 0.92 seconds
Started Aug 05 06:08:09 PM PDT 24
Finished Aug 05 06:08:10 PM PDT 24
Peak memory 215292 kb
Host smart-13fcc417-bbe3-4575-b5fa-093c4f49fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699885590 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.699885590
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2110256800
Short name T40
Test name
Test status
Simulation time 264531626 ps
CPU time 3.15 seconds
Started Aug 05 06:08:06 PM PDT 24
Finished Aug 05 06:08:09 PM PDT 24
Peak memory 217092 kb
Host smart-01e710f9-5266-4818-b45d-c6386a423841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110256800 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2110256800
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2864901438
Short name T226
Test name
Test status
Simulation time 330392300259 ps
CPU time 2108.17 seconds
Started Aug 05 06:08:11 PM PDT 24
Finished Aug 05 06:43:20 PM PDT 24
Peak memory 229660 kb
Host smart-224bd6b6-c77a-45ad-a945-76bfa71dc0d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864901438 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2864901438
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2173872154
Short name T284
Test name
Test status
Simulation time 68695068 ps
CPU time 1.22 seconds
Started Aug 05 06:09:30 PM PDT 24
Finished Aug 05 06:09:31 PM PDT 24
Peak memory 218820 kb
Host smart-b5a5bab5-de27-4fd1-ad8c-2f8b48671d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173872154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2173872154
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1439792854
Short name T902
Test name
Test status
Simulation time 66207587 ps
CPU time 1.34 seconds
Started Aug 05 06:09:33 PM PDT 24
Finished Aug 05 06:09:34 PM PDT 24
Peak memory 219912 kb
Host smart-a548381b-3718-4ded-90b2-efa97874e416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439792854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1439792854
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2367757078
Short name T700
Test name
Test status
Simulation time 162623636 ps
CPU time 1.46 seconds
Started Aug 05 06:09:34 PM PDT 24
Finished Aug 05 06:09:36 PM PDT 24
Peak memory 218712 kb
Host smart-4137104b-1ddb-4f58-9d36-1862e5feda18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367757078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2367757078
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2788755952
Short name T795
Test name
Test status
Simulation time 133497582 ps
CPU time 1.1 seconds
Started Aug 05 06:09:32 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 217208 kb
Host smart-55ab7526-dcab-4f97-8186-c867bca7ea47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788755952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2788755952
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.4214875118
Short name T646
Test name
Test status
Simulation time 53167065 ps
CPU time 1.52 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:32 PM PDT 24
Peak memory 218512 kb
Host smart-5a523c77-70b9-49e6-b552-227ba2210cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214875118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.4214875118
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3036443351
Short name T362
Test name
Test status
Simulation time 54248484 ps
CPU time 1.29 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 217172 kb
Host smart-ce89862a-0eb8-4ba0-b1ec-aafc192cc6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036443351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3036443351
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.452644888
Short name T11
Test name
Test status
Simulation time 63702861 ps
CPU time 1.33 seconds
Started Aug 05 06:09:37 PM PDT 24
Finished Aug 05 06:09:39 PM PDT 24
Peak memory 220032 kb
Host smart-ad5dbfa2-63be-46bb-9ef1-0d18789858f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452644888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.452644888
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3322771816
Short name T373
Test name
Test status
Simulation time 127898168 ps
CPU time 1.34 seconds
Started Aug 05 06:09:36 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 218760 kb
Host smart-7be733e6-b063-4760-bb33-43866325c85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322771816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3322771816
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1496129061
Short name T340
Test name
Test status
Simulation time 39061837 ps
CPU time 1.49 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:36 PM PDT 24
Peak memory 218524 kb
Host smart-e0918fe3-900b-4676-867f-2cc03fe7538b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496129061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1496129061
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2729694794
Short name T357
Test name
Test status
Simulation time 46156442 ps
CPU time 1.45 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:36 PM PDT 24
Peak memory 218296 kb
Host smart-c1e8a521-71dc-4e51-8185-e9198781f07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729694794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2729694794
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.2048911785
Short name T353
Test name
Test status
Simulation time 12432735 ps
CPU time 0.88 seconds
Started Aug 05 06:08:14 PM PDT 24
Finished Aug 05 06:08:15 PM PDT 24
Peak memory 206944 kb
Host smart-7c38107e-ea76-46de-9904-31e6b38564b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048911785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2048911785
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2448809076
Short name T820
Test name
Test status
Simulation time 11254110 ps
CPU time 0.88 seconds
Started Aug 05 06:08:07 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 216212 kb
Host smart-5a883a38-2310-4994-8d40-5d7c337a36f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448809076 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2448809076
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2682039736
Short name T18
Test name
Test status
Simulation time 28485973 ps
CPU time 1.22 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 218752 kb
Host smart-950700d4-9db5-4df4-9664-d2b890e3da47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682039736 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2682039736
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3287510745
Short name T707
Test name
Test status
Simulation time 23556723 ps
CPU time 1 seconds
Started Aug 05 06:08:13 PM PDT 24
Finished Aug 05 06:08:14 PM PDT 24
Peak memory 218244 kb
Host smart-17eae1b8-9997-4c17-9471-c722f680a1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287510745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3287510745
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1013715059
Short name T475
Test name
Test status
Simulation time 49906950 ps
CPU time 1.86 seconds
Started Aug 05 06:08:11 PM PDT 24
Finished Aug 05 06:08:12 PM PDT 24
Peak memory 218636 kb
Host smart-1ba64cbc-ce28-4abb-8d94-3be52723b167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013715059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1013715059
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1442625532
Short name T530
Test name
Test status
Simulation time 43079208 ps
CPU time 0.98 seconds
Started Aug 05 06:08:07 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 224020 kb
Host smart-1023fde7-e8a7-42f5-acb4-277e48cb329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442625532 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1442625532
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.4131607464
Short name T810
Test name
Test status
Simulation time 18540675 ps
CPU time 1.01 seconds
Started Aug 05 06:08:11 PM PDT 24
Finished Aug 05 06:08:13 PM PDT 24
Peak memory 207084 kb
Host smart-69015352-b7b0-4da7-af22-980056543dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131607464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.4131607464
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1170850290
Short name T447
Test name
Test status
Simulation time 152966610 ps
CPU time 3.5 seconds
Started Aug 05 06:08:24 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 218488 kb
Host smart-7bb46220-98b8-474e-b105-673c668f91dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170850290 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1170850290
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3579038547
Short name T481
Test name
Test status
Simulation time 23326007473 ps
CPU time 385.02 seconds
Started Aug 05 06:08:08 PM PDT 24
Finished Aug 05 06:14:33 PM PDT 24
Peak memory 217964 kb
Host smart-25bc4dda-4669-4d53-9e51-94e04a326fbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579038547 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3579038547
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.124289673
Short name T325
Test name
Test status
Simulation time 41862517 ps
CPU time 1.78 seconds
Started Aug 05 06:09:33 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 218512 kb
Host smart-a99de510-cfec-4c6e-95a3-972e19f4fa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124289673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.124289673
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.269252551
Short name T981
Test name
Test status
Simulation time 54835013 ps
CPU time 1.27 seconds
Started Aug 05 06:09:36 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 218820 kb
Host smart-98e91d2e-17fe-4b93-afcb-9310aaccf6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269252551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.269252551
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2064927265
Short name T31
Test name
Test status
Simulation time 34961788 ps
CPU time 1.39 seconds
Started Aug 05 06:09:39 PM PDT 24
Finished Aug 05 06:09:40 PM PDT 24
Peak memory 217644 kb
Host smart-bd88c649-9287-4fa9-9ca7-38663fced30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064927265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2064927265
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3049408166
Short name T327
Test name
Test status
Simulation time 38089987 ps
CPU time 1.29 seconds
Started Aug 05 06:09:31 PM PDT 24
Finished Aug 05 06:09:33 PM PDT 24
Peak memory 217156 kb
Host smart-d458fef7-c491-44f7-9660-ec545a8f9022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049408166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3049408166
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1300263851
Short name T851
Test name
Test status
Simulation time 80415975 ps
CPU time 1.32 seconds
Started Aug 05 06:09:29 PM PDT 24
Finished Aug 05 06:09:30 PM PDT 24
Peak memory 217436 kb
Host smart-60310ca0-2ec6-4d89-a1c7-2ffde59811c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300263851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1300263851
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3458621826
Short name T376
Test name
Test status
Simulation time 91597504 ps
CPU time 1.21 seconds
Started Aug 05 06:09:36 PM PDT 24
Finished Aug 05 06:09:38 PM PDT 24
Peak memory 217320 kb
Host smart-c560f612-95de-4c23-839d-977b60900ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458621826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3458621826
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2402507619
Short name T310
Test name
Test status
Simulation time 28708813 ps
CPU time 1.29 seconds
Started Aug 05 06:09:34 PM PDT 24
Finished Aug 05 06:09:35 PM PDT 24
Peak memory 218612 kb
Host smart-a1e5ccf4-a958-474b-8f11-74c32ef39c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402507619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2402507619
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1988497779
Short name T419
Test name
Test status
Simulation time 361929943 ps
CPU time 4.53 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:40 PM PDT 24
Peak memory 220188 kb
Host smart-a7a9a6e2-6d9a-4a7f-95d5-5981d78085ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988497779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1988497779
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3369616379
Short name T433
Test name
Test status
Simulation time 41687800 ps
CPU time 1.74 seconds
Started Aug 05 06:09:40 PM PDT 24
Finished Aug 05 06:09:42 PM PDT 24
Peak memory 218564 kb
Host smart-b5327eca-3371-4fc6-96d2-84d214629f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369616379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3369616379
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.4292154986
Short name T389
Test name
Test status
Simulation time 49773344 ps
CPU time 1.59 seconds
Started Aug 05 06:09:54 PM PDT 24
Finished Aug 05 06:09:56 PM PDT 24
Peak memory 218488 kb
Host smart-d7d782d0-e400-4b3b-9e95-377fb1880c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292154986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.4292154986
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3084147187
Short name T180
Test name
Test status
Simulation time 75560432 ps
CPU time 1.09 seconds
Started Aug 05 06:08:22 PM PDT 24
Finished Aug 05 06:08:23 PM PDT 24
Peak memory 219312 kb
Host smart-8b9fb91a-03d7-4013-8c2e-03ce777ff501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084147187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3084147187
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2126749388
Short name T465
Test name
Test status
Simulation time 90128966 ps
CPU time 0.99 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 206728 kb
Host smart-59969ca8-f517-41e7-b40a-32b4a0371132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126749388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2126749388
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2962351647
Short name T19
Test name
Test status
Simulation time 45497960 ps
CPU time 1.05 seconds
Started Aug 05 06:08:17 PM PDT 24
Finished Aug 05 06:08:18 PM PDT 24
Peak memory 218408 kb
Host smart-a721edb9-1431-4c2d-95df-cac48082f21a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962351647 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2962351647
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.345096285
Short name T388
Test name
Test status
Simulation time 26871519 ps
CPU time 0.91 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 218384 kb
Host smart-42228128-56e7-4954-8037-633f718c7ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345096285 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.345096285
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.730621399
Short name T946
Test name
Test status
Simulation time 56127859 ps
CPU time 1.26 seconds
Started Aug 05 06:08:20 PM PDT 24
Finished Aug 05 06:08:22 PM PDT 24
Peak memory 218644 kb
Host smart-e1eac2a2-7980-4e6e-b0d7-d821f1b17d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730621399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.730621399
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.4186213493
Short name T803
Test name
Test status
Simulation time 44937877 ps
CPU time 0.86 seconds
Started Aug 05 06:08:12 PM PDT 24
Finished Aug 05 06:08:13 PM PDT 24
Peak memory 215148 kb
Host smart-ada3cbe9-8a5c-49a0-b398-9cdf669a1ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186213493 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4186213493
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.494154938
Short name T471
Test name
Test status
Simulation time 97042197 ps
CPU time 0.97 seconds
Started Aug 05 06:08:11 PM PDT 24
Finished Aug 05 06:08:12 PM PDT 24
Peak memory 215284 kb
Host smart-c2b6b0b1-eea1-45cb-b4db-ae34e7696daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494154938 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.494154938
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.21932338
Short name T443
Test name
Test status
Simulation time 188897246 ps
CPU time 1.63 seconds
Started Aug 05 06:08:12 PM PDT 24
Finished Aug 05 06:08:14 PM PDT 24
Peak memory 219960 kb
Host smart-6da76d4a-a7a6-49ed-869f-df0915d72927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21932338 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.21932338
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3686671657
Short name T408
Test name
Test status
Simulation time 21537474729 ps
CPU time 237.81 seconds
Started Aug 05 06:08:14 PM PDT 24
Finished Aug 05 06:12:12 PM PDT 24
Peak memory 223008 kb
Host smart-74292b74-f721-4af6-bd69-bce6fd64fc8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686671657 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3686671657
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/291.edn_genbits.135573928
Short name T595
Test name
Test status
Simulation time 57683530 ps
CPU time 1.99 seconds
Started Aug 05 06:09:35 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 220140 kb
Host smart-03b37956-645e-4d8c-9aae-7289b82da032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135573928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.135573928
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2831449250
Short name T28
Test name
Test status
Simulation time 31695568 ps
CPU time 1.35 seconds
Started Aug 05 06:09:41 PM PDT 24
Finished Aug 05 06:09:43 PM PDT 24
Peak memory 217248 kb
Host smart-6d9700d4-6bb7-4029-b3ad-40a722a636ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831449250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2831449250
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2607740054
Short name T544
Test name
Test status
Simulation time 69826238 ps
CPU time 1.05 seconds
Started Aug 05 06:09:47 PM PDT 24
Finished Aug 05 06:09:48 PM PDT 24
Peak memory 217360 kb
Host smart-7ca1b48c-4161-4616-be8d-0b79f6f5fb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607740054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2607740054
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2072821306
Short name T240
Test name
Test status
Simulation time 106138405 ps
CPU time 1.24 seconds
Started Aug 05 06:09:44 PM PDT 24
Finished Aug 05 06:09:46 PM PDT 24
Peak memory 218964 kb
Host smart-afb37a04-4cf4-469e-9047-ea27bf36c034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072821306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2072821306
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3945317614
Short name T396
Test name
Test status
Simulation time 496672891 ps
CPU time 3.79 seconds
Started Aug 05 06:10:05 PM PDT 24
Finished Aug 05 06:10:09 PM PDT 24
Peak memory 218972 kb
Host smart-27cedf42-559a-45ef-996d-1a364295b65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945317614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3945317614
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.725755779
Short name T305
Test name
Test status
Simulation time 34658179 ps
CPU time 1.24 seconds
Started Aug 05 06:09:54 PM PDT 24
Finished Aug 05 06:09:56 PM PDT 24
Peak memory 219892 kb
Host smart-b1738e48-0911-4568-8e52-2fd53fff24f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725755779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.725755779
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3067466111
Short name T732
Test name
Test status
Simulation time 39552402 ps
CPU time 1.03 seconds
Started Aug 05 06:09:49 PM PDT 24
Finished Aug 05 06:09:51 PM PDT 24
Peak memory 217260 kb
Host smart-913780f9-f01c-43d9-aebd-f8880ec68234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067466111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3067466111
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2927434858
Short name T398
Test name
Test status
Simulation time 51268563 ps
CPU time 1.15 seconds
Started Aug 05 06:09:38 PM PDT 24
Finished Aug 05 06:09:39 PM PDT 24
Peak memory 218368 kb
Host smart-71d7b197-8be2-4b65-9805-93d49d387517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927434858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2927434858
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2725267740
Short name T826
Test name
Test status
Simulation time 131816364 ps
CPU time 2.51 seconds
Started Aug 05 06:09:36 PM PDT 24
Finished Aug 05 06:09:39 PM PDT 24
Peak memory 219884 kb
Host smart-83a5b9e5-a51c-4411-840a-53c4ee30034c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725267740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2725267740
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3766807072
Short name T741
Test name
Test status
Simulation time 23872544 ps
CPU time 1.16 seconds
Started Aug 05 06:07:28 PM PDT 24
Finished Aug 05 06:07:30 PM PDT 24
Peak memory 219680 kb
Host smart-7cce6b02-62eb-4894-aa2b-7bccbc4acea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766807072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3766807072
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3363024758
Short name T482
Test name
Test status
Simulation time 46446613 ps
CPU time 0.84 seconds
Started Aug 05 06:07:29 PM PDT 24
Finished Aug 05 06:07:30 PM PDT 24
Peak memory 206728 kb
Host smart-0690ab40-a180-43c0-8a55-7aec841e403b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363024758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3363024758
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3742707403
Short name T589
Test name
Test status
Simulation time 41716453 ps
CPU time 0.9 seconds
Started Aug 05 06:07:35 PM PDT 24
Finished Aug 05 06:07:36 PM PDT 24
Peak memory 216248 kb
Host smart-f2a973f2-2c27-4a3a-8892-57e980ae8af5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742707403 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3742707403
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2271351893
Short name T244
Test name
Test status
Simulation time 50869319 ps
CPU time 1.09 seconds
Started Aug 05 06:07:33 PM PDT 24
Finished Aug 05 06:07:34 PM PDT 24
Peak memory 219880 kb
Host smart-6716a39d-aedb-45bb-88e8-52c266749b4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271351893 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2271351893
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.861153553
Short name T555
Test name
Test status
Simulation time 51273196 ps
CPU time 0.93 seconds
Started Aug 05 06:07:31 PM PDT 24
Finished Aug 05 06:07:32 PM PDT 24
Peak memory 219836 kb
Host smart-845ddea9-55f3-4cfb-851a-eb3c7a206183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861153553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.861153553
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2700073682
Short name T675
Test name
Test status
Simulation time 78314578 ps
CPU time 1.1 seconds
Started Aug 05 06:07:34 PM PDT 24
Finished Aug 05 06:07:36 PM PDT 24
Peak memory 217320 kb
Host smart-8c3c2ab7-208d-4fbc-9e67-4e941db14235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700073682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2700073682
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.249585208
Short name T973
Test name
Test status
Simulation time 31940389 ps
CPU time 0.86 seconds
Started Aug 05 06:07:26 PM PDT 24
Finished Aug 05 06:07:27 PM PDT 24
Peak memory 215448 kb
Host smart-83fcb39e-2bbe-490e-a4b0-3c5e0cb604b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249585208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.249585208
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1034373665
Short name T643
Test name
Test status
Simulation time 26088306 ps
CPU time 0.91 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 207108 kb
Host smart-820aa361-0141-4257-805c-25911ff5de20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034373665 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1034373665
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.3423766922
Short name T414
Test name
Test status
Simulation time 26377261 ps
CPU time 0.97 seconds
Started Aug 05 06:07:28 PM PDT 24
Finished Aug 05 06:07:29 PM PDT 24
Peak memory 215308 kb
Host smart-52ca191a-83e7-4b92-b1ad-24345e488d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423766922 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3423766922
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3691949205
Short name T935
Test name
Test status
Simulation time 805604269 ps
CPU time 4.69 seconds
Started Aug 05 06:07:24 PM PDT 24
Finished Aug 05 06:07:29 PM PDT 24
Peak memory 215276 kb
Host smart-14a8cfec-d4d7-44a2-84f0-a7b656c4da6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691949205 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3691949205
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3826884774
Short name T524
Test name
Test status
Simulation time 43635608904 ps
CPU time 989.93 seconds
Started Aug 05 06:07:39 PM PDT 24
Finished Aug 05 06:24:09 PM PDT 24
Peak memory 218824 kb
Host smart-9969e213-a274-4b6d-b697-06714fddb77b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826884774 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3826884774
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1181044625
Short name T139
Test name
Test status
Simulation time 36579415 ps
CPU time 1.23 seconds
Started Aug 05 06:08:10 PM PDT 24
Finished Aug 05 06:08:12 PM PDT 24
Peak memory 218920 kb
Host smart-d9132d47-67c0-4170-97ac-8afb97ccca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181044625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1181044625
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1456372606
Short name T658
Test name
Test status
Simulation time 59202718 ps
CPU time 0.95 seconds
Started Aug 05 06:08:18 PM PDT 24
Finished Aug 05 06:08:19 PM PDT 24
Peak memory 214872 kb
Host smart-24b8a517-1cff-4599-80a3-28eb70acf6bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456372606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1456372606
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1066554815
Short name T966
Test name
Test status
Simulation time 10895847 ps
CPU time 0.87 seconds
Started Aug 05 06:08:12 PM PDT 24
Finished Aug 05 06:08:13 PM PDT 24
Peak memory 216308 kb
Host smart-1e6eb089-41fa-44a3-9edd-0667be9b949e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066554815 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1066554815
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1593505978
Short name T894
Test name
Test status
Simulation time 40680333 ps
CPU time 1.27 seconds
Started Aug 05 06:08:13 PM PDT 24
Finished Aug 05 06:08:15 PM PDT 24
Peak memory 216864 kb
Host smart-01e5e912-d0a9-4943-8349-a23695b8f709
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593505978 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1593505978
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_genbits.899071607
Short name T450
Test name
Test status
Simulation time 231945652 ps
CPU time 3.22 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:08:19 PM PDT 24
Peak memory 220100 kb
Host smart-70518ff0-cfe0-4f18-8bf5-77cc9b545c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899071607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.899071607
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_smoke.1642054535
Short name T917
Test name
Test status
Simulation time 17100101 ps
CPU time 1.01 seconds
Started Aug 05 06:08:14 PM PDT 24
Finished Aug 05 06:08:15 PM PDT 24
Peak memory 215276 kb
Host smart-a0154a8e-1370-4875-b02e-8f0c95223236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642054535 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1642054535
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.256807590
Short name T875
Test name
Test status
Simulation time 266636422 ps
CPU time 1.63 seconds
Started Aug 05 06:08:20 PM PDT 24
Finished Aug 05 06:08:21 PM PDT 24
Peak memory 217208 kb
Host smart-84bbb1c1-9ac0-406b-8898-cc22eb2a5554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256807590 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.256807590
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3326479860
Short name T897
Test name
Test status
Simulation time 115581382631 ps
CPU time 668.37 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:19:25 PM PDT 24
Peak memory 223704 kb
Host smart-d0b4c323-bd85-467a-8493-a1115fb2b313
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326479860 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3326479860
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1923203755
Short name T152
Test name
Test status
Simulation time 67853424 ps
CPU time 1.06 seconds
Started Aug 05 06:08:12 PM PDT 24
Finished Aug 05 06:08:13 PM PDT 24
Peak memory 218760 kb
Host smart-2907e862-7511-4d12-bc8f-4c286d1b41fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923203755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1923203755
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2335384176
Short name T399
Test name
Test status
Simulation time 31460134 ps
CPU time 0.96 seconds
Started Aug 05 06:08:18 PM PDT 24
Finished Aug 05 06:08:19 PM PDT 24
Peak memory 206688 kb
Host smart-30d19227-91f2-48aa-8c5c-b6e90b041281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335384176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2335384176
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3050622331
Short name T948
Test name
Test status
Simulation time 10185986 ps
CPU time 0.86 seconds
Started Aug 05 06:08:09 PM PDT 24
Finished Aug 05 06:08:10 PM PDT 24
Peak memory 216224 kb
Host smart-7c58308e-9210-479c-8913-e36fae258463
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050622331 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3050622331
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3260921299
Short name T367
Test name
Test status
Simulation time 48834434 ps
CPU time 1.17 seconds
Started Aug 05 06:08:07 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 216800 kb
Host smart-d4cad383-c234-43b7-ac2d-bf9db9c893e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260921299 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3260921299
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1233918356
Short name T101
Test name
Test status
Simulation time 37699151 ps
CPU time 1.05 seconds
Started Aug 05 06:08:17 PM PDT 24
Finished Aug 05 06:08:18 PM PDT 24
Peak memory 220548 kb
Host smart-a6a228a9-c63b-4a19-9f2b-fe0228cda532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233918356 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1233918356
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.853701446
Short name T853
Test name
Test status
Simulation time 37561302 ps
CPU time 1.06 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 217236 kb
Host smart-67d09217-db13-48e8-b6d3-f05d6ae1dbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853701446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.853701446
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.4293783369
Short name T758
Test name
Test status
Simulation time 93183335 ps
CPU time 0.86 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 215524 kb
Host smart-a494feef-ce6d-4e0e-872a-f99647135e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293783369 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.4293783369
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1903986594
Short name T804
Test name
Test status
Simulation time 33938870 ps
CPU time 0.98 seconds
Started Aug 05 06:08:14 PM PDT 24
Finished Aug 05 06:08:15 PM PDT 24
Peak memory 215276 kb
Host smart-d6db15ec-cbda-4451-bff8-b18ccaec4bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903986594 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1903986594
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.14357457
Short name T730
Test name
Test status
Simulation time 86589969 ps
CPU time 2.11 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:08:19 PM PDT 24
Peak memory 217136 kb
Host smart-37cafdef-74d9-4a1c-a119-dbe501100b39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14357457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.14357457
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3986140046
Short name T637
Test name
Test status
Simulation time 135715237651 ps
CPU time 895.43 seconds
Started Aug 05 06:08:23 PM PDT 24
Finished Aug 05 06:23:19 PM PDT 24
Peak memory 223636 kb
Host smart-5b44f131-9a74-4ee8-989e-5eb8a3c4bd05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986140046 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3986140046
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3951701001
Short name T551
Test name
Test status
Simulation time 25586125 ps
CPU time 1.2 seconds
Started Aug 05 06:08:18 PM PDT 24
Finished Aug 05 06:08:19 PM PDT 24
Peak memory 220860 kb
Host smart-5f811d62-9abf-48bb-b52a-ef4221af38c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951701001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3951701001
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2662245337
Short name T567
Test name
Test status
Simulation time 14020147 ps
CPU time 0.94 seconds
Started Aug 05 06:08:25 PM PDT 24
Finished Aug 05 06:08:26 PM PDT 24
Peak memory 206696 kb
Host smart-4bd1cb21-34e6-4f6c-8176-7a6196e40b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662245337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2662245337
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1116143244
Short name T939
Test name
Test status
Simulation time 29234159 ps
CPU time 1.12 seconds
Started Aug 05 06:08:23 PM PDT 24
Finished Aug 05 06:08:24 PM PDT 24
Peak memory 218352 kb
Host smart-036e3528-b71f-423f-b589-bad3e77b5fc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116143244 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1116143244
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2387046085
Short name T382
Test name
Test status
Simulation time 24665822 ps
CPU time 1.16 seconds
Started Aug 05 06:08:08 PM PDT 24
Finished Aug 05 06:08:09 PM PDT 24
Peak memory 218596 kb
Host smart-0a21f0bf-15b3-468f-920c-814b67c88dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387046085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2387046085
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1890644123
Short name T987
Test name
Test status
Simulation time 34951898 ps
CPU time 1.3 seconds
Started Aug 05 06:08:19 PM PDT 24
Finished Aug 05 06:08:21 PM PDT 24
Peak memory 217196 kb
Host smart-c6d9963e-f7f9-4e30-ac66-e5eef4542f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890644123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1890644123
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1032996333
Short name T85
Test name
Test status
Simulation time 24393717 ps
CPU time 0.93 seconds
Started Aug 05 06:08:07 PM PDT 24
Finished Aug 05 06:08:08 PM PDT 24
Peak memory 215872 kb
Host smart-8c25272e-2e9f-4d37-98f7-1e58c0790130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032996333 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1032996333
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.4162515836
Short name T954
Test name
Test status
Simulation time 18584281 ps
CPU time 1.05 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 215360 kb
Host smart-972d6605-6d8a-4928-8574-b056c910fda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162515836 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.4162515836
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.825306749
Short name T919
Test name
Test status
Simulation time 824991669 ps
CPU time 4.83 seconds
Started Aug 05 06:08:29 PM PDT 24
Finished Aug 05 06:08:34 PM PDT 24
Peak memory 218468 kb
Host smart-b87b2c5c-b29d-4401-820a-fb8d313e3087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825306749 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.825306749
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1026731626
Short name T227
Test name
Test status
Simulation time 66328514300 ps
CPU time 801.69 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:21:38 PM PDT 24
Peak memory 220536 kb
Host smart-73ee40aa-cc27-40d5-a41a-5675696e9078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026731626 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1026731626
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3850742783
Short name T870
Test name
Test status
Simulation time 29135183 ps
CPU time 1.33 seconds
Started Aug 05 06:08:17 PM PDT 24
Finished Aug 05 06:08:18 PM PDT 24
Peak memory 215672 kb
Host smart-dd07ab62-f6d4-4f8b-bd31-ee56fca29526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850742783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3850742783
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3507013049
Short name T674
Test name
Test status
Simulation time 23807183 ps
CPU time 0.89 seconds
Started Aug 05 06:08:29 PM PDT 24
Finished Aug 05 06:08:30 PM PDT 24
Peak memory 206684 kb
Host smart-d4f2c805-86ec-4ed8-9b3a-50a3fc32c78c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507013049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3507013049
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.4132120533
Short name T695
Test name
Test status
Simulation time 21379977 ps
CPU time 0.86 seconds
Started Aug 05 06:08:33 PM PDT 24
Finished Aug 05 06:08:34 PM PDT 24
Peak memory 216228 kb
Host smart-86a7be6c-a35f-416c-8d25-90a79624d0a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132120533 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.4132120533
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1312045419
Short name T967
Test name
Test status
Simulation time 46150898 ps
CPU time 1.49 seconds
Started Aug 05 06:08:19 PM PDT 24
Finished Aug 05 06:08:21 PM PDT 24
Peak memory 216964 kb
Host smart-e2c6732e-e93c-40d2-99c9-09067dac94cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312045419 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1312045419
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2871100171
Short name T195
Test name
Test status
Simulation time 24930251 ps
CPU time 0.89 seconds
Started Aug 05 06:08:28 PM PDT 24
Finished Aug 05 06:08:29 PM PDT 24
Peak memory 218572 kb
Host smart-9b1aedea-6c92-410c-83e5-c226083dbafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871100171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2871100171
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3570459460
Short name T596
Test name
Test status
Simulation time 56374164 ps
CPU time 1.36 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 218308 kb
Host smart-fce89887-b362-4ede-8b1e-cd45f5e4b5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570459460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3570459460
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3424484706
Short name T662
Test name
Test status
Simulation time 36548061 ps
CPU time 1.04 seconds
Started Aug 05 06:08:32 PM PDT 24
Finished Aug 05 06:08:33 PM PDT 24
Peak memory 224100 kb
Host smart-1f865ec9-6a8e-41d4-9834-0c60629e82d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424484706 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3424484706
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3003382276
Short name T879
Test name
Test status
Simulation time 23155412 ps
CPU time 0.91 seconds
Started Aug 05 06:08:15 PM PDT 24
Finished Aug 05 06:08:16 PM PDT 24
Peak memory 215292 kb
Host smart-aa1189ce-a2e8-4deb-b42d-dd9d0e125110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003382276 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3003382276
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.88673446
Short name T370
Test name
Test status
Simulation time 1635885441 ps
CPU time 4.34 seconds
Started Aug 05 06:08:14 PM PDT 24
Finished Aug 05 06:08:18 PM PDT 24
Peak memory 217472 kb
Host smart-0eb34441-f7d4-4fb3-b4a9-e2bc9e4b97e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88673446 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.88673446
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.1000989190
Short name T787
Test name
Test status
Simulation time 73472887 ps
CPU time 1.15 seconds
Started Aug 05 06:08:27 PM PDT 24
Finished Aug 05 06:08:28 PM PDT 24
Peak memory 218916 kb
Host smart-263c6853-101c-4ead-981e-46a5ea739a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000989190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1000989190
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1727754340
Short name T402
Test name
Test status
Simulation time 59214303 ps
CPU time 0.94 seconds
Started Aug 05 06:08:30 PM PDT 24
Finished Aug 05 06:08:31 PM PDT 24
Peak memory 215024 kb
Host smart-1188107b-568a-4d59-8a35-f867965c28f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727754340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1727754340
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3920119250
Short name T209
Test name
Test status
Simulation time 11612569 ps
CPU time 0.88 seconds
Started Aug 05 06:08:21 PM PDT 24
Finished Aug 05 06:08:22 PM PDT 24
Peak memory 216240 kb
Host smart-c1a3be3a-e3b3-4354-be5b-94865c49ee9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920119250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3920119250
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2347857442
Short name T716
Test name
Test status
Simulation time 79987164 ps
CPU time 1.1 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:28 PM PDT 24
Peak memory 215600 kb
Host smart-b6ed4b77-d098-4c0d-a91a-8ad90bc1c79d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347857442 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2347857442
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3846022980
Short name T141
Test name
Test status
Simulation time 18941446 ps
CPU time 1.11 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 218492 kb
Host smart-a268f880-92a2-4bfe-9178-569004b39d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846022980 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3846022980
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1399836934
Short name T505
Test name
Test status
Simulation time 38824431 ps
CPU time 1.63 seconds
Started Aug 05 06:08:29 PM PDT 24
Finished Aug 05 06:08:31 PM PDT 24
Peak memory 219896 kb
Host smart-e738e2cf-3f0d-4e34-9aac-a4bd6ce90bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399836934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1399836934
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2283995309
Short name T83
Test name
Test status
Simulation time 20723339 ps
CPU time 1.1 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 215888 kb
Host smart-ed36f633-448a-4412-b656-2962e31d7d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283995309 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2283995309
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3966060714
Short name T470
Test name
Test status
Simulation time 21301362 ps
CPU time 0.96 seconds
Started Aug 05 06:08:15 PM PDT 24
Finished Aug 05 06:08:16 PM PDT 24
Peak memory 215308 kb
Host smart-a856a1ec-c03a-45fa-8500-2d8c4ffad3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966060714 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3966060714
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.774471902
Short name T328
Test name
Test status
Simulation time 45156254460 ps
CPU time 1131.73 seconds
Started Aug 05 06:08:20 PM PDT 24
Finished Aug 05 06:27:12 PM PDT 24
Peak memory 223624 kb
Host smart-c2e8c796-08dc-41a9-871c-e7173fbdfbeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774471902 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.774471902
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2644373163
Short name T783
Test name
Test status
Simulation time 25401710 ps
CPU time 1.22 seconds
Started Aug 05 06:08:18 PM PDT 24
Finished Aug 05 06:08:19 PM PDT 24
Peak memory 218524 kb
Host smart-3b12cf77-a9ef-4bfc-8782-ff2b70906188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644373163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2644373163
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3605775256
Short name T349
Test name
Test status
Simulation time 233229355 ps
CPU time 0.93 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 214896 kb
Host smart-cc1b951f-4ed7-4ef2-aa97-c7f68deb26ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605775256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3605775256
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3881062099
Short name T893
Test name
Test status
Simulation time 22135016 ps
CPU time 0.88 seconds
Started Aug 05 06:08:23 PM PDT 24
Finished Aug 05 06:08:24 PM PDT 24
Peak memory 216008 kb
Host smart-ba558fe1-3245-4bee-81e9-1e0b3dcde0fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881062099 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3881062099
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3885587200
Short name T781
Test name
Test status
Simulation time 64011170 ps
CPU time 1.23 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 216944 kb
Host smart-725e661b-e9e9-4e43-b222-85157e335f82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885587200 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3885587200
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.316624229
Short name T549
Test name
Test status
Simulation time 26259334 ps
CPU time 0.98 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 223812 kb
Host smart-34e98cef-ea9e-4413-aa7f-99dfd1d949bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316624229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.316624229
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.60789185
Short name T901
Test name
Test status
Simulation time 64639689 ps
CPU time 1.58 seconds
Started Aug 05 06:08:32 PM PDT 24
Finished Aug 05 06:08:34 PM PDT 24
Peak memory 217388 kb
Host smart-316b928c-92c1-4ee4-b2f1-2c6e8a2c2d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60789185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.60789185
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2188451708
Short name T91
Test name
Test status
Simulation time 22723328 ps
CPU time 0.97 seconds
Started Aug 05 06:08:27 PM PDT 24
Finished Aug 05 06:08:28 PM PDT 24
Peak memory 215868 kb
Host smart-839d2602-50ce-409a-baf8-1ab9be2fbf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188451708 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2188451708
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3141714093
Short name T61
Test name
Test status
Simulation time 15846055 ps
CPU time 0.96 seconds
Started Aug 05 06:08:21 PM PDT 24
Finished Aug 05 06:08:22 PM PDT 24
Peak memory 215276 kb
Host smart-ca02398e-755c-4087-b3db-48b0d546c2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141714093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3141714093
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2616009608
Short name T606
Test name
Test status
Simulation time 919490586 ps
CPU time 2.2 seconds
Started Aug 05 06:08:33 PM PDT 24
Finished Aug 05 06:08:36 PM PDT 24
Peak memory 217468 kb
Host smart-d668162c-5ff4-402b-b4e9-02ccea1bd237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616009608 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2616009608
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3331301398
Short name T802
Test name
Test status
Simulation time 21488286480 ps
CPU time 120.92 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:10:37 PM PDT 24
Peak memory 220904 kb
Host smart-e6423786-7fc7-4b80-8598-df8ce37e1d1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331301398 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3331301398
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1237598791
Short name T527
Test name
Test status
Simulation time 51320983 ps
CPU time 1.21 seconds
Started Aug 05 06:08:22 PM PDT 24
Finished Aug 05 06:08:23 PM PDT 24
Peak memory 218720 kb
Host smart-98b2c7c5-6494-46b8-a098-60dc3eba33d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237598791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1237598791
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2474209304
Short name T498
Test name
Test status
Simulation time 36037111 ps
CPU time 0.97 seconds
Started Aug 05 06:08:20 PM PDT 24
Finished Aug 05 06:08:21 PM PDT 24
Peak memory 206832 kb
Host smart-aff31dd0-0157-40a1-8de7-e2ea6f3e87f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474209304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2474209304
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2197179141
Short name T186
Test name
Test status
Simulation time 22784678 ps
CPU time 0.9 seconds
Started Aug 05 06:08:37 PM PDT 24
Finished Aug 05 06:08:38 PM PDT 24
Peak memory 216356 kb
Host smart-8731746c-8741-4419-beba-69b88e23ece7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197179141 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2197179141
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.330998124
Short name T206
Test name
Test status
Simulation time 111486992 ps
CPU time 1.15 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:28 PM PDT 24
Peak memory 216808 kb
Host smart-e039e3bb-409e-4874-9818-f26719477b92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330998124 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.330998124
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.4027248393
Short name T204
Test name
Test status
Simulation time 24107103 ps
CPU time 0.91 seconds
Started Aug 05 06:08:32 PM PDT 24
Finished Aug 05 06:08:33 PM PDT 24
Peak memory 219300 kb
Host smart-0c7401ef-46c1-4298-8412-eeecd3ced47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027248393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.4027248393
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1281879784
Short name T518
Test name
Test status
Simulation time 159757919 ps
CPU time 1.55 seconds
Started Aug 05 06:08:24 PM PDT 24
Finished Aug 05 06:08:26 PM PDT 24
Peak memory 218812 kb
Host smart-18bf2a07-0080-49f0-b211-541406d5c211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281879784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1281879784
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.933286829
Short name T918
Test name
Test status
Simulation time 32654759 ps
CPU time 0.98 seconds
Started Aug 05 06:08:16 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 224020 kb
Host smart-b6fd6ff4-4e0a-4922-a3b4-16cf9713bb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933286829 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.933286829
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.4272688249
Short name T339
Test name
Test status
Simulation time 127403379 ps
CPU time 0.96 seconds
Started Aug 05 06:08:37 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 215288 kb
Host smart-4bc98663-4636-4f78-b7c2-42e366eeec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272688249 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.4272688249
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2114607106
Short name T429
Test name
Test status
Simulation time 224618422 ps
CPU time 4.57 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 217404 kb
Host smart-5b426498-4da9-4c97-942e-788bd26785d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114607106 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2114607106
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.907524297
Short name T238
Test name
Test status
Simulation time 69863516347 ps
CPU time 1500.39 seconds
Started Aug 05 06:08:15 PM PDT 24
Finished Aug 05 06:33:16 PM PDT 24
Peak memory 222620 kb
Host smart-04f4895d-dc5e-4184-a370-37211a6603a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907524297 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.907524297
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.914238639
Short name T151
Test name
Test status
Simulation time 40198132 ps
CPU time 1.09 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 220676 kb
Host smart-c8a53475-278b-4d79-9630-767985ea86d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914238639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.914238639
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2282887669
Short name T786
Test name
Test status
Simulation time 15153479 ps
CPU time 0.92 seconds
Started Aug 05 06:08:29 PM PDT 24
Finished Aug 05 06:08:30 PM PDT 24
Peak memory 206752 kb
Host smart-3b36a84e-94d9-4366-942d-95b7e8bed975
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282887669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2282887669
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2658879152
Short name T930
Test name
Test status
Simulation time 39733764 ps
CPU time 0.83 seconds
Started Aug 05 06:08:17 PM PDT 24
Finished Aug 05 06:08:18 PM PDT 24
Peak memory 216212 kb
Host smart-530debcf-14b7-495b-9c47-9920b5472284
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658879152 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2658879152
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3433585114
Short name T913
Test name
Test status
Simulation time 188859742 ps
CPU time 1.03 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:28 PM PDT 24
Peak memory 218452 kb
Host smart-7dbdf886-bae5-4141-8d6d-5e363ba7ecbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433585114 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3433585114
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.207712957
Short name T202
Test name
Test status
Simulation time 28492776 ps
CPU time 0.88 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 218220 kb
Host smart-63ea70ad-8323-473b-a1e2-9400ba0d4a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207712957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.207712957
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.531941994
Short name T580
Test name
Test status
Simulation time 31667423 ps
CPU time 1.42 seconds
Started Aug 05 06:08:27 PM PDT 24
Finished Aug 05 06:08:29 PM PDT 24
Peak memory 217472 kb
Host smart-808c5a17-4455-42fd-bfc0-8fa491678b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531941994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.531941994
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2483224997
Short name T752
Test name
Test status
Simulation time 118008948 ps
CPU time 0.93 seconds
Started Aug 05 06:08:33 PM PDT 24
Finished Aug 05 06:08:34 PM PDT 24
Peak memory 223848 kb
Host smart-320fee84-5ed3-4e87-9b0c-04622f3277d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483224997 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2483224997
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.49225723
Short name T699
Test name
Test status
Simulation time 46426596 ps
CPU time 0.9 seconds
Started Aug 05 06:08:33 PM PDT 24
Finished Aug 05 06:08:34 PM PDT 24
Peak memory 215312 kb
Host smart-aed3e023-6ebd-4c33-a980-c22a42925b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49225723 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.49225723
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3244738064
Short name T724
Test name
Test status
Simulation time 721464010 ps
CPU time 4.32 seconds
Started Aug 05 06:08:22 PM PDT 24
Finished Aug 05 06:08:26 PM PDT 24
Peak memory 217184 kb
Host smart-42bf50c4-2429-42f9-9175-ae705cd72663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244738064 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3244738064
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3663439874
Short name T703
Test name
Test status
Simulation time 85472066527 ps
CPU time 1040.56 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:25:47 PM PDT 24
Peak memory 224436 kb
Host smart-2d014340-3cda-4780-bdec-65956cfdf658
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663439874 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3663439874
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3498949556
Short name T876
Test name
Test status
Simulation time 47253190 ps
CPU time 1.24 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 219716 kb
Host smart-9998ac3e-dcf7-4487-879e-7485cbd2d638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498949556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3498949556
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3178152145
Short name T413
Test name
Test status
Simulation time 50291594 ps
CPU time 0.92 seconds
Started Aug 05 06:08:20 PM PDT 24
Finished Aug 05 06:08:21 PM PDT 24
Peak memory 206716 kb
Host smart-748201be-f6b7-4ce3-bcaf-968d60fbc39c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178152145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3178152145
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.4068469134
Short name T744
Test name
Test status
Simulation time 14358570 ps
CPU time 0.95 seconds
Started Aug 05 06:08:23 PM PDT 24
Finished Aug 05 06:08:24 PM PDT 24
Peak memory 216396 kb
Host smart-3d38e2ca-d336-460c-bbf1-8338ad366e1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068469134 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4068469134
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1864935117
Short name T132
Test name
Test status
Simulation time 26194281 ps
CPU time 1.12 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:08:38 PM PDT 24
Peak memory 216864 kb
Host smart-98fb5bec-ead1-42e6-9493-a8c682c9e910
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864935117 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1864935117
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3771311670
Short name T682
Test name
Test status
Simulation time 27026627 ps
CPU time 1.28 seconds
Started Aug 05 06:08:31 PM PDT 24
Finished Aug 05 06:08:32 PM PDT 24
Peak memory 220800 kb
Host smart-efe02374-a00f-4edd-94b5-cd705003cf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771311670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3771311670
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1817311391
Short name T314
Test name
Test status
Simulation time 155599798 ps
CPU time 1.83 seconds
Started Aug 05 06:08:37 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 218552 kb
Host smart-775edbc7-1064-49c7-bba8-d11bb5b63556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817311391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1817311391
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_smoke.171031858
Short name T495
Test name
Test status
Simulation time 28394881 ps
CPU time 0.93 seconds
Started Aug 05 06:08:33 PM PDT 24
Finished Aug 05 06:08:34 PM PDT 24
Peak memory 215276 kb
Host smart-8f24798c-3793-4046-b634-2307826c55c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171031858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.171031858
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1380032810
Short name T750
Test name
Test status
Simulation time 31340239 ps
CPU time 1.22 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 207192 kb
Host smart-21b26c0b-c351-49cc-8587-b104a42b2e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380032810 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1380032810
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.696011574
Short name T887
Test name
Test status
Simulation time 45291045747 ps
CPU time 1098.23 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:26:59 PM PDT 24
Peak memory 220844 kb
Host smart-0e670ac9-31fe-49b1-8454-4b9dbf732453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696011574 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.696011574
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert_test.1942601994
Short name T571
Test name
Test status
Simulation time 15926846 ps
CPU time 0.9 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 206716 kb
Host smart-4efc0cfb-c740-4fa7-a36c-a83b774fc853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942601994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1942601994
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3412279738
Short name T607
Test name
Test status
Simulation time 12178778 ps
CPU time 0.91 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 216568 kb
Host smart-1cefbfc1-39e1-4533-a4ef-e6ddda24049e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412279738 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3412279738
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2937095634
Short name T627
Test name
Test status
Simulation time 57766328 ps
CPU time 1.1 seconds
Started Aug 05 06:08:37 PM PDT 24
Finished Aug 05 06:08:38 PM PDT 24
Peak memory 218676 kb
Host smart-cbf9c87a-79f2-404e-b4f2-7e0adc4fe6b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937095634 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2937095634
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1866857921
Short name T109
Test name
Test status
Simulation time 25982507 ps
CPU time 1.06 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 219488 kb
Host smart-1eae6590-f6e3-47e2-99de-71034507a080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866857921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1866857921
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3916600881
Short name T709
Test name
Test status
Simulation time 101988902 ps
CPU time 1.41 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 218600 kb
Host smart-e580bf15-6f7e-45a1-b236-1a36524dda42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916600881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3916600881
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1762585139
Short name T469
Test name
Test status
Simulation time 24292524 ps
CPU time 0.95 seconds
Started Aug 05 06:08:24 PM PDT 24
Finished Aug 05 06:08:25 PM PDT 24
Peak memory 215516 kb
Host smart-f1b81aa5-5133-4594-82d4-0eeb608adab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762585139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1762585139
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1844624225
Short name T868
Test name
Test status
Simulation time 16682419 ps
CPU time 0.96 seconds
Started Aug 05 06:08:23 PM PDT 24
Finished Aug 05 06:08:24 PM PDT 24
Peak memory 215292 kb
Host smart-1fd749f3-befc-4b46-a897-1c52cf380240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844624225 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1844624225
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2626519986
Short name T685
Test name
Test status
Simulation time 520094633 ps
CPU time 4.8 seconds
Started Aug 05 06:08:31 PM PDT 24
Finished Aug 05 06:08:36 PM PDT 24
Peak memory 217292 kb
Host smart-2deb5ffd-ac6f-41fd-bf9b-324311e13039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626519986 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2626519986
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1733773034
Short name T839
Test name
Test status
Simulation time 258689077513 ps
CPU time 784.21 seconds
Started Aug 05 06:08:44 PM PDT 24
Finished Aug 05 06:21:48 PM PDT 24
Peak memory 221612 kb
Host smart-0d7a718b-2df4-4c60-a6ce-4fb9878226be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733773034 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1733773034
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1202251894
Short name T630
Test name
Test status
Simulation time 72895926 ps
CPU time 1.09 seconds
Started Aug 05 06:07:37 PM PDT 24
Finished Aug 05 06:07:39 PM PDT 24
Peak memory 218560 kb
Host smart-026236c1-e596-4da3-8d67-7c253de22b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202251894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1202251894
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.342870058
Short name T53
Test name
Test status
Simulation time 73273672 ps
CPU time 1.03 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 206748 kb
Host smart-b2f2161d-8912-437e-ae82-13511a330048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342870058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.342870058
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.4094754842
Short name T578
Test name
Test status
Simulation time 75078323 ps
CPU time 0.86 seconds
Started Aug 05 06:07:38 PM PDT 24
Finished Aug 05 06:07:39 PM PDT 24
Peak memory 216012 kb
Host smart-361df91a-9978-4b41-927e-7ce16f446558
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094754842 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.4094754842
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.2361729366
Short name T710
Test name
Test status
Simulation time 18278523 ps
CPU time 1.06 seconds
Started Aug 05 06:07:47 PM PDT 24
Finished Aug 05 06:07:49 PM PDT 24
Peak memory 218532 kb
Host smart-480cbb99-5a94-49be-91e0-c407519db19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361729366 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2361729366
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1707435059
Short name T772
Test name
Test status
Simulation time 30842483 ps
CPU time 1.56 seconds
Started Aug 05 06:07:39 PM PDT 24
Finished Aug 05 06:07:40 PM PDT 24
Peak memory 220212 kb
Host smart-86861b9f-486f-4336-a588-63cf601419d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707435059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1707435059
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2527801475
Short name T943
Test name
Test status
Simulation time 21755913 ps
CPU time 1.08 seconds
Started Aug 05 06:07:35 PM PDT 24
Finished Aug 05 06:07:36 PM PDT 24
Peak memory 215536 kb
Host smart-6488c0da-c3ea-4557-99f3-a5c784bcc95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527801475 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2527801475
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_smoke.2293152973
Short name T629
Test name
Test status
Simulation time 46685743 ps
CPU time 0.9 seconds
Started Aug 05 06:07:36 PM PDT 24
Finished Aug 05 06:07:37 PM PDT 24
Peak memory 207088 kb
Host smart-68ad8a3a-55fa-4e36-bb94-d8d3e211868c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293152973 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2293152973
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1914458811
Short name T282
Test name
Test status
Simulation time 468568627 ps
CPU time 4.95 seconds
Started Aug 05 06:07:38 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 215392 kb
Host smart-915e7b40-d76f-414c-afd7-b25c267c8a9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914458811 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1914458811
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_alert.2478276381
Short name T216
Test name
Test status
Simulation time 25391919 ps
CPU time 1.25 seconds
Started Aug 05 06:08:33 PM PDT 24
Finished Aug 05 06:08:35 PM PDT 24
Peak memory 218664 kb
Host smart-12d43dff-1256-435e-9974-434e828fed66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478276381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2478276381
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1658869706
Short name T862
Test name
Test status
Simulation time 14235313 ps
CPU time 0.89 seconds
Started Aug 05 06:08:32 PM PDT 24
Finished Aug 05 06:08:33 PM PDT 24
Peak memory 214864 kb
Host smart-7d4c6094-fde2-4ed4-917e-d7f312918423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658869706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1658869706
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2434813836
Short name T72
Test name
Test status
Simulation time 71649177 ps
CPU time 0.86 seconds
Started Aug 05 06:08:42 PM PDT 24
Finished Aug 05 06:08:43 PM PDT 24
Peak memory 215928 kb
Host smart-ec2d8866-339e-4b3a-b32b-9fbd61297a70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434813836 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2434813836
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2615310930
Short name T113
Test name
Test status
Simulation time 50959660 ps
CPU time 1.04 seconds
Started Aug 05 06:08:25 PM PDT 24
Finished Aug 05 06:08:26 PM PDT 24
Peak memory 218736 kb
Host smart-ff7407e1-d6ee-4cbf-8ef6-48d34d101eca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615310930 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2615310930
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3550793653
Short name T779
Test name
Test status
Simulation time 22618127 ps
CPU time 0.93 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 218640 kb
Host smart-09e7d07a-e1b8-4b48-a8a8-a029c78dfb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550793653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3550793653
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1331393743
Short name T400
Test name
Test status
Simulation time 96973990 ps
CPU time 2.77 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:08:48 PM PDT 24
Peak memory 217444 kb
Host smart-6df5fb70-13cb-495a-9b9e-c6f67b14a919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331393743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1331393743
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.4129575823
Short name T577
Test name
Test status
Simulation time 35748553 ps
CPU time 0.88 seconds
Started Aug 05 06:08:34 PM PDT 24
Finished Aug 05 06:08:35 PM PDT 24
Peak memory 215520 kb
Host smart-b5a35165-236f-433c-9128-15134f163bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129575823 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.4129575823
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.366040102
Short name T379
Test name
Test status
Simulation time 80511603 ps
CPU time 0.9 seconds
Started Aug 05 06:08:34 PM PDT 24
Finished Aug 05 06:08:35 PM PDT 24
Peak memory 215300 kb
Host smart-c4fde303-b6bf-4110-9765-7bfcf83299f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366040102 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.366040102
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1510203910
Short name T842
Test name
Test status
Simulation time 563427037 ps
CPU time 6.38 seconds
Started Aug 05 06:08:31 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 217364 kb
Host smart-1ac60ba9-854c-4aad-a0f3-1f79fb4bfc20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510203910 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1510203910
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2630103112
Short name T830
Test name
Test status
Simulation time 84802245986 ps
CPU time 1952.52 seconds
Started Aug 05 06:08:30 PM PDT 24
Finished Aug 05 06:41:03 PM PDT 24
Peak memory 225700 kb
Host smart-8f3437ac-63e0-4d23-b721-ba2811384f20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630103112 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2630103112
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert_test.3946148790
Short name T684
Test name
Test status
Simulation time 41194676 ps
CPU time 0.85 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 206696 kb
Host smart-027c30bb-5d72-4619-aee9-b7f0f884497f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946148790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3946148790
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1619643007
Short name T974
Test name
Test status
Simulation time 50066948 ps
CPU time 0.87 seconds
Started Aug 05 06:08:23 PM PDT 24
Finished Aug 05 06:08:24 PM PDT 24
Peak memory 216228 kb
Host smart-c35ba6f8-57fc-4fc1-9c2f-bbce99319084
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619643007 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1619643007
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1368090311
Short name T599
Test name
Test status
Simulation time 291370954 ps
CPU time 1.17 seconds
Started Aug 05 06:08:27 PM PDT 24
Finished Aug 05 06:08:28 PM PDT 24
Peak memory 218708 kb
Host smart-c3765930-df8d-4700-9393-813a8c277b90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368090311 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1368090311
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2728917784
Short name T153
Test name
Test status
Simulation time 22742441 ps
CPU time 0.9 seconds
Started Aug 05 06:08:24 PM PDT 24
Finished Aug 05 06:08:25 PM PDT 24
Peak memory 218396 kb
Host smart-033c66c6-6c3e-426f-a5c8-422605585e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728917784 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2728917784
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.917358928
Short name T466
Test name
Test status
Simulation time 45251597 ps
CPU time 1.18 seconds
Started Aug 05 06:08:34 PM PDT 24
Finished Aug 05 06:08:35 PM PDT 24
Peak memory 220068 kb
Host smart-aae9e6ad-b788-434b-a0f4-53e3ea33c249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917358928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.917358928
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.4076815875
Short name T690
Test name
Test status
Simulation time 23579872 ps
CPU time 0.97 seconds
Started Aug 05 06:08:21 PM PDT 24
Finished Aug 05 06:08:22 PM PDT 24
Peak memory 215516 kb
Host smart-fbad5f75-0331-433d-bf14-0d2a5ab6c197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076815875 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.4076815875
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3079407675
Short name T346
Test name
Test status
Simulation time 43372113 ps
CPU time 0.9 seconds
Started Aug 05 06:08:30 PM PDT 24
Finished Aug 05 06:08:31 PM PDT 24
Peak memory 215276 kb
Host smart-b3a4dd2f-7bd7-4db0-8365-f4b8446636e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079407675 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3079407675
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.615381605
Short name T525
Test name
Test status
Simulation time 162102532 ps
CPU time 1.9 seconds
Started Aug 05 06:08:32 PM PDT 24
Finished Aug 05 06:08:34 PM PDT 24
Peak memory 217316 kb
Host smart-005bc04f-4ded-42c6-bff3-a3daf1a2a0a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615381605 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.615381605
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2144893228
Short name T540
Test name
Test status
Simulation time 89758435808 ps
CPU time 1051.04 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:26:11 PM PDT 24
Peak memory 223656 kb
Host smart-df810d0e-d3b7-4b84-a0c9-8f6f6c7d35d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144893228 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2144893228
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.812633371
Short name T531
Test name
Test status
Simulation time 50429465 ps
CPU time 1.28 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:36 PM PDT 24
Peak memory 220776 kb
Host smart-a0993caf-3c1c-4dff-a937-8aac16a29858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812633371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.812633371
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.257375263
Short name T963
Test name
Test status
Simulation time 44122240 ps
CPU time 0.84 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 206680 kb
Host smart-f9887c6d-39d8-48aa-9eb4-1f688165eeb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257375263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.257375263
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3945359865
Short name T903
Test name
Test status
Simulation time 20063013 ps
CPU time 0.86 seconds
Started Aug 05 06:08:30 PM PDT 24
Finished Aug 05 06:08:31 PM PDT 24
Peak memory 216216 kb
Host smart-df751bbf-3bc6-422e-bc9c-fe7f03483415
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945359865 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3945359865
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3680523023
Short name T534
Test name
Test status
Simulation time 63131483 ps
CPU time 1.05 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 216924 kb
Host smart-6a06a69f-883c-49c3-ba1a-a27d64b7383e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680523023 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3680523023
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.202015109
Short name T784
Test name
Test status
Simulation time 26666928 ps
CPU time 0.83 seconds
Started Aug 05 06:08:31 PM PDT 24
Finished Aug 05 06:08:32 PM PDT 24
Peak memory 218328 kb
Host smart-20a5d3e0-a5f6-466a-87a8-9f1b921147ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202015109 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.202015109
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1149162307
Short name T825
Test name
Test status
Simulation time 82718463 ps
CPU time 1.11 seconds
Started Aug 05 06:08:41 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 217368 kb
Host smart-b9a7a02a-a5cd-4766-8162-b7aeaa31d862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149162307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1149162307
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1265527331
Short name T949
Test name
Test status
Simulation time 25853660 ps
CPU time 0.94 seconds
Started Aug 05 06:08:47 PM PDT 24
Finished Aug 05 06:08:48 PM PDT 24
Peak memory 215520 kb
Host smart-bda4b632-440f-406a-bcef-d42dbdfa7b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265527331 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1265527331
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.4116433596
Short name T397
Test name
Test status
Simulation time 25964972 ps
CPU time 0.97 seconds
Started Aug 05 06:08:31 PM PDT 24
Finished Aug 05 06:08:32 PM PDT 24
Peak memory 207104 kb
Host smart-b1538e14-a391-448d-8a5b-6f23fb4ebd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116433596 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4116433596
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1143771860
Short name T584
Test name
Test status
Simulation time 132619038 ps
CPU time 2.98 seconds
Started Aug 05 06:08:34 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 217064 kb
Host smart-b395f05a-d842-4355-8d06-7becaa340cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143771860 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1143771860
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.633136865
Short name T231
Test name
Test status
Simulation time 21217448845 ps
CPU time 467.3 seconds
Started Aug 05 06:08:28 PM PDT 24
Finished Aug 05 06:16:16 PM PDT 24
Peak memory 223572 kb
Host smart-71a1a6ea-7274-4156-930f-4f683912d228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633136865 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.633136865
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2871393495
Short name T866
Test name
Test status
Simulation time 23444475 ps
CPU time 1.17 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 218760 kb
Host smart-dfb58baa-ae9b-4210-ac45-f40dac79054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871393495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2871393495
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2207245072
Short name T721
Test name
Test status
Simulation time 16559077 ps
CPU time 0.95 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:36 PM PDT 24
Peak memory 214852 kb
Host smart-e8daf260-44f6-42cf-bdec-e82de6193155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207245072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2207245072
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1043489867
Short name T138
Test name
Test status
Simulation time 11633945 ps
CPU time 0.87 seconds
Started Aug 05 06:08:23 PM PDT 24
Finished Aug 05 06:08:24 PM PDT 24
Peak memory 214900 kb
Host smart-ddbcb920-e83c-402d-b5ca-f5f9c616d27b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043489867 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1043489867
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.394902581
Short name T194
Test name
Test status
Simulation time 66973710 ps
CPU time 1.03 seconds
Started Aug 05 06:08:30 PM PDT 24
Finished Aug 05 06:08:31 PM PDT 24
Peak memory 216832 kb
Host smart-14c940f5-558f-4246-b3ef-331b162340ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394902581 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.394902581
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2679344058
Short name T121
Test name
Test status
Simulation time 27907911 ps
CPU time 1.18 seconds
Started Aug 05 06:08:33 PM PDT 24
Finished Aug 05 06:08:35 PM PDT 24
Peak memory 217132 kb
Host smart-0869cdff-3e1c-40c8-8f1d-3d8feed6a807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679344058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2679344058
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1469578453
Short name T387
Test name
Test status
Simulation time 106316122 ps
CPU time 1.21 seconds
Started Aug 05 06:08:22 PM PDT 24
Finished Aug 05 06:08:24 PM PDT 24
Peak memory 217404 kb
Host smart-9605f505-1edf-48db-be63-280244d111d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469578453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1469578453
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.978549903
Short name T605
Test name
Test status
Simulation time 32867873 ps
CPU time 0.88 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 215328 kb
Host smart-09b7cd81-2c9f-4fb6-844e-33b686f518e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978549903 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.978549903
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1418144206
Short name T453
Test name
Test status
Simulation time 19138196 ps
CPU time 1.06 seconds
Started Aug 05 06:08:28 PM PDT 24
Finished Aug 05 06:08:29 PM PDT 24
Peak memory 215264 kb
Host smart-8c9bb1f9-b483-434f-b94a-f4301b2723e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418144206 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1418144206
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2169412608
Short name T6
Test name
Test status
Simulation time 580584965 ps
CPU time 3.43 seconds
Started Aug 05 06:08:31 PM PDT 24
Finished Aug 05 06:08:35 PM PDT 24
Peak memory 217320 kb
Host smart-3f4685c7-2d9a-4aa0-81b2-20517d47619b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169412608 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2169412608
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3914588877
Short name T827
Test name
Test status
Simulation time 68612483735 ps
CPU time 1143.31 seconds
Started Aug 05 06:08:25 PM PDT 24
Finished Aug 05 06:27:29 PM PDT 24
Peak memory 223976 kb
Host smart-b27dfe7e-62ed-413e-acc1-bd3305b9cb91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914588877 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3914588877
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3378184543
Short name T342
Test name
Test status
Simulation time 30637729 ps
CPU time 1.16 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 219840 kb
Host smart-d1eed861-d2d3-499b-b1ec-eb66d479c7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378184543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3378184543
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3599621278
Short name T356
Test name
Test status
Simulation time 24952754 ps
CPU time 0.81 seconds
Started Aug 05 06:08:29 PM PDT 24
Finished Aug 05 06:08:30 PM PDT 24
Peak memory 206492 kb
Host smart-f4bac669-2a13-4e5a-b04e-6ed9daeb49a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599621278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3599621278
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1942265006
Short name T137
Test name
Test status
Simulation time 17308626 ps
CPU time 0.88 seconds
Started Aug 05 06:08:27 PM PDT 24
Finished Aug 05 06:08:28 PM PDT 24
Peak memory 215400 kb
Host smart-154c7109-052b-43d6-a65d-4cb0b57a3a8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942265006 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1942265006
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1963460614
Short name T670
Test name
Test status
Simulation time 35788062 ps
CPU time 1.2 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:28 PM PDT 24
Peak memory 218012 kb
Host smart-cab0bc2c-3b72-4cb6-91df-cc8f95ce6a1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963460614 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1963460614
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2889801655
Short name T863
Test name
Test status
Simulation time 94885008 ps
CPU time 1.11 seconds
Started Aug 05 06:08:29 PM PDT 24
Finished Aug 05 06:08:30 PM PDT 24
Peak memory 225728 kb
Host smart-e9ea1f5e-058f-4ee3-8c39-bb732bbbc6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889801655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2889801655
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1900071094
Short name T459
Test name
Test status
Simulation time 770237400 ps
CPU time 6.84 seconds
Started Aug 05 06:08:32 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 217444 kb
Host smart-a4469981-0920-4f73-8fbc-543dd450704a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900071094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1900071094
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1746085743
Short name T489
Test name
Test status
Simulation time 23548665 ps
CPU time 1.16 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 223996 kb
Host smart-46271171-2886-4df3-8347-0db03363d13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746085743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1746085743
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.311841918
Short name T968
Test name
Test status
Simulation time 16925094 ps
CPU time 0.98 seconds
Started Aug 05 06:08:34 PM PDT 24
Finished Aug 05 06:08:35 PM PDT 24
Peak memory 214444 kb
Host smart-15cfe455-6166-4608-b067-da11ba5fef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311841918 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.311841918
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2191428375
Short name T972
Test name
Test status
Simulation time 204418068 ps
CPU time 3.9 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:43 PM PDT 24
Peak memory 215268 kb
Host smart-a5b34843-eafe-4c33-bb49-a9618ee9f035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191428375 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2191428375
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.601771839
Short name T235
Test name
Test status
Simulation time 67559050566 ps
CPU time 1415.67 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:32:16 PM PDT 24
Peak memory 221948 kb
Host smart-6e2b6a5a-4770-4b45-8902-238c2a8a55df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601771839 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.601771839
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2733421700
Short name T50
Test name
Test status
Simulation time 317853756 ps
CPU time 1.27 seconds
Started Aug 05 06:08:29 PM PDT 24
Finished Aug 05 06:08:31 PM PDT 24
Peak memory 215648 kb
Host smart-f62a5968-d6a6-4cc1-8711-b735c112a4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733421700 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2733421700
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.182441134
Short name T789
Test name
Test status
Simulation time 42937739 ps
CPU time 0.9 seconds
Started Aug 05 06:08:31 PM PDT 24
Finished Aug 05 06:08:32 PM PDT 24
Peak memory 214820 kb
Host smart-63df4a9c-4489-415f-b26f-9c642f1e2f21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182441134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.182441134
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1349247737
Short name T154
Test name
Test status
Simulation time 87844063 ps
CPU time 0.83 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 216216 kb
Host smart-6d50d588-0eb5-4484-a8b8-a755b20f9287
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349247737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1349247737
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.373024365
Short name T189
Test name
Test status
Simulation time 50142682 ps
CPU time 1.1 seconds
Started Aug 05 06:08:28 PM PDT 24
Finished Aug 05 06:08:29 PM PDT 24
Peak memory 216988 kb
Host smart-cdfbe7a1-9ac9-48e4-b159-64c2244549a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373024365 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.373024365
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1487497955
Short name T619
Test name
Test status
Simulation time 17946533 ps
CPU time 1.14 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:36 PM PDT 24
Peak memory 224024 kb
Host smart-9835b44c-a29a-4b2d-ae25-da7125de87d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487497955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1487497955
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2477207364
Short name T564
Test name
Test status
Simulation time 36541398 ps
CPU time 1.36 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 220028 kb
Host smart-aed050af-318d-4bbe-894f-4f1cdb0db37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477207364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2477207364
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3608109382
Short name T88
Test name
Test status
Simulation time 21942920 ps
CPU time 0.92 seconds
Started Aug 05 06:08:31 PM PDT 24
Finished Aug 05 06:08:32 PM PDT 24
Peak memory 215804 kb
Host smart-c8d5b831-ebc5-421b-b26e-ec41a06a34ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608109382 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3608109382
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.860389355
Short name T890
Test name
Test status
Simulation time 50243882 ps
CPU time 0.9 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 214776 kb
Host smart-995db9c5-5a75-4303-aee2-e7ec95d49f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860389355 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.860389355
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2692745015
Short name T889
Test name
Test status
Simulation time 120730032 ps
CPU time 1.74 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:08:38 PM PDT 24
Peak memory 217048 kb
Host smart-cdf3ca53-ed3f-4102-8756-5dbfc247fb29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692745015 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2692745015
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.467092649
Short name T232
Test name
Test status
Simulation time 53451071384 ps
CPU time 292.6 seconds
Started Aug 05 06:08:30 PM PDT 24
Finished Aug 05 06:13:23 PM PDT 24
Peak memory 217984 kb
Host smart-748bd367-300a-4c9a-a31f-9b8814e7ab0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467092649 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.467092649
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1077761821
Short name T962
Test name
Test status
Simulation time 148299572 ps
CPU time 1.04 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:36 PM PDT 24
Peak memory 219728 kb
Host smart-663379b2-95fe-48dd-8962-3918abc5bfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077761821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1077761821
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1197101384
Short name T56
Test name
Test status
Simulation time 29013717 ps
CPU time 0.91 seconds
Started Aug 05 06:08:41 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 206704 kb
Host smart-98a122cc-7a63-43e3-89dd-a29bad120075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197101384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1197101384
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2119910611
Short name T891
Test name
Test status
Simulation time 19947813 ps
CPU time 0.87 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 215408 kb
Host smart-ae15910b-2dba-4775-9457-c936c01a4238
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119910611 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2119910611
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.20877892
Short name T593
Test name
Test status
Simulation time 82943829 ps
CPU time 1.05 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 217092 kb
Host smart-88c1fbba-70e9-4d54-b416-6c0135c07542
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20877892 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_dis
able_auto_req_mode.20877892
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3810421401
Short name T192
Test name
Test status
Simulation time 186577742 ps
CPU time 1.11 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 219776 kb
Host smart-3e78f224-b8da-47e5-bcab-373f6c32a07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810421401 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3810421401
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_intr.3268712850
Short name T89
Test name
Test status
Simulation time 29526585 ps
CPU time 0.86 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 215628 kb
Host smart-6a47e5a4-65a2-4147-ad2a-dc902bfc79df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268712850 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3268712850
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3438770752
Short name T375
Test name
Test status
Simulation time 14954951 ps
CPU time 1.01 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 215276 kb
Host smart-3eea34d4-38d9-408f-8dcb-9bcbf08c1310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438770752 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3438770752
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.4052289385
Short name T461
Test name
Test status
Simulation time 332709925 ps
CPU time 6.19 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:46 PM PDT 24
Peak memory 215288 kb
Host smart-f66c8bce-a929-41b9-869c-18e7cbe76ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052289385 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.4052289385
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2823113830
Short name T836
Test name
Test status
Simulation time 62387811154 ps
CPU time 1538.69 seconds
Started Aug 05 06:08:25 PM PDT 24
Finished Aug 05 06:34:04 PM PDT 24
Peak memory 224416 kb
Host smart-374e7034-9d15-4e16-83c4-8112fa217244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823113830 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2823113830
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.25274320
Short name T881
Test name
Test status
Simulation time 46956861 ps
CPU time 1.14 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 219304 kb
Host smart-e436d2d0-4527-41a5-8c34-c3b1aa191cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25274320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.25274320
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2360422622
Short name T358
Test name
Test status
Simulation time 29038831 ps
CPU time 0.81 seconds
Started Aug 05 06:08:42 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 206752 kb
Host smart-21fb1eb8-089a-4245-a5c5-2b145b71acd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360422622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2360422622
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.302950585
Short name T217
Test name
Test status
Simulation time 25835915 ps
CPU time 0.84 seconds
Started Aug 05 06:08:37 PM PDT 24
Finished Aug 05 06:08:38 PM PDT 24
Peak memory 216304 kb
Host smart-e5affb94-e0ff-4b42-bbdf-f1843a31233e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302950585 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.302950585
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1802867620
Short name T103
Test name
Test status
Simulation time 42767374 ps
CPU time 1.04 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 216868 kb
Host smart-8114d76d-9001-4011-add4-2d572a20dadc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802867620 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1802867620
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3164311468
Short name T691
Test name
Test status
Simulation time 20646935 ps
CPU time 0.92 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:36 PM PDT 24
Peak memory 218292 kb
Host smart-10842cce-c439-44fe-a3c4-83d54262a5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164311468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3164311468
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.263125345
Short name T950
Test name
Test status
Simulation time 250933472 ps
CPU time 1.11 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 217496 kb
Host smart-878ee8e3-5c93-4481-86e5-d33e3326e1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263125345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.263125345
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3682913363
Short name T955
Test name
Test status
Simulation time 26884191 ps
CPU time 1.07 seconds
Started Aug 05 06:08:41 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 224048 kb
Host smart-4499eca6-ed4b-44d7-b964-5fab3b45bf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682913363 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3682913363
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3011483040
Short name T503
Test name
Test status
Simulation time 20852375 ps
CPU time 0.9 seconds
Started Aug 05 06:08:23 PM PDT 24
Finished Aug 05 06:08:24 PM PDT 24
Peak memory 214800 kb
Host smart-83aa0937-0e56-4456-ad5e-4509fc216386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011483040 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3011483040
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2772363494
Short name T667
Test name
Test status
Simulation time 686318675 ps
CPU time 4.21 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:08:45 PM PDT 24
Peak memory 215344 kb
Host smart-8b4c3c84-fe30-482c-9957-729aadce149e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772363494 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2772363494
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1475150577
Short name T25
Test name
Test status
Simulation time 18653493724 ps
CPU time 415.23 seconds
Started Aug 05 06:08:41 PM PDT 24
Finished Aug 05 06:15:36 PM PDT 24
Peak memory 218120 kb
Host smart-bca97afa-adef-4e72-96b2-886e01bd4ace
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475150577 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1475150577
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.415796803
Short name T359
Test name
Test status
Simulation time 28839132 ps
CPU time 1.29 seconds
Started Aug 05 06:08:29 PM PDT 24
Finished Aug 05 06:08:30 PM PDT 24
Peak memory 219844 kb
Host smart-c8358b7e-287a-4403-82aa-0fc8c603d028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415796803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.415796803
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1590325146
Short name T806
Test name
Test status
Simulation time 50789879 ps
CPU time 0.76 seconds
Started Aug 05 06:08:30 PM PDT 24
Finished Aug 05 06:08:31 PM PDT 24
Peak memory 206436 kb
Host smart-44d7e4b8-6811-4dfd-9929-184401a7b08c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590325146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1590325146
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.625681322
Short name T162
Test name
Test status
Simulation time 15094145 ps
CPU time 0.85 seconds
Started Aug 05 06:08:32 PM PDT 24
Finished Aug 05 06:08:33 PM PDT 24
Peak memory 216212 kb
Host smart-4b913ab2-9646-4bc3-99fc-d68ced9e6fb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625681322 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.625681322
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3294714856
Short name T104
Test name
Test status
Simulation time 54117118 ps
CPU time 1.17 seconds
Started Aug 05 06:08:41 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 216956 kb
Host smart-6082d7c6-213c-4b27-a191-5df5c76c9df2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294714856 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3294714856
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3554579432
Short name T965
Test name
Test status
Simulation time 27396442 ps
CPU time 0.83 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 218132 kb
Host smart-86077b77-e94e-4474-8f90-1f499074b2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554579432 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3554579432
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.4007491751
Short name T664
Test name
Test status
Simulation time 85730790 ps
CPU time 1.22 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 218644 kb
Host smart-b5a8b10a-dd75-4676-953c-d939ebd05e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007491751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.4007491751
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.943332895
Short name T172
Test name
Test status
Simulation time 22563769 ps
CPU time 1.13 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 215460 kb
Host smart-06c7b726-bf66-446e-9f44-95cdaa8c41a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943332895 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.943332895
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2090006853
Short name T547
Test name
Test status
Simulation time 75394887 ps
CPU time 0.88 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 215012 kb
Host smart-f254291b-f3a9-43c4-88e7-444e598312a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090006853 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2090006853
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.941489322
Short name T281
Test name
Test status
Simulation time 314130694 ps
CPU time 2.26 seconds
Started Aug 05 06:08:37 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 217228 kb
Host smart-9175dbdb-e142-4aff-8711-f05aeb4627bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941489322 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.941489322
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.525906710
Short name T491
Test name
Test status
Simulation time 172362609721 ps
CPU time 1048.4 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:26:04 PM PDT 24
Peak memory 223012 kb
Host smart-e4637e01-51d8-45a6-8390-cc5a0048e924
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525906710 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.525906710
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.649946098
Short name T290
Test name
Test status
Simulation time 45308323 ps
CPU time 1.26 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 219604 kb
Host smart-07c3dea1-3eea-4f17-ab24-86b5ed5b5caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649946098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.649946098
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3091457479
Short name T355
Test name
Test status
Simulation time 51692233 ps
CPU time 0.85 seconds
Started Aug 05 06:08:29 PM PDT 24
Finished Aug 05 06:08:30 PM PDT 24
Peak memory 214688 kb
Host smart-9e6104f9-e4c4-46c2-a8b6-6fc7ece45f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091457479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3091457479
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.932006632
Short name T145
Test name
Test status
Simulation time 24779933 ps
CPU time 0.85 seconds
Started Aug 05 06:08:34 PM PDT 24
Finished Aug 05 06:08:35 PM PDT 24
Peak memory 216216 kb
Host smart-d3a83ecc-84b4-42f4-9ded-d7a58caa3648
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932006632 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.932006632
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.4138056572
Short name T105
Test name
Test status
Simulation time 71205935 ps
CPU time 1.28 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 216892 kb
Host smart-2fa98bf1-7a64-4e64-a058-f75dbc8fd8ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138056572 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.4138056572
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3963707417
Short name T978
Test name
Test status
Simulation time 50967513 ps
CPU time 0.88 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 218300 kb
Host smart-99f1a12b-d60c-4c4d-87be-cfa44eac47f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963707417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3963707417
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1728256003
Short name T473
Test name
Test status
Simulation time 62908549 ps
CPU time 1.34 seconds
Started Aug 05 06:08:30 PM PDT 24
Finished Aug 05 06:08:31 PM PDT 24
Peak memory 217372 kb
Host smart-260a9603-d6d1-4955-846c-dd6061f31dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728256003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1728256003
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3669821426
Short name T654
Test name
Test status
Simulation time 31879832 ps
CPU time 0.93 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 215516 kb
Host smart-9da6974b-9ab5-446c-bb1d-26a4ba8ae08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669821426 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3669821426
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.4103170003
Short name T908
Test name
Test status
Simulation time 14292644 ps
CPU time 0.94 seconds
Started Aug 05 06:08:34 PM PDT 24
Finished Aug 05 06:08:35 PM PDT 24
Peak memory 215284 kb
Host smart-b971a92c-153b-4f4f-944a-8184f3c21ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103170003 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.4103170003
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2286769549
Short name T335
Test name
Test status
Simulation time 120954288 ps
CPU time 1.6 seconds
Started Aug 05 06:08:32 PM PDT 24
Finished Aug 05 06:08:33 PM PDT 24
Peak memory 217396 kb
Host smart-1ab0d6f0-4fde-428d-a335-aa9e53bf4387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286769549 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2286769549
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1117466190
Short name T933
Test name
Test status
Simulation time 40395273248 ps
CPU time 537.06 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:17:33 PM PDT 24
Peak memory 218072 kb
Host smart-c81386c8-644f-4b15-ba95-308b716e53e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117466190 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1117466190
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.333256173
Short name T867
Test name
Test status
Simulation time 27492734 ps
CPU time 1.29 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 220768 kb
Host smart-3c110af0-05ee-4547-851e-23ebb84b58b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333256173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.333256173
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.374789755
Short name T54
Test name
Test status
Simulation time 45892519 ps
CPU time 0.92 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 206700 kb
Host smart-88297ab1-6807-47f4-8b3f-cf045086c6dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374789755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.374789755
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3626336749
Short name T585
Test name
Test status
Simulation time 13094507 ps
CPU time 0.92 seconds
Started Aug 05 06:07:40 PM PDT 24
Finished Aug 05 06:07:41 PM PDT 24
Peak memory 216152 kb
Host smart-7628aad6-6be1-40ee-8095-cd4a2e8fb242
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626336749 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3626336749
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.1141815589
Short name T129
Test name
Test status
Simulation time 76117785 ps
CPU time 0.92 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 219016 kb
Host smart-5b2ca3c4-003f-4cae-8e19-a4c55ba72c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141815589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1141815589
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1963704377
Short name T384
Test name
Test status
Simulation time 69795413 ps
CPU time 1.06 seconds
Started Aug 05 06:07:35 PM PDT 24
Finished Aug 05 06:07:36 PM PDT 24
Peak memory 217152 kb
Host smart-d5565be8-b9ee-4830-b229-e7a9b6c7aef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963704377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1963704377
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1076190751
Short name T17
Test name
Test status
Simulation time 30668929 ps
CPU time 0.94 seconds
Started Aug 05 06:07:40 PM PDT 24
Finished Aug 05 06:07:41 PM PDT 24
Peak memory 223816 kb
Host smart-cac85e9d-7349-4032-9038-67517afe39f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076190751 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1076190751
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2090267814
Short name T854
Test name
Test status
Simulation time 26645631 ps
CPU time 0.94 seconds
Started Aug 05 06:07:49 PM PDT 24
Finished Aug 05 06:07:50 PM PDT 24
Peak memory 207084 kb
Host smart-7e3c1f9b-fa6c-405c-942d-f546a0b62c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090267814 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2090267814
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3074583566
Short name T807
Test name
Test status
Simulation time 15830937 ps
CPU time 1 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 215272 kb
Host smart-c65e5330-9239-4e4a-90ea-2efd8dfbe52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074583566 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3074583566
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2171999029
Short name T638
Test name
Test status
Simulation time 127259211 ps
CPU time 1.11 seconds
Started Aug 05 06:07:39 PM PDT 24
Finished Aug 05 06:07:40 PM PDT 24
Peak memory 217388 kb
Host smart-e140f364-3ea2-49ef-848e-64112dc38a44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171999029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2171999029
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2931696043
Short name T742
Test name
Test status
Simulation time 74579364485 ps
CPU time 1805.17 seconds
Started Aug 05 06:07:41 PM PDT 24
Finished Aug 05 06:37:47 PM PDT 24
Peak memory 226520 kb
Host smart-eca84079-f042-4910-b8fc-345b513f9957
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931696043 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2931696043
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2330455266
Short name T164
Test name
Test status
Simulation time 32680592 ps
CPU time 1.3 seconds
Started Aug 05 06:08:41 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 215688 kb
Host smart-5a20f25a-e527-4a70-a0cf-4562ad6a960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330455266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2330455266
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.573997905
Short name T102
Test name
Test status
Simulation time 26358725 ps
CPU time 1.29 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 229512 kb
Host smart-c44e2917-73cb-4a53-b7d0-5b8f415c29c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573997905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.573997905
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3365913377
Short name T771
Test name
Test status
Simulation time 85777892 ps
CPU time 1.47 seconds
Started Aug 05 06:08:37 PM PDT 24
Finished Aug 05 06:08:38 PM PDT 24
Peak memory 217252 kb
Host smart-423a628f-5e8b-4d7a-bd0b-64cacfa0d71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365913377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3365913377
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2045029251
Short name T75
Test name
Test status
Simulation time 25797103 ps
CPU time 1.29 seconds
Started Aug 05 06:08:26 PM PDT 24
Finished Aug 05 06:08:27 PM PDT 24
Peak memory 218740 kb
Host smart-44cbd4d5-b122-4171-a69a-6819de7fc05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045029251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2045029251
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1366335262
Short name T976
Test name
Test status
Simulation time 33490881 ps
CPU time 0.96 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 223748 kb
Host smart-04dbcabc-9bdb-4b6a-a411-c0de720a9257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366335262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1366335262
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3744342665
Short name T613
Test name
Test status
Simulation time 38996455 ps
CPU time 1.43 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 217248 kb
Host smart-b5d8ce98-7047-46e4-86a4-ea1414ee441c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744342665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3744342665
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.389585118
Short name T938
Test name
Test status
Simulation time 56608452 ps
CPU time 1.1 seconds
Started Aug 05 06:08:32 PM PDT 24
Finished Aug 05 06:08:33 PM PDT 24
Peak memory 219764 kb
Host smart-5b7035c5-1e0b-4ec0-a6f2-47590cf99276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389585118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.389585118
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2755956902
Short name T740
Test name
Test status
Simulation time 57154841 ps
CPU time 1.14 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 229624 kb
Host smart-373df47f-95cb-4423-b325-6da70210a140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755956902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2755956902
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1030452811
Short name T493
Test name
Test status
Simulation time 34015855 ps
CPU time 1.1 seconds
Started Aug 05 06:08:32 PM PDT 24
Finished Aug 05 06:08:33 PM PDT 24
Peak memory 219808 kb
Host smart-9a8961d4-89cb-4b8e-b784-8a56e2fc0db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030452811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1030452811
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.875497625
Short name T158
Test name
Test status
Simulation time 65356750 ps
CPU time 1.15 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 218632 kb
Host smart-4a0a9904-83ab-47b8-b945-be67db0ea28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875497625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.875497625
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2265427336
Short name T65
Test name
Test status
Simulation time 34675981 ps
CPU time 0.9 seconds
Started Aug 05 06:08:37 PM PDT 24
Finished Aug 05 06:08:38 PM PDT 24
Peak memory 218376 kb
Host smart-443e1e26-3272-4f99-b8e4-a39dd630c75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265427336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2265427336
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2030816757
Short name T528
Test name
Test status
Simulation time 50571313 ps
CPU time 1.57 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 218480 kb
Host smart-21eef32b-de64-4e4d-985c-928fff5ed37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030816757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2030816757
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3612381198
Short name T59
Test name
Test status
Simulation time 63886707 ps
CPU time 1.19 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:45 PM PDT 24
Peak memory 218632 kb
Host smart-66fbbd45-ee0a-4092-aaa8-56ae9fb4cc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612381198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3612381198
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.1682323184
Short name T47
Test name
Test status
Simulation time 34395087 ps
CPU time 1.28 seconds
Started Aug 05 06:08:34 PM PDT 24
Finished Aug 05 06:08:35 PM PDT 24
Peak memory 225520 kb
Host smart-a94e9b81-2275-4edc-b5d4-8d9a55707851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682323184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1682323184
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1072581571
Short name T717
Test name
Test status
Simulation time 108758847 ps
CPU time 1.32 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 217300 kb
Host smart-591cf64d-a606-4cde-85fd-e30705703c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072581571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1072581571
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2457956340
Short name T301
Test name
Test status
Simulation time 28705210 ps
CPU time 1.11 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:36 PM PDT 24
Peak memory 219540 kb
Host smart-155a5f68-885b-4131-8ccb-df9246d012f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457956340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2457956340
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3584273337
Short name T213
Test name
Test status
Simulation time 23117403 ps
CPU time 0.94 seconds
Started Aug 05 06:08:31 PM PDT 24
Finished Aug 05 06:08:32 PM PDT 24
Peak memory 219468 kb
Host smart-bf582251-59d2-4360-8ed0-65717d574b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584273337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3584273337
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1045248357
Short name T628
Test name
Test status
Simulation time 97347874 ps
CPU time 1.51 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 218608 kb
Host smart-40bd00c3-da95-4f04-aae8-04d9d69e33c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045248357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1045248357
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2403218587
Short name T860
Test name
Test status
Simulation time 76661989 ps
CPU time 1.04 seconds
Started Aug 05 06:08:33 PM PDT 24
Finished Aug 05 06:08:34 PM PDT 24
Peak memory 220044 kb
Host smart-fd4def38-ed9f-4016-9cbd-9e1c5fdda453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403218587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2403218587
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.2130830419
Short name T128
Test name
Test status
Simulation time 33613988 ps
CPU time 1.14 seconds
Started Aug 05 06:08:42 PM PDT 24
Finished Aug 05 06:08:43 PM PDT 24
Peak memory 229608 kb
Host smart-832b0ac4-139d-46b2-bc7d-74836f82b643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130830419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2130830419
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1284196501
Short name T626
Test name
Test status
Simulation time 96020289 ps
CPU time 1.15 seconds
Started Aug 05 06:08:37 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 217244 kb
Host smart-2788ca70-1609-46f6-8a49-47f68d58c142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284196501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1284196501
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.572024194
Short name T657
Test name
Test status
Simulation time 36851362 ps
CPU time 1.14 seconds
Started Aug 05 06:08:34 PM PDT 24
Finished Aug 05 06:08:35 PM PDT 24
Peak memory 219400 kb
Host smart-d3e60ef7-526e-4bbf-903c-3d129b301cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572024194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.572024194
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1140622982
Short name T885
Test name
Test status
Simulation time 53441691 ps
CPU time 0.9 seconds
Started Aug 05 06:08:42 PM PDT 24
Finished Aug 05 06:08:43 PM PDT 24
Peak memory 219812 kb
Host smart-534379a7-520a-47cd-adcc-7234f415840f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140622982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1140622982
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1563289336
Short name T557
Test name
Test status
Simulation time 25167342 ps
CPU time 1.1 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 217364 kb
Host smart-f8c61afe-e042-4299-b9a8-cc3e9ef14ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563289336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1563289336
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.2809454671
Short name T297
Test name
Test status
Simulation time 35393342 ps
CPU time 1.3 seconds
Started Aug 05 06:08:32 PM PDT 24
Finished Aug 05 06:08:33 PM PDT 24
Peak memory 218676 kb
Host smart-f4d3f961-f6a7-4991-9b2e-38b0cdb5d642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809454671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.2809454671
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2116418997
Short name T118
Test name
Test status
Simulation time 23666938 ps
CPU time 1.04 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 224032 kb
Host smart-c9261428-344f-493a-95c8-d59afefe1680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116418997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2116418997
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1532280647
Short name T942
Test name
Test status
Simulation time 123618801 ps
CPU time 2.81 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 220308 kb
Host smart-9a698a09-ebd7-44ac-b8a7-3d7a33b74382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532280647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1532280647
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3410384604
Short name T100
Test name
Test status
Simulation time 103100716 ps
CPU time 1.31 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:08:38 PM PDT 24
Peak memory 215688 kb
Host smart-1e7cf600-7cf0-469b-b29f-16f7c04b6ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410384604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3410384604
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.888266914
Short name T745
Test name
Test status
Simulation time 22469347 ps
CPU time 0.92 seconds
Started Aug 05 06:08:41 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 218556 kb
Host smart-6b1f633a-6bd9-47aa-9f3f-56defba6b31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888266914 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.888266914
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3590741498
Short name T318
Test name
Test status
Simulation time 73383513 ps
CPU time 1.16 seconds
Started Aug 05 06:08:31 PM PDT 24
Finished Aug 05 06:08:33 PM PDT 24
Peak memory 219020 kb
Host smart-560dc82f-26f2-48a8-a9ec-194ce844e6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590741498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3590741498
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3795968300
Short name T767
Test name
Test status
Simulation time 68548895 ps
CPU time 1.25 seconds
Started Aug 05 06:07:40 PM PDT 24
Finished Aug 05 06:07:42 PM PDT 24
Peak memory 215660 kb
Host smart-a2f1f6e9-d530-4bb0-8b7e-eeaf053ed897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795968300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3795968300
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3056366227
Short name T729
Test name
Test status
Simulation time 22330230 ps
CPU time 1.03 seconds
Started Aug 05 06:07:37 PM PDT 24
Finished Aug 05 06:07:39 PM PDT 24
Peak memory 206688 kb
Host smart-bf87562d-6207-4596-8988-31cfdff6a339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056366227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3056366227
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1766083841
Short name T156
Test name
Test status
Simulation time 17333346 ps
CPU time 0.88 seconds
Started Aug 05 06:07:46 PM PDT 24
Finished Aug 05 06:07:47 PM PDT 24
Peak memory 216200 kb
Host smart-4cad7775-4ac4-453d-ac41-7cd6c4f66b4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766083841 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1766083841
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3725258527
Short name T114
Test name
Test status
Simulation time 41255477 ps
CPU time 1.26 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 219712 kb
Host smart-b97c752e-56ea-4c9e-8161-ebda61ffe1a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725258527 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3725258527
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1788525535
Short name T681
Test name
Test status
Simulation time 29787738 ps
CPU time 1.26 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 219604 kb
Host smart-d5526355-bc12-42db-8f3b-32af8af6bb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788525535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1788525535
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.151547969
Short name T312
Test name
Test status
Simulation time 130015631 ps
CPU time 2.92 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 217664 kb
Host smart-4f89e47c-deac-4351-bc85-1e9896492bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151547969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.151547969
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3814783608
Short name T4
Test name
Test status
Simulation time 21442373 ps
CPU time 1.1 seconds
Started Aug 05 06:07:41 PM PDT 24
Finished Aug 05 06:07:42 PM PDT 24
Peak memory 215880 kb
Host smart-82369d61-095d-4d58-a277-f38ea3e6242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814783608 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3814783608
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.925995297
Short name T546
Test name
Test status
Simulation time 19140385 ps
CPU time 0.99 seconds
Started Aug 05 06:07:39 PM PDT 24
Finished Aug 05 06:07:40 PM PDT 24
Peak memory 207100 kb
Host smart-c7ac3331-80ee-40d4-b776-04b24e65b004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925995297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.925995297
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1318700352
Short name T914
Test name
Test status
Simulation time 36440114 ps
CPU time 0.9 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 215032 kb
Host smart-2d039d9a-93cd-46c5-adf6-a14153cbac51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318700352 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1318700352
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2242288598
Short name T677
Test name
Test status
Simulation time 275468495 ps
CPU time 5.33 seconds
Started Aug 05 06:07:37 PM PDT 24
Finished Aug 05 06:07:42 PM PDT 24
Peak memory 217328 kb
Host smart-33875698-df06-4b69-9128-400a09a848db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242288598 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2242288598
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1923574693
Short name T225
Test name
Test status
Simulation time 69659068061 ps
CPU time 1599.56 seconds
Started Aug 05 06:07:40 PM PDT 24
Finished Aug 05 06:34:20 PM PDT 24
Peak memory 222992 kb
Host smart-1c2ec600-3476-414b-ae02-3dd5875ce1cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923574693 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1923574693
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.3500006254
Short name T479
Test name
Test status
Simulation time 46615547 ps
CPU time 1.16 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 218476 kb
Host smart-55d7f2df-d770-4c02-9380-62b3f17b3cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500006254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.3500006254
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.444184077
Short name T722
Test name
Test status
Simulation time 22622475 ps
CPU time 0.96 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:36 PM PDT 24
Peak memory 218384 kb
Host smart-d5e9a574-d3db-4c83-a9d3-ffb36a0bc6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444184077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.444184077
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.987252988
Short name T602
Test name
Test status
Simulation time 121687036 ps
CPU time 1.67 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:08:47 PM PDT 24
Peak memory 218848 kb
Host smart-a266c052-7cbc-4acd-bd2f-5ec526f5ec41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987252988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.987252988
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.2748753172
Short name T280
Test name
Test status
Simulation time 46134785 ps
CPU time 1.15 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 218728 kb
Host smart-2a7d89f8-c8f2-40a4-afc9-ee7dad857933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748753172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.2748753172
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.818978814
Short name T241
Test name
Test status
Simulation time 59013395 ps
CPU time 0.96 seconds
Started Aug 05 06:08:44 PM PDT 24
Finished Aug 05 06:08:45 PM PDT 24
Peak memory 218604 kb
Host smart-22d245e7-1760-435a-bbe7-5dfd028430f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818978814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.818978814
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.5293423
Short name T313
Test name
Test status
Simulation time 48431096 ps
CPU time 1.22 seconds
Started Aug 05 06:08:45 PM PDT 24
Finished Aug 05 06:08:46 PM PDT 24
Peak memory 215272 kb
Host smart-4edb63d2-6736-4393-a7a6-7ce2720aa4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5293423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.5293423
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2984815724
Short name T936
Test name
Test status
Simulation time 37746394 ps
CPU time 1.21 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 218720 kb
Host smart-1eddf62b-b20f-43b7-b393-ec280862f3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984815724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2984815724
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3493340170
Short name T42
Test name
Test status
Simulation time 73831178 ps
CPU time 1.17 seconds
Started Aug 05 06:08:41 PM PDT 24
Finished Aug 05 06:08:43 PM PDT 24
Peak memory 225592 kb
Host smart-7875e5ff-4f81-478c-9f53-18012b7c4734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493340170 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3493340170
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1803283216
Short name T895
Test name
Test status
Simulation time 90466666 ps
CPU time 1.15 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 217316 kb
Host smart-323e8a35-c4e2-405c-b807-0dfa9822d55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803283216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1803283216
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.108537781
Short name T70
Test name
Test status
Simulation time 96532331 ps
CPU time 1.23 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 220500 kb
Host smart-a1a59ca9-0a84-4103-acb7-371acd282c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108537781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.108537781
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.451896175
Short name T9
Test name
Test status
Simulation time 35537324 ps
CPU time 1.09 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:08:41 PM PDT 24
Peak memory 218860 kb
Host smart-bbade6d8-8a3b-4592-89ce-53819ad46f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451896175 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.451896175
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1378985254
Short name T882
Test name
Test status
Simulation time 99817098 ps
CPU time 1.24 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:39 PM PDT 24
Peak memory 217288 kb
Host smart-e9ddbe0a-483a-47c9-b3f0-73b025f1d447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378985254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1378985254
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1338174593
Short name T634
Test name
Test status
Simulation time 24686543 ps
CPU time 1.21 seconds
Started Aug 05 06:08:31 PM PDT 24
Finished Aug 05 06:08:33 PM PDT 24
Peak memory 219428 kb
Host smart-db53f57e-c43e-4d3c-a70b-9fd36509d4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338174593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1338174593
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.4061229138
Short name T184
Test name
Test status
Simulation time 28017867 ps
CPU time 1.18 seconds
Started Aug 05 06:08:37 PM PDT 24
Finished Aug 05 06:08:38 PM PDT 24
Peak memory 217344 kb
Host smart-d51f2d55-4fdf-4d64-b583-22c8b72c2677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061229138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4061229138
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3813513532
Short name T552
Test name
Test status
Simulation time 47182880 ps
CPU time 1.64 seconds
Started Aug 05 06:08:37 PM PDT 24
Finished Aug 05 06:08:38 PM PDT 24
Peak memory 218724 kb
Host smart-07b92dd3-c85c-42dd-8c07-d08ad782153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813513532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3813513532
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3119502370
Short name T921
Test name
Test status
Simulation time 76028617 ps
CPU time 1.17 seconds
Started Aug 05 06:08:49 PM PDT 24
Finished Aug 05 06:08:50 PM PDT 24
Peak memory 220756 kb
Host smart-02c6f9e9-2950-4c82-973f-02de497db9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119502370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3119502370
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.4183197834
Short name T480
Test name
Test status
Simulation time 19675036 ps
CPU time 1.22 seconds
Started Aug 05 06:08:41 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 218680 kb
Host smart-35336520-7ea4-43c4-bb93-19f903d13906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183197834 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4183197834
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.365259099
Short name T434
Test name
Test status
Simulation time 41939410 ps
CPU time 1.22 seconds
Started Aug 05 06:08:58 PM PDT 24
Finished Aug 05 06:08:59 PM PDT 24
Peak memory 218720 kb
Host smart-bb20cb1c-0c60-4bf8-a1eb-5f4d9dbfc059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365259099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.365259099
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1484552726
Short name T980
Test name
Test status
Simulation time 47458211 ps
CPU time 1.16 seconds
Started Aug 05 06:08:44 PM PDT 24
Finished Aug 05 06:08:45 PM PDT 24
Peak memory 220796 kb
Host smart-627574f0-63e4-42fc-8db6-0878b0c0296a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484552726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1484552726
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2068816390
Short name T169
Test name
Test status
Simulation time 65356468 ps
CPU time 0.83 seconds
Started Aug 05 06:08:43 PM PDT 24
Finished Aug 05 06:08:44 PM PDT 24
Peak memory 218996 kb
Host smart-c149a602-23e8-4fb8-9b84-d8933a61d315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068816390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2068816390
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.330617175
Short name T381
Test name
Test status
Simulation time 123425381 ps
CPU time 1.24 seconds
Started Aug 05 06:08:39 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 218784 kb
Host smart-14d432d2-a0f9-4b97-8a56-23e70398e73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330617175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.330617175
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.3075047029
Short name T293
Test name
Test status
Simulation time 47923560 ps
CPU time 1.15 seconds
Started Aug 05 06:08:35 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 220516 kb
Host smart-6db2ab15-874d-4d13-a6aa-ec94db9badfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075047029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.3075047029
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1205888887
Short name T135
Test name
Test status
Simulation time 73051509 ps
CPU time 1.08 seconds
Started Aug 05 06:08:43 PM PDT 24
Finished Aug 05 06:08:45 PM PDT 24
Peak memory 219640 kb
Host smart-58c2ce42-8995-43bf-bde5-cc21ed6f0a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205888887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1205888887
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3822989451
Short name T502
Test name
Test status
Simulation time 99534905 ps
CPU time 1.36 seconds
Started Aug 05 06:08:54 PM PDT 24
Finished Aug 05 06:08:56 PM PDT 24
Peak memory 219856 kb
Host smart-46511d51-ea83-4f13-9485-584e4dcd97b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822989451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3822989451
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.43892683
Short name T215
Test name
Test status
Simulation time 71182248 ps
CPU time 1.17 seconds
Started Aug 05 06:08:44 PM PDT 24
Finished Aug 05 06:08:45 PM PDT 24
Peak memory 218568 kb
Host smart-453d423b-ad63-4d7a-b1d7-3b208123a324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43892683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.43892683
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.561845469
Short name T818
Test name
Test status
Simulation time 26241577 ps
CPU time 0.92 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:08:37 PM PDT 24
Peak memory 218476 kb
Host smart-6f2fc6e6-656e-4499-88f9-63e263bd92c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561845469 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.561845469
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1068058152
Short name T488
Test name
Test status
Simulation time 380049002 ps
CPU time 4.51 seconds
Started Aug 05 06:08:43 PM PDT 24
Finished Aug 05 06:08:47 PM PDT 24
Peak memory 218596 kb
Host smart-845951d0-cc4a-4d61-a7a2-3ef4c1d8f6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068058152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1068058152
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.2056665813
Short name T763
Test name
Test status
Simulation time 28737997 ps
CPU time 1.31 seconds
Started Aug 05 06:08:58 PM PDT 24
Finished Aug 05 06:08:59 PM PDT 24
Peak memory 215672 kb
Host smart-da1d0ec2-631e-4096-b3fa-3b02fca474fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056665813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.2056665813
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2875816108
Short name T127
Test name
Test status
Simulation time 26367241 ps
CPU time 1.14 seconds
Started Aug 05 06:08:46 PM PDT 24
Finished Aug 05 06:08:48 PM PDT 24
Peak memory 229520 kb
Host smart-295bae28-d046-46d7-840e-29a9ad025dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875816108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2875816108
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3556995147
Short name T499
Test name
Test status
Simulation time 55518417 ps
CPU time 1.18 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 217428 kb
Host smart-8d6eb34b-7c23-45ba-b36b-0d6f5b9f51a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556995147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3556995147
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.119929084
Short name T793
Test name
Test status
Simulation time 40915618 ps
CPU time 1.28 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 220556 kb
Host smart-03693d7e-f449-41c7-b802-843b9f9babe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119929084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.119929084
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.302806775
Short name T350
Test name
Test status
Simulation time 62859678 ps
CPU time 0.78 seconds
Started Aug 05 06:07:38 PM PDT 24
Finished Aug 05 06:07:39 PM PDT 24
Peak memory 205976 kb
Host smart-f59c74f2-b9fd-4f2b-9421-b71f77279c09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302806775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.302806775
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2074137723
Short name T953
Test name
Test status
Simulation time 18992890 ps
CPU time 0.81 seconds
Started Aug 05 06:07:46 PM PDT 24
Finished Aug 05 06:07:47 PM PDT 24
Peak memory 215388 kb
Host smart-89dc3ffd-b358-4809-a4dc-99f7a07eab2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074137723 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2074137723
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.2487809771
Short name T144
Test name
Test status
Simulation time 26271348 ps
CPU time 0.88 seconds
Started Aug 05 06:07:40 PM PDT 24
Finished Aug 05 06:07:41 PM PDT 24
Peak memory 218164 kb
Host smart-5d70bb18-3f9f-4417-8304-fa2e14935f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487809771 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2487809771
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1678637478
Short name T775
Test name
Test status
Simulation time 71450914 ps
CPU time 1.14 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 217188 kb
Host smart-1264803a-ba5c-4895-94cc-f03858879b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678637478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1678637478
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2392111541
Short name T48
Test name
Test status
Simulation time 28349751 ps
CPU time 1.08 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 224024 kb
Host smart-b31e3f0a-b61f-42a6-944b-8af5fdae9f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392111541 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2392111541
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3255268376
Short name T60
Test name
Test status
Simulation time 54396208 ps
CPU time 0.94 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 207072 kb
Host smart-6a105036-7f0e-4e12-8d28-1b2787373b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255268376 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3255268376
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.514764175
Short name T412
Test name
Test status
Simulation time 22910569 ps
CPU time 0.99 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 215208 kb
Host smart-0c3deef7-5e71-4a09-85a1-b588fe8321ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514764175 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.514764175
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1165697834
Short name T561
Test name
Test status
Simulation time 38245950 ps
CPU time 1 seconds
Started Aug 05 06:07:33 PM PDT 24
Finished Aug 05 06:07:34 PM PDT 24
Peak memory 206888 kb
Host smart-8dbf97d2-19eb-4461-9a2e-0f2d78f7d89f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165697834 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1165697834
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3855348749
Short name T415
Test name
Test status
Simulation time 109603022019 ps
CPU time 2032.78 seconds
Started Aug 05 06:07:39 PM PDT 24
Finished Aug 05 06:41:32 PM PDT 24
Peak memory 229128 kb
Host smart-ead2944c-13b9-41a1-843e-1266408e860d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855348749 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3855348749
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.3994350121
Short name T600
Test name
Test status
Simulation time 151946121 ps
CPU time 1.19 seconds
Started Aug 05 06:08:44 PM PDT 24
Finished Aug 05 06:08:46 PM PDT 24
Peak memory 221436 kb
Host smart-e7e0d140-9bf0-4ca0-a99c-188803e9a53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994350121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3994350121
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2138247934
Short name T171
Test name
Test status
Simulation time 21243380 ps
CPU time 1.13 seconds
Started Aug 05 06:08:38 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 219484 kb
Host smart-c2c577b5-5312-497d-bbf7-b502d92464fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138247934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2138247934
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.206841388
Short name T12
Test name
Test status
Simulation time 103867929 ps
CPU time 1.1 seconds
Started Aug 05 06:08:41 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 217600 kb
Host smart-d8af88de-e94c-4a96-bda2-45bbf085ffab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206841388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.206841388
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.886864157
Short name T165
Test name
Test status
Simulation time 27691205 ps
CPU time 1.23 seconds
Started Aug 05 06:08:37 PM PDT 24
Finished Aug 05 06:08:38 PM PDT 24
Peak memory 219912 kb
Host smart-96fa9ffe-3023-4958-af49-11f14c849019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886864157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.886864157
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.4291227440
Short name T212
Test name
Test status
Simulation time 61145470 ps
CPU time 1.19 seconds
Started Aug 05 06:08:44 PM PDT 24
Finished Aug 05 06:08:45 PM PDT 24
Peak memory 225692 kb
Host smart-f0ce7d20-5c68-46db-9d8b-c94eb41a5481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291227440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.4291227440
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.58387109
Short name T417
Test name
Test status
Simulation time 36068186 ps
CPU time 1.35 seconds
Started Aug 05 06:08:36 PM PDT 24
Finished Aug 05 06:08:38 PM PDT 24
Peak memory 217212 kb
Host smart-144f9938-f5d0-4379-8edd-ce5b6442d5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58387109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.58387109
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3961390497
Short name T696
Test name
Test status
Simulation time 25030418 ps
CPU time 1.18 seconds
Started Aug 05 06:08:40 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 218716 kb
Host smart-753b56b6-eaa7-4dde-954f-057c15743843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961390497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3961390497
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_genbits.3299051901
Short name T666
Test name
Test status
Simulation time 176909333 ps
CPU time 1.43 seconds
Started Aug 05 06:08:43 PM PDT 24
Finished Aug 05 06:08:44 PM PDT 24
Peak memory 218752 kb
Host smart-3d8fa7ab-a567-46fb-b7aa-8b22458147f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299051901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3299051901
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.981562629
Short name T984
Test name
Test status
Simulation time 150243132 ps
CPU time 1.15 seconds
Started Aug 05 06:08:45 PM PDT 24
Finished Aug 05 06:08:46 PM PDT 24
Peak memory 218556 kb
Host smart-d40dea0d-9350-4953-ad45-ac08f3b5a448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981562629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.981562629
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1783791713
Short name T203
Test name
Test status
Simulation time 103325621 ps
CPU time 0.94 seconds
Started Aug 05 06:09:00 PM PDT 24
Finished Aug 05 06:09:01 PM PDT 24
Peak memory 219708 kb
Host smart-bfba53b2-6dee-4c19-af4c-8399ddd52aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783791713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1783791713
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1687586995
Short name T773
Test name
Test status
Simulation time 92140528 ps
CPU time 1.16 seconds
Started Aug 05 06:08:46 PM PDT 24
Finished Aug 05 06:08:48 PM PDT 24
Peak memory 217460 kb
Host smart-e39ef88d-c38e-486a-a7db-8b31f8584cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687586995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1687586995
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.4248444418
Short name T67
Test name
Test status
Simulation time 39874049 ps
CPU time 1.16 seconds
Started Aug 05 06:08:58 PM PDT 24
Finished Aug 05 06:08:59 PM PDT 24
Peak memory 218636 kb
Host smart-1ff97f57-8ae2-494f-91e4-80d19a9fdf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248444418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.4248444418
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3544349267
Short name T476
Test name
Test status
Simulation time 24415430 ps
CPU time 1.09 seconds
Started Aug 05 06:08:56 PM PDT 24
Finished Aug 05 06:08:57 PM PDT 24
Peak memory 224092 kb
Host smart-22c7d282-3bad-4c67-8919-8ab318d887c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544349267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3544349267
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.4229816372
Short name T986
Test name
Test status
Simulation time 36634443 ps
CPU time 1.14 seconds
Started Aug 05 06:08:44 PM PDT 24
Finished Aug 05 06:08:45 PM PDT 24
Peak memory 217364 kb
Host smart-9b87dcc8-1043-4d20-abe5-5690b61cdf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229816372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.4229816372
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.442406852
Short name T884
Test name
Test status
Simulation time 50457398 ps
CPU time 1.23 seconds
Started Aug 05 06:08:54 PM PDT 24
Finished Aug 05 06:08:55 PM PDT 24
Peak memory 220328 kb
Host smart-313fc613-a523-401b-85d6-d7469de5130d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442406852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.442406852
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.577475510
Short name T95
Test name
Test status
Simulation time 48114151 ps
CPU time 0.96 seconds
Started Aug 05 06:08:58 PM PDT 24
Finished Aug 05 06:08:59 PM PDT 24
Peak memory 219740 kb
Host smart-5cd056fe-dee8-42b9-bebb-c13c4e8caf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577475510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.577475510
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.479302919
Short name T437
Test name
Test status
Simulation time 42024112 ps
CPU time 1.53 seconds
Started Aug 05 06:08:48 PM PDT 24
Finished Aug 05 06:08:50 PM PDT 24
Peak memory 217556 kb
Host smart-63165157-3c1f-4fbf-9a09-2ddd70b4d89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479302919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.479302919
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.3079618975
Short name T106
Test name
Test status
Simulation time 99218701 ps
CPU time 1.3 seconds
Started Aug 05 06:08:44 PM PDT 24
Finished Aug 05 06:08:45 PM PDT 24
Peak memory 219956 kb
Host smart-e36901c1-16fd-4f18-8fa3-51c08b21f43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079618975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3079618975
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.262894131
Short name T574
Test name
Test status
Simulation time 36036387 ps
CPU time 0.89 seconds
Started Aug 05 06:08:57 PM PDT 24
Finished Aug 05 06:08:58 PM PDT 24
Peak memory 218416 kb
Host smart-3e769ab4-3ba2-4f11-a5f3-b8a7991a2c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262894131 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.262894131
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2555215211
Short name T368
Test name
Test status
Simulation time 61656659 ps
CPU time 2.09 seconds
Started Aug 05 06:09:00 PM PDT 24
Finished Aug 05 06:09:02 PM PDT 24
Peak memory 215352 kb
Host smart-57c08ae4-1d22-42ff-b874-27967d8a1801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555215211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2555215211
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.94780760
Short name T951
Test name
Test status
Simulation time 47254247 ps
CPU time 1.15 seconds
Started Aug 05 06:08:48 PM PDT 24
Finished Aug 05 06:08:49 PM PDT 24
Peak memory 218792 kb
Host smart-9f949348-8bf2-4a73-a72e-a2a075b66793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94780760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.94780760
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.365037795
Short name T196
Test name
Test status
Simulation time 21623059 ps
CPU time 1.06 seconds
Started Aug 05 06:08:56 PM PDT 24
Finished Aug 05 06:08:58 PM PDT 24
Peak memory 219512 kb
Host smart-19cda9d0-8a58-473f-856d-bdbc9fa169b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365037795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.365037795
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2963155843
Short name T242
Test name
Test status
Simulation time 53844597 ps
CPU time 1.28 seconds
Started Aug 05 06:08:58 PM PDT 24
Finished Aug 05 06:09:00 PM PDT 24
Peak memory 217232 kb
Host smart-a1fde98a-313f-4bd0-9d64-a81fa5c6250f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963155843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2963155843
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.4201691248
Short name T526
Test name
Test status
Simulation time 250101206 ps
CPU time 1.21 seconds
Started Aug 05 06:08:46 PM PDT 24
Finished Aug 05 06:08:48 PM PDT 24
Peak memory 219464 kb
Host smart-9baa37f5-5534-426b-9090-78dbf175dc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201691248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.4201691248
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.4059947294
Short name T769
Test name
Test status
Simulation time 67429588 ps
CPU time 1 seconds
Started Aug 05 06:08:47 PM PDT 24
Finished Aug 05 06:08:53 PM PDT 24
Peak memory 220644 kb
Host smart-3cecbd17-8919-41e8-81eb-ca1dfb1170ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059947294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.4059947294
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3211706463
Short name T496
Test name
Test status
Simulation time 50695711 ps
CPU time 1.29 seconds
Started Aug 05 06:08:50 PM PDT 24
Finished Aug 05 06:08:52 PM PDT 24
Peak memory 218668 kb
Host smart-f4b75513-680c-43d4-acd8-1e8c6e08b905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211706463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3211706463
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1301356798
Short name T883
Test name
Test status
Simulation time 28192998 ps
CPU time 1.24 seconds
Started Aug 05 06:08:52 PM PDT 24
Finished Aug 05 06:08:53 PM PDT 24
Peak memory 218584 kb
Host smart-075fccbf-9c59-4e7d-b6e8-dc648d2e43d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301356798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1301356798
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2983227726
Short name T15
Test name
Test status
Simulation time 77530861 ps
CPU time 1.27 seconds
Started Aug 05 06:09:04 PM PDT 24
Finished Aug 05 06:09:05 PM PDT 24
Peak memory 225668 kb
Host smart-04d3dbee-6fd8-4ea1-9a65-5815b675e6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983227726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2983227726
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2651406615
Short name T360
Test name
Test status
Simulation time 47761485 ps
CPU time 1.47 seconds
Started Aug 05 06:08:44 PM PDT 24
Finished Aug 05 06:08:46 PM PDT 24
Peak memory 217260 kb
Host smart-f2ccc075-8deb-4fd1-b42d-f5619f2e754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651406615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2651406615
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3418769485
Short name T435
Test name
Test status
Simulation time 38234909 ps
CPU time 1.15 seconds
Started Aug 05 06:07:38 PM PDT 24
Finished Aug 05 06:07:40 PM PDT 24
Peak memory 220724 kb
Host smart-2c94dce7-3c11-42fc-8159-3fea2aad5a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418769485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3418769485
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.198600370
Short name T581
Test name
Test status
Simulation time 34352034 ps
CPU time 1 seconds
Started Aug 05 06:07:39 PM PDT 24
Finished Aug 05 06:07:40 PM PDT 24
Peak memory 215140 kb
Host smart-534b2fa6-9600-424e-9ddf-dea36a96bda1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198600370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.198600370
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.305842935
Short name T207
Test name
Test status
Simulation time 66086551 ps
CPU time 0.86 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 216204 kb
Host smart-3fed020e-ec92-44a1-90f8-34a6ffcd93ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305842935 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.305842935
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1361438944
Short name T123
Test name
Test status
Simulation time 41269083 ps
CPU time 1.43 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 216876 kb
Host smart-21fb6bab-a735-4f97-a094-3007c0219b82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361438944 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1361438944
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2589471947
Short name T247
Test name
Test status
Simulation time 34922974 ps
CPU time 1.07 seconds
Started Aug 05 06:07:39 PM PDT 24
Finished Aug 05 06:07:40 PM PDT 24
Peak memory 218712 kb
Host smart-7f7c87e4-fca2-4496-823d-1fc24eb6bfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589471947 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2589471947
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3892760300
Short name T484
Test name
Test status
Simulation time 101937660 ps
CPU time 1.21 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 218976 kb
Host smart-0a0422bd-32a5-4ce3-b04f-ed4345eed98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892760300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3892760300
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1527023139
Short name T84
Test name
Test status
Simulation time 19694765 ps
CPU time 1.15 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 215804 kb
Host smart-68d343a6-25bd-4885-ab13-56c8ee53668b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527023139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1527023139
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3410282349
Short name T711
Test name
Test status
Simulation time 39804379 ps
CPU time 0.89 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 207076 kb
Host smart-ca9fff2d-3313-43ca-97fc-2dae39c98d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410282349 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3410282349
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2433862526
Short name T344
Test name
Test status
Simulation time 16540646 ps
CPU time 1.05 seconds
Started Aug 05 06:07:41 PM PDT 24
Finished Aug 05 06:07:42 PM PDT 24
Peak memory 215264 kb
Host smart-1ad7eb59-fbf4-448f-b066-c9f6a38e9ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433862526 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2433862526
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2074389872
Short name T250
Test name
Test status
Simulation time 689210176 ps
CPU time 3.68 seconds
Started Aug 05 06:07:40 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 218524 kb
Host smart-a737f59e-27c7-46e8-ac3e-b42dc094e007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074389872 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2074389872
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2885952951
Short name T228
Test name
Test status
Simulation time 55594779636 ps
CPU time 1371.11 seconds
Started Aug 05 06:07:46 PM PDT 24
Finished Aug 05 06:30:37 PM PDT 24
Peak memory 224220 kb
Host smart-e42e041f-ac1d-4930-901d-ce9edaf2f0d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885952951 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2885952951
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2858085396
Short name T300
Test name
Test status
Simulation time 49606024 ps
CPU time 1.16 seconds
Started Aug 05 06:08:52 PM PDT 24
Finished Aug 05 06:08:53 PM PDT 24
Peak memory 219620 kb
Host smart-163f8094-cd13-40fe-b1af-5d11c8089278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858085396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2858085396
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1597829550
Short name T653
Test name
Test status
Simulation time 18335271 ps
CPU time 1.14 seconds
Started Aug 05 06:08:45 PM PDT 24
Finished Aug 05 06:08:46 PM PDT 24
Peak memory 224020 kb
Host smart-6579f7db-970f-44b9-8ad4-c0cd68d7a2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597829550 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1597829550
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3468735319
Short name T179
Test name
Test status
Simulation time 94713733 ps
CPU time 1.5 seconds
Started Aug 05 06:09:16 PM PDT 24
Finished Aug 05 06:09:18 PM PDT 24
Peak memory 219040 kb
Host smart-0209b5bc-1e93-49f9-836e-ae39c4ae7d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468735319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3468735319
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2850635484
Short name T150
Test name
Test status
Simulation time 67479303 ps
CPU time 1.11 seconds
Started Aug 05 06:09:09 PM PDT 24
Finished Aug 05 06:09:10 PM PDT 24
Peak memory 215676 kb
Host smart-da498a69-1286-4374-bb1a-ef92bba6ea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850635484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2850635484
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1896729386
Short name T142
Test name
Test status
Simulation time 53663530 ps
CPU time 0.96 seconds
Started Aug 05 06:09:11 PM PDT 24
Finished Aug 05 06:09:12 PM PDT 24
Peak memory 218240 kb
Host smart-39962bd4-1606-4e8b-93a4-2ee3c8d8797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896729386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1896729386
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3042254481
Short name T753
Test name
Test status
Simulation time 34528327 ps
CPU time 1.35 seconds
Started Aug 05 06:08:53 PM PDT 24
Finished Aug 05 06:08:55 PM PDT 24
Peak memory 218388 kb
Host smart-7b05e948-5028-4297-9019-c38dabb8ff53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042254481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3042254481
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.290400614
Short name T73
Test name
Test status
Simulation time 97980395 ps
CPU time 1.26 seconds
Started Aug 05 06:08:54 PM PDT 24
Finished Aug 05 06:08:55 PM PDT 24
Peak memory 219820 kb
Host smart-0f4b7b08-191f-4d76-a50f-82c30e251ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290400614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.290400614
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3447727967
Short name T683
Test name
Test status
Simulation time 72754130 ps
CPU time 0.78 seconds
Started Aug 05 06:08:58 PM PDT 24
Finished Aug 05 06:08:59 PM PDT 24
Peak memory 218452 kb
Host smart-8fef0eb1-9283-4d61-992f-117aaeafd308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447727967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3447727967
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.4289218595
Short name T947
Test name
Test status
Simulation time 39469096 ps
CPU time 1.51 seconds
Started Aug 05 06:08:45 PM PDT 24
Finished Aug 05 06:08:46 PM PDT 24
Peak memory 218808 kb
Host smart-691210f4-8f24-4a3d-85de-fa07e1d72af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289218595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.4289218595
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3798383339
Short name T126
Test name
Test status
Simulation time 32326961 ps
CPU time 1.37 seconds
Started Aug 05 06:08:53 PM PDT 24
Finished Aug 05 06:08:54 PM PDT 24
Peak memory 220028 kb
Host smart-c01db3ba-fbeb-4bf0-aad1-90314f9ba2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798383339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3798383339
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.4022685680
Short name T197
Test name
Test status
Simulation time 131959862 ps
CPU time 1.33 seconds
Started Aug 05 06:09:04 PM PDT 24
Finished Aug 05 06:09:06 PM PDT 24
Peak memory 225696 kb
Host smart-0a8b63f4-7230-47b0-b47c-d9992471b431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022685680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4022685680
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2674544065
Short name T702
Test name
Test status
Simulation time 46640842 ps
CPU time 1.48 seconds
Started Aug 05 06:08:44 PM PDT 24
Finished Aug 05 06:08:46 PM PDT 24
Peak memory 218440 kb
Host smart-2b519416-98a7-49dd-a3c4-b2a33a8ab338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674544065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2674544065
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2973211621
Short name T252
Test name
Test status
Simulation time 410101574 ps
CPU time 1.41 seconds
Started Aug 05 06:08:48 PM PDT 24
Finished Aug 05 06:08:49 PM PDT 24
Peak memory 219888 kb
Host smart-18bb954f-a48a-402f-accd-426ee2cd2cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973211621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2973211621
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1007384922
Short name T93
Test name
Test status
Simulation time 32974415 ps
CPU time 1.16 seconds
Started Aug 05 06:09:08 PM PDT 24
Finished Aug 05 06:09:09 PM PDT 24
Peak memory 229724 kb
Host smart-ee90e686-ecc6-4517-97c2-41e79819c6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007384922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1007384922
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3333423011
Short name T676
Test name
Test status
Simulation time 121290902 ps
CPU time 1.25 seconds
Started Aug 05 06:08:47 PM PDT 24
Finished Aug 05 06:08:48 PM PDT 24
Peak memory 217340 kb
Host smart-10fb5f70-074a-458f-9f6c-22d7dccf111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333423011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3333423011
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2292087233
Short name T941
Test name
Test status
Simulation time 26365278 ps
CPU time 1.18 seconds
Started Aug 05 06:09:09 PM PDT 24
Finished Aug 05 06:09:11 PM PDT 24
Peak memory 219652 kb
Host smart-5ebdecbb-e14d-4215-ad2a-c6d716b77537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292087233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2292087233
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.2545840990
Short name T46
Test name
Test status
Simulation time 19537573 ps
CPU time 1.2 seconds
Started Aug 05 06:08:57 PM PDT 24
Finished Aug 05 06:08:58 PM PDT 24
Peak memory 224144 kb
Host smart-04410346-7e94-428b-8a37-ae5b48dbf286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545840990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2545840990
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1943372995
Short name T378
Test name
Test status
Simulation time 35646358 ps
CPU time 1.64 seconds
Started Aug 05 06:09:00 PM PDT 24
Finished Aug 05 06:09:01 PM PDT 24
Peak memory 215288 kb
Host smart-66b7f1d5-7894-433d-8091-0544d95da287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943372995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1943372995
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1998965186
Short name T448
Test name
Test status
Simulation time 24660295 ps
CPU time 1.19 seconds
Started Aug 05 06:09:16 PM PDT 24
Finished Aug 05 06:09:17 PM PDT 24
Peak memory 220692 kb
Host smart-a91ee900-074d-4516-9952-9bb1a1e1f636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998965186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1998965186
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3930398734
Short name T170
Test name
Test status
Simulation time 23307693 ps
CPU time 0.9 seconds
Started Aug 05 06:09:00 PM PDT 24
Finished Aug 05 06:09:01 PM PDT 24
Peak memory 219120 kb
Host smart-c727c460-2190-4e61-8629-aaf56d99c715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930398734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3930398734
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.4212638799
Short name T977
Test name
Test status
Simulation time 35094436 ps
CPU time 1.23 seconds
Started Aug 05 06:08:53 PM PDT 24
Finished Aug 05 06:08:54 PM PDT 24
Peak memory 218820 kb
Host smart-f063c133-a168-4a5d-a704-3d856b63efc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212638799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.4212638799
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1133776596
Short name T959
Test name
Test status
Simulation time 21351130 ps
CPU time 1.14 seconds
Started Aug 05 06:09:27 PM PDT 24
Finished Aug 05 06:09:29 PM PDT 24
Peak memory 219656 kb
Host smart-2236c3b9-f5c6-46ae-b82a-d0db57fb589e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133776596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1133776596
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2928746243
Short name T911
Test name
Test status
Simulation time 48936906 ps
CPU time 1.78 seconds
Started Aug 05 06:09:12 PM PDT 24
Finished Aug 05 06:09:13 PM PDT 24
Peak memory 218596 kb
Host smart-919c5c6f-5ac5-46e3-b6bb-fa055e35cf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928746243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2928746243
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3528962497
Short name T859
Test name
Test status
Simulation time 41202584 ps
CPU time 1.12 seconds
Started Aug 05 06:09:03 PM PDT 24
Finished Aug 05 06:09:04 PM PDT 24
Peak memory 215676 kb
Host smart-b4b6da65-d477-4c5b-903e-036d719a5512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528962497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3528962497
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2391460726
Short name T579
Test name
Test status
Simulation time 33190069 ps
CPU time 0.88 seconds
Started Aug 05 06:09:08 PM PDT 24
Finished Aug 05 06:09:09 PM PDT 24
Peak memory 218260 kb
Host smart-8dbd4448-a684-4095-a2f5-feb769b5bbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391460726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2391460726
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.178065461
Short name T439
Test name
Test status
Simulation time 75045214 ps
CPU time 2.66 seconds
Started Aug 05 06:09:06 PM PDT 24
Finished Aug 05 06:09:09 PM PDT 24
Peak memory 219116 kb
Host smart-5ee6537d-c4f1-43ff-b4db-388c3748b3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178065461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.178065461
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.646905267
Short name T183
Test name
Test status
Simulation time 25149368 ps
CPU time 1.25 seconds
Started Aug 05 06:09:09 PM PDT 24
Finished Aug 05 06:09:10 PM PDT 24
Peak memory 219832 kb
Host smart-74ddb108-e34d-49d9-bcf4-c91b1210e3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646905267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.646905267
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1279698174
Short name T7
Test name
Test status
Simulation time 74579277 ps
CPU time 0.9 seconds
Started Aug 05 06:09:09 PM PDT 24
Finished Aug 05 06:09:10 PM PDT 24
Peak memory 219556 kb
Host smart-fe32f267-7181-475e-bd1f-06fb11017717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279698174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1279698174
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.1639218386
Short name T219
Test name
Test status
Simulation time 32951174 ps
CPU time 1.37 seconds
Started Aug 05 06:07:43 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 215676 kb
Host smart-320b6513-eed6-4841-8ba7-9afac6ae3858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639218386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1639218386
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1914556176
Short name T432
Test name
Test status
Simulation time 45999469 ps
CPU time 0.89 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:44 PM PDT 24
Peak memory 214884 kb
Host smart-c22864ac-7d85-47ab-b235-34f93b057706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914556176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1914556176
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1556247905
Short name T672
Test name
Test status
Simulation time 13966547 ps
CPU time 0.96 seconds
Started Aug 05 06:07:42 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 216412 kb
Host smart-23fe5182-53e5-421b-8c00-865b96b6acc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556247905 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1556247905
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2085909368
Short name T185
Test name
Test status
Simulation time 60523963 ps
CPU time 1.17 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 218588 kb
Host smart-0daf93a0-21d8-48b5-949e-9729e960ef48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085909368 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2085909368
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1882949027
Short name T200
Test name
Test status
Simulation time 88966303 ps
CPU time 0.86 seconds
Started Aug 05 06:07:45 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 218568 kb
Host smart-0e174500-5e3e-4a56-b9cd-82973c9d6cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882949027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1882949027
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2008634487
Short name T714
Test name
Test status
Simulation time 50157502 ps
CPU time 1.55 seconds
Started Aug 05 06:07:44 PM PDT 24
Finished Aug 05 06:07:46 PM PDT 24
Peak memory 218436 kb
Host smart-b3720f85-0e80-4b5e-9a8c-f109ba5113b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008634487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2008634487
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3084092061
Short name T543
Test name
Test status
Simulation time 98260170 ps
CPU time 0.89 seconds
Started Aug 05 06:07:38 PM PDT 24
Finished Aug 05 06:07:39 PM PDT 24
Peak memory 215172 kb
Host smart-e20f857f-f541-4e5f-a780-973417bcc717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084092061 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3084092061
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2283725591
Short name T418
Test name
Test status
Simulation time 33593091 ps
CPU time 0.88 seconds
Started Aug 05 06:07:48 PM PDT 24
Finished Aug 05 06:07:50 PM PDT 24
Peak memory 207108 kb
Host smart-334d305d-c3b4-4947-9417-597e20dffc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283725591 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2283725591
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3102230054
Short name T756
Test name
Test status
Simulation time 42640765 ps
CPU time 0.89 seconds
Started Aug 05 06:07:38 PM PDT 24
Finished Aug 05 06:07:39 PM PDT 24
Peak memory 215288 kb
Host smart-e73ca72c-9843-4d84-b972-fe37a0b1f30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102230054 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3102230054
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.206071611
Short name T251
Test name
Test status
Simulation time 429914984 ps
CPU time 4.91 seconds
Started Aug 05 06:07:36 PM PDT 24
Finished Aug 05 06:07:41 PM PDT 24
Peak memory 217280 kb
Host smart-f21dd595-eaa4-4181-a9af-4c7fbf6912ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206071611 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.206071611
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3806331532
Short name T237
Test name
Test status
Simulation time 41554493038 ps
CPU time 249.25 seconds
Started Aug 05 06:07:49 PM PDT 24
Finished Aug 05 06:12:03 PM PDT 24
Peak memory 218032 kb
Host smart-66e37731-3173-4229-8e89-7904af514c94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806331532 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3806331532
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.4153862617
Short name T617
Test name
Test status
Simulation time 26884103 ps
CPU time 1.2 seconds
Started Aug 05 06:08:57 PM PDT 24
Finished Aug 05 06:08:58 PM PDT 24
Peak memory 220048 kb
Host smart-2f2a3116-03cb-43e8-a66b-aaf9996ed76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153862617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.4153862617
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1283124519
Short name T515
Test name
Test status
Simulation time 41571118 ps
CPU time 1.21 seconds
Started Aug 05 06:09:01 PM PDT 24
Finished Aug 05 06:09:02 PM PDT 24
Peak memory 225816 kb
Host smart-68986a20-4c2b-490e-9a50-f0f1ee3d7454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283124519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1283124519
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2604279570
Short name T656
Test name
Test status
Simulation time 52304053 ps
CPU time 1.13 seconds
Started Aug 05 06:09:03 PM PDT 24
Finished Aug 05 06:09:04 PM PDT 24
Peak memory 218968 kb
Host smart-1bdf8388-7725-4090-a956-65db8737443c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604279570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2604279570
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.4273623823
Short name T715
Test name
Test status
Simulation time 24773678 ps
CPU time 1.16 seconds
Started Aug 05 06:09:07 PM PDT 24
Finished Aug 05 06:09:09 PM PDT 24
Peak memory 219768 kb
Host smart-7bc7e557-3d79-4ef0-8c98-d028aebc0564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273623823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.4273623823
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3889744030
Short name T782
Test name
Test status
Simulation time 27512822 ps
CPU time 0.95 seconds
Started Aug 05 06:09:08 PM PDT 24
Finished Aug 05 06:09:09 PM PDT 24
Peak memory 223752 kb
Host smart-d0a634fb-12b8-447a-8afe-7ee90892a9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889744030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3889744030
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1135839498
Short name T354
Test name
Test status
Simulation time 21993013 ps
CPU time 1.15 seconds
Started Aug 05 06:09:00 PM PDT 24
Finished Aug 05 06:09:01 PM PDT 24
Peak memory 219824 kb
Host smart-89b0d0cf-5d42-4018-acf6-1837d84f7782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135839498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1135839498
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_genbits.52922271
Short name T618
Test name
Test status
Simulation time 53710644 ps
CPU time 1.5 seconds
Started Aug 05 06:09:18 PM PDT 24
Finished Aug 05 06:09:20 PM PDT 24
Peak memory 218880 kb
Host smart-c14602d9-07ae-482f-9e61-c3fbdaa590ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52922271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.52922271
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.686179887
Short name T622
Test name
Test status
Simulation time 49185440 ps
CPU time 1.1 seconds
Started Aug 05 06:09:05 PM PDT 24
Finished Aug 05 06:09:06 PM PDT 24
Peak memory 218696 kb
Host smart-969a8686-d38c-475e-978f-8cf3c20d2bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686179887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.686179887
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2908691429
Short name T846
Test name
Test status
Simulation time 30239517 ps
CPU time 0.94 seconds
Started Aug 05 06:08:54 PM PDT 24
Finished Aug 05 06:08:55 PM PDT 24
Peak memory 229440 kb
Host smart-b01c81dd-77f8-41b5-aee0-1b00dc4501ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908691429 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2908691429
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3668923667
Short name T501
Test name
Test status
Simulation time 72283729 ps
CPU time 1.06 seconds
Started Aug 05 06:09:10 PM PDT 24
Finished Aug 05 06:09:12 PM PDT 24
Peak memory 217420 kb
Host smart-b493623a-a448-4d44-b79e-42f825b67eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668923667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3668923667
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2264294883
Short name T292
Test name
Test status
Simulation time 26083889 ps
CPU time 1.24 seconds
Started Aug 05 06:08:59 PM PDT 24
Finished Aug 05 06:09:00 PM PDT 24
Peak memory 219640 kb
Host smart-635106fc-6eb4-47ad-a5b9-4930dc27f5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264294883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2264294883
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3863448120
Short name T92
Test name
Test status
Simulation time 20394763 ps
CPU time 1.11 seconds
Started Aug 05 06:09:12 PM PDT 24
Finished Aug 05 06:09:13 PM PDT 24
Peak memory 219528 kb
Host smart-014a7a94-1061-4803-992c-62fc861cfab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863448120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3863448120
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3160899349
Short name T749
Test name
Test status
Simulation time 31932168 ps
CPU time 1.29 seconds
Started Aug 05 06:08:50 PM PDT 24
Finished Aug 05 06:08:51 PM PDT 24
Peak memory 217440 kb
Host smart-956cc274-ed7a-4b82-93aa-6a73add7e9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160899349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3160899349
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.1074294429
Short name T706
Test name
Test status
Simulation time 127258826 ps
CPU time 1.15 seconds
Started Aug 05 06:09:04 PM PDT 24
Finished Aug 05 06:09:05 PM PDT 24
Peak memory 220924 kb
Host smart-e61a34a8-1d0f-4382-b1b4-d53fb3d38199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074294429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.1074294429
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1851282474
Short name T850
Test name
Test status
Simulation time 26840233 ps
CPU time 0.89 seconds
Started Aug 05 06:09:04 PM PDT 24
Finished Aug 05 06:09:06 PM PDT 24
Peak memory 218296 kb
Host smart-8cb8f40d-1a1b-4505-a697-c66635044ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851282474 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1851282474
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/96.edn_alert.1472120989
Short name T796
Test name
Test status
Simulation time 72602376 ps
CPU time 1.19 seconds
Started Aug 05 06:09:02 PM PDT 24
Finished Aug 05 06:09:03 PM PDT 24
Peak memory 218320 kb
Host smart-74c5044a-a7c6-4938-91ee-d856e4a1db5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472120989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1472120989
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3346427800
Short name T64
Test name
Test status
Simulation time 36645252 ps
CPU time 1.06 seconds
Started Aug 05 06:09:11 PM PDT 24
Finished Aug 05 06:09:12 PM PDT 24
Peak memory 220664 kb
Host smart-8b9ed664-3728-49e0-8ea5-3291294e9a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346427800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3346427800
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3703376909
Short name T494
Test name
Test status
Simulation time 46419079 ps
CPU time 1.23 seconds
Started Aug 05 06:09:07 PM PDT 24
Finished Aug 05 06:09:08 PM PDT 24
Peak memory 219672 kb
Host smart-7d8227f2-6fc4-4706-9156-81578b390d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703376909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3703376909
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1413493709
Short name T736
Test name
Test status
Simulation time 94782252 ps
CPU time 1.16 seconds
Started Aug 05 06:09:00 PM PDT 24
Finished Aug 05 06:09:01 PM PDT 24
Peak memory 219792 kb
Host smart-bac7792a-f58a-4828-a210-dea7b4dde3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413493709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1413493709
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.2423150173
Short name T201
Test name
Test status
Simulation time 20180013 ps
CPU time 1.05 seconds
Started Aug 05 06:09:07 PM PDT 24
Finished Aug 05 06:09:08 PM PDT 24
Peak memory 219580 kb
Host smart-280b915e-594c-4945-b8ee-895bd5aa9556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423150173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2423150173
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3545849503
Short name T805
Test name
Test status
Simulation time 29775150 ps
CPU time 1.18 seconds
Started Aug 05 06:09:07 PM PDT 24
Finished Aug 05 06:09:08 PM PDT 24
Peak memory 218644 kb
Host smart-b3778f78-a326-4e90-88a8-780224f63241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545849503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3545849503
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.3090660277
Short name T99
Test name
Test status
Simulation time 27020933 ps
CPU time 1.28 seconds
Started Aug 05 06:09:01 PM PDT 24
Finished Aug 05 06:09:02 PM PDT 24
Peak memory 219508 kb
Host smart-8eacd95b-95ff-4db8-968e-078f1113eca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090660277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3090660277
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2299002117
Short name T545
Test name
Test status
Simulation time 52294331 ps
CPU time 1.04 seconds
Started Aug 05 06:09:06 PM PDT 24
Finished Aug 05 06:09:07 PM PDT 24
Peak memory 219456 kb
Host smart-4041971d-7e6a-4579-99fe-44e6a38f7228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299002117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2299002117
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.195191740
Short name T817
Test name
Test status
Simulation time 50998160 ps
CPU time 1.38 seconds
Started Aug 05 06:09:18 PM PDT 24
Finished Aug 05 06:09:20 PM PDT 24
Peak memory 218632 kb
Host smart-5bf042a6-50bf-465d-b8b4-4fa3fb4eebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195191740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.195191740
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.4180918103
Short name T160
Test name
Test status
Simulation time 47469949 ps
CPU time 1.2 seconds
Started Aug 05 06:09:22 PM PDT 24
Finished Aug 05 06:09:23 PM PDT 24
Peak memory 219776 kb
Host smart-db8c7289-5bcf-4532-a064-fa2c2811a5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180918103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.4180918103
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.4188994554
Short name T122
Test name
Test status
Simulation time 24301532 ps
CPU time 1.12 seconds
Started Aug 05 06:09:15 PM PDT 24
Finished Aug 05 06:09:16 PM PDT 24
Peak memory 220544 kb
Host smart-b6403db0-9ff7-4c6a-8f99-ab8139e93aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188994554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.4188994554
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.51099159
Short name T406
Test name
Test status
Simulation time 91291704 ps
CPU time 1.58 seconds
Started Aug 05 06:09:00 PM PDT 24
Finished Aug 05 06:09:01 PM PDT 24
Peak memory 218884 kb
Host smart-04b427ee-aa58-4bcc-a88a-353b17960258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51099159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.51099159
Directory /workspace/99.edn_genbits/latest
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