Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.09 98.25 93.07 90.85 86.63 95.50 96.83 90.48


Total test records in report: 1125
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T1015 /workspace/coverage/cover_reg_top/46.edn_intr_test.1728599480 Aug 06 07:46:25 PM PDT 24 Aug 06 07:46:26 PM PDT 24 38279612 ps
T279 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.359804590 Aug 06 07:46:05 PM PDT 24 Aug 06 07:46:07 PM PDT 24 194261489 ps
T1016 /workspace/coverage/cover_reg_top/38.edn_intr_test.1525850974 Aug 06 07:46:26 PM PDT 24 Aug 06 07:46:27 PM PDT 24 26710384 ps
T1017 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2041670729 Aug 06 07:46:12 PM PDT 24 Aug 06 07:46:14 PM PDT 24 54068621 ps
T1018 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1636556707 Aug 06 07:45:59 PM PDT 24 Aug 06 07:46:01 PM PDT 24 50213352 ps
T252 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2339264630 Aug 06 07:45:55 PM PDT 24 Aug 06 07:45:56 PM PDT 24 13446334 ps
T1019 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3396461282 Aug 06 07:46:00 PM PDT 24 Aug 06 07:46:02 PM PDT 24 27515116 ps
T1020 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2457906960 Aug 06 07:46:14 PM PDT 24 Aug 06 07:46:15 PM PDT 24 14087408 ps
T1021 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2885784101 Aug 06 07:46:08 PM PDT 24 Aug 06 07:46:09 PM PDT 24 27811801 ps
T1022 /workspace/coverage/cover_reg_top/15.edn_tl_errors.531189134 Aug 06 07:46:13 PM PDT 24 Aug 06 07:46:16 PM PDT 24 342783645 ps
T261 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1080200156 Aug 06 07:45:58 PM PDT 24 Aug 06 07:46:00 PM PDT 24 51509717 ps
T1023 /workspace/coverage/cover_reg_top/47.edn_intr_test.859143011 Aug 06 07:46:30 PM PDT 24 Aug 06 07:46:31 PM PDT 24 11241919 ps
T257 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4129299549 Aug 06 07:45:57 PM PDT 24 Aug 06 07:46:01 PM PDT 24 144781431 ps
T262 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3138104504 Aug 06 07:46:00 PM PDT 24 Aug 06 07:46:01 PM PDT 24 81849587 ps
T1024 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1487871363 Aug 06 07:46:06 PM PDT 24 Aug 06 07:46:08 PM PDT 24 465986726 ps
T1025 /workspace/coverage/cover_reg_top/39.edn_intr_test.4219245270 Aug 06 07:46:23 PM PDT 24 Aug 06 07:46:24 PM PDT 24 22094040 ps
T1026 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1484406958 Aug 06 07:45:56 PM PDT 24 Aug 06 07:45:59 PM PDT 24 67405733 ps
T1027 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1308865308 Aug 06 07:45:59 PM PDT 24 Aug 06 07:46:01 PM PDT 24 100087115 ps
T1028 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.913895917 Aug 06 07:45:59 PM PDT 24 Aug 06 07:46:01 PM PDT 24 129457403 ps
T1029 /workspace/coverage/cover_reg_top/3.edn_intr_test.62490705 Aug 06 07:45:59 PM PDT 24 Aug 06 07:46:00 PM PDT 24 161407633 ps
T1030 /workspace/coverage/cover_reg_top/37.edn_intr_test.2960503012 Aug 06 07:46:26 PM PDT 24 Aug 06 07:46:27 PM PDT 24 39172581 ps
T1031 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1395356556 Aug 06 07:46:30 PM PDT 24 Aug 06 07:46:33 PM PDT 24 175000810 ps
T1032 /workspace/coverage/cover_reg_top/12.edn_intr_test.3842868514 Aug 06 07:46:09 PM PDT 24 Aug 06 07:46:10 PM PDT 24 16456061 ps
T1033 /workspace/coverage/cover_reg_top/44.edn_intr_test.1952299283 Aug 06 07:46:24 PM PDT 24 Aug 06 07:46:25 PM PDT 24 18318247 ps
T253 /workspace/coverage/cover_reg_top/11.edn_csr_rw.285106212 Aug 06 07:46:07 PM PDT 24 Aug 06 07:46:08 PM PDT 24 12751204 ps
T263 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1204320242 Aug 06 07:45:58 PM PDT 24 Aug 06 07:45:59 PM PDT 24 41351243 ps
T1034 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3904780946 Aug 06 07:46:01 PM PDT 24 Aug 06 07:46:03 PM PDT 24 19116282 ps
T1035 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1455353486 Aug 06 07:46:09 PM PDT 24 Aug 06 07:46:10 PM PDT 24 43188681 ps
T1036 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2978210870 Aug 06 07:45:57 PM PDT 24 Aug 06 07:45:59 PM PDT 24 223407117 ps
T1037 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3256779717 Aug 06 07:46:08 PM PDT 24 Aug 06 07:46:09 PM PDT 24 20017166 ps
T1038 /workspace/coverage/cover_reg_top/35.edn_intr_test.1660735510 Aug 06 07:46:24 PM PDT 24 Aug 06 07:46:25 PM PDT 24 40109869 ps
T1039 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1927729222 Aug 06 07:45:57 PM PDT 24 Aug 06 07:45:58 PM PDT 24 118125631 ps
T254 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.643016327 Aug 06 07:45:59 PM PDT 24 Aug 06 07:46:00 PM PDT 24 305527205 ps
T1040 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1705279636 Aug 06 07:46:00 PM PDT 24 Aug 06 07:46:01 PM PDT 24 48567003 ps
T1041 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1660343220 Aug 06 07:46:08 PM PDT 24 Aug 06 07:46:09 PM PDT 24 228066666 ps
T1042 /workspace/coverage/cover_reg_top/10.edn_tl_errors.268794848 Aug 06 07:45:59 PM PDT 24 Aug 06 07:46:03 PM PDT 24 784070549 ps
T1043 /workspace/coverage/cover_reg_top/2.edn_tl_errors.4181100975 Aug 06 07:45:56 PM PDT 24 Aug 06 07:46:01 PM PDT 24 2211159436 ps
T1044 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3995594518 Aug 06 07:46:12 PM PDT 24 Aug 06 07:46:13 PM PDT 24 54070188 ps
T255 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2358577626 Aug 06 07:45:55 PM PDT 24 Aug 06 07:45:56 PM PDT 24 36446836 ps
T1045 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3233953925 Aug 06 07:46:06 PM PDT 24 Aug 06 07:46:09 PM PDT 24 507239220 ps
T1046 /workspace/coverage/cover_reg_top/9.edn_intr_test.2092392504 Aug 06 07:45:54 PM PDT 24 Aug 06 07:45:54 PM PDT 24 31755805 ps
T1047 /workspace/coverage/cover_reg_top/32.edn_intr_test.3399715646 Aug 06 07:46:25 PM PDT 24 Aug 06 07:46:26 PM PDT 24 16500034 ps
T275 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3537181751 Aug 06 07:45:55 PM PDT 24 Aug 06 07:45:57 PM PDT 24 250290237 ps
T1048 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2824530336 Aug 06 07:45:59 PM PDT 24 Aug 06 07:46:00 PM PDT 24 29272042 ps
T1049 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3452269899 Aug 06 07:46:12 PM PDT 24 Aug 06 07:46:15 PM PDT 24 91418109 ps
T1050 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.105857294 Aug 06 07:46:06 PM PDT 24 Aug 06 07:46:08 PM PDT 24 79733684 ps
T1051 /workspace/coverage/cover_reg_top/22.edn_intr_test.2983506399 Aug 06 07:46:26 PM PDT 24 Aug 06 07:46:27 PM PDT 24 11114923 ps
T1052 /workspace/coverage/cover_reg_top/4.edn_tl_errors.730841484 Aug 06 07:45:55 PM PDT 24 Aug 06 07:45:59 PM PDT 24 171497722 ps
T1053 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.569787220 Aug 06 07:46:00 PM PDT 24 Aug 06 07:46:01 PM PDT 24 46029542 ps
T1054 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2516505177 Aug 06 07:46:10 PM PDT 24 Aug 06 07:46:12 PM PDT 24 74241223 ps
T1055 /workspace/coverage/cover_reg_top/4.edn_intr_test.3534121348 Aug 06 07:45:57 PM PDT 24 Aug 06 07:45:58 PM PDT 24 22766437 ps
T256 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3808502969 Aug 06 07:45:56 PM PDT 24 Aug 06 07:45:57 PM PDT 24 16366341 ps
T1056 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2614751339 Aug 06 07:46:10 PM PDT 24 Aug 06 07:46:11 PM PDT 24 41891763 ps
T1057 /workspace/coverage/cover_reg_top/16.edn_intr_test.1201120510 Aug 06 07:46:08 PM PDT 24 Aug 06 07:46:09 PM PDT 24 102397607 ps
T1058 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.140130729 Aug 06 07:46:06 PM PDT 24 Aug 06 07:46:07 PM PDT 24 261247599 ps
T1059 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4140248385 Aug 06 07:46:23 PM PDT 24 Aug 06 07:46:25 PM PDT 24 30138705 ps
T1060 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3505648740 Aug 06 07:46:06 PM PDT 24 Aug 06 07:46:08 PM PDT 24 29522873 ps
T1061 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2985090390 Aug 06 07:45:59 PM PDT 24 Aug 06 07:46:01 PM PDT 24 102949801 ps
T1062 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2772132748 Aug 06 07:45:58 PM PDT 24 Aug 06 07:46:00 PM PDT 24 18095194 ps
T1063 /workspace/coverage/cover_reg_top/31.edn_intr_test.4131876609 Aug 06 07:46:26 PM PDT 24 Aug 06 07:46:27 PM PDT 24 24483122 ps
T1064 /workspace/coverage/cover_reg_top/19.edn_intr_test.110404071 Aug 06 07:46:22 PM PDT 24 Aug 06 07:46:23 PM PDT 24 24066665 ps
T1065 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1514022105 Aug 06 07:45:58 PM PDT 24 Aug 06 07:45:59 PM PDT 24 15112056 ps
T1066 /workspace/coverage/cover_reg_top/8.edn_intr_test.1809625412 Aug 06 07:46:06 PM PDT 24 Aug 06 07:46:07 PM PDT 24 22369352 ps
T1067 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3718359375 Aug 06 07:45:56 PM PDT 24 Aug 06 07:45:57 PM PDT 24 20523962 ps
T1068 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3155411914 Aug 06 07:46:06 PM PDT 24 Aug 06 07:46:09 PM PDT 24 117706005 ps
T1069 /workspace/coverage/cover_reg_top/34.edn_intr_test.4275757506 Aug 06 07:46:28 PM PDT 24 Aug 06 07:46:29 PM PDT 24 56021987 ps
T1070 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2405527426 Aug 06 07:46:00 PM PDT 24 Aug 06 07:46:01 PM PDT 24 52012694 ps
T1071 /workspace/coverage/cover_reg_top/24.edn_intr_test.3000072937 Aug 06 07:46:23 PM PDT 24 Aug 06 07:46:24 PM PDT 24 147196737 ps
T258 /workspace/coverage/cover_reg_top/6.edn_csr_rw.497339037 Aug 06 07:45:59 PM PDT 24 Aug 06 07:46:00 PM PDT 24 14769383 ps
T1072 /workspace/coverage/cover_reg_top/1.edn_intr_test.3803903284 Aug 06 07:45:57 PM PDT 24 Aug 06 07:45:58 PM PDT 24 14552358 ps
T1073 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1380639599 Aug 06 07:46:22 PM PDT 24 Aug 06 07:46:23 PM PDT 24 25833507 ps
T1074 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3873126651 Aug 06 07:45:56 PM PDT 24 Aug 06 07:45:57 PM PDT 24 157562156 ps
T1075 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2913245688 Aug 06 07:45:57 PM PDT 24 Aug 06 07:45:59 PM PDT 24 18158448 ps
T1076 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3575881462 Aug 06 07:45:53 PM PDT 24 Aug 06 07:45:55 PM PDT 24 110984218 ps
T1077 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2260063094 Aug 06 07:46:01 PM PDT 24 Aug 06 07:46:02 PM PDT 24 79170416 ps
T1078 /workspace/coverage/cover_reg_top/18.edn_intr_test.3349403474 Aug 06 07:46:21 PM PDT 24 Aug 06 07:46:22 PM PDT 24 38444735 ps
T1079 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1852380487 Aug 06 07:46:30 PM PDT 24 Aug 06 07:46:31 PM PDT 24 46722618 ps
T1080 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3820718705 Aug 06 07:46:01 PM PDT 24 Aug 06 07:46:03 PM PDT 24 71577956 ps
T1081 /workspace/coverage/cover_reg_top/23.edn_intr_test.3598141713 Aug 06 07:46:30 PM PDT 24 Aug 06 07:46:31 PM PDT 24 107263264 ps
T1082 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1685673839 Aug 06 07:45:56 PM PDT 24 Aug 06 07:45:57 PM PDT 24 21578110 ps
T1083 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1119920740 Aug 06 07:46:10 PM PDT 24 Aug 06 07:46:11 PM PDT 24 107560063 ps
T1084 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1350221701 Aug 06 07:45:59 PM PDT 24 Aug 06 07:46:00 PM PDT 24 58799056 ps
T1085 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2896546875 Aug 06 07:46:11 PM PDT 24 Aug 06 07:46:12 PM PDT 24 81960309 ps
T1086 /workspace/coverage/cover_reg_top/2.edn_intr_test.2260383000 Aug 06 07:45:57 PM PDT 24 Aug 06 07:45:58 PM PDT 24 11013250 ps
T1087 /workspace/coverage/cover_reg_top/6.edn_intr_test.445654097 Aug 06 07:45:58 PM PDT 24 Aug 06 07:45:59 PM PDT 24 16863603 ps
T1088 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2690108821 Aug 06 07:45:56 PM PDT 24 Aug 06 07:45:57 PM PDT 24 269072989 ps
T1089 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4235170447 Aug 06 07:45:56 PM PDT 24 Aug 06 07:45:57 PM PDT 24 21235961 ps
T1090 /workspace/coverage/cover_reg_top/14.edn_tl_errors.770363027 Aug 06 07:46:11 PM PDT 24 Aug 06 07:46:15 PM PDT 24 252823321 ps
T1091 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1448291530 Aug 06 07:46:09 PM PDT 24 Aug 06 07:46:09 PM PDT 24 41468560 ps
T1092 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3441629872 Aug 06 07:45:56 PM PDT 24 Aug 06 07:45:57 PM PDT 24 14177371 ps
T1093 /workspace/coverage/cover_reg_top/7.edn_intr_test.1143144103 Aug 06 07:45:59 PM PDT 24 Aug 06 07:46:00 PM PDT 24 71168338 ps
T1094 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3994533905 Aug 06 07:45:56 PM PDT 24 Aug 06 07:45:58 PM PDT 24 25809703 ps
T1095 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2543086139 Aug 06 07:46:11 PM PDT 24 Aug 06 07:46:13 PM PDT 24 100304203 ps
T1096 /workspace/coverage/cover_reg_top/49.edn_intr_test.3238595459 Aug 06 07:46:22 PM PDT 24 Aug 06 07:46:23 PM PDT 24 23726963 ps
T1097 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1596587423 Aug 06 07:45:57 PM PDT 24 Aug 06 07:45:59 PM PDT 24 83180446 ps
T1098 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.569238489 Aug 06 07:46:08 PM PDT 24 Aug 06 07:46:09 PM PDT 24 252763908 ps
T1099 /workspace/coverage/cover_reg_top/42.edn_intr_test.2367468067 Aug 06 07:46:30 PM PDT 24 Aug 06 07:46:31 PM PDT 24 22105797 ps
T1100 /workspace/coverage/cover_reg_top/33.edn_intr_test.3083983912 Aug 06 07:46:21 PM PDT 24 Aug 06 07:46:22 PM PDT 24 17773468 ps
T1101 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3563816495 Aug 06 07:45:56 PM PDT 24 Aug 06 07:45:58 PM PDT 24 33685346 ps
T1102 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3293802103 Aug 06 07:46:10 PM PDT 24 Aug 06 07:46:11 PM PDT 24 24017580 ps
T1103 /workspace/coverage/cover_reg_top/25.edn_intr_test.2874529861 Aug 06 07:46:27 PM PDT 24 Aug 06 07:46:28 PM PDT 24 27761432 ps
T1104 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3238093556 Aug 06 07:45:58 PM PDT 24 Aug 06 07:46:01 PM PDT 24 916849481 ps
T1105 /workspace/coverage/cover_reg_top/48.edn_intr_test.2209795198 Aug 06 07:46:25 PM PDT 24 Aug 06 07:46:26 PM PDT 24 48506918 ps
T1106 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4154487236 Aug 06 07:46:06 PM PDT 24 Aug 06 07:46:07 PM PDT 24 90605202 ps
T1107 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3635242175 Aug 06 07:45:57 PM PDT 24 Aug 06 07:45:59 PM PDT 24 162058963 ps
T1108 /workspace/coverage/cover_reg_top/29.edn_intr_test.1681432156 Aug 06 07:46:22 PM PDT 24 Aug 06 07:46:23 PM PDT 24 202136070 ps
T1109 /workspace/coverage/cover_reg_top/10.edn_intr_test.3587771434 Aug 06 07:46:06 PM PDT 24 Aug 06 07:46:06 PM PDT 24 51276093 ps
T1110 /workspace/coverage/cover_reg_top/40.edn_intr_test.4145933131 Aug 06 07:46:24 PM PDT 24 Aug 06 07:46:24 PM PDT 24 21385887 ps
T1111 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1513027753 Aug 06 07:45:56 PM PDT 24 Aug 06 07:45:57 PM PDT 24 78334550 ps
T1112 /workspace/coverage/cover_reg_top/17.edn_intr_test.424684377 Aug 06 07:46:08 PM PDT 24 Aug 06 07:46:09 PM PDT 24 22410116 ps
T1113 /workspace/coverage/cover_reg_top/28.edn_intr_test.2186789537 Aug 06 07:46:27 PM PDT 24 Aug 06 07:46:28 PM PDT 24 34111539 ps
T1114 /workspace/coverage/cover_reg_top/11.edn_intr_test.2047462085 Aug 06 07:46:08 PM PDT 24 Aug 06 07:46:09 PM PDT 24 12541782 ps
T259 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2522444579 Aug 06 07:45:57 PM PDT 24 Aug 06 07:45:59 PM PDT 24 39491405 ps
T276 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.45840786 Aug 06 07:46:22 PM PDT 24 Aug 06 07:46:25 PM PDT 24 301355373 ps
T1115 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.854180015 Aug 06 07:45:57 PM PDT 24 Aug 06 07:45:58 PM PDT 24 32000940 ps
T1116 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1057307480 Aug 06 07:45:59 PM PDT 24 Aug 06 07:46:00 PM PDT 24 45561143 ps
T1117 /workspace/coverage/cover_reg_top/1.edn_tl_errors.739462642 Aug 06 07:45:55 PM PDT 24 Aug 06 07:45:57 PM PDT 24 250293645 ps
T1118 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2376863617 Aug 06 07:46:26 PM PDT 24 Aug 06 07:46:27 PM PDT 24 149249957 ps
T1119 /workspace/coverage/cover_reg_top/17.edn_tl_errors.50547752 Aug 06 07:46:11 PM PDT 24 Aug 06 07:46:13 PM PDT 24 47134639 ps
T1120 /workspace/coverage/cover_reg_top/14.edn_intr_test.1022088335 Aug 06 07:46:09 PM PDT 24 Aug 06 07:46:10 PM PDT 24 88334517 ps
T1121 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2855869197 Aug 06 07:46:12 PM PDT 24 Aug 06 07:46:15 PM PDT 24 210631971 ps
T1122 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2967410780 Aug 06 07:46:23 PM PDT 24 Aug 06 07:46:24 PM PDT 24 158900595 ps
T1123 /workspace/coverage/cover_reg_top/45.edn_intr_test.1945736499 Aug 06 07:46:25 PM PDT 24 Aug 06 07:46:26 PM PDT 24 47593192 ps
T1124 /workspace/coverage/cover_reg_top/41.edn_intr_test.1863782979 Aug 06 07:46:26 PM PDT 24 Aug 06 07:46:27 PM PDT 24 16038185 ps
T1125 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2031751720 Aug 06 07:46:21 PM PDT 24 Aug 06 07:46:22 PM PDT 24 36138503 ps

Test location /workspace/coverage/default/258.edn_genbits.1570819363
Short name T23
Test name
Test status
Simulation time 63122065 ps
CPU time 1.61 seconds
Started Aug 06 07:45:42 PM PDT 24
Finished Aug 06 07:45:44 PM PDT 24
Peak memory 218396 kb
Host smart-bc5e0504-0245-4c51-a7ea-0947089e896b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570819363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1570819363
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2545815788
Short name T20
Test name
Test status
Simulation time 30519297946 ps
CPU time 395.52 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:50:12 PM PDT 24
Peak memory 218108 kb
Host smart-fef17026-1eb0-47fe-9d6b-45e8e2174dad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545815788 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2545815788
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_err.3528723528
Short name T14
Test name
Test status
Simulation time 26038516 ps
CPU time 1.16 seconds
Started Aug 06 07:42:44 PM PDT 24
Finished Aug 06 07:42:45 PM PDT 24
Peak memory 229288 kb
Host smart-b4e6c15a-eda6-467a-ae9e-4090a983b71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528723528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3528723528
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/191.edn_alert.2309799661
Short name T57
Test name
Test status
Simulation time 248865568 ps
CPU time 1.39 seconds
Started Aug 06 07:45:24 PM PDT 24
Finished Aug 06 07:45:26 PM PDT 24
Peak memory 218312 kb
Host smart-e3b1e768-e5b6-40ea-b75d-71043ef9bd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309799661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2309799661
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/61.edn_genbits.2492203773
Short name T11
Test name
Test status
Simulation time 76238478 ps
CPU time 1.09 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:54 PM PDT 24
Peak memory 219316 kb
Host smart-c988781f-5126-4b41-815c-263cd3f62680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492203773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2492203773
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.4052699297
Short name T13
Test name
Test status
Simulation time 20806085 ps
CPU time 1.12 seconds
Started Aug 06 07:44:01 PM PDT 24
Finished Aug 06 07:44:02 PM PDT 24
Peak memory 223696 kb
Host smart-97503d29-8b26-4c9a-89e3-1035b9623ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052699297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.4052699297
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/38.edn_stress_all.1543730145
Short name T101
Test name
Test status
Simulation time 416135514 ps
CPU time 4.76 seconds
Started Aug 06 07:43:19 PM PDT 24
Finished Aug 06 07:43:24 PM PDT 24
Peak memory 216832 kb
Host smart-8e48d86c-83b7-45e5-b8bb-dedb9d85fe6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543730145 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1543730145
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_alert.4260978519
Short name T3
Test name
Test status
Simulation time 29181213 ps
CPU time 1.22 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 07:41:34 PM PDT 24
Peak memory 215288 kb
Host smart-ea81a8d9-4f3f-491f-ae99-b639cfeaa3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260978519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.4260978519
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/109.edn_alert.130204210
Short name T272
Test name
Test status
Simulation time 40831147 ps
CPU time 1.17 seconds
Started Aug 06 07:44:49 PM PDT 24
Finished Aug 06 07:44:50 PM PDT 24
Peak memory 219376 kb
Host smart-11732d39-45c8-47d0-8ffd-7a9ba71030d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130204210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.130204210
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1314857042
Short name T91
Test name
Test status
Simulation time 781664748784 ps
CPU time 2597.36 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 08:26:55 PM PDT 24
Peak memory 226936 kb
Host smart-d0351bb2-be24-4892-8fb3-888337585d4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314857042 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1314857042
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.840250896
Short name T68
Test name
Test status
Simulation time 60905297 ps
CPU time 1.21 seconds
Started Aug 06 07:40:19 PM PDT 24
Finished Aug 06 07:40:20 PM PDT 24
Peak memory 219440 kb
Host smart-eb1e400e-5ab1-43e1-a953-9ef98eb40b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840250896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.840250896
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3090675909
Short name T111
Test name
Test status
Simulation time 464995548 ps
CPU time 1.18 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 216812 kb
Host smart-8294d41e-3966-4bc9-a84e-26e4c69a3ca8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090675909 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3090675909
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_intr.1500430973
Short name T75
Test name
Test status
Simulation time 34968062 ps
CPU time 0.88 seconds
Started Aug 06 07:40:18 PM PDT 24
Finished Aug 06 07:40:19 PM PDT 24
Peak memory 215616 kb
Host smart-d837fa2c-5396-4235-8c33-33dac108d511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500430973 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1500430973
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.563749211
Short name T621
Test name
Test status
Simulation time 41464137 ps
CPU time 0.88 seconds
Started Aug 06 07:40:06 PM PDT 24
Finished Aug 06 07:40:07 PM PDT 24
Peak memory 206664 kb
Host smart-aa17613a-9090-48db-a223-769422084646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563749211 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.563749211
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1351019976
Short name T216
Test name
Test status
Simulation time 94031158 ps
CPU time 2.69 seconds
Started Aug 06 07:46:01 PM PDT 24
Finished Aug 06 07:46:04 PM PDT 24
Peak memory 206748 kb
Host smart-0d743af9-c63f-4759-b7ea-8d74f0ade969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351019976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1351019976
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/199.edn_alert.1447481489
Short name T37
Test name
Test status
Simulation time 24987542 ps
CPU time 1.22 seconds
Started Aug 06 07:45:26 PM PDT 24
Finished Aug 06 07:45:28 PM PDT 24
Peak memory 219456 kb
Host smart-38fd144f-08b5-4692-a88a-b9d8bf63275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447481489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1447481489
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/8.edn_disable.4138641122
Short name T119
Test name
Test status
Simulation time 14266723 ps
CPU time 0.94 seconds
Started Aug 06 07:41:15 PM PDT 24
Finished Aug 06 07:41:16 PM PDT 24
Peak memory 216264 kb
Host smart-9dae0785-5f60-476f-9b8d-44c1f9c2f29d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138641122 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4138641122
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.285106212
Short name T253
Test name
Test status
Simulation time 12751204 ps
CPU time 0.91 seconds
Started Aug 06 07:46:07 PM PDT 24
Finished Aug 06 07:46:08 PM PDT 24
Peak memory 206568 kb
Host smart-eff6528d-ae68-4e00-a32c-6655fa57dee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285106212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.285106212
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/default/22.edn_disable.2210754135
Short name T95
Test name
Test status
Simulation time 13072531 ps
CPU time 0.88 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 216288 kb
Host smart-acf8457f-01de-42a5-8566-f05f6104cdef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210754135 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2210754135
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/28.edn_intr.4075716812
Short name T47
Test name
Test status
Simulation time 43443286 ps
CPU time 1.03 seconds
Started Aug 06 07:42:36 PM PDT 24
Finished Aug 06 07:42:37 PM PDT 24
Peak memory 223600 kb
Host smart-659b4966-2237-4b3f-a149-b17747e5740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075716812 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.4075716812
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3456056440
Short name T103
Test name
Test status
Simulation time 48416746 ps
CPU time 1.06 seconds
Started Aug 06 07:41:32 PM PDT 24
Finished Aug 06 07:41:34 PM PDT 24
Peak memory 219108 kb
Host smart-ddc2bb15-5ed7-4938-be43-0de18b442b26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456056440 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3456056440
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_disable.4212806359
Short name T898
Test name
Test status
Simulation time 37436292 ps
CPU time 0.82 seconds
Started Aug 06 07:42:44 PM PDT 24
Finished Aug 06 07:42:45 PM PDT 24
Peak memory 216236 kb
Host smart-b8f601b2-2ef0-48ec-b0b0-33642471cfaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212806359 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4212806359
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/15.edn_intr.3702105318
Short name T74
Test name
Test status
Simulation time 23519326 ps
CPU time 0.93 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 215368 kb
Host smart-490a6957-cbc6-4b0a-bf50-32bb5683cacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702105318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3702105318
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/84.edn_alert.422708321
Short name T236
Test name
Test status
Simulation time 174203444 ps
CPU time 1.17 seconds
Started Aug 06 07:44:19 PM PDT 24
Finished Aug 06 07:44:20 PM PDT 24
Peak memory 218212 kb
Host smart-1000d2ae-31c2-453f-a44f-6b94142eb056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422708321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.422708321
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/147.edn_alert.1315781880
Short name T202
Test name
Test status
Simulation time 95140388 ps
CPU time 1.26 seconds
Started Aug 06 07:45:02 PM PDT 24
Finished Aug 06 07:45:04 PM PDT 24
Peak memory 220532 kb
Host smart-b03093e5-224f-4988-baa0-480a882943cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315781880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1315781880
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/71.edn_alert.3195631495
Short name T280
Test name
Test status
Simulation time 85834951 ps
CPU time 1.23 seconds
Started Aug 06 07:44:14 PM PDT 24
Finished Aug 06 07:44:15 PM PDT 24
Peak memory 218292 kb
Host smart-c554bdb0-612f-4667-8bc5-452d7f76927c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195631495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.3195631495
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/99.edn_genbits.226630382
Short name T67
Test name
Test status
Simulation time 68884251 ps
CPU time 1.04 seconds
Started Aug 06 07:44:49 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 217056 kb
Host smart-1a775c5d-14fb-45ba-9a1b-1f9f850c6ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226630382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.226630382
Directory /workspace/99.edn_genbits/latest

Test location /workspace/coverage/default/220.edn_genbits.3536295280
Short name T7
Test name
Test status
Simulation time 237483715 ps
CPU time 2.82 seconds
Started Aug 06 07:45:39 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 219544 kb
Host smart-53a6ffea-5b88-41a8-a59d-d8b9d73eca90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536295280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3536295280
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_err.2402572451
Short name T128
Test name
Test status
Simulation time 31981881 ps
CPU time 0.9 seconds
Started Aug 06 07:41:35 PM PDT 24
Finished Aug 06 07:41:36 PM PDT 24
Peak memory 218336 kb
Host smart-cef6326b-1d22-4122-9cd6-183c2f2fb8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402572451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2402572451
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2767467120
Short name T464
Test name
Test status
Simulation time 79594953 ps
CPU time 1.53 seconds
Started Aug 06 07:44:15 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 219632 kb
Host smart-7a2c832e-3937-429a-beb7-c14da2d10788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767467120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2767467120
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert.2352458235
Short name T528
Test name
Test status
Simulation time 30820866 ps
CPU time 1.11 seconds
Started Aug 06 07:40:18 PM PDT 24
Finished Aug 06 07:40:20 PM PDT 24
Peak memory 218236 kb
Host smart-dcc02051-0cf2-419c-8b28-e08f1af57998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352458235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2352458235
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/149.edn_alert.1385326340
Short name T36
Test name
Test status
Simulation time 48932304 ps
CPU time 1.11 seconds
Started Aug 06 07:45:02 PM PDT 24
Finished Aug 06 07:45:03 PM PDT 24
Peak memory 219192 kb
Host smart-f2b1d8c5-36de-489f-81e9-9afd3ab3de41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385326340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1385326340
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/170.edn_alert.3481636797
Short name T191
Test name
Test status
Simulation time 25865604 ps
CPU time 1.15 seconds
Started Aug 06 07:45:27 PM PDT 24
Finished Aug 06 07:45:28 PM PDT 24
Peak memory 219324 kb
Host smart-9bbad2e2-d8f0-44c7-a07f-9f9be26a6778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481636797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3481636797
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2260827865
Short name T123
Test name
Test status
Simulation time 53237515683 ps
CPU time 1278.75 seconds
Started Aug 06 07:40:19 PM PDT 24
Finished Aug 06 08:01:38 PM PDT 24
Peak memory 223288 kb
Host smart-24039269-3e17-4001-9c16-4fe9cb29ab6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260827865 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2260827865
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3633599585
Short name T197
Test name
Test status
Simulation time 85972513 ps
CPU time 1.23 seconds
Started Aug 06 07:43:24 PM PDT 24
Finished Aug 06 07:43:25 PM PDT 24
Peak memory 218636 kb
Host smart-004b13b8-f2e4-4b8b-8813-01a34076efcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633599585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3633599585
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.3377094494
Short name T760
Test name
Test status
Simulation time 37821899 ps
CPU time 0.85 seconds
Started Aug 06 07:40:19 PM PDT 24
Finished Aug 06 07:40:20 PM PDT 24
Peak memory 215092 kb
Host smart-cbc84e77-cbff-4da8-bbf6-68c286830957
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377094494 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3377094494
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/70.edn_alert.320867159
Short name T158
Test name
Test status
Simulation time 24664043 ps
CPU time 1.21 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 219416 kb
Host smart-77a51376-cda6-4c1f-a4b0-0e16b8bf2a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320867159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.320867159
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/0.edn_err.3234024289
Short name T122
Test name
Test status
Simulation time 30919989 ps
CPU time 0.83 seconds
Started Aug 06 07:40:17 PM PDT 24
Finished Aug 06 07:40:18 PM PDT 24
Peak memory 219024 kb
Host smart-ed733084-963d-489d-b72e-3dae5b809054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234024289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3234024289
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/10.edn_alert.865185007
Short name T181
Test name
Test status
Simulation time 43195839 ps
CPU time 1.11 seconds
Started Aug 06 07:41:34 PM PDT 24
Finished Aug 06 07:41:35 PM PDT 24
Peak memory 219452 kb
Host smart-12311569-9303-4a42-ad29-2db06f3f4556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865185007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.865185007
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3330380003
Short name T885
Test name
Test status
Simulation time 147008679 ps
CPU time 1.15 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 07:41:34 PM PDT 24
Peak memory 216920 kb
Host smart-3cd96ac8-b5b9-49a8-94f2-3ef636f38e01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330380003 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3330380003
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/106.edn_alert.3087738620
Short name T134
Test name
Test status
Simulation time 73761395 ps
CPU time 1.14 seconds
Started Aug 06 07:44:44 PM PDT 24
Finished Aug 06 07:44:46 PM PDT 24
Peak memory 219444 kb
Host smart-c627b4f8-c75f-471b-bd87-6ed57f7eb9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087738620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3087738620
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/111.edn_alert.2363521090
Short name T887
Test name
Test status
Simulation time 72881847 ps
CPU time 1.1 seconds
Started Aug 06 07:44:47 PM PDT 24
Finished Aug 06 07:44:49 PM PDT 24
Peak memory 219452 kb
Host smart-8fbfb977-1859-4466-ba4a-991cee6cab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363521090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2363521090
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1326978118
Short name T798
Test name
Test status
Simulation time 38308955 ps
CPU time 1.18 seconds
Started Aug 06 07:41:35 PM PDT 24
Finished Aug 06 07:41:36 PM PDT 24
Peak memory 219308 kb
Host smart-2acdc0df-4ef7-4fbf-90f4-aaacdc31df3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326978118 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1326978118
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3167352170
Short name T610
Test name
Test status
Simulation time 23380959 ps
CPU time 1.02 seconds
Started Aug 06 07:42:11 PM PDT 24
Finished Aug 06 07:42:12 PM PDT 24
Peak memory 219236 kb
Host smart-d0dcde17-0258-4f97-bc66-c112e1654df8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167352170 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3167352170
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable.3940824101
Short name T107
Test name
Test status
Simulation time 42087621 ps
CPU time 0.87 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 219832 kb
Host smart-10b31335-4257-4ac0-82ce-0c19829904b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940824101 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3940824101
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable.2912162357
Short name T187
Test name
Test status
Simulation time 24967108 ps
CPU time 0.79 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 216188 kb
Host smart-1a4228da-5246-40c5-a411-b8040a8a1b4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912162357 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2912162357
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable.4170816738
Short name T127
Test name
Test status
Simulation time 33066524 ps
CPU time 0.8 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 216200 kb
Host smart-a67a78a4-c01c-46bc-b24b-091975aad17e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170816738 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4170816738
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable.1024072023
Short name T96
Test name
Test status
Simulation time 80096721 ps
CPU time 0.91 seconds
Started Aug 06 07:43:04 PM PDT 24
Finished Aug 06 07:43:05 PM PDT 24
Peak memory 218056 kb
Host smart-7f627b22-1042-4164-a005-3f35910ce9e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024072023 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1024072023
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/205.edn_genbits.1397806172
Short name T29
Test name
Test status
Simulation time 44219547 ps
CPU time 1.5 seconds
Started Aug 06 07:45:36 PM PDT 24
Finished Aug 06 07:45:38 PM PDT 24
Peak memory 219064 kb
Host smart-d0de2c39-2e41-41cb-b441-405795584096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397806172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1397806172
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2944881818
Short name T300
Test name
Test status
Simulation time 43595897 ps
CPU time 1.22 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 219524 kb
Host smart-2a73a460-131d-4644-b417-c38b6fd7067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944881818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2944881818
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert_test.783275467
Short name T341
Test name
Test status
Simulation time 14895160 ps
CPU time 0.89 seconds
Started Aug 06 07:42:00 PM PDT 24
Finished Aug 06 07:42:01 PM PDT 24
Peak memory 206272 kb
Host smart-3cd2f261-713b-4698-bef2-dfa6c36b7296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783275467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.783275467
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/288.edn_genbits.109874340
Short name T321
Test name
Test status
Simulation time 66194621 ps
CPU time 1.04 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 217008 kb
Host smart-397c5976-b0d4-4723-a603-9f64e37693b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109874340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.109874340
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3902707198
Short name T222
Test name
Test status
Simulation time 968151304669 ps
CPU time 1670.07 seconds
Started Aug 06 07:42:06 PM PDT 24
Finished Aug 06 08:09:56 PM PDT 24
Peak memory 223352 kb
Host smart-d4402677-7866-4d01-bc24-135a7916813f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902707198 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3902707198
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.edn_genbits.791537912
Short name T63
Test name
Test status
Simulation time 59387558 ps
CPU time 1.6 seconds
Started Aug 06 07:44:15 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 218192 kb
Host smart-0df5dd2d-5c7b-4937-933c-3e3bcc2a28ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791537912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.791537912
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.2139695483
Short name T71
Test name
Test status
Simulation time 14928360 ps
CPU time 0.93 seconds
Started Aug 06 07:41:17 PM PDT 24
Finished Aug 06 07:41:18 PM PDT 24
Peak memory 206736 kb
Host smart-934677c7-af21-4689-8ca2-f5271d853bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139695483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2139695483
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/26.edn_intr.2066483653
Short name T80
Test name
Test status
Simulation time 37900844 ps
CPU time 0.93 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 215516 kb
Host smart-a3a72a8e-f322-498f-a639-e38ba488cf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066483653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2066483653
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/11.edn_err.3701052726
Short name T367
Test name
Test status
Simulation time 86223443 ps
CPU time 0.79 seconds
Started Aug 06 07:41:34 PM PDT 24
Finished Aug 06 07:41:34 PM PDT 24
Peak memory 218504 kb
Host smart-d31cd8fc-5c55-456e-a3eb-48a028707e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701052726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3701052726
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.45840786
Short name T276
Test name
Test status
Simulation time 301355373 ps
CPU time 2.75 seconds
Started Aug 06 07:46:22 PM PDT 24
Finished Aug 06 07:46:25 PM PDT 24
Peak memory 206732 kb
Host smart-15eea921-a835-4588-be1a-a135fe5572fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45840786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.45840786
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.6683011
Short name T310
Test name
Test status
Simulation time 54514653931 ps
CPU time 625 seconds
Started Aug 06 07:41:36 PM PDT 24
Finished Aug 06 07:52:01 PM PDT 24
Peak memory 217540 kb
Host smart-dc87cfce-6bef-4669-b7cf-9524cb4df27e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6683011 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.6683011
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2155859214
Short name T324
Test name
Test status
Simulation time 113063192 ps
CPU time 2.51 seconds
Started Aug 06 07:44:49 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 217288 kb
Host smart-8314e2a7-2bd3-415a-9e58-59717cf9e372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155859214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2155859214
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.687866091
Short name T165
Test name
Test status
Simulation time 97228044 ps
CPU time 1.31 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:47 PM PDT 24
Peak memory 218488 kb
Host smart-8eee10b0-6529-4ba6-8682-23e14495f17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687866091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.687866091
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.556593975
Short name T956
Test name
Test status
Simulation time 136300243 ps
CPU time 1.32 seconds
Started Aug 06 07:44:44 PM PDT 24
Finished Aug 06 07:44:46 PM PDT 24
Peak memory 218388 kb
Host smart-1a03d23e-4ea6-40c5-bc33-ab9d4d6d2359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556593975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.556593975
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1908842188
Short name T301
Test name
Test status
Simulation time 54035264 ps
CPU time 2.01 seconds
Started Aug 06 07:45:08 PM PDT 24
Finished Aug 06 07:45:10 PM PDT 24
Peak memory 219576 kb
Host smart-4fd14d43-864a-4ab9-8e67-9c4c59eecd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908842188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1908842188
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_genbits.106556641
Short name T322
Test name
Test status
Simulation time 103607078 ps
CPU time 1.57 seconds
Started Aug 06 07:42:06 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 218372 kb
Host smart-0fb3eb54-832f-44ef-aac7-58a7e80f98bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106556641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.106556641
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.3569778842
Short name T298
Test name
Test status
Simulation time 102750040 ps
CPU time 1.51 seconds
Started Aug 06 07:45:18 PM PDT 24
Finished Aug 06 07:45:20 PM PDT 24
Peak memory 218660 kb
Host smart-14f90670-4cdd-4e6a-8d9b-db09604ec3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569778842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3569778842
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.875161354
Short name T320
Test name
Test status
Simulation time 62481767 ps
CPU time 1.18 seconds
Started Aug 06 07:45:37 PM PDT 24
Finished Aug 06 07:45:38 PM PDT 24
Peak memory 217304 kb
Host smart-e33604ed-85bd-40d2-a2bd-ac11cca79060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875161354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.875161354
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.725979211
Short name T303
Test name
Test status
Simulation time 34367632 ps
CPU time 1.31 seconds
Started Aug 06 07:45:43 PM PDT 24
Finished Aug 06 07:45:45 PM PDT 24
Peak memory 217032 kb
Host smart-45dea697-3ead-4fc1-85f8-d8207d79b33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725979211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.725979211
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3087494478
Short name T302
Test name
Test status
Simulation time 52702938 ps
CPU time 1.74 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 217004 kb
Host smart-3ee5f1a0-ba60-4430-87f4-c2089bb60075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087494478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3087494478
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/100.edn_alert.2814697877
Short name T208
Test name
Test status
Simulation time 25739636 ps
CPU time 1.24 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 220400 kb
Host smart-95047a4d-6eb2-4d4d-ada1-0fd4ec4c940d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814697877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2814697877
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.643016327
Short name T254
Test name
Test status
Simulation time 305527205 ps
CPU time 1.25 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 206660 kb
Host smart-a0d244b3-1f2e-42a5-bc3f-e33d4fa88bf4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643016327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.643016327
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3238093556
Short name T1104
Test name
Test status
Simulation time 916849481 ps
CPU time 3.35 seconds
Started Aug 06 07:45:58 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 206688 kb
Host smart-0ff43320-64a9-4f0d-9e2f-933d49a26fb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238093556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3238093556
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1091179655
Short name T998
Test name
Test status
Simulation time 282935202 ps
CPU time 0.98 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206636 kb
Host smart-516a0bf6-3302-4da9-a8a5-e2ed3e0513f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091179655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1091179655
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1513027753
Short name T1111
Test name
Test status
Simulation time 78334550 ps
CPU time 1.23 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 215196 kb
Host smart-3aefcd30-8dca-41b9-bad0-4cda623c4c08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513027753 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1513027753
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3441629872
Short name T1092
Test name
Test status
Simulation time 14177371 ps
CPU time 0.96 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 206608 kb
Host smart-a7c72b82-6e28-4541-b8d1-48270ced6389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441629872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3441629872
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3192314918
Short name T993
Test name
Test status
Simulation time 44437264 ps
CPU time 0.86 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 206536 kb
Host smart-1436844c-6491-490c-bd93-28a9ac7f9b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192314918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3192314918
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2690108821
Short name T1088
Test name
Test status
Simulation time 269072989 ps
CPU time 1.21 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 206792 kb
Host smart-aaf08e40-1816-4c1b-981f-712d8908538b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690108821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2690108821
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3994533905
Short name T1094
Test name
Test status
Simulation time 25809703 ps
CPU time 1.79 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:58 PM PDT 24
Peak memory 214940 kb
Host smart-dfbe4198-49f6-4e11-afe0-f51c7478b54f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994533905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3994533905
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1484406958
Short name T1026
Test name
Test status
Simulation time 67405733 ps
CPU time 1.96 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206796 kb
Host smart-b4d9dea9-ed4d-4e33-8131-c2f2cc2e4318
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484406958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1484406958
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2961514466
Short name T1009
Test name
Test status
Simulation time 158415684 ps
CPU time 1.09 seconds
Started Aug 06 07:45:58 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 206688 kb
Host smart-02883f31-848e-4ff3-b150-3d223f675c40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961514466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2961514466
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2738569490
Short name T245
Test name
Test status
Simulation time 865883391 ps
CPU time 3.16 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 206672 kb
Host smart-945e666c-249f-4e8a-b5d6-d7e33cb2d4b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738569490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2738569490
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.657324004
Short name T250
Test name
Test status
Simulation time 184310661 ps
CPU time 0.89 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:58 PM PDT 24
Peak memory 206624 kb
Host smart-736df916-af94-40a9-beb9-8b3d29e533cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657324004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.657324004
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.854180015
Short name T1115
Test name
Test status
Simulation time 32000940 ps
CPU time 1.27 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:58 PM PDT 24
Peak memory 215016 kb
Host smart-c1d6aba0-d5f1-444c-9e40-456c4ea05a70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854180015 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.854180015
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2339264630
Short name T252
Test name
Test status
Simulation time 13446334 ps
CPU time 0.91 seconds
Started Aug 06 07:45:55 PM PDT 24
Finished Aug 06 07:45:56 PM PDT 24
Peak memory 206624 kb
Host smart-0b6e1ece-ca56-47a3-800e-6dd2f9c5aa25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339264630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2339264630
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3803903284
Short name T1072
Test name
Test status
Simulation time 14552358 ps
CPU time 0.9 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:58 PM PDT 24
Peak memory 206572 kb
Host smart-6c368fc1-ffeb-4bfe-95cc-332f331381df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803903284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3803903284
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1057307480
Short name T1116
Test name
Test status
Simulation time 45561143 ps
CPU time 1.21 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 206720 kb
Host smart-1995fb83-258f-4f51-8718-e306cbf54f96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057307480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1057307480
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.739462642
Short name T1117
Test name
Test status
Simulation time 250293645 ps
CPU time 2.43 seconds
Started Aug 06 07:45:55 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 214896 kb
Host smart-e9c06818-ae1b-4173-8713-95c52c0ea3c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739462642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.739462642
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.4109739740
Short name T214
Test name
Test status
Simulation time 57174663 ps
CPU time 1.79 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206872 kb
Host smart-4f769592-70c0-43a8-8463-c0c8c3a2a231
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109739740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.4109739740
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3904780946
Short name T1034
Test name
Test status
Simulation time 19116282 ps
CPU time 1.09 seconds
Started Aug 06 07:46:01 PM PDT 24
Finished Aug 06 07:46:03 PM PDT 24
Peak memory 206772 kb
Host smart-f723f0b0-d819-45ab-8764-f9953f404ae9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904780946 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3904780946
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2405527426
Short name T1070
Test name
Test status
Simulation time 52012694 ps
CPU time 0.9 seconds
Started Aug 06 07:46:00 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 206620 kb
Host smart-85ff4e5b-8146-40e5-ac6c-e8dc53f40555
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405527426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2405527426
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3587771434
Short name T1109
Test name
Test status
Simulation time 51276093 ps
CPU time 0.76 seconds
Started Aug 06 07:46:06 PM PDT 24
Finished Aug 06 07:46:06 PM PDT 24
Peak memory 206344 kb
Host smart-137239ab-bf9e-459e-a1ee-ac47d5f2a6a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587771434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3587771434
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3820718705
Short name T1080
Test name
Test status
Simulation time 71577956 ps
CPU time 1.59 seconds
Started Aug 06 07:46:01 PM PDT 24
Finished Aug 06 07:46:03 PM PDT 24
Peak memory 206692 kb
Host smart-08ca9a16-efe7-44d0-8517-3e1b3a1436e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820718705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3820718705
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.268794848
Short name T1042
Test name
Test status
Simulation time 784070549 ps
CPU time 3.11 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:03 PM PDT 24
Peak memory 214956 kb
Host smart-15ddf7ad-9f10-4af7-990a-dc06db3973d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268794848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.268794848
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.610324760
Short name T1007
Test name
Test status
Simulation time 82889546 ps
CPU time 1.36 seconds
Started Aug 06 07:46:06 PM PDT 24
Finished Aug 06 07:46:07 PM PDT 24
Peak memory 215052 kb
Host smart-87952281-c376-4a2c-8553-b83acd5dd5ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610324760 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.610324760
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2047462085
Short name T1114
Test name
Test status
Simulation time 12541782 ps
CPU time 0.82 seconds
Started Aug 06 07:46:08 PM PDT 24
Finished Aug 06 07:46:09 PM PDT 24
Peak memory 206512 kb
Host smart-0bea266e-2cfe-432f-9ba2-6435e30d9ecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047462085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2047462085
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3505648740
Short name T1060
Test name
Test status
Simulation time 29522873 ps
CPU time 1.14 seconds
Started Aug 06 07:46:06 PM PDT 24
Finished Aug 06 07:46:08 PM PDT 24
Peak memory 206808 kb
Host smart-965805df-b1dc-43db-b613-b80f99171908
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505648740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3505648740
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2543086139
Short name T1095
Test name
Test status
Simulation time 100304203 ps
CPU time 2.09 seconds
Started Aug 06 07:46:11 PM PDT 24
Finished Aug 06 07:46:13 PM PDT 24
Peak memory 214992 kb
Host smart-eab5d1c2-22a6-4c0c-b4a6-c5c11fd8c1d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543086139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2543086139
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.52930737
Short name T278
Test name
Test status
Simulation time 185303759 ps
CPU time 2.08 seconds
Started Aug 06 07:46:05 PM PDT 24
Finished Aug 06 07:46:07 PM PDT 24
Peak memory 206984 kb
Host smart-8f82720d-8130-48ea-b666-bb71a3928493
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52930737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.52930737
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.992211183
Short name T1008
Test name
Test status
Simulation time 30918790 ps
CPU time 1.45 seconds
Started Aug 06 07:46:08 PM PDT 24
Finished Aug 06 07:46:10 PM PDT 24
Peak memory 215192 kb
Host smart-6522f932-982f-452e-8f83-4e5194d0af08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992211183 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.992211183
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.460146733
Short name T991
Test name
Test status
Simulation time 15143105 ps
CPU time 0.98 seconds
Started Aug 06 07:46:06 PM PDT 24
Finished Aug 06 07:46:07 PM PDT 24
Peak memory 206560 kb
Host smart-d6d896a1-3729-4053-a915-fb3873dc674f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460146733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.460146733
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3842868514
Short name T1032
Test name
Test status
Simulation time 16456061 ps
CPU time 0.79 seconds
Started Aug 06 07:46:09 PM PDT 24
Finished Aug 06 07:46:10 PM PDT 24
Peak memory 206456 kb
Host smart-e5aea071-54fc-4872-9f87-03700939f67a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842868514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3842868514
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1660343220
Short name T1041
Test name
Test status
Simulation time 228066666 ps
CPU time 1.01 seconds
Started Aug 06 07:46:08 PM PDT 24
Finished Aug 06 07:46:09 PM PDT 24
Peak memory 206700 kb
Host smart-71c65785-b31b-41dd-8940-762e81185813
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660343220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1660343220
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3577214642
Short name T990
Test name
Test status
Simulation time 120958955 ps
CPU time 4.5 seconds
Started Aug 06 07:46:14 PM PDT 24
Finished Aug 06 07:46:18 PM PDT 24
Peak memory 214920 kb
Host smart-c804a2a7-f02c-488f-bdd4-cbccf643887a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577214642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3577214642
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2516505177
Short name T1054
Test name
Test status
Simulation time 74241223 ps
CPU time 1.53 seconds
Started Aug 06 07:46:10 PM PDT 24
Finished Aug 06 07:46:12 PM PDT 24
Peak memory 206728 kb
Host smart-e085c22c-48ec-4597-9947-a25cf2a24744
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516505177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2516505177
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1119920740
Short name T1083
Test name
Test status
Simulation time 107560063 ps
CPU time 1.33 seconds
Started Aug 06 07:46:10 PM PDT 24
Finished Aug 06 07:46:11 PM PDT 24
Peak memory 215068 kb
Host smart-a3ebacfe-7f49-447f-8d1a-963f5c06fd41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119920740 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1119920740
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2457906960
Short name T1020
Test name
Test status
Simulation time 14087408 ps
CPU time 0.9 seconds
Started Aug 06 07:46:14 PM PDT 24
Finished Aug 06 07:46:15 PM PDT 24
Peak memory 206580 kb
Host smart-38463892-5d47-4687-a90b-46b3ca756505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457906960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2457906960
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1183691066
Short name T1004
Test name
Test status
Simulation time 26091003 ps
CPU time 0.89 seconds
Started Aug 06 07:46:11 PM PDT 24
Finished Aug 06 07:46:12 PM PDT 24
Peak memory 206440 kb
Host smart-f1a26b87-d7f7-47c6-833c-9a427b7ad951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183691066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1183691066
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4154487236
Short name T1106
Test name
Test status
Simulation time 90605202 ps
CPU time 1.11 seconds
Started Aug 06 07:46:06 PM PDT 24
Finished Aug 06 07:46:07 PM PDT 24
Peak memory 206796 kb
Host smart-cd6a96da-fec9-47e8-a91a-b45200c84ba9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154487236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.4154487236
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3155411914
Short name T1068
Test name
Test status
Simulation time 117706005 ps
CPU time 2.32 seconds
Started Aug 06 07:46:06 PM PDT 24
Finished Aug 06 07:46:09 PM PDT 24
Peak memory 214896 kb
Host smart-c248c838-3254-442b-a926-1e777e391971
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155411914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3155411914
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.359804590
Short name T279
Test name
Test status
Simulation time 194261489 ps
CPU time 1.57 seconds
Started Aug 06 07:46:05 PM PDT 24
Finished Aug 06 07:46:07 PM PDT 24
Peak memory 207252 kb
Host smart-0ee81440-ae40-4b5e-a745-68d7f6ee4c2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359804590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.359804590
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3486438611
Short name T1014
Test name
Test status
Simulation time 64017378 ps
CPU time 1.48 seconds
Started Aug 06 07:46:10 PM PDT 24
Finished Aug 06 07:46:11 PM PDT 24
Peak memory 215032 kb
Host smart-dfa23d4b-5ad1-4a91-a6a3-b7cbe09730be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486438611 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3486438611
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3293802103
Short name T1102
Test name
Test status
Simulation time 24017580 ps
CPU time 0.87 seconds
Started Aug 06 07:46:10 PM PDT 24
Finished Aug 06 07:46:11 PM PDT 24
Peak memory 206648 kb
Host smart-f97cb536-012a-4a30-95ed-dc4475ef868b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293802103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3293802103
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1022088335
Short name T1120
Test name
Test status
Simulation time 88334517 ps
CPU time 0.82 seconds
Started Aug 06 07:46:09 PM PDT 24
Finished Aug 06 07:46:10 PM PDT 24
Peak memory 206472 kb
Host smart-17b83e16-be0d-4660-9584-2c6187392bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022088335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1022088335
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3256779717
Short name T1037
Test name
Test status
Simulation time 20017166 ps
CPU time 1.16 seconds
Started Aug 06 07:46:08 PM PDT 24
Finished Aug 06 07:46:09 PM PDT 24
Peak memory 206756 kb
Host smart-fa5d8801-0a17-4fa1-9a79-e54641819682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256779717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3256779717
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.770363027
Short name T1090
Test name
Test status
Simulation time 252823321 ps
CPU time 4 seconds
Started Aug 06 07:46:11 PM PDT 24
Finished Aug 06 07:46:15 PM PDT 24
Peak memory 214920 kb
Host smart-f4708b86-8cc1-4006-b499-32abcfe8ac5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770363027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.770363027
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.569238489
Short name T1098
Test name
Test status
Simulation time 252763908 ps
CPU time 1.47 seconds
Started Aug 06 07:46:08 PM PDT 24
Finished Aug 06 07:46:09 PM PDT 24
Peak memory 206732 kb
Host smart-7f2b1df4-b59c-488b-b951-0a7e432db501
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569238489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.569238489
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2885784101
Short name T1021
Test name
Test status
Simulation time 27811801 ps
CPU time 1.35 seconds
Started Aug 06 07:46:08 PM PDT 24
Finished Aug 06 07:46:09 PM PDT 24
Peak memory 214944 kb
Host smart-6385d794-016e-45aa-8fca-3fdd4a5db206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885784101 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2885784101
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1448291530
Short name T1091
Test name
Test status
Simulation time 41468560 ps
CPU time 0.83 seconds
Started Aug 06 07:46:09 PM PDT 24
Finished Aug 06 07:46:09 PM PDT 24
Peak memory 206524 kb
Host smart-27562161-20d7-462b-99eb-139c5a3fe259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448291530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1448291530
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1570498811
Short name T992
Test name
Test status
Simulation time 36718065 ps
CPU time 0.86 seconds
Started Aug 06 07:46:11 PM PDT 24
Finished Aug 06 07:46:12 PM PDT 24
Peak memory 206440 kb
Host smart-860ea0ca-2e2e-4d30-a9de-0fd35d811184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570498811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1570498811
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3995594518
Short name T1044
Test name
Test status
Simulation time 54070188 ps
CPU time 1.09 seconds
Started Aug 06 07:46:12 PM PDT 24
Finished Aug 06 07:46:13 PM PDT 24
Peak memory 206792 kb
Host smart-f480cffe-827c-45db-91e0-43837370d8c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995594518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3995594518
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.531189134
Short name T1022
Test name
Test status
Simulation time 342783645 ps
CPU time 2.39 seconds
Started Aug 06 07:46:13 PM PDT 24
Finished Aug 06 07:46:16 PM PDT 24
Peak memory 214912 kb
Host smart-d8253842-7ed5-45b9-975d-0a85290ecb1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531189134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.531189134
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3452269899
Short name T1049
Test name
Test status
Simulation time 91418109 ps
CPU time 2.63 seconds
Started Aug 06 07:46:12 PM PDT 24
Finished Aug 06 07:46:15 PM PDT 24
Peak memory 207024 kb
Host smart-f0c30476-ee12-4f4a-8e41-bcda69c02f29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452269899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3452269899
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3491481602
Short name T994
Test name
Test status
Simulation time 113636374 ps
CPU time 1.14 seconds
Started Aug 06 07:46:11 PM PDT 24
Finished Aug 06 07:46:12 PM PDT 24
Peak memory 215016 kb
Host smart-99364479-5def-470a-847e-9f7ddd8a6f2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491481602 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3491481602
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1455353486
Short name T1035
Test name
Test status
Simulation time 43188681 ps
CPU time 0.85 seconds
Started Aug 06 07:46:09 PM PDT 24
Finished Aug 06 07:46:10 PM PDT 24
Peak memory 206624 kb
Host smart-fb724084-5954-4709-8450-7fc4bfdc1933
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455353486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1455353486
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1201120510
Short name T1057
Test name
Test status
Simulation time 102397607 ps
CPU time 0.86 seconds
Started Aug 06 07:46:08 PM PDT 24
Finished Aug 06 07:46:09 PM PDT 24
Peak memory 206544 kb
Host smart-5fbd90de-d855-4d98-a564-d9f49c61687e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201120510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1201120510
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2614751339
Short name T1056
Test name
Test status
Simulation time 41891763 ps
CPU time 1.14 seconds
Started Aug 06 07:46:10 PM PDT 24
Finished Aug 06 07:46:11 PM PDT 24
Peak memory 206760 kb
Host smart-87258b96-5c06-4b32-a23b-4f4c02009a22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614751339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2614751339
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2041670729
Short name T1017
Test name
Test status
Simulation time 54068621 ps
CPU time 2.15 seconds
Started Aug 06 07:46:12 PM PDT 24
Finished Aug 06 07:46:14 PM PDT 24
Peak memory 218464 kb
Host smart-8e6488bf-39c3-4585-bc5d-01e0eb42c25a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041670729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2041670729
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.105857294
Short name T1050
Test name
Test status
Simulation time 79733684 ps
CPU time 2.2 seconds
Started Aug 06 07:46:06 PM PDT 24
Finished Aug 06 07:46:08 PM PDT 24
Peak memory 207172 kb
Host smart-c31383d6-ba62-4fcd-bef5-90ff267cadae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105857294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.105857294
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2896546875
Short name T1085
Test name
Test status
Simulation time 81960309 ps
CPU time 1.27 seconds
Started Aug 06 07:46:11 PM PDT 24
Finished Aug 06 07:46:12 PM PDT 24
Peak memory 215040 kb
Host smart-9836cda5-134f-4a11-878b-0494549d9341
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896546875 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2896546875
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2497040868
Short name T244
Test name
Test status
Simulation time 13968670 ps
CPU time 0.9 seconds
Started Aug 06 07:46:13 PM PDT 24
Finished Aug 06 07:46:14 PM PDT 24
Peak memory 206640 kb
Host smart-a43f856c-c86d-493c-8658-d88df2a38099
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497040868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2497040868
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.424684377
Short name T1112
Test name
Test status
Simulation time 22410116 ps
CPU time 0.84 seconds
Started Aug 06 07:46:08 PM PDT 24
Finished Aug 06 07:46:09 PM PDT 24
Peak memory 206544 kb
Host smart-2f687342-c1a0-4a82-9b10-c8764a7a7d93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424684377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.424684377
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.696109125
Short name T248
Test name
Test status
Simulation time 44088711 ps
CPU time 1.56 seconds
Started Aug 06 07:46:11 PM PDT 24
Finished Aug 06 07:46:13 PM PDT 24
Peak memory 206724 kb
Host smart-88cd9f5f-76cc-4678-be71-2b170ce8b976
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696109125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.696109125
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.50547752
Short name T1119
Test name
Test status
Simulation time 47134639 ps
CPU time 1.88 seconds
Started Aug 06 07:46:11 PM PDT 24
Finished Aug 06 07:46:13 PM PDT 24
Peak memory 214992 kb
Host smart-b079f3db-e7a5-4998-a7bc-45bdc84d12a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50547752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.50547752
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2855869197
Short name T1121
Test name
Test status
Simulation time 210631971 ps
CPU time 2.28 seconds
Started Aug 06 07:46:12 PM PDT 24
Finished Aug 06 07:46:15 PM PDT 24
Peak memory 206876 kb
Host smart-8a2f53e5-f924-4551-8e15-97eb5e93e88b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855869197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2855869197
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1852380487
Short name T1079
Test name
Test status
Simulation time 46722618 ps
CPU time 1.24 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:31 PM PDT 24
Peak memory 215080 kb
Host smart-e39b60f3-13c2-4f6a-b2b7-cb5814b5ad5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852380487 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1852380487
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.4142974332
Short name T251
Test name
Test status
Simulation time 23965954 ps
CPU time 0.93 seconds
Started Aug 06 07:46:26 PM PDT 24
Finished Aug 06 07:46:27 PM PDT 24
Peak memory 206660 kb
Host smart-283a4c98-32db-49d1-b189-37b58b860814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142974332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.4142974332
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3349403474
Short name T1078
Test name
Test status
Simulation time 38444735 ps
CPU time 0.79 seconds
Started Aug 06 07:46:21 PM PDT 24
Finished Aug 06 07:46:22 PM PDT 24
Peak memory 206460 kb
Host smart-e09a487c-3e37-42e7-9410-ee2005f21ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349403474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3349403474
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2031751720
Short name T1125
Test name
Test status
Simulation time 36138503 ps
CPU time 1.14 seconds
Started Aug 06 07:46:21 PM PDT 24
Finished Aug 06 07:46:22 PM PDT 24
Peak memory 206728 kb
Host smart-a81217b0-54b9-4aed-8016-0f5f11f2170f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031751720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2031751720
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1380639599
Short name T1073
Test name
Test status
Simulation time 25833507 ps
CPU time 1.47 seconds
Started Aug 06 07:46:22 PM PDT 24
Finished Aug 06 07:46:23 PM PDT 24
Peak memory 215012 kb
Host smart-0254e0ea-7984-4695-ad88-7f8f5595e2bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380639599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1380639599
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2376863617
Short name T1118
Test name
Test status
Simulation time 149249957 ps
CPU time 1.52 seconds
Started Aug 06 07:46:26 PM PDT 24
Finished Aug 06 07:46:27 PM PDT 24
Peak memory 206752 kb
Host smart-8ce8bd78-bfa9-4fcf-ba32-07906791d89a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376863617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2376863617
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2638121378
Short name T1012
Test name
Test status
Simulation time 82899035 ps
CPU time 1.31 seconds
Started Aug 06 07:46:28 PM PDT 24
Finished Aug 06 07:46:30 PM PDT 24
Peak memory 215004 kb
Host smart-cbf1b039-9891-4395-a5fc-471ae3b9a7b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638121378 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2638121378
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2967410780
Short name T1122
Test name
Test status
Simulation time 158900595 ps
CPU time 0.92 seconds
Started Aug 06 07:46:23 PM PDT 24
Finished Aug 06 07:46:24 PM PDT 24
Peak memory 206668 kb
Host smart-ee4117e9-9886-425a-9d4d-59e01058ba71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967410780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2967410780
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.110404071
Short name T1064
Test name
Test status
Simulation time 24066665 ps
CPU time 0.85 seconds
Started Aug 06 07:46:22 PM PDT 24
Finished Aug 06 07:46:23 PM PDT 24
Peak memory 206552 kb
Host smart-a6d7b03f-b754-4df4-bebb-371035b85aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110404071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.110404071
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4140248385
Short name T1059
Test name
Test status
Simulation time 30138705 ps
CPU time 1.1 seconds
Started Aug 06 07:46:23 PM PDT 24
Finished Aug 06 07:46:25 PM PDT 24
Peak memory 206764 kb
Host smart-134034c1-4495-4924-9d97-8bdad4bbca40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140248385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.4140248385
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1395356556
Short name T1031
Test name
Test status
Simulation time 175000810 ps
CPU time 3.22 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:33 PM PDT 24
Peak memory 215012 kb
Host smart-63896b5e-fb14-45ac-99ad-be33e9b9a889
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395356556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1395356556
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1596587423
Short name T1097
Test name
Test status
Simulation time 83180446 ps
CPU time 1.45 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206688 kb
Host smart-b23bc807-5cce-41c8-9001-3829fdd3b130
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596587423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1596587423
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1779279005
Short name T1001
Test name
Test status
Simulation time 457923428 ps
CPU time 3.36 seconds
Started Aug 06 07:45:58 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 206652 kb
Host smart-e57fa658-0c48-4a86-968a-a8c6a6704b5a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779279005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1779279005
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2358577626
Short name T255
Test name
Test status
Simulation time 36446836 ps
CPU time 0.82 seconds
Started Aug 06 07:45:55 PM PDT 24
Finished Aug 06 07:45:56 PM PDT 24
Peak memory 206540 kb
Host smart-4560ccfb-1154-435d-83ab-53b1b799192f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358577626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2358577626
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1636556707
Short name T1018
Test name
Test status
Simulation time 50213352 ps
CPU time 1.74 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 215032 kb
Host smart-c4d01838-06d4-4ebd-826e-05235cade713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636556707 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1636556707
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3718359375
Short name T1067
Test name
Test status
Simulation time 20523962 ps
CPU time 0.91 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 206664 kb
Host smart-996bac78-97a9-4eb9-ba9d-1cba6779f540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718359375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3718359375
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2260383000
Short name T1086
Test name
Test status
Simulation time 11013250 ps
CPU time 0.82 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:58 PM PDT 24
Peak memory 206512 kb
Host smart-2d1ae2ec-67f4-4966-97a3-93d94b55ed78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260383000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2260383000
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1080200156
Short name T261
Test name
Test status
Simulation time 51509717 ps
CPU time 1.1 seconds
Started Aug 06 07:45:58 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 206724 kb
Host smart-45b9d445-4aea-428a-8617-ea1517ac7012
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080200156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1080200156
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4181100975
Short name T1043
Test name
Test status
Simulation time 2211159436 ps
CPU time 4.68 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 215048 kb
Host smart-cbfb0acd-cba8-4fb5-8f22-4a8100213aab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181100975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4181100975
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2978210870
Short name T1036
Test name
Test status
Simulation time 223407117 ps
CPU time 1.72 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206996 kb
Host smart-48824743-af9a-45af-b9db-17887dddda91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978210870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2978210870
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.172748326
Short name T1006
Test name
Test status
Simulation time 25650075 ps
CPU time 0.84 seconds
Started Aug 06 07:46:22 PM PDT 24
Finished Aug 06 07:46:23 PM PDT 24
Peak memory 206500 kb
Host smart-ce19a6b3-83f3-44b7-80c1-be2abd49d6ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172748326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.172748326
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1323448804
Short name T995
Test name
Test status
Simulation time 26779045 ps
CPU time 0.79 seconds
Started Aug 06 07:46:24 PM PDT 24
Finished Aug 06 07:46:25 PM PDT 24
Peak memory 206440 kb
Host smart-c7d8874b-413d-4c41-bf3a-1fc986c194cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323448804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1323448804
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2983506399
Short name T1051
Test name
Test status
Simulation time 11114923 ps
CPU time 0.87 seconds
Started Aug 06 07:46:26 PM PDT 24
Finished Aug 06 07:46:27 PM PDT 24
Peak memory 206544 kb
Host smart-cde55b57-d222-40f2-9388-4753335bd4ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983506399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2983506399
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3598141713
Short name T1081
Test name
Test status
Simulation time 107263264 ps
CPU time 0.81 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:31 PM PDT 24
Peak memory 206496 kb
Host smart-fbbef28f-a00f-4cab-a741-8d6ff1750d8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598141713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3598141713
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3000072937
Short name T1071
Test name
Test status
Simulation time 147196737 ps
CPU time 0.84 seconds
Started Aug 06 07:46:23 PM PDT 24
Finished Aug 06 07:46:24 PM PDT 24
Peak memory 206476 kb
Host smart-a0a6e075-aaf5-4935-8b8b-cda858efd6e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000072937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3000072937
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2874529861
Short name T1103
Test name
Test status
Simulation time 27761432 ps
CPU time 0.77 seconds
Started Aug 06 07:46:27 PM PDT 24
Finished Aug 06 07:46:28 PM PDT 24
Peak memory 206492 kb
Host smart-e094dd3b-003e-4737-b5df-de154f83a073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874529861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2874529861
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2199886248
Short name T1000
Test name
Test status
Simulation time 23185494 ps
CPU time 0.92 seconds
Started Aug 06 07:46:24 PM PDT 24
Finished Aug 06 07:46:25 PM PDT 24
Peak memory 206544 kb
Host smart-abc6a595-8235-4216-a858-5f0c8e1a0a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199886248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2199886248
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.97941344
Short name T1002
Test name
Test status
Simulation time 11235423 ps
CPU time 0.84 seconds
Started Aug 06 07:46:23 PM PDT 24
Finished Aug 06 07:46:24 PM PDT 24
Peak memory 206536 kb
Host smart-2038d888-f037-40f0-8756-cbbbec800bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97941344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.97941344
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2186789537
Short name T1113
Test name
Test status
Simulation time 34111539 ps
CPU time 0.8 seconds
Started Aug 06 07:46:27 PM PDT 24
Finished Aug 06 07:46:28 PM PDT 24
Peak memory 206492 kb
Host smart-b658fb70-cf62-4d5b-a6ad-b444dd2471c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186789537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2186789537
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1681432156
Short name T1108
Test name
Test status
Simulation time 202136070 ps
CPU time 0.83 seconds
Started Aug 06 07:46:22 PM PDT 24
Finished Aug 06 07:46:23 PM PDT 24
Peak memory 206444 kb
Host smart-8a42ff99-5a55-445a-8fc8-1eb930d24691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681432156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1681432156
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3253396624
Short name T246
Test name
Test status
Simulation time 25166503 ps
CPU time 1.22 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206600 kb
Host smart-54f779bd-f7b4-40e7-a754-ee075bbd66a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253396624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3253396624
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4129299549
Short name T257
Test name
Test status
Simulation time 144781431 ps
CPU time 3.31 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 206728 kb
Host smart-646cc42e-aea1-468e-b3b5-7d2eedce8fc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129299549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.4129299549
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1927729222
Short name T1039
Test name
Test status
Simulation time 118125631 ps
CPU time 0.93 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:58 PM PDT 24
Peak memory 206640 kb
Host smart-efd98a4e-fefb-4aeb-9d7f-88fde27a58b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927729222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1927729222
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2979599459
Short name T996
Test name
Test status
Simulation time 27122864 ps
CPU time 1.78 seconds
Started Aug 06 07:45:55 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 215092 kb
Host smart-e3422464-9934-4f5e-b239-ac18013f1a9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979599459 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2979599459
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1685673839
Short name T1082
Test name
Test status
Simulation time 21578110 ps
CPU time 0.91 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 206688 kb
Host smart-364002bf-f760-4ff0-8fd1-4074dbfe1891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685673839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1685673839
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.62490705
Short name T1029
Test name
Test status
Simulation time 161407633 ps
CPU time 0.9 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 206316 kb
Host smart-7ac50cc7-c888-435e-8668-f7ea85abb429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62490705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.62490705
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2913245688
Short name T1075
Test name
Test status
Simulation time 18158448 ps
CPU time 1.2 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206764 kb
Host smart-d7459c8d-c448-4170-b5f4-2da1aa455a70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913245688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2913245688
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3563816495
Short name T1101
Test name
Test status
Simulation time 33685346 ps
CPU time 2.16 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:58 PM PDT 24
Peak memory 215024 kb
Host smart-a9a1cd64-46fc-4a1d-83a8-82c22231ff64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563816495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3563816495
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3537181751
Short name T275
Test name
Test status
Simulation time 250290237 ps
CPU time 1.99 seconds
Started Aug 06 07:45:55 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 206792 kb
Host smart-1a176091-874b-45c4-8632-83eb0d488ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537181751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3537181751
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1159568446
Short name T1005
Test name
Test status
Simulation time 43002502 ps
CPU time 0.85 seconds
Started Aug 06 07:46:23 PM PDT 24
Finished Aug 06 07:46:24 PM PDT 24
Peak memory 206600 kb
Host smart-51cb1b60-4590-441b-9e9f-3b3aeae31973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159568446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1159568446
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.4131876609
Short name T1063
Test name
Test status
Simulation time 24483122 ps
CPU time 0.87 seconds
Started Aug 06 07:46:26 PM PDT 24
Finished Aug 06 07:46:27 PM PDT 24
Peak memory 206740 kb
Host smart-44d4fbad-0e31-4ff0-9d2a-f5f0a79af64d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131876609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.4131876609
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3399715646
Short name T1047
Test name
Test status
Simulation time 16500034 ps
CPU time 0.84 seconds
Started Aug 06 07:46:25 PM PDT 24
Finished Aug 06 07:46:26 PM PDT 24
Peak memory 206500 kb
Host smart-979f8721-aa48-4852-b9e1-f765763a1b0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399715646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3399715646
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3083983912
Short name T1100
Test name
Test status
Simulation time 17773468 ps
CPU time 0.85 seconds
Started Aug 06 07:46:21 PM PDT 24
Finished Aug 06 07:46:22 PM PDT 24
Peak memory 206548 kb
Host smart-c56c42ea-07cd-404e-ad0f-d83cb7da2922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083983912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3083983912
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.4275757506
Short name T1069
Test name
Test status
Simulation time 56021987 ps
CPU time 0.88 seconds
Started Aug 06 07:46:28 PM PDT 24
Finished Aug 06 07:46:29 PM PDT 24
Peak memory 206512 kb
Host smart-a36ee341-68fb-41e8-b010-d5ec2a0a9cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275757506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.4275757506
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1660735510
Short name T1038
Test name
Test status
Simulation time 40109869 ps
CPU time 0.79 seconds
Started Aug 06 07:46:24 PM PDT 24
Finished Aug 06 07:46:25 PM PDT 24
Peak memory 206456 kb
Host smart-221d2e89-32c4-4c1a-b6ed-154ad8964d03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660735510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1660735510
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2518208950
Short name T989
Test name
Test status
Simulation time 25579885 ps
CPU time 0.88 seconds
Started Aug 06 07:46:28 PM PDT 24
Finished Aug 06 07:46:29 PM PDT 24
Peak memory 206476 kb
Host smart-7879cc98-acaf-4e73-983f-be8b931c9506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518208950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2518208950
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2960503012
Short name T1030
Test name
Test status
Simulation time 39172581 ps
CPU time 0.77 seconds
Started Aug 06 07:46:26 PM PDT 24
Finished Aug 06 07:46:27 PM PDT 24
Peak memory 206668 kb
Host smart-7ec9bfb7-93b6-4449-b88e-555501c4cf40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960503012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2960503012
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1525850974
Short name T1016
Test name
Test status
Simulation time 26710384 ps
CPU time 0.85 seconds
Started Aug 06 07:46:26 PM PDT 24
Finished Aug 06 07:46:27 PM PDT 24
Peak memory 206536 kb
Host smart-2fde123a-bd69-4d78-8a4f-7f10e4cc8073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525850974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1525850974
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.4219245270
Short name T1025
Test name
Test status
Simulation time 22094040 ps
CPU time 0.87 seconds
Started Aug 06 07:46:23 PM PDT 24
Finished Aug 06 07:46:24 PM PDT 24
Peak memory 206544 kb
Host smart-0f9f2b13-9a7c-4466-b8a6-9a98f3f5e5f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219245270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.4219245270
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2522444579
Short name T259
Test name
Test status
Simulation time 39491405 ps
CPU time 1.59 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206668 kb
Host smart-a3018047-c487-4f57-9240-d3c3b722ab19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522444579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2522444579
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3597844095
Short name T1011
Test name
Test status
Simulation time 948131403 ps
CPU time 5.61 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:46:03 PM PDT 24
Peak memory 206720 kb
Host smart-f936abb4-8daa-4af3-a753-669a6c7ca871
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597844095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3597844095
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1514022105
Short name T1065
Test name
Test status
Simulation time 15112056 ps
CPU time 0.96 seconds
Started Aug 06 07:45:58 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206596 kb
Host smart-52b66421-abce-4dc0-910d-95033f61b91a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514022105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1514022105
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3873126651
Short name T1074
Test name
Test status
Simulation time 157562156 ps
CPU time 1.24 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 215080 kb
Host smart-78e99b38-c4ae-4a67-af1f-516d828ca57a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873126651 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3873126651
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1859481296
Short name T247
Test name
Test status
Simulation time 103444968 ps
CPU time 0.86 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 206572 kb
Host smart-96be3684-b155-41c4-946d-72088967f2bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859481296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1859481296
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3534121348
Short name T1055
Test name
Test status
Simulation time 22766437 ps
CPU time 0.86 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:58 PM PDT 24
Peak memory 206480 kb
Host smart-802da4c8-11ee-4788-9e28-95fb01d1fc5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534121348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3534121348
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2824530336
Short name T1048
Test name
Test status
Simulation time 29272042 ps
CPU time 1.03 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 206560 kb
Host smart-194a7797-40d1-425c-8672-28aa23ab96e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824530336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2824530336
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.730841484
Short name T1052
Test name
Test status
Simulation time 171497722 ps
CPU time 3.47 seconds
Started Aug 06 07:45:55 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 215000 kb
Host smart-49147d97-a058-4ab6-be45-4d6da5a41ece
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730841484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.730841484
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2558191129
Short name T215
Test name
Test status
Simulation time 72592715 ps
CPU time 1.95 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 206672 kb
Host smart-f7d1dde6-13f2-4b83-bac2-033b5dea4c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558191129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2558191129
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.4145933131
Short name T1110
Test name
Test status
Simulation time 21385887 ps
CPU time 0.81 seconds
Started Aug 06 07:46:24 PM PDT 24
Finished Aug 06 07:46:24 PM PDT 24
Peak memory 206440 kb
Host smart-ad9699b8-fbde-4b8e-8492-95bb00b6a85f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145933131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.4145933131
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1863782979
Short name T1124
Test name
Test status
Simulation time 16038185 ps
CPU time 0.93 seconds
Started Aug 06 07:46:26 PM PDT 24
Finished Aug 06 07:46:27 PM PDT 24
Peak memory 206544 kb
Host smart-fca2da11-a40d-46ed-9d72-6d02efe7c7e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863782979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1863782979
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2367468067
Short name T1099
Test name
Test status
Simulation time 22105797 ps
CPU time 0.88 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:31 PM PDT 24
Peak memory 206552 kb
Host smart-0c4c7c5e-74d3-4152-96e9-3df5adce2f0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367468067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2367468067
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.4202827176
Short name T1013
Test name
Test status
Simulation time 19469674 ps
CPU time 0.86 seconds
Started Aug 06 07:46:27 PM PDT 24
Finished Aug 06 07:46:28 PM PDT 24
Peak memory 206564 kb
Host smart-4f108224-b058-4455-8dc6-7c62cf630b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202827176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.4202827176
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1952299283
Short name T1033
Test name
Test status
Simulation time 18318247 ps
CPU time 0.88 seconds
Started Aug 06 07:46:24 PM PDT 24
Finished Aug 06 07:46:25 PM PDT 24
Peak memory 206504 kb
Host smart-95197212-ae57-4d04-95eb-c9259db30ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952299283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1952299283
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1945736499
Short name T1123
Test name
Test status
Simulation time 47593192 ps
CPU time 0.84 seconds
Started Aug 06 07:46:25 PM PDT 24
Finished Aug 06 07:46:26 PM PDT 24
Peak memory 206588 kb
Host smart-6f07ac98-ecad-41c5-9957-38ce43985eda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945736499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1945736499
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1728599480
Short name T1015
Test name
Test status
Simulation time 38279612 ps
CPU time 0.81 seconds
Started Aug 06 07:46:25 PM PDT 24
Finished Aug 06 07:46:26 PM PDT 24
Peak memory 206456 kb
Host smart-1fe6e683-e551-469c-9ae4-bfd8ee55581e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728599480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1728599480
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.859143011
Short name T1023
Test name
Test status
Simulation time 11241919 ps
CPU time 0.88 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:31 PM PDT 24
Peak memory 206544 kb
Host smart-aa1a5a31-5d30-4083-81f6-d5df22fc7c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859143011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.859143011
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2209795198
Short name T1105
Test name
Test status
Simulation time 48506918 ps
CPU time 0.84 seconds
Started Aug 06 07:46:25 PM PDT 24
Finished Aug 06 07:46:26 PM PDT 24
Peak memory 206584 kb
Host smart-59c92746-d77a-4918-8984-b017dcf7c569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209795198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2209795198
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3238595459
Short name T1096
Test name
Test status
Simulation time 23726963 ps
CPU time 0.83 seconds
Started Aug 06 07:46:22 PM PDT 24
Finished Aug 06 07:46:23 PM PDT 24
Peak memory 206616 kb
Host smart-66ab998e-d86f-4f3f-801d-d0d37a528b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238595459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3238595459
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3396461282
Short name T1019
Test name
Test status
Simulation time 27515116 ps
CPU time 1.58 seconds
Started Aug 06 07:46:00 PM PDT 24
Finished Aug 06 07:46:02 PM PDT 24
Peak memory 214936 kb
Host smart-68525241-b3c4-4d0b-b038-c1f783025d4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396461282 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3396461282
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1705279636
Short name T1040
Test name
Test status
Simulation time 48567003 ps
CPU time 0.86 seconds
Started Aug 06 07:46:00 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 206584 kb
Host smart-4f9db177-d962-40b2-91ce-58472646a0c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705279636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1705279636
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.4266714593
Short name T1003
Test name
Test status
Simulation time 23038464 ps
CPU time 0.87 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206536 kb
Host smart-babc5779-65a9-49ca-9837-4b7a52b08219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266714593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.4266714593
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4235170447
Short name T1089
Test name
Test status
Simulation time 21235961 ps
CPU time 1.12 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 206660 kb
Host smart-64fc08ef-d135-4073-851f-7e3374de5229
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235170447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.4235170447
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3497586187
Short name T1010
Test name
Test status
Simulation time 86904900 ps
CPU time 1.69 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 215008 kb
Host smart-744ae3a7-39ef-47ea-9715-c7a7b3d5ceed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497586187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3497586187
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3635242175
Short name T1107
Test name
Test status
Simulation time 162058963 ps
CPU time 1.7 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206724 kb
Host smart-5e1163db-e5e6-41da-94e3-f98406483328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635242175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3635242175
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1308865308
Short name T1027
Test name
Test status
Simulation time 100087115 ps
CPU time 1.26 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 215000 kb
Host smart-f0c427c5-c1d6-4036-b473-4bbc03f70c55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308865308 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1308865308
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.497339037
Short name T258
Test name
Test status
Simulation time 14769383 ps
CPU time 0.89 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 206624 kb
Host smart-7cbf8625-0894-4d2d-b0b9-87d038c381f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497339037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.497339037
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.445654097
Short name T1087
Test name
Test status
Simulation time 16863603 ps
CPU time 0.83 seconds
Started Aug 06 07:45:58 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206564 kb
Host smart-6263a680-625d-4298-b3b2-6d39db041bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445654097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.445654097
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.867547113
Short name T249
Test name
Test status
Simulation time 26552255 ps
CPU time 0.95 seconds
Started Aug 06 07:45:58 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206744 kb
Host smart-1b2a5aeb-71d4-49a2-aa36-7be51810f75e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867547113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.867547113
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3803036986
Short name T999
Test name
Test status
Simulation time 113559540 ps
CPU time 2.15 seconds
Started Aug 06 07:46:00 PM PDT 24
Finished Aug 06 07:46:02 PM PDT 24
Peak memory 214972 kb
Host smart-0d8727da-2182-4c38-882c-a1e935f78fae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803036986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3803036986
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2985090390
Short name T1061
Test name
Test status
Simulation time 102949801 ps
CPU time 2.18 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 206776 kb
Host smart-08cc5c74-df81-49f0-a94d-c3496291b168
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985090390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2985090390
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2772132748
Short name T1062
Test name
Test status
Simulation time 18095194 ps
CPU time 1.08 seconds
Started Aug 06 07:45:58 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 216404 kb
Host smart-28909838-d648-4def-b141-79406dba30bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772132748 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2772132748
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1350221701
Short name T1084
Test name
Test status
Simulation time 58799056 ps
CPU time 0.85 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 206480 kb
Host smart-45881c59-94cb-4770-a8f0-5dc1e16ed64f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350221701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1350221701
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1143144103
Short name T1093
Test name
Test status
Simulation time 71168338 ps
CPU time 0.9 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 206492 kb
Host smart-88897acd-18f4-48d4-a72b-213320cdb431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143144103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1143144103
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1204320242
Short name T263
Test name
Test status
Simulation time 41351243 ps
CPU time 1.05 seconds
Started Aug 06 07:45:58 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 206688 kb
Host smart-5bba438a-e591-43d2-be1b-4379670a21d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204320242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1204320242
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3575881462
Short name T1076
Test name
Test status
Simulation time 110984218 ps
CPU time 1.66 seconds
Started Aug 06 07:45:53 PM PDT 24
Finished Aug 06 07:45:55 PM PDT 24
Peak memory 214900 kb
Host smart-e80a59ba-cf3a-4c96-95ee-28ec543084b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575881462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3575881462
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.913895917
Short name T1028
Test name
Test status
Simulation time 129457403 ps
CPU time 2.16 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 214948 kb
Host smart-9f1752fc-41b1-4b9c-b20b-8f2281c5b389
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913895917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.913895917
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.569787220
Short name T1053
Test name
Test status
Simulation time 46029542 ps
CPU time 1.1 seconds
Started Aug 06 07:46:00 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 214960 kb
Host smart-3bbb5cf3-c3ec-4111-aabf-e393c52666a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569787220 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.569787220
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.304575624
Short name T260
Test name
Test status
Simulation time 102288497 ps
CPU time 0.84 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 206480 kb
Host smart-9699288f-ba95-4e22-91ac-34b9f549e0b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304575624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.304575624
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1809625412
Short name T1066
Test name
Test status
Simulation time 22369352 ps
CPU time 0.85 seconds
Started Aug 06 07:46:06 PM PDT 24
Finished Aug 06 07:46:07 PM PDT 24
Peak memory 206568 kb
Host smart-e271c14b-b6d6-42c6-9d89-25a38035c6ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809625412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1809625412
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2260063094
Short name T1077
Test name
Test status
Simulation time 79170416 ps
CPU time 1.04 seconds
Started Aug 06 07:46:01 PM PDT 24
Finished Aug 06 07:46:02 PM PDT 24
Peak memory 206692 kb
Host smart-de2bf939-4a3d-4989-8cc1-9b552e2d83fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260063094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2260063094
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1468218046
Short name T997
Test name
Test status
Simulation time 34821738 ps
CPU time 1.48 seconds
Started Aug 06 07:46:05 PM PDT 24
Finished Aug 06 07:46:07 PM PDT 24
Peak memory 215016 kb
Host smart-cad1de3b-500d-4e5a-a421-99fd3cf1f046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468218046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1468218046
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1487871363
Short name T1024
Test name
Test status
Simulation time 465986726 ps
CPU time 2.41 seconds
Started Aug 06 07:46:06 PM PDT 24
Finished Aug 06 07:46:08 PM PDT 24
Peak memory 206828 kb
Host smart-ac6d1cda-29eb-41a4-ae12-862cf0b38b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487871363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1487871363
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.140130729
Short name T1058
Test name
Test status
Simulation time 261247599 ps
CPU time 1.31 seconds
Started Aug 06 07:46:06 PM PDT 24
Finished Aug 06 07:46:07 PM PDT 24
Peak memory 218420 kb
Host smart-360d5d2a-1e31-491e-bb73-7a80f00d7608
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140130729 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.140130729
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3808502969
Short name T256
Test name
Test status
Simulation time 16366341 ps
CPU time 0.81 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 206552 kb
Host smart-ab2983f2-6e9f-4f7b-81e2-4655426bd826
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808502969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3808502969
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2092392504
Short name T1046
Test name
Test status
Simulation time 31755805 ps
CPU time 0.78 seconds
Started Aug 06 07:45:54 PM PDT 24
Finished Aug 06 07:45:54 PM PDT 24
Peak memory 206396 kb
Host smart-32cdb291-aa8e-46ae-bb64-71f6e41df637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092392504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2092392504
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3138104504
Short name T262
Test name
Test status
Simulation time 81849587 ps
CPU time 1.06 seconds
Started Aug 06 07:46:00 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 206696 kb
Host smart-446ec5d7-3c3d-46aa-82f3-78e29954b5f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138104504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3138104504
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3233953925
Short name T1045
Test name
Test status
Simulation time 507239220 ps
CPU time 3.54 seconds
Started Aug 06 07:46:06 PM PDT 24
Finished Aug 06 07:46:09 PM PDT 24
Peak memory 214828 kb
Host smart-a18ee4c3-898c-4151-ba02-33a6fc2beff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233953925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3233953925
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3279917649
Short name T277
Test name
Test status
Simulation time 55273214 ps
CPU time 1.72 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 206824 kb
Host smart-8d369f15-727c-42e5-81f2-66ef49932b08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279917649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3279917649
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.528995034
Short name T238
Test name
Test status
Simulation time 22460436 ps
CPU time 0.8 seconds
Started Aug 06 07:40:16 PM PDT 24
Finished Aug 06 07:40:17 PM PDT 24
Peak memory 206272 kb
Host smart-b372fa42-c856-442b-af4e-d6b64f50b83a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528995034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.528995034
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.4184431188
Short name T538
Test name
Test status
Simulation time 14408223 ps
CPU time 0.86 seconds
Started Aug 06 07:40:21 PM PDT 24
Finished Aug 06 07:40:22 PM PDT 24
Peak memory 215976 kb
Host smart-e69fa636-0bc4-4be1-8c69-35c0521b2d30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184431188 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.4184431188
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2176034857
Short name T828
Test name
Test status
Simulation time 358816933 ps
CPU time 1.12 seconds
Started Aug 06 07:40:21 PM PDT 24
Finished Aug 06 07:40:22 PM PDT 24
Peak memory 218140 kb
Host smart-102aac2f-7a92-4646-9b95-f29f56c6b1eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176034857 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2176034857
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_genbits.2787047878
Short name T396
Test name
Test status
Simulation time 37694813 ps
CPU time 1.07 seconds
Started Aug 06 07:40:05 PM PDT 24
Finished Aug 06 07:40:06 PM PDT 24
Peak memory 218116 kb
Host smart-66f28856-7b90-453f-8b32-8f45bc42293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787047878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2787047878
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_smoke.1589880134
Short name T61
Test name
Test status
Simulation time 27568584 ps
CPU time 0.91 seconds
Started Aug 06 07:40:09 PM PDT 24
Finished Aug 06 07:40:10 PM PDT 24
Peak memory 206708 kb
Host smart-23d4084a-0787-4b3a-b5e2-fa9825888e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589880134 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1589880134
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.376837139
Short name T854
Test name
Test status
Simulation time 495934181 ps
CPU time 4.95 seconds
Started Aug 06 07:40:21 PM PDT 24
Finished Aug 06 07:40:26 PM PDT 24
Peak memory 217056 kb
Host smart-982ddd71-4623-473e-a44f-92f47408d51c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376837139 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.376837139
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert_test.2981421219
Short name T811
Test name
Test status
Simulation time 47606245 ps
CPU time 0.84 seconds
Started Aug 06 07:40:38 PM PDT 24
Finished Aug 06 07:40:39 PM PDT 24
Peak memory 214584 kb
Host smart-1289eb42-57c7-4523-8621-3181ac4754ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981421219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2981421219
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3362861745
Short name T113
Test name
Test status
Simulation time 121485223 ps
CPU time 1.13 seconds
Started Aug 06 07:40:19 PM PDT 24
Finished Aug 06 07:40:20 PM PDT 24
Peak memory 216660 kb
Host smart-7007e703-06d6-4935-bd3c-98aea6376380
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362861745 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3362861745
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.141875216
Short name T703
Test name
Test status
Simulation time 28727226 ps
CPU time 1 seconds
Started Aug 06 07:40:19 PM PDT 24
Finished Aug 06 07:40:20 PM PDT 24
Peak memory 218280 kb
Host smart-1868cc87-e770-473d-9c8d-f3bc4067658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141875216 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.141875216
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2348278695
Short name T818
Test name
Test status
Simulation time 118103004 ps
CPU time 2.69 seconds
Started Aug 06 07:40:16 PM PDT 24
Finished Aug 06 07:40:19 PM PDT 24
Peak memory 218208 kb
Host smart-2edb0d89-7ff9-49a6-a9b9-59c5d9cf38ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348278695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2348278695
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.881854537
Short name T81
Test name
Test status
Simulation time 22481897 ps
CPU time 1.04 seconds
Started Aug 06 07:40:16 PM PDT 24
Finished Aug 06 07:40:17 PM PDT 24
Peak memory 215812 kb
Host smart-1eb6b5eb-087c-41b0-a409-966c437c8b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881854537 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.881854537
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3024807784
Short name T919
Test name
Test status
Simulation time 42197793 ps
CPU time 0.85 seconds
Started Aug 06 07:40:16 PM PDT 24
Finished Aug 06 07:40:17 PM PDT 24
Peak memory 206684 kb
Host smart-e7435826-e17a-41a3-8cc6-b6b6422623eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024807784 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3024807784
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1074726331
Short name T523
Test name
Test status
Simulation time 28796092 ps
CPU time 0.93 seconds
Started Aug 06 07:40:21 PM PDT 24
Finished Aug 06 07:40:22 PM PDT 24
Peak memory 214872 kb
Host smart-a421a7ee-b55e-49ef-a4c4-cbec5bd56d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074726331 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1074726331
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3700050364
Short name T677
Test name
Test status
Simulation time 368963220 ps
CPU time 6.91 seconds
Started Aug 06 07:40:21 PM PDT 24
Finished Aug 06 07:40:28 PM PDT 24
Peak memory 216956 kb
Host smart-7fd80694-26cf-4a51-aa17-1c02e6df9ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700050364 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3700050364
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2898920410
Short name T643
Test name
Test status
Simulation time 38829116220 ps
CPU time 695.38 seconds
Started Aug 06 07:40:17 PM PDT 24
Finished Aug 06 07:51:52 PM PDT 24
Peak memory 218440 kb
Host smart-31707fdd-32fe-4d9c-af07-c6263e251739
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898920410 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2898920410
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.781131416
Short name T805
Test name
Test status
Simulation time 13230077 ps
CPU time 0.83 seconds
Started Aug 06 07:41:35 PM PDT 24
Finished Aug 06 07:41:36 PM PDT 24
Peak memory 206408 kb
Host smart-97b9f49b-5ca2-49d8-af42-9fbae9d68dc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781131416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.781131416
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1542750714
Short name T876
Test name
Test status
Simulation time 12647506 ps
CPU time 0.85 seconds
Started Aug 06 07:41:32 PM PDT 24
Finished Aug 06 07:41:33 PM PDT 24
Peak memory 215940 kb
Host smart-82f88dc4-e5ee-49af-9a25-54809b17600f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542750714 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1542750714
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1027059407
Short name T167
Test name
Test status
Simulation time 46077086 ps
CPU time 1.23 seconds
Started Aug 06 07:41:36 PM PDT 24
Finished Aug 06 07:41:38 PM PDT 24
Peak memory 225212 kb
Host smart-c305f220-ed41-45a2-acad-814b79c09bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027059407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1027059407
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3764279826
Short name T58
Test name
Test status
Simulation time 57049154 ps
CPU time 1.19 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 07:41:34 PM PDT 24
Peak memory 214896 kb
Host smart-56049964-95f0-4ca5-b031-66a31045548b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764279826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3764279826
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3812334944
Short name T558
Test name
Test status
Simulation time 22759964 ps
CPU time 1.1 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 07:41:34 PM PDT 24
Peak memory 215084 kb
Host smart-f7ee7e13-a6f2-4947-9985-839b53298f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812334944 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3812334944
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.388979703
Short name T869
Test name
Test status
Simulation time 22719148 ps
CPU time 0.86 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 07:41:34 PM PDT 24
Peak memory 214836 kb
Host smart-1ea1f554-18cd-4ea7-bf03-1d56f8e97e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388979703 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.388979703
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2894183184
Short name T406
Test name
Test status
Simulation time 124043193 ps
CPU time 2.68 seconds
Started Aug 06 07:41:36 PM PDT 24
Finished Aug 06 07:41:39 PM PDT 24
Peak memory 218188 kb
Host smart-add53244-ed5e-4f97-bbcb-fbd0336a815f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894183184 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2894183184
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.390800006
Short name T372
Test name
Test status
Simulation time 51181180097 ps
CPU time 304.06 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 07:46:37 PM PDT 24
Peak memory 220376 kb
Host smart-61e20469-cfac-4de5-bce2-3505f70b706e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390800006 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.390800006
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.165292354
Short name T389
Test name
Test status
Simulation time 30524081 ps
CPU time 1.26 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 218792 kb
Host smart-59423a9c-79e6-47e4-a57f-c14916355376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165292354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.165292354
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.2390317362
Short name T970
Test name
Test status
Simulation time 47335495 ps
CPU time 1.26 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 219172 kb
Host smart-93b82156-2918-44be-9586-085ac31eb01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390317362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2390317362
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.2946540169
Short name T274
Test name
Test status
Simulation time 153044633 ps
CPU time 1.48 seconds
Started Aug 06 07:44:51 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 217092 kb
Host smart-b695801c-6c84-406b-8e07-2d728ebf0b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946540169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2946540169
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.388472887
Short name T269
Test name
Test status
Simulation time 48671916 ps
CPU time 1.04 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 217948 kb
Host smart-3a6488b7-805c-4068-8cc2-816f2f7aa882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388472887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.388472887
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.330316717
Short name T552
Test name
Test status
Simulation time 55429922 ps
CPU time 0.96 seconds
Started Aug 06 07:44:51 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 218844 kb
Host smart-a669a9bf-bbfb-4a5d-9d80-de2ca89a21a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330316717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.330316717
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.2249756842
Short name T441
Test name
Test status
Simulation time 258846032 ps
CPU time 1.39 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 218364 kb
Host smart-e63fa30e-4df2-4daa-98ed-9913ca7a2aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249756842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.2249756842
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.2075717030
Short name T870
Test name
Test status
Simulation time 230376536 ps
CPU time 2.88 seconds
Started Aug 06 07:44:51 PM PDT 24
Finished Aug 06 07:44:54 PM PDT 24
Peak memory 219544 kb
Host smart-edbfe6a2-10a0-4cc6-bffa-9c24f14c5d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075717030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2075717030
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2704730468
Short name T748
Test name
Test status
Simulation time 27418101 ps
CPU time 1.19 seconds
Started Aug 06 07:44:44 PM PDT 24
Finished Aug 06 07:44:45 PM PDT 24
Peak memory 219992 kb
Host smart-4a482c29-35e9-4ca8-a2a9-2ef86dad4c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704730468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2704730468
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.3033970345
Short name T736
Test name
Test status
Simulation time 43102770 ps
CPU time 1.12 seconds
Started Aug 06 07:44:49 PM PDT 24
Finished Aug 06 07:44:50 PM PDT 24
Peak memory 217168 kb
Host smart-af50250e-4eaa-42c7-a391-5488469d44fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033970345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3033970345
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.643370761
Short name T564
Test name
Test status
Simulation time 27646943 ps
CPU time 1.19 seconds
Started Aug 06 07:44:44 PM PDT 24
Finished Aug 06 07:44:46 PM PDT 24
Peak memory 220336 kb
Host smart-e14c656e-3846-43a0-be84-fd013435bb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643370761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.643370761
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.1870254041
Short name T499
Test name
Test status
Simulation time 195199127 ps
CPU time 1.19 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:47 PM PDT 24
Peak memory 219464 kb
Host smart-29d03f62-5519-4432-a250-e24e54725e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870254041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1870254041
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3562641665
Short name T590
Test name
Test status
Simulation time 47292914 ps
CPU time 1.3 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:48 PM PDT 24
Peak memory 218276 kb
Host smart-070c6c1a-0ce0-475c-901c-a3d403c3a7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562641665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3562641665
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.1219427678
Short name T685
Test name
Test status
Simulation time 73099297 ps
CPU time 1.05 seconds
Started Aug 06 07:44:44 PM PDT 24
Finished Aug 06 07:44:45 PM PDT 24
Peak memory 218180 kb
Host smart-12ced222-7906-49bd-95c9-d844254313c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219427678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1219427678
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.1262910870
Short name T22
Test name
Test status
Simulation time 79668185 ps
CPU time 1.33 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:48 PM PDT 24
Peak memory 218468 kb
Host smart-fa5d3a67-9fc1-4291-95bd-397baeea644f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262910870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1262910870
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.2165074024
Short name T159
Test name
Test status
Simulation time 30041767 ps
CPU time 1.23 seconds
Started Aug 06 07:44:43 PM PDT 24
Finished Aug 06 07:44:44 PM PDT 24
Peak memory 220152 kb
Host smart-ba63b81a-167a-45fc-9f92-ba6d80b69e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165074024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2165074024
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.613891471
Short name T308
Test name
Test status
Simulation time 353171573 ps
CPU time 1.56 seconds
Started Aug 06 07:44:42 PM PDT 24
Finished Aug 06 07:44:44 PM PDT 24
Peak memory 218232 kb
Host smart-b31e1746-63c8-4f1a-8543-0e21df224bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613891471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.613891471
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.227837216
Short name T820
Test name
Test status
Simulation time 79294218 ps
CPU time 1.13 seconds
Started Aug 06 07:44:44 PM PDT 24
Finished Aug 06 07:44:45 PM PDT 24
Peak memory 218680 kb
Host smart-f16bc887-f09f-4d5c-b89c-1b5af1ff0e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227837216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.227837216
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.954551169
Short name T891
Test name
Test status
Simulation time 21240204 ps
CPU time 0.97 seconds
Started Aug 06 07:41:35 PM PDT 24
Finished Aug 06 07:41:36 PM PDT 24
Peak memory 206356 kb
Host smart-195b9ac3-a83d-4717-8ae7-a410ce4faabb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954551169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.954551169
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.698107049
Short name T852
Test name
Test status
Simulation time 29202282 ps
CPU time 0.77 seconds
Started Aug 06 07:41:35 PM PDT 24
Finished Aug 06 07:41:35 PM PDT 24
Peak memory 215904 kb
Host smart-9e5381f9-ab15-42ec-88f6-e2785d66cfb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698107049 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.698107049
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2328490773
Short name T661
Test name
Test status
Simulation time 206005560 ps
CPU time 1.14 seconds
Started Aug 06 07:41:34 PM PDT 24
Finished Aug 06 07:41:35 PM PDT 24
Peak memory 218144 kb
Host smart-d553e4ef-bb3f-47a8-9f76-c3f9d430648b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328490773 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2328490773
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.713774494
Short name T675
Test name
Test status
Simulation time 150564734 ps
CPU time 2.17 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 07:41:36 PM PDT 24
Peak memory 219804 kb
Host smart-04aa2006-05ac-4194-8a04-37067de59b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713774494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.713774494
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.706099628
Short name T540
Test name
Test status
Simulation time 38499971 ps
CPU time 0.91 seconds
Started Aug 06 07:41:37 PM PDT 24
Finished Aug 06 07:41:37 PM PDT 24
Peak memory 215084 kb
Host smart-112e44d6-3678-4931-912a-e9843e50592a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706099628 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.706099628
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2113787379
Short name T548
Test name
Test status
Simulation time 66819812 ps
CPU time 0.84 seconds
Started Aug 06 07:41:32 PM PDT 24
Finished Aug 06 07:41:33 PM PDT 24
Peak memory 214792 kb
Host smart-729e60e8-6dec-47c6-bb90-09e18b09b758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113787379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2113787379
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.889622943
Short name T718
Test name
Test status
Simulation time 445182828 ps
CPU time 4.5 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 07:41:38 PM PDT 24
Peak memory 216780 kb
Host smart-715731e0-088b-418f-8a66-64c34aa2155d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889622943 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.889622943
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_alert.1329727652
Short name T287
Test name
Test status
Simulation time 115711407 ps
CPU time 1.1 seconds
Started Aug 06 07:44:47 PM PDT 24
Finished Aug 06 07:44:48 PM PDT 24
Peak memory 219116 kb
Host smart-c9c0579b-4ee9-4647-a80a-3bd8a6ce7d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329727652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1329727652
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.349620252
Short name T882
Test name
Test status
Simulation time 41364287 ps
CPU time 1.09 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:47 PM PDT 24
Peak memory 217132 kb
Host smart-f0a092b7-c2ec-487d-a45e-e6720a2911ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349620252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.349620252
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.74634892
Short name T744
Test name
Test status
Simulation time 84670937 ps
CPU time 1.06 seconds
Started Aug 06 07:44:47 PM PDT 24
Finished Aug 06 07:44:48 PM PDT 24
Peak memory 218708 kb
Host smart-07d5cdc7-ab61-4b1b-ba53-bb56faa2b1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74634892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.74634892
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.1136300273
Short name T398
Test name
Test status
Simulation time 37107939 ps
CPU time 1.36 seconds
Started Aug 06 07:44:47 PM PDT 24
Finished Aug 06 07:44:48 PM PDT 24
Peak memory 216816 kb
Host smart-1c0bfec9-8aee-4aa3-b438-a6cb006c1c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136300273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1136300273
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.3727199482
Short name T294
Test name
Test status
Simulation time 46486896 ps
CPU time 1.09 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:47 PM PDT 24
Peak memory 218236 kb
Host smart-f646b594-c8f9-425c-aa91-dc4beb94e48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727199482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3727199482
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3361309895
Short name T366
Test name
Test status
Simulation time 264985325 ps
CPU time 1.14 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 217096 kb
Host smart-5d247b39-6cfc-44bd-9198-1939022a10ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361309895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3361309895
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.2662379812
Short name T975
Test name
Test status
Simulation time 141080515 ps
CPU time 1.21 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 219516 kb
Host smart-dc45c4f2-0d9b-4cce-8337-f9b22d7916c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662379812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.2662379812
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3676059123
Short name T420
Test name
Test status
Simulation time 70390838 ps
CPU time 1.51 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:48 PM PDT 24
Peak memory 217032 kb
Host smart-9d47642a-0c45-4ad6-a977-d19edde5c418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676059123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3676059123
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.4039331442
Short name T289
Test name
Test status
Simulation time 26448399 ps
CPU time 1.25 seconds
Started Aug 06 07:44:44 PM PDT 24
Finished Aug 06 07:44:46 PM PDT 24
Peak memory 220184 kb
Host smart-60e14ed2-0129-40b6-84e3-891b4053f1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039331442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.4039331442
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.3551595514
Short name T953
Test name
Test status
Simulation time 74489371 ps
CPU time 1.04 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:48 PM PDT 24
Peak memory 217160 kb
Host smart-014e4cd3-758e-4232-902e-8028722c14f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551595514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3551595514
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.799017631
Short name T777
Test name
Test status
Simulation time 53060901 ps
CPU time 1.2 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 218176 kb
Host smart-5861cab0-d6b0-4c04-a1cb-72f3cb71e820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799017631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.799017631
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3197272211
Short name T967
Test name
Test status
Simulation time 28895221 ps
CPU time 1.2 seconds
Started Aug 06 07:44:48 PM PDT 24
Finished Aug 06 07:44:49 PM PDT 24
Peak memory 217004 kb
Host smart-d2b704d4-2e89-4372-8595-8b67f97fb3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197272211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3197272211
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.2233365196
Short name T986
Test name
Test status
Simulation time 24070549 ps
CPU time 1.25 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 219452 kb
Host smart-38135a1e-ea24-4169-8a6a-b98ecc68358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233365196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2233365196
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.2195095880
Short name T399
Test name
Test status
Simulation time 297226527 ps
CPU time 3.53 seconds
Started Aug 06 07:44:48 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 219668 kb
Host smart-a85eb00d-2415-4fa0-a66f-6d28bfd933e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195095880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2195095880
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1391245791
Short name T463
Test name
Test status
Simulation time 26419635 ps
CPU time 1.16 seconds
Started Aug 06 07:44:47 PM PDT 24
Finished Aug 06 07:44:48 PM PDT 24
Peak memory 218276 kb
Host smart-71243e4e-9737-4272-b2f5-955ffbd39bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391245791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1391245791
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3704576687
Short name T10
Test name
Test status
Simulation time 52204134 ps
CPU time 1.13 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 217276 kb
Host smart-cd191816-6b15-44b5-a42b-99d4bc408a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704576687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3704576687
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.378158727
Short name T171
Test name
Test status
Simulation time 76674328 ps
CPU time 1.13 seconds
Started Aug 06 07:41:35 PM PDT 24
Finished Aug 06 07:41:36 PM PDT 24
Peak memory 218556 kb
Host smart-f738accf-cb76-4ed8-9539-f8f9d666c046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378158727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.378158727
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2282591935
Short name T415
Test name
Test status
Simulation time 10637426 ps
CPU time 0.86 seconds
Started Aug 06 07:41:35 PM PDT 24
Finished Aug 06 07:41:36 PM PDT 24
Peak memory 206452 kb
Host smart-bf9e80f1-299c-40af-8030-b72929ccdce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282591935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2282591935
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2642402658
Short name T480
Test name
Test status
Simulation time 41418809 ps
CPU time 0.86 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 07:41:34 PM PDT 24
Peak memory 218856 kb
Host smart-6b71edba-45bc-4044-8492-94c1b3ca60d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642402658 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2642402658
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_genbits.4220704889
Short name T916
Test name
Test status
Simulation time 94949433 ps
CPU time 1.14 seconds
Started Aug 06 07:41:34 PM PDT 24
Finished Aug 06 07:41:35 PM PDT 24
Peak memory 216960 kb
Host smart-f2787053-50dc-4efc-b692-143fc260210a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220704889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.4220704889
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2080602147
Short name T426
Test name
Test status
Simulation time 22575948 ps
CPU time 1.07 seconds
Started Aug 06 07:41:35 PM PDT 24
Finished Aug 06 07:41:36 PM PDT 24
Peak memory 215004 kb
Host smart-267eec5f-1eb0-4400-8778-cb696d81eb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080602147 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2080602147
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.403892878
Short name T862
Test name
Test status
Simulation time 19781974 ps
CPU time 0.89 seconds
Started Aug 06 07:41:36 PM PDT 24
Finished Aug 06 07:41:37 PM PDT 24
Peak memory 214560 kb
Host smart-5d3df9a5-27a9-4faf-a3f7-b40a5c5f2f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403892878 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.403892878
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3881326610
Short name T617
Test name
Test status
Simulation time 127777300 ps
CPU time 1.85 seconds
Started Aug 06 07:41:36 PM PDT 24
Finished Aug 06 07:41:38 PM PDT 24
Peak memory 214820 kb
Host smart-cad4b0c4-d558-4c7b-aab6-d63c77699d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881326610 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3881326610
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1936184235
Short name T474
Test name
Test status
Simulation time 21095239228 ps
CPU time 488.51 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 07:49:42 PM PDT 24
Peak memory 220000 kb
Host smart-975084da-0b05-4f28-b20a-ae697c31d118
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936184235 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1936184235
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.2584761633
Short name T755
Test name
Test status
Simulation time 68748904 ps
CPU time 1.14 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 218736 kb
Host smart-5dc8aff5-ed6c-404e-932f-fb68f966350f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584761633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2584761633
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.2107987805
Short name T414
Test name
Test status
Simulation time 112261025 ps
CPU time 1.36 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 216984 kb
Host smart-d2572e18-e854-4e7b-9a23-a7ca4746ac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107987805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2107987805
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1775812981
Short name T92
Test name
Test status
Simulation time 57216239 ps
CPU time 1.26 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 219588 kb
Host smart-b61f9023-5c40-4ba0-b774-f8f686494734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775812981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1775812981
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.3452224332
Short name T377
Test name
Test status
Simulation time 193702427 ps
CPU time 1.53 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 218276 kb
Host smart-71dd97b1-ded1-4dc6-aa14-9a67129a8692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452224332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3452224332
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.2310506428
Short name T773
Test name
Test status
Simulation time 73927707 ps
CPU time 1.13 seconds
Started Aug 06 07:44:51 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 220352 kb
Host smart-9ba6e5ed-4427-4457-b2aa-2929c3d89bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310506428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2310506428
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.1496939226
Short name T489
Test name
Test status
Simulation time 24781335 ps
CPU time 0.93 seconds
Started Aug 06 07:44:49 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 218804 kb
Host smart-e5544e1b-d70e-4a8b-ab06-cc6caa12882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496939226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1496939226
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2172168294
Short name T856
Test name
Test status
Simulation time 52250810 ps
CPU time 1.23 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 218704 kb
Host smart-c08d5d08-3d69-40bb-bf72-246cffe783f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172168294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2172168294
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2041590186
Short name T335
Test name
Test status
Simulation time 83803728 ps
CPU time 1.38 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 216932 kb
Host smart-20ba0609-4dfc-4721-8791-1fd3e6bb71b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041590186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2041590186
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.4131856944
Short name T295
Test name
Test status
Simulation time 127555858 ps
CPU time 1.27 seconds
Started Aug 06 07:44:49 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 220124 kb
Host smart-4ffd1be4-d22d-4335-9a78-804165628542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131856944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.4131856944
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.1675252869
Short name T696
Test name
Test status
Simulation time 119449106 ps
CPU time 1.31 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 218364 kb
Host smart-7fe4aa19-7d22-42d3-82b9-3841ca123e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675252869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1675252869
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.1494070969
Short name T636
Test name
Test status
Simulation time 50122295 ps
CPU time 1.26 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 219496 kb
Host smart-b4615cb9-ea29-412b-9638-bb0bfbc007ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494070969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1494070969
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.491405598
Short name T914
Test name
Test status
Simulation time 94352298 ps
CPU time 1.27 seconds
Started Aug 06 07:44:43 PM PDT 24
Finished Aug 06 07:44:44 PM PDT 24
Peak memory 216872 kb
Host smart-88674509-e828-4d0d-b2b2-e82c1b1401c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491405598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.491405598
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.1833683578
Short name T490
Test name
Test status
Simulation time 27999401 ps
CPU time 1.22 seconds
Started Aug 06 07:44:48 PM PDT 24
Finished Aug 06 07:44:49 PM PDT 24
Peak memory 215292 kb
Host smart-9033764f-0089-4797-ae6a-eef983b380d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833683578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1833683578
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.1124819630
Short name T637
Test name
Test status
Simulation time 62216017 ps
CPU time 1.04 seconds
Started Aug 06 07:44:49 PM PDT 24
Finished Aug 06 07:44:50 PM PDT 24
Peak memory 217036 kb
Host smart-ad553a3c-1eee-41cd-8071-def4db09e7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124819630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1124819630
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.489100066
Short name T285
Test name
Test status
Simulation time 28976188 ps
CPU time 1.23 seconds
Started Aug 06 07:44:47 PM PDT 24
Finished Aug 06 07:44:48 PM PDT 24
Peak memory 219264 kb
Host smart-a9c2bad9-fed3-4bff-8e09-23f85a5e3619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489100066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.489100066
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.13505732
Short name T356
Test name
Test status
Simulation time 56882825 ps
CPU time 1.44 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 218428 kb
Host smart-07d1937a-8489-4dde-9f29-69d8759783d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13505732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.13505732
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3245187248
Short name T268
Test name
Test status
Simulation time 90203390 ps
CPU time 1.34 seconds
Started Aug 06 07:45:01 PM PDT 24
Finished Aug 06 07:45:03 PM PDT 24
Peak memory 218072 kb
Host smart-23983ba6-7455-40b3-8845-11c2f58d7944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245187248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3245187248
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.1777171309
Short name T780
Test name
Test status
Simulation time 240073298 ps
CPU time 3.41 seconds
Started Aug 06 07:44:49 PM PDT 24
Finished Aug 06 07:44:53 PM PDT 24
Peak memory 220064 kb
Host smart-13198b11-830c-4401-a913-25cef878e813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777171309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1777171309
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3273072370
Short name T198
Test name
Test status
Simulation time 48428033 ps
CPU time 1.12 seconds
Started Aug 06 07:45:01 PM PDT 24
Finished Aug 06 07:45:03 PM PDT 24
Peak memory 219800 kb
Host smart-bd30473a-f841-4c93-b30d-9109f6954153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273072370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3273072370
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.4112561426
Short name T808
Test name
Test status
Simulation time 117064435 ps
CPU time 1.14 seconds
Started Aug 06 07:45:00 PM PDT 24
Finished Aug 06 07:45:01 PM PDT 24
Peak memory 219476 kb
Host smart-d57e2e82-6354-43c0-89a5-738f36ff2be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112561426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.4112561426
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2898539428
Short name T385
Test name
Test status
Simulation time 292542220 ps
CPU time 1.27 seconds
Started Aug 06 07:41:34 PM PDT 24
Finished Aug 06 07:41:35 PM PDT 24
Peak memory 219668 kb
Host smart-48a9a36b-3a8e-48c7-aa92-76d6328d8116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898539428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2898539428
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1798194664
Short name T588
Test name
Test status
Simulation time 48209518 ps
CPU time 0.87 seconds
Started Aug 06 07:41:36 PM PDT 24
Finished Aug 06 07:41:37 PM PDT 24
Peak memory 214684 kb
Host smart-3483b138-9ebb-4d8f-8cd0-b833187ca0c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798194664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1798194664
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3962273247
Short name T582
Test name
Test status
Simulation time 77395241 ps
CPU time 0.82 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 07:41:34 PM PDT 24
Peak memory 215860 kb
Host smart-de4e64e6-f229-420a-ade1-f53e8af79ce0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962273247 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3962273247
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.3972978739
Short name T204
Test name
Test status
Simulation time 20743807 ps
CPU time 1.08 seconds
Started Aug 06 07:41:35 PM PDT 24
Finished Aug 06 07:41:37 PM PDT 24
Peak memory 219428 kb
Host smart-e0a03b50-2499-45bf-a46b-1c5ba48f5b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972978739 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3972978739
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3843121612
Short name T977
Test name
Test status
Simulation time 107221753 ps
CPU time 1.18 seconds
Started Aug 06 07:41:36 PM PDT 24
Finished Aug 06 07:41:37 PM PDT 24
Peak memory 216848 kb
Host smart-c57736d4-b1bd-4e11-bafd-ef70ea82ff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843121612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3843121612
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2170436800
Short name T889
Test name
Test status
Simulation time 39079709 ps
CPU time 0.94 seconds
Started Aug 06 07:41:34 PM PDT 24
Finished Aug 06 07:41:35 PM PDT 24
Peak memory 223704 kb
Host smart-4c7ef19a-510b-41ff-809a-a43ea31f4229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170436800 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2170436800
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2249703727
Short name T497
Test name
Test status
Simulation time 19060049 ps
CPU time 0.95 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 07:41:34 PM PDT 24
Peak memory 214920 kb
Host smart-5030dfd8-ec57-4acc-b4e6-3a2bf172368c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249703727 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2249703727
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.452293192
Short name T985
Test name
Test status
Simulation time 250550157 ps
CPU time 4.24 seconds
Started Aug 06 07:41:35 PM PDT 24
Finished Aug 06 07:41:39 PM PDT 24
Peak memory 216832 kb
Host smart-deab6190-7341-4bd4-930d-0f630df93ed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452293192 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.452293192
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2446388489
Short name T782
Test name
Test status
Simulation time 109985802290 ps
CPU time 1484.32 seconds
Started Aug 06 07:41:33 PM PDT 24
Finished Aug 06 08:06:18 PM PDT 24
Peak memory 226152 kb
Host smart-82ecdcaa-9990-47ae-b63b-111d2157b52d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446388489 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2446388489
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.1258000119
Short name T515
Test name
Test status
Simulation time 30007818 ps
CPU time 1.26 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 215236 kb
Host smart-a817621d-dfbf-46a3-b527-19be160e4ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258000119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.1258000119
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.4040871365
Short name T516
Test name
Test status
Simulation time 45477068 ps
CPU time 1.3 seconds
Started Aug 06 07:45:03 PM PDT 24
Finished Aug 06 07:45:04 PM PDT 24
Peak memory 218208 kb
Host smart-6afdbaff-11f0-46fc-9c56-252348c544ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040871365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.4040871365
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3769210237
Short name T243
Test name
Test status
Simulation time 70027510 ps
CPU time 1.12 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 219332 kb
Host smart-0563fbab-2d1f-4964-9fab-08e31807b569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769210237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3769210237
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.3537084009
Short name T419
Test name
Test status
Simulation time 51420251 ps
CPU time 1.13 seconds
Started Aug 06 07:45:01 PM PDT 24
Finished Aug 06 07:45:02 PM PDT 24
Peak memory 216912 kb
Host smart-ebba91d3-b05e-4066-a2d7-1e086dae3eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537084009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3537084009
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3666760266
Short name T752
Test name
Test status
Simulation time 52546033 ps
CPU time 1.22 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 215304 kb
Host smart-bc2321a1-07e2-46ea-971f-b754cb03c75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666760266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3666760266
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2762311120
Short name T48
Test name
Test status
Simulation time 72573577 ps
CPU time 1.26 seconds
Started Aug 06 07:45:06 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 218504 kb
Host smart-60791cf1-c56f-4e06-8a46-676775ccc0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762311120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2762311120
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.2159235317
Short name T503
Test name
Test status
Simulation time 179583720 ps
CPU time 1.19 seconds
Started Aug 06 07:45:01 PM PDT 24
Finished Aug 06 07:45:02 PM PDT 24
Peak memory 219020 kb
Host smart-639963f8-2710-4a21-ae37-798e8192ec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159235317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2159235317
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3989055749
Short name T900
Test name
Test status
Simulation time 53450662 ps
CPU time 1.25 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 216872 kb
Host smart-fc32a3d6-a76f-4af6-9668-f50e8dd1f8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989055749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3989055749
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1879284036
Short name T733
Test name
Test status
Simulation time 25607501 ps
CPU time 1.27 seconds
Started Aug 06 07:45:03 PM PDT 24
Finished Aug 06 07:45:04 PM PDT 24
Peak memory 220088 kb
Host smart-0996ba7e-0dda-4d3d-a3d9-7e5310e492ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879284036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1879284036
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.484210477
Short name T476
Test name
Test status
Simulation time 35437690 ps
CPU time 1.23 seconds
Started Aug 06 07:45:05 PM PDT 24
Finished Aug 06 07:45:06 PM PDT 24
Peak memory 218128 kb
Host smart-5b170657-ebb1-4dd0-8b5e-a9a8fdd99468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484210477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.484210477
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.3953196788
Short name T170
Test name
Test status
Simulation time 46966134 ps
CPU time 1.23 seconds
Started Aug 06 07:45:01 PM PDT 24
Finished Aug 06 07:45:02 PM PDT 24
Peak memory 220572 kb
Host smart-d3746419-8daa-4b89-bf41-be7bdf910805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953196788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3953196788
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1207344723
Short name T32
Test name
Test status
Simulation time 40268645 ps
CPU time 1.53 seconds
Started Aug 06 07:45:03 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 216952 kb
Host smart-cfba3476-36d7-40dd-b751-550e71efe042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207344723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1207344723
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2280900520
Short name T576
Test name
Test status
Simulation time 74958507 ps
CPU time 1.22 seconds
Started Aug 06 07:45:01 PM PDT 24
Finished Aug 06 07:45:03 PM PDT 24
Peak memory 218544 kb
Host smart-b8b89bcb-92a8-4c52-a805-bd5b057e8f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280900520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2280900520
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.3084894875
Short name T484
Test name
Test status
Simulation time 38696264 ps
CPU time 1.34 seconds
Started Aug 06 07:45:07 PM PDT 24
Finished Aug 06 07:45:08 PM PDT 24
Peak memory 216924 kb
Host smart-50a4a67b-7164-4413-8c90-3a519fc17e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084894875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3084894875
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.161991552
Short name T800
Test name
Test status
Simulation time 76461999 ps
CPU time 1.15 seconds
Started Aug 06 07:45:01 PM PDT 24
Finished Aug 06 07:45:03 PM PDT 24
Peak memory 219064 kb
Host smart-16906065-9324-4d9b-99c1-9716c7f26698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161991552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.161991552
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/138.edn_alert.3467522802
Short name T347
Test name
Test status
Simulation time 28143988 ps
CPU time 1.16 seconds
Started Aug 06 07:45:06 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 218212 kb
Host smart-b28d11fc-5fd6-404d-9841-2a938e35e0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467522802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3467522802
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1523877407
Short name T317
Test name
Test status
Simulation time 25119162 ps
CPU time 1.26 seconds
Started Aug 06 07:45:02 PM PDT 24
Finished Aug 06 07:45:04 PM PDT 24
Peak memory 218384 kb
Host smart-2d735125-fece-44e3-a1b4-8132db561b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523877407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1523877407
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.4100704394
Short name T905
Test name
Test status
Simulation time 75650771 ps
CPU time 1.12 seconds
Started Aug 06 07:45:06 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 221192 kb
Host smart-4f8bc588-1675-48b1-88ec-b981aeffe64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100704394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.4100704394
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.521237077
Short name T719
Test name
Test status
Simulation time 47319548 ps
CPU time 1.83 seconds
Started Aug 06 07:45:06 PM PDT 24
Finished Aug 06 07:45:08 PM PDT 24
Peak memory 217192 kb
Host smart-eefdd101-85d6-47b9-be80-3a3633cdfb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521237077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.521237077
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2854722381
Short name T648
Test name
Test status
Simulation time 45205830 ps
CPU time 1.19 seconds
Started Aug 06 07:42:16 PM PDT 24
Finished Aug 06 07:42:17 PM PDT 24
Peak memory 219752 kb
Host smart-8c090c52-c6c7-41c4-bd3a-d90bae932e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854722381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2854722381
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2640623944
Short name T519
Test name
Test status
Simulation time 202153621 ps
CPU time 1.13 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 206440 kb
Host smart-f62d0c71-6940-422c-ab4e-76d558951055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640623944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2640623944
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.292660899
Short name T124
Test name
Test status
Simulation time 47837458 ps
CPU time 0.84 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 216176 kb
Host smart-474a1778-086e-4186-898b-d53e344a4228
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292660899 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.292660899
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.2703810226
Short name T130
Test name
Test status
Simulation time 23079571 ps
CPU time 1.06 seconds
Started Aug 06 07:42:06 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 219800 kb
Host smart-7a8232d6-72bb-4621-9559-2b70f6394f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703810226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2703810226
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2231723752
Short name T943
Test name
Test status
Simulation time 105599166 ps
CPU time 1.18 seconds
Started Aug 06 07:41:35 PM PDT 24
Finished Aug 06 07:41:37 PM PDT 24
Peak memory 218732 kb
Host smart-3f600069-361a-48ed-aba4-c6c501fe6e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231723752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2231723752
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2392072880
Short name T402
Test name
Test status
Simulation time 21886292 ps
CPU time 1.15 seconds
Started Aug 06 07:42:12 PM PDT 24
Finished Aug 06 07:42:13 PM PDT 24
Peak memory 223684 kb
Host smart-ac4ec231-689b-4799-836a-f7f692929e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392072880 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2392072880
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2891208072
Short name T529
Test name
Test status
Simulation time 17896851 ps
CPU time 0.99 seconds
Started Aug 06 07:41:32 PM PDT 24
Finished Aug 06 07:41:33 PM PDT 24
Peak memory 214808 kb
Host smart-55dbb3a2-d939-408b-92a1-107b6d8f98e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891208072 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2891208072
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3989319640
Short name T607
Test name
Test status
Simulation time 502941881 ps
CPU time 5.14 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:42:13 PM PDT 24
Peak memory 214880 kb
Host smart-79452c07-f318-40ad-a6f6-b4db68efb55c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989319640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3989319640
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2315876064
Short name T487
Test name
Test status
Simulation time 26467903122 ps
CPU time 665.85 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:53:13 PM PDT 24
Peak memory 217772 kb
Host smart-7cb27853-aad8-4290-acdf-912262346387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315876064 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2315876064
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1309780290
Short name T290
Test name
Test status
Simulation time 25086680 ps
CPU time 1.12 seconds
Started Aug 06 07:45:06 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 219212 kb
Host smart-7b2535c5-3b46-4f50-824a-fbd901908a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309780290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1309780290
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.1193894944
Short name T923
Test name
Test status
Simulation time 85999203 ps
CPU time 1.39 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:06 PM PDT 24
Peak memory 218200 kb
Host smart-2b98e01e-b190-43f2-a760-1d7a5899c7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193894944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1193894944
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2781094850
Short name T924
Test name
Test status
Simulation time 21989995 ps
CPU time 1.17 seconds
Started Aug 06 07:45:03 PM PDT 24
Finished Aug 06 07:45:04 PM PDT 24
Peak memory 218260 kb
Host smart-2700f411-a426-4ae3-950e-544d0b7acda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781094850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2781094850
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1601509217
Short name T597
Test name
Test status
Simulation time 44600353 ps
CPU time 1.41 seconds
Started Aug 06 07:45:02 PM PDT 24
Finished Aug 06 07:45:03 PM PDT 24
Peak memory 218508 kb
Host smart-fc376ab8-26bd-433f-b5e6-38323b4bbd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601509217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1601509217
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3850955824
Short name T673
Test name
Test status
Simulation time 32731062 ps
CPU time 1.41 seconds
Started Aug 06 07:45:01 PM PDT 24
Finished Aug 06 07:45:03 PM PDT 24
Peak memory 215244 kb
Host smart-c6840858-4940-4f29-a2df-caff7d28a612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850955824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3850955824
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2401174424
Short name T393
Test name
Test status
Simulation time 71043529 ps
CPU time 1.35 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 218080 kb
Host smart-2a50a1a5-cd42-443a-aabe-8258a1991ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401174424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2401174424
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.3653131032
Short name T662
Test name
Test status
Simulation time 62745077 ps
CPU time 1.17 seconds
Started Aug 06 07:45:06 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 220564 kb
Host smart-4709245e-9850-4ca8-bcea-5fc3c09d0852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653131032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3653131032
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.2175937901
Short name T26
Test name
Test status
Simulation time 50051679 ps
CPU time 1.29 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:06 PM PDT 24
Peak memory 217944 kb
Host smart-36a27249-8bce-46c5-83bb-142413216204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175937901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2175937901
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.3864414730
Short name T456
Test name
Test status
Simulation time 22208695 ps
CPU time 1.17 seconds
Started Aug 06 07:45:02 PM PDT 24
Finished Aug 06 07:45:03 PM PDT 24
Peak memory 218336 kb
Host smart-284986cd-d7e5-4000-abd4-97b280634931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864414730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.3864414730
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.1654441344
Short name T438
Test name
Test status
Simulation time 156356923 ps
CPU time 1.08 seconds
Started Aug 06 07:45:02 PM PDT 24
Finished Aug 06 07:45:03 PM PDT 24
Peak memory 216932 kb
Host smart-a1708bc5-5ddb-40d2-b8cc-53af17a30f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654441344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1654441344
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2038522803
Short name T209
Test name
Test status
Simulation time 86240160 ps
CPU time 1.22 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 218160 kb
Host smart-f7861924-d6bf-452f-b2c5-dbed5337c33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038522803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2038522803
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.129899765
Short name T448
Test name
Test status
Simulation time 30951134 ps
CPU time 1.2 seconds
Started Aug 06 07:45:03 PM PDT 24
Finished Aug 06 07:45:04 PM PDT 24
Peak memory 217100 kb
Host smart-4f67c876-04c8-4c59-80c4-16f05a751be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129899765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.129899765
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.544645162
Short name T94
Test name
Test status
Simulation time 256188096 ps
CPU time 1.31 seconds
Started Aug 06 07:45:03 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 217964 kb
Host smart-c169f128-2024-4faf-a05d-a5478d91d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544645162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.544645162
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2593030738
Short name T352
Test name
Test status
Simulation time 111148955 ps
CPU time 1.65 seconds
Started Aug 06 07:45:03 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 218544 kb
Host smart-3c6b2b37-e479-4965-afc6-dbcab4849e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593030738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2593030738
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3623281839
Short name T585
Test name
Test status
Simulation time 106302768 ps
CPU time 1.3 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:06 PM PDT 24
Peak memory 216904 kb
Host smart-4c4c9886-e52c-490f-a065-9f6fa3858747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623281839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3623281839
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.276079098
Short name T942
Test name
Test status
Simulation time 36908646 ps
CPU time 1.1 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 219708 kb
Host smart-3a52b115-16e7-4b60-8be3-f6f47d8086c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276079098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.276079098
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.673704750
Short name T845
Test name
Test status
Simulation time 40385536 ps
CPU time 1.47 seconds
Started Aug 06 07:45:03 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 217876 kb
Host smart-567b8eab-8866-4acd-a0c9-c207d558b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673704750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.673704750
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1975633261
Short name T527
Test name
Test status
Simulation time 53794982 ps
CPU time 1.88 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:06 PM PDT 24
Peak memory 219580 kb
Host smart-b2633a7e-709b-4b93-b2d6-65d3b0cce778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975633261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1975633261
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.127315487
Short name T747
Test name
Test status
Simulation time 79646992 ps
CPU time 1.15 seconds
Started Aug 06 07:42:15 PM PDT 24
Finished Aug 06 07:42:16 PM PDT 24
Peak memory 218028 kb
Host smart-a0ea065e-a504-483c-b66e-b81b366df645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127315487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.127315487
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1589170440
Short name T656
Test name
Test status
Simulation time 18081985 ps
CPU time 0.91 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 206312 kb
Host smart-27e28c87-4ef1-453a-bf6c-ef8542ee9325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589170440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1589170440
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3863472788
Short name T860
Test name
Test status
Simulation time 45937558 ps
CPU time 0.84 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 215112 kb
Host smart-76bffe86-9da1-40e3-9cab-29c11332e909
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863472788 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3863472788
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.749595067
Short name T726
Test name
Test status
Simulation time 22733826 ps
CPU time 1.03 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 218220 kb
Host smart-c8b02006-fd49-4f33-93d9-51a703cdd099
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749595067 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.749595067
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3075220982
Short name T500
Test name
Test status
Simulation time 25030827 ps
CPU time 0.88 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 218300 kb
Host smart-a8fa0686-53f9-4e03-809c-73455eb0901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075220982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3075220982
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3289610231
Short name T737
Test name
Test status
Simulation time 190694267 ps
CPU time 2.93 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:42:10 PM PDT 24
Peak memory 217404 kb
Host smart-61f6701e-3374-436c-972c-1b31a4693e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289610231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3289610231
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.612457393
Short name T330
Test name
Test status
Simulation time 100121608 ps
CPU time 0.92 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 214844 kb
Host smart-750b16c7-a873-48f0-9fe7-9be66e12deb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612457393 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.612457393
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.4136223635
Short name T234
Test name
Test status
Simulation time 264500274 ps
CPU time 3.04 seconds
Started Aug 06 07:42:09 PM PDT 24
Finished Aug 06 07:42:13 PM PDT 24
Peak memory 216936 kb
Host smart-501076f9-a9d5-4385-bf70-8bc666ea1052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136223635 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.4136223635
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2223753790
Short name T570
Test name
Test status
Simulation time 20531982002 ps
CPU time 528.86 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:50:56 PM PDT 24
Peak memory 218072 kb
Host smart-cb69bcf6-32ce-4b56-a934-45086fcd989d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223753790 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2223753790
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.841303852
Short name T701
Test name
Test status
Simulation time 94668861 ps
CPU time 1.06 seconds
Started Aug 06 07:45:03 PM PDT 24
Finished Aug 06 07:45:04 PM PDT 24
Peak memory 217976 kb
Host smart-85040787-6b39-43f8-96e4-7a60a7f51515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841303852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.841303852
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.1466892248
Short name T70
Test name
Test status
Simulation time 57780779 ps
CPU time 1.53 seconds
Started Aug 06 07:45:02 PM PDT 24
Finished Aug 06 07:45:04 PM PDT 24
Peak memory 218584 kb
Host smart-04aa7238-9e82-47df-bfee-5d9e7816cb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466892248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1466892248
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.2736407791
Short name T143
Test name
Test status
Simulation time 104053293 ps
CPU time 1.27 seconds
Started Aug 06 07:45:02 PM PDT 24
Finished Aug 06 07:45:03 PM PDT 24
Peak memory 215292 kb
Host smart-a7021adb-39a9-4800-8eda-7d674592d542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736407791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.2736407791
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.475069236
Short name T332
Test name
Test status
Simulation time 62269174 ps
CPU time 1.09 seconds
Started Aug 06 07:45:06 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 218560 kb
Host smart-31093625-3ede-4139-8936-b50be6e0e0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475069236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.475069236
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.2167080507
Short name T369
Test name
Test status
Simulation time 44260991 ps
CPU time 1.21 seconds
Started Aug 06 07:45:06 PM PDT 24
Finished Aug 06 07:45:08 PM PDT 24
Peak memory 219472 kb
Host smart-920b181e-d5a1-43c3-bc4d-13e90961bcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167080507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2167080507
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.107265227
Short name T555
Test name
Test status
Simulation time 48351134 ps
CPU time 1.53 seconds
Started Aug 06 07:45:08 PM PDT 24
Finished Aug 06 07:45:10 PM PDT 24
Peak memory 218032 kb
Host smart-c698e378-e2d9-467e-b168-1f44873a2f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107265227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.107265227
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2088421511
Short name T732
Test name
Test status
Simulation time 41952283 ps
CPU time 1.13 seconds
Started Aug 06 07:45:05 PM PDT 24
Finished Aug 06 07:45:06 PM PDT 24
Peak memory 218236 kb
Host smart-7d44513c-5df7-4d15-8244-5d530c2315ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088421511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2088421511
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3500009082
Short name T460
Test name
Test status
Simulation time 100778246 ps
CPU time 1.16 seconds
Started Aug 06 07:45:03 PM PDT 24
Finished Aug 06 07:45:04 PM PDT 24
Peak memory 216948 kb
Host smart-81fafdf8-a304-4f29-951a-be1b58531f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500009082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3500009082
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1325904989
Short name T518
Test name
Test status
Simulation time 39360811 ps
CPU time 1.25 seconds
Started Aug 06 07:45:03 PM PDT 24
Finished Aug 06 07:45:04 PM PDT 24
Peak memory 219000 kb
Host smart-10fb7eae-087c-4cae-a4f6-c22abd621c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325904989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1325904989
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.3277525794
Short name T485
Test name
Test status
Simulation time 44797996 ps
CPU time 1.18 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 217288 kb
Host smart-bb94c422-b630-460e-b04c-e055d7784ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277525794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3277525794
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.1620401444
Short name T177
Test name
Test status
Simulation time 44828296 ps
CPU time 1.11 seconds
Started Aug 06 07:45:00 PM PDT 24
Finished Aug 06 07:45:01 PM PDT 24
Peak memory 218156 kb
Host smart-e2085f3b-3690-490d-9b62-5d03119bbf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620401444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.1620401444
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3768446872
Short name T357
Test name
Test status
Simulation time 62619812 ps
CPU time 1.37 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:06 PM PDT 24
Peak memory 219516 kb
Host smart-9b944091-44cd-42d1-a6e8-bcab35c6ab08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768446872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3768446872
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1151690932
Short name T642
Test name
Test status
Simulation time 95309894 ps
CPU time 1.18 seconds
Started Aug 06 07:45:02 PM PDT 24
Finished Aug 06 07:45:03 PM PDT 24
Peak memory 220112 kb
Host smart-46e4111f-33f1-4231-9d00-8ffda6430205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151690932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1151690932
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.1777993487
Short name T475
Test name
Test status
Simulation time 44828018 ps
CPU time 1.62 seconds
Started Aug 06 07:45:06 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 218532 kb
Host smart-2028be33-f93b-4905-9339-9a3c2f76c3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777993487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1777993487
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3102668448
Short name T817
Test name
Test status
Simulation time 80222788 ps
CPU time 1.18 seconds
Started Aug 06 07:45:02 PM PDT 24
Finished Aug 06 07:45:03 PM PDT 24
Peak memory 220228 kb
Host smart-39ec0ad0-c019-4617-915c-3aad8bf02719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102668448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3102668448
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.1239810565
Short name T769
Test name
Test status
Simulation time 36346113 ps
CPU time 1.54 seconds
Started Aug 06 07:45:05 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 218132 kb
Host smart-4f982b8b-438b-4b5b-9955-092c2ed247c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239810565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1239810565
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1748131545
Short name T683
Test name
Test status
Simulation time 105608723 ps
CPU time 1.07 seconds
Started Aug 06 07:45:06 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 219480 kb
Host smart-dc8e1c76-38a5-47df-a9c8-ba4ccc036043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748131545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1748131545
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.38283661
Short name T831
Test name
Test status
Simulation time 96954706 ps
CPU time 1.1 seconds
Started Aug 06 07:45:05 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 214884 kb
Host smart-5e30cd6d-d9c6-4a21-9112-6f2173a4b2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38283661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.38283661
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.2934907700
Short name T293
Test name
Test status
Simulation time 345337054 ps
CPU time 1.32 seconds
Started Aug 06 07:45:03 PM PDT 24
Finished Aug 06 07:45:04 PM PDT 24
Peak memory 218040 kb
Host smart-4be22b4e-0a4f-4624-8ed6-a513826626ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934907700 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2934907700
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.354706724
Short name T707
Test name
Test status
Simulation time 43436491 ps
CPU time 1.39 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 217996 kb
Host smart-5066cc11-64f6-4cd2-a487-48bade0ec38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354706724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.354706724
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.4292715090
Short name T941
Test name
Test status
Simulation time 23680138 ps
CPU time 1.18 seconds
Started Aug 06 07:42:06 PM PDT 24
Finished Aug 06 07:42:07 PM PDT 24
Peak memory 218380 kb
Host smart-0d7dd742-c834-4675-82e6-69415485f34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292715090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.4292715090
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2236784197
Short name T151
Test name
Test status
Simulation time 23520325 ps
CPU time 1.04 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 218124 kb
Host smart-e6533b00-1865-4012-9961-5157ca518504
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236784197 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2236784197
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.746949506
Short name T43
Test name
Test status
Simulation time 66242496 ps
CPU time 0.97 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 229288 kb
Host smart-b57a72df-26dd-46b3-876a-854c345133f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746949506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.746949506
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2562134879
Short name T927
Test name
Test status
Simulation time 27058435 ps
CPU time 1.19 seconds
Started Aug 06 07:42:06 PM PDT 24
Finished Aug 06 07:42:07 PM PDT 24
Peak memory 219716 kb
Host smart-f842daca-da64-459a-a543-ac39102a4a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562134879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2562134879
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3087143828
Short name T571
Test name
Test status
Simulation time 39118990 ps
CPU time 1.02 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 223748 kb
Host smart-ebe06539-8e14-4a4e-b857-9a9794d48727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087143828 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3087143828
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2978037748
Short name T650
Test name
Test status
Simulation time 20491588 ps
CPU time 0.94 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 215000 kb
Host smart-a1176a60-e6d2-4725-9ddd-45c567513c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978037748 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2978037748
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.893379998
Short name T790
Test name
Test status
Simulation time 293964146 ps
CPU time 6.23 seconds
Started Aug 06 07:42:06 PM PDT 24
Finished Aug 06 07:42:13 PM PDT 24
Peak memory 218124 kb
Host smart-5c7715ed-3cbf-44bc-88b3-a520e2f4be1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893379998 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.893379998
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_alert.1191431068
Short name T844
Test name
Test status
Simulation time 31667016 ps
CPU time 1.19 seconds
Started Aug 06 07:45:06 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 220028 kb
Host smart-05ad470d-d071-4aef-ae68-0b56cf572da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191431068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.1191431068
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3506245408
Short name T62
Test name
Test status
Simulation time 31731806 ps
CPU time 1.32 seconds
Started Aug 06 07:45:07 PM PDT 24
Finished Aug 06 07:45:08 PM PDT 24
Peak memory 216976 kb
Host smart-1412c6ac-293f-44a1-afb8-41db35572564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506245408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3506245408
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2550239590
Short name T64
Test name
Test status
Simulation time 22973195 ps
CPU time 1.07 seconds
Started Aug 06 07:45:05 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 218008 kb
Host smart-e49074ae-f0aa-405a-8d0d-32bd797a6e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550239590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2550239590
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.3815302786
Short name T731
Test name
Test status
Simulation time 42155782 ps
CPU time 1.34 seconds
Started Aug 06 07:45:08 PM PDT 24
Finished Aug 06 07:45:09 PM PDT 24
Peak memory 217960 kb
Host smart-beb149d7-9cbe-44de-a568-7e7d660d7f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815302786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3815302786
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.3763170860
Short name T902
Test name
Test status
Simulation time 23333190 ps
CPU time 1.16 seconds
Started Aug 06 07:45:08 PM PDT 24
Finished Aug 06 07:45:09 PM PDT 24
Peak memory 218264 kb
Host smart-823b9297-971f-41a8-b0db-5f19b689c5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763170860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.3763170860
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3236096110
Short name T237
Test name
Test status
Simulation time 91159035 ps
CPU time 1.21 seconds
Started Aug 06 07:45:05 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 216904 kb
Host smart-17d5404c-8887-4a82-9e13-c6a77f861ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236096110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3236096110
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1831100262
Short name T598
Test name
Test status
Simulation time 26189630 ps
CPU time 1.22 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 220316 kb
Host smart-a9848827-f73f-46b6-bca4-d1978b940798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831100262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1831100262
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1060590323
Short name T569
Test name
Test status
Simulation time 70874866 ps
CPU time 1.1 seconds
Started Aug 06 07:45:08 PM PDT 24
Finished Aug 06 07:45:09 PM PDT 24
Peak memory 216744 kb
Host smart-9af9bf79-82e7-4668-b95a-7414c624b213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060590323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1060590323
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.3905180181
Short name T635
Test name
Test status
Simulation time 27499660 ps
CPU time 1.25 seconds
Started Aug 06 07:45:04 PM PDT 24
Finished Aug 06 07:45:05 PM PDT 24
Peak memory 218436 kb
Host smart-ac7fb775-87ef-4162-ae12-1d2f12b3a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905180181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3905180181
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1505376716
Short name T971
Test name
Test status
Simulation time 52540363 ps
CPU time 1.85 seconds
Started Aug 06 07:45:05 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 218292 kb
Host smart-bb32d766-e23b-46ab-8c85-21b4aa323084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505376716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1505376716
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.1704122985
Short name T947
Test name
Test status
Simulation time 124009927 ps
CPU time 1.3 seconds
Started Aug 06 07:45:26 PM PDT 24
Finished Aug 06 07:45:28 PM PDT 24
Peak memory 220132 kb
Host smart-8c1719ed-10c0-4514-8ddf-247fad4791be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704122985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.1704122985
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2859623626
Short name T451
Test name
Test status
Simulation time 34240355 ps
CPU time 1.27 seconds
Started Aug 06 07:45:23 PM PDT 24
Finished Aug 06 07:45:24 PM PDT 24
Peak memory 216884 kb
Host smart-e4bfde5b-ea00-4474-ac99-1344b6345193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859623626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2859623626
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.2701532746
Short name T892
Test name
Test status
Simulation time 27530663 ps
CPU time 1.22 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 218292 kb
Host smart-35a001ba-ee5e-4f2e-9a9a-00d35fbc4175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701532746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2701532746
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.1451175856
Short name T323
Test name
Test status
Simulation time 53497997 ps
CPU time 1.84 seconds
Started Aug 06 07:45:20 PM PDT 24
Finished Aug 06 07:45:22 PM PDT 24
Peak memory 219704 kb
Host smart-91bbcef2-cb33-4e80-a32b-3d1e911c3e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451175856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1451175856
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1014015983
Short name T66
Test name
Test status
Simulation time 37979520 ps
CPU time 1.17 seconds
Started Aug 06 07:45:29 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 218228 kb
Host smart-e82aa652-0b06-4c97-b9d3-7c873f05031a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014015983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1014015983
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.967779152
Short name T430
Test name
Test status
Simulation time 42022060 ps
CPU time 1.67 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 219284 kb
Host smart-75a2ef57-7bc7-4a1f-a9aa-d12b445dfff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967779152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.967779152
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.4188145999
Short name T239
Test name
Test status
Simulation time 60740243 ps
CPU time 1.09 seconds
Started Aug 06 07:45:26 PM PDT 24
Finished Aug 06 07:45:27 PM PDT 24
Peak memory 220364 kb
Host smart-3d5bd07c-de12-4df4-9f24-f2a481fd179d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188145999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.4188145999
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1862891054
Short name T841
Test name
Test status
Simulation time 50208888 ps
CPU time 1.38 seconds
Started Aug 06 07:45:19 PM PDT 24
Finished Aug 06 07:45:20 PM PDT 24
Peak memory 218272 kb
Host smart-c1cb708a-6438-45e9-b678-054726b4e97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862891054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1862891054
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1370545716
Short name T397
Test name
Test status
Simulation time 41317055 ps
CPU time 1.18 seconds
Started Aug 06 07:45:22 PM PDT 24
Finished Aug 06 07:45:23 PM PDT 24
Peak memory 219796 kb
Host smart-b08a1eb9-fd28-4a20-9d00-ed354793c7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370545716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1370545716
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.2936096806
Short name T87
Test name
Test status
Simulation time 56811672 ps
CPU time 1.23 seconds
Started Aug 06 07:45:26 PM PDT 24
Finished Aug 06 07:45:28 PM PDT 24
Peak memory 218556 kb
Host smart-bbeb2894-957a-4b85-a041-e9e03fdaabe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936096806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2936096806
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2639534315
Short name T440
Test name
Test status
Simulation time 138010928 ps
CPU time 1.28 seconds
Started Aug 06 07:42:09 PM PDT 24
Finished Aug 06 07:42:10 PM PDT 24
Peak memory 215220 kb
Host smart-ebd6fa17-2e99-45c1-8d77-42c0f6abb707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639534315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2639534315
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1231157188
Short name T825
Test name
Test status
Simulation time 49088556 ps
CPU time 0.9 seconds
Started Aug 06 07:42:06 PM PDT 24
Finished Aug 06 07:42:07 PM PDT 24
Peak memory 206368 kb
Host smart-23e76eb3-29d7-4b42-8257-ce6b62fbc520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231157188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1231157188
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2690352515
Short name T98
Test name
Test status
Simulation time 64451428 ps
CPU time 0.98 seconds
Started Aug 06 07:42:09 PM PDT 24
Finished Aug 06 07:42:10 PM PDT 24
Peak memory 219208 kb
Host smart-69d61f72-a044-4e4e-8167-779d633280ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690352515 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2690352515
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3668789358
Short name T125
Test name
Test status
Simulation time 33246233 ps
CPU time 1.06 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 220784 kb
Host smart-81464506-bf0c-41f1-90b0-8685cb58123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668789358 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3668789358
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.1243803351
Short name T710
Test name
Test status
Simulation time 31314555 ps
CPU time 0.85 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 214880 kb
Host smart-1c1393b9-8a3e-44b6-9c3d-acb42647b6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243803351 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1243803351
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3723101007
Short name T714
Test name
Test status
Simulation time 15969381 ps
CPU time 0.98 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 214852 kb
Host smart-04c9bd8f-90ad-47a3-9d64-66e6c3e13817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723101007 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3723101007
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2444512043
Short name T403
Test name
Test status
Simulation time 668319953 ps
CPU time 2.99 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:42:10 PM PDT 24
Peak memory 219520 kb
Host smart-b1e0f3fd-d212-48bf-8275-db1685676712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444512043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2444512043
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2018843219
Short name T5
Test name
Test status
Simulation time 24506268258 ps
CPU time 493.43 seconds
Started Aug 06 07:42:06 PM PDT 24
Finished Aug 06 07:50:20 PM PDT 24
Peak memory 223340 kb
Host smart-c72df850-7ac2-4fcc-b182-fce91f00ace8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018843219 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2018843219
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2139067731
Short name T595
Test name
Test status
Simulation time 48108337 ps
CPU time 1.14 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 218140 kb
Host smart-d1c20a3f-cfa6-4547-a937-91ac1cf3851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139067731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2139067731
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.4253016791
Short name T152
Test name
Test status
Simulation time 114956549 ps
CPU time 1.13 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 218284 kb
Host smart-69f454a5-5d14-4720-bd20-fa3ee46f654a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253016791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.4253016791
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.4026877311
Short name T541
Test name
Test status
Simulation time 42245186 ps
CPU time 1.36 seconds
Started Aug 06 07:45:22 PM PDT 24
Finished Aug 06 07:45:23 PM PDT 24
Peak memory 217172 kb
Host smart-f46498d2-6498-438f-a82e-2a7108c1f089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026877311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4026877311
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.810737961
Short name T751
Test name
Test status
Simulation time 26948374 ps
CPU time 1.24 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 218240 kb
Host smart-201ae059-9a4f-4346-973e-3bda156e6fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810737961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.810737961
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/173.edn_alert.3448939552
Short name T35
Test name
Test status
Simulation time 23471114 ps
CPU time 1.15 seconds
Started Aug 06 07:45:29 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 217996 kb
Host smart-fb7353e0-1e77-46dc-8b17-5e640406d82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448939552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3448939552
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.2002224592
Short name T765
Test name
Test status
Simulation time 44376662 ps
CPU time 1.07 seconds
Started Aug 06 07:45:25 PM PDT 24
Finished Aug 06 07:45:26 PM PDT 24
Peak memory 216916 kb
Host smart-1532f04c-0657-4cb5-b195-c4518963dec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002224592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2002224592
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.1520096918
Short name T201
Test name
Test status
Simulation time 22413556 ps
CPU time 1.15 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 218612 kb
Host smart-99057701-f418-4322-97cb-46aaabea0b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520096918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1520096918
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3079835321
Short name T827
Test name
Test status
Simulation time 59819847 ps
CPU time 1.42 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 216888 kb
Host smart-88b8c426-6803-461b-98c6-dd9545bfe219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079835321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3079835321
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3512075400
Short name T960
Test name
Test status
Simulation time 68024072 ps
CPU time 1.02 seconds
Started Aug 06 07:45:20 PM PDT 24
Finished Aug 06 07:45:21 PM PDT 24
Peak memory 218264 kb
Host smart-8502b630-bdc7-4896-9325-633ccbb22737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512075400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3512075400
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.1490666354
Short name T433
Test name
Test status
Simulation time 71547798 ps
CPU time 1.16 seconds
Started Aug 06 07:45:20 PM PDT 24
Finished Aug 06 07:45:21 PM PDT 24
Peak memory 218680 kb
Host smart-1c7d8cae-6e7d-45c4-9fe5-421bb330e2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490666354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1490666354
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1166075615
Short name T284
Test name
Test status
Simulation time 97545645 ps
CPU time 1.2 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 219452 kb
Host smart-6787407b-2610-43b3-ab56-e431dd102f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166075615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1166075615
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.4120534226
Short name T8
Test name
Test status
Simulation time 40458431 ps
CPU time 1.43 seconds
Started Aug 06 07:45:26 PM PDT 24
Finished Aug 06 07:45:28 PM PDT 24
Peak memory 214976 kb
Host smart-979b9b95-c197-47c8-af04-87708e81eb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120534226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.4120534226
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.101683644
Short name T712
Test name
Test status
Simulation time 33142884 ps
CPU time 1.27 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 219368 kb
Host smart-e801f64b-239e-4d5d-bf59-81ad138c74da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101683644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.101683644
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.3794100515
Short name T9
Test name
Test status
Simulation time 42369150 ps
CPU time 1.15 seconds
Started Aug 06 07:45:22 PM PDT 24
Finished Aug 06 07:45:23 PM PDT 24
Peak memory 217028 kb
Host smart-4fb907a8-11a8-4b73-afa6-8c0130a3c572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794100515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3794100515
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.1742023493
Short name T135
Test name
Test status
Simulation time 86997023 ps
CPU time 1.23 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 218132 kb
Host smart-78118ab4-984b-4006-a5f8-b1db2e06f6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742023493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1742023493
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3435065395
Short name T678
Test name
Test status
Simulation time 46309185 ps
CPU time 1.44 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 218192 kb
Host smart-b5b0e952-e103-4353-adb7-d8dea19d9448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435065395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3435065395
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2869381910
Short name T669
Test name
Test status
Simulation time 36793541 ps
CPU time 1.04 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 218224 kb
Host smart-820f8289-c81e-40a3-97d1-5c8722bcd4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869381910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2869381910
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2156152271
Short name T665
Test name
Test status
Simulation time 71433492 ps
CPU time 1.31 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 217092 kb
Host smart-db13c9d6-52cf-4b2e-b631-dcf7442f5f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156152271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2156152271
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1475598823
Short name T65
Test name
Test status
Simulation time 29135931 ps
CPU time 1.25 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 218232 kb
Host smart-5ffca7f3-96af-4ae0-b5eb-f79f74911267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475598823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1475598823
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1142269631
Short name T50
Test name
Test status
Simulation time 14939174 ps
CPU time 0.88 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:09 PM PDT 24
Peak memory 206532 kb
Host smart-0e5eada0-1b9b-4062-aad4-b6a9c4932e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142269631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1142269631
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1538780342
Short name T620
Test name
Test status
Simulation time 15958238 ps
CPU time 0.92 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 216292 kb
Host smart-e4ed15cb-8767-473d-9d12-4a006e6ff3a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538780342 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1538780342
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.101954906
Short name T763
Test name
Test status
Simulation time 54133380 ps
CPU time 1.13 seconds
Started Aug 06 07:42:10 PM PDT 24
Finished Aug 06 07:42:11 PM PDT 24
Peak memory 216812 kb
Host smart-20b43668-e43c-40f8-8782-38c4a1019bde
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101954906 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.101954906
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.176236420
Short name T410
Test name
Test status
Simulation time 18471445 ps
CPU time 1.14 seconds
Started Aug 06 07:42:09 PM PDT 24
Finished Aug 06 07:42:10 PM PDT 24
Peak memory 223608 kb
Host smart-8a1e59be-db21-4bb3-a38e-3060af2dddd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176236420 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.176236420
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.698747551
Short name T865
Test name
Test status
Simulation time 245071079 ps
CPU time 1.07 seconds
Started Aug 06 07:42:07 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 214872 kb
Host smart-5845a1b0-909c-45c2-8b0a-758fdb910874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698747551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.698747551
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1786749142
Short name T839
Test name
Test status
Simulation time 55622645 ps
CPU time 0.93 seconds
Started Aug 06 07:42:06 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 214900 kb
Host smart-8222438c-f15a-4776-bf22-9434ba49d5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786749142 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1786749142
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.312162364
Short name T232
Test name
Test status
Simulation time 29521357 ps
CPU time 0.9 seconds
Started Aug 06 07:42:06 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 206632 kb
Host smart-e60ff247-0541-49d5-b742-4c2ea1723590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312162364 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.312162364
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2655047419
Short name T895
Test name
Test status
Simulation time 103484884 ps
CPU time 1.52 seconds
Started Aug 06 07:42:14 PM PDT 24
Finished Aug 06 07:42:16 PM PDT 24
Peak memory 216920 kb
Host smart-032b6da2-d2f5-4dff-8879-57e57fe3bab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655047419 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2655047419
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3332261631
Short name T988
Test name
Test status
Simulation time 115322752756 ps
CPU time 546.09 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:51:15 PM PDT 24
Peak memory 219908 kb
Host smart-580fbbcc-3497-4e95-b610-44129bbb01d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332261631 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3332261631
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1537280256
Short name T904
Test name
Test status
Simulation time 254864666 ps
CPU time 1.24 seconds
Started Aug 06 07:45:29 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 218192 kb
Host smart-b19841f9-178e-44c9-8e5f-20430ea720d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537280256 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1537280256
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2567796476
Short name T494
Test name
Test status
Simulation time 72291834 ps
CPU time 1.32 seconds
Started Aug 06 07:45:21 PM PDT 24
Finished Aug 06 07:45:23 PM PDT 24
Peak memory 218524 kb
Host smart-65117bf6-928a-4917-a145-9d6e7c8c6266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567796476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2567796476
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.747818179
Short name T534
Test name
Test status
Simulation time 37101085 ps
CPU time 1.16 seconds
Started Aug 06 07:45:19 PM PDT 24
Finished Aug 06 07:45:20 PM PDT 24
Peak memory 215236 kb
Host smart-113a5b88-bd90-4e0d-a60c-7607c3b88fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747818179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.747818179
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3115561049
Short name T944
Test name
Test status
Simulation time 186377778 ps
CPU time 3.4 seconds
Started Aug 06 07:45:23 PM PDT 24
Finished Aug 06 07:45:27 PM PDT 24
Peak memory 219944 kb
Host smart-95870d52-1148-47dc-b01b-e2cbcca85c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115561049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3115561049
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.1534071870
Short name T153
Test name
Test status
Simulation time 28455789 ps
CPU time 1.32 seconds
Started Aug 06 07:45:29 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 220236 kb
Host smart-6b62aaef-7f11-43d1-887a-26005fe2a590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534071870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.1534071870
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/183.edn_alert.3011093970
Short name T199
Test name
Test status
Simulation time 93837426 ps
CPU time 1.22 seconds
Started Aug 06 07:45:21 PM PDT 24
Finished Aug 06 07:45:22 PM PDT 24
Peak memory 218616 kb
Host smart-6b867e7c-266d-4527-bbde-e1192b73c70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011093970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.3011093970
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.3188971233
Short name T326
Test name
Test status
Simulation time 91741437 ps
CPU time 2.03 seconds
Started Aug 06 07:45:29 PM PDT 24
Finished Aug 06 07:45:32 PM PDT 24
Peak memory 218116 kb
Host smart-b42f3ef5-b1d1-4ec1-98c1-05903a0fd132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188971233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3188971233
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.234789795
Short name T727
Test name
Test status
Simulation time 29046277 ps
CPU time 1.28 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 219324 kb
Host smart-3c425f06-6dd6-4587-89b7-57a0c935ae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234789795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.234789795
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.3585737891
Short name T454
Test name
Test status
Simulation time 36146151 ps
CPU time 1.28 seconds
Started Aug 06 07:45:19 PM PDT 24
Finished Aug 06 07:45:21 PM PDT 24
Peak memory 218172 kb
Host smart-a68e611a-1503-4aeb-9a10-2e25e64c8176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585737891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3585737891
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.4271128344
Short name T837
Test name
Test status
Simulation time 105575435 ps
CPU time 1.22 seconds
Started Aug 06 07:45:27 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 219844 kb
Host smart-9c38c681-cbdf-43b1-9bfe-e29a3f2b95a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271128344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.4271128344
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2040286098
Short name T409
Test name
Test status
Simulation time 37687587 ps
CPU time 1.31 seconds
Started Aug 06 07:45:20 PM PDT 24
Finished Aug 06 07:45:21 PM PDT 24
Peak memory 217056 kb
Host smart-4baf983a-3128-4f72-b6e8-d6140b3c9881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040286098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2040286098
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.465076315
Short name T12
Test name
Test status
Simulation time 52844087 ps
CPU time 1.24 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 215240 kb
Host smart-731ac8d6-99a6-47ed-a0aa-72a77fd22ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465076315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.465076315
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.1224389939
Short name T627
Test name
Test status
Simulation time 49396554 ps
CPU time 1.29 seconds
Started Aug 06 07:45:25 PM PDT 24
Finished Aug 06 07:45:26 PM PDT 24
Peak memory 217992 kb
Host smart-89b7799d-d68a-4474-8db8-24e223e0ab51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224389939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1224389939
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.2153516843
Short name T353
Test name
Test status
Simulation time 26058513 ps
CPU time 1.22 seconds
Started Aug 06 07:45:21 PM PDT 24
Finished Aug 06 07:45:23 PM PDT 24
Peak memory 219312 kb
Host smart-15274eaa-1f9a-4c6d-98ff-1518ce06a946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153516843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2153516843
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.2672547454
Short name T491
Test name
Test status
Simulation time 46150795 ps
CPU time 1.86 seconds
Started Aug 06 07:45:29 PM PDT 24
Finished Aug 06 07:45:31 PM PDT 24
Peak memory 218032 kb
Host smart-4c05b47e-946c-475a-a9c5-7cef83b280f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672547454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2672547454
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.1980080455
Short name T458
Test name
Test status
Simulation time 39958518 ps
CPU time 1.27 seconds
Started Aug 06 07:45:21 PM PDT 24
Finished Aug 06 07:45:22 PM PDT 24
Peak memory 215392 kb
Host smart-e7ce12f1-7615-46c3-a849-c4348445ce61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980080455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1980080455
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.1926362634
Short name T339
Test name
Test status
Simulation time 40427286 ps
CPU time 1.67 seconds
Started Aug 06 07:45:24 PM PDT 24
Finished Aug 06 07:45:26 PM PDT 24
Peak memory 218060 kb
Host smart-f2e57c28-dbef-462b-a0bc-57fc17f5f405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926362634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1926362634
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.791829243
Short name T434
Test name
Test status
Simulation time 40558558 ps
CPU time 1.11 seconds
Started Aug 06 07:45:18 PM PDT 24
Finished Aug 06 07:45:19 PM PDT 24
Peak memory 218216 kb
Host smart-b8ff27e4-2061-47e0-b97c-5cbff0aaa0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791829243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.791829243
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.3203029945
Short name T614
Test name
Test status
Simulation time 89300668 ps
CPU time 1.33 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 218360 kb
Host smart-e579dbfc-5d53-44e6-baa3-bd6052668b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203029945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3203029945
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.683227978
Short name T756
Test name
Test status
Simulation time 26498600 ps
CPU time 1.27 seconds
Started Aug 06 07:42:31 PM PDT 24
Finished Aug 06 07:42:33 PM PDT 24
Peak memory 220148 kb
Host smart-769d9fd3-4fe4-4bd1-99ba-aed008629464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683227978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.683227978
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2051964494
Short name T681
Test name
Test status
Simulation time 18288910 ps
CPU time 0.93 seconds
Started Aug 06 07:42:28 PM PDT 24
Finished Aug 06 07:42:29 PM PDT 24
Peak memory 214468 kb
Host smart-d467869c-3d59-4538-be31-0e84df7edc85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051964494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2051964494
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2143745793
Short name T687
Test name
Test status
Simulation time 40285439 ps
CPU time 0.83 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 216204 kb
Host smart-c0a57acd-f988-437d-b591-ee6354ace0ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143745793 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2143745793
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2419844952
Short name T140
Test name
Test status
Simulation time 132352058 ps
CPU time 1.08 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:32 PM PDT 24
Peak memory 216728 kb
Host smart-23a1f2a4-b9d8-45cc-a53f-fc54fe305241
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419844952 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2419844952
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1439921766
Short name T771
Test name
Test status
Simulation time 26355014 ps
CPU time 1.21 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 220372 kb
Host smart-be978f7d-6358-4684-a1e5-9dea7ed46006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439921766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1439921766
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.294166095
Short name T657
Test name
Test status
Simulation time 70059064 ps
CPU time 1.42 seconds
Started Aug 06 07:42:09 PM PDT 24
Finished Aug 06 07:42:11 PM PDT 24
Peak memory 218072 kb
Host smart-b5523c97-bc82-47a3-83e3-31b2babccc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294166095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.294166095
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3382514599
Short name T612
Test name
Test status
Simulation time 21946430 ps
CPU time 1.08 seconds
Started Aug 06 07:42:31 PM PDT 24
Finished Aug 06 07:42:32 PM PDT 24
Peak memory 214944 kb
Host smart-e7b4874c-7780-4557-b856-36fd3c43c592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382514599 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3382514599
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.144488211
Short name T698
Test name
Test status
Simulation time 25284409 ps
CPU time 0.9 seconds
Started Aug 06 07:42:10 PM PDT 24
Finished Aug 06 07:42:11 PM PDT 24
Peak memory 214936 kb
Host smart-70fea199-7c88-49ba-a8ed-11734887901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144488211 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.144488211
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1379180084
Short name T693
Test name
Test status
Simulation time 159946475 ps
CPU time 2.93 seconds
Started Aug 06 07:42:08 PM PDT 24
Finished Aug 06 07:42:11 PM PDT 24
Peak memory 214880 kb
Host smart-8bc49a31-bcce-435e-bdd9-23134c7ea4b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379180084 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1379180084
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3614188143
Short name T311
Test name
Test status
Simulation time 360826193116 ps
CPU time 2542.16 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 08:24:53 PM PDT 24
Peak memory 229452 kb
Host smart-4ceb0523-d8f8-4a3c-82a8-a88ee1a55bc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614188143 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3614188143
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3433001538
Short name T189
Test name
Test status
Simulation time 28568792 ps
CPU time 1.18 seconds
Started Aug 06 07:45:25 PM PDT 24
Finished Aug 06 07:45:26 PM PDT 24
Peak memory 215276 kb
Host smart-bb705894-cd7c-43aa-8fcd-2b39be5089be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433001538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3433001538
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3803959224
Short name T893
Test name
Test status
Simulation time 25839865 ps
CPU time 1.27 seconds
Started Aug 06 07:45:26 PM PDT 24
Finished Aug 06 07:45:27 PM PDT 24
Peak memory 217096 kb
Host smart-be5dd6ef-b092-4bd8-ae6c-256a31837985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803959224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3803959224
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2748389209
Short name T672
Test name
Test status
Simulation time 285802914 ps
CPU time 1.35 seconds
Started Aug 06 07:45:27 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 218264 kb
Host smart-c5e99b5b-5554-4c16-96f1-329250e170e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748389209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2748389209
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3244061816
Short name T200
Test name
Test status
Simulation time 36125049 ps
CPU time 1.04 seconds
Started Aug 06 07:45:23 PM PDT 24
Finished Aug 06 07:45:24 PM PDT 24
Peak memory 218548 kb
Host smart-c0a44a6c-6853-42e2-98fb-c42d592c8150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244061816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3244061816
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2144723445
Short name T31
Test name
Test status
Simulation time 44402160 ps
CPU time 1.56 seconds
Started Aug 06 07:45:21 PM PDT 24
Finished Aug 06 07:45:22 PM PDT 24
Peak memory 216704 kb
Host smart-46a14745-1e68-407f-964c-b0e6373a97f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144723445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2144723445
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2018203394
Short name T182
Test name
Test status
Simulation time 46601129 ps
CPU time 1.14 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 219264 kb
Host smart-556ca3ca-dd0c-49e8-9d86-0dcd0ccc9f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018203394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2018203394
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.471899572
Short name T227
Test name
Test status
Simulation time 137374718 ps
CPU time 1.2 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 216984 kb
Host smart-df36780d-064c-4bda-94d5-2b968670efc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471899572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.471899572
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2861581719
Short name T664
Test name
Test status
Simulation time 59319972 ps
CPU time 1.02 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 218088 kb
Host smart-918f6f9d-e8e3-4c8a-a367-d8d253746bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861581719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2861581719
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3799175496
Short name T938
Test name
Test status
Simulation time 42319397 ps
CPU time 1.59 seconds
Started Aug 06 07:45:27 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 218108 kb
Host smart-463c12c7-c4cf-494a-911f-01faf5038de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799175496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3799175496
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.3444782285
Short name T968
Test name
Test status
Simulation time 31723506 ps
CPU time 1.21 seconds
Started Aug 06 07:45:25 PM PDT 24
Finished Aug 06 07:45:26 PM PDT 24
Peak memory 219228 kb
Host smart-22774424-dd31-4287-84be-19de8cd49233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444782285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3444782285
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.819025105
Short name T309
Test name
Test status
Simulation time 76772189 ps
CPU time 1.19 seconds
Started Aug 06 07:45:27 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 217016 kb
Host smart-6662342c-01b4-4aee-bffd-cdb33c47496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819025105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.819025105
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.3746852640
Short name T360
Test name
Test status
Simulation time 41897452 ps
CPU time 1.19 seconds
Started Aug 06 07:45:22 PM PDT 24
Finished Aug 06 07:45:23 PM PDT 24
Peak memory 219180 kb
Host smart-b2d9b96f-7059-4557-8991-0ccd36cdd8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746852640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.3746852640
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3449058381
Short name T342
Test name
Test status
Simulation time 55889936 ps
CPU time 0.98 seconds
Started Aug 06 07:45:23 PM PDT 24
Finished Aug 06 07:45:24 PM PDT 24
Peak memory 217040 kb
Host smart-8a712237-6548-435b-adf8-35e67088dd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449058381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3449058381
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3757947885
Short name T894
Test name
Test status
Simulation time 75098576 ps
CPU time 1.2 seconds
Started Aug 06 07:45:21 PM PDT 24
Finished Aug 06 07:45:23 PM PDT 24
Peak memory 218252 kb
Host smart-810566b8-1b02-4679-b2aa-c54d442c8413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757947885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3757947885
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.2971526522
Short name T605
Test name
Test status
Simulation time 52267129 ps
CPU time 1.86 seconds
Started Aug 06 07:45:21 PM PDT 24
Finished Aug 06 07:45:23 PM PDT 24
Peak memory 219632 kb
Host smart-38ed4e62-8107-43cb-9f34-f194f1dea46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971526522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2971526522
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.1329422035
Short name T579
Test name
Test status
Simulation time 181114414 ps
CPU time 1.35 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 220356 kb
Host smart-af02a208-15b5-40a6-b823-05483f79da0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329422035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1329422035
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.4182315693
Short name T404
Test name
Test status
Simulation time 207127359 ps
CPU time 1.4 seconds
Started Aug 06 07:45:28 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 217036 kb
Host smart-ba128623-7146-4275-bbcc-f38bc8f0f5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182315693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.4182315693
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2233583855
Short name T34
Test name
Test status
Simulation time 47320705 ps
CPU time 1.26 seconds
Started Aug 06 07:45:27 PM PDT 24
Finished Aug 06 07:45:28 PM PDT 24
Peak memory 217104 kb
Host smart-5c0cfaf5-f2ae-45db-9404-a1b59165b882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233583855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2233583855
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3330217995
Short name T281
Test name
Test status
Simulation time 68126939 ps
CPU time 1.11 seconds
Started Aug 06 07:40:38 PM PDT 24
Finished Aug 06 07:40:39 PM PDT 24
Peak memory 221080 kb
Host smart-fbc9c3af-918a-4af0-864f-25d2f19a384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330217995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3330217995
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3328294143
Short name T774
Test name
Test status
Simulation time 80947363 ps
CPU time 0.81 seconds
Started Aug 06 07:40:35 PM PDT 24
Finished Aug 06 07:40:36 PM PDT 24
Peak memory 206340 kb
Host smart-053c0c39-54e1-4ce0-b1a1-6e1e18753c40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328294143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3328294143
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.714092203
Short name T551
Test name
Test status
Simulation time 31297177 ps
CPU time 0.81 seconds
Started Aug 06 07:40:36 PM PDT 24
Finished Aug 06 07:40:37 PM PDT 24
Peak memory 215816 kb
Host smart-56653aa2-a711-48c1-9981-917655c592d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714092203 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.714092203
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3547006684
Short name T631
Test name
Test status
Simulation time 24022092 ps
CPU time 1.03 seconds
Started Aug 06 07:40:35 PM PDT 24
Finished Aug 06 07:40:36 PM PDT 24
Peak memory 215228 kb
Host smart-3b81df74-5314-43f4-838e-be60d1949e5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547006684 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3547006684
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3182042695
Short name T940
Test name
Test status
Simulation time 24387654 ps
CPU time 0.91 seconds
Started Aug 06 07:40:35 PM PDT 24
Finished Aug 06 07:40:36 PM PDT 24
Peak memory 218476 kb
Host smart-01e65ecb-59ab-4d86-95aa-4c107a37eae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182042695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3182042695
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.985702454
Short name T679
Test name
Test status
Simulation time 74901840 ps
CPU time 1.41 seconds
Started Aug 06 07:40:36 PM PDT 24
Finished Aug 06 07:40:38 PM PDT 24
Peak memory 216960 kb
Host smart-ce6acb83-53ef-4a43-b996-07826b6b3898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985702454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.985702454
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.222068252
Short name T855
Test name
Test status
Simulation time 22444254 ps
CPU time 0.98 seconds
Started Aug 06 07:40:35 PM PDT 24
Finished Aug 06 07:40:36 PM PDT 24
Peak memory 214904 kb
Host smart-1157f760-a315-4c86-acb4-b71af1c013dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222068252 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.222068252
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2222876466
Short name T964
Test name
Test status
Simulation time 39433985 ps
CPU time 0.88 seconds
Started Aug 06 07:40:36 PM PDT 24
Finished Aug 06 07:40:37 PM PDT 24
Peak memory 206600 kb
Host smart-5f8079d2-869a-492b-9a28-a30f862645df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222876466 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2222876466
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.419583042
Short name T388
Test name
Test status
Simulation time 111883960 ps
CPU time 0.89 seconds
Started Aug 06 07:40:36 PM PDT 24
Finished Aug 06 07:40:37 PM PDT 24
Peak memory 214828 kb
Host smart-88d23930-01b3-44de-b16e-8304931ff685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419583042 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.419583042
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2114762007
Short name T633
Test name
Test status
Simulation time 324701999 ps
CPU time 1.93 seconds
Started Aug 06 07:40:33 PM PDT 24
Finished Aug 06 07:40:35 PM PDT 24
Peak memory 216856 kb
Host smart-4f5e18a5-b552-4dde-b577-532550688877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114762007 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2114762007
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1406174618
Short name T424
Test name
Test status
Simulation time 1613021686590 ps
CPU time 3162 seconds
Started Aug 06 07:40:37 PM PDT 24
Finished Aug 06 08:33:19 PM PDT 24
Peak memory 227660 kb
Host smart-c6f289cf-3450-45a5-824b-489d69532fb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406174618 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1406174618
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.296208737
Short name T922
Test name
Test status
Simulation time 86306354 ps
CPU time 1.1 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 219224 kb
Host smart-cd9bb41d-2ca7-4bc4-9404-e73c3b124eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296208737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.296208737
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3065655200
Short name T680
Test name
Test status
Simulation time 22050887 ps
CPU time 0.85 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 206296 kb
Host smart-155332fd-2778-4713-819c-bf76b6b26b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065655200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3065655200
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.748623794
Short name T867
Test name
Test status
Simulation time 41235559 ps
CPU time 0.89 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 215132 kb
Host smart-049aa606-d3ec-48bb-a5ec-9b741c443a85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748623794 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.748623794
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.4127809920
Short name T768
Test name
Test status
Simulation time 39881346 ps
CPU time 1.05 seconds
Started Aug 06 07:42:31 PM PDT 24
Finished Aug 06 07:42:32 PM PDT 24
Peak memory 219380 kb
Host smart-35c75aa4-8f2c-4ed0-99f9-370114483209
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127809920 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.4127809920
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.507292721
Short name T105
Test name
Test status
Simulation time 21842683 ps
CPU time 0.99 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 218376 kb
Host smart-aa079962-3dbb-48a5-adaf-347dad3a2172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507292721 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.507292721
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3953773535
Short name T911
Test name
Test status
Simulation time 46073020 ps
CPU time 1.36 seconds
Started Aug 06 07:42:35 PM PDT 24
Finished Aug 06 07:42:37 PM PDT 24
Peak memory 218328 kb
Host smart-a618a8a9-b948-460a-9fbb-9846726ed077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953773535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3953773535
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.4248799496
Short name T776
Test name
Test status
Simulation time 24543293 ps
CPU time 1.05 seconds
Started Aug 06 07:42:28 PM PDT 24
Finished Aug 06 07:42:29 PM PDT 24
Peak memory 223828 kb
Host smart-6e015fba-dd5e-498b-b314-ca0d3fbde0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248799496 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.4248799496
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2044322316
Short name T354
Test name
Test status
Simulation time 17181758 ps
CPU time 1.03 seconds
Started Aug 06 07:42:28 PM PDT 24
Finished Aug 06 07:42:29 PM PDT 24
Peak memory 215088 kb
Host smart-a096eba1-96bf-4821-9bd8-281d367464fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044322316 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2044322316
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2343890646
Short name T531
Test name
Test status
Simulation time 1554519711 ps
CPU time 3.3 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:36 PM PDT 24
Peak memory 216968 kb
Host smart-b41a3c98-cd55-424e-bbb8-108f6ea26e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343890646 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2343890646
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3280134370
Short name T728
Test name
Test status
Simulation time 151658652366 ps
CPU time 860.89 seconds
Started Aug 06 07:42:34 PM PDT 24
Finished Aug 06 07:56:55 PM PDT 24
Peak memory 220732 kb
Host smart-63bf3695-4062-4c52-a0e6-f33b9da437e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280134370 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3280134370
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3112697434
Short name T824
Test name
Test status
Simulation time 57937563 ps
CPU time 1.29 seconds
Started Aug 06 07:45:27 PM PDT 24
Finished Aug 06 07:45:29 PM PDT 24
Peak memory 219480 kb
Host smart-096bb5ac-1e50-4ce7-90ac-1202874729bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112697434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3112697434
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.772751750
Short name T972
Test name
Test status
Simulation time 52932051 ps
CPU time 1.14 seconds
Started Aug 06 07:45:44 PM PDT 24
Finished Aug 06 07:45:45 PM PDT 24
Peak memory 216804 kb
Host smart-471c42e6-fb83-4ee5-bb3a-032a62e46f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772751750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.772751750
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.78113339
Short name T425
Test name
Test status
Simulation time 186416943 ps
CPU time 1.9 seconds
Started Aug 06 07:45:41 PM PDT 24
Finished Aug 06 07:45:43 PM PDT 24
Peak memory 218656 kb
Host smart-d9537df3-6752-43f3-b63b-671cd12195d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78113339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.78113339
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3476583556
Short name T788
Test name
Test status
Simulation time 41664990 ps
CPU time 1.33 seconds
Started Aug 06 07:45:36 PM PDT 24
Finished Aug 06 07:45:37 PM PDT 24
Peak memory 218184 kb
Host smart-f8463bca-e6c6-4608-b02c-e08ec44a9e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476583556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3476583556
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3307292809
Short name T533
Test name
Test status
Simulation time 317205695 ps
CPU time 4.23 seconds
Started Aug 06 07:45:38 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 217128 kb
Host smart-8e9e1b5e-6f7e-42c3-9c5b-121335fff0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307292809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3307292809
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1895321391
Short name T962
Test name
Test status
Simulation time 136592534 ps
CPU time 1.31 seconds
Started Aug 06 07:45:39 PM PDT 24
Finished Aug 06 07:45:41 PM PDT 24
Peak memory 218504 kb
Host smart-c4dca508-35ab-4d1c-acab-bd2b3d69d5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895321391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1895321391
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4204118628
Short name T883
Test name
Test status
Simulation time 37083649 ps
CPU time 1.28 seconds
Started Aug 06 07:45:35 PM PDT 24
Finished Aug 06 07:45:37 PM PDT 24
Peak memory 216996 kb
Host smart-de5b4323-cf40-4973-bbcc-2b184e81febc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204118628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4204118628
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.160881511
Short name T700
Test name
Test status
Simulation time 76391987 ps
CPU time 1.61 seconds
Started Aug 06 07:45:38 PM PDT 24
Finished Aug 06 07:45:40 PM PDT 24
Peak memory 218380 kb
Host smart-a2f034cb-ed12-4e56-9fe2-059681d2c545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160881511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.160881511
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3812914486
Short name T822
Test name
Test status
Simulation time 69243275 ps
CPU time 1.05 seconds
Started Aug 06 07:42:29 PM PDT 24
Finished Aug 06 07:42:30 PM PDT 24
Peak memory 220432 kb
Host smart-d526c90e-e713-417a-8ea6-71f77b14dc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812914486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3812914486
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1714951306
Short name T428
Test name
Test status
Simulation time 151312357 ps
CPU time 0.88 seconds
Started Aug 06 07:42:29 PM PDT 24
Finished Aug 06 07:42:30 PM PDT 24
Peak memory 206240 kb
Host smart-a1c84960-ec9c-483f-b3e0-659452df317e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714951306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1714951306
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2087132174
Short name T185
Test name
Test status
Simulation time 98194101 ps
CPU time 0.82 seconds
Started Aug 06 07:42:34 PM PDT 24
Finished Aug 06 07:42:35 PM PDT 24
Peak memory 216192 kb
Host smart-5a9ed22e-6416-4ecf-94ea-a3cd0a74318c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087132174 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2087132174
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1883389127
Short name T504
Test name
Test status
Simulation time 60488626 ps
CPU time 1.11 seconds
Started Aug 06 07:42:31 PM PDT 24
Finished Aug 06 07:42:33 PM PDT 24
Peak memory 218236 kb
Host smart-475a29a8-acf1-453b-ae6c-e61172440808
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883389127 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1883389127
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2319658727
Short name T447
Test name
Test status
Simulation time 19465074 ps
CPU time 1.06 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 218388 kb
Host smart-abbe3462-d298-4902-8f87-3064a4e174fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319658727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2319658727
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.304290235
Short name T401
Test name
Test status
Simulation time 77523203 ps
CPU time 1.25 seconds
Started Aug 06 07:42:31 PM PDT 24
Finished Aug 06 07:42:33 PM PDT 24
Peak memory 218316 kb
Host smart-e3566ae7-02da-40f5-b295-12ce85b10669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304290235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.304290235
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3188346655
Short name T526
Test name
Test status
Simulation time 33063278 ps
CPU time 0.93 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 214984 kb
Host smart-138ba1ad-f356-41e6-8819-46a8c186f0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188346655 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3188346655
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2676888374
Short name T411
Test name
Test status
Simulation time 26771099 ps
CPU time 0.95 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 214864 kb
Host smart-c45759dc-f39a-48a9-b3b8-e15d879192e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676888374 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2676888374
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3211844629
Short name T730
Test name
Test status
Simulation time 152957414 ps
CPU time 3.47 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:36 PM PDT 24
Peak memory 217060 kb
Host smart-5bbcaac6-ca16-4cc7-9b61-4b4de1897893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211844629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3211844629
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2705632346
Short name T421
Test name
Test status
Simulation time 249367504398 ps
CPU time 935.84 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:58:06 PM PDT 24
Peak memory 223100 kb
Host smart-aab5b974-fbb5-4aac-9593-ffe5127c6a68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705632346 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2705632346
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.550719655
Short name T592
Test name
Test status
Simulation time 35428536 ps
CPU time 1.34 seconds
Started Aug 06 07:45:43 PM PDT 24
Finished Aug 06 07:45:45 PM PDT 24
Peak memory 218276 kb
Host smart-7da6ae25-5c40-4d45-9cf1-dbbbee77d0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550719655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.550719655
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2310738685
Short name T724
Test name
Test status
Simulation time 130565419 ps
CPU time 1.17 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:41 PM PDT 24
Peak memory 215156 kb
Host smart-c387d8a3-6307-44dd-8497-f0a453792f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310738685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2310738685
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3402169447
Short name T850
Test name
Test status
Simulation time 37576409 ps
CPU time 1.63 seconds
Started Aug 06 07:45:37 PM PDT 24
Finished Aug 06 07:45:39 PM PDT 24
Peak memory 218252 kb
Host smart-6da8a46d-2ac5-4fd9-a69d-19cde16fe959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402169447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3402169447
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3741571531
Short name T316
Test name
Test status
Simulation time 54237099 ps
CPU time 0.99 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 214840 kb
Host smart-7aef3282-90f0-425e-b7f6-13931e91eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741571531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3741571531
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1376732949
Short name T741
Test name
Test status
Simulation time 174746967 ps
CPU time 1.01 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:41 PM PDT 24
Peak memory 216880 kb
Host smart-1fee54f0-8669-48e3-a3a9-c273a9d667ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376732949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1376732949
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3104257595
Short name T772
Test name
Test status
Simulation time 44804380 ps
CPU time 1.54 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:41 PM PDT 24
Peak memory 219768 kb
Host smart-9e9814a2-2f95-44ab-9b42-c8fb3b4e3466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104257595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3104257595
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1096993398
Short name T513
Test name
Test status
Simulation time 51332089 ps
CPU time 1.29 seconds
Started Aug 06 07:45:41 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 218072 kb
Host smart-1df39907-342e-464d-a193-3e36846f31bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096993398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1096993398
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1017762218
Short name T560
Test name
Test status
Simulation time 39988921 ps
CPU time 1.46 seconds
Started Aug 06 07:45:38 PM PDT 24
Finished Aug 06 07:45:40 PM PDT 24
Peak memory 219612 kb
Host smart-bb75bae6-cfa3-4fa6-ad46-4540b32befed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017762218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1017762218
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3276775388
Short name T809
Test name
Test status
Simulation time 76303728 ps
CPU time 1.16 seconds
Started Aug 06 07:45:36 PM PDT 24
Finished Aug 06 07:45:37 PM PDT 24
Peak memory 216784 kb
Host smart-88cb1659-c280-46e8-ac9c-39fc5742df5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276775388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3276775388
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3296115778
Short name T432
Test name
Test status
Simulation time 200440086 ps
CPU time 2.67 seconds
Started Aug 06 07:45:35 PM PDT 24
Finished Aug 06 07:45:38 PM PDT 24
Peak memory 219964 kb
Host smart-2bee635d-03e9-479a-b941-33e7247817b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296115778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3296115778
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1276800771
Short name T878
Test name
Test status
Simulation time 37170748 ps
CPU time 1.05 seconds
Started Aug 06 07:42:28 PM PDT 24
Finished Aug 06 07:42:29 PM PDT 24
Peak memory 218036 kb
Host smart-cfd821ed-a53d-4143-be9f-988cdacce32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276800771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1276800771
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.595276914
Short name T596
Test name
Test status
Simulation time 18918698 ps
CPU time 0.95 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 206320 kb
Host smart-116bc3f6-69d3-44c7-a9bf-1a70ba84b145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595276914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.595276914
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.609127219
Short name T15
Test name
Test status
Simulation time 168002630 ps
CPU time 1.11 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:42:33 PM PDT 24
Peak memory 219192 kb
Host smart-b51124ad-b172-49f4-89ad-b7248759f33b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609127219 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.609127219
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1151878056
Short name T120
Test name
Test status
Simulation time 127767106 ps
CPU time 0.98 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 219576 kb
Host smart-981228cb-3b9f-48e5-a9ea-3442bbfcc630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151878056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1151878056
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1295032781
Short name T381
Test name
Test status
Simulation time 96711855 ps
CPU time 1.22 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:32 PM PDT 24
Peak memory 218184 kb
Host smart-67a81018-c70e-42ad-b1a0-5484e45cd53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295032781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1295032781
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.4123782682
Short name T76
Test name
Test status
Simulation time 35076253 ps
CPU time 0.87 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:42:33 PM PDT 24
Peak memory 215596 kb
Host smart-9251d7ee-5e0b-4646-a1c3-ae33d81fe6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123782682 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.4123782682
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2410544159
Short name T563
Test name
Test status
Simulation time 16267122 ps
CPU time 0.99 seconds
Started Aug 06 07:42:29 PM PDT 24
Finished Aug 06 07:42:30 PM PDT 24
Peak memory 214932 kb
Host smart-64aa03c4-63b0-496a-9e00-ed0bb6a6a981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410544159 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2410544159
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2556528433
Short name T445
Test name
Test status
Simulation time 25340982 ps
CPU time 1.05 seconds
Started Aug 06 07:42:31 PM PDT 24
Finished Aug 06 07:42:33 PM PDT 24
Peak memory 206256 kb
Host smart-a3b6c5cf-99d4-49c5-9c34-64a85d5246e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556528433 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2556528433
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.775700880
Short name T223
Test name
Test status
Simulation time 129006489887 ps
CPU time 1488.29 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 08:07:21 PM PDT 24
Peak memory 222868 kb
Host smart-7befe81c-5473-42b9-a141-f623a4be5051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775700880 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.775700880
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/221.edn_genbits.1588834266
Short name T17
Test name
Test status
Simulation time 55662131 ps
CPU time 1.33 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 219896 kb
Host smart-50c3f2bf-bf6e-41b2-ac11-4a7f97fcec28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588834266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1588834266
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3639340301
Short name T315
Test name
Test status
Simulation time 44698433 ps
CPU time 1.57 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 217964 kb
Host smart-bcfd02b6-205c-4d00-8228-ff53d5517abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639340301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3639340301
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3408871336
Short name T720
Test name
Test status
Simulation time 43669548 ps
CPU time 1.47 seconds
Started Aug 06 07:45:41 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 217004 kb
Host smart-7eab08e4-c105-4512-914f-c93e2145d8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408871336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3408871336
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4151662678
Short name T429
Test name
Test status
Simulation time 107232805 ps
CPU time 1.41 seconds
Started Aug 06 07:45:42 PM PDT 24
Finished Aug 06 07:45:43 PM PDT 24
Peak memory 217020 kb
Host smart-898f23e3-8e10-45f8-ae1d-c98a78d9c3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151662678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4151662678
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2946345057
Short name T537
Test name
Test status
Simulation time 63004912 ps
CPU time 0.98 seconds
Started Aug 06 07:45:39 PM PDT 24
Finished Aug 06 07:45:40 PM PDT 24
Peak memory 214996 kb
Host smart-36f81685-72a4-4a70-801c-94a8db3db94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946345057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2946345057
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3442399357
Short name T524
Test name
Test status
Simulation time 52531440 ps
CPU time 1.41 seconds
Started Aug 06 07:45:35 PM PDT 24
Finished Aug 06 07:45:37 PM PDT 24
Peak memory 218196 kb
Host smart-0a991597-ffe3-4f3e-9774-25000e2637c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442399357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3442399357
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1341391565
Short name T613
Test name
Test status
Simulation time 37355656 ps
CPU time 1.4 seconds
Started Aug 06 07:45:39 PM PDT 24
Finished Aug 06 07:45:40 PM PDT 24
Peak memory 217936 kb
Host smart-81345f85-ac24-45c1-ade1-e2736589eb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341391565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1341391565
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1693517132
Short name T477
Test name
Test status
Simulation time 52569153 ps
CPU time 1.87 seconds
Started Aug 06 07:45:42 PM PDT 24
Finished Aug 06 07:45:44 PM PDT 24
Peak memory 218304 kb
Host smart-c74faced-2a6a-49d4-9073-afd93f7aa77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693517132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1693517132
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.4206388818
Short name T939
Test name
Test status
Simulation time 266231666 ps
CPU time 3.4 seconds
Started Aug 06 07:45:39 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 220036 kb
Host smart-57c68b75-3748-4b6f-8334-e631d21828b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206388818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.4206388818
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2995194615
Short name T133
Test name
Test status
Simulation time 42057373 ps
CPU time 1.15 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 219108 kb
Host smart-14326bee-f0dc-4d40-9a08-dff6501ea989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995194615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2995194615
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3226332026
Short name T836
Test name
Test status
Simulation time 38629661 ps
CPU time 0.8 seconds
Started Aug 06 07:42:31 PM PDT 24
Finished Aug 06 07:42:32 PM PDT 24
Peak memory 206020 kb
Host smart-42d12ac3-113e-4c4c-acfd-5b8b8d06d499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226332026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3226332026
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2224628770
Short name T945
Test name
Test status
Simulation time 15152141 ps
CPU time 0.93 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:42:33 PM PDT 24
Peak memory 216304 kb
Host smart-4bb9438f-a227-456f-a6be-f2121786a019
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224628770 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2224628770
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.227985338
Short name T634
Test name
Test status
Simulation time 62832189 ps
CPU time 1.2 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 218196 kb
Host smart-50f5a290-d95e-4024-9219-d30f49e39048
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227985338 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.227985338
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1086392717
Short name T115
Test name
Test status
Simulation time 19439539 ps
CPU time 1.09 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 223832 kb
Host smart-102f594e-f74e-4734-a5a5-afe3d0cbd8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086392717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1086392717
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3040858365
Short name T536
Test name
Test status
Simulation time 82451566 ps
CPU time 1.23 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 218156 kb
Host smart-a424795a-6450-495c-8e5d-93111da9a7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040858365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3040858365
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3283631232
Short name T565
Test name
Test status
Simulation time 37654157 ps
CPU time 0.99 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 223652 kb
Host smart-e48c6804-d369-4095-b144-822021759f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283631232 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3283631232
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3914509188
Short name T418
Test name
Test status
Simulation time 16633282 ps
CPU time 0.96 seconds
Started Aug 06 07:42:28 PM PDT 24
Finished Aug 06 07:42:29 PM PDT 24
Peak memory 214860 kb
Host smart-66e20de2-9e07-4096-a7b3-17713198ed84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914509188 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3914509188
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1126064759
Short name T364
Test name
Test status
Simulation time 298908141 ps
CPU time 1.37 seconds
Started Aug 06 07:42:29 PM PDT 24
Finished Aug 06 07:42:30 PM PDT 24
Peak memory 214840 kb
Host smart-bb6ccb05-6be7-4d87-9e59-54cba69425f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126064759 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1126064759
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2350507550
Short name T881
Test name
Test status
Simulation time 165662180617 ps
CPU time 668.43 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:53:39 PM PDT 24
Peak memory 219600 kb
Host smart-1e277704-a277-4dca-84d5-2e8f6297f82f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350507550 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2350507550
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1781818513
Short name T299
Test name
Test status
Simulation time 67930869 ps
CPU time 1.26 seconds
Started Aug 06 07:45:39 PM PDT 24
Finished Aug 06 07:45:41 PM PDT 24
Peak memory 217100 kb
Host smart-2c8fa403-6597-4f45-b523-71f82ac1dab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781818513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1781818513
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1680789448
Short name T306
Test name
Test status
Simulation time 90674319 ps
CPU time 1.56 seconds
Started Aug 06 07:45:43 PM PDT 24
Finished Aug 06 07:45:44 PM PDT 24
Peak memory 218532 kb
Host smart-c87d4e6b-6323-4a09-88da-4d70cb5495f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680789448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1680789448
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.141669358
Short name T327
Test name
Test status
Simulation time 28231790 ps
CPU time 1.27 seconds
Started Aug 06 07:45:43 PM PDT 24
Finished Aug 06 07:45:44 PM PDT 24
Peak memory 219304 kb
Host smart-e5fcf13e-d728-421c-a324-2681e562fc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141669358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.141669358
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.57578757
Short name T240
Test name
Test status
Simulation time 61130539 ps
CPU time 1.31 seconds
Started Aug 06 07:45:39 PM PDT 24
Finished Aug 06 07:45:41 PM PDT 24
Peak memory 219108 kb
Host smart-a0d81345-bc81-4f20-a157-cffff6246d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57578757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.57578757
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2720803039
Short name T616
Test name
Test status
Simulation time 55132709 ps
CPU time 1.34 seconds
Started Aug 06 07:45:42 PM PDT 24
Finished Aug 06 07:45:44 PM PDT 24
Peak memory 218112 kb
Host smart-c6c16000-f57e-453b-8643-35be09868197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720803039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2720803039
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.4085883392
Short name T351
Test name
Test status
Simulation time 89801959 ps
CPU time 1.28 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 218288 kb
Host smart-3b4738cf-0697-41e2-9410-da02c5ea7b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085883392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.4085883392
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2868326178
Short name T770
Test name
Test status
Simulation time 74091942 ps
CPU time 1.76 seconds
Started Aug 06 07:45:42 PM PDT 24
Finished Aug 06 07:45:44 PM PDT 24
Peak memory 218040 kb
Host smart-388f9fd4-b060-46f9-b831-4cdbcb4438a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868326178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2868326178
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1094635840
Short name T713
Test name
Test status
Simulation time 81575729 ps
CPU time 1.36 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:41 PM PDT 24
Peak memory 218148 kb
Host smart-6dc04c21-4dad-4386-a3b8-fa5d27359871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094635840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1094635840
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.139302809
Short name T834
Test name
Test status
Simulation time 26350354 ps
CPU time 1.23 seconds
Started Aug 06 07:45:38 PM PDT 24
Finished Aug 06 07:45:39 PM PDT 24
Peak memory 216960 kb
Host smart-3288f23f-9fdc-476f-ab3f-0c62932fd271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139302809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.139302809
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.308031912
Short name T488
Test name
Test status
Simulation time 202088464 ps
CPU time 1.12 seconds
Started Aug 06 07:45:38 PM PDT 24
Finished Aug 06 07:45:39 PM PDT 24
Peak memory 219648 kb
Host smart-1740738c-aebf-4409-bca3-c3dad45cffc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308031912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.308031912
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3226535985
Short name T810
Test name
Test status
Simulation time 88083469 ps
CPU time 1.25 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 219412 kb
Host smart-6564970a-8e9f-41b4-96d7-9e72bd980852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226535985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3226535985
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3032164160
Short name T886
Test name
Test status
Simulation time 56657161 ps
CPU time 0.91 seconds
Started Aug 06 07:42:34 PM PDT 24
Finished Aug 06 07:42:35 PM PDT 24
Peak memory 214760 kb
Host smart-b38b9f7f-6557-43cf-8a44-853cb39d27d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032164160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3032164160
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.4075778842
Short name T871
Test name
Test status
Simulation time 34718425 ps
CPU time 0.83 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 216176 kb
Host smart-d94d8d70-fc05-49b3-8126-921596e0f4c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075778842 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.4075778842
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2522226507
Short name T117
Test name
Test status
Simulation time 29757884 ps
CPU time 1.26 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 216844 kb
Host smart-21575933-650b-4e70-9745-1c4a0bc75a18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522226507 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2522226507
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1884623677
Short name T549
Test name
Test status
Simulation time 18595648 ps
CPU time 1.12 seconds
Started Aug 06 07:42:34 PM PDT 24
Finished Aug 06 07:42:35 PM PDT 24
Peak memory 223852 kb
Host smart-8cafbc45-25f2-4704-a59d-62d170727489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884623677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1884623677
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3022220848
Short name T787
Test name
Test status
Simulation time 222779034 ps
CPU time 1.68 seconds
Started Aug 06 07:42:35 PM PDT 24
Finished Aug 06 07:42:37 PM PDT 24
Peak memory 218296 kb
Host smart-771090c3-2c80-415c-9938-a4a2bd44cdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022220848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3022220848
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1938610426
Short name T206
Test name
Test status
Simulation time 34742424 ps
CPU time 0.91 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 214876 kb
Host smart-b74693db-2add-4043-ab98-653a2a59ebfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938610426 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1938610426
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.318881176
Short name T807
Test name
Test status
Simulation time 16800408 ps
CPU time 0.99 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 214852 kb
Host smart-cf6a37f5-098f-44d4-91b6-17f9d5b37847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318881176 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.318881176
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.4193510655
Short name T39
Test name
Test status
Simulation time 168160682 ps
CPU time 3.75 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 214876 kb
Host smart-2e7ca682-4006-44a5-882a-e0a561dae689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193510655 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.4193510655
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2490849754
Short name T806
Test name
Test status
Simulation time 45468588702 ps
CPU time 646.67 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:53:17 PM PDT 24
Peak memory 223272 kb
Host smart-2d3c04c2-2cdd-4b53-9623-722810f53fff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490849754 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2490849754
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1425797152
Short name T847
Test name
Test status
Simulation time 39839325 ps
CPU time 1.12 seconds
Started Aug 06 07:45:44 PM PDT 24
Finished Aug 06 07:45:46 PM PDT 24
Peak memory 217116 kb
Host smart-1e97f6b4-a3f5-4c0c-b129-e704fede3183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425797152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1425797152
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1049580719
Short name T779
Test name
Test status
Simulation time 81760840 ps
CPU time 1.31 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:41 PM PDT 24
Peak memory 219624 kb
Host smart-5da94818-7c73-47c3-a816-ad209467e58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049580719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1049580719
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.541219986
Short name T392
Test name
Test status
Simulation time 276862716 ps
CPU time 3.62 seconds
Started Aug 06 07:45:35 PM PDT 24
Finished Aug 06 07:45:38 PM PDT 24
Peak memory 219076 kb
Host smart-a4d07673-696c-4333-8355-f6b0979ba5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541219986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.541219986
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3026894948
Short name T502
Test name
Test status
Simulation time 86360085 ps
CPU time 1.14 seconds
Started Aug 06 07:45:38 PM PDT 24
Finished Aug 06 07:45:40 PM PDT 24
Peak memory 216912 kb
Host smart-56d16817-028a-4aa8-9dde-03651c6e94fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026894948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3026894948
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3126478726
Short name T344
Test name
Test status
Simulation time 110919762 ps
CPU time 1.74 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 219008 kb
Host smart-9966b8ee-1923-4db7-9af4-80249dd0c127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126478726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3126478726
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1811785277
Short name T329
Test name
Test status
Simulation time 27598758 ps
CPU time 1.35 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 218228 kb
Host smart-3a39ff58-9dae-4f43-a96d-e114d558d67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811785277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1811785277
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.314131193
Short name T858
Test name
Test status
Simulation time 61977976 ps
CPU time 1.09 seconds
Started Aug 06 07:45:38 PM PDT 24
Finished Aug 06 07:45:40 PM PDT 24
Peak memory 219392 kb
Host smart-541f6685-6ef3-4b27-9a9a-5ca353573782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314131193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.314131193
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1364692861
Short name T525
Test name
Test status
Simulation time 107144965 ps
CPU time 2.54 seconds
Started Aug 06 07:45:39 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 219924 kb
Host smart-1a9e74e3-3eb7-44d3-aa54-a4de9726d65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364692861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1364692861
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1002143665
Short name T183
Test name
Test status
Simulation time 62748661 ps
CPU time 1.1 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:42:33 PM PDT 24
Peak memory 219280 kb
Host smart-8e37ed49-86bf-48e8-9e43-baf51d61d459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002143665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1002143665
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1681702405
Short name T437
Test name
Test status
Simulation time 30359929 ps
CPU time 0.91 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:42:33 PM PDT 24
Peak memory 206356 kb
Host smart-3ec17424-8b89-4605-9c4f-c0cd7edc3988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681702405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1681702405
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1042760782
Short name T906
Test name
Test status
Simulation time 12039331 ps
CPU time 0.93 seconds
Started Aug 06 07:42:31 PM PDT 24
Finished Aug 06 07:42:32 PM PDT 24
Peak memory 215884 kb
Host smart-c73447a7-25f5-481c-8a22-2b38b814fded
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042760782 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1042760782
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.2128863634
Short name T121
Test name
Test status
Simulation time 24914097 ps
CPU time 0.98 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:42:33 PM PDT 24
Peak memory 219532 kb
Host smart-f946acc1-a378-46cf-ba4e-fc6db30416b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128863634 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2128863634
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2752221799
Short name T981
Test name
Test status
Simulation time 43080649 ps
CPU time 1.12 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 217196 kb
Host smart-974f3683-982d-4391-8fc4-c8d4c4a5ff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752221799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2752221799
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.277124786
Short name T575
Test name
Test status
Simulation time 46821052 ps
CPU time 0.85 seconds
Started Aug 06 07:42:31 PM PDT 24
Finished Aug 06 07:42:32 PM PDT 24
Peak memory 214848 kb
Host smart-c9884607-13a4-40d4-a61e-da5f0435d0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277124786 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.277124786
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.4118695020
Short name T375
Test name
Test status
Simulation time 25576347 ps
CPU time 0.94 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 214880 kb
Host smart-c620ed63-c8da-4c6f-ae3c-c72cfdaedb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118695020 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.4118695020
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.4167999359
Short name T493
Test name
Test status
Simulation time 899515405 ps
CPU time 4.21 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 216800 kb
Host smart-0884153c-4748-4b61-8017-921a34c2ce4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167999359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.4167999359
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2437772555
Short name T217
Test name
Test status
Simulation time 48667610964 ps
CPU time 319.5 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:47:51 PM PDT 24
Peak memory 223380 kb
Host smart-65ffc945-0874-4cf2-a56b-fd7d048c7e87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437772555 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2437772555
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2408764547
Short name T899
Test name
Test status
Simulation time 72800259 ps
CPU time 1.27 seconds
Started Aug 06 07:45:39 PM PDT 24
Finished Aug 06 07:45:41 PM PDT 24
Peak memory 218352 kb
Host smart-a526a932-5e45-4db3-ac7c-1eb5174c0dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408764547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2408764547
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2528124977
Short name T963
Test name
Test status
Simulation time 59154936 ps
CPU time 1.43 seconds
Started Aug 06 07:45:36 PM PDT 24
Finished Aug 06 07:45:38 PM PDT 24
Peak memory 218104 kb
Host smart-1d1edb45-d5ff-4730-bd0e-93416710ae60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528124977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2528124977
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1103307003
Short name T623
Test name
Test status
Simulation time 42553009 ps
CPU time 1.15 seconds
Started Aug 06 07:45:42 PM PDT 24
Finished Aug 06 07:45:43 PM PDT 24
Peak memory 216784 kb
Host smart-725d4038-f63a-43e9-be8e-ff553f88c416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103307003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1103307003
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.649615970
Short name T838
Test name
Test status
Simulation time 36174811 ps
CPU time 1.1 seconds
Started Aug 06 07:45:42 PM PDT 24
Finished Aug 06 07:45:43 PM PDT 24
Peak memory 219564 kb
Host smart-9987f9c5-2a34-4cd0-9ca6-b2587264ef05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649615970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.649615970
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2380583313
Short name T926
Test name
Test status
Simulation time 46017280 ps
CPU time 1.43 seconds
Started Aug 06 07:45:42 PM PDT 24
Finished Aug 06 07:45:44 PM PDT 24
Peak memory 219468 kb
Host smart-b9195980-7726-4577-9654-f614e138153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380583313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2380583313
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2888704776
Short name T767
Test name
Test status
Simulation time 43557050 ps
CPU time 1.46 seconds
Started Aug 06 07:45:39 PM PDT 24
Finished Aug 06 07:45:40 PM PDT 24
Peak memory 218480 kb
Host smart-cec2592a-0824-4d91-a1fb-29694d626bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888704776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2888704776
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2137429215
Short name T319
Test name
Test status
Simulation time 5248182033 ps
CPU time 95.32 seconds
Started Aug 06 07:45:38 PM PDT 24
Finished Aug 06 07:47:13 PM PDT 24
Peak memory 220380 kb
Host smart-9f25d99e-84f4-4f9c-bb97-12482addc9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137429215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2137429215
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1098702081
Short name T481
Test name
Test status
Simulation time 39796064 ps
CPU time 1.31 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 219608 kb
Host smart-c8da90e8-55f6-4ed4-8493-e58f677677dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098702081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1098702081
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3552047594
Short name T794
Test name
Test status
Simulation time 41416658 ps
CPU time 1.66 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 218224 kb
Host smart-f0bd1c52-b50c-4458-9ad1-cc7b17380cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552047594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3552047594
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3123773350
Short name T291
Test name
Test status
Simulation time 43379833 ps
CPU time 1.2 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 218272 kb
Host smart-84798b1a-f1c0-433d-b78f-05342e9e3cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123773350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3123773350
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.215991119
Short name T359
Test name
Test status
Simulation time 15013292 ps
CPU time 0.89 seconds
Started Aug 06 07:42:34 PM PDT 24
Finished Aug 06 07:42:35 PM PDT 24
Peak memory 206332 kb
Host smart-499e31ba-51ba-4a08-9d8b-316bc2520d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215991119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.215991119
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3965240600
Short name T758
Test name
Test status
Simulation time 77765563 ps
CPU time 1.31 seconds
Started Aug 06 07:42:35 PM PDT 24
Finished Aug 06 07:42:36 PM PDT 24
Peak memory 216836 kb
Host smart-e4bc8582-2953-49a9-8364-6c5aaa9315e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965240600 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3965240600
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2743823736
Short name T934
Test name
Test status
Simulation time 45201305 ps
CPU time 1.23 seconds
Started Aug 06 07:42:34 PM PDT 24
Finished Aug 06 07:42:35 PM PDT 24
Peak memory 225484 kb
Host smart-1eae95d9-7749-4fe2-aabf-5349588972c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743823736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2743823736
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.293648564
Short name T645
Test name
Test status
Simulation time 74183059 ps
CPU time 1.02 seconds
Started Aug 06 07:42:34 PM PDT 24
Finished Aug 06 07:42:35 PM PDT 24
Peak memory 216872 kb
Host smart-23d25dab-0359-4935-9312-3f3a516ff6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293648564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.293648564
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.1427440479
Short name T331
Test name
Test status
Simulation time 25177155 ps
CPU time 0.93 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:42:33 PM PDT 24
Peak memory 206688 kb
Host smart-58c6e24c-3616-451d-bcdb-86bbb19743c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427440479 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1427440479
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3019310362
Short name T435
Test name
Test status
Simulation time 120347986 ps
CPU time 2.61 seconds
Started Aug 06 07:42:33 PM PDT 24
Finished Aug 06 07:42:36 PM PDT 24
Peak memory 214972 kb
Host smart-2736fa5e-3516-42ff-919e-bfc642f56783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019310362 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3019310362
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3893520230
Short name T501
Test name
Test status
Simulation time 223661561595 ps
CPU time 1423.69 seconds
Started Aug 06 07:42:34 PM PDT 24
Finished Aug 06 08:06:18 PM PDT 24
Peak memory 225940 kb
Host smart-b8e27692-7995-4fd9-bbc6-42357fa584fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893520230 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3893520230
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1886934136
Short name T340
Test name
Test status
Simulation time 82028843 ps
CPU time 1.75 seconds
Started Aug 06 07:45:44 PM PDT 24
Finished Aug 06 07:45:46 PM PDT 24
Peak memory 218476 kb
Host smart-d54a2436-7eee-4f78-aaac-b60c98457398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886934136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1886934136
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.355523552
Short name T984
Test name
Test status
Simulation time 33473620 ps
CPU time 1.24 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 217956 kb
Host smart-03e7cedb-2941-4e6f-b2f6-051b5abbe349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355523552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.355523552
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3573254014
Short name T417
Test name
Test status
Simulation time 37842609 ps
CPU time 1.11 seconds
Started Aug 06 07:45:42 PM PDT 24
Finished Aug 06 07:45:43 PM PDT 24
Peak memory 216988 kb
Host smart-f966f0e0-f770-422f-af90-7ad51a688858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573254014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3573254014
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2885791870
Short name T318
Test name
Test status
Simulation time 148683898 ps
CPU time 3.03 seconds
Started Aug 06 07:45:35 PM PDT 24
Finished Aug 06 07:45:38 PM PDT 24
Peak memory 218196 kb
Host smart-9c6125b4-f172-4052-b40c-4f5a1fa2f442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885791870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2885791870
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1192151115
Short name T394
Test name
Test status
Simulation time 138250769 ps
CPU time 1.01 seconds
Started Aug 06 07:45:42 PM PDT 24
Finished Aug 06 07:45:43 PM PDT 24
Peak memory 216816 kb
Host smart-22b34bb0-4f63-4501-88c5-1f05935965df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192151115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1192151115
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.71433293
Short name T520
Test name
Test status
Simulation time 58866246 ps
CPU time 1.26 seconds
Started Aug 06 07:45:38 PM PDT 24
Finished Aug 06 07:45:40 PM PDT 24
Peak memory 217060 kb
Host smart-ae8d6708-3b9f-48c3-a375-fc86eaa4dcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71433293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.71433293
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.4008175013
Short name T407
Test name
Test status
Simulation time 40888192 ps
CPU time 1.07 seconds
Started Aug 06 07:45:43 PM PDT 24
Finished Aug 06 07:45:45 PM PDT 24
Peak memory 217124 kb
Host smart-00f433d4-21c4-438b-b136-52a8c97c27e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008175013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.4008175013
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.410488113
Short name T517
Test name
Test status
Simulation time 47577949 ps
CPU time 0.97 seconds
Started Aug 06 07:45:43 PM PDT 24
Finished Aug 06 07:45:44 PM PDT 24
Peak memory 217084 kb
Host smart-24485149-2eb4-4534-838b-5d4346ece070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410488113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.410488113
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1803698679
Short name T814
Test name
Test status
Simulation time 30270788 ps
CPU time 1.27 seconds
Started Aug 06 07:45:41 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 218200 kb
Host smart-c1281935-ed8e-4809-9678-f664f607a745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803698679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1803698679
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2551213703
Short name T826
Test name
Test status
Simulation time 335418011 ps
CPU time 3.1 seconds
Started Aug 06 07:45:44 PM PDT 24
Finished Aug 06 07:45:47 PM PDT 24
Peak memory 218596 kb
Host smart-feb6c390-82a7-4215-9f2f-88a8fbcce16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551213703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2551213703
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3282426685
Short name T174
Test name
Test status
Simulation time 85285313 ps
CPU time 1.15 seconds
Started Aug 06 07:42:37 PM PDT 24
Finished Aug 06 07:42:39 PM PDT 24
Peak memory 219196 kb
Host smart-8045b1b1-61aa-44f6-8d19-93fc72b07f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282426685 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3282426685
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1459212617
Short name T379
Test name
Test status
Simulation time 61422303 ps
CPU time 0.84 seconds
Started Aug 06 07:42:37 PM PDT 24
Finished Aug 06 07:42:39 PM PDT 24
Peak memory 206148 kb
Host smart-8424669d-9e4e-49c9-9d40-c417addb119b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459212617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1459212617
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3848796632
Short name T169
Test name
Test status
Simulation time 12980885 ps
CPU time 0.89 seconds
Started Aug 06 07:42:37 PM PDT 24
Finished Aug 06 07:42:37 PM PDT 24
Peak memory 215076 kb
Host smart-12a958e6-1f6f-47a0-ace5-ad7da29fca54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848796632 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3848796632
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.4084249623
Short name T880
Test name
Test status
Simulation time 101483137 ps
CPU time 1.09 seconds
Started Aug 06 07:42:29 PM PDT 24
Finished Aug 06 07:42:30 PM PDT 24
Peak memory 219304 kb
Host smart-5eebb502-d7e3-4218-8a07-765dc9d23b50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084249623 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.4084249623
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1472704120
Short name T778
Test name
Test status
Simulation time 25475533 ps
CPU time 1.2 seconds
Started Aug 06 07:42:34 PM PDT 24
Finished Aug 06 07:42:35 PM PDT 24
Peak memory 219456 kb
Host smart-f7498249-f1be-4815-86d7-f4e872bebd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472704120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1472704120
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.763950750
Short name T935
Test name
Test status
Simulation time 83756544 ps
CPU time 1.16 seconds
Started Aug 06 07:42:34 PM PDT 24
Finished Aug 06 07:42:36 PM PDT 24
Peak memory 216848 kb
Host smart-c60eaadd-d89f-42f6-b1d6-fa29ed7c19b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763950750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.763950750
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.5180338
Short name T373
Test name
Test status
Simulation time 22290664 ps
CPU time 1.16 seconds
Started Aug 06 07:42:37 PM PDT 24
Finished Aug 06 07:42:38 PM PDT 24
Peak memory 223596 kb
Host smart-7c5f2570-5065-4b4c-84a7-8e29c2adfee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5180338 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.5180338
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1952124118
Short name T915
Test name
Test status
Simulation time 31757454 ps
CPU time 0.94 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 214888 kb
Host smart-78a75b18-41b2-41fc-82d5-dabc0c45e144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952124118 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1952124118
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2088977000
Short name T863
Test name
Test status
Simulation time 216031359 ps
CPU time 4.3 seconds
Started Aug 06 07:42:34 PM PDT 24
Finished Aug 06 07:42:39 PM PDT 24
Peak memory 214872 kb
Host smart-686fdfda-cebc-42cd-9d74-7cb657bbfd39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088977000 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2088977000
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2929492821
Short name T21
Test name
Test status
Simulation time 72793089811 ps
CPU time 1764.56 seconds
Started Aug 06 07:42:34 PM PDT 24
Finished Aug 06 08:11:59 PM PDT 24
Peak memory 226376 kb
Host smart-ce2de481-935d-4a0c-85e9-0bb00b2a0c04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929492821 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2929492821
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.628743989
Short name T446
Test name
Test status
Simulation time 56763385 ps
CPU time 1.29 seconds
Started Aug 06 07:45:37 PM PDT 24
Finished Aug 06 07:45:39 PM PDT 24
Peak memory 216768 kb
Host smart-14be8e49-b75a-4c4c-be82-3c2f7c736954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628743989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.628743989
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.4294275402
Short name T929
Test name
Test status
Simulation time 129105174 ps
CPU time 1.11 seconds
Started Aug 06 07:45:40 PM PDT 24
Finished Aug 06 07:45:41 PM PDT 24
Peak memory 216956 kb
Host smart-78a885df-4e89-465f-9d47-539b7fde6fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294275402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4294275402
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3979167068
Short name T459
Test name
Test status
Simulation time 32457710 ps
CPU time 1.37 seconds
Started Aug 06 07:45:43 PM PDT 24
Finished Aug 06 07:45:45 PM PDT 24
Peak memory 217104 kb
Host smart-27a37dfa-7159-4f35-8f77-101a3ee3df28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979167068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3979167068
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3828600537
Short name T25
Test name
Test status
Simulation time 90023877 ps
CPU time 1.37 seconds
Started Aug 06 07:45:41 PM PDT 24
Finished Aug 06 07:45:42 PM PDT 24
Peak memory 217964 kb
Host smart-2dd693e9-7642-4e5e-98ad-a7d9fac2437b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828600537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3828600537
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3039482323
Short name T325
Test name
Test status
Simulation time 100025799 ps
CPU time 1.27 seconds
Started Aug 06 07:45:43 PM PDT 24
Finished Aug 06 07:45:45 PM PDT 24
Peak memory 219680 kb
Host smart-0c140013-caa5-4ec7-abf2-f5ca61927120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039482323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3039482323
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3668393936
Short name T949
Test name
Test status
Simulation time 65523147 ps
CPU time 1.53 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 218484 kb
Host smart-05e23cd5-6254-4e8f-87fd-82d0e45524a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668393936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3668393936
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1197872125
Short name T405
Test name
Test status
Simulation time 153097744 ps
CPU time 0.97 seconds
Started Aug 06 07:45:54 PM PDT 24
Finished Aug 06 07:45:55 PM PDT 24
Peak memory 218868 kb
Host smart-cda98dec-907f-4a58-9270-3763f47a7a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197872125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1197872125
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.62193716
Short name T59
Test name
Test status
Simulation time 70135350 ps
CPU time 1.36 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 219648 kb
Host smart-6a23067e-cdf2-4959-939d-60695b895c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62193716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.62193716
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.102686003
Short name T16
Test name
Test status
Simulation time 149677619 ps
CPU time 1.17 seconds
Started Aug 06 07:45:55 PM PDT 24
Finished Aug 06 07:45:56 PM PDT 24
Peak memory 218176 kb
Host smart-2f2aa2f9-cefb-48e4-80ba-be0c846ba9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102686003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.102686003
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.485069769
Short name T965
Test name
Test status
Simulation time 35658920 ps
CPU time 1.37 seconds
Started Aug 06 07:45:54 PM PDT 24
Finished Aug 06 07:45:56 PM PDT 24
Peak memory 218128 kb
Host smart-1a9bd9bf-ddd0-4478-8195-da84d5d9f4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485069769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.485069769
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3389865538
Short name T193
Test name
Test status
Simulation time 85033371 ps
CPU time 1.21 seconds
Started Aug 06 07:42:32 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 218264 kb
Host smart-0cd88705-2087-40c4-9d8d-4c4a7c5d7227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389865538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3389865538
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2369223615
Short name T38
Test name
Test status
Simulation time 17093963 ps
CPU time 0.95 seconds
Started Aug 06 07:42:45 PM PDT 24
Finished Aug 06 07:42:46 PM PDT 24
Peak memory 205588 kb
Host smart-d8835388-901c-428f-95f1-1e3c1a7f333d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369223615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2369223615
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2073917281
Short name T589
Test name
Test status
Simulation time 38392737 ps
CPU time 1.24 seconds
Started Aug 06 07:42:46 PM PDT 24
Finished Aug 06 07:42:47 PM PDT 24
Peak memory 216768 kb
Host smart-b1b39669-accc-4dad-8527-93fd994c60b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073917281 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2073917281
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2431214303
Short name T722
Test name
Test status
Simulation time 22893605 ps
CPU time 1 seconds
Started Aug 06 07:42:45 PM PDT 24
Finished Aug 06 07:42:46 PM PDT 24
Peak memory 219368 kb
Host smart-c69078db-02cf-4672-bb0d-2a28319ee55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431214303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2431214303
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3621444192
Short name T583
Test name
Test status
Simulation time 83897689 ps
CPU time 1.35 seconds
Started Aug 06 07:42:30 PM PDT 24
Finished Aug 06 07:42:32 PM PDT 24
Peak memory 218560 kb
Host smart-a05c9ecb-74e1-4ccc-927c-812809675eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621444192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3621444192
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_smoke.3091860186
Short name T890
Test name
Test status
Simulation time 17541744 ps
CPU time 0.96 seconds
Started Aug 06 07:42:36 PM PDT 24
Finished Aug 06 07:42:37 PM PDT 24
Peak memory 214880 kb
Host smart-365961df-6d99-4960-ae4d-ca4786af76cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091860186 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3091860186
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2682161338
Short name T813
Test name
Test status
Simulation time 246949503 ps
CPU time 4.8 seconds
Started Aug 06 07:42:37 PM PDT 24
Finished Aug 06 07:42:42 PM PDT 24
Peak memory 216728 kb
Host smart-b0a6bef1-25fb-4640-b454-e5c13fe41e4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682161338 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2682161338
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.498318999
Short name T444
Test name
Test status
Simulation time 40355040073 ps
CPU time 466.24 seconds
Started Aug 06 07:42:37 PM PDT 24
Finished Aug 06 07:50:24 PM PDT 24
Peak memory 223284 kb
Host smart-fc255fed-9c7e-47f6-9061-0cb4637a8d4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498318999 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.498318999
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.726836173
Short name T618
Test name
Test status
Simulation time 53583455 ps
CPU time 1.63 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 218152 kb
Host smart-ad2a0a01-96aa-43d0-9495-302dc77bb565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726836173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.726836173
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3900573359
Short name T921
Test name
Test status
Simulation time 66792780 ps
CPU time 1.67 seconds
Started Aug 06 07:45:53 PM PDT 24
Finished Aug 06 07:45:55 PM PDT 24
Peak memory 218348 kb
Host smart-125b7916-f830-4ddf-8bdc-ff198d850d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900573359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3900573359
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3685671548
Short name T833
Test name
Test status
Simulation time 46461944 ps
CPU time 1.76 seconds
Started Aug 06 07:45:53 PM PDT 24
Finished Aug 06 07:45:55 PM PDT 24
Peak memory 219356 kb
Host smart-87646e37-adbb-4d49-94c8-7ae4ab8898bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685671548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3685671548
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1264002859
Short name T912
Test name
Test status
Simulation time 85097415 ps
CPU time 1.56 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 218636 kb
Host smart-69649916-0ee2-4037-baff-2e6092e9bad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264002859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1264002859
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1091171679
Short name T740
Test name
Test status
Simulation time 62757092 ps
CPU time 1.26 seconds
Started Aug 06 07:45:53 PM PDT 24
Finished Aug 06 07:45:54 PM PDT 24
Peak memory 218384 kb
Host smart-6a23d74a-a784-4c16-9b3c-3fb2b10c75e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091171679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1091171679
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3621212766
Short name T624
Test name
Test status
Simulation time 53565954 ps
CPU time 1.36 seconds
Started Aug 06 07:45:53 PM PDT 24
Finished Aug 06 07:45:54 PM PDT 24
Peak memory 218376 kb
Host smart-1f62cb60-ac5a-402c-a9e2-9162f7fb9001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621212766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3621212766
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.266638447
Short name T483
Test name
Test status
Simulation time 200955333 ps
CPU time 1.08 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 217096 kb
Host smart-526bc669-ebfb-4444-9f34-9a33a2692896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266638447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.266638447
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1619836288
Short name T716
Test name
Test status
Simulation time 75801650 ps
CPU time 1.27 seconds
Started Aug 06 07:45:54 PM PDT 24
Finished Aug 06 07:45:55 PM PDT 24
Peak memory 219968 kb
Host smart-668c3a96-0f22-489d-ac30-4f73d1f37686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619836288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1619836288
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1711163296
Short name T761
Test name
Test status
Simulation time 74226076 ps
CPU time 1.46 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 217984 kb
Host smart-cf8ef866-b38e-400a-9ce4-80e7693adc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711163296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1711163296
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.473014577
Short name T286
Test name
Test status
Simulation time 81176959 ps
CPU time 1.15 seconds
Started Aug 06 07:42:45 PM PDT 24
Finished Aug 06 07:42:46 PM PDT 24
Peak memory 218972 kb
Host smart-759c8366-7b94-44e8-abe8-710d28e28357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473014577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.473014577
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3214595340
Short name T345
Test name
Test status
Simulation time 32438777 ps
CPU time 1.17 seconds
Started Aug 06 07:42:45 PM PDT 24
Finished Aug 06 07:42:46 PM PDT 24
Peak memory 214664 kb
Host smart-b3f08760-7685-41bf-808b-3dd9bb2ee43d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214595340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3214595340
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2904559737
Short name T932
Test name
Test status
Simulation time 16789029 ps
CPU time 0.83 seconds
Started Aug 06 07:42:46 PM PDT 24
Finished Aug 06 07:42:47 PM PDT 24
Peak memory 215940 kb
Host smart-41bbdf9d-8b0e-43ae-96e2-765e263506ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904559737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2904559737
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.62405157
Short name T723
Test name
Test status
Simulation time 19250078 ps
CPU time 0.95 seconds
Started Aug 06 07:42:47 PM PDT 24
Finished Aug 06 07:42:48 PM PDT 24
Peak memory 218012 kb
Host smart-ab03825a-8f01-4061-91f4-e11ddfbdfae4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62405157 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_dis
able_auto_req_mode.62405157
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_genbits.3175546565
Short name T266
Test name
Test status
Simulation time 105913060 ps
CPU time 1.36 seconds
Started Aug 06 07:42:46 PM PDT 24
Finished Aug 06 07:42:47 PM PDT 24
Peak memory 218656 kb
Host smart-8312a764-b11c-4889-a2da-a6329875cac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175546565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3175546565
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1982902595
Short name T84
Test name
Test status
Simulation time 22648681 ps
CPU time 1 seconds
Started Aug 06 07:42:47 PM PDT 24
Finished Aug 06 07:42:48 PM PDT 24
Peak memory 215112 kb
Host smart-07091f6f-f171-4fd4-9147-237764e66dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982902595 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1982902595
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.4011232556
Short name T413
Test name
Test status
Simulation time 47282148 ps
CPU time 0.9 seconds
Started Aug 06 07:42:45 PM PDT 24
Finished Aug 06 07:42:46 PM PDT 24
Peak memory 214892 kb
Host smart-81f31cb5-11c3-4635-8d60-36b066fd6475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011232556 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.4011232556
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.192009712
Short name T228
Test name
Test status
Simulation time 370251322 ps
CPU time 6.5 seconds
Started Aug 06 07:42:45 PM PDT 24
Finished Aug 06 07:42:52 PM PDT 24
Peak memory 217360 kb
Host smart-5ee6f4d5-8202-4599-861c-fd84ffaf24e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192009712 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.192009712
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2817232259
Short name T469
Test name
Test status
Simulation time 185952801716 ps
CPU time 444.39 seconds
Started Aug 06 07:42:44 PM PDT 24
Finished Aug 06 07:50:08 PM PDT 24
Peak memory 223444 kb
Host smart-09363715-c24a-4110-b86d-1bb4366ae812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817232259 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2817232259
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1427362355
Short name T875
Test name
Test status
Simulation time 69415919 ps
CPU time 1.34 seconds
Started Aug 06 07:45:57 PM PDT 24
Finished Aug 06 07:45:58 PM PDT 24
Peak memory 218500 kb
Host smart-a2010592-bfc4-4334-9f75-3c33630c9542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427362355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1427362355
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1205218681
Short name T969
Test name
Test status
Simulation time 36602430 ps
CPU time 1.39 seconds
Started Aug 06 07:45:59 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 217020 kb
Host smart-ed34f90b-bdf9-4e75-a06b-eb87569b18e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205218681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1205218681
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2482779445
Short name T653
Test name
Test status
Simulation time 68258964 ps
CPU time 1.53 seconds
Started Aug 06 07:45:56 PM PDT 24
Finished Aug 06 07:45:58 PM PDT 24
Peak memory 218408 kb
Host smart-5a1bde63-d6ad-4683-aeb1-1b6dd6d7bc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482779445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2482779445
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3493726590
Short name T358
Test name
Test status
Simulation time 76580112 ps
CPU time 1.2 seconds
Started Aug 06 07:45:54 PM PDT 24
Finished Aug 06 07:45:55 PM PDT 24
Peak memory 217008 kb
Host smart-898e4a72-aa47-4c0c-a3d5-380ebde3a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493726590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3493726590
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.4135630085
Short name T739
Test name
Test status
Simulation time 56598655 ps
CPU time 1.43 seconds
Started Aug 06 07:45:52 PM PDT 24
Finished Aug 06 07:45:54 PM PDT 24
Peak memory 219792 kb
Host smart-e879e1de-125e-457e-8afb-b113d76ca3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135630085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.4135630085
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3487720677
Short name T60
Test name
Test status
Simulation time 61717792 ps
CPU time 1.68 seconds
Started Aug 06 07:45:58 PM PDT 24
Finished Aug 06 07:46:00 PM PDT 24
Peak memory 218292 kb
Host smart-021cd3c0-5916-4926-aa2f-eaea8de4b6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487720677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3487720677
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2238532535
Short name T498
Test name
Test status
Simulation time 73116420 ps
CPU time 2.62 seconds
Started Aug 06 07:45:54 PM PDT 24
Finished Aug 06 07:45:57 PM PDT 24
Peak memory 219920 kb
Host smart-492e67d1-f406-4268-80c3-db69a85c2dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238532535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2238532535
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.183478751
Short name T859
Test name
Test status
Simulation time 838019730 ps
CPU time 6.12 seconds
Started Aug 06 07:45:53 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 219848 kb
Host smart-e0c9f740-e24f-4534-861b-01e1377e1bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183478751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.183478751
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3728170291
Short name T925
Test name
Test status
Simulation time 58572355 ps
CPU time 1.12 seconds
Started Aug 06 07:45:54 PM PDT 24
Finished Aug 06 07:45:55 PM PDT 24
Peak memory 218416 kb
Host smart-6522b532-8b79-4e84-9771-ce6159019c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728170291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3728170291
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1946601042
Short name T766
Test name
Test status
Simulation time 77505234 ps
CPU time 1.19 seconds
Started Aug 06 07:45:54 PM PDT 24
Finished Aug 06 07:45:56 PM PDT 24
Peak memory 216836 kb
Host smart-f832359e-099e-4616-9af2-8b17aceaed5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946601042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1946601042
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3314670359
Short name T654
Test name
Test status
Simulation time 169212050 ps
CPU time 1.22 seconds
Started Aug 06 07:40:53 PM PDT 24
Finished Aug 06 07:40:55 PM PDT 24
Peak memory 220260 kb
Host smart-bd6a8244-f558-4906-9932-d182bf35eb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314670359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3314670359
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3388123921
Short name T909
Test name
Test status
Simulation time 38896527 ps
CPU time 0.94 seconds
Started Aug 06 07:40:52 PM PDT 24
Finished Aug 06 07:40:53 PM PDT 24
Peak memory 206344 kb
Host smart-14c8c3b9-5a59-4ec5-9927-7fb267c15582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388123921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3388123921
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1673744919
Short name T465
Test name
Test status
Simulation time 13030021 ps
CPU time 0.9 seconds
Started Aug 06 07:40:52 PM PDT 24
Finished Aug 06 07:40:53 PM PDT 24
Peak memory 216104 kb
Host smart-d8ca4b4e-8283-4bdc-b8e3-daa5b7553ccb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673744919 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1673744919
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3254936728
Short name T349
Test name
Test status
Simulation time 184067205 ps
CPU time 1.28 seconds
Started Aug 06 07:40:53 PM PDT 24
Finished Aug 06 07:40:54 PM PDT 24
Peak memory 216716 kb
Host smart-a6953d5e-a757-42c6-9556-0fecdbd2f4dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254936728 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3254936728
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2219502444
Short name T176
Test name
Test status
Simulation time 35437905 ps
CPU time 0.85 seconds
Started Aug 06 07:40:55 PM PDT 24
Finished Aug 06 07:40:56 PM PDT 24
Peak memory 218252 kb
Host smart-3418d20b-a215-488f-a1ee-db1b6b5fe78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219502444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2219502444
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.561517816
Short name T387
Test name
Test status
Simulation time 42542644 ps
CPU time 1.42 seconds
Started Aug 06 07:40:35 PM PDT 24
Finished Aug 06 07:40:37 PM PDT 24
Peak memory 217948 kb
Host smart-4a24b39e-f710-496b-a22b-172dadcfea91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561517816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.561517816
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.997056280
Short name T644
Test name
Test status
Simulation time 34303112 ps
CPU time 0.86 seconds
Started Aug 06 07:40:34 PM PDT 24
Finished Aug 06 07:40:35 PM PDT 24
Peak memory 215148 kb
Host smart-8848aa98-6cb8-4893-95b0-e2cc48463b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997056280 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.997056280
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.177405102
Short name T54
Test name
Test status
Simulation time 18533785 ps
CPU time 1.04 seconds
Started Aug 06 07:40:36 PM PDT 24
Finished Aug 06 07:40:37 PM PDT 24
Peak memory 206708 kb
Host smart-7af49418-3ac5-4c0f-8c48-bc66877dc79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177405102 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.177405102
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.1219478170
Short name T980
Test name
Test status
Simulation time 20028757 ps
CPU time 0.88 seconds
Started Aug 06 07:40:35 PM PDT 24
Finished Aug 06 07:40:36 PM PDT 24
Peak memory 214944 kb
Host smart-2771af7a-b978-440d-bb4d-79ba068a18f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219478170 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1219478170
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.641279447
Short name T390
Test name
Test status
Simulation time 25416847 ps
CPU time 1.09 seconds
Started Aug 06 07:40:35 PM PDT 24
Finished Aug 06 07:40:37 PM PDT 24
Peak memory 214892 kb
Host smart-3a294eee-b3ef-4eba-8dd7-5cfb26c7e9ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641279447 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.641279447
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1867234774
Short name T226
Test name
Test status
Simulation time 84601110025 ps
CPU time 1894.87 seconds
Started Aug 06 07:40:38 PM PDT 24
Finished Aug 06 08:12:14 PM PDT 24
Peak memory 224752 kb
Host smart-7d062fe9-7568-4bee-b0e9-bbf6233e6768
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867234774 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1867234774
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.163690949
Short name T647
Test name
Test status
Simulation time 38564006 ps
CPU time 1.12 seconds
Started Aug 06 07:42:44 PM PDT 24
Finished Aug 06 07:42:45 PM PDT 24
Peak memory 219768 kb
Host smart-8cebde77-ef02-42d6-8bb2-3cbe1589ac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163690949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.163690949
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2525761860
Short name T702
Test name
Test status
Simulation time 170050285 ps
CPU time 0.85 seconds
Started Aug 06 07:42:47 PM PDT 24
Finished Aug 06 07:42:47 PM PDT 24
Peak memory 206328 kb
Host smart-0d4a7dc2-603e-41ab-a18b-57641eeb031d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525761860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2525761860
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.597646517
Short name T455
Test name
Test status
Simulation time 58227658 ps
CPU time 0.85 seconds
Started Aug 06 07:42:44 PM PDT 24
Finished Aug 06 07:42:45 PM PDT 24
Peak memory 215060 kb
Host smart-ca29f9c8-3c28-4dff-8e68-2a6c056c4817
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597646517 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.597646517
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2630656297
Short name T785
Test name
Test status
Simulation time 64524414 ps
CPU time 1.14 seconds
Started Aug 06 07:42:46 PM PDT 24
Finished Aug 06 07:42:47 PM PDT 24
Peak memory 215200 kb
Host smart-c3ee2380-6ad6-48dc-9a64-b31ca2e6d43d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630656297 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2630656297
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3051889372
Short name T44
Test name
Test status
Simulation time 26570088 ps
CPU time 0.99 seconds
Started Aug 06 07:42:46 PM PDT 24
Finished Aug 06 07:42:47 PM PDT 24
Peak memory 223644 kb
Host smart-c1c871c4-4825-4e53-9031-6f93438ca3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051889372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3051889372
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.415947817
Short name T877
Test name
Test status
Simulation time 87653989 ps
CPU time 1.06 seconds
Started Aug 06 07:42:43 PM PDT 24
Finished Aug 06 07:42:45 PM PDT 24
Peak memory 218264 kb
Host smart-5fc701da-e68d-44df-bf8e-1d29cfda16ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415947817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.415947817
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3424330684
Short name T361
Test name
Test status
Simulation time 24789914 ps
CPU time 1.15 seconds
Started Aug 06 07:42:46 PM PDT 24
Finished Aug 06 07:42:47 PM PDT 24
Peak memory 223704 kb
Host smart-52bc642f-67d5-4217-a2f0-d32e5d485289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424330684 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3424330684
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2582418535
Short name T848
Test name
Test status
Simulation time 32337299 ps
CPU time 0.84 seconds
Started Aug 06 07:42:44 PM PDT 24
Finished Aug 06 07:42:45 PM PDT 24
Peak memory 214888 kb
Host smart-89168b40-f303-4720-a161-fa2f1b25424f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582418535 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2582418535
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2627997566
Short name T556
Test name
Test status
Simulation time 299092538 ps
CPU time 3.17 seconds
Started Aug 06 07:42:45 PM PDT 24
Finished Aug 06 07:42:48 PM PDT 24
Peak memory 216788 kb
Host smart-caeb83b5-c390-403c-8aff-2b0fc7dbf690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627997566 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2627997566
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2072128701
Short name T745
Test name
Test status
Simulation time 11924988667 ps
CPU time 256.39 seconds
Started Aug 06 07:42:44 PM PDT 24
Finished Aug 06 07:47:01 PM PDT 24
Peak memory 221920 kb
Host smart-362bfd23-61d5-4194-809c-6ab068713fdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072128701 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2072128701
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1831148629
Short name T173
Test name
Test status
Simulation time 77427166 ps
CPU time 1.08 seconds
Started Aug 06 07:42:59 PM PDT 24
Finished Aug 06 07:43:00 PM PDT 24
Peak memory 218368 kb
Host smart-497e457d-1450-4fe0-ab3c-28887aebd508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831148629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1831148629
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2678030987
Short name T866
Test name
Test status
Simulation time 15843794 ps
CPU time 0.86 seconds
Started Aug 06 07:42:58 PM PDT 24
Finished Aug 06 07:42:59 PM PDT 24
Peak memory 206288 kb
Host smart-cf63bcf1-facc-40db-a160-cb27c94446b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678030987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2678030987
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3003304755
Short name T466
Test name
Test status
Simulation time 10657911 ps
CPU time 0.85 seconds
Started Aug 06 07:42:59 PM PDT 24
Finished Aug 06 07:43:00 PM PDT 24
Peak memory 215132 kb
Host smart-10e1d83e-853c-4d58-97ad-07574eae6e73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003304755 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3003304755
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3972617091
Short name T267
Test name
Test status
Simulation time 27990677 ps
CPU time 1.17 seconds
Started Aug 06 07:42:59 PM PDT 24
Finished Aug 06 07:43:00 PM PDT 24
Peak memory 218076 kb
Host smart-de540546-7bf1-4443-9ad9-722d17cb8d49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972617091 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3972617091
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3419509718
Short name T979
Test name
Test status
Simulation time 31581809 ps
CPU time 0.93 seconds
Started Aug 06 07:42:58 PM PDT 24
Finished Aug 06 07:42:59 PM PDT 24
Peak memory 223628 kb
Host smart-e77c1ea2-571b-41e2-bb27-c169568247ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419509718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3419509718
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2613086907
Short name T603
Test name
Test status
Simulation time 226307658 ps
CPU time 3.01 seconds
Started Aug 06 07:42:59 PM PDT 24
Finished Aug 06 07:43:02 PM PDT 24
Peak memory 219596 kb
Host smart-4a77a16b-59db-4643-a70d-9994da7fdaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613086907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2613086907
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1108264758
Short name T505
Test name
Test status
Simulation time 22189995 ps
CPU time 1.08 seconds
Started Aug 06 07:43:00 PM PDT 24
Finished Aug 06 07:43:01 PM PDT 24
Peak memory 214908 kb
Host smart-e214cf40-88a3-466b-903b-1e46084d90d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108264758 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1108264758
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3585083796
Short name T350
Test name
Test status
Simulation time 16865600 ps
CPU time 0.97 seconds
Started Aug 06 07:42:44 PM PDT 24
Finished Aug 06 07:42:45 PM PDT 24
Peak memory 214944 kb
Host smart-22d5c358-bd32-4a91-82db-d20d305d96b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585083796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3585083796
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2064825729
Short name T439
Test name
Test status
Simulation time 230789048 ps
CPU time 2.77 seconds
Started Aug 06 07:43:01 PM PDT 24
Finished Aug 06 07:43:03 PM PDT 24
Peak memory 219084 kb
Host smart-2d031cf7-0762-42c5-95ca-250bcd175691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064825729 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2064825729
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3659671200
Short name T412
Test name
Test status
Simulation time 144638811720 ps
CPU time 659.03 seconds
Started Aug 06 07:43:00 PM PDT 24
Finished Aug 06 07:53:59 PM PDT 24
Peak memory 223364 kb
Host smart-26fc469e-5e05-43f8-bf01-bb40beb9a8bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659671200 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3659671200
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.4131284382
Short name T554
Test name
Test status
Simulation time 41346591 ps
CPU time 1.28 seconds
Started Aug 06 07:42:59 PM PDT 24
Finished Aug 06 07:43:00 PM PDT 24
Peak memory 215316 kb
Host smart-dc82a838-e89e-4c2e-a58b-dfb653164a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131284382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.4131284382
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2704534163
Short name T370
Test name
Test status
Simulation time 42531975 ps
CPU time 0.83 seconds
Started Aug 06 07:43:12 PM PDT 24
Finished Aug 06 07:43:13 PM PDT 24
Peak memory 206328 kb
Host smart-f84494eb-ec53-4e66-8c0b-f57a771dcd86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704534163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2704534163
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.4130313873
Short name T242
Test name
Test status
Simulation time 13183166 ps
CPU time 0.89 seconds
Started Aug 06 07:43:04 PM PDT 24
Finished Aug 06 07:43:05 PM PDT 24
Peak memory 216152 kb
Host smart-dbb60eb2-6956-4a08-83d5-367de3ca035b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130313873 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.4130313873
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3140641957
Short name T164
Test name
Test status
Simulation time 64496155 ps
CPU time 1.24 seconds
Started Aug 06 07:42:59 PM PDT 24
Finished Aug 06 07:43:00 PM PDT 24
Peak memory 216724 kb
Host smart-0664cc1f-9674-4606-8453-67511dae0476
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140641957 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3140641957
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1906587685
Short name T473
Test name
Test status
Simulation time 21762864 ps
CPU time 1.19 seconds
Started Aug 06 07:43:01 PM PDT 24
Finished Aug 06 07:43:02 PM PDT 24
Peak memory 223712 kb
Host smart-2258b17c-40fc-439e-8f10-7e153831b168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906587685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1906587685
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.4205073925
Short name T539
Test name
Test status
Simulation time 68074358 ps
CPU time 1.63 seconds
Started Aug 06 07:43:00 PM PDT 24
Finished Aug 06 07:43:01 PM PDT 24
Peak memory 217996 kb
Host smart-7bdd13ff-2ec0-4483-b118-140ad106cff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205073925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.4205073925
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1211479287
Short name T754
Test name
Test status
Simulation time 23267654 ps
CPU time 0.91 seconds
Started Aug 06 07:42:58 PM PDT 24
Finished Aug 06 07:42:59 PM PDT 24
Peak memory 215644 kb
Host smart-485fba3b-cd6f-4c11-a900-a981673fb39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211479287 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1211479287
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.4085100477
Short name T467
Test name
Test status
Simulation time 51564556 ps
CPU time 0.91 seconds
Started Aug 06 07:43:06 PM PDT 24
Finished Aug 06 07:43:07 PM PDT 24
Peak memory 214884 kb
Host smart-c0832699-8646-44d5-96bc-1f5256883498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085100477 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.4085100477
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3892049393
Short name T796
Test name
Test status
Simulation time 149350409 ps
CPU time 3.35 seconds
Started Aug 06 07:43:01 PM PDT 24
Finished Aug 06 07:43:04 PM PDT 24
Peak memory 215088 kb
Host smart-17be3e2c-a5fa-49d6-bda3-fe3f191bc27d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892049393 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3892049393
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2494000139
Short name T629
Test name
Test status
Simulation time 155500001037 ps
CPU time 1022.05 seconds
Started Aug 06 07:43:13 PM PDT 24
Finished Aug 06 08:00:15 PM PDT 24
Peak memory 222504 kb
Host smart-60e08829-484b-4f03-9d63-a9835d8e792e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494000139 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2494000139
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.18514347
Short name T699
Test name
Test status
Simulation time 32815662 ps
CPU time 1.1 seconds
Started Aug 06 07:43:06 PM PDT 24
Finished Aug 06 07:43:08 PM PDT 24
Peak memory 219520 kb
Host smart-725901e0-ac17-4be7-b70f-c117c879490f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18514347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.18514347
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3683668676
Short name T721
Test name
Test status
Simulation time 19609477 ps
CPU time 0.79 seconds
Started Aug 06 07:42:58 PM PDT 24
Finished Aug 06 07:42:59 PM PDT 24
Peak memory 206492 kb
Host smart-a07ed80d-29e8-4878-9650-f211a4f55294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683668676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3683668676
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.282702032
Short name T606
Test name
Test status
Simulation time 379841777 ps
CPU time 1 seconds
Started Aug 06 07:43:06 PM PDT 24
Finished Aug 06 07:43:07 PM PDT 24
Peak memory 218056 kb
Host smart-ae24db43-d8e4-420d-baf1-35353bf986a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282702032 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.282702032
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1098477735
Short name T55
Test name
Test status
Simulation time 38627800 ps
CPU time 1 seconds
Started Aug 06 07:43:01 PM PDT 24
Finished Aug 06 07:43:02 PM PDT 24
Peak memory 218684 kb
Host smart-d1b112dd-3d0a-486b-a8d2-c20c1416b845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098477735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1098477735
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2833089920
Short name T431
Test name
Test status
Simulation time 34722016 ps
CPU time 1.36 seconds
Started Aug 06 07:42:59 PM PDT 24
Finished Aug 06 07:43:01 PM PDT 24
Peak memory 216928 kb
Host smart-44eeb8d7-d2fb-444d-aa09-c9ba5e817ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833089920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2833089920
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2501401834
Short name T86
Test name
Test status
Simulation time 25595082 ps
CPU time 0.95 seconds
Started Aug 06 07:42:59 PM PDT 24
Finished Aug 06 07:43:00 PM PDT 24
Peak memory 215620 kb
Host smart-84673355-eb7d-4d4b-b308-818a65d46254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501401834 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2501401834
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.105984592
Short name T580
Test name
Test status
Simulation time 40922951 ps
CPU time 0.86 seconds
Started Aug 06 07:43:00 PM PDT 24
Finished Aug 06 07:43:01 PM PDT 24
Peak memory 214892 kb
Host smart-e6d104e2-366c-4e8c-8c1f-0471d5b5f636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105984592 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.105984592
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.126129194
Short name T784
Test name
Test status
Simulation time 363696365 ps
CPU time 3.87 seconds
Started Aug 06 07:43:13 PM PDT 24
Finished Aug 06 07:43:17 PM PDT 24
Peak memory 214936 kb
Host smart-8fb2ab16-b3c8-44de-a421-367e3f4d4a30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126129194 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.126129194
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3288939220
Short name T224
Test name
Test status
Simulation time 124678609366 ps
CPU time 737.63 seconds
Started Aug 06 07:43:01 PM PDT 24
Finished Aug 06 07:55:18 PM PDT 24
Peak memory 219504 kb
Host smart-14e6ef48-ff5b-4a61-91ee-6aa54050ce9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288939220 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3288939220
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3004646109
Short name T296
Test name
Test status
Simulation time 28078189 ps
CPU time 1.25 seconds
Started Aug 06 07:43:11 PM PDT 24
Finished Aug 06 07:43:12 PM PDT 24
Peak memory 220476 kb
Host smart-58142414-a2a9-4c38-bda8-c720de3913db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004646109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3004646109
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1139675094
Short name T708
Test name
Test status
Simulation time 40495090 ps
CPU time 0.94 seconds
Started Aug 06 07:43:12 PM PDT 24
Finished Aug 06 07:43:13 PM PDT 24
Peak memory 214964 kb
Host smart-456aeec8-875f-4211-a548-3d61bfc9e85d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139675094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1139675094
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1067766966
Short name T896
Test name
Test status
Simulation time 23394427 ps
CPU time 0.88 seconds
Started Aug 06 07:43:01 PM PDT 24
Finished Aug 06 07:43:02 PM PDT 24
Peak memory 218732 kb
Host smart-5f9d8662-9624-4a51-9e92-37bb1cd43b73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067766966 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1067766966
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3782977452
Short name T126
Test name
Test status
Simulation time 88822330 ps
CPU time 1.19 seconds
Started Aug 06 07:43:13 PM PDT 24
Finished Aug 06 07:43:15 PM PDT 24
Peak memory 216840 kb
Host smart-88ded050-cb13-4966-8d2a-e733370de5cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782977452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3782977452
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4163138506
Short name T920
Test name
Test status
Simulation time 31168497 ps
CPU time 0.84 seconds
Started Aug 06 07:42:58 PM PDT 24
Finished Aug 06 07:42:59 PM PDT 24
Peak memory 218312 kb
Host smart-254d641b-0925-462e-943c-9e10e6a62657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163138506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4163138506
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.446184939
Short name T566
Test name
Test status
Simulation time 51110381 ps
CPU time 1.48 seconds
Started Aug 06 07:43:12 PM PDT 24
Finished Aug 06 07:43:14 PM PDT 24
Peak memory 218264 kb
Host smart-a3a691b2-076f-4d60-91ca-7fe5cc865994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446184939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.446184939
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.306490462
Short name T384
Test name
Test status
Simulation time 20888564 ps
CPU time 1.07 seconds
Started Aug 06 07:43:00 PM PDT 24
Finished Aug 06 07:43:01 PM PDT 24
Peak memory 215216 kb
Host smart-45f51313-edbf-43e6-99b1-cdb2dac159a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306490462 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.306490462
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3094094966
Short name T355
Test name
Test status
Simulation time 153302658 ps
CPU time 0.91 seconds
Started Aug 06 07:43:04 PM PDT 24
Finished Aug 06 07:43:05 PM PDT 24
Peak memory 214916 kb
Host smart-481a0cba-1819-46f5-8946-76c0c66a5623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094094966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3094094966
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1970395500
Short name T976
Test name
Test status
Simulation time 173060963 ps
CPU time 2.49 seconds
Started Aug 06 07:42:59 PM PDT 24
Finished Aug 06 07:43:02 PM PDT 24
Peak memory 217036 kb
Host smart-fd513806-5da1-4831-9289-e8b64cab58ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970395500 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1970395500
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2255031678
Short name T457
Test name
Test status
Simulation time 91689939060 ps
CPU time 2092.12 seconds
Started Aug 06 07:43:02 PM PDT 24
Finished Aug 06 08:17:54 PM PDT 24
Peak memory 226132 kb
Host smart-66419551-7d32-47ac-afd5-4de91dbb96c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255031678 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2255031678
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1762989771
Short name T649
Test name
Test status
Simulation time 101649853 ps
CPU time 1.15 seconds
Started Aug 06 07:43:02 PM PDT 24
Finished Aug 06 07:43:04 PM PDT 24
Peak memory 217864 kb
Host smart-ac855d35-f62e-48e8-a5b4-28e5506c1197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762989771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1762989771
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2012406795
Short name T812
Test name
Test status
Simulation time 32108961 ps
CPU time 1.19 seconds
Started Aug 06 07:43:02 PM PDT 24
Finished Aug 06 07:43:04 PM PDT 24
Peak memory 206248 kb
Host smart-42866679-a3d5-46ad-8acb-7dc8acb2bf34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012406795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2012406795
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2959704807
Short name T180
Test name
Test status
Simulation time 35728625 ps
CPU time 0.94 seconds
Started Aug 06 07:43:04 PM PDT 24
Finished Aug 06 07:43:05 PM PDT 24
Peak memory 216248 kb
Host smart-87ac03ed-356c-4aae-a77d-5a676a1b68f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959704807 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2959704807
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3387670639
Short name T104
Test name
Test status
Simulation time 52311327 ps
CPU time 1.15 seconds
Started Aug 06 07:43:07 PM PDT 24
Finished Aug 06 07:43:08 PM PDT 24
Peak memory 219156 kb
Host smart-df290109-2a8d-477b-ab45-6086911b22d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387670639 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3387670639
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1427208088
Short name T879
Test name
Test status
Simulation time 21386841 ps
CPU time 1.25 seconds
Started Aug 06 07:43:12 PM PDT 24
Finished Aug 06 07:43:14 PM PDT 24
Peak memory 223792 kb
Host smart-99d5c769-1ab7-47ca-b587-4aa120e5ed01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427208088 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1427208088
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2778462604
Short name T307
Test name
Test status
Simulation time 111018906 ps
CPU time 1.58 seconds
Started Aug 06 07:42:59 PM PDT 24
Finished Aug 06 07:43:00 PM PDT 24
Peak memory 218340 kb
Host smart-5f99c1d8-99e8-44f9-9f0d-821ef64af9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778462604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2778462604
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1367341256
Short name T587
Test name
Test status
Simulation time 34687042 ps
CPU time 0.88 seconds
Started Aug 06 07:43:12 PM PDT 24
Finished Aug 06 07:43:13 PM PDT 24
Peak memory 214936 kb
Host smart-734b4d5d-5498-4c59-8fe8-1ad4e8da7e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367341256 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1367341256
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.4285547203
Short name T950
Test name
Test status
Simulation time 19233801 ps
CPU time 1 seconds
Started Aug 06 07:43:05 PM PDT 24
Finished Aug 06 07:43:06 PM PDT 24
Peak memory 214916 kb
Host smart-adf59e21-7ba8-493a-88aa-0bb1c66e0b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285547203 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.4285547203
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3559691092
Short name T544
Test name
Test status
Simulation time 331793591 ps
CPU time 6.25 seconds
Started Aug 06 07:43:01 PM PDT 24
Finished Aug 06 07:43:07 PM PDT 24
Peak memory 214952 kb
Host smart-a75fd49e-802f-4698-b512-762cd34aceb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559691092 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3559691092
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.815949547
Short name T584
Test name
Test status
Simulation time 403126506668 ps
CPU time 2376.8 seconds
Started Aug 06 07:42:59 PM PDT 24
Finished Aug 06 08:22:36 PM PDT 24
Peak memory 230708 kb
Host smart-5f0193f5-dccf-4caf-9bd8-01fae0cf1515
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815949547 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.815949547
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.377504122
Short name T842
Test name
Test status
Simulation time 205099698 ps
CPU time 1.11 seconds
Started Aug 06 07:43:17 PM PDT 24
Finished Aug 06 07:43:18 PM PDT 24
Peak memory 220304 kb
Host smart-34bed7f3-1db5-4543-b054-b9fc5e868979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377504122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.377504122
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3217769510
Short name T461
Test name
Test status
Simulation time 73138101 ps
CPU time 0.84 seconds
Started Aug 06 07:43:20 PM PDT 24
Finished Aug 06 07:43:21 PM PDT 24
Peak memory 206220 kb
Host smart-a8072c5f-4bf0-48df-af7f-482f0aa83df2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217769510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3217769510
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3059787944
Short name T118
Test name
Test status
Simulation time 17463076 ps
CPU time 0.93 seconds
Started Aug 06 07:43:17 PM PDT 24
Finished Aug 06 07:43:19 PM PDT 24
Peak memory 216456 kb
Host smart-2b6304f9-473a-4bd9-9f98-7439e81245ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059787944 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3059787944
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.340787807
Short name T470
Test name
Test status
Simulation time 109160132 ps
CPU time 1.17 seconds
Started Aug 06 07:43:18 PM PDT 24
Finished Aug 06 07:43:19 PM PDT 24
Peak memory 216756 kb
Host smart-73510663-7279-48e5-9db3-4c580a27aabf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340787807 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.340787807
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2815120764
Short name T542
Test name
Test status
Simulation time 30964189 ps
CPU time 0.86 seconds
Started Aug 06 07:43:21 PM PDT 24
Finished Aug 06 07:43:22 PM PDT 24
Peak memory 217984 kb
Host smart-c9d26284-4c79-4333-a90f-1b21ed2e98d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815120764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2815120764
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.85472564
Short name T511
Test name
Test status
Simulation time 52084440 ps
CPU time 1.14 seconds
Started Aug 06 07:43:00 PM PDT 24
Finished Aug 06 07:43:01 PM PDT 24
Peak memory 216864 kb
Host smart-1f9c6d49-1b4f-4e6e-b2b6-8e4413d8efbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85472564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.85472564
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3628574397
Short name T73
Test name
Test status
Simulation time 35140989 ps
CPU time 0.86 seconds
Started Aug 06 07:43:06 PM PDT 24
Finished Aug 06 07:43:07 PM PDT 24
Peak memory 215468 kb
Host smart-851912fc-5665-425d-b7c6-7b955bb3dfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628574397 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3628574397
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.966496132
Short name T422
Test name
Test status
Simulation time 20670090 ps
CPU time 1.04 seconds
Started Aug 06 07:43:02 PM PDT 24
Finished Aug 06 07:43:03 PM PDT 24
Peak memory 214908 kb
Host smart-b2ad3b30-678e-4712-82fd-051a006d460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966496132 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.966496132
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3610280673
Short name T436
Test name
Test status
Simulation time 706065694 ps
CPU time 4.22 seconds
Started Aug 06 07:43:00 PM PDT 24
Finished Aug 06 07:43:05 PM PDT 24
Peak memory 216756 kb
Host smart-6a84c8b5-23e4-404f-8ce1-eaec40fa66e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610280673 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3610280673
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1384902477
Short name T219
Test name
Test status
Simulation time 42834909714 ps
CPU time 448.21 seconds
Started Aug 06 07:43:07 PM PDT 24
Finished Aug 06 07:50:35 PM PDT 24
Peak memory 218380 kb
Host smart-01a521e2-3c1b-488e-8ec3-15f91fe8df0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384902477 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1384902477
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1437161737
Short name T689
Test name
Test status
Simulation time 242320016 ps
CPU time 1.15 seconds
Started Aug 06 07:43:19 PM PDT 24
Finished Aug 06 07:43:20 PM PDT 24
Peak memory 219592 kb
Host smart-4f1a11ed-5a71-4639-ae35-91a16c3daed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437161737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1437161737
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3261758460
Short name T843
Test name
Test status
Simulation time 79933385 ps
CPU time 0.84 seconds
Started Aug 06 07:43:18 PM PDT 24
Finished Aug 06 07:43:19 PM PDT 24
Peak memory 214700 kb
Host smart-8183a946-fca8-4d95-a3ac-95b1452e32a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261758460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3261758460
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3209725954
Short name T974
Test name
Test status
Simulation time 18315709 ps
CPU time 0.85 seconds
Started Aug 06 07:43:17 PM PDT 24
Finished Aug 06 07:43:18 PM PDT 24
Peak memory 215096 kb
Host smart-1da3df54-4734-4bdb-9cf6-9afbb17fce4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209725954 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3209725954
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1275981764
Short name T150
Test name
Test status
Simulation time 50189166 ps
CPU time 1.08 seconds
Started Aug 06 07:43:24 PM PDT 24
Finished Aug 06 07:43:25 PM PDT 24
Peak memory 219412 kb
Host smart-0cea0bd5-d9f4-460c-a1d9-752cc27b0283
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275981764 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1275981764
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1827269353
Short name T666
Test name
Test status
Simulation time 53319889 ps
CPU time 0.85 seconds
Started Aug 06 07:43:19 PM PDT 24
Finished Aug 06 07:43:20 PM PDT 24
Peak memory 218148 kb
Host smart-8dc34d18-d0f5-4de6-89d6-00cb69576ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827269353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1827269353
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1698583510
Short name T572
Test name
Test status
Simulation time 44249778 ps
CPU time 1.47 seconds
Started Aug 06 07:43:19 PM PDT 24
Finished Aug 06 07:43:21 PM PDT 24
Peak memory 218464 kb
Host smart-458b46d7-4952-4f0c-abac-5da49f08902c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698583510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1698583510
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1453361987
Short name T363
Test name
Test status
Simulation time 21157933 ps
CPU time 1.03 seconds
Started Aug 06 07:43:19 PM PDT 24
Finished Aug 06 07:43:20 PM PDT 24
Peak memory 215100 kb
Host smart-6fe6f21e-6299-472b-bf9a-4b67b6c023eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453361987 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1453361987
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3284377363
Short name T602
Test name
Test status
Simulation time 38620284 ps
CPU time 0.87 seconds
Started Aug 06 07:43:21 PM PDT 24
Finished Aug 06 07:43:22 PM PDT 24
Peak memory 214916 kb
Host smart-085c3837-c926-46c2-b33f-af9197ab35c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284377363 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3284377363
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.953632276
Short name T801
Test name
Test status
Simulation time 178940580 ps
CPU time 1.47 seconds
Started Aug 06 07:43:20 PM PDT 24
Finished Aug 06 07:43:21 PM PDT 24
Peak memory 214860 kb
Host smart-1b64ea7d-fad0-4257-997c-df568ce92d83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953632276 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.953632276
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3890690965
Short name T874
Test name
Test status
Simulation time 89333484408 ps
CPU time 1043.16 seconds
Started Aug 06 07:43:19 PM PDT 24
Finished Aug 06 08:00:43 PM PDT 24
Peak memory 221380 kb
Host smart-70fcd4fa-bd84-4181-910d-d46285111a65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890690965 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3890690965
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert_test.3812251684
Short name T832
Test name
Test status
Simulation time 81178358 ps
CPU time 0.88 seconds
Started Aug 06 07:43:20 PM PDT 24
Finished Aug 06 07:43:21 PM PDT 24
Peak memory 214708 kb
Host smart-60762d78-2117-4bb4-a405-13fba7fe25c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812251684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3812251684
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3546553774
Short name T928
Test name
Test status
Simulation time 110776809 ps
CPU time 0.82 seconds
Started Aug 06 07:43:18 PM PDT 24
Finished Aug 06 07:43:19 PM PDT 24
Peak memory 215108 kb
Host smart-55e8e7b5-e3a6-4f8a-a888-9f9ede6eb7f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546553774 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3546553774
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1855523140
Short name T543
Test name
Test status
Simulation time 24461019 ps
CPU time 1.07 seconds
Started Aug 06 07:43:21 PM PDT 24
Finished Aug 06 07:43:22 PM PDT 24
Peak memory 219364 kb
Host smart-182b9016-6c10-43eb-8843-5687db0487d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855523140 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1855523140
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1136249163
Short name T452
Test name
Test status
Simulation time 31935000 ps
CPU time 0.88 seconds
Started Aug 06 07:43:21 PM PDT 24
Finished Aug 06 07:43:21 PM PDT 24
Peak memory 218292 kb
Host smart-a68cb181-e24a-4880-950a-d8fb0cbd5db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136249163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1136249163
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1022275555
Short name T789
Test name
Test status
Simulation time 64618473 ps
CPU time 1.01 seconds
Started Aug 06 07:43:20 PM PDT 24
Finished Aug 06 07:43:21 PM PDT 24
Peak memory 216960 kb
Host smart-940a99da-dc4f-41b8-9941-99890c773178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022275555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1022275555
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3304424680
Short name T868
Test name
Test status
Simulation time 55731910 ps
CPU time 0.88 seconds
Started Aug 06 07:43:18 PM PDT 24
Finished Aug 06 07:43:19 PM PDT 24
Peak memory 214844 kb
Host smart-e6f9a673-12f4-4395-96b2-10bccfaa9a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304424680 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3304424680
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.537562805
Short name T386
Test name
Test status
Simulation time 19913708 ps
CPU time 1.01 seconds
Started Aug 06 07:43:22 PM PDT 24
Finished Aug 06 07:43:23 PM PDT 24
Peak memory 214904 kb
Host smart-01538df4-0df1-4cbb-a9cf-3439b204f483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537562805 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.537562805
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3822032264
Short name T562
Test name
Test status
Simulation time 26983118878 ps
CPU time 604.6 seconds
Started Aug 06 07:43:19 PM PDT 24
Finished Aug 06 07:53:24 PM PDT 24
Peak memory 219792 kb
Host smart-89ccf6da-b166-44f1-96df-538da6795e99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822032264 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3822032264
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2324193047
Short name T453
Test name
Test status
Simulation time 23874499 ps
CPU time 1.16 seconds
Started Aug 06 07:43:19 PM PDT 24
Finished Aug 06 07:43:20 PM PDT 24
Peak memory 217980 kb
Host smart-85ff6263-33cd-4227-87d4-5af885ba9b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324193047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2324193047
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3543956736
Short name T472
Test name
Test status
Simulation time 24964344 ps
CPU time 0.89 seconds
Started Aug 06 07:43:18 PM PDT 24
Finished Aug 06 07:43:19 PM PDT 24
Peak memory 206220 kb
Host smart-04111a96-50ab-4492-ac73-df8aa328765d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543956736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3543956736
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1144012321
Short name T196
Test name
Test status
Simulation time 42640334 ps
CPU time 0.88 seconds
Started Aug 06 07:43:23 PM PDT 24
Finished Aug 06 07:43:24 PM PDT 24
Peak memory 216176 kb
Host smart-f7bea821-1501-4501-8215-631a418c31b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144012321 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1144012321
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.775874727
Short name T821
Test name
Test status
Simulation time 27240242 ps
CPU time 1.07 seconds
Started Aug 06 07:43:21 PM PDT 24
Finished Aug 06 07:43:22 PM PDT 24
Peak memory 218092 kb
Host smart-dc8890af-f7b5-4911-b5fe-a8cf49bbd08d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775874727 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.775874727
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1541071526
Short name T129
Test name
Test status
Simulation time 30620790 ps
CPU time 1.25 seconds
Started Aug 06 07:43:18 PM PDT 24
Finished Aug 06 07:43:20 PM PDT 24
Peak memory 219740 kb
Host smart-bcdfbcd0-0e6d-42d6-9e34-3e80b8caf3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541071526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1541071526
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2549650561
Short name T378
Test name
Test status
Simulation time 53773504 ps
CPU time 1.31 seconds
Started Aug 06 07:43:18 PM PDT 24
Finished Aug 06 07:43:20 PM PDT 24
Peak memory 219148 kb
Host smart-ced8c869-ebaf-4b0c-a06f-6a9a06638aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549650561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2549650561
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1808319792
Short name T600
Test name
Test status
Simulation time 84045384 ps
CPU time 0.87 seconds
Started Aug 06 07:43:17 PM PDT 24
Finished Aug 06 07:43:18 PM PDT 24
Peak memory 214920 kb
Host smart-835af8aa-3cbc-4c27-ac5c-9e072652377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808319792 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1808319792
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.672773059
Short name T630
Test name
Test status
Simulation time 58015265 ps
CPU time 0.98 seconds
Started Aug 06 07:43:20 PM PDT 24
Finished Aug 06 07:43:21 PM PDT 24
Peak memory 214840 kb
Host smart-284c0c16-ff13-4e35-a641-ef46ef973cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672773059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.672773059
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.363346617
Short name T468
Test name
Test status
Simulation time 432256563 ps
CPU time 2.85 seconds
Started Aug 06 07:43:19 PM PDT 24
Finished Aug 06 07:43:22 PM PDT 24
Peak memory 216796 kb
Host smart-13815860-35a1-4082-8452-7b2c193180e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363346617 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.363346617
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2377180571
Short name T443
Test name
Test status
Simulation time 427652482179 ps
CPU time 1011.39 seconds
Started Aug 06 07:43:20 PM PDT 24
Finished Aug 06 08:00:12 PM PDT 24
Peak memory 223400 kb
Host smart-16529c57-477e-45ab-9598-53bf1f159466
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377180571 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2377180571
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2086565486
Short name T166
Test name
Test status
Simulation time 27389695 ps
CPU time 1.27 seconds
Started Aug 06 07:40:53 PM PDT 24
Finished Aug 06 07:40:54 PM PDT 24
Peak memory 218760 kb
Host smart-270f7efc-e4fd-4f48-a63e-37f84d14b7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086565486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2086565486
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3587309859
Short name T954
Test name
Test status
Simulation time 24100516 ps
CPU time 0.9 seconds
Started Aug 06 07:40:53 PM PDT 24
Finished Aug 06 07:40:54 PM PDT 24
Peak memory 206356 kb
Host smart-860ce86a-3792-40a5-8fdd-596ce3845d68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587309859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3587309859
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2564949085
Short name T591
Test name
Test status
Simulation time 29494047 ps
CPU time 0.83 seconds
Started Aug 06 07:40:56 PM PDT 24
Finished Aug 06 07:40:57 PM PDT 24
Peak memory 215908 kb
Host smart-00d6fc0c-8678-4e61-9b36-050a2a66c142
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564949085 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2564949085
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2313106939
Short name T835
Test name
Test status
Simulation time 112311803 ps
CPU time 1.2 seconds
Started Aug 06 07:40:54 PM PDT 24
Finished Aug 06 07:40:56 PM PDT 24
Peak memory 216828 kb
Host smart-5a5cb335-9435-46fd-ab1f-4e4c6210203f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313106939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2313106939
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2721501750
Short name T194
Test name
Test status
Simulation time 36708289 ps
CPU time 0.86 seconds
Started Aug 06 07:40:53 PM PDT 24
Finished Aug 06 07:40:54 PM PDT 24
Peak memory 218200 kb
Host smart-34eb11e2-0df5-494f-ac0b-a924458f3c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721501750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2721501750
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3271340123
Short name T626
Test name
Test status
Simulation time 236576363 ps
CPU time 1.49 seconds
Started Aug 06 07:40:54 PM PDT 24
Finished Aug 06 07:40:55 PM PDT 24
Peak memory 219428 kb
Host smart-4741415d-e9c4-4ee9-aa80-fa088f16d4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271340123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3271340123
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1302845457
Short name T79
Test name
Test status
Simulation time 25365710 ps
CPU time 0.93 seconds
Started Aug 06 07:40:54 PM PDT 24
Finished Aug 06 07:40:55 PM PDT 24
Peak memory 215564 kb
Host smart-759434c5-e475-4341-bf39-348aa657a1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302845457 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1302845457
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3960377459
Short name T692
Test name
Test status
Simulation time 76953175 ps
CPU time 0.88 seconds
Started Aug 06 07:40:56 PM PDT 24
Finished Aug 06 07:40:57 PM PDT 24
Peak memory 206576 kb
Host smart-bcefb1a8-11ae-4840-aa11-6d6b4c2e1e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960377459 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3960377459
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.339649939
Short name T371
Test name
Test status
Simulation time 36184295 ps
CPU time 0.88 seconds
Started Aug 06 07:40:54 PM PDT 24
Finished Aug 06 07:40:54 PM PDT 24
Peak memory 214908 kb
Host smart-45839e9a-f19f-44bb-a5ce-a79b2413d66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339649939 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.339649939
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1799206794
Short name T478
Test name
Test status
Simulation time 257198425 ps
CPU time 4.92 seconds
Started Aug 06 07:40:53 PM PDT 24
Finished Aug 06 07:40:58 PM PDT 24
Peak memory 214936 kb
Host smart-9016cfc6-4c8e-40d9-97a1-74a5aefdc980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799206794 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1799206794
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.769394218
Short name T225
Test name
Test status
Simulation time 81622238645 ps
CPU time 1705.76 seconds
Started Aug 06 07:40:55 PM PDT 24
Finished Aug 06 08:09:21 PM PDT 24
Peak memory 223584 kb
Host smart-e91d83d0-748a-47fa-8b66-78c3d5bc1c69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769394218 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.769394218
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3645683843
Short name T706
Test name
Test status
Simulation time 26079182 ps
CPU time 1.15 seconds
Started Aug 06 07:43:34 PM PDT 24
Finished Aug 06 07:43:35 PM PDT 24
Peak memory 220392 kb
Host smart-9ce1715a-af14-419f-a6e0-6a658d887453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645683843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3645683843
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3435538674
Short name T917
Test name
Test status
Simulation time 53970465 ps
CPU time 0.99 seconds
Started Aug 06 07:43:36 PM PDT 24
Finished Aug 06 07:43:37 PM PDT 24
Peak memory 214784 kb
Host smart-be9fea61-3f9f-4c5c-aaff-041c39335069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435538674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3435538674
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1412196970
Short name T639
Test name
Test status
Simulation time 17098227 ps
CPU time 0.97 seconds
Started Aug 06 07:43:35 PM PDT 24
Finished Aug 06 07:43:36 PM PDT 24
Peak memory 219904 kb
Host smart-4c916801-57af-4b5a-a685-8812ac5bba0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412196970 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1412196970
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3873717858
Short name T816
Test name
Test status
Simulation time 61385546 ps
CPU time 1.01 seconds
Started Aug 06 07:43:36 PM PDT 24
Finished Aug 06 07:43:37 PM PDT 24
Peak memory 219040 kb
Host smart-222ab736-ea82-47a1-a482-78a894551cee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873717858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3873717858
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2638645204
Short name T179
Test name
Test status
Simulation time 25752051 ps
CPU time 0.95 seconds
Started Aug 06 07:43:40 PM PDT 24
Finished Aug 06 07:43:41 PM PDT 24
Peak memory 218436 kb
Host smart-9fba7136-a314-45eb-a112-601ef9ec98fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638645204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2638645204
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2180264444
Short name T512
Test name
Test status
Simulation time 54051556 ps
CPU time 1.04 seconds
Started Aug 06 07:43:19 PM PDT 24
Finished Aug 06 07:43:21 PM PDT 24
Peak memory 217052 kb
Host smart-786ee76a-6808-4cdd-9618-f36514cd4cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180264444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2180264444
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.534873932
Short name T695
Test name
Test status
Simulation time 25138325 ps
CPU time 0.98 seconds
Started Aug 06 07:43:22 PM PDT 24
Finished Aug 06 07:43:23 PM PDT 24
Peak memory 215144 kb
Host smart-27c308a8-17a1-4a9a-b2c9-729c410ba5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534873932 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.534873932
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2267029947
Short name T803
Test name
Test status
Simulation time 100144647 ps
CPU time 0.97 seconds
Started Aug 06 07:43:18 PM PDT 24
Finished Aug 06 07:43:19 PM PDT 24
Peak memory 214896 kb
Host smart-7e04dbfa-bf0f-4e23-9ff6-a3c1790d42b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267029947 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2267029947
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2766645082
Short name T663
Test name
Test status
Simulation time 318927724 ps
CPU time 6.01 seconds
Started Aug 06 07:43:20 PM PDT 24
Finished Aug 06 07:43:26 PM PDT 24
Peak memory 216804 kb
Host smart-6282f94d-0f2f-4306-8c32-e7b8f10ef4cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766645082 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2766645082
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3402501408
Short name T89
Test name
Test status
Simulation time 798614798038 ps
CPU time 1174.75 seconds
Started Aug 06 07:43:22 PM PDT 24
Finished Aug 06 08:02:57 PM PDT 24
Peak memory 223464 kb
Host smart-a90c8bbb-dce7-4013-b928-99fd529a6a92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402501408 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3402501408
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.627575960
Short name T709
Test name
Test status
Simulation time 96588388 ps
CPU time 1.28 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:43:41 PM PDT 24
Peak memory 215252 kb
Host smart-b0affe2a-a65e-4ff5-bc67-cf9ab0175fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627575960 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.627575960
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.620142740
Short name T783
Test name
Test status
Simulation time 101313799 ps
CPU time 0.93 seconds
Started Aug 06 07:43:42 PM PDT 24
Finished Aug 06 07:43:43 PM PDT 24
Peak memory 206372 kb
Host smart-346f8911-7d6e-4b1d-a970-551764e4884d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620142740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.620142740
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2331689463
Short name T97
Test name
Test status
Simulation time 26237335 ps
CPU time 0.91 seconds
Started Aug 06 07:43:35 PM PDT 24
Finished Aug 06 07:43:36 PM PDT 24
Peak memory 216160 kb
Host smart-8d307982-af87-4dc1-9d0b-602c0e985764
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331689463 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2331689463
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.101802681
Short name T163
Test name
Test status
Simulation time 54006859 ps
CPU time 1.43 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:43:38 PM PDT 24
Peak memory 216916 kb
Host smart-5e5573d5-a449-4ac0-b128-1c924d631bec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101802681 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.101802681
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3964300274
Short name T56
Test name
Test status
Simulation time 19254772 ps
CPU time 0.98 seconds
Started Aug 06 07:43:35 PM PDT 24
Finished Aug 06 07:43:36 PM PDT 24
Peak memory 218416 kb
Host smart-5b88b353-b1b4-4fd5-a772-f50ca79b14be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964300274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3964300274
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3097873336
Short name T553
Test name
Test status
Simulation time 47192195 ps
CPU time 1.13 seconds
Started Aug 06 07:43:36 PM PDT 24
Finished Aug 06 07:43:37 PM PDT 24
Peak memory 216944 kb
Host smart-e6cceabf-4485-4abc-8a5f-32a66f60191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097873336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3097873336
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1938302031
Short name T937
Test name
Test status
Simulation time 21942656 ps
CPU time 1.07 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 214940 kb
Host smart-478d9130-d45d-4cfe-a232-b9c5941c8745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938302031 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1938302031
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.4123754285
Short name T230
Test name
Test status
Simulation time 55339070 ps
CPU time 0.93 seconds
Started Aug 06 07:43:36 PM PDT 24
Finished Aug 06 07:43:37 PM PDT 24
Peak memory 206624 kb
Host smart-39e291ca-5648-4ee7-a80c-160f80b63cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123754285 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.4123754285
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1969525205
Short name T49
Test name
Test status
Simulation time 119374803 ps
CPU time 1.01 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:43:38 PM PDT 24
Peak memory 214936 kb
Host smart-97896e6d-a44c-4493-9b91-a548950fa676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969525205 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1969525205
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3355167911
Short name T792
Test name
Test status
Simulation time 399923049868 ps
CPU time 3769.42 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 08:46:28 PM PDT 24
Peak memory 237180 kb
Host smart-c6c8d9e4-5862-4417-b3c8-4426022d283b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355167911 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3355167911
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1797332637
Short name T601
Test name
Test status
Simulation time 31581346 ps
CPU time 1.34 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:43:38 PM PDT 24
Peak memory 219304 kb
Host smart-de7b024f-9095-45b9-a32a-dcb047ece2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797332637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1797332637
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2108238560
Short name T52
Test name
Test status
Simulation time 26506900 ps
CPU time 0.93 seconds
Started Aug 06 07:43:35 PM PDT 24
Finished Aug 06 07:43:36 PM PDT 24
Peak memory 214660 kb
Host smart-191e6012-9daa-400b-ae08-8be0a09dde1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108238560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2108238560
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1478238837
Short name T884
Test name
Test status
Simulation time 14804658 ps
CPU time 0.85 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 216196 kb
Host smart-8f3f680f-0be7-4ffa-9a17-5359d1b6dc67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478238837 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1478238837
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.146296292
Short name T141
Test name
Test status
Simulation time 55651053 ps
CPU time 1.33 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:43:38 PM PDT 24
Peak memory 216680 kb
Host smart-b6440f49-2160-4b1c-a985-f18b3338203e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146296292 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.146296292
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1344375561
Short name T804
Test name
Test status
Simulation time 19007300 ps
CPU time 0.99 seconds
Started Aug 06 07:43:40 PM PDT 24
Finished Aug 06 07:43:41 PM PDT 24
Peak memory 218268 kb
Host smart-8e778c4f-385a-416a-88c0-599aa26b3e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344375561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1344375561
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.289253031
Short name T851
Test name
Test status
Simulation time 247797519 ps
CPU time 3.48 seconds
Started Aug 06 07:43:35 PM PDT 24
Finished Aug 06 07:43:39 PM PDT 24
Peak memory 217328 kb
Host smart-e4ba2a2d-e37a-4d7e-8a6e-54eb7908a449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289253031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.289253031
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3630407221
Short name T729
Test name
Test status
Simulation time 21282141 ps
CPU time 1.08 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:43:40 PM PDT 24
Peak memory 215512 kb
Host smart-17379d31-e344-4465-894a-43e2f1960b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630407221 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3630407221
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3382796801
Short name T609
Test name
Test status
Simulation time 107598208 ps
CPU time 0.9 seconds
Started Aug 06 07:43:38 PM PDT 24
Finished Aug 06 07:43:39 PM PDT 24
Peak memory 214864 kb
Host smart-dbda6eb5-cb8a-4500-97bc-934383142f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382796801 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3382796801
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.106270681
Short name T362
Test name
Test status
Simulation time 335755475 ps
CPU time 1.34 seconds
Started Aug 06 07:43:42 PM PDT 24
Finished Aug 06 07:43:43 PM PDT 24
Peak memory 216840 kb
Host smart-a446c0cf-cae5-4626-a09e-ae98f6d71833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106270681 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.106270681
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.1495589411
Short name T750
Test name
Test status
Simulation time 64311660 ps
CPU time 1.12 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:43:40 PM PDT 24
Peak memory 218236 kb
Host smart-98f2c513-3414-4581-b7c9-82cc6f8878b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495589411 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1495589411
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3868066032
Short name T599
Test name
Test status
Simulation time 37249005 ps
CPU time 0.97 seconds
Started Aug 06 07:43:38 PM PDT 24
Finished Aug 06 07:43:39 PM PDT 24
Peak memory 206468 kb
Host smart-691ec5aa-d8ce-4512-884a-13cd649a5202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868066032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3868066032
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3716167467
Short name T211
Test name
Test status
Simulation time 14960820 ps
CPU time 0.9 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 216304 kb
Host smart-e795d7d5-3b44-4f44-bc8a-9851b0e7c777
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716167467 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3716167467
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3090866616
Short name T622
Test name
Test status
Simulation time 36119699 ps
CPU time 1.14 seconds
Started Aug 06 07:43:38 PM PDT 24
Finished Aug 06 07:43:39 PM PDT 24
Peak memory 219396 kb
Host smart-f58f5c20-243c-4ba4-875e-acc062fee7c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090866616 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3090866616
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2260484669
Short name T155
Test name
Test status
Simulation time 69230886 ps
CPU time 1.29 seconds
Started Aug 06 07:43:36 PM PDT 24
Finished Aug 06 07:43:37 PM PDT 24
Peak memory 225504 kb
Host smart-2f1e4cba-6cb6-49c0-b971-f3b2f099d036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260484669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2260484669
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.285697375
Short name T936
Test name
Test status
Simulation time 36918697 ps
CPU time 1.54 seconds
Started Aug 06 07:43:35 PM PDT 24
Finished Aug 06 07:43:37 PM PDT 24
Peak memory 216820 kb
Host smart-c821ff30-8310-4c71-805f-5c778ba53374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285697375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.285697375
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1926075098
Short name T416
Test name
Test status
Simulation time 40786636 ps
CPU time 0.88 seconds
Started Aug 06 07:43:38 PM PDT 24
Finished Aug 06 07:43:39 PM PDT 24
Peak memory 215112 kb
Host smart-d56e0859-f7dc-4980-9b6e-39e998e8bf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926075098 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1926075098
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2019237683
Short name T738
Test name
Test status
Simulation time 17311326 ps
CPU time 0.95 seconds
Started Aug 06 07:43:40 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 214916 kb
Host smart-5d6c7505-1c0c-4151-901d-0748375ac286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019237683 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2019237683
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2386678852
Short name T100
Test name
Test status
Simulation time 143851169 ps
CPU time 1.42 seconds
Started Aug 06 07:43:35 PM PDT 24
Finished Aug 06 07:43:36 PM PDT 24
Peak memory 216920 kb
Host smart-fcecaab0-77b4-468e-8e07-e257224bb7e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386678852 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2386678852
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1619610603
Short name T615
Test name
Test status
Simulation time 353540130717 ps
CPU time 2054.14 seconds
Started Aug 06 07:43:38 PM PDT 24
Finished Aug 06 08:17:53 PM PDT 24
Peak memory 225444 kb
Host smart-b3e92388-23fd-4d70-8832-2004423e2553
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619610603 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1619610603
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1557779901
Short name T676
Test name
Test status
Simulation time 28462048 ps
CPU time 1.24 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:43:40 PM PDT 24
Peak memory 218332 kb
Host smart-005a9707-8616-4416-933c-d67135044e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557779901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1557779901
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2357072433
Short name T400
Test name
Test status
Simulation time 16675887 ps
CPU time 0.77 seconds
Started Aug 06 07:43:34 PM PDT 24
Finished Aug 06 07:43:35 PM PDT 24
Peak memory 206052 kb
Host smart-7821ccc2-0861-41e2-8857-d2f373322b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357072433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2357072433
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.54017947
Short name T368
Test name
Test status
Simulation time 16309159 ps
CPU time 0.81 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:43:38 PM PDT 24
Peak memory 215880 kb
Host smart-101264c9-05d8-48d3-b1fe-a4253278131c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54017947 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.54017947
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.471208459
Short name T139
Test name
Test status
Simulation time 43457634 ps
CPU time 1.31 seconds
Started Aug 06 07:43:36 PM PDT 24
Finished Aug 06 07:43:37 PM PDT 24
Peak memory 216872 kb
Host smart-5c4ba9a6-5bff-40f1-ad08-3df48fa53962
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471208459 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.471208459
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1169967856
Short name T973
Test name
Test status
Simulation time 18265618 ps
CPU time 1.02 seconds
Started Aug 06 07:43:42 PM PDT 24
Finished Aug 06 07:43:43 PM PDT 24
Peak memory 218088 kb
Host smart-79153a12-48b7-4003-972b-b11541fc078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169967856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1169967856
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.4027399552
Short name T486
Test name
Test status
Simulation time 105831549 ps
CPU time 1.28 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:43:38 PM PDT 24
Peak memory 219724 kb
Host smart-d5bad19a-258e-417a-866a-ab2d291e864f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027399552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.4027399552
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3050995300
Short name T85
Test name
Test status
Simulation time 43751647 ps
CPU time 0.86 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 215564 kb
Host smart-7c99b01c-2f0d-4228-9277-cd83baf9758b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050995300 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3050995300
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.410450458
Short name T559
Test name
Test status
Simulation time 49625318 ps
CPU time 0.93 seconds
Started Aug 06 07:43:38 PM PDT 24
Finished Aug 06 07:43:39 PM PDT 24
Peak memory 214888 kb
Host smart-5666e58b-5645-4984-9232-7bdee5339104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410450458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.410450458
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.504491636
Short name T625
Test name
Test status
Simulation time 76095021 ps
CPU time 1.96 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:43 PM PDT 24
Peak memory 214896 kb
Host smart-08321f42-8fdf-4256-9c62-fe355a23054f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504491636 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.504491636
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2383089738
Short name T221
Test name
Test status
Simulation time 10727680601 ps
CPU time 233.21 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:47:35 PM PDT 24
Peak memory 217700 kb
Host smart-4e141bac-84af-4bb1-8ef2-09b665859e07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383089738 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2383089738
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2236866423
Short name T966
Test name
Test status
Simulation time 38490381 ps
CPU time 1.09 seconds
Started Aug 06 07:43:35 PM PDT 24
Finished Aug 06 07:43:36 PM PDT 24
Peak memory 218364 kb
Host smart-9461029a-0261-41e4-bbae-1a2f1a16c628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236866423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2236866423
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3504657327
Short name T674
Test name
Test status
Simulation time 45712632 ps
CPU time 0.9 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:43:40 PM PDT 24
Peak memory 206324 kb
Host smart-c597e237-c5ce-4718-a322-7e00d1d6d256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504657327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3504657327
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3879235968
Short name T717
Test name
Test status
Simulation time 12568680 ps
CPU time 0.89 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 215164 kb
Host smart-68487520-a9cb-4fff-a256-0797406a1638
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879235968 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3879235968
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2409073154
Short name T704
Test name
Test status
Simulation time 23749843 ps
CPU time 1.06 seconds
Started Aug 06 07:43:40 PM PDT 24
Finished Aug 06 07:43:41 PM PDT 24
Peak memory 219056 kb
Host smart-26a740a2-b870-42ea-81bb-32447030cedf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409073154 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2409073154
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2325704178
Short name T913
Test name
Test status
Simulation time 84565757 ps
CPU time 0.87 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:43:38 PM PDT 24
Peak memory 219664 kb
Host smart-7a4a530e-8e99-4ee3-ba58-568284670e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325704178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2325704178
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1735278742
Short name T510
Test name
Test status
Simulation time 48479754 ps
CPU time 1.51 seconds
Started Aug 06 07:43:38 PM PDT 24
Finished Aug 06 07:43:40 PM PDT 24
Peak memory 218084 kb
Host smart-7812fe30-61e3-4fa5-a84b-b8e45e2a3cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735278742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1735278742
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2327833193
Short name T380
Test name
Test status
Simulation time 40494553 ps
CPU time 0.88 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:43:38 PM PDT 24
Peak memory 214960 kb
Host smart-f3eea884-43ad-4975-9bcb-701b4b8b2297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327833193 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2327833193
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3484663803
Short name T658
Test name
Test status
Simulation time 25119186 ps
CPU time 0.89 seconds
Started Aug 06 07:43:36 PM PDT 24
Finished Aug 06 07:43:37 PM PDT 24
Peak memory 214864 kb
Host smart-0e7cfb89-e9c6-4ba6-ae26-fe00d6409568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484663803 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3484663803
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.817652177
Short name T715
Test name
Test status
Simulation time 641185045 ps
CPU time 6.56 seconds
Started Aug 06 07:43:34 PM PDT 24
Finished Aug 06 07:43:40 PM PDT 24
Peak memory 218208 kb
Host smart-54ea1b16-8ec7-400c-83f9-a5a86b1016d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817652177 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.817652177
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_alert.123416310
Short name T288
Test name
Test status
Simulation time 187741295 ps
CPU time 1.14 seconds
Started Aug 06 07:43:42 PM PDT 24
Finished Aug 06 07:43:43 PM PDT 24
Peak memory 218252 kb
Host smart-286c5eeb-c7e4-4c9f-ad7a-047474c1f315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123416310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.123416310
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1377127734
Short name T734
Test name
Test status
Simulation time 21760914 ps
CPU time 0.99 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:43:38 PM PDT 24
Peak memory 206336 kb
Host smart-c7855a4c-9109-4e73-af02-e446d27d03d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377127734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1377127734
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2710242506
Short name T578
Test name
Test status
Simulation time 21174430 ps
CPU time 0.86 seconds
Started Aug 06 07:43:35 PM PDT 24
Finished Aug 06 07:43:36 PM PDT 24
Peak memory 216224 kb
Host smart-0a7c2a05-1568-4e6a-8e30-7abdbf8a99d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710242506 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2710242506
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2269281764
Short name T492
Test name
Test status
Simulation time 131165378 ps
CPU time 1.15 seconds
Started Aug 06 07:43:36 PM PDT 24
Finished Aug 06 07:43:37 PM PDT 24
Peak memory 216860 kb
Host smart-13124e92-76ed-4d50-b80c-70e5ae41c7fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269281764 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2269281764
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1138165507
Short name T382
Test name
Test status
Simulation time 50810920 ps
CPU time 1.13 seconds
Started Aug 06 07:43:40 PM PDT 24
Finished Aug 06 07:43:41 PM PDT 24
Peak memory 219684 kb
Host smart-f05fedbd-efc4-4eba-98ac-9d284b0f4de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138165507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1138165507
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.390257199
Short name T423
Test name
Test status
Simulation time 44844959 ps
CPU time 1.41 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:43:41 PM PDT 24
Peak memory 218156 kb
Host smart-87af5f66-e75b-4d00-9462-876444daa3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390257199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.390257199
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1559610775
Short name T77
Test name
Test status
Simulation time 90162010 ps
CPU time 0.81 seconds
Started Aug 06 07:43:35 PM PDT 24
Finished Aug 06 07:43:36 PM PDT 24
Peak memory 215096 kb
Host smart-0a8e923b-81ab-43c0-9d7b-6bc9f328e1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559610775 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1559610775
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1844822662
Short name T795
Test name
Test status
Simulation time 15333247 ps
CPU time 0.97 seconds
Started Aug 06 07:43:40 PM PDT 24
Finished Aug 06 07:43:41 PM PDT 24
Peak memory 214908 kb
Host smart-745670f8-ca6c-4247-a4c7-4872c7e3386a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844822662 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1844822662
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3004782751
Short name T102
Test name
Test status
Simulation time 323238629 ps
CPU time 6.17 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:43:45 PM PDT 24
Peak memory 214920 kb
Host smart-e436fe60-92ba-41bf-bb67-d50c9e867920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004782751 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3004782751
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3506375516
Short name T667
Test name
Test status
Simulation time 53148081189 ps
CPU time 662.83 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:54:42 PM PDT 24
Peak memory 223388 kb
Host smart-379a3d4e-ab90-4006-a879-750a2d356e59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506375516 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3506375516
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.722692698
Short name T156
Test name
Test status
Simulation time 263936287 ps
CPU time 1.17 seconds
Started Aug 06 07:43:42 PM PDT 24
Finished Aug 06 07:43:43 PM PDT 24
Peak memory 219340 kb
Host smart-db448375-5ecb-4f58-b706-cbe71ba24025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722692698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.722692698
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2744279634
Short name T449
Test name
Test status
Simulation time 15330366 ps
CPU time 0.9 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 206332 kb
Host smart-f73d7462-19a6-4a18-8600-c8184c419448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744279634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2744279634
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2253916874
Short name T908
Test name
Test status
Simulation time 20536228 ps
CPU time 0.82 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:43:40 PM PDT 24
Peak memory 215916 kb
Host smart-bff3498b-d56d-4ce6-8891-4a89e6043dda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253916874 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2253916874
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1406862765
Short name T116
Test name
Test status
Simulation time 74655515 ps
CPU time 1.26 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:43 PM PDT 24
Peak memory 216792 kb
Host smart-0e05f3b3-7740-4114-a1e3-8767391c7fd2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406862765 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1406862765
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1604317889
Short name T161
Test name
Test status
Simulation time 24442501 ps
CPU time 1.23 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 229328 kb
Host smart-7924e0c5-4506-4571-a024-533db05a7952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604317889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1604317889
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1481994618
Short name T343
Test name
Test status
Simulation time 38894183 ps
CPU time 1.45 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:43:41 PM PDT 24
Peak memory 218164 kb
Host smart-73e9f092-b83e-4589-bca2-d42d8ec29584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481994618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1481994618
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.740880199
Short name T374
Test name
Test status
Simulation time 27579786 ps
CPU time 0.97 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:43:40 PM PDT 24
Peak memory 214928 kb
Host smart-dd0dba92-6c51-4fb1-a205-d9175e02652b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740880199 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.740880199
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.4075848792
Short name T961
Test name
Test status
Simulation time 178783305 ps
CPU time 0.95 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:43:38 PM PDT 24
Peak memory 215068 kb
Host smart-8cbe6130-cee9-459a-a67b-298e84f9bca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075848792 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.4075848792
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3777238138
Short name T793
Test name
Test status
Simulation time 166561578 ps
CPU time 3.19 seconds
Started Aug 06 07:43:38 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 216764 kb
Host smart-ff5fc780-8b71-43b8-8908-918a5518474a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777238138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3777238138
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.362386665
Short name T907
Test name
Test status
Simulation time 19930205923 ps
CPU time 456.6 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:51:16 PM PDT 24
Peak memory 223304 kb
Host smart-c4aa5305-8757-4735-9d65-587e806bb400
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362386665 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.362386665
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3658762963
Short name T192
Test name
Test status
Simulation time 81197607 ps
CPU time 1.15 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 215312 kb
Host smart-42852f37-3951-4bb4-a953-c3c31a7b7c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658762963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3658762963
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2483497459
Short name T51
Test name
Test status
Simulation time 25372711 ps
CPU time 0.87 seconds
Started Aug 06 07:43:38 PM PDT 24
Finished Aug 06 07:43:39 PM PDT 24
Peak memory 206328 kb
Host smart-55403569-3bb3-458d-80b5-d0660ef0d4ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483497459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2483497459
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3898774862
Short name T168
Test name
Test status
Simulation time 10994618 ps
CPU time 0.88 seconds
Started Aug 06 07:43:38 PM PDT 24
Finished Aug 06 07:43:39 PM PDT 24
Peak memory 215108 kb
Host smart-04254717-d854-44dc-a528-1d6a13cf19f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898774862 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3898774862
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.490708498
Short name T568
Test name
Test status
Simulation time 47851092 ps
CPU time 1.52 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:43:39 PM PDT 24
Peak memory 216824 kb
Host smart-56f2679c-6749-4a37-be8c-7f8d3a139afd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490708498 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.490708498
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3952882456
Short name T933
Test name
Test status
Simulation time 21517848 ps
CPU time 1 seconds
Started Aug 06 07:43:35 PM PDT 24
Finished Aug 06 07:43:36 PM PDT 24
Peak memory 219464 kb
Host smart-29baed3a-728e-4756-8764-dafed1311e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952882456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3952882456
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1338845896
Short name T743
Test name
Test status
Simulation time 130946302 ps
CPU time 1.4 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:43 PM PDT 24
Peak memory 217080 kb
Host smart-49bf5a0a-0f6e-4da7-bfa0-f712105e605f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338845896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1338845896
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3231615422
Short name T573
Test name
Test status
Simulation time 31089103 ps
CPU time 0.89 seconds
Started Aug 06 07:43:40 PM PDT 24
Finished Aug 06 07:43:41 PM PDT 24
Peak memory 215084 kb
Host smart-1698a2b7-56ec-48d6-a078-49dc34d8d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231615422 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3231615422
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.679665641
Short name T786
Test name
Test status
Simulation time 39537761 ps
CPU time 0.9 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 206716 kb
Host smart-888b9bbb-bfa3-4a33-ba43-f432e93de602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679665641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.679665641
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3858787538
Short name T853
Test name
Test status
Simulation time 184734847 ps
CPU time 3.98 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:45 PM PDT 24
Peak memory 219844 kb
Host smart-1d0f4e4e-ef42-49a0-a838-57d7a2d61922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858787538 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3858787538
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3495659632
Short name T508
Test name
Test status
Simulation time 25669891970 ps
CPU time 306.58 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:48:46 PM PDT 24
Peak memory 217520 kb
Host smart-b9321564-1081-42c6-bc7b-20859797d90b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495659632 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3495659632
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2467726278
Short name T142
Test name
Test status
Simulation time 85293662 ps
CPU time 1.29 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:43:41 PM PDT 24
Peak memory 219264 kb
Host smart-293dd352-264d-4188-bbff-0ea32eb7887f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467726278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2467726278
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3379303457
Short name T336
Test name
Test status
Simulation time 27965138 ps
CPU time 1.12 seconds
Started Aug 06 07:43:57 PM PDT 24
Finished Aug 06 07:43:58 PM PDT 24
Peak memory 214680 kb
Host smart-672a9665-17d4-4e02-bb9a-29f5b43cfe52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379303457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3379303457
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2228832674
Short name T212
Test name
Test status
Simulation time 24987671 ps
CPU time 0.87 seconds
Started Aug 06 07:43:36 PM PDT 24
Finished Aug 06 07:43:37 PM PDT 24
Peak memory 215128 kb
Host smart-582ff8ae-5b7d-419d-85c4-e7850a00b587
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228832674 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2228832674
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3509654372
Short name T846
Test name
Test status
Simulation time 104580909 ps
CPU time 1.12 seconds
Started Aug 06 07:43:58 PM PDT 24
Finished Aug 06 07:43:59 PM PDT 24
Peak memory 218948 kb
Host smart-4405ebd2-519d-4dbe-a3ba-8c84abbf9544
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509654372 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3509654372
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.141672487
Short name T184
Test name
Test status
Simulation time 33610553 ps
CPU time 0.95 seconds
Started Aug 06 07:43:39 PM PDT 24
Finished Aug 06 07:43:40 PM PDT 24
Peak memory 223628 kb
Host smart-2311a394-86c9-4c8b-bbdc-afc6ea7263b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141672487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.141672487
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2873641241
Short name T982
Test name
Test status
Simulation time 82234641 ps
CPU time 1.08 seconds
Started Aug 06 07:43:35 PM PDT 24
Finished Aug 06 07:43:36 PM PDT 24
Peak memory 216764 kb
Host smart-9d518524-e1dc-4e27-a845-8d56d20e4204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873641241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2873641241
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2239697756
Short name T383
Test name
Test status
Simulation time 21824441 ps
CPU time 1.23 seconds
Started Aug 06 07:43:37 PM PDT 24
Finished Aug 06 07:43:39 PM PDT 24
Peak memory 223748 kb
Host smart-a95f062f-eda0-4420-9f07-29996210b1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239697756 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2239697756
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.441147861
Short name T88
Test name
Test status
Simulation time 121366422 ps
CPU time 0.86 seconds
Started Aug 06 07:43:41 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 214872 kb
Host smart-423288b6-ebfd-49f5-a9ad-53975418721e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441147861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.441147861
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.4146591525
Short name T567
Test name
Test status
Simulation time 798053682 ps
CPU time 4.32 seconds
Started Aug 06 07:43:36 PM PDT 24
Finished Aug 06 07:43:41 PM PDT 24
Peak memory 216812 kb
Host smart-845e0384-bb35-41df-8fc1-85c3d25590d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146591525 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.4146591525
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3143328327
Short name T218
Test name
Test status
Simulation time 219116177067 ps
CPU time 1280.83 seconds
Started Aug 06 07:43:36 PM PDT 24
Finished Aug 06 08:04:57 PM PDT 24
Peak memory 223372 kb
Host smart-aac6d1ea-a3fa-45cc-b524-59a3b6541c57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143328327 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3143328327
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3435494077
Short name T604
Test name
Test status
Simulation time 36187752 ps
CPU time 1.2 seconds
Started Aug 06 07:40:56 PM PDT 24
Finished Aug 06 07:40:58 PM PDT 24
Peak memory 219292 kb
Host smart-be3514de-5a97-4c03-876a-1bc292340ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435494077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3435494077
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3704973781
Short name T479
Test name
Test status
Simulation time 63605368 ps
CPU time 0.81 seconds
Started Aug 06 07:40:56 PM PDT 24
Finished Aug 06 07:40:57 PM PDT 24
Peak memory 214656 kb
Host smart-146f367b-8d4f-4320-bf7e-3e77dc53c0d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704973781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3704973781
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1111224475
Short name T178
Test name
Test status
Simulation time 22790189 ps
CPU time 0.85 seconds
Started Aug 06 07:40:56 PM PDT 24
Finished Aug 06 07:40:56 PM PDT 24
Peak memory 219120 kb
Host smart-52a7346f-458d-4363-bd4a-9931c15749aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111224475 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1111224475
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3396485846
Short name T593
Test name
Test status
Simulation time 28046369 ps
CPU time 1.14 seconds
Started Aug 06 07:40:56 PM PDT 24
Finished Aug 06 07:40:57 PM PDT 24
Peak memory 218164 kb
Host smart-899beabb-a015-44a2-9530-0a9da116fed7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396485846 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3396485846
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1373751822
Short name T910
Test name
Test status
Simulation time 20749961 ps
CPU time 1.04 seconds
Started Aug 06 07:40:56 PM PDT 24
Finished Aug 06 07:40:57 PM PDT 24
Peak memory 223700 kb
Host smart-025f32ab-d254-4f95-b4fe-29ad5af48202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373751822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1373751822
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3597081686
Short name T532
Test name
Test status
Simulation time 26053301 ps
CPU time 1.2 seconds
Started Aug 06 07:40:55 PM PDT 24
Finished Aug 06 07:40:56 PM PDT 24
Peak memory 218196 kb
Host smart-9b9eb865-ed61-4118-a90a-19297a30104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597081686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3597081686
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.4059725767
Short name T930
Test name
Test status
Simulation time 21151359 ps
CPU time 1.06 seconds
Started Aug 06 07:40:53 PM PDT 24
Finished Aug 06 07:40:54 PM PDT 24
Peak memory 215600 kb
Host smart-a3229cc7-d53a-4f2f-b9c3-990c2096fb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059725767 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.4059725767
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1209705565
Short name T72
Test name
Test status
Simulation time 38250808 ps
CPU time 0.89 seconds
Started Aug 06 07:40:55 PM PDT 24
Finished Aug 06 07:40:56 PM PDT 24
Peak memory 206656 kb
Host smart-d1301b1b-40a2-4d62-9f1b-696be6dd40e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209705565 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1209705565
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1819191414
Short name T462
Test name
Test status
Simulation time 16087758 ps
CPU time 0.95 seconds
Started Aug 06 07:40:53 PM PDT 24
Finished Aug 06 07:40:54 PM PDT 24
Peak memory 214908 kb
Host smart-fe3149cc-6de2-495c-90f5-045bb6bfafa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819191414 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1819191414
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.518579530
Short name T235
Test name
Test status
Simulation time 464271942 ps
CPU time 6.42 seconds
Started Aug 06 07:40:53 PM PDT 24
Finished Aug 06 07:41:00 PM PDT 24
Peak memory 217124 kb
Host smart-bee26d0b-00f9-4ffe-a294-0f194289815e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518579530 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.518579530
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1282305997
Short name T742
Test name
Test status
Simulation time 58258799621 ps
CPU time 481.92 seconds
Started Aug 06 07:40:54 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 218192 kb
Host smart-a4d86c55-9385-4998-85ae-93ff320356e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282305997 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1282305997
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.630343337
Short name T18
Test name
Test status
Simulation time 126980066 ps
CPU time 1.08 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:55 PM PDT 24
Peak memory 219128 kb
Host smart-ea4544f3-f080-47cc-ba94-df52a836ebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630343337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.630343337
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.2692542807
Short name T799
Test name
Test status
Simulation time 27111443 ps
CPU time 1.25 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:55 PM PDT 24
Peak memory 220564 kb
Host smart-641d908a-5175-4e75-997f-2ed1144ca4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692542807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2692542807
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1026543995
Short name T297
Test name
Test status
Simulation time 35460569 ps
CPU time 1.03 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:54 PM PDT 24
Peak memory 216884 kb
Host smart-06c4faed-3a97-4caa-83dc-7e44747c256d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026543995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1026543995
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.240407759
Short name T574
Test name
Test status
Simulation time 71833816 ps
CPU time 1.18 seconds
Started Aug 06 07:43:57 PM PDT 24
Finished Aug 06 07:43:58 PM PDT 24
Peak memory 218272 kb
Host smart-747b6837-6284-4d24-b46f-db661d8bbfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240407759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.240407759
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.180200190
Short name T144
Test name
Test status
Simulation time 24723784 ps
CPU time 1.18 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:54 PM PDT 24
Peak memory 219720 kb
Host smart-1ab1b212-9c22-46a9-bb3d-038c4d70cefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180200190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.180200190
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4012742410
Short name T646
Test name
Test status
Simulation time 248129251 ps
CPU time 3.08 seconds
Started Aug 06 07:43:54 PM PDT 24
Finished Aug 06 07:43:57 PM PDT 24
Peak memory 218340 kb
Host smart-d6320a52-f7a7-41eb-b848-474cf24015e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012742410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4012742410
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.4216409823
Short name T815
Test name
Test status
Simulation time 44522498 ps
CPU time 1.21 seconds
Started Aug 06 07:44:00 PM PDT 24
Finished Aug 06 07:44:02 PM PDT 24
Peak memory 220348 kb
Host smart-b201e995-bf40-45cc-84bc-6cade313cd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216409823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.4216409823
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2736172595
Short name T4
Test name
Test status
Simulation time 19346278 ps
CPU time 1.2 seconds
Started Aug 06 07:43:56 PM PDT 24
Finished Aug 06 07:43:57 PM PDT 24
Peak memory 223716 kb
Host smart-b6d14701-02c4-452b-b07a-3bf6523c1d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736172595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2736172595
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1427679664
Short name T229
Test name
Test status
Simulation time 101428781 ps
CPU time 1.4 seconds
Started Aug 06 07:44:01 PM PDT 24
Finished Aug 06 07:44:02 PM PDT 24
Peak memory 219956 kb
Host smart-dc5a274f-0fc6-4f70-8a52-db78a35c3d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427679664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1427679664
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1509229372
Short name T931
Test name
Test status
Simulation time 50892802 ps
CPU time 1.22 seconds
Started Aug 06 07:43:59 PM PDT 24
Finished Aug 06 07:44:00 PM PDT 24
Peak memory 219932 kb
Host smart-5b109121-89aa-4be8-b1f9-44b170e6316a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509229372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1509229372
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_genbits.4200374158
Short name T376
Test name
Test status
Simulation time 36593208 ps
CPU time 1.36 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:55 PM PDT 24
Peak memory 216888 kb
Host smart-e3b08895-fa8a-4bb9-84c0-b81db0223a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200374158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.4200374158
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.683378712
Short name T873
Test name
Test status
Simulation time 78493913 ps
CPU time 1.13 seconds
Started Aug 06 07:43:57 PM PDT 24
Finished Aug 06 07:43:59 PM PDT 24
Peak memory 219356 kb
Host smart-9af6c8f3-0f43-463e-95ab-af74ed46f76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683378712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.683378712
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2411761769
Short name T108
Test name
Test status
Simulation time 50560829 ps
CPU time 0.82 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:54 PM PDT 24
Peak memory 218428 kb
Host smart-cf833772-be84-409c-b3eb-e56501cda1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411761769 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2411761769
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.659141819
Short name T759
Test name
Test status
Simulation time 38115068 ps
CPU time 1.29 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:55 PM PDT 24
Peak memory 218136 kb
Host smart-3eeacbc6-e8fd-441c-b8af-f5247caef467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659141819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.659141819
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2936678011
Short name T210
Test name
Test status
Simulation time 72935382 ps
CPU time 1.16 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:54 PM PDT 24
Peak memory 221180 kb
Host smart-a7f4a44d-7666-4ff6-9561-91d960b49512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936678011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2936678011
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3809437600
Short name T495
Test name
Test status
Simulation time 33119819 ps
CPU time 1.03 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:55 PM PDT 24
Peak memory 219688 kb
Host smart-fc04f1f7-7cab-4112-8c4b-2f5b14172440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809437600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3809437600
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1160744077
Short name T581
Test name
Test status
Simulation time 36158991 ps
CPU time 0.9 seconds
Started Aug 06 07:43:56 PM PDT 24
Finished Aug 06 07:43:57 PM PDT 24
Peak memory 216976 kb
Host smart-b029e374-bc05-4677-a112-a3e717537046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160744077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1160744077
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.1469571635
Short name T270
Test name
Test status
Simulation time 29481947 ps
CPU time 1.27 seconds
Started Aug 06 07:44:01 PM PDT 24
Finished Aug 06 07:44:02 PM PDT 24
Peak memory 218408 kb
Host smart-ef7949ef-ce0a-4f02-9555-828b7345cb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469571635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1469571635
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.2811386892
Short name T897
Test name
Test status
Simulation time 32811128 ps
CPU time 0.91 seconds
Started Aug 06 07:43:58 PM PDT 24
Finished Aug 06 07:43:59 PM PDT 24
Peak memory 218404 kb
Host smart-65da3bd5-9b00-485e-9e6f-1c23c854f42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811386892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2811386892
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3455438083
Short name T547
Test name
Test status
Simulation time 44188491 ps
CPU time 1.75 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:55 PM PDT 24
Peak memory 218312 kb
Host smart-38ed824a-ece3-4272-843e-ed3e005b7e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455438083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3455438083
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3632544467
Short name T535
Test name
Test status
Simulation time 82957078 ps
CPU time 1.22 seconds
Started Aug 06 07:43:57 PM PDT 24
Finished Aug 06 07:43:58 PM PDT 24
Peak memory 218100 kb
Host smart-1e440c33-bd3a-4931-8ccc-8686884e5a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632544467 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3632544467
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.3389340808
Short name T686
Test name
Test status
Simulation time 20600337 ps
CPU time 1.19 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:54 PM PDT 24
Peak memory 229244 kb
Host smart-e5e7c424-d310-4b54-893e-cd0427e1f73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389340808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3389340808
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.807903375
Short name T27
Test name
Test status
Simulation time 229749588 ps
CPU time 3.2 seconds
Started Aug 06 07:43:55 PM PDT 24
Finished Aug 06 07:43:58 PM PDT 24
Peak memory 219748 kb
Host smart-dc8d27d6-6f43-4fb5-9b29-55e85b154e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807903375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.807903375
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3643709513
Short name T408
Test name
Test status
Simulation time 36605843 ps
CPU time 1.29 seconds
Started Aug 06 07:43:57 PM PDT 24
Finished Aug 06 07:43:58 PM PDT 24
Peak memory 215316 kb
Host smart-4cc86e76-c3ec-4133-afd4-211ea91431e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643709513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3643709513
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3820910837
Short name T762
Test name
Test status
Simulation time 23653469 ps
CPU time 1.02 seconds
Started Aug 06 07:43:55 PM PDT 24
Finished Aug 06 07:43:56 PM PDT 24
Peak memory 219428 kb
Host smart-1ce90ff2-f877-4085-820c-04768a397e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820910837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3820910837
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3482169945
Short name T697
Test name
Test status
Simulation time 35680825 ps
CPU time 1.38 seconds
Started Aug 06 07:43:57 PM PDT 24
Finished Aug 06 07:43:58 PM PDT 24
Peak memory 218316 kb
Host smart-0aee18a2-0732-44b7-bd11-cccc491297ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482169945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3482169945
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1287798250
Short name T507
Test name
Test status
Simulation time 73238648 ps
CPU time 1.16 seconds
Started Aug 06 07:43:56 PM PDT 24
Finished Aug 06 07:43:57 PM PDT 24
Peak memory 218188 kb
Host smart-cb00925b-50fb-4218-a504-048d42d31ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287798250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1287798250
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1440453886
Short name T42
Test name
Test status
Simulation time 29901823 ps
CPU time 1.25 seconds
Started Aug 06 07:44:02 PM PDT 24
Finished Aug 06 07:44:03 PM PDT 24
Peak memory 229392 kb
Host smart-41a90561-8de0-4968-bf81-bedf00c9a4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440453886 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1440453886
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3750700803
Short name T337
Test name
Test status
Simulation time 44315580 ps
CPU time 1.63 seconds
Started Aug 06 07:44:01 PM PDT 24
Finished Aug 06 07:44:02 PM PDT 24
Peak memory 216956 kb
Host smart-bacc49e1-d2eb-42c3-a853-3c8fc2e49841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750700803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3750700803
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3080447004
Short name T608
Test name
Test status
Simulation time 27549959 ps
CPU time 1.18 seconds
Started Aug 06 07:41:15 PM PDT 24
Finished Aug 06 07:41:17 PM PDT 24
Peak memory 219436 kb
Host smart-b1da14c0-9d7f-4a79-9460-4f05ad897cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080447004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3080447004
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.4217681584
Short name T241
Test name
Test status
Simulation time 19028646 ps
CPU time 1.02 seconds
Started Aug 06 07:41:16 PM PDT 24
Finished Aug 06 07:41:17 PM PDT 24
Peak memory 206380 kb
Host smart-61d078ba-d1e4-4e5f-bb73-a5e9d4a22f60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217681584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.4217681584
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2502731217
Short name T655
Test name
Test status
Simulation time 55399287 ps
CPU time 0.88 seconds
Started Aug 06 07:41:14 PM PDT 24
Finished Aug 06 07:41:15 PM PDT 24
Peak memory 216208 kb
Host smart-48b71ad4-877c-40d7-8205-cde6ac5b9239
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502731217 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2502731217
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1084697037
Short name T112
Test name
Test status
Simulation time 36299037 ps
CPU time 1.19 seconds
Started Aug 06 07:41:15 PM PDT 24
Finished Aug 06 07:41:16 PM PDT 24
Peak memory 219300 kb
Host smart-e23c69b1-3c46-4b23-902c-beb2f69302fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084697037 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1084697037
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3058210282
Short name T147
Test name
Test status
Simulation time 21899181 ps
CPU time 1.11 seconds
Started Aug 06 07:41:15 PM PDT 24
Finished Aug 06 07:41:16 PM PDT 24
Peak memory 219700 kb
Host smart-0476959c-c03e-4f6e-9b92-0b4661ef14f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058210282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3058210282
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3071435677
Short name T632
Test name
Test status
Simulation time 116904193 ps
CPU time 1.16 seconds
Started Aug 06 07:40:54 PM PDT 24
Finished Aug 06 07:40:56 PM PDT 24
Peak memory 215004 kb
Host smart-8df1dfdc-8de4-4d33-b3fb-8fc350756a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071435677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3071435677
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.70254056
Short name T78
Test name
Test status
Simulation time 20386253 ps
CPU time 1.05 seconds
Started Aug 06 07:41:15 PM PDT 24
Finished Aug 06 07:41:17 PM PDT 24
Peak memory 215604 kb
Host smart-b3f9d9a1-1379-4ee9-8b83-9120cd8a601e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70254056 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.70254056
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.727762413
Short name T283
Test name
Test status
Simulation time 97290650 ps
CPU time 0.86 seconds
Started Aug 06 07:40:56 PM PDT 24
Finished Aug 06 07:40:57 PM PDT 24
Peak memory 206644 kb
Host smart-fdae1944-6375-4aed-93c4-dfcd70fd6067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727762413 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.727762413
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3011384374
Short name T40
Test name
Test status
Simulation time 42855931 ps
CPU time 0.86 seconds
Started Aug 06 07:40:55 PM PDT 24
Finished Aug 06 07:40:55 PM PDT 24
Peak memory 214848 kb
Host smart-d2d47564-0bcd-4db3-9155-0d3eb9fa1d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011384374 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3011384374
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1743199677
Short name T365
Test name
Test status
Simulation time 220820978 ps
CPU time 4.25 seconds
Started Aug 06 07:40:56 PM PDT 24
Finished Aug 06 07:41:00 PM PDT 24
Peak memory 214868 kb
Host smart-98e80f6c-22c3-4f36-9e20-c244c59049df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743199677 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1743199677
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2362656411
Short name T90
Test name
Test status
Simulation time 182588777830 ps
CPU time 1209.03 seconds
Started Aug 06 07:40:55 PM PDT 24
Finished Aug 06 08:01:04 PM PDT 24
Peak memory 223376 kb
Host smart-52ad8f60-4e52-47b4-aaa7-efc82801f027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362656411 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2362656411
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.609777547
Short name T530
Test name
Test status
Simulation time 24289498 ps
CPU time 1.22 seconds
Started Aug 06 07:43:56 PM PDT 24
Finished Aug 06 07:43:58 PM PDT 24
Peak memory 219308 kb
Host smart-879ee319-6cc8-49cd-9f17-a2e0ec3303d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609777547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.609777547
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1322627642
Short name T857
Test name
Test status
Simulation time 41397247 ps
CPU time 0.86 seconds
Started Aug 06 07:43:56 PM PDT 24
Finished Aug 06 07:43:57 PM PDT 24
Peak memory 219304 kb
Host smart-a2834754-e22f-458a-aa9b-e07656e0742c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322627642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1322627642
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3548866122
Short name T840
Test name
Test status
Simulation time 68906137 ps
CPU time 1.13 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:54 PM PDT 24
Peak memory 219544 kb
Host smart-e0d101a6-591b-4654-8ff7-9795bfd84a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548866122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3548866122
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.2925380904
Short name T757
Test name
Test status
Simulation time 86656922 ps
CPU time 1.2 seconds
Started Aug 06 07:43:54 PM PDT 24
Finished Aug 06 07:43:55 PM PDT 24
Peak memory 215304 kb
Host smart-9bb59613-2c2a-4c25-bbd0-6717347154b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925380904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.2925380904
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2746772195
Short name T670
Test name
Test status
Simulation time 23525722 ps
CPU time 0.93 seconds
Started Aug 06 07:43:56 PM PDT 24
Finished Aug 06 07:43:58 PM PDT 24
Peak memory 219584 kb
Host smart-7ebd1be7-02d7-4e47-83a2-6bb47d8785a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746772195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2746772195
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/62.edn_alert.2724572784
Short name T522
Test name
Test status
Simulation time 27850170 ps
CPU time 1.09 seconds
Started Aug 06 07:43:57 PM PDT 24
Finished Aug 06 07:43:58 PM PDT 24
Peak memory 217940 kb
Host smart-7e0e6ac9-63b5-4cef-9fa6-8cc3857011c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724572784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2724572784
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3865462670
Short name T136
Test name
Test status
Simulation time 26849707 ps
CPU time 1.02 seconds
Started Aug 06 07:44:02 PM PDT 24
Finished Aug 06 07:44:03 PM PDT 24
Peak memory 219392 kb
Host smart-e5b112ad-e71f-47e5-94cc-c6edbed018c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865462670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3865462670
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1828374902
Short name T753
Test name
Test status
Simulation time 70735306 ps
CPU time 1.22 seconds
Started Aug 06 07:43:56 PM PDT 24
Finished Aug 06 07:43:58 PM PDT 24
Peak memory 218820 kb
Host smart-1d904f11-f297-45c9-be9e-f0594152bb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828374902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1828374902
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.299959296
Short name T271
Test name
Test status
Simulation time 73739146 ps
CPU time 1.12 seconds
Started Aug 06 07:43:57 PM PDT 24
Finished Aug 06 07:43:58 PM PDT 24
Peak memory 218144 kb
Host smart-cfb9a1cc-16b3-44bc-838d-2f663063c2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299959296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.299959296
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1631808128
Short name T149
Test name
Test status
Simulation time 44418127 ps
CPU time 1.15 seconds
Started Aug 06 07:43:53 PM PDT 24
Finished Aug 06 07:43:54 PM PDT 24
Peak memory 229352 kb
Host smart-1abfbbd9-b6c8-4a95-b4ff-286156962748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631808128 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1631808128
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3390196163
Short name T550
Test name
Test status
Simulation time 59554096 ps
CPU time 2.11 seconds
Started Aug 06 07:43:57 PM PDT 24
Finished Aug 06 07:43:59 PM PDT 24
Peak memory 218016 kb
Host smart-4b1bc7e1-9c31-453b-afc2-df801effc4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390196163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3390196163
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1891304026
Short name T746
Test name
Test status
Simulation time 228880930 ps
CPU time 1.17 seconds
Started Aug 06 07:44:01 PM PDT 24
Finished Aug 06 07:44:02 PM PDT 24
Peak memory 219412 kb
Host smart-0636caee-918b-49a3-8f30-3b2e725c3b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891304026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1891304026
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1137717352
Short name T175
Test name
Test status
Simulation time 18433727 ps
CPU time 1.17 seconds
Started Aug 06 07:44:01 PM PDT 24
Finished Aug 06 07:44:03 PM PDT 24
Peak memory 223712 kb
Host smart-3603d292-c286-44d9-8a1d-44421e46a884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137717352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1137717352
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.440181475
Short name T395
Test name
Test status
Simulation time 51437476 ps
CPU time 1.19 seconds
Started Aug 06 07:43:58 PM PDT 24
Finished Aug 06 07:44:00 PM PDT 24
Peak memory 219436 kb
Host smart-10d87379-5793-4bee-83a2-503b6165cdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440181475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.440181475
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3690475556
Short name T292
Test name
Test status
Simulation time 108280629 ps
CPU time 1.22 seconds
Started Aug 06 07:44:18 PM PDT 24
Finished Aug 06 07:44:19 PM PDT 24
Peak memory 220344 kb
Host smart-dd33fd2a-5842-44d0-9d42-71926fdee69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690475556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3690475556
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.939093901
Short name T987
Test name
Test status
Simulation time 25598750 ps
CPU time 1.2 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 217188 kb
Host smart-a06ba1e5-41bf-49cc-b80d-c8921635f6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939093901 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.939093901
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2112092342
Short name T749
Test name
Test status
Simulation time 51403926 ps
CPU time 1.13 seconds
Started Aug 06 07:44:14 PM PDT 24
Finished Aug 06 07:44:15 PM PDT 24
Peak memory 217036 kb
Host smart-ced9c8bd-006b-4c2e-b676-214428aaa74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112092342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2112092342
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1452476782
Short name T82
Test name
Test status
Simulation time 109325879 ps
CPU time 1.1 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 219240 kb
Host smart-7fb924c1-1657-4950-b2c5-eac42db4221b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452476782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1452476782
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2878330316
Short name T106
Test name
Test status
Simulation time 102390901 ps
CPU time 0.91 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 219576 kb
Host smart-4d08f5dd-0105-4e51-97de-6e8a16a33411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878330316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2878330316
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1864569923
Short name T391
Test name
Test status
Simulation time 60329774 ps
CPU time 1.05 seconds
Started Aug 06 07:44:15 PM PDT 24
Finished Aug 06 07:44:16 PM PDT 24
Peak memory 218412 kb
Host smart-25ed94df-e87f-4173-ab88-a973f3127fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864569923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1864569923
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.3683682901
Short name T145
Test name
Test status
Simulation time 24458007 ps
CPU time 1.22 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 220088 kb
Host smart-125d97c8-be36-41c0-85ff-65a82d0d03a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683682901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.3683682901
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1047905075
Short name T946
Test name
Test status
Simulation time 154890594 ps
CPU time 1.06 seconds
Started Aug 06 07:44:14 PM PDT 24
Finished Aug 06 07:44:15 PM PDT 24
Peak memory 219776 kb
Host smart-7bb3cbb0-31c0-4e6c-a449-df7ce37aa0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047905075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1047905075
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1572418399
Short name T69
Test name
Test status
Simulation time 29363931 ps
CPU time 1.25 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 216968 kb
Host smart-e64088f8-f928-4434-b520-4c41ac977307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572418399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1572418399
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.2778196961
Short name T849
Test name
Test status
Simulation time 80541032 ps
CPU time 1.24 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 218256 kb
Host smart-b1bf9acc-b1f0-4eea-a256-35d3088aef73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778196961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.2778196961
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.2298243668
Short name T506
Test name
Test status
Simulation time 27997583 ps
CPU time 0.84 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 218340 kb
Host smart-bf157c82-dd14-4f6f-b30e-31dcde233085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298243668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2298243668
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.4159788362
Short name T24
Test name
Test status
Simulation time 119962174 ps
CPU time 1.32 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:19 PM PDT 24
Peak memory 218756 kb
Host smart-23dd5992-056d-4f97-99bf-40004d966775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159788362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.4159788362
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.4226390937
Short name T690
Test name
Test status
Simulation time 22798204 ps
CPU time 1.16 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 218084 kb
Host smart-4c58a448-a912-436f-b96f-05ffca1a546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226390937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.4226390937
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2146537491
Short name T154
Test name
Test status
Simulation time 33384029 ps
CPU time 1.45 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:19 PM PDT 24
Peak memory 225492 kb
Host smart-3f489d8e-8f2c-4314-bd38-d35587596fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146537491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2146537491
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1668280299
Short name T951
Test name
Test status
Simulation time 83735381 ps
CPU time 1.42 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 218308 kb
Host smart-89f735b9-ffae-4a65-8a5b-7d05036ed9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668280299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1668280299
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3215893614
Short name T688
Test name
Test status
Simulation time 48358727 ps
CPU time 1.25 seconds
Started Aug 06 07:41:15 PM PDT 24
Finished Aug 06 07:41:17 PM PDT 24
Peak memory 219580 kb
Host smart-cfce825a-32a9-4dae-9498-4f8e9a9926a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215893614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3215893614
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2505271154
Short name T264
Test name
Test status
Simulation time 13574453 ps
CPU time 0.92 seconds
Started Aug 06 07:41:16 PM PDT 24
Finished Aug 06 07:41:17 PM PDT 24
Peak memory 206328 kb
Host smart-1fb84605-d102-4e31-9b77-fd46fd92402c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505271154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2505271154
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2701462310
Short name T186
Test name
Test status
Simulation time 12457586 ps
CPU time 0.9 seconds
Started Aug 06 07:41:18 PM PDT 24
Finished Aug 06 07:41:19 PM PDT 24
Peak memory 216304 kb
Host smart-b0c4bb1b-46a4-4a61-b7f1-34e48be2e20d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701462310 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2701462310
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2924295797
Short name T53
Test name
Test status
Simulation time 109009509 ps
CPU time 1.13 seconds
Started Aug 06 07:41:15 PM PDT 24
Finished Aug 06 07:41:17 PM PDT 24
Peak memory 218120 kb
Host smart-ab0a82cd-14d4-4234-8166-6ce36d1fb746
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924295797 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2924295797
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1770048918
Short name T959
Test name
Test status
Simulation time 20541814 ps
CPU time 1.11 seconds
Started Aug 06 07:41:15 PM PDT 24
Finished Aug 06 07:41:16 PM PDT 24
Peak memory 219672 kb
Host smart-0b0f4f7b-dd04-4ca0-ae6f-9064772e508d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770048918 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1770048918
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.112812590
Short name T682
Test name
Test status
Simulation time 41512589 ps
CPU time 1.61 seconds
Started Aug 06 07:41:17 PM PDT 24
Finished Aug 06 07:41:19 PM PDT 24
Peak memory 218136 kb
Host smart-5c6c13cb-29d5-4097-941c-6f20b7c04bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112812590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.112812590
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2504031395
Short name T775
Test name
Test status
Simulation time 27364439 ps
CPU time 0.95 seconds
Started Aug 06 07:41:14 PM PDT 24
Finished Aug 06 07:41:15 PM PDT 24
Peak memory 214992 kb
Host smart-a390b63c-3e42-42a4-9724-001e6b81d201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504031395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2504031395
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.523661938
Short name T638
Test name
Test status
Simulation time 21585721 ps
CPU time 0.89 seconds
Started Aug 06 07:41:15 PM PDT 24
Finished Aug 06 07:41:16 PM PDT 24
Peak memory 206704 kb
Host smart-89286c31-457d-4a87-ae70-a01c46945ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523661938 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.523661938
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3495710423
Short name T346
Test name
Test status
Simulation time 29209049 ps
CPU time 0.94 seconds
Started Aug 06 07:41:15 PM PDT 24
Finished Aug 06 07:41:16 PM PDT 24
Peak memory 214904 kb
Host smart-242134cc-1aae-471c-b1b4-891c7f1260ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495710423 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3495710423
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.434771472
Short name T233
Test name
Test status
Simulation time 55241850 ps
CPU time 1.59 seconds
Started Aug 06 07:41:14 PM PDT 24
Finished Aug 06 07:41:15 PM PDT 24
Peak memory 214912 kb
Host smart-a3f13936-9610-4596-a3e8-644c9f549d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434771472 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.434771472
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.296777669
Short name T586
Test name
Test status
Simulation time 60010711889 ps
CPU time 1555.1 seconds
Started Aug 06 07:41:14 PM PDT 24
Finished Aug 06 08:07:10 PM PDT 24
Peak memory 223732 kb
Host smart-8056b031-8007-478b-b175-c14c4e03c5d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296777669 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.296777669
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.3532546938
Short name T628
Test name
Test status
Simulation time 19001884 ps
CPU time 1.03 seconds
Started Aug 06 07:44:15 PM PDT 24
Finished Aug 06 07:44:16 PM PDT 24
Peak memory 218600 kb
Host smart-11c1b8a1-68be-470b-84c8-7cb9fe89109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532546938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3532546938
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1291496781
Short name T546
Test name
Test status
Simulation time 42039621 ps
CPU time 1.28 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 218208 kb
Host smart-889e86ac-6713-4276-94c7-2837b2ef63fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291496781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1291496781
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1509013014
Short name T872
Test name
Test status
Simulation time 30457071 ps
CPU time 1.02 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:19 PM PDT 24
Peak memory 218576 kb
Host smart-936e7f77-d76f-471c-9f69-fbf41f118d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509013014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1509013014
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.503689349
Short name T338
Test name
Test status
Simulation time 25554527 ps
CPU time 1.22 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 216916 kb
Host smart-55924cfd-d68c-4fa7-9c55-73a5fa9e330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503689349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.503689349
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.2662289921
Short name T427
Test name
Test status
Simulation time 25271190 ps
CPU time 1.23 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:19 PM PDT 24
Peak memory 218404 kb
Host smart-5da3a8fe-3a76-47e4-a8aa-96ad319c52b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662289921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.2662289921
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.133105960
Short name T148
Test name
Test status
Simulation time 47410826 ps
CPU time 1.01 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 219584 kb
Host smart-3548f88a-bd44-474c-838a-c761b6503507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133105960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.133105960
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.4097918167
Short name T652
Test name
Test status
Simulation time 47479609 ps
CPU time 1.51 seconds
Started Aug 06 07:44:20 PM PDT 24
Finished Aug 06 07:44:22 PM PDT 24
Peak memory 218108 kb
Host smart-a899f37f-feb6-4ea6-9c01-89794e599c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097918167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.4097918167
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3774272870
Short name T958
Test name
Test status
Simulation time 83109319 ps
CPU time 1.16 seconds
Started Aug 06 07:44:18 PM PDT 24
Finished Aug 06 07:44:20 PM PDT 24
Peak memory 220496 kb
Host smart-73816bda-7b44-4cba-9bbb-7a1cd138a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774272870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3774272870
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3927535040
Short name T514
Test name
Test status
Simulation time 19247128 ps
CPU time 1.21 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 223692 kb
Host smart-2d86ae6b-e07d-4638-ab96-62fceafd1239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927535040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3927535040
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1125930567
Short name T545
Test name
Test status
Simulation time 249002254 ps
CPU time 1.29 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 218276 kb
Host smart-3f80e5df-0042-4289-92a1-e266b19ff6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125930567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1125930567
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.1918259131
Short name T146
Test name
Test status
Simulation time 74033781 ps
CPU time 1.16 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 219304 kb
Host smart-30f66922-3671-4c50-97e0-6d82ed517bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918259131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1918259131
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3483023191
Short name T2
Test name
Test status
Simulation time 32363605 ps
CPU time 1.1 seconds
Started Aug 06 07:44:18 PM PDT 24
Finished Aug 06 07:44:19 PM PDT 24
Peak memory 219684 kb
Host smart-7dd3dcfa-b8e3-4859-9048-142046365540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483023191 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3483023191
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.365999998
Short name T983
Test name
Test status
Simulation time 79293444 ps
CPU time 1.15 seconds
Started Aug 06 07:44:18 PM PDT 24
Finished Aug 06 07:44:19 PM PDT 24
Peak memory 216972 kb
Host smart-7c1fd5b2-8990-4c90-adbd-6a6f3ba9581c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365999998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.365999998
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.989706351
Short name T619
Test name
Test status
Simulation time 76115918 ps
CPU time 1.19 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 218528 kb
Host smart-2fe0bb68-8aef-44fb-9827-a716b98f294e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989706351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.989706351
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2366839514
Short name T764
Test name
Test status
Simulation time 28922787 ps
CPU time 1.11 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 218196 kb
Host smart-ea99a5b1-71bb-47ee-bb48-34b9f29d7b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366839514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2366839514
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3215880841
Short name T561
Test name
Test status
Simulation time 96062482 ps
CPU time 1.11 seconds
Started Aug 06 07:44:18 PM PDT 24
Finished Aug 06 07:44:19 PM PDT 24
Peak memory 218484 kb
Host smart-5a9bd979-ab75-4d53-b037-d66183520b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215880841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3215880841
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.2998479696
Short name T188
Test name
Test status
Simulation time 30397581 ps
CPU time 1.23 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 219148 kb
Host smart-18b169de-1f4f-477b-a6c1-14b0b3654343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998479696 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.2998479696
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.1038686253
Short name T99
Test name
Test status
Simulation time 26679769 ps
CPU time 0.9 seconds
Started Aug 06 07:44:18 PM PDT 24
Finished Aug 06 07:44:19 PM PDT 24
Peak memory 218400 kb
Host smart-a56efbef-cfda-410a-8548-24f18368a335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038686253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1038686253
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2140257260
Short name T305
Test name
Test status
Simulation time 42592894 ps
CPU time 1.26 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:19 PM PDT 24
Peak memory 218324 kb
Host smart-e05ec682-088c-4353-84d3-de5f2ae769f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140257260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2140257260
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.371061783
Short name T93
Test name
Test status
Simulation time 25068212 ps
CPU time 1.21 seconds
Started Aug 06 07:44:20 PM PDT 24
Finished Aug 06 07:44:21 PM PDT 24
Peak memory 219372 kb
Host smart-2c70b31b-7599-48f2-bea0-d3cf02496420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371061783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.371061783
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3530142728
Short name T132
Test name
Test status
Simulation time 25058312 ps
CPU time 1.29 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 229460 kb
Host smart-908a55f0-e86a-4f96-9fc6-d8e822cfff53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530142728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3530142728
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.172610847
Short name T918
Test name
Test status
Simulation time 36647605 ps
CPU time 1.41 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 217144 kb
Host smart-ce17df74-7707-4603-a165-6fdbc1928d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172610847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.172610847
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3624618358
Short name T668
Test name
Test status
Simulation time 27354814 ps
CPU time 1.15 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 218052 kb
Host smart-53e102f3-37e6-4c28-a59f-9a9857d5b805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624618358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3624618358
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.1191323607
Short name T203
Test name
Test status
Simulation time 19933016 ps
CPU time 1.16 seconds
Started Aug 06 07:44:19 PM PDT 24
Finished Aug 06 07:44:20 PM PDT 24
Peak memory 229280 kb
Host smart-7dc59542-3a2c-4828-8327-cb173235bef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191323607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1191323607
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_alert.2984908534
Short name T273
Test name
Test status
Simulation time 72565159 ps
CPU time 1.08 seconds
Started Aug 06 07:44:15 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 219032 kb
Host smart-cba3c87a-548d-4b53-a5cf-03d5f1f4ee8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984908534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2984908534
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.1885314950
Short name T205
Test name
Test status
Simulation time 32275472 ps
CPU time 0.84 seconds
Started Aug 06 07:44:14 PM PDT 24
Finished Aug 06 07:44:15 PM PDT 24
Peak memory 218028 kb
Host smart-5b07e0ad-05fe-4c1e-bcc6-7a0da62ce7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885314950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1885314950
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3908439851
Short name T328
Test name
Test status
Simulation time 40380815 ps
CPU time 1.1 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 219788 kb
Host smart-384abb62-b5cb-4988-8321-d24d14652576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908439851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3908439851
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3690764970
Short name T160
Test name
Test status
Simulation time 23272999 ps
CPU time 1.19 seconds
Started Aug 06 07:41:17 PM PDT 24
Finished Aug 06 07:41:18 PM PDT 24
Peak memory 218252 kb
Host smart-6b8f10dd-8b18-4edf-91e9-6dc14a6acafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690764970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3690764970
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2727347503
Short name T711
Test name
Test status
Simulation time 19881004 ps
CPU time 0.99 seconds
Started Aug 06 07:41:16 PM PDT 24
Finished Aug 06 07:41:17 PM PDT 24
Peak memory 206360 kb
Host smart-2c412987-69b8-4c55-9d30-b4137c7f6c1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727347503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2727347503
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3274211713
Short name T162
Test name
Test status
Simulation time 152914025 ps
CPU time 1.19 seconds
Started Aug 06 07:41:18 PM PDT 24
Finished Aug 06 07:41:19 PM PDT 24
Peak memory 216844 kb
Host smart-1ffc2779-3da4-4097-af63-0915cd4a7d6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274211713 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3274211713
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3167059950
Short name T830
Test name
Test status
Simulation time 41543822 ps
CPU time 1.04 seconds
Started Aug 06 07:41:14 PM PDT 24
Finished Aug 06 07:41:15 PM PDT 24
Peak memory 229252 kb
Host smart-17e0c3dd-ec5f-46dd-b543-aa667399ee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167059950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3167059950
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3348866619
Short name T1
Test name
Test status
Simulation time 90467874 ps
CPU time 1.18 seconds
Started Aug 06 07:41:13 PM PDT 24
Finished Aug 06 07:41:15 PM PDT 24
Peak memory 218252 kb
Host smart-9a46a914-1d3d-4a93-bf08-36a4c27ad37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348866619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3348866619
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2331054248
Short name T45
Test name
Test status
Simulation time 39364933 ps
CPU time 0.98 seconds
Started Aug 06 07:41:13 PM PDT 24
Finished Aug 06 07:41:14 PM PDT 24
Peak memory 223636 kb
Host smart-f9889bf8-e161-421b-89ea-408091472156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331054248 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2331054248
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1440770138
Short name T651
Test name
Test status
Simulation time 18867017 ps
CPU time 0.98 seconds
Started Aug 06 07:41:14 PM PDT 24
Finished Aug 06 07:41:15 PM PDT 24
Peak memory 206648 kb
Host smart-d14f7cbc-bc61-4f92-bcd4-045934b49872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440770138 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1440770138
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1566032490
Short name T577
Test name
Test status
Simulation time 47688869 ps
CPU time 0.92 seconds
Started Aug 06 07:41:16 PM PDT 24
Finished Aug 06 07:41:17 PM PDT 24
Peak memory 215020 kb
Host smart-d3c985b3-83e8-4651-951a-7c4907e585d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566032490 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1566032490
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2478492962
Short name T231
Test name
Test status
Simulation time 365872194 ps
CPU time 3.74 seconds
Started Aug 06 07:41:13 PM PDT 24
Finished Aug 06 07:41:17 PM PDT 24
Peak memory 214900 kb
Host smart-3a93a605-fc0e-4cd1-8433-f061c30ee08a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478492962 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2478492962
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1091261493
Short name T220
Test name
Test status
Simulation time 48963475109 ps
CPU time 172.93 seconds
Started Aug 06 07:41:16 PM PDT 24
Finished Aug 06 07:44:09 PM PDT 24
Peak memory 217468 kb
Host smart-4a9c6ef9-fe87-44db-b3cb-ac14748dc0a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091261493 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1091261493
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2317967188
Short name T888
Test name
Test status
Simulation time 45968828 ps
CPU time 1.18 seconds
Started Aug 06 07:44:14 PM PDT 24
Finished Aug 06 07:44:15 PM PDT 24
Peak memory 219784 kb
Host smart-56ac8074-30bb-4a22-af81-f7edf6c4ae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317967188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2317967188
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3400926001
Short name T109
Test name
Test status
Simulation time 31000627 ps
CPU time 0.97 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 223640 kb
Host smart-2a741916-501a-4bdc-b93e-041b1dac1fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400926001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3400926001
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2329500320
Short name T901
Test name
Test status
Simulation time 43611612 ps
CPU time 1.56 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 218148 kb
Host smart-2dd801b2-5da3-40a2-8931-cdc2eb053654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329500320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2329500320
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2861206944
Short name T641
Test name
Test status
Simulation time 29049659 ps
CPU time 1.23 seconds
Started Aug 06 07:44:15 PM PDT 24
Finished Aug 06 07:44:16 PM PDT 24
Peak memory 220300 kb
Host smart-22dd23ed-ef62-4495-ac8f-ac27995d2c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861206944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2861206944
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1766375914
Short name T952
Test name
Test status
Simulation time 19556921 ps
CPU time 0.98 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 218492 kb
Host smart-accda342-23cb-42f4-9ef9-7659c21c5217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766375914 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1766375914
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_alert.2162733177
Short name T450
Test name
Test status
Simulation time 88525724 ps
CPU time 1.13 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 219024 kb
Host smart-7554627f-8ca9-4d9c-805d-d7bb78f17b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162733177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2162733177
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.4132137410
Short name T41
Test name
Test status
Simulation time 38412189 ps
CPU time 0.97 seconds
Started Aug 06 07:44:18 PM PDT 24
Finished Aug 06 07:44:19 PM PDT 24
Peak memory 223648 kb
Host smart-b31c307d-1038-4d80-a276-8cdd2529bfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132137410 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.4132137410
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3451087192
Short name T265
Test name
Test status
Simulation time 39804239 ps
CPU time 1.07 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 214836 kb
Host smart-d81603be-657e-43dc-8d49-afe6b228fcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451087192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3451087192
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1773870323
Short name T797
Test name
Test status
Simulation time 135697020 ps
CPU time 1.17 seconds
Started Aug 06 07:44:14 PM PDT 24
Finished Aug 06 07:44:16 PM PDT 24
Peak memory 218124 kb
Host smart-e742dfd5-8334-48f4-8f95-2df74a265241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773870323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1773870323
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.1178005587
Short name T195
Test name
Test status
Simulation time 21744682 ps
CPU time 1.06 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:17 PM PDT 24
Peak memory 223704 kb
Host smart-a7829440-a750-45de-90ee-65f43410200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178005587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1178005587
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1703073485
Short name T304
Test name
Test status
Simulation time 35163933 ps
CPU time 1.4 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 219188 kb
Host smart-54a03282-7554-4d67-a601-e1a5ca000cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703073485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1703073485
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.4026171214
Short name T83
Test name
Test status
Simulation time 21933384 ps
CPU time 0.93 seconds
Started Aug 06 07:44:17 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 218184 kb
Host smart-8d66a130-7657-4c02-8084-0de9fd047359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026171214 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.4026171214
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.938757039
Short name T861
Test name
Test status
Simulation time 77014929 ps
CPU time 1.11 seconds
Started Aug 06 07:44:15 PM PDT 24
Finished Aug 06 07:44:16 PM PDT 24
Peak memory 217132 kb
Host smart-fd12da02-2ed0-4f64-aeb2-1d6e7bc2a7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938757039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.938757039
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.871584531
Short name T705
Test name
Test status
Simulation time 87798955 ps
CPU time 1.21 seconds
Started Aug 06 07:44:43 PM PDT 24
Finished Aug 06 07:44:45 PM PDT 24
Peak memory 218384 kb
Host smart-bf647031-dc6b-45f6-b4c9-af53553d1152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871584531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.871584531
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1384972319
Short name T138
Test name
Test status
Simulation time 26141279 ps
CPU time 0.97 seconds
Started Aug 06 07:44:41 PM PDT 24
Finished Aug 06 07:44:42 PM PDT 24
Peak memory 219348 kb
Host smart-0f020fc1-42a8-4f46-ab70-7fb3b3a3c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384972319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1384972319
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2184159282
Short name T471
Test name
Test status
Simulation time 34156220 ps
CPU time 1.26 seconds
Started Aug 06 07:44:16 PM PDT 24
Finished Aug 06 07:44:18 PM PDT 24
Peak memory 219392 kb
Host smart-b0e25816-f8fb-4027-8a23-38c61e730261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184159282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2184159282
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.4108367286
Short name T829
Test name
Test status
Simulation time 46892611 ps
CPU time 1.19 seconds
Started Aug 06 07:44:44 PM PDT 24
Finished Aug 06 07:44:45 PM PDT 24
Peak memory 218704 kb
Host smart-2dd51789-7ec8-4a76-9bc8-43226d752e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108367286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.4108367286
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.513961548
Short name T509
Test name
Test status
Simulation time 244686969 ps
CPU time 1.16 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:47 PM PDT 24
Peak memory 225552 kb
Host smart-284ce79b-a16a-4713-abe0-4d8c373b0692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513961548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.513961548
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1795731397
Short name T313
Test name
Test status
Simulation time 47891889 ps
CPU time 1.45 seconds
Started Aug 06 07:44:43 PM PDT 24
Finished Aug 06 07:44:44 PM PDT 24
Peak memory 217224 kb
Host smart-0e15fc35-22b9-4715-9f84-a0d4870aac39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795731397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1795731397
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.2085305358
Short name T496
Test name
Test status
Simulation time 45001353 ps
CPU time 1.22 seconds
Started Aug 06 07:44:41 PM PDT 24
Finished Aug 06 07:44:43 PM PDT 24
Peak memory 219332 kb
Host smart-14642e72-f65c-4e33-9238-5f5f0b64f972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085305358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2085305358
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3649109725
Short name T207
Test name
Test status
Simulation time 23973620 ps
CPU time 0.83 seconds
Started Aug 06 07:44:45 PM PDT 24
Finished Aug 06 07:44:46 PM PDT 24
Peak memory 218200 kb
Host smart-e0f8eec8-9f76-4fab-af88-6c32c2b102b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649109725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3649109725
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.619157835
Short name T735
Test name
Test status
Simulation time 39766269 ps
CPU time 1.36 seconds
Started Aug 06 07:44:42 PM PDT 24
Finished Aug 06 07:44:43 PM PDT 24
Peak memory 219600 kb
Host smart-9ef566ce-bd9d-4417-bb6a-550db9987724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619157835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.619157835
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1613486026
Short name T725
Test name
Test status
Simulation time 27684968 ps
CPU time 1.19 seconds
Started Aug 06 07:44:43 PM PDT 24
Finished Aug 06 07:44:44 PM PDT 24
Peak memory 218004 kb
Host smart-3ff89cc2-107e-4397-a610-633c1916e7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613486026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1613486026
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.4181490374
Short name T137
Test name
Test status
Simulation time 25312031 ps
CPU time 0.98 seconds
Started Aug 06 07:44:42 PM PDT 24
Finished Aug 06 07:44:43 PM PDT 24
Peak memory 219512 kb
Host smart-2657b746-b27d-44af-aec9-e2d71b815157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181490374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.4181490374
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1161243959
Short name T314
Test name
Test status
Simulation time 103875832 ps
CPU time 1.28 seconds
Started Aug 06 07:44:43 PM PDT 24
Finished Aug 06 07:44:45 PM PDT 24
Peak memory 218700 kb
Host smart-f1f478ea-5d55-4cd1-83a4-f5f0be9b7022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161243959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1161243959
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.592639349
Short name T594
Test name
Test status
Simulation time 69833609 ps
CPU time 1.17 seconds
Started Aug 06 07:44:43 PM PDT 24
Finished Aug 06 07:44:45 PM PDT 24
Peak memory 218196 kb
Host smart-caa7f630-2e19-4607-b3cb-4647207f8f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592639349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.592639349
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1353238997
Short name T114
Test name
Test status
Simulation time 18656872 ps
CPU time 1.01 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:47 PM PDT 24
Peak memory 218300 kb
Host smart-eb579f7b-7432-4117-8578-1869ca62ada1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353238997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1353238997
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1370682146
Short name T819
Test name
Test status
Simulation time 49340717 ps
CPU time 1.02 seconds
Started Aug 06 07:44:45 PM PDT 24
Finished Aug 06 07:44:46 PM PDT 24
Peak memory 217044 kb
Host smart-c4e5bf88-da52-4340-815e-996c6d88f309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370682146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1370682146
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1794520527
Short name T903
Test name
Test status
Simulation time 27983448 ps
CPU time 1.22 seconds
Started Aug 06 07:41:15 PM PDT 24
Finished Aug 06 07:41:17 PM PDT 24
Peak memory 219392 kb
Host smart-1d5e8a8d-b1d8-40e4-8b57-50a3f68c44a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794520527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1794520527
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2506395226
Short name T348
Test name
Test status
Simulation time 29277756 ps
CPU time 0.89 seconds
Started Aug 06 07:41:34 PM PDT 24
Finished Aug 06 07:41:35 PM PDT 24
Peak memory 206332 kb
Host smart-37e69fd4-a474-4fa2-848c-b7b25029a158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506395226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2506395226
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2734541884
Short name T33
Test name
Test status
Simulation time 16065952 ps
CPU time 0.83 seconds
Started Aug 06 07:41:17 PM PDT 24
Finished Aug 06 07:41:18 PM PDT 24
Peak memory 215108 kb
Host smart-298b5e69-8dfd-476d-9775-197808591357
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734541884 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2734541884
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2011973956
Short name T957
Test name
Test status
Simulation time 99830162 ps
CPU time 1.12 seconds
Started Aug 06 07:41:36 PM PDT 24
Finished Aug 06 07:41:37 PM PDT 24
Peak memory 219248 kb
Host smart-b2aebe4a-8f34-48ce-86ff-3857cb2f1b11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011973956 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2011973956
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1669418347
Short name T131
Test name
Test status
Simulation time 38777280 ps
CPU time 1.1 seconds
Started Aug 06 07:41:17 PM PDT 24
Finished Aug 06 07:41:18 PM PDT 24
Peak memory 229352 kb
Host smart-85f0d764-f07a-4e03-bd67-2f28baeb13cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669418347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1669418347
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.581624630
Short name T694
Test name
Test status
Simulation time 39701489 ps
CPU time 1.72 seconds
Started Aug 06 07:41:16 PM PDT 24
Finished Aug 06 07:41:18 PM PDT 24
Peak memory 218032 kb
Host smart-fc05ecf5-0501-4c87-8f37-f19a44c4e8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581624630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.581624630
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1371343845
Short name T19
Test name
Test status
Simulation time 38923021 ps
CPU time 0.85 seconds
Started Aug 06 07:41:16 PM PDT 24
Finished Aug 06 07:41:17 PM PDT 24
Peak memory 215296 kb
Host smart-09f2b347-ef6b-45b4-9b42-60daed65ec30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371343845 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1371343845
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.3057211362
Short name T334
Test name
Test status
Simulation time 14606278 ps
CPU time 0.92 seconds
Started Aug 06 07:41:14 PM PDT 24
Finished Aug 06 07:41:15 PM PDT 24
Peak memory 214832 kb
Host smart-9f327b92-ad4c-4abb-9a5f-800ff9eff2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057211362 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3057211362
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3732742489
Short name T671
Test name
Test status
Simulation time 491955830 ps
CPU time 3.34 seconds
Started Aug 06 07:41:18 PM PDT 24
Finished Aug 06 07:41:22 PM PDT 24
Peak memory 217076 kb
Host smart-6c7ba755-6d9b-491f-ae08-c8f7a3f075ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732742489 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3732742489
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3754213793
Short name T955
Test name
Test status
Simulation time 28488402013 ps
CPU time 631.91 seconds
Started Aug 06 07:41:15 PM PDT 24
Finished Aug 06 07:51:47 PM PDT 24
Peak memory 218004 kb
Host smart-8f3c6f9b-163c-4d65-9990-8c31a4cee34a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754213793 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3754213793
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.1044410230
Short name T660
Test name
Test status
Simulation time 73484232 ps
CPU time 1.14 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:47 PM PDT 24
Peak memory 219548 kb
Host smart-8dafe44b-edcf-4f4e-9fa6-3eb1422130fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044410230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.1044410230
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3715459195
Short name T557
Test name
Test status
Simulation time 26311848 ps
CPU time 0.89 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:47 PM PDT 24
Peak memory 218408 kb
Host smart-20d73052-474b-4ac7-8842-476707523661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715459195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3715459195
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1233096725
Short name T30
Test name
Test status
Simulation time 83052271 ps
CPU time 1.39 seconds
Started Aug 06 07:44:47 PM PDT 24
Finished Aug 06 07:44:49 PM PDT 24
Peak memory 218244 kb
Host smart-8a75f533-d2e3-4195-a52d-9439f87e0077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233096725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1233096725
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.3365602627
Short name T791
Test name
Test status
Simulation time 94700388 ps
CPU time 1.2 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:47 PM PDT 24
Peak memory 215328 kb
Host smart-95e4196e-ac73-4348-b01d-774d0f8857af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365602627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.3365602627
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.252074084
Short name T157
Test name
Test status
Simulation time 33622989 ps
CPU time 1.01 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:47 PM PDT 24
Peak memory 229528 kb
Host smart-b0e3c4bf-a056-447b-bad3-58081508c885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252074084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.252074084
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.419777240
Short name T684
Test name
Test status
Simulation time 91111180 ps
CPU time 1.52 seconds
Started Aug 06 07:44:47 PM PDT 24
Finished Aug 06 07:44:49 PM PDT 24
Peak memory 218640 kb
Host smart-fb3c192d-32fa-4606-a5f5-fb5995408eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419777240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.419777240
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.1135912525
Short name T213
Test name
Test status
Simulation time 23221069 ps
CPU time 1.19 seconds
Started Aug 06 07:44:48 PM PDT 24
Finished Aug 06 07:44:49 PM PDT 24
Peak memory 218312 kb
Host smart-fdfe34fd-fcd2-4e94-b310-c301a5b6292a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135912525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.1135912525
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.1144223001
Short name T521
Test name
Test status
Simulation time 38237204 ps
CPU time 0.94 seconds
Started Aug 06 07:44:48 PM PDT 24
Finished Aug 06 07:44:49 PM PDT 24
Peak memory 218528 kb
Host smart-09106d22-8d9b-4dee-a84f-70ff136db810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144223001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1144223001
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.691112974
Short name T442
Test name
Test status
Simulation time 59544580 ps
CPU time 1.45 seconds
Started Aug 06 07:44:44 PM PDT 24
Finished Aug 06 07:44:46 PM PDT 24
Peak memory 218268 kb
Host smart-155cf73a-26e7-4b21-82be-9034b17e6db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691112974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.691112974
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.3234749658
Short name T611
Test name
Test status
Simulation time 51442582 ps
CPU time 1.27 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 219284 kb
Host smart-a173f46e-b502-42c4-b6b8-c3782311658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234749658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3234749658
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.440165950
Short name T172
Test name
Test status
Simulation time 19671594 ps
CPU time 1.04 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:47 PM PDT 24
Peak memory 218492 kb
Host smart-394ada9b-38a5-43d6-b627-478bd544b0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440165950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.440165950
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1481277751
Short name T333
Test name
Test status
Simulation time 34426075 ps
CPU time 1.5 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 218104 kb
Host smart-ae6f7757-66fb-4554-9b18-82d48e56f4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481277751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1481277751
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1590549036
Short name T823
Test name
Test status
Simulation time 29447151 ps
CPU time 1.27 seconds
Started Aug 06 07:44:48 PM PDT 24
Finished Aug 06 07:44:50 PM PDT 24
Peak memory 215300 kb
Host smart-4f75988c-7c95-42f9-9d6d-77465718e5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590549036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1590549036
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3227706714
Short name T781
Test name
Test status
Simulation time 43728350 ps
CPU time 1.12 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 219680 kb
Host smart-1b4473dc-6c95-48ba-b385-8c1ecb799b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227706714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3227706714
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.43123456
Short name T691
Test name
Test status
Simulation time 32296216 ps
CPU time 1.28 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 216820 kb
Host smart-e39adde4-cc63-4c0f-8c8c-4d5e9a6c74ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43123456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.43123456
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3680423898
Short name T659
Test name
Test status
Simulation time 22565169 ps
CPU time 1.15 seconds
Started Aug 06 07:44:49 PM PDT 24
Finished Aug 06 07:44:50 PM PDT 24
Peak memory 219388 kb
Host smart-3b4e1e2d-a380-44a7-aa36-d9371057e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680423898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3680423898
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.4125444559
Short name T948
Test name
Test status
Simulation time 28647917 ps
CPU time 1.22 seconds
Started Aug 06 07:44:49 PM PDT 24
Finished Aug 06 07:44:50 PM PDT 24
Peak memory 219656 kb
Host smart-74aee183-e679-4556-88f4-06b59105f254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125444559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4125444559
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1137209632
Short name T978
Test name
Test status
Simulation time 98996003 ps
CPU time 1.34 seconds
Started Aug 06 07:44:48 PM PDT 24
Finished Aug 06 07:44:49 PM PDT 24
Peak memory 218140 kb
Host smart-74f6877d-454f-428a-9aa0-5166c36f5d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137209632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1137209632
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.3143225840
Short name T864
Test name
Test status
Simulation time 47804531 ps
CPU time 1.19 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 218156 kb
Host smart-73462af0-3d32-4673-8792-f029323f87ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143225840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.3143225840
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1648186300
Short name T190
Test name
Test status
Simulation time 24050821 ps
CPU time 1 seconds
Started Aug 06 07:44:46 PM PDT 24
Finished Aug 06 07:44:48 PM PDT 24
Peak memory 218384 kb
Host smart-6d7005c0-e649-4444-935e-f8b64e137339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648186300 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1648186300
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2439365084
Short name T482
Test name
Test status
Simulation time 42679049 ps
CPU time 1.78 seconds
Started Aug 06 07:44:45 PM PDT 24
Finished Aug 06 07:44:47 PM PDT 24
Peak memory 218328 kb
Host smart-773f6c0f-b593-4ec8-a4d9-f9b34ecd6bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439365084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2439365084
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2977748555
Short name T802
Test name
Test status
Simulation time 45958794 ps
CPU time 1.26 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:52 PM PDT 24
Peak memory 219428 kb
Host smart-8f42dce1-7ee9-4ffb-9bf9-00fc7ebf4694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977748555 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2977748555
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.107744408
Short name T110
Test name
Test status
Simulation time 32669032 ps
CPU time 1.13 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 219560 kb
Host smart-255f4a4e-11da-4c6a-bc54-3482d227f173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107744408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.107744408
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3348320284
Short name T28
Test name
Test status
Simulation time 93836239 ps
CPU time 2.02 seconds
Started Aug 06 07:44:48 PM PDT 24
Finished Aug 06 07:44:50 PM PDT 24
Peak memory 219652 kb
Host smart-497b1f7f-8bb4-4d1b-a6e1-957f7044ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348320284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3348320284
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.427002217
Short name T282
Test name
Test status
Simulation time 44007934 ps
CPU time 1.14 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 219136 kb
Host smart-cfadfa5c-f52b-444d-bae4-8b50e98851d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427002217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.427002217
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.391208193
Short name T46
Test name
Test status
Simulation time 31589398 ps
CPU time 1.06 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 229388 kb
Host smart-26843b46-d6f3-4b95-afb8-9219ebf38dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391208193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.391208193
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1059340823
Short name T312
Test name
Test status
Simulation time 33807553 ps
CPU time 1.49 seconds
Started Aug 06 07:44:49 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 218152 kb
Host smart-b609cf65-5bb5-452a-8e4a-252eedbba656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059340823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1059340823
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3983434887
Short name T640
Test name
Test status
Simulation time 81699833 ps
CPU time 1.14 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 218112 kb
Host smart-f737d64e-2e5f-449b-9ab2-e8cb4b3d32a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983434887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3983434887
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3609557759
Short name T6
Test name
Test status
Simulation time 33632200 ps
CPU time 0.96 seconds
Started Aug 06 07:44:50 PM PDT 24
Finished Aug 06 07:44:51 PM PDT 24
Peak memory 219744 kb
Host smart-034cd759-2290-4ff5-8f6d-7e2c2811d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609557759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3609557759
Directory /workspace/99.edn_err/latest
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