Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.17 98.25 93.07 90.85 87.21 95.50 96.83 90.48


Total test records in report: 1125
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T1012 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.4205362395 Aug 07 05:36:08 PM PDT 24 Aug 07 05:36:09 PM PDT 24 30643091 ps
T1013 /workspace/coverage/cover_reg_top/34.edn_intr_test.2598070816 Aug 07 05:36:38 PM PDT 24 Aug 07 05:36:39 PM PDT 24 19513571 ps
T287 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.960100825 Aug 07 05:36:08 PM PDT 24 Aug 07 05:36:11 PM PDT 24 991611675 ps
T1014 /workspace/coverage/cover_reg_top/43.edn_intr_test.37882665 Aug 07 05:36:45 PM PDT 24 Aug 07 05:36:46 PM PDT 24 40506789 ps
T1015 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3354886225 Aug 07 05:36:09 PM PDT 24 Aug 07 05:36:14 PM PDT 24 675632167 ps
T1016 /workspace/coverage/cover_reg_top/41.edn_intr_test.1974385684 Aug 07 05:36:48 PM PDT 24 Aug 07 05:36:49 PM PDT 24 189237072 ps
T1017 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3853683426 Aug 07 05:36:08 PM PDT 24 Aug 07 05:36:11 PM PDT 24 68095208 ps
T1018 /workspace/coverage/cover_reg_top/8.edn_tl_errors.936703514 Aug 07 05:36:20 PM PDT 24 Aug 07 05:36:22 PM PDT 24 22183013 ps
T1019 /workspace/coverage/cover_reg_top/12.edn_intr_test.3884909649 Aug 07 05:36:25 PM PDT 24 Aug 07 05:36:26 PM PDT 24 31669309 ps
T1020 /workspace/coverage/cover_reg_top/6.edn_csr_rw.840758139 Aug 07 05:36:13 PM PDT 24 Aug 07 05:36:14 PM PDT 24 21366797 ps
T256 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1878914994 Aug 07 05:36:06 PM PDT 24 Aug 07 05:36:08 PM PDT 24 60843962 ps
T1021 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2347437055 Aug 07 05:36:18 PM PDT 24 Aug 07 05:36:20 PM PDT 24 45827413 ps
T1022 /workspace/coverage/cover_reg_top/46.edn_intr_test.1279219423 Aug 07 05:36:45 PM PDT 24 Aug 07 05:36:46 PM PDT 24 59196036 ps
T1023 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2311149011 Aug 07 05:36:33 PM PDT 24 Aug 07 05:36:34 PM PDT 24 100896282 ps
T257 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2055166213 Aug 07 05:36:08 PM PDT 24 Aug 07 05:36:09 PM PDT 24 17361075 ps
T1024 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3306011086 Aug 07 05:36:16 PM PDT 24 Aug 07 05:36:18 PM PDT 24 110957980 ps
T1025 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1920514804 Aug 07 05:36:15 PM PDT 24 Aug 07 05:36:17 PM PDT 24 46525485 ps
T1026 /workspace/coverage/cover_reg_top/7.edn_intr_test.2286233136 Aug 07 05:36:16 PM PDT 24 Aug 07 05:36:17 PM PDT 24 94796242 ps
T1027 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3660981331 Aug 07 05:36:07 PM PDT 24 Aug 07 05:36:08 PM PDT 24 16466486 ps
T1028 /workspace/coverage/cover_reg_top/1.edn_tl_errors.192058474 Aug 07 05:36:10 PM PDT 24 Aug 07 05:36:13 PM PDT 24 112118813 ps
T1029 /workspace/coverage/cover_reg_top/21.edn_intr_test.45468770 Aug 07 05:36:39 PM PDT 24 Aug 07 05:36:40 PM PDT 24 27900837 ps
T1030 /workspace/coverage/cover_reg_top/1.edn_intr_test.330557992 Aug 07 05:36:08 PM PDT 24 Aug 07 05:36:09 PM PDT 24 18894487 ps
T1031 /workspace/coverage/cover_reg_top/2.edn_intr_test.611204551 Aug 07 05:36:08 PM PDT 24 Aug 07 05:36:09 PM PDT 24 22051342 ps
T1032 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3657403250 Aug 07 05:36:28 PM PDT 24 Aug 07 05:36:29 PM PDT 24 15519709 ps
T1033 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3567364045 Aug 07 05:36:10 PM PDT 24 Aug 07 05:36:12 PM PDT 24 148630720 ps
T1034 /workspace/coverage/cover_reg_top/29.edn_intr_test.561901092 Aug 07 05:36:38 PM PDT 24 Aug 07 05:36:39 PM PDT 24 89283466 ps
T1035 /workspace/coverage/cover_reg_top/7.edn_tl_errors.303586049 Aug 07 05:36:16 PM PDT 24 Aug 07 05:36:19 PM PDT 24 174984062 ps
T1036 /workspace/coverage/cover_reg_top/20.edn_intr_test.800941509 Aug 07 05:36:37 PM PDT 24 Aug 07 05:36:38 PM PDT 24 21166548 ps
T1037 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3375970413 Aug 07 05:36:26 PM PDT 24 Aug 07 05:36:28 PM PDT 24 73616250 ps
T1038 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3934663051 Aug 07 05:36:34 PM PDT 24 Aug 07 05:36:36 PM PDT 24 23687678 ps
T1039 /workspace/coverage/cover_reg_top/39.edn_intr_test.3365630990 Aug 07 05:36:45 PM PDT 24 Aug 07 05:36:46 PM PDT 24 13205852 ps
T1040 /workspace/coverage/cover_reg_top/44.edn_intr_test.1492011977 Aug 07 05:36:44 PM PDT 24 Aug 07 05:36:44 PM PDT 24 21548891 ps
T1041 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2893334187 Aug 07 05:36:08 PM PDT 24 Aug 07 05:36:15 PM PDT 24 520809100 ps
T1042 /workspace/coverage/cover_reg_top/18.edn_intr_test.2376386715 Aug 07 05:36:39 PM PDT 24 Aug 07 05:36:40 PM PDT 24 131686099 ps
T1043 /workspace/coverage/cover_reg_top/26.edn_intr_test.2277076987 Aug 07 05:36:40 PM PDT 24 Aug 07 05:36:41 PM PDT 24 15132658 ps
T1044 /workspace/coverage/cover_reg_top/30.edn_intr_test.3461565400 Aug 07 05:36:40 PM PDT 24 Aug 07 05:36:41 PM PDT 24 27628842 ps
T1045 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3117821711 Aug 07 05:36:28 PM PDT 24 Aug 07 05:36:29 PM PDT 24 45901394 ps
T1046 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3567058717 Aug 07 05:36:24 PM PDT 24 Aug 07 05:36:26 PM PDT 24 61908141 ps
T1047 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2115370722 Aug 07 05:36:19 PM PDT 24 Aug 07 05:36:20 PM PDT 24 26413453 ps
T1048 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2389081308 Aug 07 05:36:09 PM PDT 24 Aug 07 05:36:10 PM PDT 24 42294169 ps
T1049 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.401670969 Aug 07 05:36:09 PM PDT 24 Aug 07 05:36:11 PM PDT 24 85369518 ps
T1050 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3606747345 Aug 07 05:36:02 PM PDT 24 Aug 07 05:36:05 PM PDT 24 499000570 ps
T284 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2219683993 Aug 07 05:36:23 PM PDT 24 Aug 07 05:36:26 PM PDT 24 325078487 ps
T1051 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2432187301 Aug 07 05:36:41 PM PDT 24 Aug 07 05:36:42 PM PDT 24 35254498 ps
T1052 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.301820980 Aug 07 05:36:15 PM PDT 24 Aug 07 05:36:21 PM PDT 24 673322185 ps
T1053 /workspace/coverage/cover_reg_top/19.edn_tl_errors.276978765 Aug 07 05:36:39 PM PDT 24 Aug 07 05:36:42 PM PDT 24 262761863 ps
T1054 /workspace/coverage/cover_reg_top/9.edn_intr_test.1318687456 Aug 07 05:36:20 PM PDT 24 Aug 07 05:36:21 PM PDT 24 15991620 ps
T1055 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1287909706 Aug 07 05:36:38 PM PDT 24 Aug 07 05:36:39 PM PDT 24 152024586 ps
T285 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3277427365 Aug 07 05:36:28 PM PDT 24 Aug 07 05:36:30 PM PDT 24 229161233 ps
T1056 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2229875493 Aug 07 05:36:15 PM PDT 24 Aug 07 05:36:16 PM PDT 24 93823542 ps
T258 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2142596832 Aug 07 05:36:24 PM PDT 24 Aug 07 05:36:25 PM PDT 24 22972607 ps
T1057 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2768312944 Aug 07 05:36:07 PM PDT 24 Aug 07 05:36:08 PM PDT 24 131086614 ps
T1058 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4153408450 Aug 07 05:36:12 PM PDT 24 Aug 07 05:36:13 PM PDT 24 45149937 ps
T1059 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2799387233 Aug 07 05:36:20 PM PDT 24 Aug 07 05:36:22 PM PDT 24 122310284 ps
T1060 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1675085149 Aug 07 05:36:19 PM PDT 24 Aug 07 05:36:21 PM PDT 24 70470959 ps
T1061 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.882260810 Aug 07 05:36:28 PM PDT 24 Aug 07 05:36:29 PM PDT 24 21844513 ps
T1062 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.205301315 Aug 07 05:36:17 PM PDT 24 Aug 07 05:36:19 PM PDT 24 69078737 ps
T1063 /workspace/coverage/cover_reg_top/5.edn_intr_test.2566818941 Aug 07 05:36:14 PM PDT 24 Aug 07 05:36:15 PM PDT 24 18047200 ps
T1064 /workspace/coverage/cover_reg_top/24.edn_intr_test.3516076098 Aug 07 05:36:43 PM PDT 24 Aug 07 05:36:44 PM PDT 24 13449618 ps
T1065 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4151416770 Aug 07 05:36:32 PM PDT 24 Aug 07 05:36:34 PM PDT 24 131208804 ps
T1066 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2159373582 Aug 07 05:36:27 PM PDT 24 Aug 07 05:36:29 PM PDT 24 103795639 ps
T1067 /workspace/coverage/cover_reg_top/22.edn_intr_test.1256442842 Aug 07 05:36:38 PM PDT 24 Aug 07 05:36:39 PM PDT 24 29134089 ps
T1068 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2462482838 Aug 07 05:36:26 PM PDT 24 Aug 07 05:36:27 PM PDT 24 29053269 ps
T1069 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.459878813 Aug 07 05:36:26 PM PDT 24 Aug 07 05:36:28 PM PDT 24 14342007 ps
T1070 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2663373248 Aug 07 05:36:19 PM PDT 24 Aug 07 05:36:20 PM PDT 24 36539078 ps
T1071 /workspace/coverage/cover_reg_top/38.edn_intr_test.1622189224 Aug 07 05:36:48 PM PDT 24 Aug 07 05:36:49 PM PDT 24 38319156 ps
T1072 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2785216834 Aug 07 05:36:09 PM PDT 24 Aug 07 05:36:10 PM PDT 24 125143762 ps
T1073 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1470954340 Aug 07 05:36:07 PM PDT 24 Aug 07 05:36:10 PM PDT 24 70044915 ps
T1074 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2712398271 Aug 07 05:36:41 PM PDT 24 Aug 07 05:36:42 PM PDT 24 15198449 ps
T1075 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.4286766064 Aug 07 05:36:26 PM PDT 24 Aug 07 05:36:28 PM PDT 24 15183484 ps
T1076 /workspace/coverage/cover_reg_top/17.edn_tl_errors.71879807 Aug 07 05:36:38 PM PDT 24 Aug 07 05:36:40 PM PDT 24 23096137 ps
T1077 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2349288401 Aug 07 05:36:20 PM PDT 24 Aug 07 05:36:22 PM PDT 24 249122053 ps
T259 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.615082136 Aug 07 05:36:15 PM PDT 24 Aug 07 05:36:16 PM PDT 24 135349517 ps
T260 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1600826796 Aug 07 05:36:20 PM PDT 24 Aug 07 05:36:21 PM PDT 24 39812180 ps
T1078 /workspace/coverage/cover_reg_top/23.edn_intr_test.549277491 Aug 07 05:36:41 PM PDT 24 Aug 07 05:36:42 PM PDT 24 17073366 ps
T1079 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1230899108 Aug 07 05:36:18 PM PDT 24 Aug 07 05:36:21 PM PDT 24 162397240 ps
T1080 /workspace/coverage/cover_reg_top/42.edn_intr_test.274634382 Aug 07 05:36:44 PM PDT 24 Aug 07 05:36:45 PM PDT 24 18309061 ps
T1081 /workspace/coverage/cover_reg_top/13.edn_tl_errors.988881377 Aug 07 05:36:27 PM PDT 24 Aug 07 05:36:30 PM PDT 24 78674615 ps
T1082 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2042869143 Aug 07 05:36:31 PM PDT 24 Aug 07 05:36:33 PM PDT 24 47673671 ps
T1083 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3747896973 Aug 07 05:36:13 PM PDT 24 Aug 07 05:36:14 PM PDT 24 14388968 ps
T1084 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3468020732 Aug 07 05:36:14 PM PDT 24 Aug 07 05:36:17 PM PDT 24 111727042 ps
T1085 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.391626493 Aug 07 05:36:35 PM PDT 24 Aug 07 05:36:36 PM PDT 24 23736974 ps
T1086 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1617677172 Aug 07 05:36:20 PM PDT 24 Aug 07 05:36:21 PM PDT 24 179734364 ps
T1087 /workspace/coverage/cover_reg_top/35.edn_intr_test.2197624105 Aug 07 05:36:40 PM PDT 24 Aug 07 05:36:41 PM PDT 24 20173754 ps
T1088 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2483735139 Aug 07 05:36:20 PM PDT 24 Aug 07 05:36:22 PM PDT 24 57568987 ps
T1089 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.645342362 Aug 07 05:36:08 PM PDT 24 Aug 07 05:36:10 PM PDT 24 100956641 ps
T261 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3500638249 Aug 07 05:36:13 PM PDT 24 Aug 07 05:36:14 PM PDT 24 36705805 ps
T1090 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1561899244 Aug 07 05:36:20 PM PDT 24 Aug 07 05:36:21 PM PDT 24 20856809 ps
T1091 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2953017944 Aug 07 05:36:18 PM PDT 24 Aug 07 05:36:19 PM PDT 24 43110863 ps
T262 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3138763262 Aug 07 05:36:08 PM PDT 24 Aug 07 05:36:09 PM PDT 24 183548726 ps
T1092 /workspace/coverage/cover_reg_top/15.edn_tl_errors.821207692 Aug 07 05:36:30 PM PDT 24 Aug 07 05:36:34 PM PDT 24 95980937 ps
T1093 /workspace/coverage/cover_reg_top/32.edn_intr_test.3783048311 Aug 07 05:36:41 PM PDT 24 Aug 07 05:36:42 PM PDT 24 22392791 ps
T1094 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.558766412 Aug 07 05:36:23 PM PDT 24 Aug 07 05:36:25 PM PDT 24 241971449 ps
T1095 /workspace/coverage/cover_reg_top/4.edn_intr_test.4056867794 Aug 07 05:36:14 PM PDT 24 Aug 07 05:36:15 PM PDT 24 84220105 ps
T1096 /workspace/coverage/cover_reg_top/16.edn_intr_test.3769557816 Aug 07 05:36:32 PM PDT 24 Aug 07 05:36:33 PM PDT 24 12833407 ps
T1097 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.535291782 Aug 07 05:36:28 PM PDT 24 Aug 07 05:36:29 PM PDT 24 88061733 ps
T1098 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2829807522 Aug 07 05:36:37 PM PDT 24 Aug 07 05:36:39 PM PDT 24 38537291 ps
T1099 /workspace/coverage/cover_reg_top/25.edn_intr_test.1288981422 Aug 07 05:36:36 PM PDT 24 Aug 07 05:36:37 PM PDT 24 16006894 ps
T1100 /workspace/coverage/cover_reg_top/9.edn_tl_errors.625975990 Aug 07 05:36:19 PM PDT 24 Aug 07 05:36:23 PM PDT 24 114137319 ps
T1101 /workspace/coverage/cover_reg_top/14.edn_intr_test.44662941 Aug 07 05:36:26 PM PDT 24 Aug 07 05:36:27 PM PDT 24 25153955 ps
T1102 /workspace/coverage/cover_reg_top/49.edn_intr_test.3000676857 Aug 07 05:36:47 PM PDT 24 Aug 07 05:36:48 PM PDT 24 12882781 ps
T1103 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3080975227 Aug 07 05:36:40 PM PDT 24 Aug 07 05:36:41 PM PDT 24 24688049 ps
T1104 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.627617826 Aug 07 05:36:10 PM PDT 24 Aug 07 05:36:12 PM PDT 24 26727018 ps
T263 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3311337048 Aug 07 05:36:14 PM PDT 24 Aug 07 05:36:15 PM PDT 24 134753496 ps
T1105 /workspace/coverage/cover_reg_top/48.edn_intr_test.2078612260 Aug 07 05:36:46 PM PDT 24 Aug 07 05:36:47 PM PDT 24 25961932 ps
T1106 /workspace/coverage/cover_reg_top/3.edn_intr_test.1813176043 Aug 07 05:36:07 PM PDT 24 Aug 07 05:36:08 PM PDT 24 45710765 ps
T1107 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1533193668 Aug 07 05:36:39 PM PDT 24 Aug 07 05:36:40 PM PDT 24 167047599 ps
T1108 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1679361516 Aug 07 05:36:32 PM PDT 24 Aug 07 05:36:35 PM PDT 24 45758562 ps
T1109 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1035668912 Aug 07 05:36:13 PM PDT 24 Aug 07 05:36:16 PM PDT 24 84575232 ps
T1110 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2871099983 Aug 07 05:36:25 PM PDT 24 Aug 07 05:36:26 PM PDT 24 20268272 ps
T1111 /workspace/coverage/cover_reg_top/33.edn_intr_test.3401940630 Aug 07 05:36:41 PM PDT 24 Aug 07 05:36:42 PM PDT 24 34751637 ps
T1112 /workspace/coverage/cover_reg_top/19.edn_intr_test.1842608383 Aug 07 05:36:40 PM PDT 24 Aug 07 05:36:41 PM PDT 24 21006032 ps
T1113 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3374204951 Aug 07 05:36:08 PM PDT 24 Aug 07 05:36:09 PM PDT 24 27548118 ps
T1114 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4052410412 Aug 07 05:36:14 PM PDT 24 Aug 07 05:36:16 PM PDT 24 42016373 ps
T1115 /workspace/coverage/cover_reg_top/11.edn_tl_errors.723379255 Aug 07 05:36:19 PM PDT 24 Aug 07 05:36:21 PM PDT 24 465575662 ps
T1116 /workspace/coverage/cover_reg_top/27.edn_intr_test.4031222872 Aug 07 05:36:36 PM PDT 24 Aug 07 05:36:37 PM PDT 24 16020489 ps
T1117 /workspace/coverage/cover_reg_top/11.edn_intr_test.4226882990 Aug 07 05:36:19 PM PDT 24 Aug 07 05:36:20 PM PDT 24 78543638 ps
T1118 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1216299803 Aug 07 05:36:26 PM PDT 24 Aug 07 05:36:27 PM PDT 24 74392243 ps
T1119 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4124895827 Aug 07 05:36:25 PM PDT 24 Aug 07 05:36:28 PM PDT 24 136202752 ps
T1120 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4140648997 Aug 07 05:36:11 PM PDT 24 Aug 07 05:36:13 PM PDT 24 58689962 ps
T1121 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3993139884 Aug 07 05:36:14 PM PDT 24 Aug 07 05:36:15 PM PDT 24 48988373 ps
T1122 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3317797649 Aug 07 05:36:14 PM PDT 24 Aug 07 05:36:16 PM PDT 24 131863138 ps
T1123 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3362842990 Aug 07 05:36:19 PM PDT 24 Aug 07 05:36:20 PM PDT 24 29057052 ps
T1124 /workspace/coverage/cover_reg_top/17.edn_csr_rw.921136102 Aug 07 05:36:32 PM PDT 24 Aug 07 05:36:33 PM PDT 24 42237877 ps
T1125 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3309807173 Aug 07 05:36:33 PM PDT 24 Aug 07 05:36:34 PM PDT 24 28637474 ps

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2063860035
Short name T1
Test name
Test status
Simulation time 163385632849 ps
CPU time 1773.21 seconds
Started Aug 07 06:56:21 PM PDT 24
Finished Aug 07 07:25:55 PM PDT 24
Peak memory 225460 kb
Host smart-cedfae87-cb5a-4965-a31e-0626deca3b33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063860035 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2063860035
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.edn_genbits.2903549001
Short name T8
Test name
Test status
Simulation time 56377843 ps
CPU time 1.34 seconds
Started Aug 07 06:57:43 PM PDT 24
Finished Aug 07 06:57:45 PM PDT 24
Peak memory 219616 kb
Host smart-107aa03c-e4d4-4920-a757-f245e1680d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903549001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2903549001
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_alert.2743718837
Short name T2
Test name
Test status
Simulation time 89168429 ps
CPU time 1.24 seconds
Started Aug 07 06:55:37 PM PDT 24
Finished Aug 07 06:55:38 PM PDT 24
Peak memory 218284 kb
Host smart-6dbf2afa-7212-4724-87e7-b55427de7b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743718837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2743718837
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.1143519031
Short name T35
Test name
Test status
Simulation time 50508384 ps
CPU time 1.5 seconds
Started Aug 07 06:59:02 PM PDT 24
Finished Aug 07 06:59:03 PM PDT 24
Peak memory 218256 kb
Host smart-de5a436d-7e22-4919-9ea2-269fee8beeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143519031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1143519031
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_err.1427536005
Short name T6
Test name
Test status
Simulation time 22610931 ps
CPU time 1.06 seconds
Started Aug 07 06:55:42 PM PDT 24
Finished Aug 07 06:55:43 PM PDT 24
Peak memory 219788 kb
Host smart-c52a6209-e5ff-4272-8a80-96d03dcccb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427536005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1427536005
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2305193384
Short name T68
Test name
Test status
Simulation time 26628823 ps
CPU time 1.12 seconds
Started Aug 07 06:56:38 PM PDT 24
Finished Aug 07 06:56:39 PM PDT 24
Peak memory 217876 kb
Host smart-1a9c2fa8-6a6a-4976-855f-e23323c74b13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305193384 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2305193384
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/65.edn_err.3052289809
Short name T12
Test name
Test status
Simulation time 30989184 ps
CPU time 1.12 seconds
Started Aug 07 06:57:15 PM PDT 24
Finished Aug 07 06:57:16 PM PDT 24
Peak memory 223704 kb
Host smart-2f6fab8d-9710-482d-b68e-ff9616fc8f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052289809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3052289809
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/78.edn_alert.3386401276
Short name T28
Test name
Test status
Simulation time 52271457 ps
CPU time 1.21 seconds
Started Aug 07 06:57:26 PM PDT 24
Finished Aug 07 06:57:28 PM PDT 24
Peak memory 219748 kb
Host smart-93787028-64e3-4189-8625-8227e5eee180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386401276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3386401276
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/9.edn_regwen.552597842
Short name T81
Test name
Test status
Simulation time 35751375 ps
CPU time 0.85 seconds
Started Aug 07 06:55:34 PM PDT 24
Finished Aug 07 06:55:35 PM PDT 24
Peak memory 206720 kb
Host smart-e7fd23df-ec72-40ea-9925-4eaef316269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552597842 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.552597842
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/171.edn_genbits.3901886301
Short name T16
Test name
Test status
Simulation time 88814236 ps
CPU time 2.86 seconds
Started Aug 07 06:58:49 PM PDT 24
Finished Aug 07 06:58:52 PM PDT 24
Peak memory 219824 kb
Host smart-f9700762-1c79-4387-a124-2b20ba131087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901886301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3901886301
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1293161538
Short name T100
Test name
Test status
Simulation time 21458853 ps
CPU time 1.07 seconds
Started Aug 07 06:56:53 PM PDT 24
Finished Aug 07 06:56:54 PM PDT 24
Peak memory 215444 kb
Host smart-d1aa1c55-f27a-4f4f-a310-01735c29c6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293161538 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1293161538
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/36.edn_disable.3565031586
Short name T34
Test name
Test status
Simulation time 12292822 ps
CPU time 0.92 seconds
Started Aug 07 06:56:40 PM PDT 24
Finished Aug 07 06:56:41 PM PDT 24
Peak memory 216436 kb
Host smart-c8820e38-a49b-44d6-bd2c-53093251adbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565031586 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3565031586
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4236929509
Short name T286
Test name
Test status
Simulation time 296533743 ps
CPU time 2.39 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:10 PM PDT 24
Peak memory 206752 kb
Host smart-3d763361-5c9f-443e-8c83-b61d4af8fa69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236929509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4236929509
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/188.edn_alert.1130314226
Short name T154
Test name
Test status
Simulation time 88398514 ps
CPU time 1.24 seconds
Started Aug 07 06:59:03 PM PDT 24
Finished Aug 07 06:59:04 PM PDT 24
Peak memory 219440 kb
Host smart-19ad4ac6-7e45-4540-afa9-133abda0623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130314226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1130314226
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert.3757864156
Short name T191
Test name
Test status
Simulation time 56988158 ps
CPU time 1.22 seconds
Started Aug 07 06:56:39 PM PDT 24
Finished Aug 07 06:56:40 PM PDT 24
Peak memory 219188 kb
Host smart-ee5a56ad-2b12-427a-96a2-2c1ae0fc84ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757864156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3757864156
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/18.edn_intr.3896434698
Short name T72
Test name
Test status
Simulation time 28203827 ps
CPU time 0.94 seconds
Started Aug 07 06:55:58 PM PDT 24
Finished Aug 07 06:55:59 PM PDT 24
Peak memory 215016 kb
Host smart-452028dd-81e5-4041-aac9-830b7a1effb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896434698 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3896434698
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/168.edn_alert.1117026734
Short name T249
Test name
Test status
Simulation time 52065778 ps
CPU time 1.28 seconds
Started Aug 07 06:58:44 PM PDT 24
Finished Aug 07 06:58:46 PM PDT 24
Peak memory 218276 kb
Host smart-fcf0e9e7-c005-4f22-ac06-77a6218ac00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117026734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1117026734
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.748749795
Short name T124
Test name
Test status
Simulation time 45851078 ps
CPU time 1.18 seconds
Started Aug 07 06:56:27 PM PDT 24
Finished Aug 07 06:56:28 PM PDT 24
Peak memory 219264 kb
Host smart-ca1ae624-de5c-4011-b602-f82f3208e371
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748749795 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.748749795
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_intr.2042676041
Short name T75
Test name
Test status
Simulation time 39436420 ps
CPU time 0.87 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 06:56:23 PM PDT 24
Peak memory 215344 kb
Host smart-8294814a-c0b5-4868-8ffc-00e924b6a6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042676041 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2042676041
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/18.edn_disable.1580364312
Short name T204
Test name
Test status
Simulation time 30569001 ps
CPU time 0.84 seconds
Started Aug 07 06:55:58 PM PDT 24
Finished Aug 07 06:55:59 PM PDT 24
Peak memory 215132 kb
Host smart-65df3408-d6e3-423f-8f43-018c60239998
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580364312 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1580364312
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable.3286369489
Short name T170
Test name
Test status
Simulation time 18469289 ps
CPU time 0.82 seconds
Started Aug 07 06:55:45 PM PDT 24
Finished Aug 07 06:55:46 PM PDT 24
Peak memory 216232 kb
Host smart-7ca7462a-50df-441a-96f1-3f57a263f742
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286369489 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3286369489
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.2474400271
Short name T13
Test name
Test status
Simulation time 23786300 ps
CPU time 1.06 seconds
Started Aug 07 06:56:01 PM PDT 24
Finished Aug 07 06:56:03 PM PDT 24
Peak memory 223728 kb
Host smart-ce03db34-1ec8-4908-ad2b-fbbda06aa594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474400271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2474400271
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2373522044
Short name T148
Test name
Test status
Simulation time 27267704 ps
CPU time 1.11 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 06:56:50 PM PDT 24
Peak memory 219256 kb
Host smart-acf0ace4-972f-4452-84b6-384adc0b8c4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373522044 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2373522044
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2055166213
Short name T257
Test name
Test status
Simulation time 17361075 ps
CPU time 1.02 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:09 PM PDT 24
Peak memory 206660 kb
Host smart-d62cd0ce-fb79-4ff9-9faa-0deb8c4e4e1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055166213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2055166213
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/114.edn_alert.3080852717
Short name T87
Test name
Test status
Simulation time 73891930 ps
CPU time 1.18 seconds
Started Aug 07 06:57:52 PM PDT 24
Finished Aug 07 06:57:54 PM PDT 24
Peak memory 218276 kb
Host smart-225f5c41-d7b8-4916-b0d5-add78de65df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080852717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3080852717
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/162.edn_alert.1756063826
Short name T183
Test name
Test status
Simulation time 22875516 ps
CPU time 1.2 seconds
Started Aug 07 06:58:40 PM PDT 24
Finished Aug 07 06:58:42 PM PDT 24
Peak memory 219520 kb
Host smart-7cb14960-a6bf-4bcc-bc47-d9096014b680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756063826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1756063826
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert.2493212359
Short name T787
Test name
Test status
Simulation time 75983682 ps
CPU time 1.17 seconds
Started Aug 07 06:55:28 PM PDT 24
Finished Aug 07 06:55:29 PM PDT 24
Peak memory 219028 kb
Host smart-9bdce1ca-6e3b-4ed4-9d17-62c54f46a105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493212359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2493212359
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert.3834069126
Short name T420
Test name
Test status
Simulation time 28815084 ps
CPU time 1.24 seconds
Started Aug 07 06:56:54 PM PDT 24
Finished Aug 07 06:56:55 PM PDT 24
Peak memory 218172 kb
Host smart-bd56abe7-5f30-4afe-ab7c-71dab8315b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834069126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3834069126
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/64.edn_alert.2129177397
Short name T495
Test name
Test status
Simulation time 94823200 ps
CPU time 1.24 seconds
Started Aug 07 06:57:14 PM PDT 24
Finished Aug 07 06:57:16 PM PDT 24
Peak memory 218800 kb
Host smart-190ab6c2-56b7-4135-9287-82106dd9b1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129177397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2129177397
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/139.edn_alert.2749279257
Short name T14
Test name
Test status
Simulation time 27651863 ps
CPU time 1.24 seconds
Started Aug 07 06:58:18 PM PDT 24
Finished Aug 07 06:58:19 PM PDT 24
Peak memory 220392 kb
Host smart-13a2c6ad-d4ae-4f53-8e40-4882cf6a549f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749279257 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2749279257
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert.875806297
Short name T446
Test name
Test status
Simulation time 29502934 ps
CPU time 1.31 seconds
Started Aug 07 06:56:18 PM PDT 24
Finished Aug 07 06:56:19 PM PDT 24
Peak memory 218816 kb
Host smart-28156e8a-90d2-45cc-a718-dd8a97b01aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875806297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.875806297
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/254.edn_genbits.3947252101
Short name T372
Test name
Test status
Simulation time 59665759 ps
CPU time 1.39 seconds
Started Aug 07 06:59:40 PM PDT 24
Finished Aug 07 06:59:41 PM PDT 24
Peak memory 219720 kb
Host smart-7b47109d-7a8d-4a70-aa99-4f58b8e8270e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947252101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3947252101
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2305277836
Short name T32
Test name
Test status
Simulation time 89435864 ps
CPU time 1.32 seconds
Started Aug 07 06:58:52 PM PDT 24
Finished Aug 07 06:58:53 PM PDT 24
Peak memory 218444 kb
Host smart-434450f8-084e-431e-bc8c-102672828ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305277836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2305277836
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_disable.795939582
Short name T209
Test name
Test status
Simulation time 12472948 ps
CPU time 0.97 seconds
Started Aug 07 06:55:40 PM PDT 24
Finished Aug 07 06:55:41 PM PDT 24
Peak memory 216332 kb
Host smart-72db240f-09e7-4f56-8695-d1f065a8c9d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795939582 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.795939582
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable.1851105096
Short name T207
Test name
Test status
Simulation time 11624027 ps
CPU time 0.92 seconds
Started Aug 07 06:55:27 PM PDT 24
Finished Aug 07 06:55:28 PM PDT 24
Peak memory 216216 kb
Host smart-6a84f491-fd70-4ed5-b100-7e28f4933eff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851105096 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1851105096
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable.145836664
Short name T972
Test name
Test status
Simulation time 11664897 ps
CPU time 0.86 seconds
Started Aug 07 06:55:20 PM PDT 24
Finished Aug 07 06:55:20 PM PDT 24
Peak memory 216204 kb
Host smart-235cb8d0-8420-4b3e-99fd-2b282afc6f86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145836664 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.145836664
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2246231100
Short name T731
Test name
Test status
Simulation time 28282962 ps
CPU time 1.09 seconds
Started Aug 07 06:55:20 PM PDT 24
Finished Aug 07 06:55:22 PM PDT 24
Peak memory 218412 kb
Host smart-c7b7ba5a-a694-4a49-8327-1ad38afeba9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246231100 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2246231100
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_alert.228316044
Short name T128
Test name
Test status
Simulation time 27149022 ps
CPU time 1.26 seconds
Started Aug 07 06:55:42 PM PDT 24
Finished Aug 07 06:55:44 PM PDT 24
Peak memory 219052 kb
Host smart-13574167-6713-489e-be0d-4ea7bca4afb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228316044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.228316044
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3973462630
Short name T563
Test name
Test status
Simulation time 43842829 ps
CPU time 1.3 seconds
Started Aug 07 06:55:42 PM PDT 24
Finished Aug 07 06:55:43 PM PDT 24
Peak memory 216896 kb
Host smart-2ab6c75b-5b03-4a49-945b-94d0a390d2ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973462630 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3973462630
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/123.edn_alert.2345005812
Short name T559
Test name
Test status
Simulation time 35716909 ps
CPU time 1.05 seconds
Started Aug 07 06:58:04 PM PDT 24
Finished Aug 07 06:58:05 PM PDT 24
Peak memory 220312 kb
Host smart-e76ffd84-11c7-4a16-903e-9be3f4dace7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345005812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2345005812
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/131.edn_alert.3934917338
Short name T180
Test name
Test status
Simulation time 83340976 ps
CPU time 1.17 seconds
Started Aug 07 06:58:14 PM PDT 24
Finished Aug 07 06:58:16 PM PDT 24
Peak memory 218032 kb
Host smart-7785c5a8-308f-4118-8edf-a87627f3f919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934917338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3934917338
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/133.edn_alert.3169860667
Short name T295
Test name
Test status
Simulation time 62466982 ps
CPU time 1.23 seconds
Started Aug 07 06:58:11 PM PDT 24
Finished Aug 07 06:58:13 PM PDT 24
Peak memory 215300 kb
Host smart-aee46de2-7f12-430a-a558-8a150c4f53bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169860667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3169860667
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/146.edn_alert.338558286
Short name T792
Test name
Test status
Simulation time 25607134 ps
CPU time 1.16 seconds
Started Aug 07 06:58:22 PM PDT 24
Finished Aug 07 06:58:23 PM PDT 24
Peak memory 218176 kb
Host smart-10b2c5b9-31a3-45ea-a2cc-f6472f7d6de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338558286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.338558286
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.4294025963
Short name T900
Test name
Test status
Simulation time 29735089 ps
CPU time 1.29 seconds
Started Aug 07 06:55:55 PM PDT 24
Finished Aug 07 06:55:56 PM PDT 24
Peak memory 216692 kb
Host smart-353ed5f4-0020-46cf-adf0-383363556f50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294025963 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.4294025963
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_disable.4198940703
Short name T761
Test name
Test status
Simulation time 30502161 ps
CPU time 0.86 seconds
Started Aug 07 06:56:00 PM PDT 24
Finished Aug 07 06:56:01 PM PDT 24
Peak memory 216232 kb
Host smart-9b11c52c-b6f2-4c6f-b641-469f4eb92f2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198940703 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.4198940703
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable.3730759193
Short name T951
Test name
Test status
Simulation time 34837173 ps
CPU time 0.88 seconds
Started Aug 07 06:56:06 PM PDT 24
Finished Aug 07 06:56:07 PM PDT 24
Peak memory 219636 kb
Host smart-dc2fd761-15ee-447f-b5b3-f4b6394c01a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730759193 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3730759193
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.1260584571
Short name T887
Test name
Test status
Simulation time 45287043 ps
CPU time 0.95 seconds
Started Aug 07 06:56:17 PM PDT 24
Finished Aug 07 06:56:18 PM PDT 24
Peak memory 229140 kb
Host smart-0055f833-8043-4878-baca-d55f8039dd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260584571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1260584571
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/38.edn_disable.2388817139
Short name T201
Test name
Test status
Simulation time 28405458 ps
CPU time 0.84 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 06:56:50 PM PDT 24
Peak memory 216188 kb
Host smart-ac1ead23-f256-4122-9561-e76143a56438
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388817139 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2388817139
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable.2127761033
Short name T198
Test name
Test status
Simulation time 56691290 ps
CPU time 0.91 seconds
Started Aug 07 06:56:57 PM PDT 24
Finished Aug 07 06:56:58 PM PDT 24
Peak memory 215100 kb
Host smart-a7763912-a630-4434-8510-3b505b7f3931
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127761033 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2127761033
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable.130484043
Short name T211
Test name
Test status
Simulation time 39709089 ps
CPU time 0.85 seconds
Started Aug 07 06:56:59 PM PDT 24
Finished Aug 07 06:57:00 PM PDT 24
Peak memory 218028 kb
Host smart-4f414a7f-7d40-4cac-a7ee-5d61927fa523
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130484043 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.130484043
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/14.edn_alert_test.1268783993
Short name T387
Test name
Test status
Simulation time 15978399 ps
CPU time 0.92 seconds
Started Aug 07 06:55:48 PM PDT 24
Finished Aug 07 06:55:49 PM PDT 24
Peak memory 206324 kb
Host smart-2743f313-d6b8-4ef8-8159-b7b78938e417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268783993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1268783993
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/252.edn_genbits.3393719038
Short name T24
Test name
Test status
Simulation time 213310198 ps
CPU time 1.01 seconds
Started Aug 07 06:59:34 PM PDT 24
Finished Aug 07 06:59:36 PM PDT 24
Peak memory 217028 kb
Host smart-d7b0abd5-a31f-4612-bdfb-7265a76600db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393719038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3393719038
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.3118674374
Short name T30
Test name
Test status
Simulation time 74984736 ps
CPU time 2.69 seconds
Started Aug 07 06:58:39 PM PDT 24
Finished Aug 07 06:58:42 PM PDT 24
Peak memory 218628 kb
Host smart-3c535482-83af-438d-b3be-5696731610e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118674374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3118674374
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_genbits.3444738125
Short name T457
Test name
Test status
Simulation time 48104727 ps
CPU time 1.63 seconds
Started Aug 07 06:57:09 PM PDT 24
Finished Aug 07 06:57:10 PM PDT 24
Peak memory 219816 kb
Host smart-d56f9dc2-3855-4192-b485-c6a411e8d5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444738125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3444738125
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2909683703
Short name T564
Test name
Test status
Simulation time 14176055771 ps
CPU time 333.51 seconds
Started Aug 07 06:55:44 PM PDT 24
Finished Aug 07 07:01:18 PM PDT 24
Peak memory 222660 kb
Host smart-ccebfc18-aae0-42f7-ac21-a33b87ea24b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909683703 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2909683703
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.4122321853
Short name T289
Test name
Test status
Simulation time 29720938 ps
CPU time 1.26 seconds
Started Aug 07 06:58:02 PM PDT 24
Finished Aug 07 06:58:03 PM PDT 24
Peak memory 219592 kb
Host smart-fdf5b03a-3bb4-4cd1-9975-bc1fbc553e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122321853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.4122321853
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4134292294
Short name T231
Test name
Test status
Simulation time 224117242191 ps
CPU time 2775.93 seconds
Started Aug 07 06:56:12 PM PDT 24
Finished Aug 07 07:42:28 PM PDT 24
Peak memory 228652 kb
Host smart-9dc52d84-1b56-4877-801d-40a9cfb3c5bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134292294 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4134292294
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.edn_genbits.3103407932
Short name T333
Test name
Test status
Simulation time 50901458 ps
CPU time 1.81 seconds
Started Aug 07 06:58:37 PM PDT 24
Finished Aug 07 06:58:39 PM PDT 24
Peak memory 218276 kb
Host smart-ddc16d16-1958-48fe-bf00-c40556743395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103407932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3103407932
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1950163570
Short name T266
Test name
Test status
Simulation time 13895083 ps
CPU time 0.88 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:09 PM PDT 24
Peak memory 206624 kb
Host smart-c8562630-1d29-473e-8e10-a1806db50a8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950163570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1950163570
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2219683993
Short name T284
Test name
Test status
Simulation time 325078487 ps
CPU time 2.39 seconds
Started Aug 07 05:36:23 PM PDT 24
Finished Aug 07 05:36:26 PM PDT 24
Peak memory 206744 kb
Host smart-be4d0c43-4e9e-4a0a-a741-b56d655dfb01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219683993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2219683993
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/102.edn_genbits.1864324897
Short name T315
Test name
Test status
Simulation time 54350346 ps
CPU time 1.18 seconds
Started Aug 07 06:57:54 PM PDT 24
Finished Aug 07 06:57:55 PM PDT 24
Peak memory 216972 kb
Host smart-f32c0394-555f-45db-97b1-0f76de74dff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864324897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1864324897
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3728751920
Short name T913
Test name
Test status
Simulation time 48945106 ps
CPU time 1.33 seconds
Started Aug 07 06:57:54 PM PDT 24
Finished Aug 07 06:57:55 PM PDT 24
Peak memory 216872 kb
Host smart-9f3667b9-5883-487d-be90-2c8f370f7b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728751920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3728751920
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.2757895369
Short name T577
Test name
Test status
Simulation time 108404912 ps
CPU time 1.18 seconds
Started Aug 07 06:57:58 PM PDT 24
Finished Aug 07 06:58:00 PM PDT 24
Peak memory 220220 kb
Host smart-45823674-b7d7-41f8-aec7-59329d4d1209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757895369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.2757895369
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.4012682674
Short name T955
Test name
Test status
Simulation time 188087021 ps
CPU time 1.51 seconds
Started Aug 07 06:58:27 PM PDT 24
Finished Aug 07 06:58:29 PM PDT 24
Peak memory 218344 kb
Host smart-aa608831-69d2-4576-a261-4a2a0131991f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012682674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.4012682674
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2111933091
Short name T301
Test name
Test status
Simulation time 38269041 ps
CPU time 1.53 seconds
Started Aug 07 06:58:43 PM PDT 24
Finished Aug 07 06:58:45 PM PDT 24
Peak memory 218248 kb
Host smart-cee83a7b-9890-4453-812d-340a9529c22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111933091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2111933091
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3094350718
Short name T766
Test name
Test status
Simulation time 134824409 ps
CPU time 1.32 seconds
Started Aug 07 06:58:45 PM PDT 24
Finished Aug 07 06:58:47 PM PDT 24
Peak memory 218304 kb
Host smart-0ad940e7-1f1d-492b-a004-ef56197a682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094350718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3094350718
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.7233762
Short name T309
Test name
Test status
Simulation time 51346868 ps
CPU time 1.24 seconds
Started Aug 07 06:58:52 PM PDT 24
Finished Aug 07 06:58:53 PM PDT 24
Peak memory 217360 kb
Host smart-b171bd01-92b5-48d4-aca2-607e2c7be1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7233762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.7233762
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.930998596
Short name T303
Test name
Test status
Simulation time 118625527 ps
CPU time 1.26 seconds
Started Aug 07 06:58:58 PM PDT 24
Finished Aug 07 06:58:59 PM PDT 24
Peak memory 219916 kb
Host smart-7ea58dec-97c7-432e-bd33-0952a5bfe749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930998596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.930998596
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.685856298
Short name T321
Test name
Test status
Simulation time 48843575 ps
CPU time 1.3 seconds
Started Aug 07 06:59:19 PM PDT 24
Finished Aug 07 06:59:20 PM PDT 24
Peak memory 219732 kb
Host smart-68c5a838-33e5-4586-a0ff-a480dae1dea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685856298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.685856298
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.925452887
Short name T329
Test name
Test status
Simulation time 95529419 ps
CPU time 1.7 seconds
Started Aug 07 06:59:38 PM PDT 24
Finished Aug 07 06:59:40 PM PDT 24
Peak memory 218388 kb
Host smart-33c675ee-2700-40db-82f2-27d75b21c1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925452887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.925452887
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_genbits.1515870731
Short name T324
Test name
Test status
Simulation time 39598361 ps
CPU time 1.69 seconds
Started Aug 07 06:56:11 PM PDT 24
Finished Aug 07 06:56:13 PM PDT 24
Peak memory 218292 kb
Host smart-d865dd25-e1ff-4ad2-9f19-d49c196efce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515870731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1515870731
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2943358752
Short name T619
Test name
Test status
Simulation time 28118157 ps
CPU time 0.92 seconds
Started Aug 07 06:55:17 PM PDT 24
Finished Aug 07 06:55:18 PM PDT 24
Peak memory 215624 kb
Host smart-0e6b1509-ac0c-45c0-bc49-95a0c157c75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943358752 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2943358752
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/1.edn_intr.2832041656
Short name T98
Test name
Test status
Simulation time 57319528 ps
CPU time 0.87 seconds
Started Aug 07 06:55:16 PM PDT 24
Finished Aug 07 06:55:17 PM PDT 24
Peak memory 215092 kb
Host smart-46aec134-8f40-4200-80ff-d647ffce8feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832041656 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2832041656
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1878914994
Short name T256
Test name
Test status
Simulation time 60843962 ps
CPU time 1.22 seconds
Started Aug 07 05:36:06 PM PDT 24
Finished Aug 07 05:36:08 PM PDT 24
Peak memory 206704 kb
Host smart-fd690970-8bbd-44d7-88e1-5ddc99184787
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878914994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1878914994
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2893334187
Short name T1041
Test name
Test status
Simulation time 520809100 ps
CPU time 6.43 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:15 PM PDT 24
Peak memory 206624 kb
Host smart-cff5e016-0aa8-44d8-b807-41e9ea3078cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893334187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2893334187
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1852248187
Short name T1000
Test name
Test status
Simulation time 97478620 ps
CPU time 1.28 seconds
Started Aug 07 05:36:12 PM PDT 24
Finished Aug 07 05:36:13 PM PDT 24
Peak memory 214920 kb
Host smart-35bd46a0-dfb3-4929-ab6f-befc7a98f497
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852248187 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1852248187
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2931066542
Short name T1008
Test name
Test status
Simulation time 58769748 ps
CPU time 0.81 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:09 PM PDT 24
Peak memory 206548 kb
Host smart-3739da3c-c30e-4e4a-96ed-1aaac93ac0a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931066542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2931066542
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2359003297
Short name T990
Test name
Test status
Simulation time 28028578 ps
CPU time 0.84 seconds
Started Aug 07 05:36:06 PM PDT 24
Finished Aug 07 05:36:07 PM PDT 24
Peak memory 206492 kb
Host smart-89e2bddf-b6ee-4763-bd5a-43582adf500f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359003297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2359003297
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4140648997
Short name T1120
Test name
Test status
Simulation time 58689962 ps
CPU time 1.14 seconds
Started Aug 07 05:36:11 PM PDT 24
Finished Aug 07 05:36:13 PM PDT 24
Peak memory 206704 kb
Host smart-eb85cf0d-338f-47b8-9985-2658ae918e43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140648997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.4140648997
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3606747345
Short name T1050
Test name
Test status
Simulation time 499000570 ps
CPU time 2.23 seconds
Started Aug 07 05:36:02 PM PDT 24
Finished Aug 07 05:36:05 PM PDT 24
Peak memory 215120 kb
Host smart-727a1787-5924-4c43-bc4a-7d78577cdaaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606747345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3606747345
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2768312944
Short name T1057
Test name
Test status
Simulation time 131086614 ps
CPU time 0.97 seconds
Started Aug 07 05:36:07 PM PDT 24
Finished Aug 07 05:36:08 PM PDT 24
Peak memory 206656 kb
Host smart-0347d516-4d3c-498b-9bad-8d627712d3f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768312944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2768312944
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3354886225
Short name T1015
Test name
Test status
Simulation time 675632167 ps
CPU time 4.9 seconds
Started Aug 07 05:36:09 PM PDT 24
Finished Aug 07 05:36:14 PM PDT 24
Peak memory 206552 kb
Host smart-b2e2520e-e3dc-4ace-9845-858e1afb2eed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354886225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3354886225
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2389081308
Short name T1048
Test name
Test status
Simulation time 42294169 ps
CPU time 0.89 seconds
Started Aug 07 05:36:09 PM PDT 24
Finished Aug 07 05:36:10 PM PDT 24
Peak memory 206632 kb
Host smart-1367fa34-8b04-4f0f-a4b7-1b6ac93faf07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389081308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2389081308
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.627617826
Short name T1104
Test name
Test status
Simulation time 26727018 ps
CPU time 1.6 seconds
Started Aug 07 05:36:10 PM PDT 24
Finished Aug 07 05:36:12 PM PDT 24
Peak memory 214996 kb
Host smart-ef8b5893-7514-464a-a767-819f5a8dc23f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627617826 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.627617826
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.330557992
Short name T1030
Test name
Test status
Simulation time 18894487 ps
CPU time 0.97 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:09 PM PDT 24
Peak memory 206524 kb
Host smart-b1309b17-6961-460b-a073-8420f8871d5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330557992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.330557992
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2785216834
Short name T1072
Test name
Test status
Simulation time 125143762 ps
CPU time 1.11 seconds
Started Aug 07 05:36:09 PM PDT 24
Finished Aug 07 05:36:10 PM PDT 24
Peak memory 206752 kb
Host smart-ce7230ec-2298-4dc8-8192-38721dc4fc0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785216834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2785216834
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.192058474
Short name T1028
Test name
Test status
Simulation time 112118813 ps
CPU time 3.69 seconds
Started Aug 07 05:36:10 PM PDT 24
Finished Aug 07 05:36:13 PM PDT 24
Peak memory 214824 kb
Host smart-06185461-372f-400f-b2fd-71d70779db6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192058474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.192058474
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.401670969
Short name T1049
Test name
Test status
Simulation time 85369518 ps
CPU time 2.53 seconds
Started Aug 07 05:36:09 PM PDT 24
Finished Aug 07 05:36:11 PM PDT 24
Peak memory 206840 kb
Host smart-c6a0bc2d-838f-4fe3-9fe5-9a1e01accfaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401670969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.401670969
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.681309157
Short name T1001
Test name
Test status
Simulation time 279421759 ps
CPU time 1.38 seconds
Started Aug 07 05:36:20 PM PDT 24
Finished Aug 07 05:36:22 PM PDT 24
Peak memory 215012 kb
Host smart-2c2ffbea-b47e-48ab-9922-c827049bbac6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681309157 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.681309157
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2142596832
Short name T258
Test name
Test status
Simulation time 22972607 ps
CPU time 0.85 seconds
Started Aug 07 05:36:24 PM PDT 24
Finished Aug 07 05:36:25 PM PDT 24
Peak memory 206568 kb
Host smart-ec844f70-0bd8-4afb-9735-a10791234284
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142596832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2142596832
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.91647524
Short name T1011
Test name
Test status
Simulation time 17660893 ps
CPU time 1 seconds
Started Aug 07 05:36:20 PM PDT 24
Finished Aug 07 05:36:22 PM PDT 24
Peak memory 206516 kb
Host smart-cb8b29be-3003-47dc-8236-c3566283aef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91647524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.91647524
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2800098565
Short name T264
Test name
Test status
Simulation time 70286779 ps
CPU time 1.27 seconds
Started Aug 07 05:36:18 PM PDT 24
Finished Aug 07 05:36:19 PM PDT 24
Peak memory 206732 kb
Host smart-775c5b79-6e5c-40bc-ae9a-6c9d32aa3537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800098565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2800098565
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1813054342
Short name T994
Test name
Test status
Simulation time 175169672 ps
CPU time 2.14 seconds
Started Aug 07 05:36:18 PM PDT 24
Finished Aug 07 05:36:21 PM PDT 24
Peak memory 214916 kb
Host smart-88977fc8-6394-4efb-8f34-7e268b2b1574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813054342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1813054342
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3567058717
Short name T1046
Test name
Test status
Simulation time 61908141 ps
CPU time 1.18 seconds
Started Aug 07 05:36:24 PM PDT 24
Finished Aug 07 05:36:26 PM PDT 24
Peak memory 214892 kb
Host smart-ff143faa-f0b8-4eaf-ae53-34a7a0087342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567058717 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3567058717
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1617677172
Short name T1086
Test name
Test status
Simulation time 179734364 ps
CPU time 0.86 seconds
Started Aug 07 05:36:20 PM PDT 24
Finished Aug 07 05:36:21 PM PDT 24
Peak memory 206712 kb
Host smart-930addd3-e210-4392-be4d-81f1802c1eaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617677172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1617677172
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.4226882990
Short name T1117
Test name
Test status
Simulation time 78543638 ps
CPU time 0.82 seconds
Started Aug 07 05:36:19 PM PDT 24
Finished Aug 07 05:36:20 PM PDT 24
Peak memory 206460 kb
Host smart-cc2f5052-2e8b-4aae-adf7-7e06cc582cb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226882990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.4226882990
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1346478202
Short name T268
Test name
Test status
Simulation time 201787518 ps
CPU time 1.34 seconds
Started Aug 07 05:36:21 PM PDT 24
Finished Aug 07 05:36:23 PM PDT 24
Peak memory 206696 kb
Host smart-8cf803cd-b46d-49ea-bc66-1f43dcf6424f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346478202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1346478202
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.723379255
Short name T1115
Test name
Test status
Simulation time 465575662 ps
CPU time 2.15 seconds
Started Aug 07 05:36:19 PM PDT 24
Finished Aug 07 05:36:21 PM PDT 24
Peak memory 215096 kb
Host smart-749930c9-5a56-452e-966a-a2587fcae2bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723379255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.723379255
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4278207905
Short name T219
Test name
Test status
Simulation time 842044502 ps
CPU time 2.45 seconds
Started Aug 07 05:36:18 PM PDT 24
Finished Aug 07 05:36:21 PM PDT 24
Peak memory 214980 kb
Host smart-716437b9-8806-44ee-8b37-808a9ec295f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278207905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.4278207905
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1216299803
Short name T1118
Test name
Test status
Simulation time 74392243 ps
CPU time 1.43 seconds
Started Aug 07 05:36:26 PM PDT 24
Finished Aug 07 05:36:27 PM PDT 24
Peak memory 215052 kb
Host smart-5bf26c78-09fb-46f8-bf05-68dbb5ba2751
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216299803 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1216299803
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2311149011
Short name T1023
Test name
Test status
Simulation time 100896282 ps
CPU time 0.87 seconds
Started Aug 07 05:36:33 PM PDT 24
Finished Aug 07 05:36:34 PM PDT 24
Peak memory 206636 kb
Host smart-fe0692d5-002b-43d9-8b2f-15b5af7f6c77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311149011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2311149011
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3884909649
Short name T1019
Test name
Test status
Simulation time 31669309 ps
CPU time 0.82 seconds
Started Aug 07 05:36:25 PM PDT 24
Finished Aug 07 05:36:26 PM PDT 24
Peak memory 206420 kb
Host smart-0659a002-f115-487f-a94e-b09a01be0c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884909649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3884909649
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.882260810
Short name T1061
Test name
Test status
Simulation time 21844513 ps
CPU time 1.12 seconds
Started Aug 07 05:36:28 PM PDT 24
Finished Aug 07 05:36:29 PM PDT 24
Peak memory 206756 kb
Host smart-75ae4593-7226-4c57-8eb0-5369ff7ae91c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882260810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.882260810
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2349288401
Short name T1077
Test name
Test status
Simulation time 249122053 ps
CPU time 2.68 seconds
Started Aug 07 05:36:20 PM PDT 24
Finished Aug 07 05:36:22 PM PDT 24
Peak memory 214856 kb
Host smart-8fb3fb38-eff2-4c6a-819b-4b26b0145f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349288401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2349288401
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4065892325
Short name T220
Test name
Test status
Simulation time 58567096 ps
CPU time 1.73 seconds
Started Aug 07 05:36:30 PM PDT 24
Finished Aug 07 05:36:32 PM PDT 24
Peak memory 206848 kb
Host smart-20bb9f81-824e-4a56-8bbb-3a743c94c1d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065892325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4065892325
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.535291782
Short name T1097
Test name
Test status
Simulation time 88061733 ps
CPU time 1.48 seconds
Started Aug 07 05:36:28 PM PDT 24
Finished Aug 07 05:36:29 PM PDT 24
Peak memory 214928 kb
Host smart-1a2e02ba-2b9a-4214-b414-619e97b48fe4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535291782 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.535291782
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2462482838
Short name T1068
Test name
Test status
Simulation time 29053269 ps
CPU time 0.87 seconds
Started Aug 07 05:36:26 PM PDT 24
Finished Aug 07 05:36:27 PM PDT 24
Peak memory 206484 kb
Host smart-af01e0d7-7c66-4960-8ef5-64d606bfa554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462482838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2462482838
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1883181586
Short name T999
Test name
Test status
Simulation time 14301868 ps
CPU time 0.92 seconds
Started Aug 07 05:36:30 PM PDT 24
Finished Aug 07 05:36:31 PM PDT 24
Peak memory 206592 kb
Host smart-29fb198a-08df-4d9a-9116-d8e51876bfad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883181586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1883181586
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2230235053
Short name T269
Test name
Test status
Simulation time 22803935 ps
CPU time 1.16 seconds
Started Aug 07 05:36:25 PM PDT 24
Finished Aug 07 05:36:27 PM PDT 24
Peak memory 206632 kb
Host smart-652e204b-7ce9-459a-851b-c961f5366047
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230235053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2230235053
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.988881377
Short name T1081
Test name
Test status
Simulation time 78674615 ps
CPU time 2.86 seconds
Started Aug 07 05:36:27 PM PDT 24
Finished Aug 07 05:36:30 PM PDT 24
Peak memory 214976 kb
Host smart-10fe7d14-4ff1-45d6-96a7-473981423971
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988881377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.988881377
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3277427365
Short name T285
Test name
Test status
Simulation time 229161233 ps
CPU time 1.49 seconds
Started Aug 07 05:36:28 PM PDT 24
Finished Aug 07 05:36:30 PM PDT 24
Peak memory 206672 kb
Host smart-85797227-c03e-4581-b0e3-d88babcadf10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277427365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3277427365
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4151416770
Short name T1065
Test name
Test status
Simulation time 131208804 ps
CPU time 1.49 seconds
Started Aug 07 05:36:32 PM PDT 24
Finished Aug 07 05:36:34 PM PDT 24
Peak memory 214984 kb
Host smart-1d2d99ce-e7ac-449d-a481-dd9e7b50e039
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151416770 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.4151416770
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3117821711
Short name T1045
Test name
Test status
Simulation time 45901394 ps
CPU time 0.87 seconds
Started Aug 07 05:36:28 PM PDT 24
Finished Aug 07 05:36:29 PM PDT 24
Peak memory 206620 kb
Host smart-9b000d96-5509-462f-871a-2e4c1c6391be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117821711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3117821711
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.44662941
Short name T1101
Test name
Test status
Simulation time 25153955 ps
CPU time 0.91 seconds
Started Aug 07 05:36:26 PM PDT 24
Finished Aug 07 05:36:27 PM PDT 24
Peak memory 206496 kb
Host smart-eeaa30cc-6199-498b-8250-6a172b8cbe62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44662941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.44662941
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3657403250
Short name T1032
Test name
Test status
Simulation time 15519709 ps
CPU time 0.97 seconds
Started Aug 07 05:36:28 PM PDT 24
Finished Aug 07 05:36:29 PM PDT 24
Peak memory 206676 kb
Host smart-fde347e3-f44a-48d4-aaa8-2848bbf097d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657403250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3657403250
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1679361516
Short name T1108
Test name
Test status
Simulation time 45758562 ps
CPU time 2.08 seconds
Started Aug 07 05:36:32 PM PDT 24
Finished Aug 07 05:36:35 PM PDT 24
Peak memory 214956 kb
Host smart-ddcfdb2a-11f9-41c2-8053-a0d15d1f86b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679361516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1679361516
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3375970413
Short name T1037
Test name
Test status
Simulation time 73616250 ps
CPU time 1.51 seconds
Started Aug 07 05:36:26 PM PDT 24
Finished Aug 07 05:36:28 PM PDT 24
Peak memory 206960 kb
Host smart-704c77c8-f5dc-4877-a90a-c7a1ce9710b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375970413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3375970413
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.459878813
Short name T1069
Test name
Test status
Simulation time 14342007 ps
CPU time 0.96 seconds
Started Aug 07 05:36:26 PM PDT 24
Finished Aug 07 05:36:28 PM PDT 24
Peak memory 206776 kb
Host smart-36edaec5-66cb-4c3c-b9f4-98689cd9c054
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459878813 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.459878813
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2871099983
Short name T1110
Test name
Test status
Simulation time 20268272 ps
CPU time 0.82 seconds
Started Aug 07 05:36:25 PM PDT 24
Finished Aug 07 05:36:26 PM PDT 24
Peak memory 206564 kb
Host smart-4bff0ec7-2361-46f2-b12e-7925825799f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871099983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2871099983
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2287175095
Short name T996
Test name
Test status
Simulation time 24808262 ps
CPU time 0.85 seconds
Started Aug 07 05:36:24 PM PDT 24
Finished Aug 07 05:36:25 PM PDT 24
Peak memory 206480 kb
Host smart-bbe67acb-3ee3-4e91-b40d-adb4cb1190d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287175095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2287175095
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2876698899
Short name T272
Test name
Test status
Simulation time 95167392 ps
CPU time 1.1 seconds
Started Aug 07 05:36:25 PM PDT 24
Finished Aug 07 05:36:26 PM PDT 24
Peak memory 206652 kb
Host smart-23919f19-512b-4966-9a54-a8f856b82861
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876698899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2876698899
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.821207692
Short name T1092
Test name
Test status
Simulation time 95980937 ps
CPU time 3.73 seconds
Started Aug 07 05:36:30 PM PDT 24
Finished Aug 07 05:36:34 PM PDT 24
Peak memory 214960 kb
Host smart-1e94aa29-8f99-4a85-869f-ff116bd9b351
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821207692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.821207692
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4124895827
Short name T1119
Test name
Test status
Simulation time 136202752 ps
CPU time 2.41 seconds
Started Aug 07 05:36:25 PM PDT 24
Finished Aug 07 05:36:28 PM PDT 24
Peak memory 206768 kb
Host smart-e0bd02fe-ca61-4da2-9519-d56c057c6271
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124895827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.4124895827
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3934663051
Short name T1038
Test name
Test status
Simulation time 23687678 ps
CPU time 1.26 seconds
Started Aug 07 05:36:34 PM PDT 24
Finished Aug 07 05:36:36 PM PDT 24
Peak memory 215028 kb
Host smart-9082f57d-83a8-4391-8ae7-50483c29230e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934663051 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3934663051
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1744501596
Short name T993
Test name
Test status
Simulation time 37374330 ps
CPU time 0.9 seconds
Started Aug 07 05:36:32 PM PDT 24
Finished Aug 07 05:36:33 PM PDT 24
Peak memory 206636 kb
Host smart-9ee693ba-989d-429a-8e7e-f0b5f888e1b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744501596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1744501596
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3769557816
Short name T1096
Test name
Test status
Simulation time 12833407 ps
CPU time 0.85 seconds
Started Aug 07 05:36:32 PM PDT 24
Finished Aug 07 05:36:33 PM PDT 24
Peak memory 206520 kb
Host smart-7074772b-ad78-477b-8169-f6ad493c5812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769557816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3769557816
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3996224868
Short name T270
Test name
Test status
Simulation time 22580109 ps
CPU time 1.08 seconds
Started Aug 07 05:36:37 PM PDT 24
Finished Aug 07 05:36:38 PM PDT 24
Peak memory 206664 kb
Host smart-df2a1bfe-95bb-407c-b034-f61f5135cce5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996224868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3996224868
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2159373582
Short name T1066
Test name
Test status
Simulation time 103795639 ps
CPU time 2.3 seconds
Started Aug 07 05:36:27 PM PDT 24
Finished Aug 07 05:36:29 PM PDT 24
Peak memory 214960 kb
Host smart-1558efcd-3af9-4dbc-a029-6046ac7f0ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159373582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2159373582
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2042869143
Short name T1082
Test name
Test status
Simulation time 47673671 ps
CPU time 1.64 seconds
Started Aug 07 05:36:31 PM PDT 24
Finished Aug 07 05:36:33 PM PDT 24
Peak memory 206784 kb
Host smart-b8ca6f24-4d5f-4483-b107-a2b23f7ee19e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042869143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2042869143
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3309807173
Short name T1125
Test name
Test status
Simulation time 28637474 ps
CPU time 0.99 seconds
Started Aug 07 05:36:33 PM PDT 24
Finished Aug 07 05:36:34 PM PDT 24
Peak memory 206788 kb
Host smart-60736e26-c09d-4b02-8f9e-22335048b656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309807173 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3309807173
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.921136102
Short name T1124
Test name
Test status
Simulation time 42237877 ps
CPU time 0.88 seconds
Started Aug 07 05:36:32 PM PDT 24
Finished Aug 07 05:36:33 PM PDT 24
Peak memory 206636 kb
Host smart-a4baf589-0f1a-4c49-862f-b8cb0581dd5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921136102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.921136102
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3962292993
Short name T1004
Test name
Test status
Simulation time 63949033 ps
CPU time 0.8 seconds
Started Aug 07 05:36:38 PM PDT 24
Finished Aug 07 05:36:39 PM PDT 24
Peak memory 206392 kb
Host smart-29ddaea4-3f23-4f3c-be84-9838cc1deb22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962292993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3962292993
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.391626493
Short name T1085
Test name
Test status
Simulation time 23736974 ps
CPU time 1.1 seconds
Started Aug 07 05:36:35 PM PDT 24
Finished Aug 07 05:36:36 PM PDT 24
Peak memory 206712 kb
Host smart-fcfb0f60-30fb-4874-824f-817708cfb235
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391626493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.391626493
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.71879807
Short name T1076
Test name
Test status
Simulation time 23096137 ps
CPU time 1.58 seconds
Started Aug 07 05:36:38 PM PDT 24
Finished Aug 07 05:36:40 PM PDT 24
Peak memory 214928 kb
Host smart-667c30c9-707d-44b0-8ca6-7cb60085af17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71879807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.71879807
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1560770291
Short name T283
Test name
Test status
Simulation time 182271479 ps
CPU time 2.51 seconds
Started Aug 07 05:36:31 PM PDT 24
Finished Aug 07 05:36:34 PM PDT 24
Peak memory 214996 kb
Host smart-50b4be2e-7e67-452b-9477-b7be557c48f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560770291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1560770291
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.896280724
Short name T1010
Test name
Test status
Simulation time 143239974 ps
CPU time 1.21 seconds
Started Aug 07 05:36:40 PM PDT 24
Finished Aug 07 05:36:41 PM PDT 24
Peak memory 214856 kb
Host smart-38d40ddd-da12-42d0-b82e-4efa836e994e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896280724 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.896280724
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2712398271
Short name T1074
Test name
Test status
Simulation time 15198449 ps
CPU time 0.93 seconds
Started Aug 07 05:36:41 PM PDT 24
Finished Aug 07 05:36:42 PM PDT 24
Peak memory 206620 kb
Host smart-5832d859-3b5b-4bb9-bd7d-dfad1d7b35a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712398271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2712398271
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2376386715
Short name T1042
Test name
Test status
Simulation time 131686099 ps
CPU time 0.89 seconds
Started Aug 07 05:36:39 PM PDT 24
Finished Aug 07 05:36:40 PM PDT 24
Peak memory 206444 kb
Host smart-7dacafa1-3180-4e23-9609-170722cc6140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376386715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2376386715
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2711400982
Short name T265
Test name
Test status
Simulation time 39288359 ps
CPU time 1.13 seconds
Started Aug 07 05:36:39 PM PDT 24
Finished Aug 07 05:36:40 PM PDT 24
Peak memory 206704 kb
Host smart-d14a7973-107b-4161-98c0-731ec0f396bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711400982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2711400982
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.891637300
Short name T1009
Test name
Test status
Simulation time 173724660 ps
CPU time 4.6 seconds
Started Aug 07 05:36:40 PM PDT 24
Finished Aug 07 05:36:44 PM PDT 24
Peak memory 214864 kb
Host smart-b2651aa2-aca1-4779-8b96-e78aa304970d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891637300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.891637300
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1287909706
Short name T1055
Test name
Test status
Simulation time 152024586 ps
CPU time 1.6 seconds
Started Aug 07 05:36:38 PM PDT 24
Finished Aug 07 05:36:39 PM PDT 24
Peak memory 206764 kb
Host smart-d727938c-118f-45de-b1b8-e37c5de080f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287909706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1287909706
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2829807522
Short name T1098
Test name
Test status
Simulation time 38537291 ps
CPU time 1.4 seconds
Started Aug 07 05:36:37 PM PDT 24
Finished Aug 07 05:36:39 PM PDT 24
Peak memory 214952 kb
Host smart-ca237b19-827e-4b97-8447-782a655fbdcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829807522 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2829807522
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2432187301
Short name T1051
Test name
Test status
Simulation time 35254498 ps
CPU time 0.94 seconds
Started Aug 07 05:36:41 PM PDT 24
Finished Aug 07 05:36:42 PM PDT 24
Peak memory 206652 kb
Host smart-b5265589-006b-4644-9471-944295f769d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432187301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2432187301
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1842608383
Short name T1112
Test name
Test status
Simulation time 21006032 ps
CPU time 0.84 seconds
Started Aug 07 05:36:40 PM PDT 24
Finished Aug 07 05:36:41 PM PDT 24
Peak memory 206504 kb
Host smart-f744e5ec-0141-47cd-a9d2-eea69d4ab5c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842608383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1842608383
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3080975227
Short name T1103
Test name
Test status
Simulation time 24688049 ps
CPU time 1.13 seconds
Started Aug 07 05:36:40 PM PDT 24
Finished Aug 07 05:36:41 PM PDT 24
Peak memory 206720 kb
Host smart-1b61673e-620f-4f4d-9b3e-46f545249b5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080975227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3080975227
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.276978765
Short name T1053
Test name
Test status
Simulation time 262761863 ps
CPU time 3.18 seconds
Started Aug 07 05:36:39 PM PDT 24
Finished Aug 07 05:36:42 PM PDT 24
Peak memory 215004 kb
Host smart-d1185c4f-a40b-4a7f-83a0-3b4b8ac7862e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276978765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.276978765
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1533193668
Short name T1107
Test name
Test status
Simulation time 167047599 ps
CPU time 1.61 seconds
Started Aug 07 05:36:39 PM PDT 24
Finished Aug 07 05:36:40 PM PDT 24
Peak memory 206708 kb
Host smart-0fc03033-6e56-470d-8cef-7b0a2fb7334d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533193668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1533193668
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1086497018
Short name T1006
Test name
Test status
Simulation time 26501122 ps
CPU time 1.21 seconds
Started Aug 07 05:36:07 PM PDT 24
Finished Aug 07 05:36:08 PM PDT 24
Peak memory 206680 kb
Host smart-7c437166-300c-45db-999f-4c680fa284e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086497018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1086497018
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3567364045
Short name T1033
Test name
Test status
Simulation time 148630720 ps
CPU time 2.19 seconds
Started Aug 07 05:36:10 PM PDT 24
Finished Aug 07 05:36:12 PM PDT 24
Peak memory 206736 kb
Host smart-aaa474d9-ff84-4fa6-9ce2-883319ede16b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567364045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3567364045
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3138763262
Short name T262
Test name
Test status
Simulation time 183548726 ps
CPU time 0.82 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:09 PM PDT 24
Peak memory 206484 kb
Host smart-3fea7563-ed64-4ac9-9c29-f9b5cb6ae589
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138763262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3138763262
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3374204951
Short name T1113
Test name
Test status
Simulation time 27548118 ps
CPU time 0.99 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:09 PM PDT 24
Peak memory 206716 kb
Host smart-b29208ef-92c0-4a4d-9c10-2b1ccb588984
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374204951 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3374204951
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3660981331
Short name T1027
Test name
Test status
Simulation time 16466486 ps
CPU time 0.94 seconds
Started Aug 07 05:36:07 PM PDT 24
Finished Aug 07 05:36:08 PM PDT 24
Peak memory 206684 kb
Host smart-cb562346-1d11-4599-93f5-fdf3c20b9094
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660981331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3660981331
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.611204551
Short name T1031
Test name
Test status
Simulation time 22051342 ps
CPU time 0.82 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:09 PM PDT 24
Peak memory 206556 kb
Host smart-9b7c385c-a79c-451a-865e-0a71cccbbe99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611204551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.611204551
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3089313932
Short name T267
Test name
Test status
Simulation time 27837017 ps
CPU time 1.15 seconds
Started Aug 07 05:36:07 PM PDT 24
Finished Aug 07 05:36:08 PM PDT 24
Peak memory 206760 kb
Host smart-83a0fd86-9c08-4d12-8020-0b46a9116afd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089313932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3089313932
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1470954340
Short name T1073
Test name
Test status
Simulation time 70044915 ps
CPU time 2.53 seconds
Started Aug 07 05:36:07 PM PDT 24
Finished Aug 07 05:36:10 PM PDT 24
Peak memory 214964 kb
Host smart-02f31d3e-0640-4018-899c-b61621faf81e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470954340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1470954340
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.960100825
Short name T287
Test name
Test status
Simulation time 991611675 ps
CPU time 2.69 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:11 PM PDT 24
Peak memory 214868 kb
Host smart-7e88169f-70b1-40af-8d61-66fc08b5fbea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960100825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.960100825
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.800941509
Short name T1036
Test name
Test status
Simulation time 21166548 ps
CPU time 0.84 seconds
Started Aug 07 05:36:37 PM PDT 24
Finished Aug 07 05:36:38 PM PDT 24
Peak memory 206408 kb
Host smart-2549cd8f-6eae-407f-8c1f-fcdc1c305f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800941509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.800941509
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.45468770
Short name T1029
Test name
Test status
Simulation time 27900837 ps
CPU time 0.82 seconds
Started Aug 07 05:36:39 PM PDT 24
Finished Aug 07 05:36:40 PM PDT 24
Peak memory 206436 kb
Host smart-271ca213-c84c-4044-8780-d33b837815c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45468770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.45468770
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1256442842
Short name T1067
Test name
Test status
Simulation time 29134089 ps
CPU time 0.88 seconds
Started Aug 07 05:36:38 PM PDT 24
Finished Aug 07 05:36:39 PM PDT 24
Peak memory 206476 kb
Host smart-c1667a1d-7840-49b0-a7f2-d54c5056c189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256442842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1256442842
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.549277491
Short name T1078
Test name
Test status
Simulation time 17073366 ps
CPU time 0.92 seconds
Started Aug 07 05:36:41 PM PDT 24
Finished Aug 07 05:36:42 PM PDT 24
Peak memory 206448 kb
Host smart-d8fd1469-c91e-4fb0-b6d2-e4f42e38a28c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549277491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.549277491
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3516076098
Short name T1064
Test name
Test status
Simulation time 13449618 ps
CPU time 0.89 seconds
Started Aug 07 05:36:43 PM PDT 24
Finished Aug 07 05:36:44 PM PDT 24
Peak memory 206500 kb
Host smart-e87c67ce-6a3b-4ce3-a2bb-184ef60d0d7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516076098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3516076098
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1288981422
Short name T1099
Test name
Test status
Simulation time 16006894 ps
CPU time 0.79 seconds
Started Aug 07 05:36:36 PM PDT 24
Finished Aug 07 05:36:37 PM PDT 24
Peak memory 206448 kb
Host smart-d6f63482-1b03-4cd0-bd66-3660d19fb716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288981422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1288981422
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2277076987
Short name T1043
Test name
Test status
Simulation time 15132658 ps
CPU time 0.91 seconds
Started Aug 07 05:36:40 PM PDT 24
Finished Aug 07 05:36:41 PM PDT 24
Peak memory 206532 kb
Host smart-0dde28c6-c41c-4b91-a1ba-43300a1ddba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277076987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2277076987
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.4031222872
Short name T1116
Test name
Test status
Simulation time 16020489 ps
CPU time 0.9 seconds
Started Aug 07 05:36:36 PM PDT 24
Finished Aug 07 05:36:37 PM PDT 24
Peak memory 206492 kb
Host smart-71f4f533-50c9-48dd-976f-40f5e2d4a011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031222872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.4031222872
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2009715531
Short name T1005
Test name
Test status
Simulation time 22240042 ps
CPU time 0.83 seconds
Started Aug 07 05:36:37 PM PDT 24
Finished Aug 07 05:36:38 PM PDT 24
Peak memory 206428 kb
Host smart-8778cf1c-2e65-4200-b02e-0cb20b86925a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009715531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2009715531
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.561901092
Short name T1034
Test name
Test status
Simulation time 89283466 ps
CPU time 0.81 seconds
Started Aug 07 05:36:38 PM PDT 24
Finished Aug 07 05:36:39 PM PDT 24
Peak memory 206444 kb
Host smart-3c605004-f260-434e-8231-1bb31d5bcc0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561901092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.561901092
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.615082136
Short name T259
Test name
Test status
Simulation time 135349517 ps
CPU time 1.01 seconds
Started Aug 07 05:36:15 PM PDT 24
Finished Aug 07 05:36:16 PM PDT 24
Peak memory 206648 kb
Host smart-9bed1dfc-0b86-4645-82eb-8a53da81760c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615082136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.615082136
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.205301315
Short name T1062
Test name
Test status
Simulation time 69078737 ps
CPU time 2.06 seconds
Started Aug 07 05:36:17 PM PDT 24
Finished Aug 07 05:36:19 PM PDT 24
Peak memory 206672 kb
Host smart-8f3a4c37-b60a-40bb-b91c-c954c1a95b38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205301315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.205301315
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.4205362395
Short name T1012
Test name
Test status
Simulation time 30643091 ps
CPU time 0.92 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:09 PM PDT 24
Peak memory 206580 kb
Host smart-57d256e8-ddb8-4db4-9963-f101bbbf6eb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205362395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.4205362395
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3781548412
Short name T997
Test name
Test status
Simulation time 62772249 ps
CPU time 1.41 seconds
Started Aug 07 05:36:19 PM PDT 24
Finished Aug 07 05:36:20 PM PDT 24
Peak memory 215000 kb
Host smart-271f32eb-b455-468c-9c77-67e713af043a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781548412 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3781548412
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2742115114
Short name T255
Test name
Test status
Simulation time 13365825 ps
CPU time 0.87 seconds
Started Aug 07 05:36:16 PM PDT 24
Finished Aug 07 05:36:17 PM PDT 24
Peak memory 206532 kb
Host smart-1474d89a-7176-4888-8661-30e44c68573e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742115114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2742115114
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1813176043
Short name T1106
Test name
Test status
Simulation time 45710765 ps
CPU time 0.86 seconds
Started Aug 07 05:36:07 PM PDT 24
Finished Aug 07 05:36:08 PM PDT 24
Peak memory 206528 kb
Host smart-3850bef1-26ce-4633-befe-155718013aad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813176043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1813176043
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4153408450
Short name T1058
Test name
Test status
Simulation time 45149937 ps
CPU time 1.14 seconds
Started Aug 07 05:36:12 PM PDT 24
Finished Aug 07 05:36:13 PM PDT 24
Peak memory 206764 kb
Host smart-fa6dcbd7-d4db-4263-9e73-0839963cb9a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153408450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.4153408450
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3853683426
Short name T1017
Test name
Test status
Simulation time 68095208 ps
CPU time 2.53 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:11 PM PDT 24
Peak memory 214888 kb
Host smart-ff8b93f5-6b68-4063-9e75-eaf203c73e64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853683426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3853683426
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.645342362
Short name T1089
Test name
Test status
Simulation time 100956641 ps
CPU time 1.48 seconds
Started Aug 07 05:36:08 PM PDT 24
Finished Aug 07 05:36:10 PM PDT 24
Peak memory 206776 kb
Host smart-22ef8641-57e6-4228-a1cc-2f16f556a493
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645342362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.645342362
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3461565400
Short name T1044
Test name
Test status
Simulation time 27628842 ps
CPU time 0.79 seconds
Started Aug 07 05:36:40 PM PDT 24
Finished Aug 07 05:36:41 PM PDT 24
Peak memory 206324 kb
Host smart-3d5e4354-0842-4f09-9e24-d3ccc94989e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461565400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3461565400
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2697480906
Short name T991
Test name
Test status
Simulation time 18782039 ps
CPU time 0.97 seconds
Started Aug 07 05:36:41 PM PDT 24
Finished Aug 07 05:36:42 PM PDT 24
Peak memory 206524 kb
Host smart-e6dffe41-6101-4344-973a-33579ac05ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697480906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2697480906
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3783048311
Short name T1093
Test name
Test status
Simulation time 22392791 ps
CPU time 0.84 seconds
Started Aug 07 05:36:41 PM PDT 24
Finished Aug 07 05:36:42 PM PDT 24
Peak memory 206440 kb
Host smart-4311a61a-e092-4a03-ac75-021191c94c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783048311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3783048311
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3401940630
Short name T1111
Test name
Test status
Simulation time 34751637 ps
CPU time 0.87 seconds
Started Aug 07 05:36:41 PM PDT 24
Finished Aug 07 05:36:42 PM PDT 24
Peak memory 206532 kb
Host smart-f8ef4f83-d1fa-4a35-9478-bd81c1e6a866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401940630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3401940630
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2598070816
Short name T1013
Test name
Test status
Simulation time 19513571 ps
CPU time 0.83 seconds
Started Aug 07 05:36:38 PM PDT 24
Finished Aug 07 05:36:39 PM PDT 24
Peak memory 206500 kb
Host smart-56b639f6-f49d-4b3a-87c1-e6230005305f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598070816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2598070816
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2197624105
Short name T1087
Test name
Test status
Simulation time 20173754 ps
CPU time 0.81 seconds
Started Aug 07 05:36:40 PM PDT 24
Finished Aug 07 05:36:41 PM PDT 24
Peak memory 206408 kb
Host smart-92c9ca8a-1133-43ad-b0ad-59b60ed0c607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197624105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2197624105
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.138405794
Short name T995
Test name
Test status
Simulation time 17990878 ps
CPU time 0.87 seconds
Started Aug 07 05:36:43 PM PDT 24
Finished Aug 07 05:36:44 PM PDT 24
Peak memory 206448 kb
Host smart-1702a16e-7c02-4d2b-8e62-5f069cd42dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138405794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.138405794
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.968744189
Short name T1002
Test name
Test status
Simulation time 16073583 ps
CPU time 0.92 seconds
Started Aug 07 05:36:49 PM PDT 24
Finished Aug 07 05:36:50 PM PDT 24
Peak memory 206516 kb
Host smart-d3f8c589-4480-442d-9be1-09ac4a093665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968744189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.968744189
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1622189224
Short name T1071
Test name
Test status
Simulation time 38319156 ps
CPU time 0.81 seconds
Started Aug 07 05:36:48 PM PDT 24
Finished Aug 07 05:36:49 PM PDT 24
Peak memory 206532 kb
Host smart-c4278e09-8d54-4e80-beda-6a4ce55460b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622189224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1622189224
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3365630990
Short name T1039
Test name
Test status
Simulation time 13205852 ps
CPU time 0.93 seconds
Started Aug 07 05:36:45 PM PDT 24
Finished Aug 07 05:36:46 PM PDT 24
Peak memory 206528 kb
Host smart-3bfffc42-aa96-45c1-b0ea-fa30e06f6cd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365630990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3365630990
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3311337048
Short name T263
Test name
Test status
Simulation time 134753496 ps
CPU time 1.66 seconds
Started Aug 07 05:36:14 PM PDT 24
Finished Aug 07 05:36:15 PM PDT 24
Peak memory 206632 kb
Host smart-ee95abcc-e65c-4963-8a11-e7d7a7d4eadb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311337048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3311337048
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.301820980
Short name T1052
Test name
Test status
Simulation time 673322185 ps
CPU time 5.34 seconds
Started Aug 07 05:36:15 PM PDT 24
Finished Aug 07 05:36:21 PM PDT 24
Peak memory 206640 kb
Host smart-4fe03477-d474-4f42-bb55-8c385f401215
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301820980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.301820980
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3500638249
Short name T261
Test name
Test status
Simulation time 36705805 ps
CPU time 0.93 seconds
Started Aug 07 05:36:13 PM PDT 24
Finished Aug 07 05:36:14 PM PDT 24
Peak memory 206656 kb
Host smart-49f3efe2-f467-42aa-a8a3-432129f88c5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500638249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3500638249
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2229875493
Short name T1056
Test name
Test status
Simulation time 93823542 ps
CPU time 0.96 seconds
Started Aug 07 05:36:15 PM PDT 24
Finished Aug 07 05:36:16 PM PDT 24
Peak memory 216212 kb
Host smart-0c7c6ebe-a9b6-47b2-9d3c-4f454fbd0671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229875493 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2229875493
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2681617195
Short name T253
Test name
Test status
Simulation time 26940537 ps
CPU time 0.91 seconds
Started Aug 07 05:36:14 PM PDT 24
Finished Aug 07 05:36:15 PM PDT 24
Peak memory 206680 kb
Host smart-36cdba05-d541-4da0-9233-28de4b4eee8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681617195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2681617195
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.4056867794
Short name T1095
Test name
Test status
Simulation time 84220105 ps
CPU time 0.85 seconds
Started Aug 07 05:36:14 PM PDT 24
Finished Aug 07 05:36:15 PM PDT 24
Peak memory 206428 kb
Host smart-4a6b08e7-b816-4b29-a1a2-3b2a73831b75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056867794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.4056867794
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3362842990
Short name T1123
Test name
Test status
Simulation time 29057052 ps
CPU time 1.03 seconds
Started Aug 07 05:36:19 PM PDT 24
Finished Aug 07 05:36:20 PM PDT 24
Peak memory 206688 kb
Host smart-01bd2ccd-51d4-4dc7-986b-3341c4714846
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362842990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3362842990
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1920514804
Short name T1025
Test name
Test status
Simulation time 46525485 ps
CPU time 1.62 seconds
Started Aug 07 05:36:15 PM PDT 24
Finished Aug 07 05:36:17 PM PDT 24
Peak memory 214996 kb
Host smart-a9c46288-424d-4a1d-961d-834f783cde74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920514804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1920514804
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3317797649
Short name T1122
Test name
Test status
Simulation time 131863138 ps
CPU time 1.49 seconds
Started Aug 07 05:36:14 PM PDT 24
Finished Aug 07 05:36:16 PM PDT 24
Peak memory 206896 kb
Host smart-e11a8b24-cbec-4fca-8305-1ecfa8d43807
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317797649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3317797649
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1731859366
Short name T1003
Test name
Test status
Simulation time 16894206 ps
CPU time 0.93 seconds
Started Aug 07 05:36:46 PM PDT 24
Finished Aug 07 05:36:47 PM PDT 24
Peak memory 206572 kb
Host smart-e78f42d3-0d29-4087-8417-b70eb0b35232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731859366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1731859366
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1974385684
Short name T1016
Test name
Test status
Simulation time 189237072 ps
CPU time 0.84 seconds
Started Aug 07 05:36:48 PM PDT 24
Finished Aug 07 05:36:49 PM PDT 24
Peak memory 206428 kb
Host smart-64a5a194-2da4-467e-aece-b4bc338946aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974385684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1974385684
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.274634382
Short name T1080
Test name
Test status
Simulation time 18309061 ps
CPU time 0.94 seconds
Started Aug 07 05:36:44 PM PDT 24
Finished Aug 07 05:36:45 PM PDT 24
Peak memory 206524 kb
Host smart-b51c7d69-2697-4fd3-a35c-ed7df72e34ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274634382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.274634382
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.37882665
Short name T1014
Test name
Test status
Simulation time 40506789 ps
CPU time 0.84 seconds
Started Aug 07 05:36:45 PM PDT 24
Finished Aug 07 05:36:46 PM PDT 24
Peak memory 206496 kb
Host smart-a999ea02-f354-4230-81f9-48c2b6e0917a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37882665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.37882665
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1492011977
Short name T1040
Test name
Test status
Simulation time 21548891 ps
CPU time 0.82 seconds
Started Aug 07 05:36:44 PM PDT 24
Finished Aug 07 05:36:44 PM PDT 24
Peak memory 206420 kb
Host smart-97529d53-a957-4215-920a-e782cccb280d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492011977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1492011977
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3910866061
Short name T998
Test name
Test status
Simulation time 14805575 ps
CPU time 0.89 seconds
Started Aug 07 05:36:47 PM PDT 24
Finished Aug 07 05:36:48 PM PDT 24
Peak memory 206528 kb
Host smart-03e01558-d89c-4e55-b476-bea42aac768b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910866061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3910866061
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1279219423
Short name T1022
Test name
Test status
Simulation time 59196036 ps
CPU time 0.84 seconds
Started Aug 07 05:36:45 PM PDT 24
Finished Aug 07 05:36:46 PM PDT 24
Peak memory 206476 kb
Host smart-67037742-bb31-4e39-9d3f-fd139e421560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279219423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1279219423
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1434488821
Short name T992
Test name
Test status
Simulation time 36836054 ps
CPU time 0.8 seconds
Started Aug 07 05:36:43 PM PDT 24
Finished Aug 07 05:36:46 PM PDT 24
Peak memory 206488 kb
Host smart-76e3d1c4-3b32-4299-8818-971e80766052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434488821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1434488821
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2078612260
Short name T1105
Test name
Test status
Simulation time 25961932 ps
CPU time 1.04 seconds
Started Aug 07 05:36:46 PM PDT 24
Finished Aug 07 05:36:47 PM PDT 24
Peak memory 206516 kb
Host smart-a1a40245-2590-4d70-9a89-1017f27b9a59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078612260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2078612260
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3000676857
Short name T1102
Test name
Test status
Simulation time 12882781 ps
CPU time 0.93 seconds
Started Aug 07 05:36:47 PM PDT 24
Finished Aug 07 05:36:48 PM PDT 24
Peak memory 206448 kb
Host smart-c05b85a4-e758-432e-8ff1-dcbc27cbd44f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000676857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3000676857
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2115370722
Short name T1047
Test name
Test status
Simulation time 26413453 ps
CPU time 1.25 seconds
Started Aug 07 05:36:19 PM PDT 24
Finished Aug 07 05:36:20 PM PDT 24
Peak memory 215008 kb
Host smart-437a366a-706f-4bc2-8ef4-fca264151468
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115370722 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2115370722
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3747896973
Short name T1083
Test name
Test status
Simulation time 14388968 ps
CPU time 0.9 seconds
Started Aug 07 05:36:13 PM PDT 24
Finished Aug 07 05:36:14 PM PDT 24
Peak memory 206656 kb
Host smart-34eae9eb-a708-4389-8f31-f12be45c669a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747896973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3747896973
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2566818941
Short name T1063
Test name
Test status
Simulation time 18047200 ps
CPU time 0.8 seconds
Started Aug 07 05:36:14 PM PDT 24
Finished Aug 07 05:36:15 PM PDT 24
Peak memory 206500 kb
Host smart-c7c3e10a-f6e3-44f2-a5ba-7a2a8e78f063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566818941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2566818941
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4052410412
Short name T1114
Test name
Test status
Simulation time 42016373 ps
CPU time 1.31 seconds
Started Aug 07 05:36:14 PM PDT 24
Finished Aug 07 05:36:16 PM PDT 24
Peak memory 206788 kb
Host smart-1659edcf-4e75-4256-86a4-0beaee22770b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052410412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.4052410412
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1035668912
Short name T1109
Test name
Test status
Simulation time 84575232 ps
CPU time 3.29 seconds
Started Aug 07 05:36:13 PM PDT 24
Finished Aug 07 05:36:16 PM PDT 24
Peak memory 214788 kb
Host smart-1a83faaa-d041-4522-9e9a-cd8a623fa551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035668912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1035668912
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1230899108
Short name T1079
Test name
Test status
Simulation time 162397240 ps
CPU time 2.28 seconds
Started Aug 07 05:36:18 PM PDT 24
Finished Aug 07 05:36:21 PM PDT 24
Peak memory 206704 kb
Host smart-2e641763-0fe4-414b-9c86-eff732b1b185
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230899108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1230899108
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3306011086
Short name T1024
Test name
Test status
Simulation time 110957980 ps
CPU time 1.97 seconds
Started Aug 07 05:36:16 PM PDT 24
Finished Aug 07 05:36:18 PM PDT 24
Peak memory 219820 kb
Host smart-d849c3b7-f989-42e8-8aeb-35acea17a747
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306011086 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3306011086
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.840758139
Short name T1020
Test name
Test status
Simulation time 21366797 ps
CPU time 0.91 seconds
Started Aug 07 05:36:13 PM PDT 24
Finished Aug 07 05:36:14 PM PDT 24
Peak memory 206520 kb
Host smart-ea666def-e8a9-41d3-b751-b5ec6008bfa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840758139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.840758139
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1392192131
Short name T989
Test name
Test status
Simulation time 20040693 ps
CPU time 0.86 seconds
Started Aug 07 05:36:13 PM PDT 24
Finished Aug 07 05:36:14 PM PDT 24
Peak memory 206512 kb
Host smart-1b9de4f5-8073-483b-b757-8bd245ede0c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392192131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1392192131
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3993139884
Short name T1121
Test name
Test status
Simulation time 48988373 ps
CPU time 1.09 seconds
Started Aug 07 05:36:14 PM PDT 24
Finished Aug 07 05:36:15 PM PDT 24
Peak memory 206760 kb
Host smart-62e64310-5be0-4f7a-9767-ec4c4427ea2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993139884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3993139884
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2347437055
Short name T1021
Test name
Test status
Simulation time 45827413 ps
CPU time 1.71 seconds
Started Aug 07 05:36:18 PM PDT 24
Finished Aug 07 05:36:20 PM PDT 24
Peak memory 214888 kb
Host smart-01b8ef9b-104f-4fab-bd31-af8ab4195aa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347437055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2347437055
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2552938461
Short name T221
Test name
Test status
Simulation time 72101753 ps
CPU time 1.96 seconds
Started Aug 07 05:36:14 PM PDT 24
Finished Aug 07 05:36:16 PM PDT 24
Peak memory 206708 kb
Host smart-3d38f7f0-f27e-4480-9058-f7fdc270feb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552938461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2552938461
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1675085149
Short name T1060
Test name
Test status
Simulation time 70470959 ps
CPU time 1.88 seconds
Started Aug 07 05:36:19 PM PDT 24
Finished Aug 07 05:36:21 PM PDT 24
Peak memory 214908 kb
Host smart-815836eb-7c04-46a3-b4a0-b30bf258ffd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675085149 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1675085149
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2953017944
Short name T1091
Test name
Test status
Simulation time 43110863 ps
CPU time 0.86 seconds
Started Aug 07 05:36:18 PM PDT 24
Finished Aug 07 05:36:19 PM PDT 24
Peak memory 206596 kb
Host smart-0addb88d-367c-4f33-8fcb-29445eb7606a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953017944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2953017944
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2286233136
Short name T1026
Test name
Test status
Simulation time 94796242 ps
CPU time 0.84 seconds
Started Aug 07 05:36:16 PM PDT 24
Finished Aug 07 05:36:17 PM PDT 24
Peak memory 206460 kb
Host smart-3746229a-111a-41d9-ac31-3518f35f0772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286233136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2286233136
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.4286766064
Short name T1075
Test name
Test status
Simulation time 15183484 ps
CPU time 0.99 seconds
Started Aug 07 05:36:26 PM PDT 24
Finished Aug 07 05:36:28 PM PDT 24
Peak memory 206624 kb
Host smart-33cecfb9-405f-4390-95e6-05f91cba1ab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286766064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.4286766064
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.303586049
Short name T1035
Test name
Test status
Simulation time 174984062 ps
CPU time 2.92 seconds
Started Aug 07 05:36:16 PM PDT 24
Finished Aug 07 05:36:19 PM PDT 24
Peak memory 214952 kb
Host smart-e0d73344-522e-4fce-acf7-aea6ceedb1a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303586049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.303586049
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3468020732
Short name T1084
Test name
Test status
Simulation time 111727042 ps
CPU time 2.74 seconds
Started Aug 07 05:36:14 PM PDT 24
Finished Aug 07 05:36:17 PM PDT 24
Peak memory 206636 kb
Host smart-997d4472-f629-4cda-824e-68fd4da0125c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468020732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3468020732
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1561899244
Short name T1090
Test name
Test status
Simulation time 20856809 ps
CPU time 1.24 seconds
Started Aug 07 05:36:20 PM PDT 24
Finished Aug 07 05:36:21 PM PDT 24
Peak memory 218160 kb
Host smart-9a88c994-d374-4fc1-b9a8-45af807175d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561899244 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1561899244
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1600826796
Short name T260
Test name
Test status
Simulation time 39812180 ps
CPU time 0.83 seconds
Started Aug 07 05:36:20 PM PDT 24
Finished Aug 07 05:36:21 PM PDT 24
Peak memory 206568 kb
Host smart-ac24f9e0-e2ce-4f9c-82e1-5d516b1264e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600826796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1600826796
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1705578672
Short name T1007
Test name
Test status
Simulation time 23554317 ps
CPU time 0.88 seconds
Started Aug 07 05:36:20 PM PDT 24
Finished Aug 07 05:36:21 PM PDT 24
Peak memory 206432 kb
Host smart-646bdd3d-a1f1-447d-a6f2-2fbc36841658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705578672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1705578672
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1512436049
Short name T271
Test name
Test status
Simulation time 70227323 ps
CPU time 1.34 seconds
Started Aug 07 05:36:21 PM PDT 24
Finished Aug 07 05:36:23 PM PDT 24
Peak memory 206712 kb
Host smart-822144b9-a61c-45f4-acbe-f952cf0e6ec1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512436049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1512436049
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.936703514
Short name T1018
Test name
Test status
Simulation time 22183013 ps
CPU time 1.51 seconds
Started Aug 07 05:36:20 PM PDT 24
Finished Aug 07 05:36:22 PM PDT 24
Peak memory 214924 kb
Host smart-46b8073e-69a6-445e-b496-87252edfe4cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936703514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.936703514
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2799387233
Short name T1059
Test name
Test status
Simulation time 122310284 ps
CPU time 2.18 seconds
Started Aug 07 05:36:20 PM PDT 24
Finished Aug 07 05:36:22 PM PDT 24
Peak memory 206748 kb
Host smart-ec4212df-bef3-4282-9c4e-48d14f724242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799387233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2799387233
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2483735139
Short name T1088
Test name
Test status
Simulation time 57568987 ps
CPU time 1.2 seconds
Started Aug 07 05:36:20 PM PDT 24
Finished Aug 07 05:36:22 PM PDT 24
Peak memory 217980 kb
Host smart-d8cd7b01-d67a-4787-9d41-526719280e5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483735139 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2483735139
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.292171339
Short name T254
Test name
Test status
Simulation time 47225249 ps
CPU time 0.93 seconds
Started Aug 07 05:36:21 PM PDT 24
Finished Aug 07 05:36:22 PM PDT 24
Peak memory 206664 kb
Host smart-3ee0b094-f008-4c44-9ddc-c1cd5da1444f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292171339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.292171339
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1318687456
Short name T1054
Test name
Test status
Simulation time 15991620 ps
CPU time 0.97 seconds
Started Aug 07 05:36:20 PM PDT 24
Finished Aug 07 05:36:21 PM PDT 24
Peak memory 206496 kb
Host smart-722ffaa7-43e6-4ee0-9dc7-2867a63b9343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318687456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1318687456
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2663373248
Short name T1070
Test name
Test status
Simulation time 36539078 ps
CPU time 1.07 seconds
Started Aug 07 05:36:19 PM PDT 24
Finished Aug 07 05:36:20 PM PDT 24
Peak memory 206760 kb
Host smart-d2cbdf48-2c47-4b02-82a6-2a37f97f2d4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663373248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2663373248
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.625975990
Short name T1100
Test name
Test status
Simulation time 114137319 ps
CPU time 3.63 seconds
Started Aug 07 05:36:19 PM PDT 24
Finished Aug 07 05:36:23 PM PDT 24
Peak memory 214976 kb
Host smart-4dfd6d1d-e8e0-41d3-bad7-cc79fc0901a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625975990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.625975990
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.558766412
Short name T1094
Test name
Test status
Simulation time 241971449 ps
CPU time 2.23 seconds
Started Aug 07 05:36:23 PM PDT 24
Finished Aug 07 05:36:25 PM PDT 24
Peak memory 206720 kb
Host smart-441fe7c9-01a0-4b43-bcce-7fc7c7a41598
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558766412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.558766412
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1597731216
Short name T790
Test name
Test status
Simulation time 28461716 ps
CPU time 1.36 seconds
Started Aug 07 06:55:19 PM PDT 24
Finished Aug 07 06:55:20 PM PDT 24
Peak memory 218304 kb
Host smart-55d14b18-39bf-4573-9502-0a052aab1bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597731216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1597731216
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.3719913087
Short name T689
Test name
Test status
Simulation time 15533118 ps
CPU time 0.95 seconds
Started Aug 07 06:55:18 PM PDT 24
Finished Aug 07 06:55:19 PM PDT 24
Peak memory 206384 kb
Host smart-d9aba5f7-13ac-4874-a148-f7f4dc0de11c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719913087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3719913087
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.2139619405
Short name T863
Test name
Test status
Simulation time 20735140 ps
CPU time 1.11 seconds
Started Aug 07 06:55:17 PM PDT 24
Finished Aug 07 06:55:18 PM PDT 24
Peak memory 219580 kb
Host smart-6f03640d-e572-4d66-adac-75843bd43dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139619405 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2139619405
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3776326085
Short name T346
Test name
Test status
Simulation time 66652822 ps
CPU time 1.22 seconds
Started Aug 07 06:55:17 PM PDT 24
Finished Aug 07 06:55:18 PM PDT 24
Peak memory 218428 kb
Host smart-f527047e-9515-4b29-85fe-635f176f2468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776326085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3776326085
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.3600520791
Short name T560
Test name
Test status
Simulation time 48293391 ps
CPU time 0.9 seconds
Started Aug 07 06:55:17 PM PDT 24
Finished Aug 07 06:55:18 PM PDT 24
Peak memory 206732 kb
Host smart-598ce256-ced1-43e7-ae39-ccda445b3eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600520791 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3600520791
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.3553162150
Short name T480
Test name
Test status
Simulation time 99873901 ps
CPU time 0.9 seconds
Started Aug 07 06:55:20 PM PDT 24
Finished Aug 07 06:55:21 PM PDT 24
Peak memory 215048 kb
Host smart-9f1a514b-ab44-4ea1-aabb-594fff17a013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553162150 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3553162150
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.751377189
Short name T243
Test name
Test status
Simulation time 96377988 ps
CPU time 2.36 seconds
Started Aug 07 06:55:20 PM PDT 24
Finished Aug 07 06:55:22 PM PDT 24
Peak memory 214896 kb
Host smart-cdf99783-6767-4490-b957-581de360ef1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751377189 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.751377189
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.557705045
Short name T591
Test name
Test status
Simulation time 254138410078 ps
CPU time 2200.54 seconds
Started Aug 07 06:55:17 PM PDT 24
Finished Aug 07 07:31:57 PM PDT 24
Peak memory 230340 kb
Host smart-a8aa34a6-d832-4a15-8bfa-e2006ebcd281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557705045 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.557705045
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.465205877
Short name T300
Test name
Test status
Simulation time 79705915 ps
CPU time 1.19 seconds
Started Aug 07 06:55:18 PM PDT 24
Finished Aug 07 06:55:19 PM PDT 24
Peak memory 219864 kb
Host smart-56d8693d-7886-483f-9efa-a1e7fd627824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465205877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.465205877
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.4001267942
Short name T743
Test name
Test status
Simulation time 23994571 ps
CPU time 0.89 seconds
Started Aug 07 06:55:17 PM PDT 24
Finished Aug 07 06:55:18 PM PDT 24
Peak memory 206384 kb
Host smart-3a1cb582-41fb-4762-b042-bc510d250c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001267942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.4001267942
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.648890771
Short name T970
Test name
Test status
Simulation time 37742795 ps
CPU time 0.91 seconds
Started Aug 07 06:55:18 PM PDT 24
Finished Aug 07 06:55:19 PM PDT 24
Peak memory 216200 kb
Host smart-5fc80b7c-041f-4594-b8fc-021e41cdd007
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648890771 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.648890771
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2981073654
Short name T64
Test name
Test status
Simulation time 80236901 ps
CPU time 1.07 seconds
Started Aug 07 06:55:18 PM PDT 24
Finished Aug 07 06:55:19 PM PDT 24
Peak memory 219100 kb
Host smart-b0ff3c7a-e9b9-460c-8a4c-18d4a57b015d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981073654 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2981073654
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.817610405
Short name T129
Test name
Test status
Simulation time 52750422 ps
CPU time 1.01 seconds
Started Aug 07 06:55:20 PM PDT 24
Finished Aug 07 06:55:22 PM PDT 24
Peak memory 220544 kb
Host smart-b7df20cb-1704-4325-a925-cb20c8b9b2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817610405 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.817610405
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2934195636
Short name T39
Test name
Test status
Simulation time 42281660 ps
CPU time 1.51 seconds
Started Aug 07 06:55:17 PM PDT 24
Finished Aug 07 06:55:19 PM PDT 24
Peak memory 216956 kb
Host smart-f9897047-b85f-48e9-9cc9-88073ebcd9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934195636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2934195636
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.3325479209
Short name T293
Test name
Test status
Simulation time 63791252 ps
CPU time 0.93 seconds
Started Aug 07 06:55:18 PM PDT 24
Finished Aug 07 06:55:19 PM PDT 24
Peak memory 206732 kb
Host smart-29763745-810a-4c58-8ca0-1749fa65041a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325479209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3325479209
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.3266922370
Short name T830
Test name
Test status
Simulation time 30607475 ps
CPU time 1 seconds
Started Aug 07 06:55:18 PM PDT 24
Finished Aug 07 06:55:19 PM PDT 24
Peak memory 214920 kb
Host smart-2343d82d-9e30-4bb2-90ae-ee85081a4529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266922370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3266922370
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2960063597
Short name T520
Test name
Test status
Simulation time 94835100 ps
CPU time 1.12 seconds
Started Aug 07 06:55:18 PM PDT 24
Finished Aug 07 06:55:19 PM PDT 24
Peak memory 214912 kb
Host smart-7f028453-8597-427e-b3a4-50eaf17f7b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960063597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2960063597
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3300548550
Short name T226
Test name
Test status
Simulation time 55636294267 ps
CPU time 334.89 seconds
Started Aug 07 06:55:20 PM PDT 24
Finished Aug 07 07:00:55 PM PDT 24
Peak memory 223308 kb
Host smart-4c22627e-856d-4504-b5e6-10c765511ed0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300548550 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3300548550
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.3370033285
Short name T765
Test name
Test status
Simulation time 55836731 ps
CPU time 0.9 seconds
Started Aug 07 06:55:42 PM PDT 24
Finished Aug 07 06:55:43 PM PDT 24
Peak memory 206324 kb
Host smart-ae8915f8-960c-4bff-8943-3003437a1d22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370033285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3370033285
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.116220135
Short name T188
Test name
Test status
Simulation time 23314707 ps
CPU time 0.87 seconds
Started Aug 07 06:55:41 PM PDT 24
Finished Aug 07 06:55:42 PM PDT 24
Peak memory 216244 kb
Host smart-7ffaf1e3-cb24-4402-b861-0274faf7d846
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116220135 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.116220135
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1976856791
Short name T617
Test name
Test status
Simulation time 46375378 ps
CPU time 1.11 seconds
Started Aug 07 06:55:40 PM PDT 24
Finished Aug 07 06:55:42 PM PDT 24
Peak memory 219560 kb
Host smart-ed977f19-ef29-49c7-ba3a-70ba48e2c454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976856791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1976856791
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.744225117
Short name T812
Test name
Test status
Simulation time 57510320 ps
CPU time 1.61 seconds
Started Aug 07 06:55:43 PM PDT 24
Finished Aug 07 06:55:45 PM PDT 24
Peak memory 218148 kb
Host smart-6d635f5d-6238-44a6-9096-dc52183f974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744225117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.744225117
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2374724406
Short name T46
Test name
Test status
Simulation time 58101570 ps
CPU time 0.99 seconds
Started Aug 07 06:55:42 PM PDT 24
Finished Aug 07 06:55:43 PM PDT 24
Peak memory 223632 kb
Host smart-fbf859f3-919d-4f05-aceb-db44ee3d07b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374724406 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2374724406
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1137239113
Short name T360
Test name
Test status
Simulation time 29882371 ps
CPU time 0.97 seconds
Started Aug 07 06:55:38 PM PDT 24
Finished Aug 07 06:55:39 PM PDT 24
Peak memory 214900 kb
Host smart-5d361895-5d8a-4aa9-9fb8-c7776ddf9fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137239113 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1137239113
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1186305749
Short name T621
Test name
Test status
Simulation time 743476921 ps
CPU time 4.33 seconds
Started Aug 07 06:55:43 PM PDT 24
Finished Aug 07 06:55:47 PM PDT 24
Peak memory 216820 kb
Host smart-50c7e72e-a299-49a4-ba84-424c5bd4b2da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186305749 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1186305749
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_alert.104249483
Short name T600
Test name
Test status
Simulation time 47950227 ps
CPU time 1.07 seconds
Started Aug 07 06:57:45 PM PDT 24
Finished Aug 07 06:57:46 PM PDT 24
Peak memory 219472 kb
Host smart-21a23cff-3fe3-411d-8b49-d48c4135fb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104249483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.104249483
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.365148780
Short name T868
Test name
Test status
Simulation time 68201057 ps
CPU time 1.4 seconds
Started Aug 07 06:57:45 PM PDT 24
Finished Aug 07 06:57:47 PM PDT 24
Peak memory 218312 kb
Host smart-45791d3b-da87-4ce7-a505-44b6eeabefdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365148780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.365148780
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.2680033760
Short name T136
Test name
Test status
Simulation time 25179607 ps
CPU time 1.23 seconds
Started Aug 07 06:57:47 PM PDT 24
Finished Aug 07 06:57:48 PM PDT 24
Peak memory 218376 kb
Host smart-da52a4fc-06d2-44e0-9c46-e9371eb451ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680033760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2680033760
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.2847365480
Short name T904
Test name
Test status
Simulation time 72899172 ps
CPU time 1.01 seconds
Started Aug 07 06:57:48 PM PDT 24
Finished Aug 07 06:57:49 PM PDT 24
Peak memory 216796 kb
Host smart-63c5a55c-ce47-4f6c-8dfb-abd6ba7550bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847365480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2847365480
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.3856846986
Short name T89
Test name
Test status
Simulation time 21233141 ps
CPU time 1.17 seconds
Started Aug 07 06:57:49 PM PDT 24
Finished Aug 07 06:57:51 PM PDT 24
Peak memory 219208 kb
Host smart-4fdf9df8-80ff-4f47-a8a7-057f982e6ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856846986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3856846986
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/103.edn_alert.1694239278
Short name T606
Test name
Test status
Simulation time 88868131 ps
CPU time 1.2 seconds
Started Aug 07 06:57:54 PM PDT 24
Finished Aug 07 06:57:55 PM PDT 24
Peak memory 215272 kb
Host smart-1218ed38-2c1e-4bc1-93ef-91c70bc2705a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694239278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1694239278
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.2653526080
Short name T670
Test name
Test status
Simulation time 70707919 ps
CPU time 1.37 seconds
Started Aug 07 06:57:45 PM PDT 24
Finished Aug 07 06:57:46 PM PDT 24
Peak memory 218296 kb
Host smart-4364e348-f973-4074-8c18-c2d56de67be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653526080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2653526080
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.1919693112
Short name T568
Test name
Test status
Simulation time 29050421 ps
CPU time 1.28 seconds
Started Aug 07 06:57:48 PM PDT 24
Finished Aug 07 06:57:49 PM PDT 24
Peak memory 218320 kb
Host smart-e4ae0d2f-84df-4206-99f7-b589521a650c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919693112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1919693112
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.3146106611
Short name T845
Test name
Test status
Simulation time 69289406 ps
CPU time 2.68 seconds
Started Aug 07 06:57:54 PM PDT 24
Finished Aug 07 06:57:56 PM PDT 24
Peak memory 217052 kb
Host smart-005b7214-d97e-4022-89bc-9d47612d607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146106611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3146106611
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.3586887782
Short name T298
Test name
Test status
Simulation time 36890480 ps
CPU time 1.34 seconds
Started Aug 07 06:57:48 PM PDT 24
Finished Aug 07 06:57:49 PM PDT 24
Peak memory 219620 kb
Host smart-5cc6a44c-666f-415e-a361-eda2800a2de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586887782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.3586887782
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.3469039214
Short name T745
Test name
Test status
Simulation time 84400371 ps
CPU time 1.12 seconds
Started Aug 07 06:57:46 PM PDT 24
Finished Aug 07 06:57:47 PM PDT 24
Peak memory 217044 kb
Host smart-b151efac-bf60-4c74-bda4-4b2843bfeda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469039214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3469039214
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2417500915
Short name T438
Test name
Test status
Simulation time 21351892 ps
CPU time 1.15 seconds
Started Aug 07 06:57:45 PM PDT 24
Finished Aug 07 06:57:46 PM PDT 24
Peak memory 218152 kb
Host smart-cbde7a4c-ccd3-409f-9bc0-fe8d416317fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417500915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2417500915
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.1604045438
Short name T718
Test name
Test status
Simulation time 27273478 ps
CPU time 1.26 seconds
Started Aug 07 06:57:46 PM PDT 24
Finished Aug 07 06:57:47 PM PDT 24
Peak memory 217232 kb
Host smart-88608efa-2799-416f-a4f1-d93bfbcefcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604045438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1604045438
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.668207059
Short name T730
Test name
Test status
Simulation time 42472131 ps
CPU time 1.17 seconds
Started Aug 07 06:57:47 PM PDT 24
Finished Aug 07 06:57:49 PM PDT 24
Peak memory 219248 kb
Host smart-7b772e32-94b3-4377-9c10-64cf0ed4eaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668207059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.668207059
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.2886384070
Short name T361
Test name
Test status
Simulation time 54570653 ps
CPU time 1.62 seconds
Started Aug 07 06:57:47 PM PDT 24
Finished Aug 07 06:57:49 PM PDT 24
Peak memory 218092 kb
Host smart-16cc7d6c-a2cb-41b4-aea2-1ef574367976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886384070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2886384070
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.639202917
Short name T777
Test name
Test status
Simulation time 31684094 ps
CPU time 1.33 seconds
Started Aug 07 06:57:50 PM PDT 24
Finished Aug 07 06:57:51 PM PDT 24
Peak memory 218176 kb
Host smart-01892819-e92d-4a57-beec-75b393307a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639202917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.639202917
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.4270333684
Short name T368
Test name
Test status
Simulation time 46895925 ps
CPU time 1.86 seconds
Started Aug 07 06:57:46 PM PDT 24
Finished Aug 07 06:57:48 PM PDT 24
Peak memory 218132 kb
Host smart-31b71abf-6dc4-4c3e-a752-c9aa8455cf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270333684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.4270333684
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3637760235
Short name T149
Test name
Test status
Simulation time 57992045 ps
CPU time 1.28 seconds
Started Aug 07 06:57:51 PM PDT 24
Finished Aug 07 06:57:52 PM PDT 24
Peak memory 218852 kb
Host smart-bfde2f1d-1782-4757-83cc-e2ee64d81285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637760235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3637760235
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3738402046
Short name T609
Test name
Test status
Simulation time 51100483 ps
CPU time 1.53 seconds
Started Aug 07 06:57:50 PM PDT 24
Finished Aug 07 06:57:52 PM PDT 24
Peak memory 218364 kb
Host smart-3019a296-9ed0-4964-bade-775db71e9931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738402046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3738402046
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1174031717
Short name T429
Test name
Test status
Simulation time 50419957 ps
CPU time 1.23 seconds
Started Aug 07 06:55:40 PM PDT 24
Finished Aug 07 06:55:41 PM PDT 24
Peak memory 215312 kb
Host smart-a2a9f53b-f52a-4959-a0d1-248fb4f3329b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174031717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1174031717
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1103104538
Short name T482
Test name
Test status
Simulation time 39462528 ps
CPU time 0.88 seconds
Started Aug 07 06:55:48 PM PDT 24
Finished Aug 07 06:55:49 PM PDT 24
Peak memory 206364 kb
Host smart-4459cdf0-08cd-4aaf-b479-e15477c39b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103104538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1103104538
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2395957935
Short name T141
Test name
Test status
Simulation time 58310825 ps
CPU time 1.16 seconds
Started Aug 07 06:55:40 PM PDT 24
Finished Aug 07 06:55:42 PM PDT 24
Peak memory 218144 kb
Host smart-204882d9-666e-4d69-a28a-421481e079fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395957935 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2395957935
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.2677926223
Short name T826
Test name
Test status
Simulation time 27139870 ps
CPU time 1.06 seconds
Started Aug 07 06:55:40 PM PDT 24
Finished Aug 07 06:55:41 PM PDT 24
Peak memory 216996 kb
Host smart-4b06e87e-90e4-4645-8094-8010a978d02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677926223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2677926223
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2835460989
Short name T547
Test name
Test status
Simulation time 19806153 ps
CPU time 1.1 seconds
Started Aug 07 06:55:41 PM PDT 24
Finished Aug 07 06:55:42 PM PDT 24
Peak memory 215612 kb
Host smart-7f364815-37dc-46c4-807d-c317fbfd4d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835460989 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2835460989
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1067175107
Short name T721
Test name
Test status
Simulation time 19197823 ps
CPU time 1.01 seconds
Started Aug 07 06:55:42 PM PDT 24
Finished Aug 07 06:55:43 PM PDT 24
Peak memory 214844 kb
Host smart-a852f056-3d7e-4276-8045-b764b3a1e929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067175107 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1067175107
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.317778021
Short name T860
Test name
Test status
Simulation time 308011194 ps
CPU time 6.12 seconds
Started Aug 07 06:55:41 PM PDT 24
Finished Aug 07 06:55:47 PM PDT 24
Peak memory 219804 kb
Host smart-2834e18a-8f27-4412-94ba-4586677956e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317778021 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.317778021
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2784849570
Short name T588
Test name
Test status
Simulation time 39852752914 ps
CPU time 1030.56 seconds
Started Aug 07 06:55:40 PM PDT 24
Finished Aug 07 07:12:51 PM PDT 24
Peak memory 223400 kb
Host smart-5f86c441-96e6-478f-a1d0-39d2bbd0e12a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784849570 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2784849570
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.890133314
Short name T841
Test name
Test status
Simulation time 79688005 ps
CPU time 1.16 seconds
Started Aug 07 06:57:53 PM PDT 24
Finished Aug 07 06:57:54 PM PDT 24
Peak memory 219132 kb
Host smart-275f58e8-10bd-4384-a8b1-3681be33f983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890133314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.890133314
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.3938668391
Short name T754
Test name
Test status
Simulation time 48711037 ps
CPU time 1.76 seconds
Started Aug 07 06:57:52 PM PDT 24
Finished Aug 07 06:57:54 PM PDT 24
Peak memory 218024 kb
Host smart-ff5f23be-4caa-481c-b095-e0871af0b5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938668391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3938668391
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.532886939
Short name T840
Test name
Test status
Simulation time 82021403 ps
CPU time 1.13 seconds
Started Aug 07 06:57:54 PM PDT 24
Finished Aug 07 06:57:55 PM PDT 24
Peak memory 219712 kb
Host smart-c19e6ae4-0d0b-4501-a383-8f2dfc7d7426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532886939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.532886939
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.4157771380
Short name T450
Test name
Test status
Simulation time 57401605 ps
CPU time 1.27 seconds
Started Aug 07 06:57:50 PM PDT 24
Finished Aug 07 06:57:51 PM PDT 24
Peak memory 218460 kb
Host smart-dc23a3a6-7b10-4869-810d-259cf0a9e551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157771380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.4157771380
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3866144145
Short name T663
Test name
Test status
Simulation time 39148317 ps
CPU time 1.09 seconds
Started Aug 07 06:57:53 PM PDT 24
Finished Aug 07 06:57:54 PM PDT 24
Peak memory 215312 kb
Host smart-77d0b036-ff5d-400b-96e0-8da3346ededa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866144145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3866144145
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.2016387707
Short name T710
Test name
Test status
Simulation time 68220599 ps
CPU time 1.02 seconds
Started Aug 07 06:57:52 PM PDT 24
Finished Aug 07 06:57:53 PM PDT 24
Peak memory 216864 kb
Host smart-c3a1ad75-4212-4f04-84a8-d320887abf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016387707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2016387707
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.3349345050
Short name T675
Test name
Test status
Simulation time 24240085 ps
CPU time 1.15 seconds
Started Aug 07 06:57:52 PM PDT 24
Finished Aug 07 06:57:53 PM PDT 24
Peak memory 215312 kb
Host smart-d084b433-c5d4-4dde-b45d-635c9136f8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349345050 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3349345050
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.2877208969
Short name T630
Test name
Test status
Simulation time 100271408 ps
CPU time 1.2 seconds
Started Aug 07 06:57:55 PM PDT 24
Finished Aug 07 06:57:56 PM PDT 24
Peak memory 218304 kb
Host smart-c6b07fd5-9823-4b6d-9bff-4a781a93e0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877208969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2877208969
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.1163272712
Short name T820
Test name
Test status
Simulation time 67553028 ps
CPU time 1.18 seconds
Started Aug 07 06:57:56 PM PDT 24
Finished Aug 07 06:57:57 PM PDT 24
Peak memory 219244 kb
Host smart-41a57d95-b824-43c0-812d-7ed4c9a6b362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163272712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1163272712
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1067571513
Short name T874
Test name
Test status
Simulation time 127479709 ps
CPU time 1.09 seconds
Started Aug 07 06:57:55 PM PDT 24
Finished Aug 07 06:57:56 PM PDT 24
Peak memory 217308 kb
Host smart-186cccd6-e8b8-4340-b7eb-88bb7774cd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067571513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1067571513
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3676117426
Short name T291
Test name
Test status
Simulation time 32421611 ps
CPU time 1.12 seconds
Started Aug 07 06:57:54 PM PDT 24
Finished Aug 07 06:57:55 PM PDT 24
Peak memory 217984 kb
Host smart-9f745b6c-ddf5-4e6c-b27f-9ca978e306b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676117426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3676117426
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.469167726
Short name T867
Test name
Test status
Simulation time 25786896 ps
CPU time 1.31 seconds
Started Aug 07 06:57:56 PM PDT 24
Finished Aug 07 06:57:57 PM PDT 24
Peak memory 218124 kb
Host smart-8f311992-919d-44b6-81ab-010be9245910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469167726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.469167726
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1492572614
Short name T417
Test name
Test status
Simulation time 66297477 ps
CPU time 1.36 seconds
Started Aug 07 06:57:55 PM PDT 24
Finished Aug 07 06:57:57 PM PDT 24
Peak memory 219636 kb
Host smart-184531ff-9c99-4a59-8f8b-d199af429023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492572614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1492572614
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.2607822481
Short name T77
Test name
Test status
Simulation time 82313387 ps
CPU time 1.2 seconds
Started Aug 07 06:58:00 PM PDT 24
Finished Aug 07 06:58:01 PM PDT 24
Peak memory 218120 kb
Host smart-d45db093-ad55-4278-8333-4471ec742e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607822481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2607822481
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.4229003007
Short name T984
Test name
Test status
Simulation time 126610510 ps
CPU time 1.14 seconds
Started Aug 07 06:57:55 PM PDT 24
Finished Aug 07 06:57:57 PM PDT 24
Peak memory 216856 kb
Host smart-db97bd35-362f-4796-9a62-33af7dbaddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229003007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4229003007
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.735379904
Short name T114
Test name
Test status
Simulation time 31666937 ps
CPU time 1.38 seconds
Started Aug 07 06:58:02 PM PDT 24
Finished Aug 07 06:58:04 PM PDT 24
Peak memory 219468 kb
Host smart-12d9c7fc-3631-4b6a-b9af-5fec2f11a853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735379904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.735379904
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3723214634
Short name T631
Test name
Test status
Simulation time 42427297 ps
CPU time 1.47 seconds
Started Aug 07 06:58:04 PM PDT 24
Finished Aug 07 06:58:05 PM PDT 24
Peak memory 218360 kb
Host smart-1116546c-4b95-46e3-8efe-709a812c9131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723214634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3723214634
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3562766647
Short name T135
Test name
Test status
Simulation time 87556701 ps
CPU time 1.26 seconds
Started Aug 07 06:55:45 PM PDT 24
Finished Aug 07 06:55:47 PM PDT 24
Peak memory 218008 kb
Host smart-c8868abe-3fb2-4d59-b213-4e49104a89e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562766647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3562766647
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3425538718
Short name T465
Test name
Test status
Simulation time 52289458 ps
CPU time 0.94 seconds
Started Aug 07 06:55:45 PM PDT 24
Finished Aug 07 06:55:46 PM PDT 24
Peak memory 206320 kb
Host smart-1a637424-740a-46ac-8aec-3ffb9e91d6e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425538718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3425538718
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3587128957
Short name T727
Test name
Test status
Simulation time 56836784 ps
CPU time 1.17 seconds
Started Aug 07 06:55:45 PM PDT 24
Finished Aug 07 06:55:46 PM PDT 24
Peak memory 219332 kb
Host smart-f34fa6e3-752e-4f42-a41e-42ef03b6208a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587128957 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3587128957
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.229247615
Short name T542
Test name
Test status
Simulation time 22624314 ps
CPU time 0.9 seconds
Started Aug 07 06:55:45 PM PDT 24
Finished Aug 07 06:55:46 PM PDT 24
Peak memory 218476 kb
Host smart-2bf75741-faf7-4af4-b388-663102dfec76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229247615 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.229247615
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3301282952
Short name T786
Test name
Test status
Simulation time 36090272 ps
CPU time 1.04 seconds
Started Aug 07 06:55:44 PM PDT 24
Finished Aug 07 06:55:45 PM PDT 24
Peak memory 216884 kb
Host smart-ab489220-1a73-4b3d-8b25-5b0966778fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301282952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3301282952
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3433345806
Short name T655
Test name
Test status
Simulation time 22390441 ps
CPU time 1.01 seconds
Started Aug 07 06:55:45 PM PDT 24
Finished Aug 07 06:55:46 PM PDT 24
Peak memory 215732 kb
Host smart-044c275d-4739-4336-a9d9-fe959e5e2535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433345806 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3433345806
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.885453804
Short name T492
Test name
Test status
Simulation time 18622121 ps
CPU time 1.06 seconds
Started Aug 07 06:55:48 PM PDT 24
Finished Aug 07 06:55:49 PM PDT 24
Peak memory 214920 kb
Host smart-82be7fa0-31e1-4172-93fb-ea9f22c5887e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885453804 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.885453804
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2181864226
Short name T877
Test name
Test status
Simulation time 580687034 ps
CPU time 3.56 seconds
Started Aug 07 06:55:46 PM PDT 24
Finished Aug 07 06:55:50 PM PDT 24
Peak memory 214856 kb
Host smart-579dd1e9-b40d-4fc3-837c-18e77558c8e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181864226 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2181864226
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2205821030
Short name T475
Test name
Test status
Simulation time 12972295447 ps
CPU time 169.63 seconds
Started Aug 07 06:55:48 PM PDT 24
Finished Aug 07 06:58:38 PM PDT 24
Peak memory 222160 kb
Host smart-16a583fd-167c-4fd8-84a3-73109c1ec89a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205821030 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2205821030
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3172233152
Short name T306
Test name
Test status
Simulation time 69354136 ps
CPU time 2.51 seconds
Started Aug 07 06:58:01 PM PDT 24
Finished Aug 07 06:58:04 PM PDT 24
Peak memory 214936 kb
Host smart-2713819a-a072-4de7-9e40-524ae8380f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172233152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3172233152
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.2984936512
Short name T795
Test name
Test status
Simulation time 28568045 ps
CPU time 1.23 seconds
Started Aug 07 06:58:00 PM PDT 24
Finished Aug 07 06:58:02 PM PDT 24
Peak memory 219532 kb
Host smart-e87c8918-658f-4e49-b9ba-d5a7b7fbf39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984936512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.2984936512
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.3617153733
Short name T416
Test name
Test status
Simulation time 408391912 ps
CPU time 3.61 seconds
Started Aug 07 06:58:01 PM PDT 24
Finished Aug 07 06:58:04 PM PDT 24
Peak memory 219708 kb
Host smart-75f34c5b-0b2c-4c72-bcc0-7fc3a1b2dfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617153733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3617153733
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.2915683587
Short name T758
Test name
Test status
Simulation time 328348621 ps
CPU time 1.16 seconds
Started Aug 07 06:58:01 PM PDT 24
Finished Aug 07 06:58:02 PM PDT 24
Peak memory 220336 kb
Host smart-2e623a08-57dd-46f9-aee1-48be29f72249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915683587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2915683587
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3748651052
Short name T968
Test name
Test status
Simulation time 41267489 ps
CPU time 1.47 seconds
Started Aug 07 06:58:01 PM PDT 24
Finished Aug 07 06:58:02 PM PDT 24
Peak memory 219152 kb
Host smart-e15c5c8c-c049-41c7-98d1-acb0991ad4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748651052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3748651052
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2783743456
Short name T818
Test name
Test status
Simulation time 60701874 ps
CPU time 1.25 seconds
Started Aug 07 06:58:02 PM PDT 24
Finished Aug 07 06:58:04 PM PDT 24
Peak memory 216980 kb
Host smart-8685115e-4bb9-4cfc-ac6f-c1b6abd7d3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783743456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2783743456
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.1689885779
Short name T742
Test name
Test status
Simulation time 98438788 ps
CPU time 1.09 seconds
Started Aug 07 06:58:13 PM PDT 24
Finished Aug 07 06:58:15 PM PDT 24
Peak memory 218328 kb
Host smart-93ba4091-9b44-456a-a32d-a6c521863ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689885779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1689885779
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.60748052
Short name T762
Test name
Test status
Simulation time 58626130 ps
CPU time 1.18 seconds
Started Aug 07 06:58:05 PM PDT 24
Finished Aug 07 06:58:06 PM PDT 24
Peak memory 217028 kb
Host smart-85b8bcf9-ffd0-4fdd-8489-f4b50f831918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60748052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.60748052
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.3762522359
Short name T526
Test name
Test status
Simulation time 26491042 ps
CPU time 1.19 seconds
Started Aug 07 06:58:07 PM PDT 24
Finished Aug 07 06:58:08 PM PDT 24
Peak memory 218292 kb
Host smart-9fb0641c-4497-42a3-9a40-8fb9bb98f924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762522359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3762522359
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.3516481067
Short name T741
Test name
Test status
Simulation time 304686923 ps
CPU time 1.64 seconds
Started Aug 07 06:58:13 PM PDT 24
Finished Aug 07 06:58:15 PM PDT 24
Peak memory 218528 kb
Host smart-8beead71-a2a9-4748-8065-3d0c1501a0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516481067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3516481067
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.1768533344
Short name T584
Test name
Test status
Simulation time 24379019 ps
CPU time 1.23 seconds
Started Aug 07 06:58:07 PM PDT 24
Finished Aug 07 06:58:08 PM PDT 24
Peak memory 219792 kb
Host smart-6c433700-d649-4889-8e63-c91915a85049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768533344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1768533344
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.2883608145
Short name T596
Test name
Test status
Simulation time 50046269 ps
CPU time 1.41 seconds
Started Aug 07 06:58:12 PM PDT 24
Finished Aug 07 06:58:13 PM PDT 24
Peak memory 218148 kb
Host smart-2f140c68-fd2b-4e76-9e4f-cbde1a495109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883608145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2883608145
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.813574172
Short name T734
Test name
Test status
Simulation time 45052547 ps
CPU time 1.15 seconds
Started Aug 07 06:58:13 PM PDT 24
Finished Aug 07 06:58:14 PM PDT 24
Peak memory 218260 kb
Host smart-f5a40830-c3b2-4fed-a442-b98f8178ab26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813574172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.813574172
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.3260751454
Short name T771
Test name
Test status
Simulation time 69427217 ps
CPU time 1.31 seconds
Started Aug 07 06:58:06 PM PDT 24
Finished Aug 07 06:58:08 PM PDT 24
Peak memory 218972 kb
Host smart-43a65097-d2f0-46d7-a241-70c789daf989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260751454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3260751454
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.223672604
Short name T468
Test name
Test status
Simulation time 40301779 ps
CPU time 1.07 seconds
Started Aug 07 06:58:08 PM PDT 24
Finished Aug 07 06:58:10 PM PDT 24
Peak memory 218036 kb
Host smart-0d3b92c6-7d13-412b-bf0f-efb392c4411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223672604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.223672604
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.877532680
Short name T687
Test name
Test status
Simulation time 61884847 ps
CPU time 1.18 seconds
Started Aug 07 06:58:07 PM PDT 24
Finished Aug 07 06:58:08 PM PDT 24
Peak memory 219708 kb
Host smart-042761a8-3e9b-4282-8839-5e5052e02d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877532680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.877532680
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.1642135613
Short name T545
Test name
Test status
Simulation time 66502601 ps
CPU time 1.19 seconds
Started Aug 07 06:58:09 PM PDT 24
Finished Aug 07 06:58:11 PM PDT 24
Peak memory 219432 kb
Host smart-d8d14789-b2b2-43bb-af50-924967f25ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642135613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1642135613
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.1300341568
Short name T764
Test name
Test status
Simulation time 202163517 ps
CPU time 1.49 seconds
Started Aug 07 06:58:06 PM PDT 24
Finished Aug 07 06:58:07 PM PDT 24
Peak memory 219508 kb
Host smart-683630df-2750-4e91-84dd-0805eb1943e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300341568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1300341568
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.4009270354
Short name T894
Test name
Test status
Simulation time 31546712 ps
CPU time 1.3 seconds
Started Aug 07 06:55:44 PM PDT 24
Finished Aug 07 06:55:46 PM PDT 24
Peak memory 215312 kb
Host smart-6a30f8b2-04ea-485c-8b51-04a0e81ef444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009270354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.4009270354
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2493340099
Short name T815
Test name
Test status
Simulation time 13128289 ps
CPU time 0.86 seconds
Started Aug 07 06:55:50 PM PDT 24
Finished Aug 07 06:55:51 PM PDT 24
Peak memory 206596 kb
Host smart-9446319d-c150-40b7-b40f-f09ba23e93b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493340099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2493340099
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1959819798
Short name T479
Test name
Test status
Simulation time 144853254 ps
CPU time 0.87 seconds
Started Aug 07 06:55:48 PM PDT 24
Finished Aug 07 06:55:50 PM PDT 24
Peak memory 215916 kb
Host smart-d520e8b8-a08d-4ebe-9765-2500f2ff0af6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959819798 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1959819798
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1471286624
Short name T453
Test name
Test status
Simulation time 61053090 ps
CPU time 1.11 seconds
Started Aug 07 06:55:50 PM PDT 24
Finished Aug 07 06:55:52 PM PDT 24
Peak memory 219120 kb
Host smart-3ff8f1f3-1e16-4578-abe4-cf4dd103fa21
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471286624 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1471286624
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2908488887
Short name T45
Test name
Test status
Simulation time 34079020 ps
CPU time 1.6 seconds
Started Aug 07 06:55:45 PM PDT 24
Finished Aug 07 06:55:47 PM PDT 24
Peak memory 225564 kb
Host smart-a8cdfc13-3880-412a-98ab-b77912c8333f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908488887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2908488887
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1366445731
Short name T40
Test name
Test status
Simulation time 49620432 ps
CPU time 1.09 seconds
Started Aug 07 06:55:46 PM PDT 24
Finished Aug 07 06:55:48 PM PDT 24
Peak memory 216992 kb
Host smart-32e2d3ba-6fd0-47cf-af71-36569b9d467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366445731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1366445731
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1304494922
Short name T565
Test name
Test status
Simulation time 29335602 ps
CPU time 0.96 seconds
Started Aug 07 06:55:49 PM PDT 24
Finished Aug 07 06:55:50 PM PDT 24
Peak memory 215152 kb
Host smart-0dba3f44-8efc-4608-b51f-0f4adbe52e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304494922 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1304494922
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1356838980
Short name T356
Test name
Test status
Simulation time 40441649 ps
CPU time 0.89 seconds
Started Aug 07 06:55:45 PM PDT 24
Finished Aug 07 06:55:46 PM PDT 24
Peak memory 214912 kb
Host smart-89d35e67-d52b-4e34-b698-29c97cb088c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356838980 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1356838980
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1885859310
Short name T348
Test name
Test status
Simulation time 84552404 ps
CPU time 1.13 seconds
Started Aug 07 06:55:45 PM PDT 24
Finished Aug 07 06:55:46 PM PDT 24
Peak memory 216868 kb
Host smart-d7ec3834-367d-4d03-82ae-c824223c87ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885859310 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1885859310
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2610156095
Short name T866
Test name
Test status
Simulation time 34021586916 ps
CPU time 879.22 seconds
Started Aug 07 06:55:48 PM PDT 24
Finished Aug 07 07:10:27 PM PDT 24
Peak memory 223404 kb
Host smart-aa8c9d63-bcd9-45f8-8564-4a41bf42cbda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610156095 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2610156095
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2959610540
Short name T907
Test name
Test status
Simulation time 84999124 ps
CPU time 1.15 seconds
Started Aug 07 06:58:09 PM PDT 24
Finished Aug 07 06:58:10 PM PDT 24
Peak memory 219260 kb
Host smart-25c41671-e185-4be5-80e9-3a4cd3955536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959610540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2959610540
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2789176231
Short name T856
Test name
Test status
Simulation time 105787798 ps
CPU time 2.52 seconds
Started Aug 07 06:58:06 PM PDT 24
Finished Aug 07 06:58:09 PM PDT 24
Peak memory 219096 kb
Host smart-ff02d84f-1a3d-4169-9bb6-047701075fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789176231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2789176231
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1475526552
Short name T481
Test name
Test status
Simulation time 42982469 ps
CPU time 1.79 seconds
Started Aug 07 06:58:19 PM PDT 24
Finished Aug 07 06:58:20 PM PDT 24
Peak memory 215100 kb
Host smart-a5044e5e-fcfc-4123-b3b0-7d8928aea3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475526552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1475526552
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.4167791617
Short name T768
Test name
Test status
Simulation time 22518191 ps
CPU time 1.07 seconds
Started Aug 07 06:58:11 PM PDT 24
Finished Aug 07 06:58:13 PM PDT 24
Peak memory 218320 kb
Host smart-8b75ea39-ec78-4f5a-88e0-e7ec4406e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167791617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.4167791617
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3162903041
Short name T686
Test name
Test status
Simulation time 184973770 ps
CPU time 1.71 seconds
Started Aug 07 06:58:11 PM PDT 24
Finished Aug 07 06:58:13 PM PDT 24
Peak memory 218284 kb
Host smart-78424c40-e159-4eb1-a427-1a841ce14b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162903041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3162903041
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2545784275
Short name T358
Test name
Test status
Simulation time 89033632 ps
CPU time 1.19 seconds
Started Aug 07 06:58:11 PM PDT 24
Finished Aug 07 06:58:12 PM PDT 24
Peak memory 217004 kb
Host smart-5077077b-144b-475b-a04b-8b2b758696ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545784275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2545784275
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.3090836562
Short name T432
Test name
Test status
Simulation time 58142408 ps
CPU time 1.22 seconds
Started Aug 07 06:58:16 PM PDT 24
Finished Aug 07 06:58:17 PM PDT 24
Peak memory 220572 kb
Host smart-da63679f-74ef-4e6e-9bf8-e5a4ef8d0311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090836562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3090836562
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.2165274719
Short name T902
Test name
Test status
Simulation time 256230992 ps
CPU time 1.17 seconds
Started Aug 07 06:58:13 PM PDT 24
Finished Aug 07 06:58:14 PM PDT 24
Peak memory 217252 kb
Host smart-927893c4-87ed-45d1-ac32-f45dfe998ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165274719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2165274719
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.933910721
Short name T252
Test name
Test status
Simulation time 33422990 ps
CPU time 1.43 seconds
Started Aug 07 06:58:12 PM PDT 24
Finished Aug 07 06:58:13 PM PDT 24
Peak memory 215312 kb
Host smart-9f29ef84-a56c-4e7d-92a0-88e144f3336c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933910721 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.933910721
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.327849490
Short name T447
Test name
Test status
Simulation time 30599860 ps
CPU time 1.4 seconds
Started Aug 07 06:58:19 PM PDT 24
Finished Aug 07 06:58:20 PM PDT 24
Peak memory 219552 kb
Host smart-7bf0d54b-f6e6-4b01-a424-9c3df13f7411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327849490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.327849490
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.187533681
Short name T445
Test name
Test status
Simulation time 41823468 ps
CPU time 1.15 seconds
Started Aug 07 06:58:13 PM PDT 24
Finished Aug 07 06:58:14 PM PDT 24
Peak memory 219248 kb
Host smart-3ab78e9c-98d2-4854-99dd-5e1c27a0bc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187533681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.187533681
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.1509185107
Short name T412
Test name
Test status
Simulation time 36383295 ps
CPU time 1.46 seconds
Started Aug 07 06:58:13 PM PDT 24
Finished Aug 07 06:58:15 PM PDT 24
Peak memory 218184 kb
Host smart-becc0fce-2aba-40d7-aea6-64fa31f413d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509185107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1509185107
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2472982428
Short name T859
Test name
Test status
Simulation time 31438418 ps
CPU time 1.2 seconds
Started Aug 07 06:58:16 PM PDT 24
Finished Aug 07 06:58:17 PM PDT 24
Peak memory 219608 kb
Host smart-f7cdd113-c6ed-46c0-a31e-97ba2cdcfc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472982428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2472982428
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.3750055638
Short name T793
Test name
Test status
Simulation time 49470462 ps
CPU time 1.27 seconds
Started Aug 07 06:58:09 PM PDT 24
Finished Aug 07 06:58:10 PM PDT 24
Peak memory 218296 kb
Host smart-dfe1e86c-3411-4a81-90dc-a42b0138e581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750055638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3750055638
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3463189966
Short name T192
Test name
Test status
Simulation time 101036534 ps
CPU time 1.26 seconds
Started Aug 07 06:58:13 PM PDT 24
Finished Aug 07 06:58:15 PM PDT 24
Peak memory 220584 kb
Host smart-74a36d10-c593-441c-9c1d-5b3c3d286f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463189966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3463189966
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3813643802
Short name T678
Test name
Test status
Simulation time 42576114 ps
CPU time 1.2 seconds
Started Aug 07 06:58:14 PM PDT 24
Finished Aug 07 06:58:15 PM PDT 24
Peak memory 218380 kb
Host smart-d4b2f1ff-cfdf-4773-a92c-beaf52132496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813643802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3813643802
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.20270078
Short name T906
Test name
Test status
Simulation time 64572303 ps
CPU time 1.16 seconds
Started Aug 07 06:58:18 PM PDT 24
Finished Aug 07 06:58:19 PM PDT 24
Peak memory 217192 kb
Host smart-f2c2840c-b2cc-4250-9e53-a8b2c6312043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20270078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.20270078
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3518025816
Short name T644
Test name
Test status
Simulation time 33766532 ps
CPU time 1.41 seconds
Started Aug 07 06:55:51 PM PDT 24
Finished Aug 07 06:55:52 PM PDT 24
Peak memory 215292 kb
Host smart-b19587ed-bedf-46a3-b4e7-121b70879295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518025816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3518025816
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable.3298894151
Short name T178
Test name
Test status
Simulation time 20620654 ps
CPU time 0.86 seconds
Started Aug 07 06:55:52 PM PDT 24
Finished Aug 07 06:55:53 PM PDT 24
Peak memory 216216 kb
Host smart-3238fb6e-189c-4f9e-bc1f-fafe87855cd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298894151 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3298894151
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1138972536
Short name T59
Test name
Test status
Simulation time 60509256 ps
CPU time 1.1 seconds
Started Aug 07 06:55:50 PM PDT 24
Finished Aug 07 06:55:51 PM PDT 24
Peak memory 219156 kb
Host smart-ae8fba47-b6b5-44da-a8ee-2c3679cf5047
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138972536 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1138972536
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2542354864
Short name T561
Test name
Test status
Simulation time 69294230 ps
CPU time 1.05 seconds
Started Aug 07 06:55:50 PM PDT 24
Finished Aug 07 06:55:51 PM PDT 24
Peak memory 219516 kb
Host smart-6714d406-2f2b-4cf1-bb99-d291e77cb5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542354864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2542354864
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.215681578
Short name T649
Test name
Test status
Simulation time 40135784 ps
CPU time 1.8 seconds
Started Aug 07 06:55:52 PM PDT 24
Finished Aug 07 06:55:54 PM PDT 24
Peak memory 217220 kb
Host smart-42a3e1c2-4a67-4d30-aa29-0a8a10f576b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215681578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.215681578
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1402279653
Short name T102
Test name
Test status
Simulation time 27409159 ps
CPU time 0.94 seconds
Started Aug 07 06:55:49 PM PDT 24
Finished Aug 07 06:55:50 PM PDT 24
Peak memory 215608 kb
Host smart-1a609a8b-ef6e-478c-8a54-bfa587ef8ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402279653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1402279653
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2760475400
Short name T624
Test name
Test status
Simulation time 15468798 ps
CPU time 0.98 seconds
Started Aug 07 06:55:54 PM PDT 24
Finished Aug 07 06:55:55 PM PDT 24
Peak memory 214880 kb
Host smart-347d1ffe-20a7-4e81-bc4a-9675ed1ef1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760475400 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2760475400
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1484044370
Short name T927
Test name
Test status
Simulation time 751426981 ps
CPU time 4.03 seconds
Started Aug 07 06:55:54 PM PDT 24
Finished Aug 07 06:55:58 PM PDT 24
Peak memory 216860 kb
Host smart-f565b7fa-b648-4e4b-9450-e1cfd422e3b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484044370 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1484044370
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.4100842017
Short name T22
Test name
Test status
Simulation time 124178935339 ps
CPU time 799.24 seconds
Started Aug 07 06:55:50 PM PDT 24
Finished Aug 07 07:09:09 PM PDT 24
Peak memory 223380 kb
Host smart-fb6bcc78-2121-4e3f-bd73-901886ec0d19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100842017 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.4100842017
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.2302994483
Short name T784
Test name
Test status
Simulation time 53520424 ps
CPU time 1.22 seconds
Started Aug 07 06:58:16 PM PDT 24
Finished Aug 07 06:58:17 PM PDT 24
Peak memory 218364 kb
Host smart-7abf4551-48c4-459a-b916-828201e97ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302994483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.2302994483
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2430064944
Short name T441
Test name
Test status
Simulation time 98462117 ps
CPU time 1.28 seconds
Started Aug 07 06:58:16 PM PDT 24
Finished Aug 07 06:58:18 PM PDT 24
Peak memory 217032 kb
Host smart-335a8200-c84d-48d7-a350-859eeee4fdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430064944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2430064944
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2502798598
Short name T575
Test name
Test status
Simulation time 30540836 ps
CPU time 1.26 seconds
Started Aug 07 06:58:16 PM PDT 24
Finished Aug 07 06:58:17 PM PDT 24
Peak memory 215308 kb
Host smart-37f8086f-f8a1-4e09-9a1d-42b550e89d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502798598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2502798598
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.2929400656
Short name T473
Test name
Test status
Simulation time 72837981 ps
CPU time 1.55 seconds
Started Aug 07 06:58:19 PM PDT 24
Finished Aug 07 06:58:20 PM PDT 24
Peak memory 218372 kb
Host smart-0b94ff47-fd35-423c-a2e9-635076c420b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929400656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2929400656
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.4251543960
Short name T580
Test name
Test status
Simulation time 356680322 ps
CPU time 1.37 seconds
Started Aug 07 06:58:17 PM PDT 24
Finished Aug 07 06:58:18 PM PDT 24
Peak memory 220000 kb
Host smart-cf314323-d47e-454f-a206-aaf029914a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251543960 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.4251543960
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3302076867
Short name T23
Test name
Test status
Simulation time 80725437 ps
CPU time 1.14 seconds
Started Aug 07 06:58:19 PM PDT 24
Finished Aug 07 06:58:20 PM PDT 24
Peak memory 216916 kb
Host smart-023368ac-39f6-4b60-8eb5-eca442c07f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302076867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3302076867
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.4172452595
Short name T504
Test name
Test status
Simulation time 93233231 ps
CPU time 1.26 seconds
Started Aug 07 06:58:17 PM PDT 24
Finished Aug 07 06:58:18 PM PDT 24
Peak memory 220116 kb
Host smart-a6abad66-a1c2-45af-9a0e-a2e8a952ef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172452595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.4172452595
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.4043958513
Short name T654
Test name
Test status
Simulation time 51892210 ps
CPU time 1.18 seconds
Started Aug 07 06:58:18 PM PDT 24
Finished Aug 07 06:58:19 PM PDT 24
Peak memory 217024 kb
Host smart-f9f7f23b-fd67-4ef7-8e67-02a0d7a04f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043958513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4043958513
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.20857502
Short name T119
Test name
Test status
Simulation time 124418670 ps
CPU time 1.28 seconds
Started Aug 07 06:58:23 PM PDT 24
Finished Aug 07 06:58:24 PM PDT 24
Peak memory 215316 kb
Host smart-8cbb1b8c-6d32-405a-bb44-6a11e7a725d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20857502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.20857502
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.3670105159
Short name T239
Test name
Test status
Simulation time 104185713 ps
CPU time 1.12 seconds
Started Aug 07 06:58:24 PM PDT 24
Finished Aug 07 06:58:25 PM PDT 24
Peak memory 214936 kb
Host smart-b741eaf9-e10b-4c4a-9131-b9ee0633ea17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670105159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3670105159
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.1985624922
Short name T427
Test name
Test status
Simulation time 83174079 ps
CPU time 1.18 seconds
Started Aug 07 06:58:24 PM PDT 24
Finished Aug 07 06:58:25 PM PDT 24
Peak memory 218952 kb
Host smart-563a4a69-0a0b-4e8e-93ac-b475f98a2ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985624922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1985624922
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2001169535
Short name T838
Test name
Test status
Simulation time 151121661 ps
CPU time 1.01 seconds
Started Aug 07 06:58:23 PM PDT 24
Finished Aug 07 06:58:24 PM PDT 24
Peak memory 216916 kb
Host smart-4bd93248-ef02-49f8-b176-799cb2e507e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001169535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2001169535
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1595501284
Short name T555
Test name
Test status
Simulation time 55303954 ps
CPU time 1.94 seconds
Started Aug 07 06:58:26 PM PDT 24
Finished Aug 07 06:58:28 PM PDT 24
Peak memory 218136 kb
Host smart-ef157379-98e7-47e8-84fc-c7df8fb3c47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595501284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1595501284
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.663678509
Short name T889
Test name
Test status
Simulation time 76588883 ps
CPU time 1.16 seconds
Started Aug 07 06:58:25 PM PDT 24
Finished Aug 07 06:58:26 PM PDT 24
Peak memory 218404 kb
Host smart-ad154502-d184-4acb-98ee-3174c75d8754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663678509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.663678509
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3443502275
Short name T809
Test name
Test status
Simulation time 285228912 ps
CPU time 3.36 seconds
Started Aug 07 06:58:23 PM PDT 24
Finished Aug 07 06:58:27 PM PDT 24
Peak memory 219788 kb
Host smart-cfa9fe37-e403-4e4c-8996-3ce2341bcc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443502275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3443502275
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.4192764550
Short name T393
Test name
Test status
Simulation time 21304272 ps
CPU time 1.12 seconds
Started Aug 07 06:58:26 PM PDT 24
Finished Aug 07 06:58:28 PM PDT 24
Peak memory 218404 kb
Host smart-46f91c47-421d-4210-ab1f-b622e60cfdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192764550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.4192764550
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2483441078
Short name T573
Test name
Test status
Simulation time 293534384 ps
CPU time 1.63 seconds
Started Aug 07 06:58:26 PM PDT 24
Finished Aug 07 06:58:27 PM PDT 24
Peak memory 218560 kb
Host smart-0c762949-4772-4bbc-940d-61628d7413d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483441078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2483441078
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.1866946730
Short name T934
Test name
Test status
Simulation time 76925710 ps
CPU time 1.25 seconds
Started Aug 07 06:58:28 PM PDT 24
Finished Aug 07 06:58:29 PM PDT 24
Peak memory 218216 kb
Host smart-91852887-bb63-4d4a-893e-d28503a52f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866946730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1866946730
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.1002604868
Short name T423
Test name
Test status
Simulation time 70159801 ps
CPU time 1.29 seconds
Started Aug 07 06:58:26 PM PDT 24
Finished Aug 07 06:58:28 PM PDT 24
Peak memory 217972 kb
Host smart-c2fba124-f87d-4198-a4bf-5ea408b29b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002604868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1002604868
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3889975619
Short name T947
Test name
Test status
Simulation time 34684064 ps
CPU time 1.13 seconds
Started Aug 07 06:55:50 PM PDT 24
Finished Aug 07 06:55:51 PM PDT 24
Peak memory 218120 kb
Host smart-0457d283-811a-40ff-b409-8c9efd11c43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889975619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3889975619
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1010160178
Short name T442
Test name
Test status
Simulation time 15730131 ps
CPU time 0.97 seconds
Started Aug 07 06:55:52 PM PDT 24
Finished Aug 07 06:55:53 PM PDT 24
Peak memory 206332 kb
Host smart-24b19be0-3633-4969-a117-1b376c6d4e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010160178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1010160178
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3663910649
Short name T88
Test name
Test status
Simulation time 20602135 ps
CPU time 0.86 seconds
Started Aug 07 06:55:50 PM PDT 24
Finished Aug 07 06:55:51 PM PDT 24
Peak memory 216216 kb
Host smart-c9e4edee-aa4d-4bca-94cb-e263cef6e1dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663910649 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3663910649
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2674829669
Short name T755
Test name
Test status
Simulation time 40757683 ps
CPU time 1.33 seconds
Started Aug 07 06:55:52 PM PDT 24
Finished Aug 07 06:55:54 PM PDT 24
Peak memory 218012 kb
Host smart-4b3b12ec-e8ee-4550-ba90-264223d652ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674829669 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2674829669
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1151682737
Short name T57
Test name
Test status
Simulation time 55139276 ps
CPU time 0.97 seconds
Started Aug 07 06:55:51 PM PDT 24
Finished Aug 07 06:55:53 PM PDT 24
Peak memory 219476 kb
Host smart-af3daac9-f3d4-41c4-ae8f-c9f8462819f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151682737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1151682737
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2530175651
Short name T811
Test name
Test status
Simulation time 133616781 ps
CPU time 1.49 seconds
Started Aug 07 06:55:52 PM PDT 24
Finished Aug 07 06:55:54 PM PDT 24
Peak memory 218280 kb
Host smart-73a19b84-a566-41f3-9934-7ce179e0df51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530175651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2530175651
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2416017332
Short name T103
Test name
Test status
Simulation time 27947516 ps
CPU time 0.94 seconds
Started Aug 07 06:55:49 PM PDT 24
Finished Aug 07 06:55:50 PM PDT 24
Peak memory 215600 kb
Host smart-3e283ff3-af88-4e36-8298-603ca7e9fdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416017332 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2416017332
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2818286050
Short name T783
Test name
Test status
Simulation time 106707880 ps
CPU time 0.88 seconds
Started Aug 07 06:55:54 PM PDT 24
Finished Aug 07 06:55:55 PM PDT 24
Peak memory 214888 kb
Host smart-e4191720-6a85-49c9-9f77-a01ae055a2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818286050 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2818286050
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3382393384
Short name T472
Test name
Test status
Simulation time 140492806 ps
CPU time 2.98 seconds
Started Aug 07 06:55:49 PM PDT 24
Finished Aug 07 06:55:52 PM PDT 24
Peak memory 216816 kb
Host smart-b25eb7bf-7131-4537-a0df-dbdd3c68762b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382393384 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3382393384
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1548769434
Short name T983
Test name
Test status
Simulation time 84944301943 ps
CPU time 2152.83 seconds
Started Aug 07 06:55:51 PM PDT 24
Finished Aug 07 07:31:44 PM PDT 24
Peak memory 229360 kb
Host smart-c5cfcc50-fdf9-4fc7-912d-d24430e2648c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548769434 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1548769434
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.3549109663
Short name T822
Test name
Test status
Simulation time 24597534 ps
CPU time 1.22 seconds
Started Aug 07 06:58:27 PM PDT 24
Finished Aug 07 06:58:28 PM PDT 24
Peak memory 219592 kb
Host smart-7a47969f-bd9f-448a-8356-ac3400006466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549109663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3549109663
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.608325429
Short name T17
Test name
Test status
Simulation time 88919383 ps
CPU time 2.83 seconds
Started Aug 07 06:58:28 PM PDT 24
Finished Aug 07 06:58:31 PM PDT 24
Peak memory 218336 kb
Host smart-7a934e6e-ba83-4ad5-b621-6762f5c9f9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608325429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.608325429
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.4029420429
Short name T796
Test name
Test status
Simulation time 24784866 ps
CPU time 1.1 seconds
Started Aug 07 06:58:29 PM PDT 24
Finished Aug 07 06:58:31 PM PDT 24
Peak memory 219232 kb
Host smart-aeb9ef98-63d5-4c54-9787-ccc4af9c992f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029420429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.4029420429
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/152.edn_alert.1717896331
Short name T688
Test name
Test status
Simulation time 74815403 ps
CPU time 1.17 seconds
Started Aug 07 06:58:30 PM PDT 24
Finished Aug 07 06:58:31 PM PDT 24
Peak memory 218316 kb
Host smart-c292006c-9dc6-4356-ae04-9c2cf3c463fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717896331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1717896331
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3852250280
Short name T350
Test name
Test status
Simulation time 80039400 ps
CPU time 0.96 seconds
Started Aug 07 06:58:31 PM PDT 24
Finished Aug 07 06:58:32 PM PDT 24
Peak memory 216904 kb
Host smart-89b1f688-3110-4269-9fa4-5279bdcd8865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852250280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3852250280
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.4294242106
Short name T586
Test name
Test status
Simulation time 79315824 ps
CPU time 1.17 seconds
Started Aug 07 06:58:28 PM PDT 24
Finished Aug 07 06:58:29 PM PDT 24
Peak memory 219948 kb
Host smart-ab8720ad-2bc5-4694-a9df-f00f395b3d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294242106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.4294242106
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3919826552
Short name T592
Test name
Test status
Simulation time 55362384 ps
CPU time 1.21 seconds
Started Aug 07 06:58:30 PM PDT 24
Finished Aug 07 06:58:31 PM PDT 24
Peak memory 218060 kb
Host smart-043dbef9-46c0-4779-aac2-58177d6836ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919826552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3919826552
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.399943004
Short name T288
Test name
Test status
Simulation time 45416468 ps
CPU time 1.24 seconds
Started Aug 07 06:58:27 PM PDT 24
Finished Aug 07 06:58:28 PM PDT 24
Peak memory 218380 kb
Host smart-6b309bf9-396e-4e49-86f8-af721cf39c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399943004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.399943004
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.3438560962
Short name T240
Test name
Test status
Simulation time 51652914 ps
CPU time 1.53 seconds
Started Aug 07 06:58:29 PM PDT 24
Finished Aug 07 06:58:31 PM PDT 24
Peak memory 217220 kb
Host smart-b7d325da-186d-4ce1-a0f9-55bb960a9178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438560962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3438560962
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.4205724682
Short name T274
Test name
Test status
Simulation time 47029604 ps
CPU time 1.18 seconds
Started Aug 07 06:58:29 PM PDT 24
Finished Aug 07 06:58:30 PM PDT 24
Peak memory 218204 kb
Host smart-cca249a1-712f-4bd3-afc7-9cafdbb9a981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205724682 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.4205724682
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1414849237
Short name T341
Test name
Test status
Simulation time 45140841 ps
CPU time 1.55 seconds
Started Aug 07 06:58:31 PM PDT 24
Finished Aug 07 06:58:32 PM PDT 24
Peak memory 218212 kb
Host smart-3d688d8b-3b16-442e-9779-e14ef91e0726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414849237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1414849237
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1097504166
Short name T273
Test name
Test status
Simulation time 189423719 ps
CPU time 1.15 seconds
Started Aug 07 06:58:35 PM PDT 24
Finished Aug 07 06:58:36 PM PDT 24
Peak memory 218184 kb
Host smart-61511dfd-a555-4ce7-9ed8-67415596ab9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097504166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1097504166
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.1858241581
Short name T683
Test name
Test status
Simulation time 86892213 ps
CPU time 1.13 seconds
Started Aug 07 06:58:35 PM PDT 24
Finished Aug 07 06:58:37 PM PDT 24
Peak memory 218608 kb
Host smart-1646f170-24c0-47d3-ac85-754b4eae22fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858241581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1858241581
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3427696058
Short name T960
Test name
Test status
Simulation time 44560994 ps
CPU time 1.16 seconds
Started Aug 07 06:58:32 PM PDT 24
Finished Aug 07 06:58:33 PM PDT 24
Peak memory 219564 kb
Host smart-ba20d790-211d-43a9-88c7-9b6a5e3a4577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427696058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3427696058
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3950151285
Short name T882
Test name
Test status
Simulation time 248051542 ps
CPU time 1.14 seconds
Started Aug 07 06:58:32 PM PDT 24
Finished Aug 07 06:58:34 PM PDT 24
Peak memory 216940 kb
Host smart-d089656c-065d-4342-ac8d-bab64acb525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950151285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3950151285
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3862705802
Short name T217
Test name
Test status
Simulation time 34282908 ps
CPU time 1.16 seconds
Started Aug 07 06:58:33 PM PDT 24
Finished Aug 07 06:58:34 PM PDT 24
Peak memory 218288 kb
Host smart-41b911b2-e7b1-4c32-b42e-1bac45ff48d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862705802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3862705802
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.3880333887
Short name T52
Test name
Test status
Simulation time 189276556 ps
CPU time 1.17 seconds
Started Aug 07 06:58:33 PM PDT 24
Finished Aug 07 06:58:34 PM PDT 24
Peak memory 216996 kb
Host smart-48684adf-d5b1-4668-bcad-82b03a22dcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880333887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3880333887
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.224580613
Short name T471
Test name
Test status
Simulation time 297402913 ps
CPU time 1.18 seconds
Started Aug 07 06:58:34 PM PDT 24
Finished Aug 07 06:58:36 PM PDT 24
Peak memory 219484 kb
Host smart-3caf4ba5-452f-4654-9825-ce69447d135e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224580613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.224580613
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert.2203277866
Short name T807
Test name
Test status
Simulation time 25912781 ps
CPU time 1.23 seconds
Started Aug 07 06:55:56 PM PDT 24
Finished Aug 07 06:55:57 PM PDT 24
Peak memory 218180 kb
Host smart-b146d395-b25f-45aa-8600-65ed05cec897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203277866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2203277866
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1548682713
Short name T958
Test name
Test status
Simulation time 45728924 ps
CPU time 0.9 seconds
Started Aug 07 06:55:57 PM PDT 24
Finished Aug 07 06:55:58 PM PDT 24
Peak memory 214768 kb
Host smart-fd10087f-acab-4e1a-8167-3c93b4b1d9b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548682713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1548682713
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2854327237
Short name T506
Test name
Test status
Simulation time 37155924 ps
CPU time 0.82 seconds
Started Aug 07 06:55:54 PM PDT 24
Finished Aug 07 06:55:55 PM PDT 24
Peak memory 218556 kb
Host smart-7d275e93-428e-42f2-805a-3d9091911041
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854327237 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2854327237
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1349123265
Short name T58
Test name
Test status
Simulation time 99204055 ps
CPU time 1.26 seconds
Started Aug 07 06:55:56 PM PDT 24
Finished Aug 07 06:55:58 PM PDT 24
Peak memory 216824 kb
Host smart-54541be7-662b-4183-9148-91d46e5fd98f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349123265 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1349123265
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2616666632
Short name T829
Test name
Test status
Simulation time 18369413 ps
CPU time 1.03 seconds
Started Aug 07 06:55:55 PM PDT 24
Finished Aug 07 06:55:56 PM PDT 24
Peak memory 218352 kb
Host smart-0b935ca0-8fd3-4746-a6f7-66582965393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616666632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2616666632
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2637680279
Short name T714
Test name
Test status
Simulation time 49132849 ps
CPU time 1.65 seconds
Started Aug 07 06:55:56 PM PDT 24
Finished Aug 07 06:55:58 PM PDT 24
Peak memory 219152 kb
Host smart-8f69b160-c85b-47ea-9955-fedef03f2fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637680279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2637680279
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.4015395192
Short name T96
Test name
Test status
Simulation time 21744939 ps
CPU time 1.05 seconds
Started Aug 07 06:55:55 PM PDT 24
Finished Aug 07 06:55:56 PM PDT 24
Peak memory 215760 kb
Host smart-d6b60b2a-04df-42a0-8aab-e1cae4affe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015395192 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.4015395192
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1647690115
Short name T509
Test name
Test status
Simulation time 51313918 ps
CPU time 0.92 seconds
Started Aug 07 06:55:59 PM PDT 24
Finished Aug 07 06:56:00 PM PDT 24
Peak memory 214948 kb
Host smart-d0ecaadc-1b26-4706-98b2-a97f1a812fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647690115 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1647690115
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2471369148
Short name T388
Test name
Test status
Simulation time 484626898 ps
CPU time 5.5 seconds
Started Aug 07 06:56:00 PM PDT 24
Finished Aug 07 06:56:06 PM PDT 24
Peak memory 218292 kb
Host smart-75fea4f9-fffa-44a0-a036-fbe2a45c4510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471369148 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2471369148
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3757478804
Short name T222
Test name
Test status
Simulation time 115268179803 ps
CPU time 1501.54 seconds
Started Aug 07 06:55:55 PM PDT 24
Finished Aug 07 07:20:56 PM PDT 24
Peak memory 226400 kb
Host smart-8b74fede-086d-471a-ae0f-ac12e8f79013
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757478804 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3757478804
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.4152019929
Short name T684
Test name
Test status
Simulation time 43792688 ps
CPU time 1.21 seconds
Started Aug 07 06:58:41 PM PDT 24
Finished Aug 07 06:58:42 PM PDT 24
Peak memory 215336 kb
Host smart-7066556f-53e9-4de6-95d3-a12870209555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152019929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.4152019929
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.2938239293
Short name T82
Test name
Test status
Simulation time 42801191 ps
CPU time 1.12 seconds
Started Aug 07 06:58:33 PM PDT 24
Finished Aug 07 06:58:34 PM PDT 24
Peak memory 219184 kb
Host smart-f70d0664-ac89-4741-acf4-5504f90627b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938239293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2938239293
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1157506693
Short name T737
Test name
Test status
Simulation time 22757016 ps
CPU time 1.19 seconds
Started Aug 07 06:58:41 PM PDT 24
Finished Aug 07 06:58:42 PM PDT 24
Peak memory 219456 kb
Host smart-6b07eb8b-d742-4ce3-93be-537f4f70161a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157506693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1157506693
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2779704375
Short name T679
Test name
Test status
Simulation time 48034082 ps
CPU time 1.76 seconds
Started Aug 07 06:58:40 PM PDT 24
Finished Aug 07 06:58:42 PM PDT 24
Peak memory 216976 kb
Host smart-edc74b92-6bc9-4732-ad00-7ee6076d8e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779704375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2779704375
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2803661760
Short name T693
Test name
Test status
Simulation time 142088820 ps
CPU time 1.22 seconds
Started Aug 07 06:58:38 PM PDT 24
Finished Aug 07 06:58:39 PM PDT 24
Peak memory 218476 kb
Host smart-d99a205a-f2d8-458b-a2bc-2c32d509f4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803661760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2803661760
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.421912494
Short name T83
Test name
Test status
Simulation time 25175566 ps
CPU time 1.18 seconds
Started Aug 07 06:58:40 PM PDT 24
Finished Aug 07 06:58:41 PM PDT 24
Peak memory 218240 kb
Host smart-28ba467d-b304-4cf1-8686-e8c4e0426e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421912494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.421912494
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.754256932
Short name T311
Test name
Test status
Simulation time 70555548 ps
CPU time 1.27 seconds
Started Aug 07 06:58:38 PM PDT 24
Finished Aug 07 06:58:39 PM PDT 24
Peak memory 218480 kb
Host smart-39923d0a-b3c7-4afd-b1f0-b2ab0274ab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754256932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.754256932
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.971882031
Short name T893
Test name
Test status
Simulation time 23026970 ps
CPU time 1.17 seconds
Started Aug 07 06:58:38 PM PDT 24
Finished Aug 07 06:58:39 PM PDT 24
Peak memory 219380 kb
Host smart-d0b1ccd3-da0b-458c-9855-8faf4ab2deab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971882031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.971882031
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/165.edn_alert.662218672
Short name T161
Test name
Test status
Simulation time 74114563 ps
CPU time 1.12 seconds
Started Aug 07 06:58:39 PM PDT 24
Finished Aug 07 06:58:40 PM PDT 24
Peak memory 219444 kb
Host smart-5ba14d73-e3d6-40e4-91e2-fb143ff627a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662218672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.662218672
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1473315509
Short name T936
Test name
Test status
Simulation time 39746163 ps
CPU time 1.58 seconds
Started Aug 07 06:58:39 PM PDT 24
Finished Aug 07 06:58:41 PM PDT 24
Peak memory 216892 kb
Host smart-94c0dd7f-fc95-411e-8139-8bb634ebba77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473315509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1473315509
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.2609332893
Short name T548
Test name
Test status
Simulation time 58638630 ps
CPU time 1.12 seconds
Started Aug 07 06:58:42 PM PDT 24
Finished Aug 07 06:58:43 PM PDT 24
Peak memory 218116 kb
Host smart-b09561b1-de94-44e3-9fe0-7324db8e6e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609332893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2609332893
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.914974391
Short name T556
Test name
Test status
Simulation time 48130729 ps
CPU time 1.18 seconds
Started Aug 07 06:58:46 PM PDT 24
Finished Aug 07 06:58:47 PM PDT 24
Peak memory 216964 kb
Host smart-6b0bcf30-166c-42fb-83a0-ff6312b4fabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914974391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.914974391
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.4053137513
Short name T143
Test name
Test status
Simulation time 137707113 ps
CPU time 1.21 seconds
Started Aug 07 06:58:41 PM PDT 24
Finished Aug 07 06:58:43 PM PDT 24
Peak memory 215384 kb
Host smart-abae477a-c7e5-4d7d-ac3d-bdbdd679b537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053137513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.4053137513
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1505270208
Short name T422
Test name
Test status
Simulation time 37853856 ps
CPU time 1.36 seconds
Started Aug 07 06:58:44 PM PDT 24
Finished Aug 07 06:58:45 PM PDT 24
Peak memory 219524 kb
Host smart-d3d3a9be-60cb-430f-9b54-383e05feb213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505270208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1505270208
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.3026842002
Short name T118
Test name
Test status
Simulation time 31658327 ps
CPU time 1.21 seconds
Started Aug 07 06:58:46 PM PDT 24
Finished Aug 07 06:58:47 PM PDT 24
Peak memory 219328 kb
Host smart-054a437c-64f4-4365-91a9-6635172dc13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026842002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3026842002
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert.1389163700
Short name T937
Test name
Test status
Simulation time 92963497 ps
CPU time 1.25 seconds
Started Aug 07 06:55:56 PM PDT 24
Finished Aug 07 06:55:58 PM PDT 24
Peak memory 219312 kb
Host smart-a45a6b27-73cc-4f9b-b5c2-11db8f1c2af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389163700 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1389163700
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.676161166
Short name T645
Test name
Test status
Simulation time 22811194 ps
CPU time 0.84 seconds
Started Aug 07 06:55:55 PM PDT 24
Finished Aug 07 06:55:56 PM PDT 24
Peak memory 206380 kb
Host smart-0e2e4e42-29bd-4d1e-b5b0-6902573f899b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676161166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.676161166
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1146272573
Short name T869
Test name
Test status
Simulation time 28253865 ps
CPU time 0.85 seconds
Started Aug 07 06:55:55 PM PDT 24
Finished Aug 07 06:55:56 PM PDT 24
Peak memory 215144 kb
Host smart-f986fd7d-98a0-4bf9-bbd4-775a770ac632
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146272573 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1146272573
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.3880035970
Short name T54
Test name
Test status
Simulation time 100717819 ps
CPU time 1.13 seconds
Started Aug 07 06:55:56 PM PDT 24
Finished Aug 07 06:55:58 PM PDT 24
Peak memory 219800 kb
Host smart-648067ef-a697-46e9-81c2-2c567f53b9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880035970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3880035970
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3486208109
Short name T326
Test name
Test status
Simulation time 122797001 ps
CPU time 1.31 seconds
Started Aug 07 06:55:56 PM PDT 24
Finished Aug 07 06:55:57 PM PDT 24
Peak memory 217276 kb
Host smart-fe9509b9-a6bc-4cb6-a9b7-2b1a5cb00e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486208109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3486208109
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3758991693
Short name T626
Test name
Test status
Simulation time 37089018 ps
CPU time 0.91 seconds
Started Aug 07 06:55:56 PM PDT 24
Finished Aug 07 06:55:58 PM PDT 24
Peak memory 214900 kb
Host smart-200348e0-5584-43ac-ba3b-1d5d3f57d7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758991693 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3758991693
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1859718020
Short name T375
Test name
Test status
Simulation time 18226453 ps
CPU time 1.03 seconds
Started Aug 07 06:55:59 PM PDT 24
Finished Aug 07 06:56:00 PM PDT 24
Peak memory 215024 kb
Host smart-e1cdfd25-848e-468c-b6f1-4cf183d5283b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859718020 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1859718020
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2827817665
Short name T899
Test name
Test status
Simulation time 2409485651 ps
CPU time 3.67 seconds
Started Aug 07 06:55:58 PM PDT 24
Finished Aug 07 06:56:02 PM PDT 24
Peak memory 215040 kb
Host smart-72e26d56-ffe1-4567-b70b-a4c2632bb867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827817665 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2827817665
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1546236244
Short name T974
Test name
Test status
Simulation time 101292176113 ps
CPU time 1304.82 seconds
Started Aug 07 06:55:57 PM PDT 24
Finished Aug 07 07:17:42 PM PDT 24
Peak memory 223328 kb
Host smart-93710868-ff61-4024-8b2a-8eb1340a618b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546236244 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1546236244
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.3459516182
Short name T503
Test name
Test status
Simulation time 27808817 ps
CPU time 1.18 seconds
Started Aug 07 06:58:46 PM PDT 24
Finished Aug 07 06:58:47 PM PDT 24
Peak memory 218176 kb
Host smart-2cdc2f23-f77f-443d-b029-cac15f39eb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459516182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3459516182
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.3920164260
Short name T514
Test name
Test status
Simulation time 32846216 ps
CPU time 1.37 seconds
Started Aug 07 06:58:44 PM PDT 24
Finished Aug 07 06:58:45 PM PDT 24
Peak memory 218408 kb
Host smart-0ad14b93-7066-47ed-bd69-7d7b7da6b19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920164260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3920164260
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1311364655
Short name T127
Test name
Test status
Simulation time 71356912 ps
CPU time 1.18 seconds
Started Aug 07 06:58:48 PM PDT 24
Finished Aug 07 06:58:50 PM PDT 24
Peak memory 218440 kb
Host smart-bc032f92-dfea-4181-8e8a-808847f0c100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311364655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1311364655
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/172.edn_alert.2019361023
Short name T903
Test name
Test status
Simulation time 24384403 ps
CPU time 1.19 seconds
Started Aug 07 06:58:50 PM PDT 24
Finished Aug 07 06:58:52 PM PDT 24
Peak memory 218372 kb
Host smart-1a891c81-1dab-40e1-a140-a8e311999239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019361023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2019361023
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.2501825060
Short name T931
Test name
Test status
Simulation time 82966206 ps
CPU time 1.02 seconds
Started Aug 07 06:58:48 PM PDT 24
Finished Aug 07 06:58:49 PM PDT 24
Peak memory 216944 kb
Host smart-1aaef067-0c31-463e-86bf-367ffb04c23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501825060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2501825060
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3277372867
Short name T879
Test name
Test status
Simulation time 42562846 ps
CPU time 1.13 seconds
Started Aug 07 06:58:48 PM PDT 24
Finished Aug 07 06:58:50 PM PDT 24
Peak memory 220416 kb
Host smart-b09b16f7-733f-403a-a3ad-bc3fcd702ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277372867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3277372867
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1384076451
Short name T753
Test name
Test status
Simulation time 40315663 ps
CPU time 1.45 seconds
Started Aug 07 06:58:48 PM PDT 24
Finished Aug 07 06:58:49 PM PDT 24
Peak memory 219484 kb
Host smart-9376c0d7-14ae-4cc2-9977-b62815dfba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384076451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1384076451
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.1334816312
Short name T729
Test name
Test status
Simulation time 52863544 ps
CPU time 1.22 seconds
Started Aug 07 06:58:51 PM PDT 24
Finished Aug 07 06:58:52 PM PDT 24
Peak memory 218392 kb
Host smart-d9de1dfd-73e0-4100-8123-56e28ace4651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334816312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1334816312
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3082141677
Short name T612
Test name
Test status
Simulation time 76314395 ps
CPU time 1.18 seconds
Started Aug 07 06:58:48 PM PDT 24
Finished Aug 07 06:58:49 PM PDT 24
Peak memory 219148 kb
Host smart-9bbb8439-0645-4859-a49e-642891bb994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082141677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3082141677
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.1442516152
Short name T299
Test name
Test status
Simulation time 163912152 ps
CPU time 1.22 seconds
Started Aug 07 06:58:49 PM PDT 24
Finished Aug 07 06:58:50 PM PDT 24
Peak memory 219116 kb
Host smart-029c6a25-95d8-4746-b1c5-783e3fcd60df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442516152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1442516152
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.4118814286
Short name T964
Test name
Test status
Simulation time 52181474 ps
CPU time 1.2 seconds
Started Aug 07 06:58:50 PM PDT 24
Finished Aug 07 06:58:52 PM PDT 24
Peak memory 217124 kb
Host smart-7f76554b-21be-45ea-9683-0bc62ba945fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118814286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.4118814286
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.3439274142
Short name T144
Test name
Test status
Simulation time 28007724 ps
CPU time 1.2 seconds
Started Aug 07 06:58:52 PM PDT 24
Finished Aug 07 06:58:53 PM PDT 24
Peak memory 220476 kb
Host smart-1569dec1-2786-4afb-bae3-602963a7bc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439274142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3439274142
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/177.edn_alert.766236168
Short name T41
Test name
Test status
Simulation time 26334925 ps
CPU time 1.19 seconds
Started Aug 07 06:58:54 PM PDT 24
Finished Aug 07 06:58:55 PM PDT 24
Peak memory 219384 kb
Host smart-a5830aae-06e1-4dc3-ba23-89d8b5e0a4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766236168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.766236168
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.3880686498
Short name T848
Test name
Test status
Simulation time 249564553 ps
CPU time 3 seconds
Started Aug 07 06:58:52 PM PDT 24
Finished Aug 07 06:58:55 PM PDT 24
Peak memory 217264 kb
Host smart-69ad25c7-ca89-4d1a-aab0-106e17e2fb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880686498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3880686498
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2931587825
Short name T461
Test name
Test status
Simulation time 29088609 ps
CPU time 1.29 seconds
Started Aug 07 06:58:56 PM PDT 24
Finished Aug 07 06:58:57 PM PDT 24
Peak memory 218200 kb
Host smart-6cfcc84e-4ec2-494d-bf0d-10cc73df6eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931587825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2931587825
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/179.edn_alert.3596924054
Short name T86
Test name
Test status
Simulation time 90828612 ps
CPU time 1.17 seconds
Started Aug 07 06:58:52 PM PDT 24
Finished Aug 07 06:58:54 PM PDT 24
Peak memory 219196 kb
Host smart-45519641-53ad-467d-8eb1-05709acabc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596924054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3596924054
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.834704424
Short name T595
Test name
Test status
Simulation time 33580145 ps
CPU time 1.06 seconds
Started Aug 07 06:58:53 PM PDT 24
Finished Aug 07 06:58:54 PM PDT 24
Peak memory 218616 kb
Host smart-d8a9fb20-c8db-41ac-abea-91f4c6f864db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834704424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.834704424
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3648542022
Short name T430
Test name
Test status
Simulation time 24849342 ps
CPU time 1.18 seconds
Started Aug 07 06:55:57 PM PDT 24
Finished Aug 07 06:55:58 PM PDT 24
Peak memory 219296 kb
Host smart-5016e57b-f435-4b8c-b3de-2b293b34baad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648542022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3648542022
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.470747113
Short name T697
Test name
Test status
Simulation time 58645554 ps
CPU time 0.93 seconds
Started Aug 07 06:56:02 PM PDT 24
Finished Aug 07 06:56:03 PM PDT 24
Peak memory 206332 kb
Host smart-4d0d0f7a-9bb4-43c3-a967-ec06158bfac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470747113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.470747113
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2173973988
Short name T930
Test name
Test status
Simulation time 39785244 ps
CPU time 1.21 seconds
Started Aug 07 06:56:03 PM PDT 24
Finished Aug 07 06:56:04 PM PDT 24
Peak memory 216768 kb
Host smart-294bda33-7163-47d4-b07a-99f403efd8ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173973988 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2173973988
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2606266226
Short name T749
Test name
Test status
Simulation time 27788609 ps
CPU time 1.11 seconds
Started Aug 07 06:55:56 PM PDT 24
Finished Aug 07 06:55:58 PM PDT 24
Peak memory 223600 kb
Host smart-ce91e77b-22f0-4a0a-8484-60f317fcd533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606266226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2606266226
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2592334129
Short name T671
Test name
Test status
Simulation time 45912900 ps
CPU time 0.95 seconds
Started Aug 07 06:55:55 PM PDT 24
Finished Aug 07 06:55:56 PM PDT 24
Peak memory 216884 kb
Host smart-fac7761a-f956-47f7-9884-7ebe2c986cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592334129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2592334129
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.2567878463
Short name T497
Test name
Test status
Simulation time 17072664 ps
CPU time 1.01 seconds
Started Aug 07 06:55:55 PM PDT 24
Finished Aug 07 06:55:56 PM PDT 24
Peak memory 214896 kb
Host smart-845a9d2b-d9c2-4536-bef8-2fee3d806285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567878463 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2567878463
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3897438280
Short name T112
Test name
Test status
Simulation time 326669986 ps
CPU time 6.07 seconds
Started Aug 07 06:55:55 PM PDT 24
Finished Aug 07 06:56:01 PM PDT 24
Peak memory 216832 kb
Host smart-33fe63f4-b32f-44e3-af26-f4818e837246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897438280 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3897438280
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2478265454
Short name T485
Test name
Test status
Simulation time 100847065799 ps
CPU time 419.08 seconds
Started Aug 07 06:55:57 PM PDT 24
Finished Aug 07 07:02:56 PM PDT 24
Peak memory 223340 kb
Host smart-eaa4198a-2315-4150-8504-4a8eb7367bc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478265454 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2478265454
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1417401026
Short name T837
Test name
Test status
Simulation time 61070469 ps
CPU time 1.17 seconds
Started Aug 07 06:58:53 PM PDT 24
Finished Aug 07 06:58:55 PM PDT 24
Peak memory 218260 kb
Host smart-6e026ee7-aba5-47bc-b5f9-72d3ca9c47ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417401026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1417401026
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2768174506
Short name T694
Test name
Test status
Simulation time 20714710 ps
CPU time 1.14 seconds
Started Aug 07 06:58:52 PM PDT 24
Finished Aug 07 06:58:54 PM PDT 24
Peak memory 217320 kb
Host smart-7ae9ba7f-e487-4883-8f40-e5d00d16d9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768174506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2768174506
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.515869880
Short name T460
Test name
Test status
Simulation time 99162073 ps
CPU time 1.33 seconds
Started Aug 07 06:58:54 PM PDT 24
Finished Aug 07 06:58:55 PM PDT 24
Peak memory 220388 kb
Host smart-aa77019f-78b4-4ca8-9a02-45edb738528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515869880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.515869880
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.1543376054
Short name T449
Test name
Test status
Simulation time 24181446 ps
CPU time 1.13 seconds
Started Aug 07 06:58:56 PM PDT 24
Finished Aug 07 06:58:57 PM PDT 24
Peak memory 218764 kb
Host smart-b02d8946-36a3-4a75-8537-7aa691e0bc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543376054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1543376054
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.212996562
Short name T182
Test name
Test status
Simulation time 53266618 ps
CPU time 1.3 seconds
Started Aug 07 06:58:55 PM PDT 24
Finished Aug 07 06:58:56 PM PDT 24
Peak memory 215312 kb
Host smart-06c8d0cf-c5c3-40a8-bbff-da913717cb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212996562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.212996562
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.424128221
Short name T544
Test name
Test status
Simulation time 53559041 ps
CPU time 2.11 seconds
Started Aug 07 06:58:54 PM PDT 24
Finished Aug 07 06:58:57 PM PDT 24
Peak memory 218448 kb
Host smart-4f0e6aa4-3ad2-43b5-a035-ec88363a1a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424128221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.424128221
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1417365563
Short name T179
Test name
Test status
Simulation time 37459090 ps
CPU time 1.08 seconds
Started Aug 07 06:58:56 PM PDT 24
Finished Aug 07 06:58:57 PM PDT 24
Peak memory 219188 kb
Host smart-499500b4-6071-4e54-a909-a8fc56d23cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417365563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1417365563
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.1301977654
Short name T491
Test name
Test status
Simulation time 78894512 ps
CPU time 1.34 seconds
Started Aug 07 06:58:54 PM PDT 24
Finished Aug 07 06:58:55 PM PDT 24
Peak memory 218656 kb
Host smart-844e7016-c0ae-43f7-a8b8-54918dd1727b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301977654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1301977654
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.4113777747
Short name T3
Test name
Test status
Simulation time 36691495 ps
CPU time 1.12 seconds
Started Aug 07 06:58:57 PM PDT 24
Finished Aug 07 06:58:58 PM PDT 24
Peak memory 219236 kb
Host smart-90f573a6-a00d-44d7-ab6c-812eba2fd3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113777747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.4113777747
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.2916415000
Short name T292
Test name
Test status
Simulation time 31310911 ps
CPU time 1.18 seconds
Started Aug 07 06:59:04 PM PDT 24
Finished Aug 07 06:59:05 PM PDT 24
Peak memory 215088 kb
Host smart-60dc2a42-088d-45c5-b950-77ac527c0feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916415000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2916415000
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.1738651958
Short name T11
Test name
Test status
Simulation time 67480253 ps
CPU time 1.13 seconds
Started Aug 07 06:59:02 PM PDT 24
Finished Aug 07 06:59:04 PM PDT 24
Peak memory 218400 kb
Host smart-1c175360-dffb-4969-9a0f-2dceb97aefa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738651958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1738651958
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.641563314
Short name T963
Test name
Test status
Simulation time 68240993 ps
CPU time 1.33 seconds
Started Aug 07 06:58:58 PM PDT 24
Finished Aug 07 06:58:59 PM PDT 24
Peak memory 217988 kb
Host smart-031b7dd6-2f20-4572-b4d5-89e11f6a8b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641563314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.641563314
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.1938716632
Short name T659
Test name
Test status
Simulation time 55745779 ps
CPU time 1.3 seconds
Started Aug 07 06:58:59 PM PDT 24
Finished Aug 07 06:59:01 PM PDT 24
Peak memory 215300 kb
Host smart-02f2cb42-ce13-4d6d-8641-7d63720cf07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938716632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.1938716632
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/187.edn_alert.3626222450
Short name T181
Test name
Test status
Simulation time 36313590 ps
CPU time 1.06 seconds
Started Aug 07 06:59:02 PM PDT 24
Finished Aug 07 06:59:04 PM PDT 24
Peak memory 219208 kb
Host smart-6c0e2fd7-c40a-4d0b-b268-5da95de3b895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626222450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3626222450
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.4289241322
Short name T677
Test name
Test status
Simulation time 275574376 ps
CPU time 3.64 seconds
Started Aug 07 06:59:05 PM PDT 24
Finished Aug 07 06:59:09 PM PDT 24
Peak memory 219776 kb
Host smart-3ebb67f6-bea1-45d1-83a5-e3b63d17da09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289241322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4289241322
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1145809566
Short name T399
Test name
Test status
Simulation time 34258356 ps
CPU time 1.31 seconds
Started Aug 07 06:59:03 PM PDT 24
Finished Aug 07 06:59:05 PM PDT 24
Peak memory 216928 kb
Host smart-287992de-360b-4cb9-8105-e02c997a140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145809566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1145809566
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.943167727
Short name T541
Test name
Test status
Simulation time 92111382 ps
CPU time 1.17 seconds
Started Aug 07 06:59:04 PM PDT 24
Finished Aug 07 06:59:05 PM PDT 24
Peak memory 218216 kb
Host smart-b5767b61-14e0-4a94-9f90-a9fb5bbe45c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943167727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.943167727
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert.1092795744
Short name T142
Test name
Test status
Simulation time 26551419 ps
CPU time 1.24 seconds
Started Aug 07 06:56:04 PM PDT 24
Finished Aug 07 06:56:06 PM PDT 24
Peak memory 220364 kb
Host smart-426684f9-2a9d-401c-a292-5ada5753d077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092795744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1092795744
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3046550947
Short name T651
Test name
Test status
Simulation time 36892321 ps
CPU time 1.02 seconds
Started Aug 07 06:56:05 PM PDT 24
Finished Aug 07 06:56:06 PM PDT 24
Peak memory 206352 kb
Host smart-d6e686d1-ad26-4075-a850-a121bd6d9dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046550947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3046550947
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1226642991
Short name T680
Test name
Test status
Simulation time 27117623 ps
CPU time 1.1 seconds
Started Aug 07 06:56:04 PM PDT 24
Finished Aug 07 06:56:06 PM PDT 24
Peak memory 219200 kb
Host smart-c42d009d-5c9c-48f6-abf2-d4bac279985f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226642991 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1226642991
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2706850820
Short name T949
Test name
Test status
Simulation time 24516155 ps
CPU time 0.95 seconds
Started Aug 07 06:56:06 PM PDT 24
Finished Aug 07 06:56:07 PM PDT 24
Peak memory 218476 kb
Host smart-b9c7c79b-8012-43d9-94b2-6a39b3f65db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706850820 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2706850820
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.4131927597
Short name T980
Test name
Test status
Simulation time 32668760 ps
CPU time 1.33 seconds
Started Aug 07 06:56:00 PM PDT 24
Finished Aug 07 06:56:01 PM PDT 24
Peak memory 217012 kb
Host smart-386c8e67-2244-4d94-9356-e18e90e8f165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131927597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4131927597
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2589562938
Short name T571
Test name
Test status
Simulation time 68507481 ps
CPU time 0.92 seconds
Started Aug 07 06:56:01 PM PDT 24
Finished Aug 07 06:56:02 PM PDT 24
Peak memory 223704 kb
Host smart-01a12275-17c6-4991-aa73-11dcc72f7604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589562938 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2589562938
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3700627715
Short name T698
Test name
Test status
Simulation time 18579299 ps
CPU time 0.98 seconds
Started Aug 07 06:56:00 PM PDT 24
Finished Aug 07 06:56:01 PM PDT 24
Peak memory 214900 kb
Host smart-29d620c9-5416-4c64-ab7c-9706c7dcf839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700627715 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3700627715
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3720025557
Short name T709
Test name
Test status
Simulation time 390680404 ps
CPU time 4.04 seconds
Started Aug 07 06:56:06 PM PDT 24
Finished Aug 07 06:56:10 PM PDT 24
Peak memory 217020 kb
Host smart-f9bde856-daf7-4671-8011-40fbecbbac28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720025557 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3720025557
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3602713937
Short name T855
Test name
Test status
Simulation time 185822143487 ps
CPU time 736.3 seconds
Started Aug 07 06:56:00 PM PDT 24
Finished Aug 07 07:08:16 PM PDT 24
Peak memory 219900 kb
Host smart-4a76cba6-a1c0-49c5-bee0-a92e763e81b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602713937 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3602713937
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3304896675
Short name T505
Test name
Test status
Simulation time 24529505 ps
CPU time 1.24 seconds
Started Aug 07 06:59:02 PM PDT 24
Finished Aug 07 06:59:03 PM PDT 24
Peak memory 218376 kb
Host smart-443c8f61-9e5a-4d73-b6ed-469526e2ab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304896675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3304896675
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3552599815
Short name T513
Test name
Test status
Simulation time 316409155 ps
CPU time 1.98 seconds
Started Aug 07 06:59:02 PM PDT 24
Finished Aug 07 06:59:05 PM PDT 24
Peak memory 218688 kb
Host smart-a2d7b002-fd4c-4f1a-adf1-6ff36604223e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552599815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3552599815
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.1642199166
Short name T290
Test name
Test status
Simulation time 100060648 ps
CPU time 1.28 seconds
Started Aug 07 06:59:02 PM PDT 24
Finished Aug 07 06:59:04 PM PDT 24
Peak memory 215296 kb
Host smart-a2ec934e-e68f-4cc4-af18-1e6c30635d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642199166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1642199166
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2284392873
Short name T377
Test name
Test status
Simulation time 44471860 ps
CPU time 1.13 seconds
Started Aug 07 06:59:04 PM PDT 24
Finished Aug 07 06:59:05 PM PDT 24
Peak memory 219624 kb
Host smart-7c6e53a8-dc54-4f89-bcc0-59eac8049a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284392873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2284392873
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.4062719013
Short name T171
Test name
Test status
Simulation time 70625812 ps
CPU time 1.09 seconds
Started Aug 07 06:59:08 PM PDT 24
Finished Aug 07 06:59:10 PM PDT 24
Peak memory 219536 kb
Host smart-41807f1b-06d1-4ed2-ba6f-59dc274a707c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062719013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.4062719013
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.4246843878
Short name T238
Test name
Test status
Simulation time 31900702 ps
CPU time 1.02 seconds
Started Aug 07 06:59:11 PM PDT 24
Finished Aug 07 06:59:12 PM PDT 24
Peak memory 218408 kb
Host smart-b23abe1e-e845-4aef-9c31-9c9454224d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246843878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4246843878
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2524785328
Short name T707
Test name
Test status
Simulation time 130189096 ps
CPU time 1.2 seconds
Started Aug 07 06:59:08 PM PDT 24
Finished Aug 07 06:59:10 PM PDT 24
Peak memory 218740 kb
Host smart-17cf27c3-f481-4902-b737-0c5496f0e1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524785328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2524785328
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2152385034
Short name T462
Test name
Test status
Simulation time 30453198 ps
CPU time 1.28 seconds
Started Aug 07 06:59:12 PM PDT 24
Finished Aug 07 06:59:13 PM PDT 24
Peak memory 218312 kb
Host smart-c66e59ee-47fd-420c-ab94-cc578d08318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152385034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2152385034
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.3232744302
Short name T296
Test name
Test status
Simulation time 24003304 ps
CPU time 1.19 seconds
Started Aug 07 06:59:08 PM PDT 24
Finished Aug 07 06:59:10 PM PDT 24
Peak memory 219284 kb
Host smart-a9e23776-e910-48e5-94f4-a84e12b556c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232744302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3232744302
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.175218578
Short name T702
Test name
Test status
Simulation time 31554993 ps
CPU time 1.49 seconds
Started Aug 07 06:59:08 PM PDT 24
Finished Aug 07 06:59:10 PM PDT 24
Peak memory 218072 kb
Host smart-a5dfdaef-c824-42ba-b519-879ecaa65824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175218578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.175218578
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2198804957
Short name T189
Test name
Test status
Simulation time 46733116 ps
CPU time 1.19 seconds
Started Aug 07 06:59:07 PM PDT 24
Finished Aug 07 06:59:09 PM PDT 24
Peak memory 219532 kb
Host smart-d5bc9663-578e-4b24-b857-c75b0022da49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198804957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2198804957
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.567919337
Short name T27
Test name
Test status
Simulation time 220339767 ps
CPU time 1.2 seconds
Started Aug 07 06:59:07 PM PDT 24
Finished Aug 07 06:59:08 PM PDT 24
Peak memory 217084 kb
Host smart-7faeb33c-cf22-45a1-a5fb-a2b4f4181765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567919337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.567919337
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1062036549
Short name T716
Test name
Test status
Simulation time 75258530 ps
CPU time 1.07 seconds
Started Aug 07 06:59:09 PM PDT 24
Finished Aug 07 06:59:11 PM PDT 24
Peak memory 220420 kb
Host smart-3e45affd-f7e3-48d4-9615-1489ea3f00c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062036549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1062036549
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2393050700
Short name T376
Test name
Test status
Simulation time 89747593 ps
CPU time 3.03 seconds
Started Aug 07 06:59:10 PM PDT 24
Finished Aug 07 06:59:14 PM PDT 24
Peak memory 218604 kb
Host smart-29b44815-bd9c-42d6-b087-d695c48c02cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393050700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2393050700
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.4236782246
Short name T367
Test name
Test status
Simulation time 30032098 ps
CPU time 1.3 seconds
Started Aug 07 06:59:12 PM PDT 24
Finished Aug 07 06:59:13 PM PDT 24
Peak memory 220236 kb
Host smart-eca150fb-34b4-45e9-a5a5-4bb24a2e5e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236782246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.4236782246
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3948763517
Short name T396
Test name
Test status
Simulation time 119473315 ps
CPU time 2.48 seconds
Started Aug 07 06:59:10 PM PDT 24
Finished Aug 07 06:59:12 PM PDT 24
Peak memory 219712 kb
Host smart-7ea618ef-938e-426e-b824-79a717f494a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948763517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3948763517
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.819121625
Short name T378
Test name
Test status
Simulation time 25496410 ps
CPU time 1.24 seconds
Started Aug 07 06:59:21 PM PDT 24
Finished Aug 07 06:59:23 PM PDT 24
Peak memory 220432 kb
Host smart-a88bb7b0-60c8-4164-8d95-7b3f97922838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819121625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.819121625
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.4292873432
Short name T334
Test name
Test status
Simulation time 33088893 ps
CPU time 1.07 seconds
Started Aug 07 06:59:30 PM PDT 24
Finished Aug 07 06:59:31 PM PDT 24
Peak memory 216988 kb
Host smart-36b4610b-2564-41d7-9a1b-1c7ab275a2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292873432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.4292873432
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2833197372
Short name T891
Test name
Test status
Simulation time 22988647 ps
CPU time 1.15 seconds
Started Aug 07 06:59:27 PM PDT 24
Finished Aug 07 06:59:28 PM PDT 24
Peak memory 220456 kb
Host smart-aaa49910-c267-486f-b98b-2d87b1e5c0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833197372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2833197372
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.3157115234
Short name T722
Test name
Test status
Simulation time 98002222 ps
CPU time 1.58 seconds
Started Aug 07 06:59:25 PM PDT 24
Finished Aug 07 06:59:27 PM PDT 24
Peak memory 218208 kb
Host smart-c96d8662-b7c4-4ff3-bb75-d39ab61c3b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157115234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3157115234
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1141063028
Short name T530
Test name
Test status
Simulation time 47042722 ps
CPU time 1.15 seconds
Started Aug 07 06:55:22 PM PDT 24
Finished Aug 07 06:55:23 PM PDT 24
Peak memory 218212 kb
Host smart-21041949-2a6c-4fe7-9707-8455edb9004e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141063028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1141063028
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.80640560
Short name T875
Test name
Test status
Simulation time 16973703 ps
CPU time 1 seconds
Started Aug 07 06:55:22 PM PDT 24
Finished Aug 07 06:55:23 PM PDT 24
Peak memory 214784 kb
Host smart-71259576-b3bc-409c-b814-c911c4cf1362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80640560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.80640560
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1354421552
Short name T163
Test name
Test status
Simulation time 42305742 ps
CPU time 0.84 seconds
Started Aug 07 06:55:25 PM PDT 24
Finished Aug 07 06:55:26 PM PDT 24
Peak memory 216248 kb
Host smart-e035574c-b710-4047-9008-3a49f3fa6ed9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354421552 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1354421552
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1242434320
Short name T925
Test name
Test status
Simulation time 62206887 ps
CPU time 0.99 seconds
Started Aug 07 06:55:27 PM PDT 24
Finished Aug 07 06:55:28 PM PDT 24
Peak memory 216744 kb
Host smart-b2422963-01f1-4e6d-861f-f1af2052afb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242434320 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1242434320
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3239354380
Short name T967
Test name
Test status
Simulation time 73568550 ps
CPU time 1.2 seconds
Started Aug 07 06:55:22 PM PDT 24
Finished Aug 07 06:55:24 PM PDT 24
Peak memory 225284 kb
Host smart-28ec1710-0c1b-40b7-80c6-c68c0f627405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239354380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3239354380
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1499384101
Short name T681
Test name
Test status
Simulation time 61025687 ps
CPU time 1.24 seconds
Started Aug 07 06:55:23 PM PDT 24
Finished Aug 07 06:55:24 PM PDT 24
Peak memory 216940 kb
Host smart-2b22dd10-16c1-4fa5-bc85-4b1c79f3dfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499384101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1499384101
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3725940519
Short name T101
Test name
Test status
Simulation time 28326568 ps
CPU time 0.89 seconds
Started Aug 07 06:55:24 PM PDT 24
Finished Aug 07 06:55:25 PM PDT 24
Peak memory 215392 kb
Host smart-16598adc-f276-4a99-a064-e50d9303db68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725940519 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3725940519
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2339953613
Short name T94
Test name
Test status
Simulation time 23113266 ps
CPU time 0.92 seconds
Started Aug 07 06:55:21 PM PDT 24
Finished Aug 07 06:55:22 PM PDT 24
Peak memory 206724 kb
Host smart-0806e065-ec63-434a-92f3-86b764890e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339953613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2339953613
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.2322956500
Short name T733
Test name
Test status
Simulation time 42252284 ps
CPU time 0.89 seconds
Started Aug 07 06:55:25 PM PDT 24
Finished Aug 07 06:55:26 PM PDT 24
Peak memory 214916 kb
Host smart-a6ef0ec1-090a-4949-875c-6b824d66b03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322956500 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2322956500
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.506548055
Short name T406
Test name
Test status
Simulation time 220684488 ps
CPU time 4.55 seconds
Started Aug 07 06:55:24 PM PDT 24
Finished Aug 07 06:55:29 PM PDT 24
Peak memory 218280 kb
Host smart-45f272fa-7ea7-4b7e-9fe5-a7421a86453f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506548055 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.506548055
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.435976953
Short name T228
Test name
Test status
Simulation time 23753300578 ps
CPU time 526.81 seconds
Started Aug 07 06:55:23 PM PDT 24
Finished Aug 07 07:04:10 PM PDT 24
Peak memory 218288 kb
Host smart-6a727311-91ce-4e51-a63d-8025f756e374
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435976953 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.435976953
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2241768679
Short name T821
Test name
Test status
Simulation time 43539127 ps
CPU time 1.38 seconds
Started Aug 07 06:56:01 PM PDT 24
Finished Aug 07 06:56:02 PM PDT 24
Peak memory 219612 kb
Host smart-10b63f52-d505-4ad5-a651-ab60031784b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241768679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2241768679
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.812820163
Short name T551
Test name
Test status
Simulation time 18668447 ps
CPU time 0.81 seconds
Started Aug 07 06:56:00 PM PDT 24
Finished Aug 07 06:56:01 PM PDT 24
Peak memory 206380 kb
Host smart-fdeda3cc-67f8-4d3f-a5bb-e7534251863e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812820163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.812820163
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.816689008
Short name T158
Test name
Test status
Simulation time 32616963 ps
CPU time 0.82 seconds
Started Aug 07 06:56:04 PM PDT 24
Finished Aug 07 06:56:06 PM PDT 24
Peak memory 215148 kb
Host smart-77fb5577-0055-401b-bb7e-857ccbf2c371
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816689008 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.816689008
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.763594707
Short name T214
Test name
Test status
Simulation time 144302964 ps
CPU time 1.23 seconds
Started Aug 07 06:56:01 PM PDT 24
Finished Aug 07 06:56:02 PM PDT 24
Peak memory 216692 kb
Host smart-43cdfacd-2688-46e1-937f-a4ed0de243f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763594707 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.763594707
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_genbits.1594981818
Short name T345
Test name
Test status
Simulation time 81680789 ps
CPU time 1.24 seconds
Started Aug 07 06:56:01 PM PDT 24
Finished Aug 07 06:56:02 PM PDT 24
Peak memory 217120 kb
Host smart-25b40333-69af-44d0-b069-7ac97e6dc439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594981818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1594981818
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1867998121
Short name T357
Test name
Test status
Simulation time 37446920 ps
CPU time 0.87 seconds
Started Aug 07 06:56:01 PM PDT 24
Finished Aug 07 06:56:02 PM PDT 24
Peak memory 215132 kb
Host smart-577a7e56-5cb2-462b-8619-28bca717ad80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867998121 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1867998121
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.297566564
Short name T533
Test name
Test status
Simulation time 49039553 ps
CPU time 0.96 seconds
Started Aug 07 06:56:00 PM PDT 24
Finished Aug 07 06:56:01 PM PDT 24
Peak memory 214932 kb
Host smart-04770967-516b-42b9-9b6a-0efa69230fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297566564 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.297566564
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1617738681
Short name T363
Test name
Test status
Simulation time 279287957 ps
CPU time 5.75 seconds
Started Aug 07 06:56:02 PM PDT 24
Finished Aug 07 06:56:08 PM PDT 24
Peak memory 218152 kb
Host smart-7c10d63f-88e3-4c7f-a815-60581e5bd09c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617738681 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1617738681
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.4261535399
Short name T782
Test name
Test status
Simulation time 72037607742 ps
CPU time 955.9 seconds
Started Aug 07 06:56:01 PM PDT 24
Finished Aug 07 07:11:57 PM PDT 24
Peak memory 222396 kb
Host smart-462a829d-a69c-4e14-b51a-8242d5f91471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261535399 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.4261535399
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.989778133
Short name T36
Test name
Test status
Simulation time 91230543 ps
CPU time 1.61 seconds
Started Aug 07 06:59:21 PM PDT 24
Finished Aug 07 06:59:23 PM PDT 24
Peak memory 218500 kb
Host smart-10a8dde8-d1b6-4aae-8f36-33cbe0ac41b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989778133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.989778133
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2148410716
Short name T723
Test name
Test status
Simulation time 93492277 ps
CPU time 1.21 seconds
Started Aug 07 06:59:25 PM PDT 24
Finished Aug 07 06:59:27 PM PDT 24
Peak memory 219580 kb
Host smart-2f9b98d0-8beb-4f45-a240-ccd45caa3eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148410716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2148410716
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.21876141
Short name T920
Test name
Test status
Simulation time 95114198 ps
CPU time 1.16 seconds
Started Aug 07 06:59:28 PM PDT 24
Finished Aug 07 06:59:30 PM PDT 24
Peak memory 217112 kb
Host smart-c9335e42-2b77-4776-8bf2-934a256f3e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21876141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.21876141
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1651729100
Short name T307
Test name
Test status
Simulation time 30471533 ps
CPU time 1.28 seconds
Started Aug 07 06:59:19 PM PDT 24
Finished Aug 07 06:59:20 PM PDT 24
Peak memory 218160 kb
Host smart-d218188d-e9b6-4aba-ac55-c73f78ccf18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651729100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1651729100
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.281423268
Short name T759
Test name
Test status
Simulation time 91731037 ps
CPU time 1.13 seconds
Started Aug 07 06:59:21 PM PDT 24
Finished Aug 07 06:59:22 PM PDT 24
Peak memory 218576 kb
Host smart-e370b6f7-8080-43d3-97cb-4ccf9ce0e925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281423268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.281423268
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3704263049
Short name T434
Test name
Test status
Simulation time 48154035 ps
CPU time 1.5 seconds
Started Aug 07 06:59:27 PM PDT 24
Finished Aug 07 06:59:29 PM PDT 24
Peak memory 218068 kb
Host smart-45d5b1e2-6e4b-4087-b3e3-f9946f080f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704263049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3704263049
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2248735550
Short name T892
Test name
Test status
Simulation time 44441639 ps
CPU time 1.01 seconds
Started Aug 07 06:59:18 PM PDT 24
Finished Aug 07 06:59:20 PM PDT 24
Peak memory 217016 kb
Host smart-550af1d0-fbdf-42d1-8298-1ee1a8212ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248735550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2248735550
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.4181626941
Short name T313
Test name
Test status
Simulation time 72999178 ps
CPU time 2.48 seconds
Started Aug 07 06:59:26 PM PDT 24
Finished Aug 07 06:59:29 PM PDT 24
Peak memory 219860 kb
Host smart-af783ca6-bb4b-4a3f-9e64-fff31942d983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181626941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.4181626941
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.789783242
Short name T598
Test name
Test status
Simulation time 42889180 ps
CPU time 1.44 seconds
Started Aug 07 06:59:18 PM PDT 24
Finished Aug 07 06:59:20 PM PDT 24
Peak memory 216896 kb
Host smart-2d46c5e1-bb82-4e87-8351-ed7b5d5f26e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789783242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.789783242
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2932861313
Short name T84
Test name
Test status
Simulation time 65671505 ps
CPU time 1.02 seconds
Started Aug 07 06:59:19 PM PDT 24
Finished Aug 07 06:59:20 PM PDT 24
Peak memory 217036 kb
Host smart-e8d21192-123a-43f6-916b-50682e2f45bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932861313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2932861313
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.397106914
Short name T857
Test name
Test status
Simulation time 83293690 ps
CPU time 1.19 seconds
Started Aug 07 06:56:08 PM PDT 24
Finished Aug 07 06:56:09 PM PDT 24
Peak memory 218600 kb
Host smart-eeba5595-9641-43f1-bf07-90de128b0b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397106914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.397106914
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1806827135
Short name T428
Test name
Test status
Simulation time 23555027 ps
CPU time 0.84 seconds
Started Aug 07 06:56:05 PM PDT 24
Finished Aug 07 06:56:06 PM PDT 24
Peak memory 206524 kb
Host smart-7e5c3972-43f2-4537-bab6-fd09ec7fc0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806827135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1806827135
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3612984755
Short name T439
Test name
Test status
Simulation time 12426052 ps
CPU time 0.91 seconds
Started Aug 07 06:56:08 PM PDT 24
Finished Aug 07 06:56:09 PM PDT 24
Peak memory 216028 kb
Host smart-bf3fd2f6-f73e-4724-a14b-a736d5858324
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612984755 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3612984755
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2516190127
Short name T590
Test name
Test status
Simulation time 122803739 ps
CPU time 1.1 seconds
Started Aug 07 06:56:09 PM PDT 24
Finished Aug 07 06:56:10 PM PDT 24
Peak memory 216892 kb
Host smart-9627a582-03a3-46ad-b706-03b07339257e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516190127 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2516190127
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.729124093
Short name T627
Test name
Test status
Simulation time 31619047 ps
CPU time 0.9 seconds
Started Aug 07 06:56:07 PM PDT 24
Finished Aug 07 06:56:08 PM PDT 24
Peak memory 218072 kb
Host smart-befe781a-4ac1-42fe-9595-721c3ce2581e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729124093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.729124093
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.18706898
Short name T331
Test name
Test status
Simulation time 50247265 ps
CPU time 1.68 seconds
Started Aug 07 06:56:05 PM PDT 24
Finished Aug 07 06:56:07 PM PDT 24
Peak memory 219584 kb
Host smart-7255a85d-6672-40fe-9ead-576c9de0c6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18706898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.18706898
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1325035879
Short name T832
Test name
Test status
Simulation time 25459787 ps
CPU time 0.96 seconds
Started Aug 07 06:56:06 PM PDT 24
Finished Aug 07 06:56:07 PM PDT 24
Peak memory 215588 kb
Host smart-ba2ca124-fd91-47ab-918e-18c565cc38c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325035879 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1325035879
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1361676256
Short name T469
Test name
Test status
Simulation time 33794041 ps
CPU time 0.89 seconds
Started Aug 07 06:56:05 PM PDT 24
Finished Aug 07 06:56:06 PM PDT 24
Peak memory 214896 kb
Host smart-1a996f83-53a9-43a2-b180-2fef2defe938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361676256 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1361676256
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3180378110
Short name T610
Test name
Test status
Simulation time 131817485 ps
CPU time 2.96 seconds
Started Aug 07 06:56:05 PM PDT 24
Finished Aug 07 06:56:08 PM PDT 24
Peak memory 216764 kb
Host smart-e53c3f08-1226-49c3-85d1-0dba31cbe4d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180378110 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3180378110
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3519317464
Short name T582
Test name
Test status
Simulation time 276925699902 ps
CPU time 1729.69 seconds
Started Aug 07 06:56:08 PM PDT 24
Finished Aug 07 07:24:58 PM PDT 24
Peak memory 226900 kb
Host smart-77cc3e99-33ab-4a18-8402-7a5dd3ef6ad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519317464 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3519317464
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.514352705
Short name T531
Test name
Test status
Simulation time 100632250 ps
CPU time 1.62 seconds
Started Aug 07 06:59:27 PM PDT 24
Finished Aug 07 06:59:29 PM PDT 24
Peak memory 218768 kb
Host smart-681b7976-a199-4171-862b-e32a2e5e8753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514352705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.514352705
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1713733613
Short name T864
Test name
Test status
Simulation time 43624430 ps
CPU time 1.29 seconds
Started Aug 07 06:59:30 PM PDT 24
Finished Aug 07 06:59:31 PM PDT 24
Peak memory 219448 kb
Host smart-6bb10461-b800-4edd-97a9-c8daf2f50b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713733613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1713733613
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1769786776
Short name T339
Test name
Test status
Simulation time 38572153 ps
CPU time 1.33 seconds
Started Aug 07 06:59:19 PM PDT 24
Finished Aug 07 06:59:20 PM PDT 24
Peak memory 218080 kb
Host smart-7483507a-8260-4126-8ba0-5a69ded27e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769786776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1769786776
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2629319230
Short name T946
Test name
Test status
Simulation time 41486114 ps
CPU time 1.6 seconds
Started Aug 07 06:59:29 PM PDT 24
Finished Aug 07 06:59:30 PM PDT 24
Peak memory 218560 kb
Host smart-84728729-a1d2-4f99-b19b-6d34d06a4abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629319230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2629319230
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.437217706
Short name T739
Test name
Test status
Simulation time 75766439 ps
CPU time 1.48 seconds
Started Aug 07 06:59:18 PM PDT 24
Finished Aug 07 06:59:20 PM PDT 24
Peak memory 218632 kb
Host smart-a80c0b29-8d59-45e8-a90b-c7a8895b5490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437217706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.437217706
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2893755313
Short name T437
Test name
Test status
Simulation time 94073188 ps
CPU time 1.13 seconds
Started Aug 07 06:59:18 PM PDT 24
Finished Aug 07 06:59:20 PM PDT 24
Peak memory 216956 kb
Host smart-6d39550e-762b-4cbe-b797-44f4efd99f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893755313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2893755313
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1235415893
Short name T576
Test name
Test status
Simulation time 92356990 ps
CPU time 1.08 seconds
Started Aug 07 06:59:19 PM PDT 24
Finished Aug 07 06:59:20 PM PDT 24
Peak memory 216884 kb
Host smart-05086fa5-38c1-4a0d-b625-38c5d4ef5d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235415893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1235415893
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3894576682
Short name T982
Test name
Test status
Simulation time 61098269 ps
CPU time 1.38 seconds
Started Aug 07 06:59:18 PM PDT 24
Finished Aug 07 06:59:20 PM PDT 24
Peak memory 217900 kb
Host smart-2dafb293-4961-4bc6-9b05-cd311e9b4648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894576682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3894576682
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2371247433
Short name T835
Test name
Test status
Simulation time 33329299 ps
CPU time 1.21 seconds
Started Aug 07 06:59:25 PM PDT 24
Finished Aug 07 06:59:26 PM PDT 24
Peak memory 216812 kb
Host smart-ab05189a-a826-4492-9136-7541b392ef4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371247433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2371247433
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.215233855
Short name T732
Test name
Test status
Simulation time 78428839 ps
CPU time 1.16 seconds
Started Aug 07 06:56:06 PM PDT 24
Finished Aug 07 06:56:07 PM PDT 24
Peak memory 219584 kb
Host smart-3f2e3345-f337-4058-896f-024bbcad74a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215233855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.215233855
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3820651356
Short name T488
Test name
Test status
Simulation time 93827233 ps
CPU time 0.85 seconds
Started Aug 07 06:56:07 PM PDT 24
Finished Aug 07 06:56:08 PM PDT 24
Peak memory 206520 kb
Host smart-1a617bb2-9d9d-43a7-b52c-3bc158068797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820651356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3820651356
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.4013321291
Short name T650
Test name
Test status
Simulation time 27531293 ps
CPU time 1.06 seconds
Started Aug 07 06:56:07 PM PDT 24
Finished Aug 07 06:56:08 PM PDT 24
Peak memory 217200 kb
Host smart-b08d61d3-bf0d-4c3d-b24c-cae87b79848c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013321291 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.4013321291
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.200048585
Short name T521
Test name
Test status
Simulation time 24270268 ps
CPU time 0.86 seconds
Started Aug 07 06:56:04 PM PDT 24
Finished Aug 07 06:56:05 PM PDT 24
Peak memory 218388 kb
Host smart-92726924-920c-4852-ae9f-f3a36dd87fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200048585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.200048585
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1936118653
Short name T661
Test name
Test status
Simulation time 77765539 ps
CPU time 1.13 seconds
Started Aug 07 06:56:05 PM PDT 24
Finished Aug 07 06:56:06 PM PDT 24
Peak memory 218680 kb
Host smart-7013960e-52aa-479e-adfc-a36e7a46a895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936118653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1936118653
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.345118837
Short name T647
Test name
Test status
Simulation time 27633314 ps
CPU time 1.04 seconds
Started Aug 07 06:56:04 PM PDT 24
Finished Aug 07 06:56:05 PM PDT 24
Peak memory 223836 kb
Host smart-13f48f75-22f9-42cf-a5af-499341c96a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345118837 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.345118837
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2195352732
Short name T635
Test name
Test status
Simulation time 29867067 ps
CPU time 0.96 seconds
Started Aug 07 06:56:06 PM PDT 24
Finished Aug 07 06:56:07 PM PDT 24
Peak memory 214928 kb
Host smart-3e6119b7-d955-497a-b8d8-a792dccfcbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195352732 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2195352732
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.899203022
Short name T769
Test name
Test status
Simulation time 180879765 ps
CPU time 3.82 seconds
Started Aug 07 06:56:07 PM PDT 24
Finished Aug 07 06:56:11 PM PDT 24
Peak memory 217016 kb
Host smart-1264cf69-77af-4b0b-8c46-c678c0888393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899203022 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.899203022
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.431452916
Short name T232
Test name
Test status
Simulation time 532071305632 ps
CPU time 3044.9 seconds
Started Aug 07 06:56:08 PM PDT 24
Finished Aug 07 07:46:53 PM PDT 24
Peak memory 229424 kb
Host smart-c7cfa93b-9e67-479c-84a3-34158f90b320
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431452916 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.431452916
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2092855898
Short name T312
Test name
Test status
Simulation time 45837356 ps
CPU time 1.77 seconds
Started Aug 07 06:59:30 PM PDT 24
Finished Aug 07 06:59:32 PM PDT 24
Peak memory 218268 kb
Host smart-768e0651-f333-458e-910a-6c299ba3e8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092855898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2092855898
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1340003832
Short name T308
Test name
Test status
Simulation time 145565912 ps
CPU time 2.79 seconds
Started Aug 07 06:59:24 PM PDT 24
Finished Aug 07 06:59:27 PM PDT 24
Peak memory 220096 kb
Host smart-40fd0fb5-7848-4612-af33-59c084841e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340003832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1340003832
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.99576467
Short name T484
Test name
Test status
Simulation time 43469965 ps
CPU time 1.26 seconds
Started Aug 07 06:59:26 PM PDT 24
Finished Aug 07 06:59:28 PM PDT 24
Peak memory 218028 kb
Host smart-60b24b48-1863-4688-8cab-6d8143a24eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99576467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.99576467
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.4181218148
Short name T712
Test name
Test status
Simulation time 45847400 ps
CPU time 1.57 seconds
Started Aug 07 06:59:28 PM PDT 24
Finished Aug 07 06:59:30 PM PDT 24
Peak memory 218416 kb
Host smart-3741d030-af3b-4a9e-91e1-f58769227f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181218148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.4181218148
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1355220590
Short name T516
Test name
Test status
Simulation time 28838499 ps
CPU time 1.26 seconds
Started Aug 07 06:59:31 PM PDT 24
Finished Aug 07 06:59:32 PM PDT 24
Peak memory 219720 kb
Host smart-17f8763f-6b66-40b8-acfe-7016464fcfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355220590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1355220590
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.4014001436
Short name T319
Test name
Test status
Simulation time 57727222 ps
CPU time 1.51 seconds
Started Aug 07 06:59:27 PM PDT 24
Finished Aug 07 06:59:29 PM PDT 24
Peak memory 218096 kb
Host smart-da01af8a-1d94-44de-bf9f-ffd108c85fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014001436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.4014001436
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2338165351
Short name T763
Test name
Test status
Simulation time 69967223 ps
CPU time 2.56 seconds
Started Aug 07 06:59:27 PM PDT 24
Finished Aug 07 06:59:30 PM PDT 24
Peak memory 219980 kb
Host smart-87087cf2-178c-41a5-ab8f-226055f57ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338165351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2338165351
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1005773606
Short name T466
Test name
Test status
Simulation time 29807685 ps
CPU time 1.06 seconds
Started Aug 07 06:59:29 PM PDT 24
Finished Aug 07 06:59:30 PM PDT 24
Peak memory 219304 kb
Host smart-91360a5e-cb24-44ef-b9d5-8b1ce48a2d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005773606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1005773606
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3386613924
Short name T478
Test name
Test status
Simulation time 76112096 ps
CPU time 1.78 seconds
Started Aug 07 06:59:32 PM PDT 24
Finished Aug 07 06:59:33 PM PDT 24
Peak memory 218396 kb
Host smart-5607e46e-0682-4f14-b93c-9115be91d7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386613924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3386613924
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.817297677
Short name T108
Test name
Test status
Simulation time 37541929 ps
CPU time 1.47 seconds
Started Aug 07 06:59:31 PM PDT 24
Finished Aug 07 06:59:32 PM PDT 24
Peak memory 218204 kb
Host smart-d57a6804-24df-4d10-bf10-1389ada0257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817297677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.817297677
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.4279784786
Short name T917
Test name
Test status
Simulation time 377291173 ps
CPU time 1.24 seconds
Started Aug 07 06:56:12 PM PDT 24
Finished Aug 07 06:56:13 PM PDT 24
Peak memory 219232 kb
Host smart-a5f21bcb-55bf-4969-9ca1-83716c6df473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279784786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.4279784786
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3957734588
Short name T603
Test name
Test status
Simulation time 19063620 ps
CPU time 0.85 seconds
Started Aug 07 06:56:11 PM PDT 24
Finished Aug 07 06:56:12 PM PDT 24
Peak memory 206408 kb
Host smart-964b2fce-cbac-416b-bf7d-e6d27f623718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957734588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3957734588
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2666266178
Short name T177
Test name
Test status
Simulation time 52738257 ps
CPU time 0.86 seconds
Started Aug 07 06:56:14 PM PDT 24
Finished Aug 07 06:56:15 PM PDT 24
Peak memory 216192 kb
Host smart-de9ea311-6755-4f93-ae10-4b41892103fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666266178 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2666266178
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1928476188
Short name T419
Test name
Test status
Simulation time 100630500 ps
CPU time 1.15 seconds
Started Aug 07 06:56:10 PM PDT 24
Finished Aug 07 06:56:11 PM PDT 24
Peak memory 216716 kb
Host smart-cb55dfce-36ff-43b7-8ae1-80b89443c175
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928476188 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1928476188
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1665213013
Short name T202
Test name
Test status
Simulation time 34087459 ps
CPU time 0.91 seconds
Started Aug 07 06:56:13 PM PDT 24
Finished Aug 07 06:56:14 PM PDT 24
Peak memory 219480 kb
Host smart-fe7cc76e-764c-4b09-bfdd-fb5fb1a0d226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665213013 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1665213013
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3791543222
Short name T458
Test name
Test status
Simulation time 65993061 ps
CPU time 1.11 seconds
Started Aug 07 06:56:06 PM PDT 24
Finished Aug 07 06:56:07 PM PDT 24
Peak memory 218196 kb
Host smart-4fdc0be8-2b90-41a8-b638-b99ca4166be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791543222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3791543222
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1813990991
Short name T5
Test name
Test status
Simulation time 25611316 ps
CPU time 0.99 seconds
Started Aug 07 06:56:11 PM PDT 24
Finished Aug 07 06:56:12 PM PDT 24
Peak memory 215628 kb
Host smart-84c034d2-eef0-4330-b478-06dbd6bc3026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813990991 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1813990991
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3845554742
Short name T53
Test name
Test status
Simulation time 18336343 ps
CPU time 1.02 seconds
Started Aug 07 06:56:10 PM PDT 24
Finished Aug 07 06:56:11 PM PDT 24
Peak memory 214912 kb
Host smart-3fc0c841-c921-47b8-a426-5c7c10c25a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845554742 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3845554742
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.310099363
Short name T493
Test name
Test status
Simulation time 411459108 ps
CPU time 4.83 seconds
Started Aug 07 06:56:05 PM PDT 24
Finished Aug 07 06:56:10 PM PDT 24
Peak memory 216700 kb
Host smart-f037eab1-8cb0-41cb-abb5-0282a05e91d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310099363 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.310099363
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/230.edn_genbits.1687274748
Short name T501
Test name
Test status
Simulation time 27543145 ps
CPU time 1.2 seconds
Started Aug 07 06:59:23 PM PDT 24
Finished Aug 07 06:59:24 PM PDT 24
Peak memory 216856 kb
Host smart-4d6265fd-783b-4fd6-9b22-05ce4aa77cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687274748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1687274748
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3925106539
Short name T566
Test name
Test status
Simulation time 49031252 ps
CPU time 1.17 seconds
Started Aug 07 06:59:32 PM PDT 24
Finished Aug 07 06:59:33 PM PDT 24
Peak memory 216796 kb
Host smart-87df05d8-b360-4ecd-8a78-8ff9eaf66e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925106539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3925106539
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3677586657
Short name T639
Test name
Test status
Simulation time 82976819 ps
CPU time 1.56 seconds
Started Aug 07 06:59:33 PM PDT 24
Finished Aug 07 06:59:34 PM PDT 24
Peak memory 218212 kb
Host smart-1c0f555d-a524-49c5-b994-619859457d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677586657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3677586657
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2213721404
Short name T282
Test name
Test status
Simulation time 71148439 ps
CPU time 1.12 seconds
Started Aug 07 06:59:31 PM PDT 24
Finished Aug 07 06:59:32 PM PDT 24
Peak memory 216796 kb
Host smart-7f377f3c-d8f5-44aa-b41d-c414380acceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213721404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2213721404
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3220306162
Short name T785
Test name
Test status
Simulation time 30027350 ps
CPU time 1.27 seconds
Started Aug 07 06:59:33 PM PDT 24
Finished Aug 07 06:59:34 PM PDT 24
Peak memory 216576 kb
Host smart-ddcdf653-60e8-4aef-8e1b-d50de9301ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220306162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3220306162
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2356432536
Short name T806
Test name
Test status
Simulation time 47257172 ps
CPU time 1.48 seconds
Started Aug 07 06:59:31 PM PDT 24
Finished Aug 07 06:59:33 PM PDT 24
Peak memory 218188 kb
Host smart-0c86e03b-b66f-4bb9-b5f3-2be719245b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356432536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2356432536
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3714453724
Short name T977
Test name
Test status
Simulation time 34939184 ps
CPU time 1.29 seconds
Started Aug 07 06:59:31 PM PDT 24
Finished Aug 07 06:59:32 PM PDT 24
Peak memory 216804 kb
Host smart-e41b176d-857c-4fff-a5bb-fb8c7d01717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714453724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3714453724
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2478065073
Short name T33
Test name
Test status
Simulation time 52873842 ps
CPU time 1.9 seconds
Started Aug 07 06:59:28 PM PDT 24
Finished Aug 07 06:59:30 PM PDT 24
Peak memory 218424 kb
Host smart-bc312da3-7e72-40b1-8802-b9757c4fe05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478065073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2478065073
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.114752921
Short name T316
Test name
Test status
Simulation time 53789753 ps
CPU time 1.26 seconds
Started Aug 07 06:59:27 PM PDT 24
Finished Aug 07 06:59:28 PM PDT 24
Peak memory 216860 kb
Host smart-c3217a53-6b30-4ac4-b788-a84fd6963920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114752921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.114752921
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1990678108
Short name T395
Test name
Test status
Simulation time 103278931 ps
CPU time 1.26 seconds
Started Aug 07 06:59:30 PM PDT 24
Finished Aug 07 06:59:32 PM PDT 24
Peak memory 219520 kb
Host smart-04274608-3e63-437d-a834-cfb068caca42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990678108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1990678108
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.347716632
Short name T775
Test name
Test status
Simulation time 27924315 ps
CPU time 1.22 seconds
Started Aug 07 06:56:10 PM PDT 24
Finished Aug 07 06:56:12 PM PDT 24
Peak memory 220232 kb
Host smart-5a7df1ed-5241-47f7-99a0-d87176a11395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347716632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.347716632
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.591989656
Short name T65
Test name
Test status
Simulation time 21778862 ps
CPU time 1.09 seconds
Started Aug 07 06:56:13 PM PDT 24
Finished Aug 07 06:56:14 PM PDT 24
Peak memory 214764 kb
Host smart-32ac643d-c762-4edf-94ef-d2236cca803c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591989656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.591989656
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3434266523
Short name T176
Test name
Test status
Simulation time 11198566 ps
CPU time 0.88 seconds
Started Aug 07 06:56:11 PM PDT 24
Finished Aug 07 06:56:12 PM PDT 24
Peak memory 216236 kb
Host smart-1d40b121-565d-4c72-b3b8-b9de6a8880a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434266523 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3434266523
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2635657397
Short name T834
Test name
Test status
Simulation time 18437424 ps
CPU time 0.97 seconds
Started Aug 07 06:56:12 PM PDT 24
Finished Aug 07 06:56:13 PM PDT 24
Peak memory 218420 kb
Host smart-2d477b59-8f1a-422c-9b26-0fd088199bcc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635657397 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2635657397
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2096443696
Short name T131
Test name
Test status
Simulation time 26702727 ps
CPU time 1.11 seconds
Started Aug 07 06:56:13 PM PDT 24
Finished Aug 07 06:56:14 PM PDT 24
Peak memory 229348 kb
Host smart-766d681f-856c-42c7-8c29-d351c0838bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096443696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2096443696
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.717047327
Short name T549
Test name
Test status
Simulation time 75781235 ps
CPU time 1.36 seconds
Started Aug 07 06:56:11 PM PDT 24
Finished Aug 07 06:56:13 PM PDT 24
Peak memory 218144 kb
Host smart-e4555af1-8f74-4e9e-9a55-8d2dd34019f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717047327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.717047327
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3434763395
Short name T359
Test name
Test status
Simulation time 33857640 ps
CPU time 0.87 seconds
Started Aug 07 06:56:14 PM PDT 24
Finished Aug 07 06:56:15 PM PDT 24
Peak memory 214980 kb
Host smart-809581ec-b1dd-4622-992a-10b06a10b834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434763395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3434763395
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3553353047
Short name T474
Test name
Test status
Simulation time 22560293 ps
CPU time 0.92 seconds
Started Aug 07 06:56:10 PM PDT 24
Finished Aug 07 06:56:11 PM PDT 24
Peak memory 206728 kb
Host smart-fa530ab0-fbd2-43d5-bec5-64e07fd1c657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553353047 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3553353047
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1718306061
Short name T515
Test name
Test status
Simulation time 265014614 ps
CPU time 3.14 seconds
Started Aug 07 06:56:12 PM PDT 24
Finished Aug 07 06:56:16 PM PDT 24
Peak memory 214944 kb
Host smart-fbd4d3cb-fb0e-4147-89f6-f7956ad14b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718306061 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1718306061
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.491223486
Short name T935
Test name
Test status
Simulation time 230945260361 ps
CPU time 2795.24 seconds
Started Aug 07 06:56:13 PM PDT 24
Finished Aug 07 07:42:48 PM PDT 24
Peak memory 232312 kb
Host smart-379fce40-d153-497c-828a-567707a7d198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491223486 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.491223486
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3637742419
Short name T402
Test name
Test status
Simulation time 202724540 ps
CPU time 1.28 seconds
Started Aug 07 06:59:31 PM PDT 24
Finished Aug 07 06:59:33 PM PDT 24
Peak memory 218236 kb
Host smart-4d170360-794f-40df-b22a-12c835f23652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637742419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3637742419
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1428076275
Short name T91
Test name
Test status
Simulation time 87950560 ps
CPU time 1.06 seconds
Started Aug 07 06:59:28 PM PDT 24
Finished Aug 07 06:59:29 PM PDT 24
Peak memory 214908 kb
Host smart-4a5d8d26-8c77-460a-af46-29c820469cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428076275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1428076275
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1467107881
Short name T912
Test name
Test status
Simulation time 56410606 ps
CPU time 1.71 seconds
Started Aug 07 06:59:28 PM PDT 24
Finished Aug 07 06:59:30 PM PDT 24
Peak memory 218292 kb
Host smart-dd738e14-f400-487a-9500-29dd4492068a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467107881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1467107881
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1681418022
Short name T883
Test name
Test status
Simulation time 103853543 ps
CPU time 1.06 seconds
Started Aug 07 06:59:34 PM PDT 24
Finished Aug 07 06:59:36 PM PDT 24
Peak memory 216984 kb
Host smart-c29b473b-4754-4c4d-a03b-d1f23be9feb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681418022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1681418022
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.666842099
Short name T781
Test name
Test status
Simulation time 52439449 ps
CPU time 1.74 seconds
Started Aug 07 06:59:34 PM PDT 24
Finished Aug 07 06:59:36 PM PDT 24
Peak memory 218300 kb
Host smart-5c359649-8410-43c8-bfb8-48f5b4634a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666842099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.666842099
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2878913262
Short name T518
Test name
Test status
Simulation time 46801330 ps
CPU time 1.28 seconds
Started Aug 07 06:59:34 PM PDT 24
Finished Aug 07 06:59:36 PM PDT 24
Peak memory 216908 kb
Host smart-9a1f153f-dd48-4030-8949-1f066b1d0053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878913262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2878913262
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3225849987
Short name T724
Test name
Test status
Simulation time 32660159 ps
CPU time 1.31 seconds
Started Aug 07 06:59:32 PM PDT 24
Finished Aug 07 06:59:34 PM PDT 24
Peak memory 219660 kb
Host smart-72e25713-ccd4-4493-86a8-2fd025c45b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225849987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3225849987
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3496069802
Short name T317
Test name
Test status
Simulation time 31780243 ps
CPU time 1.29 seconds
Started Aug 07 06:59:33 PM PDT 24
Finished Aug 07 06:59:34 PM PDT 24
Peak memory 218220 kb
Host smart-8204ab2c-6681-4ff1-a3e4-f8ea41b1f73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496069802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3496069802
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2089291124
Short name T852
Test name
Test status
Simulation time 79151003 ps
CPU time 2.27 seconds
Started Aug 07 06:59:36 PM PDT 24
Finished Aug 07 06:59:38 PM PDT 24
Peak memory 219576 kb
Host smart-3ddf8ed0-5ef0-452b-b52f-df4a889fbe1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089291124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2089291124
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2237364044
Short name T905
Test name
Test status
Simulation time 37790552 ps
CPU time 1.29 seconds
Started Aug 07 06:59:33 PM PDT 24
Finished Aug 07 06:59:34 PM PDT 24
Peak memory 217056 kb
Host smart-58a0ad60-cd9b-47d2-8944-890d681beb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237364044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2237364044
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2452546926
Short name T690
Test name
Test status
Simulation time 26757185 ps
CPU time 1.23 seconds
Started Aug 07 06:56:14 PM PDT 24
Finished Aug 07 06:56:16 PM PDT 24
Peak memory 218284 kb
Host smart-ae6816a9-783f-4c1a-9617-7f470e01632d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452546926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2452546926
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3547202695
Short name T620
Test name
Test status
Simulation time 22506802 ps
CPU time 1.03 seconds
Started Aug 07 06:56:11 PM PDT 24
Finished Aug 07 06:56:12 PM PDT 24
Peak memory 206348 kb
Host smart-fc162246-a46d-49eb-bbc8-1a68489de386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547202695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3547202695
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3606602522
Short name T746
Test name
Test status
Simulation time 13575293 ps
CPU time 0.9 seconds
Started Aug 07 06:56:14 PM PDT 24
Finished Aug 07 06:56:15 PM PDT 24
Peak memory 215176 kb
Host smart-9d0ad33c-edb7-45c9-915c-5fb622dbccf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606602522 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3606602522
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2265104055
Short name T752
Test name
Test status
Simulation time 37300123 ps
CPU time 1.34 seconds
Started Aug 07 06:56:11 PM PDT 24
Finished Aug 07 06:56:12 PM PDT 24
Peak memory 216960 kb
Host smart-59159bf1-f700-4ecd-88db-9fcbf4e07e0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265104055 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2265104055
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1602789204
Short name T528
Test name
Test status
Simulation time 40753320 ps
CPU time 0.91 seconds
Started Aug 07 06:56:11 PM PDT 24
Finished Aug 07 06:56:12 PM PDT 24
Peak memory 218496 kb
Host smart-75b93c49-1e36-42b5-8add-e3da9ea502ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602789204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1602789204
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3390179604
Short name T353
Test name
Test status
Simulation time 75149514 ps
CPU time 1.42 seconds
Started Aug 07 06:56:12 PM PDT 24
Finished Aug 07 06:56:13 PM PDT 24
Peak memory 219936 kb
Host smart-98284154-2e9c-4429-be6b-ece13bc4cf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390179604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3390179604
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.389657686
Short name T483
Test name
Test status
Simulation time 21853285 ps
CPU time 1.03 seconds
Started Aug 07 06:56:14 PM PDT 24
Finished Aug 07 06:56:15 PM PDT 24
Peak memory 215160 kb
Host smart-09421f6c-56b8-416a-a3cf-4a5d127cc887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389657686 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.389657686
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1285570379
Short name T861
Test name
Test status
Simulation time 18173598 ps
CPU time 1.08 seconds
Started Aug 07 06:56:11 PM PDT 24
Finished Aug 07 06:56:12 PM PDT 24
Peak memory 214996 kb
Host smart-cda3e989-9958-4172-9332-0b70bb6e939a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285570379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1285570379
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.414190433
Short name T672
Test name
Test status
Simulation time 276288372 ps
CPU time 1.5 seconds
Started Aug 07 06:56:12 PM PDT 24
Finished Aug 07 06:56:14 PM PDT 24
Peak memory 214920 kb
Host smart-7ff5e290-78e3-48a9-905b-3bae07236c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414190433 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.414190433
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2747846265
Short name T310
Test name
Test status
Simulation time 171196335934 ps
CPU time 948.38 seconds
Started Aug 07 06:56:13 PM PDT 24
Finished Aug 07 07:12:02 PM PDT 24
Peak memory 221132 kb
Host smart-3b57efe8-4b6d-438f-892e-c8f3c18720c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747846265 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2747846265
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.692926210
Short name T31
Test name
Test status
Simulation time 114549297 ps
CPU time 1.65 seconds
Started Aug 07 06:59:33 PM PDT 24
Finished Aug 07 06:59:34 PM PDT 24
Peak memory 218384 kb
Host smart-67c2b998-e2e1-41b3-b18c-402a0087da80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692926210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.692926210
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.503496003
Short name T597
Test name
Test status
Simulation time 87745540 ps
CPU time 1.31 seconds
Started Aug 07 06:59:33 PM PDT 24
Finished Aug 07 06:59:34 PM PDT 24
Peak memory 214884 kb
Host smart-01d95c20-e79f-4ef2-b952-c71ebc4fc9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503496003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.503496003
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2376316914
Short name T802
Test name
Test status
Simulation time 46136067 ps
CPU time 1.57 seconds
Started Aug 07 06:59:34 PM PDT 24
Finished Aug 07 06:59:36 PM PDT 24
Peak memory 219572 kb
Host smart-552934ab-abbc-4de6-89ba-e725e729d29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376316914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2376316914
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.492965000
Short name T394
Test name
Test status
Simulation time 69402802 ps
CPU time 1.22 seconds
Started Aug 07 06:59:37 PM PDT 24
Finished Aug 07 06:59:38 PM PDT 24
Peak memory 218760 kb
Host smart-8213636b-d64a-48fe-8c97-617ba498d84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492965000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.492965000
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.712587132
Short name T278
Test name
Test status
Simulation time 77483409 ps
CPU time 1.42 seconds
Started Aug 07 06:59:37 PM PDT 24
Finished Aug 07 06:59:39 PM PDT 24
Peak memory 218024 kb
Host smart-2a5503fe-7859-423e-b4e7-06d97d4e73a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712587132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.712587132
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3220326147
Short name T517
Test name
Test status
Simulation time 47347019 ps
CPU time 1.18 seconds
Started Aug 07 06:59:42 PM PDT 24
Finished Aug 07 06:59:43 PM PDT 24
Peak memory 216980 kb
Host smart-bb81a07c-5509-42af-b955-40c6d854cc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220326147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3220326147
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4285726956
Short name T567
Test name
Test status
Simulation time 108420682 ps
CPU time 1.15 seconds
Started Aug 07 06:59:38 PM PDT 24
Finished Aug 07 06:59:39 PM PDT 24
Peak memory 217000 kb
Host smart-83154d0b-3367-45ea-a6d1-f77a8969cf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285726956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4285726956
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.732514525
Short name T354
Test name
Test status
Simulation time 42524384 ps
CPU time 1.06 seconds
Started Aug 07 06:56:16 PM PDT 24
Finished Aug 07 06:56:17 PM PDT 24
Peak memory 214736 kb
Host smart-ab3d497b-e545-4642-9d97-851113126a07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732514525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.732514525
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.952551946
Short name T897
Test name
Test status
Simulation time 19298587 ps
CPU time 0.86 seconds
Started Aug 07 06:56:21 PM PDT 24
Finished Aug 07 06:56:22 PM PDT 24
Peak memory 215132 kb
Host smart-dc7e1476-cc6e-49ac-95c1-0c830d64ca5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952551946 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.952551946
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1254061352
Short name T444
Test name
Test status
Simulation time 35183871 ps
CPU time 0.99 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 06:56:23 PM PDT 24
Peak memory 219536 kb
Host smart-1c91fb2c-62c1-4751-ba3a-5b83a226dcbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254061352 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1254061352
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_intr.3187379239
Short name T74
Test name
Test status
Simulation time 34656062 ps
CPU time 0.95 seconds
Started Aug 07 06:56:18 PM PDT 24
Finished Aug 07 06:56:19 PM PDT 24
Peak memory 214988 kb
Host smart-30f5d91f-5b25-477a-8ed4-dff3eec1ad4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187379239 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3187379239
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.428762371
Short name T362
Test name
Test status
Simulation time 18245262 ps
CPU time 1.02 seconds
Started Aug 07 06:56:11 PM PDT 24
Finished Aug 07 06:56:12 PM PDT 24
Peak memory 214936 kb
Host smart-936e75c3-ad6c-4c5c-9a85-c2d8ebf794de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428762371 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.428762371
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2362192945
Short name T109
Test name
Test status
Simulation time 114304110 ps
CPU time 2.66 seconds
Started Aug 07 06:56:18 PM PDT 24
Finished Aug 07 06:56:20 PM PDT 24
Peak memory 214992 kb
Host smart-1d7118b6-5e83-41fa-9a1a-4d824b5c845d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362192945 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2362192945
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2014519037
Short name T225
Test name
Test status
Simulation time 107423313852 ps
CPU time 614.63 seconds
Started Aug 07 06:56:17 PM PDT 24
Finished Aug 07 07:06:32 PM PDT 24
Peak memory 219464 kb
Host smart-89a23a01-2b49-42f1-b440-b11391e44c8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014519037 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2014519037
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3571190848
Short name T691
Test name
Test status
Simulation time 46965741 ps
CPU time 1.38 seconds
Started Aug 07 06:59:42 PM PDT 24
Finished Aug 07 06:59:43 PM PDT 24
Peak memory 219140 kb
Host smart-e8843910-c813-4205-9038-39f26850bb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571190848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3571190848
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1275423457
Short name T550
Test name
Test status
Simulation time 76620016 ps
CPU time 1.18 seconds
Started Aug 07 06:59:41 PM PDT 24
Finished Aug 07 06:59:42 PM PDT 24
Peak memory 216836 kb
Host smart-5e8e36bc-9438-44d2-b097-5dd253afdcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275423457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1275423457
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2149404416
Short name T824
Test name
Test status
Simulation time 49569286 ps
CPU time 1.22 seconds
Started Aug 07 06:59:38 PM PDT 24
Finished Aug 07 06:59:39 PM PDT 24
Peak memory 218996 kb
Host smart-1f9ba9fc-8b09-4f7d-a942-56a8e819f695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149404416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2149404416
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2094722117
Short name T873
Test name
Test status
Simulation time 41499098 ps
CPU time 1.48 seconds
Started Aug 07 06:59:41 PM PDT 24
Finished Aug 07 06:59:43 PM PDT 24
Peak memory 218092 kb
Host smart-3957d938-64e1-42af-999b-21906b7b9263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094722117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2094722117
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2214063838
Short name T943
Test name
Test status
Simulation time 66339665 ps
CPU time 1.72 seconds
Started Aug 07 06:59:38 PM PDT 24
Finished Aug 07 06:59:40 PM PDT 24
Peak memory 218300 kb
Host smart-5e11e0c2-0671-437e-a9a6-553b1d6b59ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214063838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2214063838
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.665762035
Short name T443
Test name
Test status
Simulation time 54380958 ps
CPU time 1.03 seconds
Started Aug 07 06:59:42 PM PDT 24
Finished Aug 07 06:59:43 PM PDT 24
Peak memory 216988 kb
Host smart-14e0d298-d937-4659-a179-765e8bb4738c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665762035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.665762035
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.473101661
Short name T440
Test name
Test status
Simulation time 50576345 ps
CPU time 2.01 seconds
Started Aug 07 06:59:37 PM PDT 24
Finished Aug 07 06:59:39 PM PDT 24
Peak memory 217168 kb
Host smart-c0febc9d-5b58-4983-9848-2a71bdfe733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473101661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.473101661
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3346089294
Short name T304
Test name
Test status
Simulation time 76916920 ps
CPU time 1.69 seconds
Started Aug 07 06:59:46 PM PDT 24
Finished Aug 07 06:59:48 PM PDT 24
Peak memory 220100 kb
Host smart-1afd9f95-ba0f-4e92-95ba-ae636d936ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346089294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3346089294
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2342542152
Short name T320
Test name
Test status
Simulation time 45121925 ps
CPU time 1.32 seconds
Started Aug 07 06:59:44 PM PDT 24
Finished Aug 07 06:59:45 PM PDT 24
Peak memory 219400 kb
Host smart-d1fb4819-01d5-4040-aafd-a08978226dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342542152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2342542152
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.86206765
Short name T803
Test name
Test status
Simulation time 66300064 ps
CPU time 1.17 seconds
Started Aug 07 06:59:46 PM PDT 24
Finished Aug 07 06:59:47 PM PDT 24
Peak memory 218260 kb
Host smart-73d492eb-1038-4a1a-9e5c-ec1e68f17de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86206765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.86206765
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1290431075
Short name T578
Test name
Test status
Simulation time 129258120 ps
CPU time 1.19 seconds
Started Aug 07 06:56:20 PM PDT 24
Finished Aug 07 06:56:21 PM PDT 24
Peak memory 218208 kb
Host smart-c099ddf3-c667-4849-ad86-1b0c328f4d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290431075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1290431075
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3952676721
Short name T849
Test name
Test status
Simulation time 18230107 ps
CPU time 0.97 seconds
Started Aug 07 06:56:17 PM PDT 24
Finished Aug 07 06:56:18 PM PDT 24
Peak memory 214668 kb
Host smart-5b057885-195e-4b3e-9f72-63b0b02538e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952676721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3952676721
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1667381443
Short name T971
Test name
Test status
Simulation time 58595664 ps
CPU time 0.91 seconds
Started Aug 07 06:56:19 PM PDT 24
Finished Aug 07 06:56:20 PM PDT 24
Peak memory 215932 kb
Host smart-947a9ab2-62ee-47be-bdf1-34ec70b64942
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667381443 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1667381443
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.44757713
Short name T133
Test name
Test status
Simulation time 46684946 ps
CPU time 1.37 seconds
Started Aug 07 06:56:18 PM PDT 24
Finished Aug 07 06:56:20 PM PDT 24
Peak memory 216636 kb
Host smart-164d4e97-5fb2-48f3-bac5-5d4801acdfbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44757713 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_dis
able_auto_req_mode.44757713
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3101995683
Short name T397
Test name
Test status
Simulation time 34957884 ps
CPU time 0.84 seconds
Started Aug 07 06:56:19 PM PDT 24
Finished Aug 07 06:56:19 PM PDT 24
Peak memory 217456 kb
Host smart-b4d72b70-dd05-4cce-933e-1bbecb2cfe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101995683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3101995683
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2537992194
Short name T929
Test name
Test status
Simulation time 45312452 ps
CPU time 1.46 seconds
Started Aug 07 06:56:20 PM PDT 24
Finished Aug 07 06:56:21 PM PDT 24
Peak memory 218264 kb
Host smart-2ab3df5b-97f2-4fff-8f35-e921630ccdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537992194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2537992194
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2416482051
Short name T641
Test name
Test status
Simulation time 40238909 ps
CPU time 0.88 seconds
Started Aug 07 06:56:17 PM PDT 24
Finished Aug 07 06:56:18 PM PDT 24
Peak memory 215056 kb
Host smart-86e0e765-89b9-4897-be35-280f8446b489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416482051 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2416482051
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3541137711
Short name T774
Test name
Test status
Simulation time 40596838 ps
CPU time 0.93 seconds
Started Aug 07 06:56:17 PM PDT 24
Finished Aug 07 06:56:18 PM PDT 24
Peak memory 214896 kb
Host smart-b15a8678-79ce-41e6-b5da-55c8a6274518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541137711 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3541137711
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3953636399
Short name T939
Test name
Test status
Simulation time 351625328 ps
CPU time 3.71 seconds
Started Aug 07 06:56:17 PM PDT 24
Finished Aug 07 06:56:21 PM PDT 24
Peak memory 214896 kb
Host smart-846b1aae-db55-467b-b650-ccb30da0df7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953636399 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3953636399
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3179484799
Short name T973
Test name
Test status
Simulation time 35536048248 ps
CPU time 767.44 seconds
Started Aug 07 06:56:18 PM PDT 24
Finished Aug 07 07:09:05 PM PDT 24
Peak memory 217076 kb
Host smart-38d37720-73ba-4ed1-a0c4-299617e6a4c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179484799 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3179484799
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.892603891
Short name T10
Test name
Test status
Simulation time 46232273 ps
CPU time 1.57 seconds
Started Aug 07 06:59:47 PM PDT 24
Finished Aug 07 06:59:49 PM PDT 24
Peak memory 215072 kb
Host smart-3ce55e59-b5f9-4d1d-a538-8c9258ce84c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892603891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.892603891
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1457280606
Short name T656
Test name
Test status
Simulation time 37197918 ps
CPU time 1.53 seconds
Started Aug 07 06:59:44 PM PDT 24
Finished Aug 07 06:59:46 PM PDT 24
Peak memory 219812 kb
Host smart-2e86f98b-6b23-48a1-9431-542f3da81c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457280606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1457280606
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3690994082
Short name T540
Test name
Test status
Simulation time 40815965 ps
CPU time 1.72 seconds
Started Aug 07 06:59:45 PM PDT 24
Finished Aug 07 06:59:47 PM PDT 24
Peak memory 218068 kb
Host smart-088e4c7e-872a-46c2-be0c-e1078dc60e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690994082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3690994082
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3397918711
Short name T410
Test name
Test status
Simulation time 60152445 ps
CPU time 1.08 seconds
Started Aug 07 06:59:44 PM PDT 24
Finished Aug 07 06:59:45 PM PDT 24
Peak memory 216900 kb
Host smart-0fd580bb-ae38-4852-ab40-d849bf96ca73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397918711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3397918711
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3072908031
Short name T574
Test name
Test status
Simulation time 129637879 ps
CPU time 1.66 seconds
Started Aug 07 06:59:47 PM PDT 24
Finished Aug 07 06:59:49 PM PDT 24
Peak memory 219876 kb
Host smart-299623ce-6123-4643-928f-8649fb6f3486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072908031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3072908031
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.4279494253
Short name T581
Test name
Test status
Simulation time 111376380 ps
CPU time 1.34 seconds
Started Aug 07 06:59:47 PM PDT 24
Finished Aug 07 06:59:48 PM PDT 24
Peak memory 216968 kb
Host smart-2a27669a-7c85-4167-bdb2-837bc2b5746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279494253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.4279494253
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1746601794
Short name T553
Test name
Test status
Simulation time 40960371 ps
CPU time 1.19 seconds
Started Aug 07 06:59:52 PM PDT 24
Finished Aug 07 06:59:54 PM PDT 24
Peak memory 217292 kb
Host smart-1726822e-e4d6-4811-958b-41735031bc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746601794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1746601794
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2714467808
Short name T646
Test name
Test status
Simulation time 70918034 ps
CPU time 1.07 seconds
Started Aug 07 06:59:48 PM PDT 24
Finished Aug 07 06:59:49 PM PDT 24
Peak memory 217000 kb
Host smart-0901409c-5d12-4d5c-a7a3-4366fc4801c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714467808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2714467808
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2030589447
Short name T418
Test name
Test status
Simulation time 89598374 ps
CPU time 2.15 seconds
Started Aug 07 06:59:48 PM PDT 24
Finished Aug 07 06:59:51 PM PDT 24
Peak memory 219928 kb
Host smart-816a1432-0426-43b8-af48-0f99a29a3bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030589447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2030589447
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1794557239
Short name T618
Test name
Test status
Simulation time 93046754 ps
CPU time 1.68 seconds
Started Aug 07 06:59:49 PM PDT 24
Finished Aug 07 06:59:51 PM PDT 24
Peak memory 218736 kb
Host smart-82f680e6-961c-489b-9e24-2677bb7b7374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794557239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1794557239
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.545614180
Short name T554
Test name
Test status
Simulation time 104588332 ps
CPU time 1.15 seconds
Started Aug 07 06:56:18 PM PDT 24
Finished Aug 07 06:56:19 PM PDT 24
Peak memory 220552 kb
Host smart-29fbd60c-6612-404d-bec7-a526014f1767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545614180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.545614180
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2728472908
Short name T881
Test name
Test status
Simulation time 54461006 ps
CPU time 0.92 seconds
Started Aug 07 06:56:19 PM PDT 24
Finished Aug 07 06:56:20 PM PDT 24
Peak memory 206380 kb
Host smart-81d2cc27-a0fc-4961-abc1-d928a125c4cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728472908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2728472908
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1617415686
Short name T833
Test name
Test status
Simulation time 13804281 ps
CPU time 0.91 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 06:56:23 PM PDT 24
Peak memory 218964 kb
Host smart-12d8365f-a446-451b-ba8f-c666265b880e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617415686 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1617415686
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1819550393
Short name T134
Test name
Test status
Simulation time 42730363 ps
CPU time 1.44 seconds
Started Aug 07 06:56:19 PM PDT 24
Finished Aug 07 06:56:21 PM PDT 24
Peak memory 216796 kb
Host smart-2c613ccd-9d6d-48ee-94ef-088027ce9a75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819550393 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1819550393
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.600101208
Short name T890
Test name
Test status
Simulation time 24775316 ps
CPU time 0.91 seconds
Started Aug 07 06:56:18 PM PDT 24
Finished Aug 07 06:56:19 PM PDT 24
Peak memory 218284 kb
Host smart-1a10de82-eb44-4f67-bc31-7c1d8fbc02c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600101208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.600101208
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.932615837
Short name T398
Test name
Test status
Simulation time 44423065 ps
CPU time 1.47 seconds
Started Aug 07 06:56:19 PM PDT 24
Finished Aug 07 06:56:21 PM PDT 24
Peak memory 218160 kb
Host smart-135aefc0-9fe4-4e1c-b56e-06d7e42b2814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932615837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.932615837
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.272605180
Short name T351
Test name
Test status
Simulation time 28294478 ps
CPU time 0.88 seconds
Started Aug 07 06:56:17 PM PDT 24
Finished Aug 07 06:56:18 PM PDT 24
Peak memory 214984 kb
Host smart-969fd731-a024-471e-ad58-106287c1cf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272605180 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.272605180
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2133558458
Short name T942
Test name
Test status
Simulation time 46390063 ps
CPU time 0.97 seconds
Started Aug 07 06:56:19 PM PDT 24
Finished Aug 07 06:56:20 PM PDT 24
Peak memory 214880 kb
Host smart-3156d7e5-bec9-4b0d-a41f-e694cb0ba554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133558458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2133558458
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1400808982
Short name T668
Test name
Test status
Simulation time 72449972 ps
CPU time 1.41 seconds
Started Aug 07 06:56:17 PM PDT 24
Finished Aug 07 06:56:18 PM PDT 24
Peak memory 216828 kb
Host smart-e7d47678-97e7-4417-ae7b-e60d977f5a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400808982 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1400808982
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3574782350
Short name T234
Test name
Test status
Simulation time 223724124200 ps
CPU time 1229.53 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 07:16:52 PM PDT 24
Peak memory 222236 kb
Host smart-afaa68ee-f186-419c-b20a-80237838803e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574782350 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3574782350
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3216263788
Short name T78
Test name
Test status
Simulation time 49338983 ps
CPU time 1.17 seconds
Started Aug 07 06:59:52 PM PDT 24
Finished Aug 07 06:59:54 PM PDT 24
Peak memory 216944 kb
Host smart-d379d596-48bb-48cb-9984-f3738d9bde01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216263788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3216263788
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2746742924
Short name T330
Test name
Test status
Simulation time 166757100 ps
CPU time 1.82 seconds
Started Aug 07 06:59:52 PM PDT 24
Finished Aug 07 06:59:54 PM PDT 24
Peak memory 218408 kb
Host smart-a9ca4c27-2b0f-4d13-b191-6a1f4e4c284f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746742924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2746742924
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1955411787
Short name T816
Test name
Test status
Simulation time 37408140 ps
CPU time 1.38 seconds
Started Aug 07 06:59:49 PM PDT 24
Finished Aug 07 06:59:51 PM PDT 24
Peak memory 216868 kb
Host smart-9fb09a37-a039-469c-b1aa-64fdeffa48dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955411787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1955411787
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2765258671
Short name T421
Test name
Test status
Simulation time 99280648 ps
CPU time 1.53 seconds
Started Aug 07 06:59:50 PM PDT 24
Finished Aug 07 06:59:51 PM PDT 24
Peak memory 218528 kb
Host smart-0f5eb9d7-3022-402e-b5f1-08b2f51e766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765258671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2765258671
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1580135952
Short name T602
Test name
Test status
Simulation time 40016618 ps
CPU time 1.34 seconds
Started Aug 07 06:59:47 PM PDT 24
Finished Aug 07 06:59:49 PM PDT 24
Peak memory 217980 kb
Host smart-c45f3a5a-4817-453c-acbb-fe3a0f372e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580135952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1580135952
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2109994072
Short name T507
Test name
Test status
Simulation time 146379675 ps
CPU time 2.05 seconds
Started Aug 07 06:59:49 PM PDT 24
Finished Aug 07 06:59:51 PM PDT 24
Peak memory 219300 kb
Host smart-f9b246a5-b6ab-4d0f-a27a-9ba67f187bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109994072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2109994072
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2738523113
Short name T623
Test name
Test status
Simulation time 102210532 ps
CPU time 2.27 seconds
Started Aug 07 06:59:45 PM PDT 24
Finished Aug 07 06:59:48 PM PDT 24
Peak memory 218172 kb
Host smart-ad322db0-eae6-4b97-86e4-899c2ca7efd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738523113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2738523113
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.435893325
Short name T643
Test name
Test status
Simulation time 51697942 ps
CPU time 1.18 seconds
Started Aug 07 06:59:52 PM PDT 24
Finished Aug 07 06:59:53 PM PDT 24
Peak memory 216812 kb
Host smart-bae922ad-78ba-4064-b598-a48704a4af84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435893325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.435893325
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2127454871
Short name T607
Test name
Test status
Simulation time 42776138 ps
CPU time 1.61 seconds
Started Aug 07 06:59:50 PM PDT 24
Finished Aug 07 06:59:52 PM PDT 24
Peak memory 217020 kb
Host smart-a2abce35-6090-480d-b85d-610c05800b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127454871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2127454871
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3196651464
Short name T401
Test name
Test status
Simulation time 63108445 ps
CPU time 2.1 seconds
Started Aug 07 06:59:53 PM PDT 24
Finished Aug 07 06:59:56 PM PDT 24
Peak memory 218008 kb
Host smart-2abdabfa-0eb9-4c42-b88e-6ae6d438f468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196651464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3196651464
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.280532673
Short name T570
Test name
Test status
Simulation time 30300066 ps
CPU time 1.05 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 06:56:23 PM PDT 24
Peak memory 219332 kb
Host smart-5f890331-1f3d-4a04-9de5-6e2a9d5f3df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280532673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.280532673
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1159044060
Short name T605
Test name
Test status
Simulation time 36770402 ps
CPU time 0.8 seconds
Started Aug 07 06:56:23 PM PDT 24
Finished Aug 07 06:56:24 PM PDT 24
Peak memory 206512 kb
Host smart-a7c0413b-a2f2-49e5-898d-425858b4abf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159044060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1159044060
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3887554849
Short name T25
Test name
Test status
Simulation time 21550722 ps
CPU time 0.88 seconds
Started Aug 07 06:56:26 PM PDT 24
Finished Aug 07 06:56:27 PM PDT 24
Peak memory 216216 kb
Host smart-33b55d35-273d-407d-9bb7-3c69f8712350
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887554849 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3887554849
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2214684778
Short name T922
Test name
Test status
Simulation time 74116478 ps
CPU time 1.13 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 06:56:24 PM PDT 24
Peak memory 219404 kb
Host smart-f308c406-46c2-4eb7-8059-a7aede51e315
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214684778 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2214684778
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3853685235
Short name T73
Test name
Test status
Simulation time 26601001 ps
CPU time 0.89 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 06:56:23 PM PDT 24
Peak memory 218244 kb
Host smart-eae93b55-08a4-4fa5-af8b-4a565c35a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853685235 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3853685235
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.542232242
Short name T366
Test name
Test status
Simulation time 92187378 ps
CPU time 1.46 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 06:56:24 PM PDT 24
Peak memory 218580 kb
Host smart-8d0596cf-c1c4-4153-8c99-a77443fc3b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542232242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.542232242
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2134560558
Short name T546
Test name
Test status
Simulation time 23873920 ps
CPU time 1.09 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 06:56:24 PM PDT 24
Peak memory 223716 kb
Host smart-73bcf1d2-6ced-4283-a6b4-d5e468d7925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134560558 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2134560558
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1424390579
Short name T757
Test name
Test status
Simulation time 43355937 ps
CPU time 0.94 seconds
Started Aug 07 06:56:18 PM PDT 24
Finished Aug 07 06:56:19 PM PDT 24
Peak memory 206740 kb
Host smart-5f77640a-1253-4252-8cda-59e60ddeae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424390579 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1424390579
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.598714753
Short name T244
Test name
Test status
Simulation time 450134167 ps
CPU time 2.15 seconds
Started Aug 07 06:56:23 PM PDT 24
Finished Aug 07 06:56:25 PM PDT 24
Peak memory 214860 kb
Host smart-6deaac53-e48c-4be9-99d1-b957afbe0e08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598714753 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.598714753
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/290.edn_genbits.503187117
Short name T569
Test name
Test status
Simulation time 30228302 ps
CPU time 1.28 seconds
Started Aug 07 06:59:53 PM PDT 24
Finished Aug 07 06:59:54 PM PDT 24
Peak memory 216904 kb
Host smart-16bd6acb-4b4e-4cfb-8520-75f4afbdecd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503187117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.503187117
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.352621320
Short name T499
Test name
Test status
Simulation time 34201141 ps
CPU time 1.05 seconds
Started Aug 07 06:59:51 PM PDT 24
Finished Aug 07 06:59:53 PM PDT 24
Peak memory 217004 kb
Host smart-28d509a4-8fe1-4815-b2c2-f33711684e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352621320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.352621320
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3516591808
Short name T408
Test name
Test status
Simulation time 71381462 ps
CPU time 1.38 seconds
Started Aug 07 06:59:57 PM PDT 24
Finished Aug 07 06:59:58 PM PDT 24
Peak memory 218404 kb
Host smart-4f3692c1-78a3-47c5-a01a-e944a06effb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516591808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3516591808
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1753975116
Short name T80
Test name
Test status
Simulation time 46110264 ps
CPU time 1.3 seconds
Started Aug 07 06:59:58 PM PDT 24
Finished Aug 07 06:59:59 PM PDT 24
Peak memory 218048 kb
Host smart-df334b18-6d3e-4f90-9280-70d7235756e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753975116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1753975116
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2128525973
Short name T323
Test name
Test status
Simulation time 70579901 ps
CPU time 1.35 seconds
Started Aug 07 06:59:59 PM PDT 24
Finished Aug 07 07:00:01 PM PDT 24
Peak memory 218544 kb
Host smart-e4db9a7c-ff49-43a9-a11d-c529375bf9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128525973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2128525973
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3565602278
Short name T872
Test name
Test status
Simulation time 44342615 ps
CPU time 1.15 seconds
Started Aug 07 07:00:01 PM PDT 24
Finished Aug 07 07:00:02 PM PDT 24
Peak memory 216964 kb
Host smart-f069a842-5c63-4486-b1e4-0d0f59ec6da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565602278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3565602278
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3278163621
Short name T870
Test name
Test status
Simulation time 96206985 ps
CPU time 1.26 seconds
Started Aug 07 06:59:58 PM PDT 24
Finished Aug 07 07:00:00 PM PDT 24
Peak memory 217028 kb
Host smart-9973d8e3-c2ed-4727-a4a5-25392c74bb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278163621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3278163621
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2120160665
Short name T910
Test name
Test status
Simulation time 247642118 ps
CPU time 3.08 seconds
Started Aug 07 06:59:58 PM PDT 24
Finished Aug 07 07:00:01 PM PDT 24
Peak memory 217056 kb
Host smart-9514d9bb-fef2-4071-a78d-4ef12f96eaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120160665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2120160665
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1711551164
Short name T944
Test name
Test status
Simulation time 37715913 ps
CPU time 1.18 seconds
Started Aug 07 07:00:01 PM PDT 24
Finished Aug 07 07:00:07 PM PDT 24
Peak memory 218304 kb
Host smart-fca1c026-720c-4e98-ae6a-5f95f8242178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711551164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1711551164
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2215352166
Short name T704
Test name
Test status
Simulation time 85566254 ps
CPU time 1.29 seconds
Started Aug 07 07:00:00 PM PDT 24
Finished Aug 07 07:00:01 PM PDT 24
Peak memory 218584 kb
Host smart-2a36dc38-981b-4e05-a3e5-4a8dd269bbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215352166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2215352166
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.552289399
Short name T276
Test name
Test status
Simulation time 117224236 ps
CPU time 1.27 seconds
Started Aug 07 06:55:22 PM PDT 24
Finished Aug 07 06:55:23 PM PDT 24
Peak memory 219344 kb
Host smart-896f6550-f2bf-46e0-b45d-ebf25fa7c907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552289399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.552289399
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3765572516
Short name T558
Test name
Test status
Simulation time 38565032 ps
CPU time 0.97 seconds
Started Aug 07 06:55:38 PM PDT 24
Finished Aug 07 06:55:39 PM PDT 24
Peak memory 214964 kb
Host smart-f4359c19-e734-4b56-84ef-82ef80c53572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765572516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3765572516
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.74191900
Short name T205
Test name
Test status
Simulation time 13386923 ps
CPU time 0.97 seconds
Started Aug 07 06:55:22 PM PDT 24
Finished Aug 07 06:55:24 PM PDT 24
Peak memory 218996 kb
Host smart-2a10d7c3-e2cf-4b47-a756-35894cb8bf3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74191900 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.74191900
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.284972611
Short name T146
Test name
Test status
Simulation time 33532575 ps
CPU time 1.13 seconds
Started Aug 07 06:55:27 PM PDT 24
Finished Aug 07 06:55:29 PM PDT 24
Peak memory 219136 kb
Host smart-c5471d27-2034-494d-a7da-a4186141d0ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284972611 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.284972611
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2644122954
Short name T817
Test name
Test status
Simulation time 43322725 ps
CPU time 0.94 seconds
Started Aug 07 06:55:25 PM PDT 24
Finished Aug 07 06:55:26 PM PDT 24
Peak memory 229144 kb
Host smart-2c884c12-6653-43fb-a9d1-531a57d17c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644122954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2644122954
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.324584680
Short name T953
Test name
Test status
Simulation time 39222364 ps
CPU time 1.59 seconds
Started Aug 07 06:55:22 PM PDT 24
Finished Aug 07 06:55:24 PM PDT 24
Peak memory 218176 kb
Host smart-ac64ea81-618b-4e00-a041-2963a2b722cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324584680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.324584680
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.678897934
Short name T658
Test name
Test status
Simulation time 27356576 ps
CPU time 1.09 seconds
Started Aug 07 06:55:22 PM PDT 24
Finished Aug 07 06:55:23 PM PDT 24
Peak memory 223724 kb
Host smart-147e0316-aa92-48ee-8be2-1482e0a73d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678897934 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.678897934
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.827741238
Short name T294
Test name
Test status
Simulation time 15436958 ps
CPU time 0.94 seconds
Started Aug 07 06:55:22 PM PDT 24
Finished Aug 07 06:55:23 PM PDT 24
Peak memory 206696 kb
Host smart-d02e4187-d83f-4153-80c5-6eaed41eb2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827741238 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.827741238
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.631088037
Short name T673
Test name
Test status
Simulation time 22315832 ps
CPU time 0.93 seconds
Started Aug 07 06:55:24 PM PDT 24
Finished Aug 07 06:55:25 PM PDT 24
Peak memory 214916 kb
Host smart-b0b8f4ee-1290-40b7-8192-d692aaac6468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631088037 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.631088037
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2219175021
Short name T336
Test name
Test status
Simulation time 172071633 ps
CPU time 3.59 seconds
Started Aug 07 06:55:24 PM PDT 24
Finished Aug 07 06:55:27 PM PDT 24
Peak memory 218268 kb
Host smart-3e0ce79c-0c45-4ff8-a31e-1ac44b2b040a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219175021 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2219175021
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2314482938
Short name T674
Test name
Test status
Simulation time 11912091580 ps
CPU time 303.25 seconds
Started Aug 07 06:55:27 PM PDT 24
Finished Aug 07 07:00:30 PM PDT 24
Peak memory 222756 kb
Host smart-ca949736-3911-440e-a0fe-0250a04a1ce6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314482938 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2314482938
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.204208112
Short name T808
Test name
Test status
Simulation time 30517590 ps
CPU time 1.25 seconds
Started Aug 07 06:56:23 PM PDT 24
Finished Aug 07 06:56:24 PM PDT 24
Peak memory 218268 kb
Host smart-2c0ec8ce-1e0d-47b8-83f4-5f9d511b9d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204208112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.204208112
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2065063371
Short name T62
Test name
Test status
Simulation time 39221745 ps
CPU time 1.05 seconds
Started Aug 07 06:56:25 PM PDT 24
Finished Aug 07 06:56:26 PM PDT 24
Peak memory 206400 kb
Host smart-d2494c34-5d1e-46f2-a510-5e984dc7ca68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065063371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2065063371
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3687946803
Short name T344
Test name
Test status
Simulation time 29765857 ps
CPU time 0.84 seconds
Started Aug 07 06:56:25 PM PDT 24
Finished Aug 07 06:56:26 PM PDT 24
Peak memory 215932 kb
Host smart-6c6040bc-4e01-4c25-9f3a-214568db0d29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687946803 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3687946803
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.742608472
Short name T111
Test name
Test status
Simulation time 57263268 ps
CPU time 1.21 seconds
Started Aug 07 06:56:24 PM PDT 24
Finished Aug 07 06:56:25 PM PDT 24
Peak memory 216920 kb
Host smart-4d067aad-a418-4a36-9aad-4071b16a6f33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742608472 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.742608472
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3447085271
Short name T798
Test name
Test status
Simulation time 35627137 ps
CPU time 1.02 seconds
Started Aug 07 06:56:25 PM PDT 24
Finished Aug 07 06:56:26 PM PDT 24
Peak memory 223668 kb
Host smart-04ee706a-882b-43f6-91a6-16564727011d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447085271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3447085271
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.838269805
Short name T302
Test name
Test status
Simulation time 108475024 ps
CPU time 1.02 seconds
Started Aug 07 06:56:24 PM PDT 24
Finished Aug 07 06:56:25 PM PDT 24
Peak memory 216836 kb
Host smart-fd35b1f2-322d-491d-9a99-e45df6503e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838269805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.838269805
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_smoke.1414858333
Short name T825
Test name
Test status
Simulation time 27571201 ps
CPU time 0.91 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 06:56:23 PM PDT 24
Peak memory 214908 kb
Host smart-0d178346-0b2c-4886-8769-748fe7ee5ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414858333 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1414858333
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.43065134
Short name T778
Test name
Test status
Simulation time 94553122 ps
CPU time 2.15 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 06:56:25 PM PDT 24
Peak memory 216952 kb
Host smart-3821f65e-0f81-4f6b-a944-25638eb18c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43065134 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.43065134
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.270133244
Short name T235
Test name
Test status
Simulation time 417398942823 ps
CPU time 1466.4 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 07:20:48 PM PDT 24
Peak memory 223956 kb
Host smart-577bff92-8e11-4f71-8a4f-9fdd239db01d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270133244 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.270133244
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3494877824
Short name T713
Test name
Test status
Simulation time 72211182 ps
CPU time 1.21 seconds
Started Aug 07 06:56:27 PM PDT 24
Finished Aug 07 06:56:28 PM PDT 24
Peak memory 218188 kb
Host smart-49a1bdab-f846-4587-9b4f-88b8bc3e8aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494877824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3494877824
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3370207281
Short name T63
Test name
Test status
Simulation time 15905944 ps
CPU time 0.94 seconds
Started Aug 07 06:56:27 PM PDT 24
Finished Aug 07 06:56:28 PM PDT 24
Peak memory 214724 kb
Host smart-58e201e2-34cf-4ed8-88d3-f504c7b328f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370207281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3370207281
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1685337194
Short name T908
Test name
Test status
Simulation time 19346218 ps
CPU time 0.85 seconds
Started Aug 07 06:56:27 PM PDT 24
Finished Aug 07 06:56:28 PM PDT 24
Peak memory 216236 kb
Host smart-f9fd6768-2255-47bd-a0d8-309aca8b2569
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685337194 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1685337194
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.434013655
Short name T174
Test name
Test status
Simulation time 20217840 ps
CPU time 1.04 seconds
Started Aug 07 06:56:29 PM PDT 24
Finished Aug 07 06:56:31 PM PDT 24
Peak memory 218412 kb
Host smart-67f8cc72-7f29-47f1-81b2-3ddff13a2382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434013655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.434013655
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.57138124
Short name T886
Test name
Test status
Simulation time 34525487 ps
CPU time 1.41 seconds
Started Aug 07 06:56:21 PM PDT 24
Finished Aug 07 06:56:22 PM PDT 24
Peak memory 217088 kb
Host smart-bbb553ef-e38f-4c68-92cb-f00adeac9e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57138124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.57138124
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1406574482
Short name T403
Test name
Test status
Simulation time 22240511 ps
CPU time 1.1 seconds
Started Aug 07 06:56:28 PM PDT 24
Finished Aug 07 06:56:29 PM PDT 24
Peak memory 214984 kb
Host smart-14323fa8-271f-497f-bfa9-dec45d3362ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406574482 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1406574482
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.410969869
Short name T110
Test name
Test status
Simulation time 32368593 ps
CPU time 0.89 seconds
Started Aug 07 06:56:23 PM PDT 24
Finished Aug 07 06:56:24 PM PDT 24
Peak memory 214912 kb
Host smart-fc3f56a0-fce0-4797-862f-0ea8adef4f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410969869 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.410969869
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3024012765
Short name T305
Test name
Test status
Simulation time 118755374 ps
CPU time 2.77 seconds
Started Aug 07 06:56:22 PM PDT 24
Finished Aug 07 06:56:25 PM PDT 24
Peak memory 216948 kb
Host smart-6b584316-450b-4f72-bbd9-e4487ffd7b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024012765 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3024012765
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3512330169
Short name T642
Test name
Test status
Simulation time 210114380712 ps
CPU time 435.79 seconds
Started Aug 07 06:56:23 PM PDT 24
Finished Aug 07 07:03:39 PM PDT 24
Peak memory 218388 kb
Host smart-9945484a-d417-4ff8-a10b-171c537a88e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512330169 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3512330169
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.835130547
Short name T29
Test name
Test status
Simulation time 361972867 ps
CPU time 1.31 seconds
Started Aug 07 06:56:28 PM PDT 24
Finished Aug 07 06:56:29 PM PDT 24
Peak memory 219324 kb
Host smart-335451ee-8c8f-4c70-9765-1f78b1e6b52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835130547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.835130547
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1399642402
Short name T725
Test name
Test status
Simulation time 17355052 ps
CPU time 0.8 seconds
Started Aug 07 06:56:31 PM PDT 24
Finished Aug 07 06:56:32 PM PDT 24
Peak memory 206416 kb
Host smart-baac3b8a-bde8-4dea-8bb7-fcbd6a196fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399642402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1399642402
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3949333820
Short name T200
Test name
Test status
Simulation time 10718533 ps
CPU time 0.87 seconds
Started Aug 07 06:56:29 PM PDT 24
Finished Aug 07 06:56:30 PM PDT 24
Peak memory 216216 kb
Host smart-02a4a563-33bb-45b8-9cc7-ead219a2a241
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949333820 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3949333820
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2651595108
Short name T926
Test name
Test status
Simulation time 31280634 ps
CPU time 1.08 seconds
Started Aug 07 06:56:31 PM PDT 24
Finished Aug 07 06:56:32 PM PDT 24
Peak memory 218056 kb
Host smart-d324d1c2-53f3-46f4-96ab-939e1980ca65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651595108 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2651595108
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.860759416
Short name T120
Test name
Test status
Simulation time 23341771 ps
CPU time 1.19 seconds
Started Aug 07 06:56:27 PM PDT 24
Finished Aug 07 06:56:29 PM PDT 24
Peak memory 219792 kb
Host smart-abf5494e-cbba-4423-aec7-b277d2426600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860759416 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.860759416
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3353817178
Short name T335
Test name
Test status
Simulation time 88249501 ps
CPU time 1.54 seconds
Started Aug 07 06:56:31 PM PDT 24
Finished Aug 07 06:56:33 PM PDT 24
Peak memory 217228 kb
Host smart-0d7a539a-54f3-4a7c-a9dd-74fe1efdc284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353817178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3353817178
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3364934921
Short name T104
Test name
Test status
Simulation time 33974313 ps
CPU time 0.92 seconds
Started Aug 07 06:56:31 PM PDT 24
Finished Aug 07 06:56:32 PM PDT 24
Peak memory 215476 kb
Host smart-e874c9ac-1319-4264-aa61-ff6e5cdc8646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364934921 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3364934921
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3795410690
Short name T862
Test name
Test status
Simulation time 18301320 ps
CPU time 0.96 seconds
Started Aug 07 06:56:28 PM PDT 24
Finished Aug 07 06:56:29 PM PDT 24
Peak memory 214868 kb
Host smart-e473088f-ebe8-4919-9fb9-010ef8262d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795410690 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3795410690
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.392809332
Short name T692
Test name
Test status
Simulation time 200172535 ps
CPU time 2.6 seconds
Started Aug 07 06:56:27 PM PDT 24
Finished Aug 07 06:56:29 PM PDT 24
Peak memory 214968 kb
Host smart-24bb31ec-c7e9-4c51-8609-f9df623cbfb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392809332 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.392809332
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.73546772
Short name T801
Test name
Test status
Simulation time 226708849237 ps
CPU time 2474.58 seconds
Started Aug 07 06:56:31 PM PDT 24
Finished Aug 07 07:37:46 PM PDT 24
Peak memory 230860 kb
Host smart-27428ced-ca1d-4b8a-8d1e-0f59f148e997
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73546772 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.73546772
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3042420329
Short name T933
Test name
Test status
Simulation time 85925005 ps
CPU time 1.15 seconds
Started Aug 07 06:56:34 PM PDT 24
Finished Aug 07 06:56:35 PM PDT 24
Peak memory 218824 kb
Host smart-fc738ddd-50b6-4926-92fc-e134705cbcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042420329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3042420329
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3883020189
Short name T409
Test name
Test status
Simulation time 70985539 ps
CPU time 0.96 seconds
Started Aug 07 06:56:33 PM PDT 24
Finished Aug 07 06:56:34 PM PDT 24
Peak memory 206404 kb
Host smart-91de13f9-7d3b-4221-b644-7bd3d50a2fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883020189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3883020189
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1545208056
Short name T788
Test name
Test status
Simulation time 30404408 ps
CPU time 0.85 seconds
Started Aug 07 06:56:33 PM PDT 24
Finished Aug 07 06:56:34 PM PDT 24
Peak memory 216200 kb
Host smart-0534b633-acc0-4578-8eb7-33a2872d042c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545208056 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1545208056
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2750985483
Short name T719
Test name
Test status
Simulation time 81892049 ps
CPU time 1.08 seconds
Started Aug 07 06:56:32 PM PDT 24
Finished Aug 07 06:56:33 PM PDT 24
Peak memory 219072 kb
Host smart-8e501e45-dd72-4972-91f3-b0c1da5df481
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750985483 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2750985483
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.266770398
Short name T957
Test name
Test status
Simulation time 111221785 ps
CPU time 1.29 seconds
Started Aug 07 06:56:34 PM PDT 24
Finished Aug 07 06:56:35 PM PDT 24
Peak memory 219500 kb
Host smart-8bfe913e-1d66-4401-9fcb-cfddf767f9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266770398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.266770398
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.356193798
Short name T750
Test name
Test status
Simulation time 153756313 ps
CPU time 1.5 seconds
Started Aug 07 06:56:31 PM PDT 24
Finished Aug 07 06:56:32 PM PDT 24
Peak memory 218376 kb
Host smart-2b797558-1f36-4a88-aa36-ba8dc583bc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356193798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.356193798
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2602492854
Short name T105
Test name
Test status
Simulation time 26813432 ps
CPU time 0.93 seconds
Started Aug 07 06:56:33 PM PDT 24
Finished Aug 07 06:56:34 PM PDT 24
Peak memory 215640 kb
Host smart-82078bda-97d9-4258-8c63-820884429416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602492854 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2602492854
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.729828677
Short name T424
Test name
Test status
Simulation time 21462678 ps
CPU time 0.95 seconds
Started Aug 07 06:56:28 PM PDT 24
Finished Aug 07 06:56:29 PM PDT 24
Peak memory 214900 kb
Host smart-da7af1a6-d059-4864-b415-f6469a143db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729828677 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.729828677
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.510062601
Short name T384
Test name
Test status
Simulation time 293014807 ps
CPU time 2.2 seconds
Started Aug 07 06:56:26 PM PDT 24
Finished Aug 07 06:56:28 PM PDT 24
Peak memory 216784 kb
Host smart-2c43f61b-6029-43e9-b101-58eef176a1d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510062601 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.510062601
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1851013737
Short name T823
Test name
Test status
Simulation time 74898106215 ps
CPU time 1878.41 seconds
Started Aug 07 06:56:30 PM PDT 24
Finished Aug 07 07:27:48 PM PDT 24
Peak memory 227692 kb
Host smart-7b2d8644-2e63-462b-8530-af0a838dbda0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851013737 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1851013737
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3804835921
Short name T669
Test name
Test status
Simulation time 73815324 ps
CPU time 1.16 seconds
Started Aug 07 06:56:33 PM PDT 24
Finished Aug 07 06:56:34 PM PDT 24
Peak memory 220388 kb
Host smart-55730479-95ae-47ae-8629-a0f99245ac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804835921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3804835921
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.295944586
Short name T66
Test name
Test status
Simulation time 73863055 ps
CPU time 1.04 seconds
Started Aug 07 06:56:35 PM PDT 24
Finished Aug 07 06:56:36 PM PDT 24
Peak memory 214764 kb
Host smart-42f1d576-8745-46bd-bc09-b2ef4b9a036c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295944586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.295944586
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3937716928
Short name T168
Test name
Test status
Simulation time 13775910 ps
CPU time 0.91 seconds
Started Aug 07 06:56:34 PM PDT 24
Finished Aug 07 06:56:35 PM PDT 24
Peak memory 216320 kb
Host smart-f285c8b6-6ba3-49cd-abb3-dadbf0d1da4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937716928 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3937716928
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3975407373
Short name T431
Test name
Test status
Simulation time 115373368 ps
CPU time 0.98 seconds
Started Aug 07 06:56:32 PM PDT 24
Finished Aug 07 06:56:33 PM PDT 24
Peak memory 219236 kb
Host smart-bedcd91b-06c0-42c8-9fbe-c919b991dd00
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975407373 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3975407373
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.599654706
Short name T876
Test name
Test status
Simulation time 47800273 ps
CPU time 1.14 seconds
Started Aug 07 06:56:34 PM PDT 24
Finished Aug 07 06:56:35 PM PDT 24
Peak memory 223712 kb
Host smart-b9695d34-ce84-49a0-8368-de565382c416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599654706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.599654706
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2912177322
Short name T42
Test name
Test status
Simulation time 198413615 ps
CPU time 1.26 seconds
Started Aug 07 06:56:35 PM PDT 24
Finished Aug 07 06:56:36 PM PDT 24
Peak memory 218856 kb
Host smart-6a6e7dd2-e65a-454e-9a10-6ac5c0674c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912177322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2912177322
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2476932479
Short name T71
Test name
Test status
Simulation time 23130981 ps
CPU time 1.13 seconds
Started Aug 07 06:56:33 PM PDT 24
Finished Aug 07 06:56:34 PM PDT 24
Peak memory 215140 kb
Host smart-ebb036e2-1a43-4324-8cea-bcb56359a9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476932479 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2476932479
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1620523314
Short name T770
Test name
Test status
Simulation time 41244184 ps
CPU time 0.86 seconds
Started Aug 07 06:56:32 PM PDT 24
Finished Aug 07 06:56:33 PM PDT 24
Peak memory 214892 kb
Host smart-cecd8b07-7058-40dd-a494-b73a2299fc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620523314 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1620523314
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.425212415
Short name T246
Test name
Test status
Simulation time 466034356 ps
CPU time 2.84 seconds
Started Aug 07 06:56:33 PM PDT 24
Finished Aug 07 06:56:36 PM PDT 24
Peak memory 214968 kb
Host smart-40f2c522-26cf-41ad-91b5-96b0c90130e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425212415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.425212415
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3697986094
Short name T223
Test name
Test status
Simulation time 65206908208 ps
CPU time 1127.82 seconds
Started Aug 07 06:56:32 PM PDT 24
Finished Aug 07 07:15:20 PM PDT 24
Peak memory 221864 kb
Host smart-dca8f047-f00f-40d0-b2d4-73467d5e4295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697986094 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3697986094
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.105650318
Short name T601
Test name
Test status
Simulation time 96549379 ps
CPU time 1.26 seconds
Started Aug 07 06:56:32 PM PDT 24
Finished Aug 07 06:56:33 PM PDT 24
Peak memory 219232 kb
Host smart-d7e25a0f-274d-48b3-a324-fbfefd3ffa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105650318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.105650318
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3175508809
Short name T340
Test name
Test status
Simulation time 46500432 ps
CPU time 0.88 seconds
Started Aug 07 06:56:32 PM PDT 24
Finished Aug 07 06:56:33 PM PDT 24
Peak memory 214728 kb
Host smart-7bb341b4-6512-40da-9fb1-2f03671900ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175508809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3175508809
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3114394328
Short name T208
Test name
Test status
Simulation time 35598008 ps
CPU time 0.82 seconds
Started Aug 07 06:56:33 PM PDT 24
Finished Aug 07 06:56:34 PM PDT 24
Peak memory 218936 kb
Host smart-e9573a1f-7dea-4ba2-bc9c-119831043b4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114394328 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3114394328
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.965668519
Short name T682
Test name
Test status
Simulation time 174890199 ps
CPU time 1.17 seconds
Started Aug 07 06:56:33 PM PDT 24
Finished Aug 07 06:56:35 PM PDT 24
Peak memory 219444 kb
Host smart-ba8ee170-3c7c-4e64-a223-efe435cfc484
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965668519 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.965668519
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3294520955
Short name T203
Test name
Test status
Simulation time 25301779 ps
CPU time 0.96 seconds
Started Aug 07 06:56:33 PM PDT 24
Finished Aug 07 06:56:34 PM PDT 24
Peak memory 218628 kb
Host smart-ddf59e1c-e0e5-42c6-ac2b-40133a011e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294520955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3294520955
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2066966275
Short name T318
Test name
Test status
Simulation time 73053943 ps
CPU time 1.6 seconds
Started Aug 07 06:56:34 PM PDT 24
Finished Aug 07 06:56:36 PM PDT 24
Peak memory 218448 kb
Host smart-dd0f7958-2b3e-47ff-af50-e91f1205e341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066966275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2066966275
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2703996829
Short name T871
Test name
Test status
Simulation time 39121252 ps
CPU time 0.91 seconds
Started Aug 07 06:56:33 PM PDT 24
Finished Aug 07 06:56:34 PM PDT 24
Peak memory 214928 kb
Host smart-30b0207f-774f-48d6-83a4-00c9305a8b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703996829 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2703996829
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.817936664
Short name T685
Test name
Test status
Simulation time 25297753 ps
CPU time 0.9 seconds
Started Aug 07 06:56:33 PM PDT 24
Finished Aug 07 06:56:34 PM PDT 24
Peak memory 214876 kb
Host smart-98111ba5-941e-4449-a691-ae745a7fc428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817936664 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.817936664
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.401270766
Short name T43
Test name
Test status
Simulation time 248698507 ps
CPU time 3.06 seconds
Started Aug 07 06:56:33 PM PDT 24
Finished Aug 07 06:56:36 PM PDT 24
Peak memory 214924 kb
Host smart-3faaf325-b36f-42b7-960a-f1f78a28dd35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401270766 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.401270766
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3183661791
Short name T332
Test name
Test status
Simulation time 53793623819 ps
CPU time 328.1 seconds
Started Aug 07 06:56:35 PM PDT 24
Finished Aug 07 07:02:03 PM PDT 24
Peak memory 218508 kb
Host smart-5ac978c3-1b9d-42fb-9ff6-27d9719042b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183661791 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3183661791
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert_test.3403484140
Short name T916
Test name
Test status
Simulation time 17455295 ps
CPU time 0.99 seconds
Started Aug 07 06:56:39 PM PDT 24
Finished Aug 07 06:56:40 PM PDT 24
Peak memory 206352 kb
Host smart-10a8fb04-c669-4be9-9360-7a08b3f07845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403484140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3403484140
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_err.3580595378
Short name T167
Test name
Test status
Simulation time 20517342 ps
CPU time 1.03 seconds
Started Aug 07 06:56:38 PM PDT 24
Finished Aug 07 06:56:39 PM PDT 24
Peak memory 218272 kb
Host smart-4e5a82cd-c1b8-407e-a779-4ab551801c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580595378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3580595378
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2248620735
Short name T349
Test name
Test status
Simulation time 124558887 ps
CPU time 2.68 seconds
Started Aug 07 06:56:38 PM PDT 24
Finished Aug 07 06:56:41 PM PDT 24
Peak memory 217100 kb
Host smart-d2f8943a-d0f6-46fc-a6b1-57c3fd77ee0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248620735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2248620735
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3091858853
Short name T508
Test name
Test status
Simulation time 25724700 ps
CPU time 0.98 seconds
Started Aug 07 06:56:39 PM PDT 24
Finished Aug 07 06:56:40 PM PDT 24
Peak memory 215164 kb
Host smart-46b3c04b-2dea-4590-9cb4-5a15e1e39619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091858853 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3091858853
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2006859075
Short name T585
Test name
Test status
Simulation time 58835616 ps
CPU time 0.94 seconds
Started Aug 07 06:56:39 PM PDT 24
Finished Aug 07 06:56:40 PM PDT 24
Peak memory 214912 kb
Host smart-d8969bde-d92b-4054-a984-647a235d8638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006859075 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2006859075
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3690906607
Short name T616
Test name
Test status
Simulation time 314456556 ps
CPU time 2.15 seconds
Started Aug 07 06:56:37 PM PDT 24
Finished Aug 07 06:56:39 PM PDT 24
Peak memory 219636 kb
Host smart-930d2085-ac65-4f67-82cb-0fc1ad3a5c17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690906607 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3690906607
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3618857983
Short name T954
Test name
Test status
Simulation time 266117592355 ps
CPU time 1548.72 seconds
Started Aug 07 06:56:38 PM PDT 24
Finished Aug 07 07:22:27 PM PDT 24
Peak memory 224964 kb
Host smart-3164474f-2c53-4baa-a847-a5da712bb162
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618857983 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3618857983
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.4129614209
Short name T411
Test name
Test status
Simulation time 91838107 ps
CPU time 1.11 seconds
Started Aug 07 06:56:37 PM PDT 24
Finished Aug 07 06:56:39 PM PDT 24
Peak memory 219936 kb
Host smart-143ad2ce-f588-4881-85a3-c67e5787f484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129614209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.4129614209
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2573845296
Short name T828
Test name
Test status
Simulation time 14978811 ps
CPU time 0.9 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 06:56:50 PM PDT 24
Peak memory 206292 kb
Host smart-e1ee284f-7256-4c1d-b8e2-6cde652ae4f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573845296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2573845296
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1927831144
Short name T218
Test name
Test status
Simulation time 11223151 ps
CPU time 0.88 seconds
Started Aug 07 06:56:43 PM PDT 24
Finished Aug 07 06:56:44 PM PDT 24
Peak memory 215132 kb
Host smart-47bab901-3a2f-4bab-afcc-2ec2555510a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927831144 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1927831144
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.956123504
Short name T744
Test name
Test status
Simulation time 100883762 ps
CPU time 1.16 seconds
Started Aug 07 06:56:42 PM PDT 24
Finished Aug 07 06:56:44 PM PDT 24
Peak memory 218056 kb
Host smart-2697cecb-4cc0-43aa-b47d-e8b36961f681
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956123504 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.956123504
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1848487427
Short name T896
Test name
Test status
Simulation time 20549406 ps
CPU time 0.97 seconds
Started Aug 07 06:56:39 PM PDT 24
Finished Aug 07 06:56:40 PM PDT 24
Peak memory 218620 kb
Host smart-28d06b8d-0ba2-4c95-8dea-e954671205b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848487427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1848487427
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.386400328
Short name T322
Test name
Test status
Simulation time 39964285 ps
CPU time 1.42 seconds
Started Aug 07 06:56:40 PM PDT 24
Finished Aug 07 06:56:41 PM PDT 24
Peak memory 216788 kb
Host smart-e219433c-4fa4-412f-b7dd-91a8204a6984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386400328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.386400328
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3137612976
Short name T715
Test name
Test status
Simulation time 23283010 ps
CPU time 0.95 seconds
Started Aug 07 06:56:39 PM PDT 24
Finished Aug 07 06:56:40 PM PDT 24
Peak memory 215516 kb
Host smart-aabf6c7d-39d8-4317-af1b-6e1a1a7e0379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137612976 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3137612976
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3042131436
Short name T382
Test name
Test status
Simulation time 41698529 ps
CPU time 0.88 seconds
Started Aug 07 06:56:39 PM PDT 24
Finished Aug 07 06:56:40 PM PDT 24
Peak memory 214908 kb
Host smart-390d698b-fcbe-4c90-8275-777c54fce4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042131436 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3042131436
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2364905663
Short name T966
Test name
Test status
Simulation time 363871074 ps
CPU time 2.28 seconds
Started Aug 07 06:56:38 PM PDT 24
Finished Aug 07 06:56:41 PM PDT 24
Peak memory 216940 kb
Host smart-72840c99-d1c3-4c0f-b190-456d9a5e2153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364905663 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2364905663
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.697578702
Short name T800
Test name
Test status
Simulation time 56177703437 ps
CPU time 1400.96 seconds
Started Aug 07 06:56:40 PM PDT 24
Finished Aug 07 07:20:01 PM PDT 24
Peak memory 224436 kb
Host smart-3900becd-e15b-4882-88fb-9a4bd0df4dca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697578702 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.697578702
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.584561723
Short name T552
Test name
Test status
Simulation time 40605203 ps
CPU time 1.19 seconds
Started Aug 07 06:56:52 PM PDT 24
Finished Aug 07 06:56:53 PM PDT 24
Peak memory 219400 kb
Host smart-a28726dd-c5bb-4a34-b2f3-26c508060b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584561723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.584561723
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3676966639
Short name T536
Test name
Test status
Simulation time 14709510 ps
CPU time 0.92 seconds
Started Aug 07 06:56:46 PM PDT 24
Finished Aug 07 06:56:47 PM PDT 24
Peak memory 206364 kb
Host smart-4967d496-1112-43b8-9dda-06f3c4d0755a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676966639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3676966639
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_err.190141353
Short name T190
Test name
Test status
Simulation time 29001222 ps
CPU time 0.91 seconds
Started Aug 07 06:56:44 PM PDT 24
Finished Aug 07 06:56:45 PM PDT 24
Peak memory 218412 kb
Host smart-175df3c2-c3c8-48ed-92b1-4b8c4de5f834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190141353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.190141353
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3468124115
Short name T374
Test name
Test status
Simulation time 51336789 ps
CPU time 1.95 seconds
Started Aug 07 06:56:45 PM PDT 24
Finished Aug 07 06:56:47 PM PDT 24
Peak memory 218224 kb
Host smart-659f932c-1b97-4961-9e50-968f767713c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468124115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3468124115
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.928999269
Short name T604
Test name
Test status
Simulation time 26861921 ps
CPU time 1.08 seconds
Started Aug 07 06:56:46 PM PDT 24
Finished Aug 07 06:56:47 PM PDT 24
Peak memory 215004 kb
Host smart-09538147-b17c-4fd2-9d7b-ede67951bab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928999269 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.928999269
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1962480718
Short name T510
Test name
Test status
Simulation time 29046331 ps
CPU time 0.94 seconds
Started Aug 07 06:56:45 PM PDT 24
Finished Aug 07 06:56:46 PM PDT 24
Peak memory 214860 kb
Host smart-52bb129c-84cb-4fa3-816e-ef8208d75bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962480718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1962480718
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2339122556
Short name T948
Test name
Test status
Simulation time 177713868 ps
CPU time 2.27 seconds
Started Aug 07 06:56:43 PM PDT 24
Finished Aug 07 06:56:46 PM PDT 24
Peak memory 216856 kb
Host smart-89241978-d45d-44b8-96bd-8c7fedae5947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339122556 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2339122556
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1159688844
Short name T233
Test name
Test status
Simulation time 118164701600 ps
CPU time 1197.35 seconds
Started Aug 07 06:56:43 PM PDT 24
Finished Aug 07 07:16:41 PM PDT 24
Peak memory 222520 kb
Host smart-dbed2ce4-bbfb-42a2-a7aa-c530315e0210
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159688844 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1159688844
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1261155046
Short name T938
Test name
Test status
Simulation time 66393455 ps
CPU time 1.23 seconds
Started Aug 07 06:56:52 PM PDT 24
Finished Aug 07 06:56:54 PM PDT 24
Peak memory 220908 kb
Host smart-fbef4014-6387-4410-bba8-3e3de43d8fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261155046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1261155046
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2871336359
Short name T615
Test name
Test status
Simulation time 50255391 ps
CPU time 0.95 seconds
Started Aug 07 06:56:43 PM PDT 24
Finished Aug 07 06:56:44 PM PDT 24
Peak memory 206380 kb
Host smart-8eb1cc0a-dd0d-475a-bf71-94d219f4dab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871336359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2871336359
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3461577475
Short name T843
Test name
Test status
Simulation time 22717005 ps
CPU time 0.86 seconds
Started Aug 07 06:56:45 PM PDT 24
Finished Aug 07 06:56:46 PM PDT 24
Peak memory 218904 kb
Host smart-4ba9eb80-bfd7-49a8-b40f-65e2756946d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461577475 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3461577475
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2701880506
Short name T275
Test name
Test status
Simulation time 76432333 ps
CPU time 1.01 seconds
Started Aug 07 06:56:48 PM PDT 24
Finished Aug 07 06:56:49 PM PDT 24
Peak memory 218216 kb
Host smart-50919c6e-aaea-47a7-8ff4-667486ca1ddd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701880506 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2701880506
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3702192564
Short name T49
Test name
Test status
Simulation time 31101670 ps
CPU time 1.06 seconds
Started Aug 07 06:56:52 PM PDT 24
Finished Aug 07 06:56:53 PM PDT 24
Peak memory 223936 kb
Host smart-856e448b-d7fd-4390-9aa0-4b4dfec12228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702192564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3702192564
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3898719076
Short name T780
Test name
Test status
Simulation time 33085397 ps
CPU time 1.04 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 06:56:50 PM PDT 24
Peak memory 216880 kb
Host smart-2daa8e12-f5d3-4b74-a326-3b66b84bbe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898719076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3898719076
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.640389155
Short name T985
Test name
Test status
Simulation time 25397075 ps
CPU time 1.13 seconds
Started Aug 07 06:56:51 PM PDT 24
Finished Aug 07 06:56:52 PM PDT 24
Peak memory 215332 kb
Host smart-298b1618-ded5-41d9-8c0e-b689ee7f5283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640389155 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.640389155
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1486973576
Short name T924
Test name
Test status
Simulation time 19874238 ps
CPU time 0.93 seconds
Started Aug 07 06:56:46 PM PDT 24
Finished Aug 07 06:56:47 PM PDT 24
Peak memory 214916 kb
Host smart-818ccee2-1207-480f-b18d-fb5837c07a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486973576 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1486973576
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.4131558200
Short name T940
Test name
Test status
Simulation time 694262101 ps
CPU time 2.11 seconds
Started Aug 07 06:56:44 PM PDT 24
Finished Aug 07 06:56:46 PM PDT 24
Peak memory 217080 kb
Host smart-8c8cfe09-a962-4571-b5bb-e50d61effffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131558200 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.4131558200
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3204008435
Short name T215
Test name
Test status
Simulation time 73184021974 ps
CPU time 1961.95 seconds
Started Aug 07 06:56:43 PM PDT 24
Finished Aug 07 07:29:25 PM PDT 24
Peak memory 226860 kb
Host smart-29defbf4-ac70-480e-a0e1-4a396db02e11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204008435 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3204008435
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert_test.1676326534
Short name T696
Test name
Test status
Simulation time 23075656 ps
CPU time 0.95 seconds
Started Aug 07 06:55:36 PM PDT 24
Finished Aug 07 06:55:37 PM PDT 24
Peak memory 214964 kb
Host smart-d449449e-63e4-4b7d-92cd-6b2e4221bb03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676326534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1676326534
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3929331800
Short name T169
Test name
Test status
Simulation time 16055018 ps
CPU time 0.87 seconds
Started Aug 07 06:55:26 PM PDT 24
Finished Aug 07 06:55:27 PM PDT 24
Peak memory 218000 kb
Host smart-afb3c410-723e-4278-894d-17119e440df5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929331800 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3929331800
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1174743963
Short name T67
Test name
Test status
Simulation time 93503039 ps
CPU time 0.97 seconds
Started Aug 07 06:55:26 PM PDT 24
Finished Aug 07 06:55:27 PM PDT 24
Peak memory 217896 kb
Host smart-3745b214-3d6f-49d4-8d7a-9952342ba8fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174743963 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1174743963
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.812982303
Short name T210
Test name
Test status
Simulation time 21900606 ps
CPU time 0.89 seconds
Started Aug 07 06:55:28 PM PDT 24
Finished Aug 07 06:55:29 PM PDT 24
Peak memory 219368 kb
Host smart-3bd8b8a4-1932-4792-9e30-ca67e616d54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812982303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.812982303
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.563967521
Short name T496
Test name
Test status
Simulation time 73779026 ps
CPU time 1.08 seconds
Started Aug 07 06:55:28 PM PDT 24
Finished Aug 07 06:55:29 PM PDT 24
Peak memory 218092 kb
Host smart-8702a13f-c26c-49cc-a2b6-219c3b370d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563967521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.563967521
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1165180980
Short name T986
Test name
Test status
Simulation time 27419469 ps
CPU time 1.13 seconds
Started Aug 07 06:55:26 PM PDT 24
Finished Aug 07 06:55:27 PM PDT 24
Peak memory 214960 kb
Host smart-6174d2d4-d652-4b84-876c-954e8988d4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165180980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1165180980
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1145205894
Short name T95
Test name
Test status
Simulation time 18827473 ps
CPU time 1.07 seconds
Started Aug 07 06:55:29 PM PDT 24
Finished Aug 07 06:55:30 PM PDT 24
Peak memory 206772 kb
Host smart-3a604bd8-0e07-4f3d-ac3b-7da6b8b0bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145205894 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1145205894
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.1587685569
Short name T433
Test name
Test status
Simulation time 51251988 ps
CPU time 0.93 seconds
Started Aug 07 06:55:26 PM PDT 24
Finished Aug 07 06:55:27 PM PDT 24
Peak memory 214888 kb
Host smart-7c4f27f2-4a5f-4e7b-b631-778b999d4be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587685569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1587685569
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1279458844
Short name T242
Test name
Test status
Simulation time 644701365 ps
CPU time 3.68 seconds
Started Aug 07 06:55:26 PM PDT 24
Finished Aug 07 06:55:30 PM PDT 24
Peak memory 216728 kb
Host smart-f646ee8d-3619-4f31-9c82-6c594c821abf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279458844 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1279458844
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1511846400
Short name T539
Test name
Test status
Simulation time 57950243545 ps
CPU time 1321.43 seconds
Started Aug 07 06:55:37 PM PDT 24
Finished Aug 07 07:17:39 PM PDT 24
Peak memory 223620 kb
Host smart-c7b2281c-6763-4f23-9724-982bbaa7d2b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511846400 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1511846400
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1312842428
Short name T494
Test name
Test status
Simulation time 32629024 ps
CPU time 1.31 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 06:56:51 PM PDT 24
Peak memory 215348 kb
Host smart-bc34526b-0462-45bc-af91-fa729c6ee50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312842428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1312842428
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1671387861
Short name T738
Test name
Test status
Simulation time 30060743 ps
CPU time 0.91 seconds
Started Aug 07 06:56:48 PM PDT 24
Finished Aug 07 06:56:49 PM PDT 24
Peak memory 214700 kb
Host smart-3d5c6c9a-5cad-43ba-9524-5e6af9844f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671387861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1671387861
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.97855396
Short name T981
Test name
Test status
Simulation time 24587322 ps
CPU time 0.82 seconds
Started Aug 07 06:56:53 PM PDT 24
Finished Aug 07 06:56:54 PM PDT 24
Peak memory 215932 kb
Host smart-489bbc11-0b39-45ed-82dd-7e170e90b562
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97855396 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.97855396
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3994127052
Short name T385
Test name
Test status
Simulation time 90728300 ps
CPU time 1.03 seconds
Started Aug 07 06:56:47 PM PDT 24
Finished Aug 07 06:56:48 PM PDT 24
Peak memory 219384 kb
Host smart-dc3cd824-0790-4113-9ef0-7bdde0fc3553
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994127052 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3994127052
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1849428766
Short name T51
Test name
Test status
Simulation time 47382067 ps
CPU time 1.09 seconds
Started Aug 07 06:56:48 PM PDT 24
Finished Aug 07 06:56:49 PM PDT 24
Peak memory 223720 kb
Host smart-2506a2b0-2648-4af8-818f-881843b73208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849428766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1849428766
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.4220718239
Short name T328
Test name
Test status
Simulation time 48060402 ps
CPU time 1.18 seconds
Started Aug 07 06:56:45 PM PDT 24
Finished Aug 07 06:56:47 PM PDT 24
Peak memory 217060 kb
Host smart-92e36497-86a9-4366-b532-a40ccbe0a5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220718239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4220718239
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_smoke.3584087857
Short name T760
Test name
Test status
Simulation time 18086300 ps
CPU time 1.01 seconds
Started Aug 07 06:56:43 PM PDT 24
Finished Aug 07 06:56:44 PM PDT 24
Peak memory 214848 kb
Host smart-c62ae58d-07ef-4201-b3dc-fd14c67874b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584087857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3584087857
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2887799250
Short name T976
Test name
Test status
Simulation time 264981172 ps
CPU time 3.07 seconds
Started Aug 07 06:56:44 PM PDT 24
Finished Aug 07 06:56:47 PM PDT 24
Peak memory 216804 kb
Host smart-78fa83d4-b0b7-42a7-9615-eb95b5247138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887799250 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2887799250
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2741508052
Short name T648
Test name
Test status
Simulation time 104355748736 ps
CPU time 616.64 seconds
Started Aug 07 06:56:45 PM PDT 24
Finished Aug 07 07:07:02 PM PDT 24
Peak memory 219260 kb
Host smart-ac8b1634-8433-45cd-afc3-2a686385307a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741508052 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2741508052
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1775837715
Short name T164
Test name
Test status
Simulation time 23893530 ps
CPU time 1.11 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 06:56:51 PM PDT 24
Peak memory 219144 kb
Host smart-b218c42d-1e98-4483-afce-40ea29b7d439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775837715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1775837715
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2420215997
Short name T527
Test name
Test status
Simulation time 50815789 ps
CPU time 0.83 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 06:56:50 PM PDT 24
Peak memory 214548 kb
Host smart-08f0057d-f209-4f98-9e4c-a5db3a86ace3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420215997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2420215997
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3605659889
Short name T945
Test name
Test status
Simulation time 54089750 ps
CPU time 1.09 seconds
Started Aug 07 06:56:48 PM PDT 24
Finished Aug 07 06:56:49 PM PDT 24
Peak memory 219428 kb
Host smart-9f0e8658-2c21-48a9-b394-93fcb120422a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605659889 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3605659889
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3667027270
Short name T166
Test name
Test status
Simulation time 20030278 ps
CPU time 1.06 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 06:56:50 PM PDT 24
Peak memory 218476 kb
Host smart-eb26f150-08d9-4f5f-9872-d057330cbd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667027270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3667027270
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2380120389
Short name T622
Test name
Test status
Simulation time 42283746 ps
CPU time 1.27 seconds
Started Aug 07 06:56:53 PM PDT 24
Finished Aug 07 06:56:54 PM PDT 24
Peak memory 218464 kb
Host smart-1ace42ac-3dd1-4cf8-b9fb-06c29db6ee24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380120389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2380120389
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1232571289
Short name T611
Test name
Test status
Simulation time 25478579 ps
CPU time 1.02 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 06:56:50 PM PDT 24
Peak memory 215152 kb
Host smart-7834e641-eef8-4aaa-b85a-b2d246776661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232571289 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1232571289
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.699292165
Short name T706
Test name
Test status
Simulation time 16998043 ps
CPU time 1.03 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 06:56:50 PM PDT 24
Peak memory 214920 kb
Host smart-0284ba58-cb95-42e8-8074-7819dec2eb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699292165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.699292165
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.275395466
Short name T279
Test name
Test status
Simulation time 288532391 ps
CPU time 3.26 seconds
Started Aug 07 06:56:57 PM PDT 24
Finished Aug 07 06:57:00 PM PDT 24
Peak memory 216800 kb
Host smart-0e55b147-ad28-447a-a050-9b5a042af128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275395466 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.275395466
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1598444856
Short name T229
Test name
Test status
Simulation time 428489942874 ps
CPU time 2460.34 seconds
Started Aug 07 06:56:47 PM PDT 24
Finished Aug 07 07:37:48 PM PDT 24
Peak memory 227120 kb
Host smart-60b9c80c-35ca-4c11-b606-0099d37da076
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598444856 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1598444856
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.4274253649
Short name T116
Test name
Test status
Simulation time 68089501 ps
CPU time 1.21 seconds
Started Aug 07 06:56:56 PM PDT 24
Finished Aug 07 06:56:58 PM PDT 24
Peak memory 218840 kb
Host smart-b5e9d94f-3ed4-49a1-99f0-4d0883376ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274253649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.4274253649
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3793550245
Short name T831
Test name
Test status
Simulation time 55017881 ps
CPU time 1.11 seconds
Started Aug 07 06:56:50 PM PDT 24
Finished Aug 07 06:56:51 PM PDT 24
Peak memory 214656 kb
Host smart-ed4a3775-29d4-4b8f-85ea-08a8cc0fde21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793550245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3793550245
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2216300768
Short name T69
Test name
Test status
Simulation time 14516871 ps
CPU time 0.92 seconds
Started Aug 07 06:56:57 PM PDT 24
Finished Aug 07 06:56:58 PM PDT 24
Peak memory 216288 kb
Host smart-9135133d-1b4d-444e-a83d-85ef9a84d0a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216300768 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2216300768
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.24387029
Short name T819
Test name
Test status
Simulation time 56119828 ps
CPU time 1.16 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 06:56:51 PM PDT 24
Peak memory 218092 kb
Host smart-cf0d1264-d9ce-48df-945f-91234936c1e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24387029 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_dis
able_auto_req_mode.24387029
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2947771671
Short name T193
Test name
Test status
Simulation time 32847862 ps
CPU time 1.19 seconds
Started Aug 07 06:56:53 PM PDT 24
Finished Aug 07 06:56:54 PM PDT 24
Peak memory 219524 kb
Host smart-650e1bf3-43ea-483d-abf0-6ac658280fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947771671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2947771671
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.4096570566
Short name T404
Test name
Test status
Simulation time 38515954 ps
CPU time 1.37 seconds
Started Aug 07 06:56:50 PM PDT 24
Finished Aug 07 06:56:52 PM PDT 24
Peak memory 217148 kb
Host smart-96b858a9-10bc-4320-8527-ca16179ea0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096570566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4096570566
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1096695068
Short name T717
Test name
Test status
Simulation time 32560973 ps
CPU time 1 seconds
Started Aug 07 06:56:48 PM PDT 24
Finished Aug 07 06:56:49 PM PDT 24
Peak memory 223816 kb
Host smart-afcf21a7-df70-4149-adcd-783853988fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096695068 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1096695068
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2326145987
Short name T751
Test name
Test status
Simulation time 47310591 ps
CPU time 0.92 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 06:56:50 PM PDT 24
Peak memory 214920 kb
Host smart-e1b7f5fb-6a0a-4062-be99-90188a22808c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326145987 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2326145987
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3263237591
Short name T583
Test name
Test status
Simulation time 112403654 ps
CPU time 2.65 seconds
Started Aug 07 06:56:51 PM PDT 24
Finished Aug 07 06:56:54 PM PDT 24
Peak memory 219800 kb
Host smart-0794f240-70e2-4a64-b5d5-2123a3fdb574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263237591 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3263237591
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.4271892123
Short name T227
Test name
Test status
Simulation time 63731804528 ps
CPU time 399.91 seconds
Started Aug 07 06:56:49 PM PDT 24
Finished Aug 07 07:03:29 PM PDT 24
Peak memory 218328 kb
Host smart-d6cfb9dc-f37d-4c27-bfaf-964dd188a19a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271892123 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.4271892123
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert_test.783172368
Short name T901
Test name
Test status
Simulation time 27163770 ps
CPU time 0.98 seconds
Started Aug 07 06:56:54 PM PDT 24
Finished Aug 07 06:56:55 PM PDT 24
Peak memory 206448 kb
Host smart-9cdecbf2-efc9-4781-91d7-688ef1c13663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783172368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.783172368
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2180355256
Short name T157
Test name
Test status
Simulation time 14196213 ps
CPU time 0.92 seconds
Started Aug 07 06:56:55 PM PDT 24
Finished Aug 07 06:56:56 PM PDT 24
Peak memory 215228 kb
Host smart-9dd0e464-ff91-4867-9d1f-d71e3220ad22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180355256 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2180355256
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3634817270
Short name T379
Test name
Test status
Simulation time 36146461 ps
CPU time 1.26 seconds
Started Aug 07 06:56:56 PM PDT 24
Finished Aug 07 06:56:58 PM PDT 24
Peak memory 218020 kb
Host smart-7def8abd-3a3b-4473-84f9-b1d3ab618248
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634817270 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3634817270
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.374988342
Short name T117
Test name
Test status
Simulation time 33717701 ps
CPU time 1.04 seconds
Started Aug 07 06:56:53 PM PDT 24
Finished Aug 07 06:56:55 PM PDT 24
Peak memory 219708 kb
Host smart-7f254ac0-10c7-4bec-bc48-060c88b5d7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374988342 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.374988342
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.545832115
Short name T629
Test name
Test status
Simulation time 29470311 ps
CPU time 1.25 seconds
Started Aug 07 06:56:53 PM PDT 24
Finished Aug 07 06:56:54 PM PDT 24
Peak memory 214980 kb
Host smart-0db0e189-7efa-472c-bf09-8cba52a4383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545832115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.545832115
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3270812153
Short name T535
Test name
Test status
Simulation time 32365633 ps
CPU time 0.9 seconds
Started Aug 07 06:56:56 PM PDT 24
Finished Aug 07 06:56:57 PM PDT 24
Peak memory 215156 kb
Host smart-84e9d767-247c-4691-8bd0-ababfbb6ffb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270812153 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3270812153
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.728706846
Short name T436
Test name
Test status
Simulation time 137015491 ps
CPU time 0.93 seconds
Started Aug 07 06:56:50 PM PDT 24
Finished Aug 07 06:56:51 PM PDT 24
Peak memory 214904 kb
Host smart-ecc03b9f-2e3e-4a75-b31e-336fe050074b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728706846 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.728706846
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.4184360734
Short name T773
Test name
Test status
Simulation time 237736065 ps
CPU time 1.66 seconds
Started Aug 07 06:56:55 PM PDT 24
Finished Aug 07 06:56:56 PM PDT 24
Peak memory 219596 kb
Host smart-71043709-d005-441f-9b47-d1aae03cc1ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184360734 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.4184360734
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3707257457
Short name T327
Test name
Test status
Simulation time 39690597948 ps
CPU time 472.78 seconds
Started Aug 07 06:56:57 PM PDT 24
Finished Aug 07 07:04:50 PM PDT 24
Peak memory 223328 kb
Host smart-ee8be942-c35e-4d00-be2e-eb54a3930677
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707257457 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3707257457
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3202851632
Short name T844
Test name
Test status
Simulation time 51883521 ps
CPU time 1.19 seconds
Started Aug 07 06:56:52 PM PDT 24
Finished Aug 07 06:56:53 PM PDT 24
Peak memory 219524 kb
Host smart-61aa2156-60e1-4173-a9de-1926378c3158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202851632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3202851632
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3948996374
Short name T599
Test name
Test status
Simulation time 43538260 ps
CPU time 0.87 seconds
Started Aug 07 06:56:57 PM PDT 24
Finished Aug 07 06:56:58 PM PDT 24
Peak memory 206356 kb
Host smart-4d789c1d-4e50-4f99-b97f-513eedd59d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948996374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3948996374
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.771186759
Short name T695
Test name
Test status
Simulation time 12439149 ps
CPU time 0.92 seconds
Started Aug 07 06:56:53 PM PDT 24
Finished Aug 07 06:56:54 PM PDT 24
Peak memory 215912 kb
Host smart-7b2be9f2-9846-42aa-afee-6fdd049dbf48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771186759 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.771186759
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2643600660
Short name T151
Test name
Test status
Simulation time 66467416 ps
CPU time 1 seconds
Started Aug 07 06:56:55 PM PDT 24
Finished Aug 07 06:56:56 PM PDT 24
Peak memory 219140 kb
Host smart-f1007aab-fead-4594-924b-826523f69250
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643600660 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2643600660
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1792156164
Short name T187
Test name
Test status
Simulation time 19997803 ps
CPU time 1.14 seconds
Started Aug 07 06:56:55 PM PDT 24
Finished Aug 07 06:56:57 PM PDT 24
Peak memory 223792 kb
Host smart-52cdfbee-dba6-4f76-b3d6-5832b31b7050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792156164 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1792156164
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.536585573
Short name T248
Test name
Test status
Simulation time 69522673 ps
CPU time 1.08 seconds
Started Aug 07 06:56:55 PM PDT 24
Finished Aug 07 06:56:56 PM PDT 24
Peak memory 217224 kb
Host smart-214a0117-f65d-4840-b0d6-bc1fe75c07e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536585573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.536585573
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1435830612
Short name T106
Test name
Test status
Simulation time 26552092 ps
CPU time 0.88 seconds
Started Aug 07 06:56:54 PM PDT 24
Finished Aug 07 06:56:55 PM PDT 24
Peak memory 215536 kb
Host smart-00149cb2-dee8-4c67-9c81-03319cafbac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435830612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1435830612
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3029789428
Short name T380
Test name
Test status
Simulation time 82572641 ps
CPU time 0.94 seconds
Started Aug 07 06:56:55 PM PDT 24
Finished Aug 07 06:56:56 PM PDT 24
Peak memory 214916 kb
Host smart-ae87f545-674d-48e0-ab19-756dc89dc5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029789428 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3029789428
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1016442552
Short name T810
Test name
Test status
Simulation time 323138522 ps
CPU time 2.4 seconds
Started Aug 07 06:56:57 PM PDT 24
Finished Aug 07 06:57:00 PM PDT 24
Peak memory 214884 kb
Host smart-d0cc32dc-22e0-4fc2-9687-cc5535197699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016442552 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1016442552
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1766364038
Short name T237
Test name
Test status
Simulation time 44150600078 ps
CPU time 735.88 seconds
Started Aug 07 06:56:55 PM PDT 24
Finished Aug 07 07:09:12 PM PDT 24
Peak memory 221148 kb
Host smart-ebe06861-2e3e-4093-b8a7-07ddf516f28d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766364038 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1766364038
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1205958632
Short name T425
Test name
Test status
Simulation time 26104405 ps
CPU time 1.17 seconds
Started Aug 07 06:56:59 PM PDT 24
Finished Aug 07 06:57:00 PM PDT 24
Peak memory 219484 kb
Host smart-ed32da16-8543-479f-9bbe-05af9f16b61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205958632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1205958632
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1366213618
Short name T636
Test name
Test status
Simulation time 32690716 ps
CPU time 0.84 seconds
Started Aug 07 06:57:00 PM PDT 24
Finished Aug 07 06:57:01 PM PDT 24
Peak memory 206192 kb
Host smart-23e47847-62dc-410f-957f-883758918b08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366213618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1366213618
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1454004060
Short name T589
Test name
Test status
Simulation time 11654358 ps
CPU time 0.89 seconds
Started Aug 07 06:57:01 PM PDT 24
Finished Aug 07 06:57:02 PM PDT 24
Peak memory 218940 kb
Host smart-a313cf60-fcb9-40a0-a33a-a5300d78124a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454004060 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1454004060
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2230470729
Short name T538
Test name
Test status
Simulation time 82943661 ps
CPU time 0.95 seconds
Started Aug 07 06:57:00 PM PDT 24
Finished Aug 07 06:57:01 PM PDT 24
Peak memory 217916 kb
Host smart-a001aefe-9807-4355-8ef5-a220bdd1f6c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230470729 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2230470729
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2217095421
Short name T865
Test name
Test status
Simulation time 20659007 ps
CPU time 1.15 seconds
Started Aug 07 06:57:00 PM PDT 24
Finished Aug 07 06:57:01 PM PDT 24
Peak memory 219920 kb
Host smart-e93f2c07-ba62-4f82-a89f-f0c4e048b857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217095421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2217095421
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3517341921
Short name T338
Test name
Test status
Simulation time 64617394 ps
CPU time 1.01 seconds
Started Aug 07 06:56:57 PM PDT 24
Finished Aug 07 06:56:59 PM PDT 24
Peak memory 216924 kb
Host smart-a3fb3aea-f7ab-4670-979e-fcdabeded110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517341921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3517341921
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2165708272
Short name T640
Test name
Test status
Simulation time 22050540 ps
CPU time 1.14 seconds
Started Aug 07 06:56:55 PM PDT 24
Finished Aug 07 06:56:56 PM PDT 24
Peak memory 214996 kb
Host smart-d5c815b8-4974-449a-8c8c-8789f8ec9bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165708272 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2165708272
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1125736527
Short name T487
Test name
Test status
Simulation time 23263038 ps
CPU time 0.91 seconds
Started Aug 07 06:56:56 PM PDT 24
Finished Aug 07 06:56:57 PM PDT 24
Peak memory 214932 kb
Host smart-dcfe4198-5066-4cf8-9e25-4ba6cfbe1e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125736527 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1125736527
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1381878784
Short name T280
Test name
Test status
Simulation time 601356996 ps
CPU time 6.08 seconds
Started Aug 07 06:56:55 PM PDT 24
Finished Aug 07 06:57:01 PM PDT 24
Peak memory 217008 kb
Host smart-58f02d58-b4d8-4bab-9264-d1ea91c32e8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381878784 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1381878784
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3054516126
Short name T230
Test name
Test status
Simulation time 93582853272 ps
CPU time 2012.5 seconds
Started Aug 07 06:56:57 PM PDT 24
Finished Aug 07 07:30:30 PM PDT 24
Peak memory 225512 kb
Host smart-51cd6019-1288-4e31-aec7-a3f2fbc64047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054516126 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3054516126
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.202673742
Short name T251
Test name
Test status
Simulation time 99031160 ps
CPU time 1.25 seconds
Started Aug 07 06:56:59 PM PDT 24
Finished Aug 07 06:57:00 PM PDT 24
Peak memory 218936 kb
Host smart-6e134ad0-f0fc-49d7-9ac8-1d6e8916f1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202673742 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.202673742
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2604187662
Short name T726
Test name
Test status
Simulation time 101404695 ps
CPU time 1.13 seconds
Started Aug 07 06:57:00 PM PDT 24
Finished Aug 07 06:57:01 PM PDT 24
Peak memory 206344 kb
Host smart-ddf0dee7-9e63-4bfd-be8a-853295418af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604187662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2604187662
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.462333582
Short name T909
Test name
Test status
Simulation time 64532687 ps
CPU time 0.83 seconds
Started Aug 07 06:56:59 PM PDT 24
Finished Aug 07 06:57:00 PM PDT 24
Peak memory 215140 kb
Host smart-99607e53-f38a-43c9-8840-40483f43c669
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462333582 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.462333582
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.208802744
Short name T152
Test name
Test status
Simulation time 358025687 ps
CPU time 1.11 seconds
Started Aug 07 06:56:58 PM PDT 24
Finished Aug 07 06:56:59 PM PDT 24
Peak memory 219128 kb
Host smart-b9a3338c-a705-4bef-925b-74f64746115e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208802744 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.208802744
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1643484920
Short name T216
Test name
Test status
Simulation time 34768735 ps
CPU time 0.94 seconds
Started Aug 07 06:56:59 PM PDT 24
Finished Aug 07 06:57:00 PM PDT 24
Peak memory 219880 kb
Host smart-a496ea20-b49b-442a-8584-0ba170205518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643484920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1643484920
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.4107665114
Short name T779
Test name
Test status
Simulation time 34063463 ps
CPU time 1.09 seconds
Started Aug 07 06:56:58 PM PDT 24
Finished Aug 07 06:56:59 PM PDT 24
Peak memory 217016 kb
Host smart-b793af83-0fcf-48d9-be10-a2344685a778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107665114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.4107665114
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.876695078
Short name T918
Test name
Test status
Simulation time 56274185 ps
CPU time 0.82 seconds
Started Aug 07 06:57:01 PM PDT 24
Finished Aug 07 06:57:02 PM PDT 24
Peak memory 215064 kb
Host smart-8ac9aeae-8288-4de3-a288-c9f980a371f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876695078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.876695078
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.866546985
Short name T476
Test name
Test status
Simulation time 19473438 ps
CPU time 1.03 seconds
Started Aug 07 06:57:00 PM PDT 24
Finished Aug 07 06:57:01 PM PDT 24
Peak memory 214952 kb
Host smart-3b22649a-9051-4a0a-aaab-ce31bdd27454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866546985 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.866546985
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.4024101877
Short name T664
Test name
Test status
Simulation time 470063813 ps
CPU time 5.81 seconds
Started Aug 07 06:57:03 PM PDT 24
Finished Aug 07 06:57:09 PM PDT 24
Peak memory 219612 kb
Host smart-47f1127b-7c20-4177-8f32-79d331ca0da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024101877 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.4024101877
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3784594438
Short name T477
Test name
Test status
Simulation time 58297389766 ps
CPU time 613.42 seconds
Started Aug 07 06:56:59 PM PDT 24
Finished Aug 07 07:07:12 PM PDT 24
Peak memory 223420 kb
Host smart-960ddef2-9ff3-4fbd-8867-6a34343cc3ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784594438 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3784594438
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1681388954
Short name T426
Test name
Test status
Simulation time 67941874 ps
CPU time 1.09 seconds
Started Aug 07 06:57:00 PM PDT 24
Finished Aug 07 06:57:01 PM PDT 24
Peak memory 218624 kb
Host smart-0f5233f4-ace5-4238-b9a6-3074c39919e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681388954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1681388954
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3876204255
Short name T365
Test name
Test status
Simulation time 20649966 ps
CPU time 1.02 seconds
Started Aug 07 06:57:01 PM PDT 24
Finished Aug 07 06:57:02 PM PDT 24
Peak memory 206400 kb
Host smart-f99e4e1d-b475-402a-b98e-b823644d0bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876204255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3876204255
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1636003403
Short name T132
Test name
Test status
Simulation time 82282849 ps
CPU time 1.05 seconds
Started Aug 07 06:56:58 PM PDT 24
Finished Aug 07 06:56:59 PM PDT 24
Peak memory 219104 kb
Host smart-7f1c54da-5727-4eef-b659-543f75adf28b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636003403 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1636003403
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1811420560
Short name T4
Test name
Test status
Simulation time 24446893 ps
CPU time 1.15 seconds
Started Aug 07 06:56:59 PM PDT 24
Finished Aug 07 06:57:00 PM PDT 24
Peak memory 220396 kb
Host smart-a08f0551-af36-4f35-b847-ccfb71d902eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811420560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1811420560
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2137697544
Short name T524
Test name
Test status
Simulation time 38547335 ps
CPU time 1.45 seconds
Started Aug 07 06:57:01 PM PDT 24
Finished Aug 07 06:57:02 PM PDT 24
Peak memory 218140 kb
Host smart-df6d62e6-dd1f-4a7a-a8cc-5d6f20ed7b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137697544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2137697544
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1356469742
Short name T97
Test name
Test status
Simulation time 24571711 ps
CPU time 0.97 seconds
Started Aug 07 06:57:01 PM PDT 24
Finished Aug 07 06:57:02 PM PDT 24
Peak memory 215696 kb
Host smart-d228b195-bb3a-4e2c-8e72-20b9b5ccf607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356469742 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1356469742
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3941672494
Short name T347
Test name
Test status
Simulation time 47239622 ps
CPU time 0.95 seconds
Started Aug 07 06:56:59 PM PDT 24
Finished Aug 07 06:57:00 PM PDT 24
Peak memory 214916 kb
Host smart-0687605f-6817-40d4-9d6e-346b56371eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941672494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3941672494
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1332315109
Short name T389
Test name
Test status
Simulation time 457603942 ps
CPU time 2.97 seconds
Started Aug 07 06:56:59 PM PDT 24
Finished Aug 07 06:57:02 PM PDT 24
Peak memory 217040 kb
Host smart-c169e03a-e9ff-48a2-9aae-f815e4e5a497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332315109 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1332315109
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.558314001
Short name T224
Test name
Test status
Simulation time 62281014456 ps
CPU time 1421.66 seconds
Started Aug 07 06:56:59 PM PDT 24
Finished Aug 07 07:20:41 PM PDT 24
Peak memory 222336 kb
Host smart-b90fb960-1ce6-4a88-8ba1-b3082da7d4b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558314001 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.558314001
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.12846434
Short name T975
Test name
Test status
Simulation time 70771661 ps
CPU time 1.18 seconds
Started Aug 07 06:57:05 PM PDT 24
Finished Aug 07 06:57:06 PM PDT 24
Peak memory 218048 kb
Host smart-6783b683-99d9-42eb-bfda-1f014147a7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12846434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.12846434
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1746097628
Short name T827
Test name
Test status
Simulation time 46290227 ps
CPU time 0.94 seconds
Started Aug 07 06:57:04 PM PDT 24
Finished Aug 07 06:57:05 PM PDT 24
Peak memory 206596 kb
Host smart-9521485c-8c6d-4af7-bf7f-4eea1c5ccbed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746097628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1746097628
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1597964769
Short name T90
Test name
Test status
Simulation time 11333869 ps
CPU time 0.9 seconds
Started Aug 07 06:57:09 PM PDT 24
Finished Aug 07 06:57:10 PM PDT 24
Peak memory 215920 kb
Host smart-bb520904-ce54-4204-b941-0264d79d7ba1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597964769 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1597964769
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3694498276
Short name T125
Test name
Test status
Simulation time 44120291 ps
CPU time 1.47 seconds
Started Aug 07 06:57:08 PM PDT 24
Finished Aug 07 06:57:10 PM PDT 24
Peak memory 216820 kb
Host smart-8f53e522-322f-4cdd-82b0-17741371103a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694498276 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3694498276
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2244118275
Short name T847
Test name
Test status
Simulation time 24908152 ps
CPU time 1.08 seconds
Started Aug 07 06:57:05 PM PDT 24
Finished Aug 07 06:57:07 PM PDT 24
Peak memory 218468 kb
Host smart-b3aaa634-19d9-4d27-aed1-cc849ee7b64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244118275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2244118275
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1200487440
Short name T247
Test name
Test status
Simulation time 45004032 ps
CPU time 1.67 seconds
Started Aug 07 06:56:59 PM PDT 24
Finished Aug 07 06:57:01 PM PDT 24
Peak memory 218216 kb
Host smart-46788e65-8fb5-43ed-86bb-ac49e09c3602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200487440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1200487440
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.456699679
Short name T196
Test name
Test status
Simulation time 40912361 ps
CPU time 0.85 seconds
Started Aug 07 06:57:10 PM PDT 24
Finished Aug 07 06:57:11 PM PDT 24
Peak memory 214932 kb
Host smart-d26e9a3f-6464-4610-b6d4-e805a464d589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456699679 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.456699679
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2406647016
Short name T44
Test name
Test status
Simulation time 30014155 ps
CPU time 0.96 seconds
Started Aug 07 06:57:00 PM PDT 24
Finished Aug 07 06:57:01 PM PDT 24
Peak memory 214924 kb
Host smart-04ab0ce8-e7ed-48df-ad70-fba4148d40db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406647016 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2406647016
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3746145603
Short name T961
Test name
Test status
Simulation time 143137751 ps
CPU time 2.35 seconds
Started Aug 07 06:56:58 PM PDT 24
Finished Aug 07 06:57:00 PM PDT 24
Peak memory 216660 kb
Host smart-d429f834-a0c0-4ecf-ba4e-1122352e39f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746145603 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3746145603
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2078038949
Short name T932
Test name
Test status
Simulation time 64427337140 ps
CPU time 763.71 seconds
Started Aug 07 06:57:05 PM PDT 24
Finished Aug 07 07:09:49 PM PDT 24
Peak memory 218752 kb
Host smart-f6d5013a-28b6-4d6a-b3c4-ac8e13a186a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078038949 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2078038949
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1280367002
Short name T594
Test name
Test status
Simulation time 43788214 ps
CPU time 1.16 seconds
Started Aug 07 06:57:03 PM PDT 24
Finished Aug 07 06:57:04 PM PDT 24
Peak memory 218280 kb
Host smart-ad33b3a5-b8db-4214-9940-2f672add38ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280367002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1280367002
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2883562558
Short name T572
Test name
Test status
Simulation time 59959202 ps
CPU time 0.84 seconds
Started Aug 07 06:57:07 PM PDT 24
Finished Aug 07 06:57:08 PM PDT 24
Peak memory 206344 kb
Host smart-ad68930c-55ac-443e-9805-12a437a8d5b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883562558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2883562558
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.333638309
Short name T928
Test name
Test status
Simulation time 17480347 ps
CPU time 0.87 seconds
Started Aug 07 06:57:06 PM PDT 24
Finished Aug 07 06:57:07 PM PDT 24
Peak memory 216232 kb
Host smart-31e2a7cf-5b65-41c3-b9c6-e75fe14a406e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333638309 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.333638309
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.507098998
Short name T653
Test name
Test status
Simulation time 38650907 ps
CPU time 1.32 seconds
Started Aug 07 06:57:05 PM PDT 24
Finished Aug 07 06:57:06 PM PDT 24
Peak memory 216872 kb
Host smart-61a8bcf2-f4cc-4393-b827-448ae03862f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507098998 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.507098998
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.186525526
Short name T885
Test name
Test status
Simulation time 23299133 ps
CPU time 1.08 seconds
Started Aug 07 06:57:06 PM PDT 24
Finished Aug 07 06:57:08 PM PDT 24
Peak memory 223716 kb
Host smart-bc3007ac-c734-41f0-a763-a99ae785c5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186525526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.186525526
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2702302227
Short name T464
Test name
Test status
Simulation time 58180746 ps
CPU time 1.49 seconds
Started Aug 07 06:57:03 PM PDT 24
Finished Aug 07 06:57:04 PM PDT 24
Peak memory 217020 kb
Host smart-bc990529-e9a2-478e-a5d6-dcf0a533d903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702302227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2702302227
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3920761117
Short name T525
Test name
Test status
Simulation time 95681416 ps
CPU time 1 seconds
Started Aug 07 06:57:06 PM PDT 24
Finished Aug 07 06:57:07 PM PDT 24
Peak memory 223656 kb
Host smart-3d214d6d-23f3-472d-beeb-9684462e68d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920761117 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3920761117
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2641122192
Short name T911
Test name
Test status
Simulation time 48056778 ps
CPU time 0.91 seconds
Started Aug 07 06:57:04 PM PDT 24
Finished Aug 07 06:57:05 PM PDT 24
Peak memory 214932 kb
Host smart-243d6d34-5d2b-4ec9-86aa-1890ad69b13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641122192 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2641122192
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3164292724
Short name T55
Test name
Test status
Simulation time 409354107 ps
CPU time 2.94 seconds
Started Aug 07 06:57:09 PM PDT 24
Finished Aug 07 06:57:12 PM PDT 24
Peak memory 215004 kb
Host smart-07ed82fe-46ac-4a55-8afa-ab7855d9784e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164292724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3164292724
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3464068851
Short name T728
Test name
Test status
Simulation time 389918187352 ps
CPU time 652.35 seconds
Started Aug 07 06:57:06 PM PDT 24
Finished Aug 07 07:07:59 PM PDT 24
Peak memory 219268 kb
Host smart-0df7bd38-b7f0-4d93-be87-f8fc294a31c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464068851 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3464068851
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert_test.3258391063
Short name T634
Test name
Test status
Simulation time 37302732 ps
CPU time 0.84 seconds
Started Aug 07 06:55:31 PM PDT 24
Finished Aug 07 06:55:32 PM PDT 24
Peak memory 206272 kb
Host smart-1f8253d2-e1ef-4979-a128-7e96c33e9452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258391063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3258391063
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3983656681
Short name T147
Test name
Test status
Simulation time 208154552 ps
CPU time 1.16 seconds
Started Aug 07 06:55:28 PM PDT 24
Finished Aug 07 06:55:29 PM PDT 24
Peak memory 219144 kb
Host smart-91beafc9-1b8e-4185-83f6-173559427cf4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983656681 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3983656681
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3388820337
Short name T175
Test name
Test status
Simulation time 19161756 ps
CPU time 1.05 seconds
Started Aug 07 06:55:28 PM PDT 24
Finished Aug 07 06:55:29 PM PDT 24
Peak memory 218524 kb
Host smart-e971b40e-1dfa-471a-b0e5-46b65e5d0a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388820337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3388820337
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1680996427
Short name T880
Test name
Test status
Simulation time 22166284 ps
CPU time 1.11 seconds
Started Aug 07 06:55:37 PM PDT 24
Finished Aug 07 06:55:38 PM PDT 24
Peak memory 217168 kb
Host smart-d6b31413-3779-4234-a687-6d964aa78fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680996427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1680996427
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2925865702
Short name T20
Test name
Test status
Simulation time 20798092 ps
CPU time 1.13 seconds
Started Aug 07 06:55:36 PM PDT 24
Finished Aug 07 06:55:37 PM PDT 24
Peak memory 215328 kb
Host smart-0332e4ba-5554-4b51-afd6-4e3536040356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925865702 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2925865702
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1048325257
Short name T613
Test name
Test status
Simulation time 32324008 ps
CPU time 0.98 seconds
Started Aug 07 06:55:28 PM PDT 24
Finished Aug 07 06:55:29 PM PDT 24
Peak memory 206696 kb
Host smart-e0a13efa-1589-403d-919c-6739aadbb2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048325257 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1048325257
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.838218599
Short name T383
Test name
Test status
Simulation time 25575265 ps
CPU time 0.94 seconds
Started Aug 07 06:55:26 PM PDT 24
Finished Aug 07 06:55:27 PM PDT 24
Peak memory 214912 kb
Host smart-911e771c-0313-4144-94a8-76b20c0a7f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838218599 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.838218599
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2912430345
Short name T587
Test name
Test status
Simulation time 432396312 ps
CPU time 3.44 seconds
Started Aug 07 06:55:27 PM PDT 24
Finished Aug 07 06:55:30 PM PDT 24
Peak memory 214944 kb
Host smart-13c53897-b0b2-4c90-b120-6a8fe683ba9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912430345 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2912430345
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2469175797
Short name T888
Test name
Test status
Simulation time 54054598444 ps
CPU time 750.29 seconds
Started Aug 07 06:55:26 PM PDT 24
Finished Aug 07 07:07:57 PM PDT 24
Peak memory 218692 kb
Host smart-434eca02-02d7-4a1a-b735-94e8e4bf1191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469175797 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2469175797
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.3752453299
Short name T451
Test name
Test status
Simulation time 69510998 ps
CPU time 1.06 seconds
Started Aug 07 06:57:08 PM PDT 24
Finished Aug 07 06:57:09 PM PDT 24
Peak memory 219560 kb
Host smart-4f1e5a76-1fc2-4665-97ef-198631a1f4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752453299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.3752453299
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.550657466
Short name T579
Test name
Test status
Simulation time 38909094 ps
CPU time 1.16 seconds
Started Aug 07 06:57:09 PM PDT 24
Finished Aug 07 06:57:11 PM PDT 24
Peak memory 231952 kb
Host smart-6b0404b5-e9ed-43ab-a9c5-d25bdcbe72a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550657466 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.550657466
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3533052252
Short name T593
Test name
Test status
Simulation time 164602302 ps
CPU time 1.4 seconds
Started Aug 07 06:57:10 PM PDT 24
Finished Aug 07 06:57:11 PM PDT 24
Peak memory 217124 kb
Host smart-28c2819e-e1d0-4d9d-aa6b-60985980b8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533052252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3533052252
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2023914911
Short name T614
Test name
Test status
Simulation time 89575433 ps
CPU time 1.34 seconds
Started Aug 07 06:57:10 PM PDT 24
Finished Aug 07 06:57:11 PM PDT 24
Peak memory 215292 kb
Host smart-22764153-fab1-4917-b3b5-7d1bd5c24547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023914911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2023914911
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.4278372844
Short name T941
Test name
Test status
Simulation time 30950714 ps
CPU time 0.95 seconds
Started Aug 07 06:57:13 PM PDT 24
Finished Aug 07 06:57:14 PM PDT 24
Peak memory 223640 kb
Host smart-c96b6a40-0cf7-4ea0-bda4-49eb558f4a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278372844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.4278372844
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.845065496
Short name T608
Test name
Test status
Simulation time 56257916 ps
CPU time 1.82 seconds
Started Aug 07 06:57:11 PM PDT 24
Finished Aug 07 06:57:13 PM PDT 24
Peak memory 217064 kb
Host smart-3fdc1b38-04c1-472b-a12d-41b1114c5ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845065496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.845065496
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1461381225
Short name T173
Test name
Test status
Simulation time 25892583 ps
CPU time 1.19 seconds
Started Aug 07 06:57:11 PM PDT 24
Finished Aug 07 06:57:12 PM PDT 24
Peak memory 215328 kb
Host smart-e555457f-adaf-4219-9f20-27d7b0379a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461381225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1461381225
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.721944887
Short name T130
Test name
Test status
Simulation time 35666824 ps
CPU time 1.08 seconds
Started Aug 07 06:57:12 PM PDT 24
Finished Aug 07 06:57:13 PM PDT 24
Peak memory 220608 kb
Host smart-1acecfd9-271e-43d9-a92a-2afbf71dc6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721944887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.721944887
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3158560712
Short name T314
Test name
Test status
Simulation time 32436322 ps
CPU time 1.44 seconds
Started Aug 07 06:57:12 PM PDT 24
Finished Aug 07 06:57:14 PM PDT 24
Peak memory 219756 kb
Host smart-3014cb2a-4dfc-45b9-9214-bbce9b337a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158560712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3158560712
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.281569249
Short name T138
Test name
Test status
Simulation time 27450600 ps
CPU time 1.26 seconds
Started Aug 07 06:57:11 PM PDT 24
Finished Aug 07 06:57:13 PM PDT 24
Peak memory 219096 kb
Host smart-ad237e64-894a-454e-a99f-c3656f4b7a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281569249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.281569249
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.1941449511
Short name T454
Test name
Test status
Simulation time 21128248 ps
CPU time 1.1 seconds
Started Aug 07 06:57:12 PM PDT 24
Finished Aug 07 06:57:14 PM PDT 24
Peak memory 218564 kb
Host smart-345b4951-de44-468d-8709-f27b9499e8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941449511 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1941449511
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2990600215
Short name T625
Test name
Test status
Simulation time 81808343 ps
CPU time 1.26 seconds
Started Aug 07 06:57:12 PM PDT 24
Finished Aug 07 06:57:13 PM PDT 24
Peak memory 219408 kb
Host smart-63647692-344f-43c4-86cc-05f87e71cc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990600215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2990600215
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3133686534
Short name T853
Test name
Test status
Simulation time 400633958 ps
CPU time 1.17 seconds
Started Aug 07 06:57:11 PM PDT 24
Finished Aug 07 06:57:13 PM PDT 24
Peak memory 219696 kb
Host smart-7a2c63df-623a-485f-9324-e1e8c849127e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133686534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3133686534
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2872613853
Short name T195
Test name
Test status
Simulation time 18888019 ps
CPU time 1.16 seconds
Started Aug 07 06:57:11 PM PDT 24
Finished Aug 07 06:57:12 PM PDT 24
Peak memory 229308 kb
Host smart-b5a0e9fb-2a39-4cca-9340-841980ffba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872613853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2872613853
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.630586767
Short name T76
Test name
Test status
Simulation time 132947256 ps
CPU time 1.2 seconds
Started Aug 07 06:57:09 PM PDT 24
Finished Aug 07 06:57:10 PM PDT 24
Peak memory 216924 kb
Host smart-077c06d7-9118-44c9-a604-a5f9db591f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630586767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.630586767
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1244148316
Short name T637
Test name
Test status
Simulation time 47973864 ps
CPU time 1.14 seconds
Started Aug 07 06:57:09 PM PDT 24
Finished Aug 07 06:57:11 PM PDT 24
Peak memory 219584 kb
Host smart-124885fa-11e0-4dde-b379-f3373a8f6c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244148316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1244148316
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2971669556
Short name T959
Test name
Test status
Simulation time 34045821 ps
CPU time 0.88 seconds
Started Aug 07 06:57:13 PM PDT 24
Finished Aug 07 06:57:14 PM PDT 24
Peak memory 218472 kb
Host smart-9e9b5d86-5ff2-470d-ab5c-405e3192a5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971669556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2971669556
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.149482808
Short name T799
Test name
Test status
Simulation time 36946194 ps
CPU time 1.65 seconds
Started Aug 07 06:57:12 PM PDT 24
Finished Aug 07 06:57:13 PM PDT 24
Peak memory 220084 kb
Host smart-3fa97295-14a9-4415-ad8b-1c9a60fa8bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149482808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.149482808
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.1964173236
Short name T364
Test name
Test status
Simulation time 25309228 ps
CPU time 1.25 seconds
Started Aug 07 06:57:10 PM PDT 24
Finished Aug 07 06:57:11 PM PDT 24
Peak memory 220180 kb
Host smart-9f718f77-df87-43e4-864c-5bc15566e928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964173236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1964173236
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.2067897927
Short name T805
Test name
Test status
Simulation time 59495864 ps
CPU time 1 seconds
Started Aug 07 06:57:11 PM PDT 24
Finished Aug 07 06:57:13 PM PDT 24
Peak memory 218476 kb
Host smart-babed838-f636-4352-80a9-75ee2849c152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067897927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2067897927
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/57.edn_alert.906594258
Short name T628
Test name
Test status
Simulation time 27023326 ps
CPU time 1.17 seconds
Started Aug 07 06:57:13 PM PDT 24
Finished Aug 07 06:57:14 PM PDT 24
Peak memory 219576 kb
Host smart-98900c73-390a-4937-939b-9a59a73dc10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906594258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.906594258
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.411998755
Short name T736
Test name
Test status
Simulation time 18558984 ps
CPU time 1.08 seconds
Started Aug 07 06:57:12 PM PDT 24
Finished Aug 07 06:57:14 PM PDT 24
Peak memory 218520 kb
Host smart-6211af12-561e-4f5e-8727-ecd331e14dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411998755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.411998755
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2282150379
Short name T851
Test name
Test status
Simulation time 74113595 ps
CPU time 1.5 seconds
Started Aug 07 06:57:12 PM PDT 24
Finished Aug 07 06:57:13 PM PDT 24
Peak memory 218524 kb
Host smart-665aa07c-10ef-4bd0-860b-97070a2ccb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282150379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2282150379
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1907459188
Short name T699
Test name
Test status
Simulation time 231896437 ps
CPU time 1.08 seconds
Started Aug 07 06:57:10 PM PDT 24
Finished Aug 07 06:57:11 PM PDT 24
Peak memory 218256 kb
Host smart-8799f3e2-a4f1-47bd-b19c-cd41302e09b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907459188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1907459188
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2929773663
Short name T813
Test name
Test status
Simulation time 54313821 ps
CPU time 0.99 seconds
Started Aug 07 06:57:11 PM PDT 24
Finished Aug 07 06:57:12 PM PDT 24
Peak memory 219680 kb
Host smart-a21b84fa-6b00-4f7a-a168-c414c779fe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929773663 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2929773663
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1457389202
Short name T405
Test name
Test status
Simulation time 30987957 ps
CPU time 1.33 seconds
Started Aug 07 06:57:15 PM PDT 24
Finished Aug 07 06:57:17 PM PDT 24
Peak memory 216832 kb
Host smart-1f55b3d9-7faf-4cee-97f2-ab6e9fa79152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457389202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1457389202
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3173149675
Short name T502
Test name
Test status
Simulation time 41852907 ps
CPU time 1.15 seconds
Started Aug 07 06:57:13 PM PDT 24
Finished Aug 07 06:57:14 PM PDT 24
Peak memory 219440 kb
Host smart-3f0564fd-5a94-490d-8a23-434d97b1255a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173149675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3173149675
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.4213640445
Short name T107
Test name
Test status
Simulation time 29110421 ps
CPU time 1.22 seconds
Started Aug 07 06:57:09 PM PDT 24
Finished Aug 07 06:57:10 PM PDT 24
Peak memory 219716 kb
Host smart-e09b1150-c646-4b12-8687-4826664460f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213640445 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.4213640445
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3097804502
Short name T459
Test name
Test status
Simulation time 41428659 ps
CPU time 1.49 seconds
Started Aug 07 06:57:09 PM PDT 24
Finished Aug 07 06:57:11 PM PDT 24
Peak memory 219572 kb
Host smart-e0113cb8-b966-42a9-bfef-df4c965824a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097804502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3097804502
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3861917447
Short name T250
Test name
Test status
Simulation time 105780546 ps
CPU time 1.19 seconds
Started Aug 07 06:55:32 PM PDT 24
Finished Aug 07 06:55:33 PM PDT 24
Peak memory 218908 kb
Host smart-dc69985d-80ff-45bc-b91a-c9e846fc1647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861917447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3861917447
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3326632252
Short name T987
Test name
Test status
Simulation time 28069175 ps
CPU time 0.86 seconds
Started Aug 07 06:55:34 PM PDT 24
Finished Aug 07 06:55:35 PM PDT 24
Peak memory 206352 kb
Host smart-ccc30065-c956-437c-b512-7fa6ef1b5d26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326632252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3326632252
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2395246660
Short name T662
Test name
Test status
Simulation time 13880982 ps
CPU time 0.9 seconds
Started Aug 07 06:55:31 PM PDT 24
Finished Aug 07 06:55:32 PM PDT 24
Peak memory 207012 kb
Host smart-a9ba732d-305e-4cfa-bd10-fc34a3510ea5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395246660 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2395246660
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2204251286
Short name T740
Test name
Test status
Simulation time 127751019 ps
CPU time 1.12 seconds
Started Aug 07 06:55:33 PM PDT 24
Finished Aug 07 06:55:34 PM PDT 24
Peak memory 218152 kb
Host smart-1c0c5e94-d577-4b48-b67b-b5e00e87b2b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204251286 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2204251286
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1141850455
Short name T711
Test name
Test status
Simulation time 67614662 ps
CPU time 0.99 seconds
Started Aug 07 06:55:35 PM PDT 24
Finished Aug 07 06:55:36 PM PDT 24
Peak memory 218608 kb
Host smart-c8c7d539-2863-42b1-8e6b-b98d691404f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141850455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1141850455
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2248540208
Short name T486
Test name
Test status
Simulation time 102672720 ps
CPU time 1.25 seconds
Started Aug 07 06:55:32 PM PDT 24
Finished Aug 07 06:55:33 PM PDT 24
Peak memory 219416 kb
Host smart-60af0284-6128-4a8d-ba94-96d8cb291868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248540208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2248540208
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2277442891
Short name T99
Test name
Test status
Simulation time 26205666 ps
CPU time 0.94 seconds
Started Aug 07 06:55:33 PM PDT 24
Finished Aug 07 06:55:34 PM PDT 24
Peak memory 215544 kb
Host smart-f75c506d-6f34-46d2-a1bf-3fbe73c95328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277442891 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2277442891
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1682611236
Short name T921
Test name
Test status
Simulation time 133873648 ps
CPU time 0.9 seconds
Started Aug 07 06:55:36 PM PDT 24
Finished Aug 07 06:55:37 PM PDT 24
Peak memory 206712 kb
Host smart-855bdc0b-3d77-4966-9501-555b6229a607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682611236 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1682611236
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1594049534
Short name T467
Test name
Test status
Simulation time 16482021 ps
CPU time 1.01 seconds
Started Aug 07 06:55:33 PM PDT 24
Finished Aug 07 06:55:34 PM PDT 24
Peak memory 214912 kb
Host smart-5032c12c-7ad3-4d8c-9c4d-6eb6652ee8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594049534 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1594049534
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.127365186
Short name T895
Test name
Test status
Simulation time 157080186 ps
CPU time 1.48 seconds
Started Aug 07 06:55:33 PM PDT 24
Finished Aug 07 06:55:35 PM PDT 24
Peak memory 214860 kb
Host smart-d8d670cf-55d3-4d88-aa1c-4df8098ebdb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127365186 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.127365186
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1820568227
Short name T956
Test name
Test status
Simulation time 65781264335 ps
CPU time 774.37 seconds
Started Aug 07 06:55:31 PM PDT 24
Finished Aug 07 07:08:26 PM PDT 24
Peak memory 218616 kb
Host smart-13a85370-dcb0-42e7-97c9-200140cd25c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820568227 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1820568227
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1773367718
Short name T519
Test name
Test status
Simulation time 22742385 ps
CPU time 1.15 seconds
Started Aug 07 06:57:11 PM PDT 24
Finished Aug 07 06:57:13 PM PDT 24
Peak memory 218204 kb
Host smart-b5ea4991-46b0-4424-bed8-97ad161b08d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773367718 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1773367718
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3897155408
Short name T836
Test name
Test status
Simulation time 38750310 ps
CPU time 0.93 seconds
Started Aug 07 06:57:15 PM PDT 24
Finished Aug 07 06:57:16 PM PDT 24
Peak memory 219212 kb
Host smart-e0b28074-5316-46ae-86b5-13d3614d0fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897155408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3897155408
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1804035075
Short name T85
Test name
Test status
Simulation time 55853284 ps
CPU time 1.03 seconds
Started Aug 07 06:57:12 PM PDT 24
Finished Aug 07 06:57:13 PM PDT 24
Peak memory 217120 kb
Host smart-60bcb7d1-a326-4925-a40b-e94d9b372417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804035075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1804035075
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1196289279
Short name T522
Test name
Test status
Simulation time 74983211 ps
CPU time 1.12 seconds
Started Aug 07 06:57:16 PM PDT 24
Finished Aug 07 06:57:17 PM PDT 24
Peak memory 220424 kb
Host smart-3f9ee6c2-693a-4bb5-bfd7-600ff494dd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196289279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1196289279
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2412866911
Short name T194
Test name
Test status
Simulation time 21429984 ps
CPU time 1.1 seconds
Started Aug 07 06:57:15 PM PDT 24
Finished Aug 07 06:57:17 PM PDT 24
Peak memory 219204 kb
Host smart-6810b7b6-deb9-4078-aceb-af1646c4f67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412866911 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2412866911
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3126990007
Short name T700
Test name
Test status
Simulation time 87915608 ps
CPU time 1.16 seconds
Started Aug 07 06:57:11 PM PDT 24
Finished Aug 07 06:57:13 PM PDT 24
Peak memory 217384 kb
Host smart-16d71367-38a0-4063-a1d8-5e6a83816723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126990007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3126990007
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.4205377004
Short name T172
Test name
Test status
Simulation time 42354177 ps
CPU time 1.13 seconds
Started Aug 07 06:57:16 PM PDT 24
Finished Aug 07 06:57:17 PM PDT 24
Peak memory 219352 kb
Host smart-8609238a-1ba3-4094-b019-8f00ddb1f756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205377004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.4205377004
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3665025030
Short name T212
Test name
Test status
Simulation time 89436570 ps
CPU time 0.87 seconds
Started Aug 07 06:57:18 PM PDT 24
Finished Aug 07 06:57:19 PM PDT 24
Peak memory 218500 kb
Host smart-be61a44d-7aaf-41ee-969a-2a1db19559aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665025030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3665025030
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1505779158
Short name T352
Test name
Test status
Simulation time 59997167 ps
CPU time 1.52 seconds
Started Aug 07 06:57:16 PM PDT 24
Finished Aug 07 06:57:18 PM PDT 24
Peak memory 218696 kb
Host smart-277336e2-ea9b-41c4-a569-98e5b3f37759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505779158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1505779158
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.3940336916
Short name T415
Test name
Test status
Simulation time 38998457 ps
CPU time 1.18 seconds
Started Aug 07 06:57:14 PM PDT 24
Finished Aug 07 06:57:16 PM PDT 24
Peak memory 219280 kb
Host smart-09856576-9510-4fb4-91c1-a0bd3f1516d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940336916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3940336916
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1354044123
Short name T666
Test name
Test status
Simulation time 19789009 ps
CPU time 1.06 seconds
Started Aug 07 06:57:16 PM PDT 24
Finished Aug 07 06:57:17 PM PDT 24
Peak memory 218292 kb
Host smart-c7721e87-1d50-4b35-bc23-b9084e01da97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354044123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1354044123
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3675444706
Short name T767
Test name
Test status
Simulation time 119165340 ps
CPU time 2.23 seconds
Started Aug 07 06:57:16 PM PDT 24
Finished Aug 07 06:57:19 PM PDT 24
Peak memory 219800 kb
Host smart-57089c93-6f92-45e3-aae5-ebba6c17a291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675444706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3675444706
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3157190076
Short name T165
Test name
Test status
Simulation time 18888508 ps
CPU time 1.06 seconds
Started Aug 07 06:57:14 PM PDT 24
Finished Aug 07 06:57:15 PM PDT 24
Peak memory 218248 kb
Host smart-5b2ec798-f38e-408d-b023-974584157b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157190076 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3157190076
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1796224817
Short name T884
Test name
Test status
Simulation time 290009835 ps
CPU time 1.49 seconds
Started Aug 07 06:57:16 PM PDT 24
Finished Aug 07 06:57:18 PM PDT 24
Peak memory 219692 kb
Host smart-d51438c4-ad13-46af-8bf3-f307a3877d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796224817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1796224817
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.2470319012
Short name T804
Test name
Test status
Simulation time 85955742 ps
CPU time 1.29 seconds
Started Aug 07 06:57:15 PM PDT 24
Finished Aug 07 06:57:17 PM PDT 24
Peak memory 219552 kb
Host smart-51aa2ea2-0f7d-41b7-a8f4-3f19b2eb0827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470319012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2470319012
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_genbits.2044546595
Short name T56
Test name
Test status
Simulation time 89842801 ps
CPU time 1.3 seconds
Started Aug 07 06:57:14 PM PDT 24
Finished Aug 07 06:57:15 PM PDT 24
Peak memory 218704 kb
Host smart-569d61f7-5f08-48cb-b3e0-d681ba911865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044546595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2044546595
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.2461860658
Short name T115
Test name
Test status
Simulation time 45964857 ps
CPU time 1.15 seconds
Started Aug 07 06:57:15 PM PDT 24
Finished Aug 07 06:57:17 PM PDT 24
Peak memory 218212 kb
Host smart-43247153-a84d-4ac3-bd98-1e922c762632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461860658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.2461860658
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.551698466
Short name T381
Test name
Test status
Simulation time 20931034 ps
CPU time 1.07 seconds
Started Aug 07 06:57:21 PM PDT 24
Finished Aug 07 06:57:22 PM PDT 24
Peak memory 219560 kb
Host smart-868ccd74-120c-47d4-a060-e9e24f317649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551698466 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.551698466
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.715703890
Short name T18
Test name
Test status
Simulation time 67453906 ps
CPU time 2.39 seconds
Started Aug 07 06:57:14 PM PDT 24
Finished Aug 07 06:57:17 PM PDT 24
Peak memory 219800 kb
Host smart-3c5fb1d0-4bb5-46fa-9915-5b8c49eef423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715703890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.715703890
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.4219862809
Short name T665
Test name
Test status
Simulation time 76577266 ps
CPU time 1.16 seconds
Started Aug 07 06:57:21 PM PDT 24
Finished Aug 07 06:57:22 PM PDT 24
Peak memory 219604 kb
Host smart-abd98e42-cfb0-4a1a-8638-a745ceae41a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219862809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.4219862809
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1674615342
Short name T952
Test name
Test status
Simulation time 19756338 ps
CPU time 1.07 seconds
Started Aug 07 06:57:20 PM PDT 24
Finished Aug 07 06:57:22 PM PDT 24
Peak memory 219456 kb
Host smart-b6994893-8762-4f79-b433-7564f1f6e5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674615342 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1674615342
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.640282159
Short name T369
Test name
Test status
Simulation time 35200997 ps
CPU time 1.39 seconds
Started Aug 07 06:57:20 PM PDT 24
Finished Aug 07 06:57:22 PM PDT 24
Peak memory 219524 kb
Host smart-75e8d6dc-4c39-4930-a9c5-86a24ccc5741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640282159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.640282159
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.3724576296
Short name T708
Test name
Test status
Simulation time 67653484 ps
CPU time 1.17 seconds
Started Aug 07 06:57:22 PM PDT 24
Finished Aug 07 06:57:24 PM PDT 24
Peak memory 219220 kb
Host smart-dab93af6-bda2-4c19-9383-dfc7e3e465c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724576296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3724576296
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.2039747842
Short name T748
Test name
Test status
Simulation time 32857496 ps
CPU time 0.89 seconds
Started Aug 07 06:57:20 PM PDT 24
Finished Aug 07 06:57:21 PM PDT 24
Peak memory 218468 kb
Host smart-a0730862-4782-4027-af1f-e5b97a21a925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039747842 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2039747842
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1098569021
Short name T93
Test name
Test status
Simulation time 55451932 ps
CPU time 1.95 seconds
Started Aug 07 06:57:20 PM PDT 24
Finished Aug 07 06:57:22 PM PDT 24
Peak memory 216948 kb
Host smart-6cee76f0-6ce6-4971-9762-a5a65dadc35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098569021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1098569021
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3106161313
Short name T386
Test name
Test status
Simulation time 83342147 ps
CPU time 1.2 seconds
Started Aug 07 06:57:22 PM PDT 24
Finished Aug 07 06:57:23 PM PDT 24
Peak memory 218180 kb
Host smart-1da8a10c-7843-458c-9b8c-41056d14eb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106161313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3106161313
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.687581780
Short name T213
Test name
Test status
Simulation time 54117050 ps
CPU time 0.88 seconds
Started Aug 07 06:57:20 PM PDT 24
Finished Aug 07 06:57:21 PM PDT 24
Peak memory 218448 kb
Host smart-45abfb02-7399-4d64-b9d6-3138ab8dc9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687581780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.687581780
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.72475625
Short name T337
Test name
Test status
Simulation time 35025311 ps
CPU time 1.4 seconds
Started Aug 07 06:57:21 PM PDT 24
Finished Aug 07 06:57:22 PM PDT 24
Peak memory 219312 kb
Host smart-af5f5733-cde2-422e-a459-27871165f9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72475625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.72475625
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.4028403441
Short name T277
Test name
Test status
Simulation time 30559038 ps
CPU time 1.33 seconds
Started Aug 07 06:55:31 PM PDT 24
Finished Aug 07 06:55:32 PM PDT 24
Peak memory 220200 kb
Host smart-21c39449-d797-4126-9e74-00b2f197cfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028403441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.4028403441
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1651777096
Short name T988
Test name
Test status
Simulation time 30505266 ps
CPU time 1.18 seconds
Started Aug 07 06:55:32 PM PDT 24
Finished Aug 07 06:55:33 PM PDT 24
Peak memory 206484 kb
Host smart-a1cb3e36-aefc-4e60-9e59-a3d8fc859383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651777096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1651777096
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2677014755
Short name T199
Test name
Test status
Simulation time 90736739 ps
CPU time 0.87 seconds
Started Aug 07 06:55:35 PM PDT 24
Finished Aug 07 06:55:36 PM PDT 24
Peak memory 218048 kb
Host smart-0443fad1-fe62-49db-a700-48167d43303d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677014755 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2677014755
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1099688454
Short name T140
Test name
Test status
Simulation time 34906338 ps
CPU time 1.26 seconds
Started Aug 07 06:55:30 PM PDT 24
Finished Aug 07 06:55:31 PM PDT 24
Peak memory 219492 kb
Host smart-2cfbe4cc-fe72-44a3-bd38-310591c54bb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099688454 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1099688454
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2487163014
Short name T490
Test name
Test status
Simulation time 19256269 ps
CPU time 1.11 seconds
Started Aug 07 06:55:31 PM PDT 24
Finished Aug 07 06:55:32 PM PDT 24
Peak memory 218684 kb
Host smart-6fbc59e3-4d8d-4dc4-a518-6cedd150a142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487163014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2487163014
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.141369697
Short name T113
Test name
Test status
Simulation time 713449183 ps
CPU time 5.72 seconds
Started Aug 07 06:55:31 PM PDT 24
Finished Aug 07 06:55:37 PM PDT 24
Peak memory 218628 kb
Host smart-078c9451-e29d-474d-a848-dd16acd90ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141369697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.141369697
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3440396875
Short name T701
Test name
Test status
Simulation time 34693244 ps
CPU time 0.88 seconds
Started Aug 07 06:55:35 PM PDT 24
Finished Aug 07 06:55:36 PM PDT 24
Peak memory 215516 kb
Host smart-52c8f264-9f4d-4f89-8cc1-a035c4118a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440396875 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3440396875
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2406134329
Short name T489
Test name
Test status
Simulation time 17745334 ps
CPU time 1.02 seconds
Started Aug 07 06:55:32 PM PDT 24
Finished Aug 07 06:55:33 PM PDT 24
Peak memory 206728 kb
Host smart-67f7d178-9521-475c-9b3f-bed242ede58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406134329 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2406134329
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1908282582
Short name T854
Test name
Test status
Simulation time 24716089 ps
CPU time 0.95 seconds
Started Aug 07 06:55:36 PM PDT 24
Finished Aug 07 06:55:37 PM PDT 24
Peak memory 214936 kb
Host smart-1b1c4a56-15d0-40ed-bf2f-1ee4dc9b1a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908282582 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1908282582
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2591135842
Short name T523
Test name
Test status
Simulation time 269132358 ps
CPU time 1.83 seconds
Started Aug 07 06:55:35 PM PDT 24
Finished Aug 07 06:55:37 PM PDT 24
Peak memory 214960 kb
Host smart-52394617-61ab-46da-8160-da9b2b674c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591135842 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2591135842
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.4174177171
Short name T21
Test name
Test status
Simulation time 18916466338 ps
CPU time 475.66 seconds
Started Aug 07 06:55:32 PM PDT 24
Finished Aug 07 07:03:28 PM PDT 24
Peak memory 217968 kb
Host smart-b965f850-3cd7-45dc-a870-48bee6927688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174177171 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.4174177171
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.357086255
Short name T160
Test name
Test status
Simulation time 39962051 ps
CPU time 1.09 seconds
Started Aug 07 06:57:22 PM PDT 24
Finished Aug 07 06:57:23 PM PDT 24
Peak memory 219092 kb
Host smart-6a598c68-d72d-4e2d-b13d-4883af8237d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357086255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.357086255
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.3489173449
Short name T772
Test name
Test status
Simulation time 31053697 ps
CPU time 0.91 seconds
Started Aug 07 06:57:23 PM PDT 24
Finished Aug 07 06:57:24 PM PDT 24
Peak memory 219180 kb
Host smart-d3430633-8cb2-4af7-b591-53f36e1907ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489173449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3489173449
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1110713987
Short name T38
Test name
Test status
Simulation time 60660148 ps
CPU time 1.45 seconds
Started Aug 07 06:57:20 PM PDT 24
Finished Aug 07 06:57:21 PM PDT 24
Peak memory 220024 kb
Host smart-3c0506cd-43b6-4402-8d3a-fac1261fdfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110713987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1110713987
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.1008066727
Short name T435
Test name
Test status
Simulation time 26161281 ps
CPU time 1.26 seconds
Started Aug 07 06:57:20 PM PDT 24
Finished Aug 07 06:57:21 PM PDT 24
Peak memory 219208 kb
Host smart-4108253d-bb8a-474a-b0a7-f644ac509c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008066727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.1008066727
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2398548243
Short name T121
Test name
Test status
Simulation time 57293956 ps
CPU time 1.06 seconds
Started Aug 07 06:57:28 PM PDT 24
Finished Aug 07 06:57:29 PM PDT 24
Peak memory 229348 kb
Host smart-e86495bf-7f5a-4ea6-a300-1bd1588a7e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398548243 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2398548243
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.4117720420
Short name T448
Test name
Test status
Simulation time 64261898 ps
CPU time 1.33 seconds
Started Aug 07 06:57:22 PM PDT 24
Finished Aug 07 06:57:24 PM PDT 24
Peak memory 219660 kb
Host smart-b85b7bb1-0d26-4168-a57f-d4a4c22ef641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117720420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.4117720420
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.4289674761
Short name T153
Test name
Test status
Simulation time 22708428 ps
CPU time 1.22 seconds
Started Aug 07 06:57:32 PM PDT 24
Finished Aug 07 06:57:33 PM PDT 24
Peak memory 218916 kb
Host smart-032a7f52-9109-4452-b98b-2411b9db9b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289674761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.4289674761
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.340043282
Short name T676
Test name
Test status
Simulation time 31605129 ps
CPU time 0.92 seconds
Started Aug 07 06:57:27 PM PDT 24
Finished Aug 07 06:57:28 PM PDT 24
Peak memory 219492 kb
Host smart-e75b7505-12e9-4b0b-9437-ea2f517577a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340043282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.340043282
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2572572980
Short name T557
Test name
Test status
Simulation time 63805606 ps
CPU time 1.11 seconds
Started Aug 07 06:57:26 PM PDT 24
Finished Aug 07 06:57:27 PM PDT 24
Peak memory 217032 kb
Host smart-06532c7f-4832-4230-a770-c486d87a54cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572572980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2572572980
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2643156650
Short name T463
Test name
Test status
Simulation time 34713178 ps
CPU time 1.3 seconds
Started Aug 07 06:57:28 PM PDT 24
Finished Aug 07 06:57:29 PM PDT 24
Peak memory 219008 kb
Host smart-7cd56a49-0ec1-44a4-a348-508c98392ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643156650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2643156650
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1763841116
Short name T534
Test name
Test status
Simulation time 42345044 ps
CPU time 0.99 seconds
Started Aug 07 06:57:27 PM PDT 24
Finished Aug 07 06:57:28 PM PDT 24
Peak memory 218600 kb
Host smart-1650a6be-f6d8-4ff9-989f-73d07b7d226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763841116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1763841116
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2288226148
Short name T529
Test name
Test status
Simulation time 67259752 ps
CPU time 1.14 seconds
Started Aug 07 06:57:29 PM PDT 24
Finished Aug 07 06:57:30 PM PDT 24
Peak memory 219452 kb
Host smart-06a3c5ea-52ef-4bed-a1eb-75668a582c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288226148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2288226148
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2444095669
Short name T391
Test name
Test status
Simulation time 40727613 ps
CPU time 1.29 seconds
Started Aug 07 06:57:27 PM PDT 24
Finished Aug 07 06:57:29 PM PDT 24
Peak memory 215296 kb
Host smart-779589a2-623a-4d58-a79e-0cc9fb4bec70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444095669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2444095669
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2098905478
Short name T122
Test name
Test status
Simulation time 33905407 ps
CPU time 1.03 seconds
Started Aug 07 06:57:29 PM PDT 24
Finished Aug 07 06:57:30 PM PDT 24
Peak memory 219424 kb
Host smart-8b6b35c7-1b50-427c-a64a-5025eb19a79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098905478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2098905478
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3253891958
Short name T657
Test name
Test status
Simulation time 46842973 ps
CPU time 1.1 seconds
Started Aug 07 06:57:26 PM PDT 24
Finished Aug 07 06:57:27 PM PDT 24
Peak memory 218284 kb
Host smart-ffd7a5b7-b28c-4c4a-9094-07e9eff9c678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253891958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3253891958
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1089106820
Short name T537
Test name
Test status
Simulation time 47248223 ps
CPU time 1.2 seconds
Started Aug 07 06:57:29 PM PDT 24
Finished Aug 07 06:57:30 PM PDT 24
Peak memory 218032 kb
Host smart-190742ce-b365-488f-a99f-7bab5358db73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089106820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1089106820
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2672820090
Short name T145
Test name
Test status
Simulation time 20947871 ps
CPU time 1.15 seconds
Started Aug 07 06:57:32 PM PDT 24
Finished Aug 07 06:57:33 PM PDT 24
Peak memory 219656 kb
Host smart-48f3b8fa-23bc-407f-ae54-6874bd3e7fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672820090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2672820090
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1228167053
Short name T965
Test name
Test status
Simulation time 126885032 ps
CPU time 1.48 seconds
Started Aug 07 06:57:28 PM PDT 24
Finished Aug 07 06:57:29 PM PDT 24
Peak memory 219708 kb
Host smart-1a1426ee-e5b3-4bc9-9f95-0183271c8d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228167053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1228167053
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1894678648
Short name T19
Test name
Test status
Simulation time 81068577 ps
CPU time 1.15 seconds
Started Aug 07 06:57:29 PM PDT 24
Finished Aug 07 06:57:30 PM PDT 24
Peak memory 219260 kb
Host smart-32d32629-e721-40a1-b358-32efbbdf77d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894678648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1894678648
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.210175680
Short name T747
Test name
Test status
Simulation time 86935943 ps
CPU time 0.79 seconds
Started Aug 07 06:57:25 PM PDT 24
Finished Aug 07 06:57:26 PM PDT 24
Peak memory 218436 kb
Host smart-c3600852-86cf-49a4-b550-ea0172fa0f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210175680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.210175680
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3926269940
Short name T969
Test name
Test status
Simulation time 30355158 ps
CPU time 1.43 seconds
Started Aug 07 06:57:31 PM PDT 24
Finished Aug 07 06:57:33 PM PDT 24
Peak memory 218056 kb
Host smart-fd00c9ca-d620-4f35-8f48-4d2e2c3d8932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926269940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3926269940
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.3805106591
Short name T184
Test name
Test status
Simulation time 50141476 ps
CPU time 1.16 seconds
Started Aug 07 06:57:27 PM PDT 24
Finished Aug 07 06:57:29 PM PDT 24
Peak memory 218488 kb
Host smart-d3386e76-7a4e-4765-be7b-08b655e8dcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805106591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3805106591
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.968166295
Short name T923
Test name
Test status
Simulation time 40358604 ps
CPU time 0.88 seconds
Started Aug 07 06:57:26 PM PDT 24
Finished Aug 07 06:57:27 PM PDT 24
Peak memory 218376 kb
Host smart-ac9391a8-050d-4492-8c27-2939af13fc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968166295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.968166295
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3333694947
Short name T281
Test name
Test status
Simulation time 55365296 ps
CPU time 2.2 seconds
Started Aug 07 06:57:28 PM PDT 24
Finished Aug 07 06:57:31 PM PDT 24
Peak memory 218728 kb
Host smart-7fd40a45-0d44-48c3-b562-63d456ca93a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333694947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3333694947
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.468360024
Short name T60
Test name
Test status
Simulation time 24597551 ps
CPU time 1.15 seconds
Started Aug 07 06:57:27 PM PDT 24
Finished Aug 07 06:57:29 PM PDT 24
Peak memory 218492 kb
Host smart-48d8f227-504a-446d-aea6-fc66a5cf8799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468360024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.468360024
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.416635629
Short name T407
Test name
Test status
Simulation time 63976469 ps
CPU time 2.52 seconds
Started Aug 07 06:57:26 PM PDT 24
Finished Aug 07 06:57:29 PM PDT 24
Peak memory 219788 kb
Host smart-613e1a73-9677-4ae3-8db0-97b622e95e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416635629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.416635629
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1638456980
Short name T370
Test name
Test status
Simulation time 28534196 ps
CPU time 1.19 seconds
Started Aug 07 06:57:26 PM PDT 24
Finished Aug 07 06:57:28 PM PDT 24
Peak memory 218028 kb
Host smart-0ec4d7ac-18b9-462f-8b86-a5a91440d017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638456980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1638456980
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.3015929059
Short name T186
Test name
Test status
Simulation time 24120912 ps
CPU time 0.99 seconds
Started Aug 07 06:57:30 PM PDT 24
Finished Aug 07 06:57:31 PM PDT 24
Peak memory 218508 kb
Host smart-edf4fa52-ee50-4cfe-b653-cc8f1df44f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015929059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3015929059
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3034025706
Short name T814
Test name
Test status
Simulation time 86061525 ps
CPU time 1.23 seconds
Started Aug 07 06:57:27 PM PDT 24
Finished Aug 07 06:57:28 PM PDT 24
Peak memory 217028 kb
Host smart-001e1cb7-dcda-4b63-b53b-6fc35644af89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034025706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3034025706
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3603807375
Short name T400
Test name
Test status
Simulation time 28927069 ps
CPU time 1.21 seconds
Started Aug 07 06:55:35 PM PDT 24
Finished Aug 07 06:55:36 PM PDT 24
Peak memory 219336 kb
Host smart-7ed80754-89f3-47f6-a0ce-ac67ae91d344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603807375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3603807375
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1566653572
Short name T858
Test name
Test status
Simulation time 39953029 ps
CPU time 1.01 seconds
Started Aug 07 06:55:38 PM PDT 24
Finished Aug 07 06:55:39 PM PDT 24
Peak memory 206340 kb
Host smart-e153fd8f-f46f-4852-9b85-e62991529b3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566653572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1566653572
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1476622837
Short name T197
Test name
Test status
Simulation time 67986840 ps
CPU time 0.86 seconds
Started Aug 07 06:55:38 PM PDT 24
Finished Aug 07 06:55:38 PM PDT 24
Peak memory 218868 kb
Host smart-534abdd1-ddeb-4409-aeb8-777f8205c9c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476622837 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1476622837
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2137279238
Short name T126
Test name
Test status
Simulation time 67762913 ps
CPU time 1.02 seconds
Started Aug 07 06:55:37 PM PDT 24
Finished Aug 07 06:55:38 PM PDT 24
Peak memory 219256 kb
Host smart-63c026b2-4f59-45a7-8628-f0398659a5e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137279238 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2137279238
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1772408902
Short name T373
Test name
Test status
Simulation time 101957845 ps
CPU time 0.92 seconds
Started Aug 07 06:55:35 PM PDT 24
Finished Aug 07 06:55:36 PM PDT 24
Peak memory 218696 kb
Host smart-c6abaccb-352d-4184-a880-6e9707cbedc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772408902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1772408902
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1026636448
Short name T756
Test name
Test status
Simulation time 54162942 ps
CPU time 1.21 seconds
Started Aug 07 06:55:32 PM PDT 24
Finished Aug 07 06:55:33 PM PDT 24
Peak memory 216896 kb
Host smart-36a3a69c-757d-4a29-968c-997fa375317d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026636448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1026636448
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2736748090
Short name T241
Test name
Test status
Simulation time 101001862 ps
CPU time 0.87 seconds
Started Aug 07 06:55:37 PM PDT 24
Finished Aug 07 06:55:38 PM PDT 24
Peak memory 215048 kb
Host smart-bc482e88-bd1b-47a4-8972-f80eee642418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736748090 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2736748090
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1513414060
Short name T979
Test name
Test status
Simulation time 18236808 ps
CPU time 1 seconds
Started Aug 07 06:55:32 PM PDT 24
Finished Aug 07 06:55:33 PM PDT 24
Peak memory 206708 kb
Host smart-69e1397a-9c70-40fe-9900-1755387518f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513414060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1513414060
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3300053804
Short name T456
Test name
Test status
Simulation time 44880196 ps
CPU time 0.94 seconds
Started Aug 07 06:55:32 PM PDT 24
Finished Aug 07 06:55:33 PM PDT 24
Peak memory 214932 kb
Host smart-0c76e229-e86f-49db-bd86-5f6cb918c0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300053804 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3300053804
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.879673898
Short name T950
Test name
Test status
Simulation time 62971029 ps
CPU time 1.56 seconds
Started Aug 07 06:55:32 PM PDT 24
Finished Aug 07 06:55:33 PM PDT 24
Peak memory 218260 kb
Host smart-07de74bb-fd62-4c1d-ac5f-c3bbe30ec950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879673898 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.879673898
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.270939754
Short name T236
Test name
Test status
Simulation time 75381738056 ps
CPU time 750.64 seconds
Started Aug 07 06:55:36 PM PDT 24
Finished Aug 07 07:08:07 PM PDT 24
Peak memory 218892 kb
Host smart-a82d7635-c722-498f-86f9-aa3d76aea16a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270939754 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.270939754
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1954460779
Short name T794
Test name
Test status
Simulation time 121737611 ps
CPU time 1.23 seconds
Started Aug 07 06:57:29 PM PDT 24
Finished Aug 07 06:57:30 PM PDT 24
Peak memory 218860 kb
Host smart-e95a84e3-33ca-40ad-9881-647f19c5ab00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954460779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1954460779
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3550928079
Short name T512
Test name
Test status
Simulation time 18799273 ps
CPU time 1.05 seconds
Started Aug 07 06:57:31 PM PDT 24
Finished Aug 07 06:57:32 PM PDT 24
Peak memory 218360 kb
Host smart-f7ef6a42-446e-438c-bafd-30662f987f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550928079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3550928079
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.881292364
Short name T511
Test name
Test status
Simulation time 31574626 ps
CPU time 1.2 seconds
Started Aug 07 06:57:26 PM PDT 24
Finished Aug 07 06:57:28 PM PDT 24
Peak memory 217956 kb
Host smart-a354039d-1eba-402d-a25e-f471e6c7150b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881292364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.881292364
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2626441860
Short name T26
Test name
Test status
Simulation time 47732399 ps
CPU time 1.09 seconds
Started Aug 07 06:57:35 PM PDT 24
Finished Aug 07 06:57:36 PM PDT 24
Peak memory 219736 kb
Host smart-c1333365-665d-4e83-8397-819ca9ba32ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626441860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2626441860
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.3822028394
Short name T915
Test name
Test status
Simulation time 33870353 ps
CPU time 0.91 seconds
Started Aug 07 06:57:35 PM PDT 24
Finished Aug 07 06:57:37 PM PDT 24
Peak memory 218316 kb
Host smart-55e1aef2-72f2-461a-9b3e-fc6082f8ba3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822028394 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3822028394
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.851476133
Short name T850
Test name
Test status
Simulation time 50613417 ps
CPU time 1.39 seconds
Started Aug 07 06:57:32 PM PDT 24
Finished Aug 07 06:57:33 PM PDT 24
Peak memory 218304 kb
Host smart-432afeab-21d7-4379-b399-c8291314ff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851476133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.851476133
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2012459386
Short name T150
Test name
Test status
Simulation time 83232791 ps
CPU time 1.22 seconds
Started Aug 07 06:57:33 PM PDT 24
Finished Aug 07 06:57:34 PM PDT 24
Peak memory 218240 kb
Host smart-c649f745-4a6c-49e8-a84d-58f134842e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012459386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2012459386
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.1224042078
Short name T839
Test name
Test status
Simulation time 18495944 ps
CPU time 1.13 seconds
Started Aug 07 06:57:31 PM PDT 24
Finished Aug 07 06:57:33 PM PDT 24
Peak memory 223744 kb
Host smart-d5e6a3d3-4f5f-4712-8fed-389fa9b817fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224042078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1224042078
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.684508997
Short name T703
Test name
Test status
Simulation time 40272315 ps
CPU time 1.43 seconds
Started Aug 07 06:57:30 PM PDT 24
Finished Aug 07 06:57:32 PM PDT 24
Peak memory 214928 kb
Host smart-cd4f909b-75f8-4846-ae56-f40b64a017ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684508997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.684508997
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3844024286
Short name T919
Test name
Test status
Simulation time 71650191 ps
CPU time 1.11 seconds
Started Aug 07 06:57:29 PM PDT 24
Finished Aug 07 06:57:31 PM PDT 24
Peak memory 219908 kb
Host smart-a28d4cb8-13ed-4e5c-ae6b-ec4c0137dc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844024286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3844024286
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.147699079
Short name T155
Test name
Test status
Simulation time 37855768 ps
CPU time 0.92 seconds
Started Aug 07 06:57:30 PM PDT 24
Finished Aug 07 06:57:31 PM PDT 24
Peak memory 218352 kb
Host smart-27c70b48-2cb1-4956-af83-9ff72a70016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147699079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.147699079
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3412431008
Short name T414
Test name
Test status
Simulation time 190185747 ps
CPU time 1.3 seconds
Started Aug 07 06:57:32 PM PDT 24
Finished Aug 07 06:57:34 PM PDT 24
Peak memory 219956 kb
Host smart-efcedb8d-1a57-43a3-b289-5b75f9d010f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412431008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3412431008
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2521051873
Short name T455
Test name
Test status
Simulation time 78528792 ps
CPU time 1.1 seconds
Started Aug 07 06:57:34 PM PDT 24
Finished Aug 07 06:57:36 PM PDT 24
Peak memory 219556 kb
Host smart-ca756f32-3ac6-4e27-9685-50654864ffca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521051873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2521051873
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3093655644
Short name T7
Test name
Test status
Simulation time 33945154 ps
CPU time 1.36 seconds
Started Aug 07 06:57:31 PM PDT 24
Finished Aug 07 06:57:32 PM PDT 24
Peak memory 229300 kb
Host smart-df299b56-1318-40b4-9ad9-7f75636c53c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093655644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3093655644
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.624595192
Short name T914
Test name
Test status
Simulation time 233767340 ps
CPU time 1.08 seconds
Started Aug 07 06:57:34 PM PDT 24
Finished Aug 07 06:57:36 PM PDT 24
Peak memory 216876 kb
Host smart-2691986c-18bf-4fe8-872a-6e8cdedc6ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624595192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.624595192
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2850570681
Short name T498
Test name
Test status
Simulation time 76410582 ps
CPU time 1.18 seconds
Started Aug 07 06:57:31 PM PDT 24
Finished Aug 07 06:57:32 PM PDT 24
Peak memory 219364 kb
Host smart-a4671232-a097-4388-9238-bea7eea08911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850570681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2850570681
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1336658738
Short name T667
Test name
Test status
Simulation time 34663846 ps
CPU time 1.09 seconds
Started Aug 07 06:57:33 PM PDT 24
Finished Aug 07 06:57:34 PM PDT 24
Peak memory 222820 kb
Host smart-32ab76da-2e19-450c-9652-5321a4231b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336658738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1336658738
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3429485001
Short name T660
Test name
Test status
Simulation time 29353442 ps
CPU time 1.23 seconds
Started Aug 07 06:57:35 PM PDT 24
Finished Aug 07 06:57:37 PM PDT 24
Peak memory 217112 kb
Host smart-651f1201-6e54-4ed0-b35b-679e875a86d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429485001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3429485001
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.4146158848
Short name T139
Test name
Test status
Simulation time 28063912 ps
CPU time 1.24 seconds
Started Aug 07 06:57:31 PM PDT 24
Finished Aug 07 06:57:32 PM PDT 24
Peak memory 218216 kb
Host smart-3b1eda76-ade3-49c0-b21b-a8d3d48f7e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146158848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.4146158848
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.4132504756
Short name T48
Test name
Test status
Simulation time 34213078 ps
CPU time 0.95 seconds
Started Aug 07 06:57:35 PM PDT 24
Finished Aug 07 06:57:36 PM PDT 24
Peak memory 223700 kb
Host smart-43c77c88-c71e-4b89-952c-0a89fa5ac070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132504756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.4132504756
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1093043197
Short name T392
Test name
Test status
Simulation time 74246647 ps
CPU time 1.64 seconds
Started Aug 07 06:57:32 PM PDT 24
Finished Aug 07 06:57:34 PM PDT 24
Peak memory 217092 kb
Host smart-46bed99f-f1a8-4747-b3cd-85d545c49f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093043197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1093043197
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.1160459674
Short name T413
Test name
Test status
Simulation time 76420844 ps
CPU time 1.07 seconds
Started Aug 07 06:57:34 PM PDT 24
Finished Aug 07 06:57:36 PM PDT 24
Peak memory 219984 kb
Host smart-ba568460-5683-4593-9260-d60d6ce7fba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160459674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1160459674
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.67632891
Short name T123
Test name
Test status
Simulation time 24345061 ps
CPU time 1.16 seconds
Started Aug 07 06:57:35 PM PDT 24
Finished Aug 07 06:57:37 PM PDT 24
Peak memory 229316 kb
Host smart-db4c9f8d-3c1e-47d8-a779-1ded210045c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67632891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.67632891
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3912382498
Short name T705
Test name
Test status
Simulation time 192564918 ps
CPU time 2.21 seconds
Started Aug 07 06:57:34 PM PDT 24
Finished Aug 07 06:57:36 PM PDT 24
Peak memory 219972 kb
Host smart-60c94e0d-df71-4735-84dd-56e3768147fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912382498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3912382498
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.967788942
Short name T92
Test name
Test status
Simulation time 43882243 ps
CPU time 1.16 seconds
Started Aug 07 06:57:31 PM PDT 24
Finished Aug 07 06:57:33 PM PDT 24
Peak memory 218084 kb
Host smart-0895bbb5-2b89-412a-886a-8b0f73099b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967788942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.967788942
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3173080705
Short name T978
Test name
Test status
Simulation time 45096397 ps
CPU time 1.25 seconds
Started Aug 07 06:57:31 PM PDT 24
Finished Aug 07 06:57:32 PM PDT 24
Peak memory 225528 kb
Host smart-74daf130-27e6-4553-bdaf-6fb52b50427a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173080705 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3173080705
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1036323309
Short name T470
Test name
Test status
Simulation time 67217245 ps
CPU time 1.13 seconds
Started Aug 07 06:57:35 PM PDT 24
Finished Aug 07 06:57:36 PM PDT 24
Peak memory 216908 kb
Host smart-1827a0ad-b1a1-4cbf-8af6-949ad8d4453e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036323309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1036323309
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.424455701
Short name T797
Test name
Test status
Simulation time 84732858 ps
CPU time 1.21 seconds
Started Aug 07 06:57:32 PM PDT 24
Finished Aug 07 06:57:33 PM PDT 24
Peak memory 220192 kb
Host smart-cd2be798-503f-41b6-a762-8b1e46fc628b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424455701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.424455701
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.4004942867
Short name T898
Test name
Test status
Simulation time 32534555 ps
CPU time 0.84 seconds
Started Aug 07 06:57:33 PM PDT 24
Finished Aug 07 06:57:35 PM PDT 24
Peak memory 217140 kb
Host smart-61aca1d8-422e-44a3-badf-5cf1a0c769f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004942867 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.4004942867
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2711586686
Short name T37
Test name
Test status
Simulation time 210327064 ps
CPU time 3.05 seconds
Started Aug 07 06:57:31 PM PDT 24
Finished Aug 07 06:57:35 PM PDT 24
Peak memory 218320 kb
Host smart-1282add6-db44-41ee-bbe5-331580d74c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711586686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2711586686
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2691395932
Short name T878
Test name
Test status
Simulation time 25170816 ps
CPU time 1.03 seconds
Started Aug 07 06:55:36 PM PDT 24
Finished Aug 07 06:55:37 PM PDT 24
Peak memory 219276 kb
Host smart-a54b0b49-2986-4f3e-b2af-a252a53d6c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691395932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2691395932
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.888258661
Short name T61
Test name
Test status
Simulation time 97173549 ps
CPU time 0.89 seconds
Started Aug 07 06:55:36 PM PDT 24
Finished Aug 07 06:55:37 PM PDT 24
Peak memory 206368 kb
Host smart-8de96baa-f5a5-4232-9399-ca255e04a84c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888258661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.888258661
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1182796662
Short name T159
Test name
Test status
Simulation time 10733946 ps
CPU time 0.87 seconds
Started Aug 07 06:55:36 PM PDT 24
Finished Aug 07 06:55:37 PM PDT 24
Peak memory 215148 kb
Host smart-a2d97975-1491-45f8-b071-9ec0c072665d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182796662 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1182796662
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3081245500
Short name T638
Test name
Test status
Simulation time 89005022 ps
CPU time 1.03 seconds
Started Aug 07 06:55:36 PM PDT 24
Finished Aug 07 06:55:37 PM PDT 24
Peak memory 218104 kb
Host smart-1b3234b4-7f77-47e5-8689-77c04d545a2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081245500 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3081245500
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1953861929
Short name T70
Test name
Test status
Simulation time 28774915 ps
CPU time 0.83 seconds
Started Aug 07 06:55:37 PM PDT 24
Finished Aug 07 06:55:38 PM PDT 24
Peak memory 218324 kb
Host smart-d31fc7d3-b3de-46a1-a2aa-291028db0249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953861929 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1953861929
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.88072978
Short name T325
Test name
Test status
Simulation time 38486494 ps
CPU time 1.26 seconds
Started Aug 07 06:55:35 PM PDT 24
Finished Aug 07 06:55:36 PM PDT 24
Peak memory 217016 kb
Host smart-6d11c706-9f32-450a-b300-85d27c6af4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88072978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.88072978
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1794042497
Short name T500
Test name
Test status
Simulation time 21692727 ps
CPU time 1.09 seconds
Started Aug 07 06:55:38 PM PDT 24
Finished Aug 07 06:55:40 PM PDT 24
Peak memory 215140 kb
Host smart-2df52d47-511c-491a-bf97-01a4c6147f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794042497 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1794042497
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.274294415
Short name T355
Test name
Test status
Simulation time 19279402 ps
CPU time 0.9 seconds
Started Aug 07 06:55:34 PM PDT 24
Finished Aug 07 06:55:35 PM PDT 24
Peak memory 214912 kb
Host smart-1fc762c6-6a7e-4bcc-ae83-f0d4ed59176c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274294415 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.274294415
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2763783393
Short name T245
Test name
Test status
Simulation time 163207394 ps
CPU time 3.38 seconds
Started Aug 07 06:55:37 PM PDT 24
Finished Aug 07 06:55:40 PM PDT 24
Peak memory 218300 kb
Host smart-72e4ec72-d298-4d05-a0dd-70029fb7c3ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763783393 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2763783393
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.18444364
Short name T776
Test name
Test status
Simulation time 88055673143 ps
CPU time 1915.48 seconds
Started Aug 07 06:55:36 PM PDT 24
Finished Aug 07 07:27:32 PM PDT 24
Peak memory 225344 kb
Host smart-7101729d-0597-4bbb-a5c1-90f6618d1a4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18444364 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.18444364
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.1126989511
Short name T846
Test name
Test status
Simulation time 153201681 ps
CPU time 1.16 seconds
Started Aug 07 06:57:31 PM PDT 24
Finished Aug 07 06:57:32 PM PDT 24
Peak memory 220392 kb
Host smart-822c8898-28d1-4a84-bbd0-00c8eda93ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126989511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.1126989511
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.543921532
Short name T156
Test name
Test status
Simulation time 44716629 ps
CPU time 1.25 seconds
Started Aug 07 06:57:37 PM PDT 24
Finished Aug 07 06:57:39 PM PDT 24
Peak memory 225380 kb
Host smart-740c65e5-2d90-45b8-be32-0f346112f73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543921532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.543921532
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1493106811
Short name T452
Test name
Test status
Simulation time 10389871718 ps
CPU time 102.97 seconds
Started Aug 07 06:57:34 PM PDT 24
Finished Aug 07 06:59:18 PM PDT 24
Peak memory 220080 kb
Host smart-d43395cb-4251-4bbe-9a85-00b0d94e5cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493106811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1493106811
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1440026733
Short name T543
Test name
Test status
Simulation time 23344520 ps
CPU time 1.15 seconds
Started Aug 07 06:57:37 PM PDT 24
Finished Aug 07 06:57:39 PM PDT 24
Peak memory 219220 kb
Host smart-05c85a79-9a60-45e1-9bf3-bc79e5393ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440026733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1440026733
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3710984499
Short name T791
Test name
Test status
Simulation time 37692517 ps
CPU time 1 seconds
Started Aug 07 06:57:37 PM PDT 24
Finished Aug 07 06:57:39 PM PDT 24
Peak memory 229228 kb
Host smart-9af16afc-a154-4544-8cf5-4b35c1ac84dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710984499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3710984499
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.443624629
Short name T390
Test name
Test status
Simulation time 105135572 ps
CPU time 1.14 seconds
Started Aug 07 06:57:36 PM PDT 24
Finished Aug 07 06:57:38 PM PDT 24
Peak memory 216928 kb
Host smart-1f758758-588c-4834-b546-74341fc72d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443624629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.443624629
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.606857233
Short name T15
Test name
Test status
Simulation time 87555066 ps
CPU time 1.18 seconds
Started Aug 07 06:57:37 PM PDT 24
Finished Aug 07 06:57:38 PM PDT 24
Peak memory 219420 kb
Host smart-9a87b36f-1ecb-47af-9a4d-f881353f37f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606857233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.606857233
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.2454838517
Short name T206
Test name
Test status
Simulation time 54847988 ps
CPU time 0.92 seconds
Started Aug 07 06:57:36 PM PDT 24
Finished Aug 07 06:57:37 PM PDT 24
Peak memory 223680 kb
Host smart-a5e4d210-1d88-4fd3-81c5-7dd650f127ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454838517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2454838517
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2782816785
Short name T532
Test name
Test status
Simulation time 40546633 ps
CPU time 1.64 seconds
Started Aug 07 06:57:37 PM PDT 24
Finished Aug 07 06:57:39 PM PDT 24
Peak memory 218100 kb
Host smart-89edf3cf-6338-44e2-b66f-2e5e4fe1d971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782816785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2782816785
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.818311375
Short name T79
Test name
Test status
Simulation time 86425343 ps
CPU time 1.14 seconds
Started Aug 07 06:57:39 PM PDT 24
Finished Aug 07 06:57:40 PM PDT 24
Peak memory 219224 kb
Host smart-38eb3a46-d1ae-48a3-9612-9144fcfeded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818311375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.818311375
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.750591720
Short name T137
Test name
Test status
Simulation time 33109130 ps
CPU time 0.93 seconds
Started Aug 07 06:57:36 PM PDT 24
Finished Aug 07 06:57:37 PM PDT 24
Peak memory 219608 kb
Host smart-a4fde5bc-ad21-4bff-be03-c275157746a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750591720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.750591720
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1867816458
Short name T342
Test name
Test status
Simulation time 101996573 ps
CPU time 1.4 seconds
Started Aug 07 06:57:36 PM PDT 24
Finished Aug 07 06:57:38 PM PDT 24
Peak memory 218272 kb
Host smart-28b5de73-42cf-4217-9ba7-3fefa42ba9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867816458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1867816458
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.3987358863
Short name T632
Test name
Test status
Simulation time 36258859 ps
CPU time 1.16 seconds
Started Aug 07 06:57:37 PM PDT 24
Finished Aug 07 06:57:38 PM PDT 24
Peak memory 220940 kb
Host smart-e187d7f2-e3c3-4a44-8db4-58c85f082c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987358863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3987358863
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.2825514312
Short name T50
Test name
Test status
Simulation time 30912602 ps
CPU time 0.99 seconds
Started Aug 07 06:57:35 PM PDT 24
Finished Aug 07 06:57:36 PM PDT 24
Peak memory 223628 kb
Host smart-f9a5b713-326b-46d3-8591-6d0eb314a500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825514312 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2825514312
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2274961655
Short name T633
Test name
Test status
Simulation time 64761424 ps
CPU time 1.08 seconds
Started Aug 07 06:57:36 PM PDT 24
Finished Aug 07 06:57:38 PM PDT 24
Peak memory 216912 kb
Host smart-cd7bd784-d27f-4daa-9136-eeddcca79d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274961655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2274961655
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3896927286
Short name T789
Test name
Test status
Simulation time 77071886 ps
CPU time 1.2 seconds
Started Aug 07 06:57:37 PM PDT 24
Finished Aug 07 06:57:38 PM PDT 24
Peak memory 219816 kb
Host smart-9a819f07-f484-4d92-b5c1-433a3d860400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896927286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3896927286
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.466511273
Short name T720
Test name
Test status
Simulation time 41621844 ps
CPU time 0.94 seconds
Started Aug 07 06:57:37 PM PDT 24
Finished Aug 07 06:57:38 PM PDT 24
Peak memory 219300 kb
Host smart-4b647c90-e880-4cf7-b086-f3a2f72b8446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466511273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.466511273
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1705911911
Short name T962
Test name
Test status
Simulation time 52501373 ps
CPU time 1.74 seconds
Started Aug 07 06:57:36 PM PDT 24
Finished Aug 07 06:57:38 PM PDT 24
Peak memory 218328 kb
Host smart-1f3caaeb-f3ee-4e1d-9bc8-0bf435a73163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705911911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1705911911
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1586836787
Short name T842
Test name
Test status
Simulation time 172706025 ps
CPU time 1.15 seconds
Started Aug 07 06:57:40 PM PDT 24
Finished Aug 07 06:57:41 PM PDT 24
Peak memory 218192 kb
Host smart-85f2820e-9f24-4604-8a15-39661b9d8387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586836787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1586836787
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.661309174
Short name T162
Test name
Test status
Simulation time 83409931 ps
CPU time 0.83 seconds
Started Aug 07 06:57:35 PM PDT 24
Finished Aug 07 06:57:36 PM PDT 24
Peak memory 218348 kb
Host smart-1ff53bf1-e1fd-4416-863c-833c9185233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661309174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.661309174
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.158163757
Short name T9
Test name
Test status
Simulation time 91533043 ps
CPU time 1.28 seconds
Started Aug 07 06:57:38 PM PDT 24
Finished Aug 07 06:57:40 PM PDT 24
Peak memory 218556 kb
Host smart-f03e09a8-e511-44e3-9b5d-1b8a90338d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158163757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.158163757
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1614617793
Short name T562
Test name
Test status
Simulation time 30536683 ps
CPU time 1.3 seconds
Started Aug 07 06:57:37 PM PDT 24
Finished Aug 07 06:57:39 PM PDT 24
Peak memory 219312 kb
Host smart-28540d2f-f250-490f-93d2-6e208cebf857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614617793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1614617793
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1063634343
Short name T185
Test name
Test status
Simulation time 19389284 ps
CPU time 1.03 seconds
Started Aug 07 06:57:39 PM PDT 24
Finished Aug 07 06:57:40 PM PDT 24
Peak memory 218568 kb
Host smart-c0c428f8-82ca-48e4-a651-181da8433c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063634343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1063634343
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2303062899
Short name T343
Test name
Test status
Simulation time 93199116 ps
CPU time 1.54 seconds
Started Aug 07 06:57:36 PM PDT 24
Finished Aug 07 06:57:38 PM PDT 24
Peak memory 218564 kb
Host smart-1936d635-2be9-4ce1-9428-666b067da9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303062899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2303062899
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2574340656
Short name T735
Test name
Test status
Simulation time 117424736 ps
CPU time 1.12 seconds
Started Aug 07 06:57:41 PM PDT 24
Finished Aug 07 06:57:42 PM PDT 24
Peak memory 218332 kb
Host smart-1e4c939a-050f-49bb-9b91-e9ae2744e709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574340656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2574340656
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1641512146
Short name T652
Test name
Test status
Simulation time 22353408 ps
CPU time 0.97 seconds
Started Aug 07 06:57:41 PM PDT 24
Finished Aug 07 06:57:42 PM PDT 24
Peak memory 218456 kb
Host smart-2ecebf4e-3c4a-44f9-ade6-454b476e8045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641512146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1641512146
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/99.edn_alert.2833944983
Short name T297
Test name
Test status
Simulation time 24042049 ps
CPU time 1.14 seconds
Started Aug 07 06:57:41 PM PDT 24
Finished Aug 07 06:57:42 PM PDT 24
Peak memory 218160 kb
Host smart-74cda462-e757-4e21-96fc-7be95cc11ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833944983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2833944983
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.1345501393
Short name T47
Test name
Test status
Simulation time 41975572 ps
CPU time 1.15 seconds
Started Aug 07 06:57:53 PM PDT 24
Finished Aug 07 06:57:55 PM PDT 24
Peak memory 231876 kb
Host smart-101350c6-d89a-4c7c-99a5-35d7e1e341cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345501393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1345501393
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2499459980
Short name T371
Test name
Test status
Simulation time 397906404 ps
CPU time 2.21 seconds
Started Aug 07 06:57:42 PM PDT 24
Finished Aug 07 06:57:44 PM PDT 24
Peak memory 218792 kb
Host smart-19f68281-c300-4d8f-b806-7b791718fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499459980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2499459980
Directory /workspace/99.edn_genbits/latest
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