Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.78 98.25 93.97 97.02 93.02 96.37 99.77 92.06


Total test records in report: 1130
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T1024 /workspace/coverage/cover_reg_top/14.edn_intr_test.3346791929 Aug 08 06:04:11 PM PDT 24 Aug 08 06:04:12 PM PDT 24 32092210 ps
T283 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3367082045 Aug 08 06:04:18 PM PDT 24 Aug 08 06:04:20 PM PDT 24 31485319 ps
T1025 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3660687916 Aug 08 06:04:10 PM PDT 24 Aug 08 06:04:11 PM PDT 24 50315353 ps
T1026 /workspace/coverage/cover_reg_top/1.edn_tl_errors.4065019291 Aug 08 06:04:10 PM PDT 24 Aug 08 06:04:12 PM PDT 24 76672955 ps
T1027 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4043613878 Aug 08 06:04:14 PM PDT 24 Aug 08 06:04:15 PM PDT 24 73817562 ps
T284 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.840692460 Aug 08 06:04:13 PM PDT 24 Aug 08 06:04:14 PM PDT 24 32626306 ps
T311 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3265948264 Aug 08 06:04:06 PM PDT 24 Aug 08 06:04:08 PM PDT 24 158566665 ps
T1028 /workspace/coverage/cover_reg_top/28.edn_intr_test.482269538 Aug 08 06:04:28 PM PDT 24 Aug 08 06:04:29 PM PDT 24 15682429 ps
T1029 /workspace/coverage/cover_reg_top/12.edn_intr_test.75920605 Aug 08 06:04:17 PM PDT 24 Aug 08 06:04:18 PM PDT 24 30976266 ps
T267 /workspace/coverage/cover_reg_top/8.edn_csr_rw.236310782 Aug 08 06:04:15 PM PDT 24 Aug 08 06:04:16 PM PDT 24 18760827 ps
T1030 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3255111078 Aug 08 06:04:16 PM PDT 24 Aug 08 06:04:19 PM PDT 24 150895436 ps
T1031 /workspace/coverage/cover_reg_top/5.edn_intr_test.1677266405 Aug 08 06:04:17 PM PDT 24 Aug 08 06:04:18 PM PDT 24 10524005 ps
T285 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3290477665 Aug 08 06:04:22 PM PDT 24 Aug 08 06:04:24 PM PDT 24 94452493 ps
T286 /workspace/coverage/cover_reg_top/17.edn_csr_rw.286458778 Aug 08 06:04:30 PM PDT 24 Aug 08 06:04:31 PM PDT 24 28790460 ps
T1032 /workspace/coverage/cover_reg_top/0.edn_csr_rw.236645633 Aug 08 06:04:08 PM PDT 24 Aug 08 06:04:09 PM PDT 24 21337403 ps
T1033 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3267727858 Aug 08 06:04:15 PM PDT 24 Aug 08 06:04:18 PM PDT 24 316935922 ps
T1034 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.743048367 Aug 08 06:04:08 PM PDT 24 Aug 08 06:04:12 PM PDT 24 263231209 ps
T1035 /workspace/coverage/cover_reg_top/49.edn_intr_test.57439137 Aug 08 06:04:39 PM PDT 24 Aug 08 06:04:40 PM PDT 24 12249276 ps
T312 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3707293292 Aug 08 06:04:20 PM PDT 24 Aug 08 06:04:21 PM PDT 24 164874246 ps
T307 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2516171967 Aug 08 06:04:16 PM PDT 24 Aug 08 06:04:18 PM PDT 24 69700556 ps
T1036 /workspace/coverage/cover_reg_top/48.edn_intr_test.773868726 Aug 08 06:04:35 PM PDT 24 Aug 08 06:04:36 PM PDT 24 30925054 ps
T1037 /workspace/coverage/cover_reg_top/22.edn_intr_test.2190518428 Aug 08 06:04:43 PM PDT 24 Aug 08 06:04:44 PM PDT 24 21354902 ps
T313 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1655703604 Aug 08 06:04:17 PM PDT 24 Aug 08 06:04:18 PM PDT 24 388612890 ps
T287 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2846351957 Aug 08 06:04:18 PM PDT 24 Aug 08 06:04:20 PM PDT 24 421908216 ps
T1038 /workspace/coverage/cover_reg_top/19.edn_tl_errors.4204363466 Aug 08 06:04:42 PM PDT 24 Aug 08 06:04:45 PM PDT 24 421415407 ps
T1039 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2276233362 Aug 08 06:04:16 PM PDT 24 Aug 08 06:04:19 PM PDT 24 495708621 ps
T1040 /workspace/coverage/cover_reg_top/4.edn_intr_test.401356640 Aug 08 06:04:16 PM PDT 24 Aug 08 06:04:17 PM PDT 24 22972205 ps
T268 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2158430374 Aug 08 06:04:05 PM PDT 24 Aug 08 06:04:06 PM PDT 24 54703332 ps
T1041 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1975403716 Aug 08 06:04:40 PM PDT 24 Aug 08 06:04:41 PM PDT 24 50695748 ps
T1042 /workspace/coverage/cover_reg_top/7.edn_csr_rw.6507283 Aug 08 06:04:14 PM PDT 24 Aug 08 06:04:15 PM PDT 24 29861380 ps
T1043 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1821317162 Aug 08 06:04:38 PM PDT 24 Aug 08 06:04:41 PM PDT 24 349250746 ps
T1044 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1445643394 Aug 08 06:04:07 PM PDT 24 Aug 08 06:04:08 PM PDT 24 31143093 ps
T1045 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2569163199 Aug 08 06:04:17 PM PDT 24 Aug 08 06:04:19 PM PDT 24 60535866 ps
T1046 /workspace/coverage/cover_reg_top/3.edn_intr_test.411869054 Aug 08 06:04:09 PM PDT 24 Aug 08 06:04:10 PM PDT 24 32437776 ps
T1047 /workspace/coverage/cover_reg_top/2.edn_intr_test.397817214 Aug 08 06:04:00 PM PDT 24 Aug 08 06:04:01 PM PDT 24 54619878 ps
T1048 /workspace/coverage/cover_reg_top/13.edn_tl_errors.765015716 Aug 08 06:04:15 PM PDT 24 Aug 08 06:04:19 PM PDT 24 357270560 ps
T1049 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2576956349 Aug 08 06:04:17 PM PDT 24 Aug 08 06:04:18 PM PDT 24 36192355 ps
T1050 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.189641394 Aug 08 06:04:12 PM PDT 24 Aug 08 06:04:15 PM PDT 24 79177850 ps
T1051 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.610497521 Aug 08 06:04:15 PM PDT 24 Aug 08 06:04:16 PM PDT 24 48572180 ps
T1052 /workspace/coverage/cover_reg_top/17.edn_intr_test.2674234120 Aug 08 06:04:17 PM PDT 24 Aug 08 06:04:18 PM PDT 24 13875204 ps
T1053 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1143815766 Aug 08 06:04:12 PM PDT 24 Aug 08 06:04:15 PM PDT 24 118011389 ps
T1054 /workspace/coverage/cover_reg_top/11.edn_csr_rw.812143216 Aug 08 06:04:14 PM PDT 24 Aug 08 06:04:15 PM PDT 24 25451547 ps
T1055 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3133835213 Aug 08 06:04:15 PM PDT 24 Aug 08 06:04:18 PM PDT 24 287916203 ps
T1056 /workspace/coverage/cover_reg_top/16.edn_tl_errors.85086650 Aug 08 06:04:28 PM PDT 24 Aug 08 06:04:32 PM PDT 24 117183607 ps
T1057 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2691177862 Aug 08 06:04:19 PM PDT 24 Aug 08 06:04:20 PM PDT 24 14622391 ps
T1058 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.482323238 Aug 08 06:04:15 PM PDT 24 Aug 08 06:04:16 PM PDT 24 25003538 ps
T1059 /workspace/coverage/cover_reg_top/16.edn_intr_test.364922415 Aug 08 06:04:17 PM PDT 24 Aug 08 06:04:18 PM PDT 24 25199619 ps
T269 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2576617074 Aug 08 06:04:10 PM PDT 24 Aug 08 06:04:11 PM PDT 24 13834983 ps
T1060 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1157114148 Aug 08 06:04:25 PM PDT 24 Aug 08 06:04:26 PM PDT 24 332565939 ps
T1061 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1079023773 Aug 08 06:04:18 PM PDT 24 Aug 08 06:04:19 PM PDT 24 43814696 ps
T1062 /workspace/coverage/cover_reg_top/19.edn_csr_rw.564336492 Aug 08 06:04:35 PM PDT 24 Aug 08 06:04:36 PM PDT 24 17728332 ps
T270 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4250187542 Aug 08 06:04:00 PM PDT 24 Aug 08 06:04:02 PM PDT 24 66306531 ps
T1063 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3599868427 Aug 08 06:04:16 PM PDT 24 Aug 08 06:04:17 PM PDT 24 16202504 ps
T271 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2802786113 Aug 08 06:04:13 PM PDT 24 Aug 08 06:04:14 PM PDT 24 16141461 ps
T1064 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3365174427 Aug 08 06:04:16 PM PDT 24 Aug 08 06:04:17 PM PDT 24 33712132 ps
T1065 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1623388175 Aug 08 06:04:16 PM PDT 24 Aug 08 06:04:18 PM PDT 24 348421922 ps
T1066 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3992606242 Aug 08 06:04:23 PM PDT 24 Aug 08 06:04:25 PM PDT 24 104672845 ps
T308 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4063483417 Aug 08 06:04:21 PM PDT 24 Aug 08 06:04:25 PM PDT 24 225585372 ps
T1067 /workspace/coverage/cover_reg_top/6.edn_tl_errors.227406127 Aug 08 06:04:13 PM PDT 24 Aug 08 06:04:16 PM PDT 24 35513337 ps
T1068 /workspace/coverage/cover_reg_top/44.edn_intr_test.578286711 Aug 08 06:04:48 PM PDT 24 Aug 08 06:04:48 PM PDT 24 64797003 ps
T1069 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3169323529 Aug 08 06:04:06 PM PDT 24 Aug 08 06:04:08 PM PDT 24 26424087 ps
T1070 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2675253578 Aug 08 06:04:11 PM PDT 24 Aug 08 06:04:15 PM PDT 24 540780217 ps
T1071 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.661304495 Aug 08 06:04:13 PM PDT 24 Aug 08 06:04:24 PM PDT 24 90782013 ps
T1072 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1077776238 Aug 08 06:04:17 PM PDT 24 Aug 08 06:04:20 PM PDT 24 145284981 ps
T1073 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3434634125 Aug 08 06:04:12 PM PDT 24 Aug 08 06:04:14 PM PDT 24 31745888 ps
T1074 /workspace/coverage/cover_reg_top/25.edn_intr_test.1790202897 Aug 08 06:04:24 PM PDT 24 Aug 08 06:04:25 PM PDT 24 40502073 ps
T1075 /workspace/coverage/cover_reg_top/45.edn_intr_test.1167009452 Aug 08 06:04:23 PM PDT 24 Aug 08 06:04:24 PM PDT 24 15975757 ps
T1076 /workspace/coverage/cover_reg_top/24.edn_intr_test.2113708425 Aug 08 06:04:27 PM PDT 24 Aug 08 06:04:28 PM PDT 24 27460515 ps
T1077 /workspace/coverage/cover_reg_top/19.edn_intr_test.2652009147 Aug 08 06:04:16 PM PDT 24 Aug 08 06:04:17 PM PDT 24 16248265 ps
T1078 /workspace/coverage/cover_reg_top/33.edn_intr_test.2730113658 Aug 08 06:04:32 PM PDT 24 Aug 08 06:04:33 PM PDT 24 23032762 ps
T1079 /workspace/coverage/cover_reg_top/18.edn_intr_test.4103621909 Aug 08 06:04:17 PM PDT 24 Aug 08 06:04:18 PM PDT 24 43995280 ps
T1080 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2716945312 Aug 08 06:04:04 PM PDT 24 Aug 08 06:04:08 PM PDT 24 100761069 ps
T1081 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2080287956 Aug 08 06:04:21 PM PDT 24 Aug 08 06:04:23 PM PDT 24 480917688 ps
T1082 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3682458742 Aug 08 06:04:14 PM PDT 24 Aug 08 06:04:18 PM PDT 24 97871278 ps
T1083 /workspace/coverage/cover_reg_top/34.edn_intr_test.2953387800 Aug 08 06:04:24 PM PDT 24 Aug 08 06:04:25 PM PDT 24 24005816 ps
T1084 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2967749315 Aug 08 06:04:17 PM PDT 24 Aug 08 06:04:20 PM PDT 24 87906897 ps
T1085 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3571765349 Aug 08 06:04:00 PM PDT 24 Aug 08 06:04:01 PM PDT 24 41187621 ps
T1086 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2385480142 Aug 08 06:04:16 PM PDT 24 Aug 08 06:04:17 PM PDT 24 57655616 ps
T1087 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.339262419 Aug 08 06:04:35 PM PDT 24 Aug 08 06:04:36 PM PDT 24 123639738 ps
T1088 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1515411984 Aug 08 06:04:18 PM PDT 24 Aug 08 06:04:19 PM PDT 24 12980616 ps
T1089 /workspace/coverage/cover_reg_top/26.edn_intr_test.3027006396 Aug 08 06:04:24 PM PDT 24 Aug 08 06:04:25 PM PDT 24 53886692 ps
T1090 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1041257958 Aug 08 06:04:21 PM PDT 24 Aug 08 06:04:22 PM PDT 24 25563582 ps
T1091 /workspace/coverage/cover_reg_top/13.edn_intr_test.2984185314 Aug 08 06:04:27 PM PDT 24 Aug 08 06:04:28 PM PDT 24 37500306 ps
T1092 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1419188343 Aug 08 06:04:13 PM PDT 24 Aug 08 06:04:14 PM PDT 24 16336758 ps
T1093 /workspace/coverage/cover_reg_top/31.edn_intr_test.2799513247 Aug 08 06:04:39 PM PDT 24 Aug 08 06:04:40 PM PDT 24 23223723 ps
T272 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2676818001 Aug 08 06:04:07 PM PDT 24 Aug 08 06:04:08 PM PDT 24 16701471 ps
T1094 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.30463894 Aug 08 06:04:11 PM PDT 24 Aug 08 06:04:12 PM PDT 24 34726084 ps
T1095 /workspace/coverage/cover_reg_top/20.edn_intr_test.1028719575 Aug 08 06:04:27 PM PDT 24 Aug 08 06:04:28 PM PDT 24 13303052 ps
T276 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2262972492 Aug 08 06:04:07 PM PDT 24 Aug 08 06:04:13 PM PDT 24 234860497 ps
T1096 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2744908047 Aug 08 06:03:57 PM PDT 24 Aug 08 06:03:58 PM PDT 24 28835937 ps
T1097 /workspace/coverage/cover_reg_top/39.edn_intr_test.819494446 Aug 08 06:04:32 PM PDT 24 Aug 08 06:04:33 PM PDT 24 19562988 ps
T1098 /workspace/coverage/cover_reg_top/36.edn_intr_test.2301526192 Aug 08 06:04:40 PM PDT 24 Aug 08 06:04:41 PM PDT 24 49436215 ps
T1099 /workspace/coverage/cover_reg_top/41.edn_intr_test.3136269086 Aug 08 06:04:43 PM PDT 24 Aug 08 06:04:44 PM PDT 24 47470866 ps
T1100 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1650674228 Aug 08 06:04:14 PM PDT 24 Aug 08 06:04:16 PM PDT 24 168008514 ps
T1101 /workspace/coverage/cover_reg_top/10.edn_intr_test.226515167 Aug 08 06:04:23 PM PDT 24 Aug 08 06:04:23 PM PDT 24 12308882 ps
T1102 /workspace/coverage/cover_reg_top/32.edn_intr_test.2599535695 Aug 08 06:04:24 PM PDT 24 Aug 08 06:04:25 PM PDT 24 13395332 ps
T1103 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1744229437 Aug 08 06:04:15 PM PDT 24 Aug 08 06:04:17 PM PDT 24 55560775 ps
T1104 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2665924023 Aug 08 06:04:15 PM PDT 24 Aug 08 06:04:17 PM PDT 24 25196026 ps
T1105 /workspace/coverage/cover_reg_top/0.edn_intr_test.3071728921 Aug 08 06:04:05 PM PDT 24 Aug 08 06:04:06 PM PDT 24 63250268 ps
T273 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3455431031 Aug 08 06:04:16 PM PDT 24 Aug 08 06:04:17 PM PDT 24 17714752 ps
T1106 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1656188319 Aug 08 06:04:22 PM PDT 24 Aug 08 06:04:28 PM PDT 24 15361226 ps
T1107 /workspace/coverage/cover_reg_top/47.edn_intr_test.2171991848 Aug 08 06:04:37 PM PDT 24 Aug 08 06:04:38 PM PDT 24 15777423 ps
T1108 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1811140293 Aug 08 06:04:15 PM PDT 24 Aug 08 06:04:16 PM PDT 24 41609367 ps
T274 /workspace/coverage/cover_reg_top/1.edn_csr_rw.454966738 Aug 08 06:04:09 PM PDT 24 Aug 08 06:04:10 PM PDT 24 40663298 ps
T1109 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2727795876 Aug 08 06:04:10 PM PDT 24 Aug 08 06:04:12 PM PDT 24 84077356 ps
T277 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2888018492 Aug 08 06:04:15 PM PDT 24 Aug 08 06:04:21 PM PDT 24 260062833 ps
T1110 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3374246663 Aug 08 06:04:37 PM PDT 24 Aug 08 06:04:39 PM PDT 24 31629132 ps
T1111 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4104341073 Aug 08 06:04:36 PM PDT 24 Aug 08 06:04:38 PM PDT 24 31558778 ps
T309 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.65612006 Aug 08 06:04:08 PM PDT 24 Aug 08 06:04:11 PM PDT 24 77226191 ps
T1112 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1837472904 Aug 08 06:04:40 PM PDT 24 Aug 08 06:04:41 PM PDT 24 24151129 ps
T1113 /workspace/coverage/cover_reg_top/1.edn_intr_test.337514407 Aug 08 06:04:08 PM PDT 24 Aug 08 06:04:09 PM PDT 24 38926052 ps
T1114 /workspace/coverage/cover_reg_top/37.edn_intr_test.819983183 Aug 08 06:04:24 PM PDT 24 Aug 08 06:04:25 PM PDT 24 40814752 ps
T1115 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1207491013 Aug 08 06:04:14 PM PDT 24 Aug 08 06:04:17 PM PDT 24 39697160 ps
T1116 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.964221786 Aug 08 06:04:16 PM PDT 24 Aug 08 06:04:18 PM PDT 24 212606299 ps
T1117 /workspace/coverage/cover_reg_top/2.edn_csr_rw.4110331929 Aug 08 06:04:05 PM PDT 24 Aug 08 06:04:06 PM PDT 24 64929287 ps
T1118 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2588049846 Aug 08 06:04:34 PM PDT 24 Aug 08 06:04:36 PM PDT 24 48395950 ps
T1119 /workspace/coverage/cover_reg_top/30.edn_intr_test.2711640489 Aug 08 06:04:25 PM PDT 24 Aug 08 06:04:26 PM PDT 24 38602905 ps
T275 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.991757154 Aug 08 06:03:55 PM PDT 24 Aug 08 06:03:56 PM PDT 24 64906952 ps
T1120 /workspace/coverage/cover_reg_top/35.edn_intr_test.1597052293 Aug 08 06:04:45 PM PDT 24 Aug 08 06:04:46 PM PDT 24 30005042 ps
T1121 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3568275870 Aug 08 06:04:36 PM PDT 24 Aug 08 06:04:37 PM PDT 24 46797201 ps
T1122 /workspace/coverage/cover_reg_top/9.edn_intr_test.543632849 Aug 08 06:04:16 PM PDT 24 Aug 08 06:04:17 PM PDT 24 17019839 ps
T1123 /workspace/coverage/cover_reg_top/43.edn_intr_test.2872934235 Aug 08 06:04:27 PM PDT 24 Aug 08 06:04:28 PM PDT 24 59586217 ps
T1124 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.986981177 Aug 08 06:04:05 PM PDT 24 Aug 08 06:04:06 PM PDT 24 84090049 ps
T278 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3505672698 Aug 08 06:04:01 PM PDT 24 Aug 08 06:04:02 PM PDT 24 17446112 ps
T1125 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2710380494 Aug 08 06:04:38 PM PDT 24 Aug 08 06:04:40 PM PDT 24 36708470 ps
T1126 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4147284798 Aug 08 06:04:41 PM PDT 24 Aug 08 06:04:44 PM PDT 24 54885695 ps
T1127 /workspace/coverage/cover_reg_top/29.edn_intr_test.4277972653 Aug 08 06:04:27 PM PDT 24 Aug 08 06:04:28 PM PDT 24 41048442 ps
T1128 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1533542329 Aug 08 06:04:18 PM PDT 24 Aug 08 06:04:19 PM PDT 24 98218967 ps
T1129 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2340621281 Aug 08 06:04:17 PM PDT 24 Aug 08 06:04:18 PM PDT 24 14163053 ps
T1130 /workspace/coverage/cover_reg_top/40.edn_intr_test.913629280 Aug 08 06:04:29 PM PDT 24 Aug 08 06:04:30 PM PDT 24 16292618 ps

Test location /workspace/coverage/default/74.edn_genbits.1109908129
Short name T26
Test name
Test status
Simulation time 96212203 ps
CPU time 1.11 seconds
Started Aug 08 07:44:49 PM PDT 24
Finished Aug 08 07:44:50 PM PDT 24
Peak memory 219040 kb
Host smart-5232e195-5362-456a-9f5c-0d3da23d4a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109908129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1109908129
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1319755519
Short name T6
Test name
Test status
Simulation time 45427919 ps
CPU time 1.08 seconds
Started Aug 08 07:44:54 PM PDT 24
Finished Aug 08 07:44:56 PM PDT 24
Peak memory 229832 kb
Host smart-cd993f11-12ff-47eb-80ed-498c3bedb8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319755519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1319755519
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3994702531
Short name T1
Test name
Test status
Simulation time 63917825241 ps
CPU time 807.67 seconds
Started Aug 08 07:43:38 PM PDT 24
Finished Aug 08 07:57:05 PM PDT 24
Peak memory 220188 kb
Host smart-08771f8e-33d4-4429-a1cd-0ba8cf3ea6fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994702531 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3994702531
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.edn_alert.559138987
Short name T19
Test name
Test status
Simulation time 26893233 ps
CPU time 1.18 seconds
Started Aug 08 07:45:27 PM PDT 24
Finished Aug 08 07:45:28 PM PDT 24
Peak memory 220868 kb
Host smart-2ffd2bfa-452b-4eef-bff5-61027acda5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559138987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.559138987
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/4.edn_sec_cm.955872432
Short name T13
Test name
Test status
Simulation time 1866076593 ps
CPU time 9.06 seconds
Started Aug 08 07:43:10 PM PDT 24
Finished Aug 08 07:43:19 PM PDT 24
Peak memory 240912 kb
Host smart-d4e79d28-748e-47cf-8830-0aedbc0740b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955872432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.955872432
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3261173415
Short name T46
Test name
Test status
Simulation time 49890149 ps
CPU time 1.01 seconds
Started Aug 08 07:43:39 PM PDT 24
Finished Aug 08 07:43:40 PM PDT 24
Peak memory 218636 kb
Host smart-8caed4ba-e955-4196-b6c4-ec607db1da8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261173415 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3261173415
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.730994954
Short name T66
Test name
Test status
Simulation time 35552182 ps
CPU time 1.13 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:53 PM PDT 24
Peak memory 218620 kb
Host smart-95ceca08-4ff2-461b-b234-82ec8af67f28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730994954 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.730994954
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1951995034
Short name T64
Test name
Test status
Simulation time 844536212 ps
CPU time 9.73 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:15 PM PDT 24
Peak memory 240308 kb
Host smart-aa34a71e-b1f0-407e-b9a2-336cb086b558
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951995034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1951995034
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/134.edn_alert.1714592829
Short name T43
Test name
Test status
Simulation time 88905311 ps
CPU time 1.06 seconds
Started Aug 08 07:45:18 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 219892 kb
Host smart-c0472ee8-a0b2-42d4-bfe2-5f2993a24ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714592829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1714592829
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.369939717
Short name T37
Test name
Test status
Simulation time 106923100287 ps
CPU time 1215.5 seconds
Started Aug 08 07:43:23 PM PDT 24
Finished Aug 08 08:03:39 PM PDT 24
Peak memory 221736 kb
Host smart-0da8be7b-df92-4ec8-8f3c-8b8399f7e962
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369939717 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.369939717
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.edn_alert.683522489
Short name T251
Test name
Test status
Simulation time 153838386 ps
CPU time 1.25 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:06 PM PDT 24
Peak memory 218480 kb
Host smart-2ad21eec-c07e-4886-81f3-e74dcac2190e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683522489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.683522489
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/275.edn_genbits.2469629931
Short name T2
Test name
Test status
Simulation time 38196673 ps
CPU time 1.47 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 219956 kb
Host smart-3de8807d-0598-445d-b193-01cb57277254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469629931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2469629931
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1207920254
Short name T93
Test name
Test status
Simulation time 23637859 ps
CPU time 1.17 seconds
Started Aug 08 07:43:55 PM PDT 24
Finished Aug 08 07:43:57 PM PDT 24
Peak memory 218648 kb
Host smart-c872d958-f0fe-44c4-a28f-44d3373adc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207920254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1207920254
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/6.edn_regwen.2915054660
Short name T319
Test name
Test status
Simulation time 49667052 ps
CPU time 0.99 seconds
Started Aug 08 07:43:28 PM PDT 24
Finished Aug 08 07:43:30 PM PDT 24
Peak memory 207168 kb
Host smart-4c65c7c5-758b-4576-975a-349432525851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915054660 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2915054660
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3265948264
Short name T311
Test name
Test status
Simulation time 158566665 ps
CPU time 2.57 seconds
Started Aug 08 06:04:06 PM PDT 24
Finished Aug 08 06:04:08 PM PDT 24
Peak memory 206880 kb
Host smart-f72fb55f-558a-49a1-a228-e3aa94a9a05e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265948264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3265948264
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/17.edn_disable.4134877538
Short name T79
Test name
Test status
Simulation time 13413267 ps
CPU time 0.92 seconds
Started Aug 08 07:43:46 PM PDT 24
Finished Aug 08 07:43:47 PM PDT 24
Peak memory 216612 kb
Host smart-30310465-a96c-4810-b626-f7f9668de706
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134877538 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.4134877538
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable.3908580296
Short name T206
Test name
Test status
Simulation time 71909514 ps
CPU time 0.9 seconds
Started Aug 08 07:44:22 PM PDT 24
Finished Aug 08 07:44:23 PM PDT 24
Peak memory 216580 kb
Host smart-d7059853-b689-465d-b7f9-647185dfa8fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908580296 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3908580296
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1781935793
Short name T266
Test name
Test status
Simulation time 30948225 ps
CPU time 0.84 seconds
Started Aug 08 06:04:24 PM PDT 24
Finished Aug 08 06:04:25 PM PDT 24
Peak memory 206664 kb
Host smart-8ff67883-ae4a-4414-87f1-aa5968673f04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781935793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1781935793
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2865491039
Short name T157
Test name
Test status
Simulation time 89454830 ps
CPU time 1.21 seconds
Started Aug 08 07:44:03 PM PDT 24
Finished Aug 08 07:44:04 PM PDT 24
Peak memory 217300 kb
Host smart-5f6e8ef8-ea73-4676-aa82-7ca3d53f1c0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865491039 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2865491039
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/101.edn_alert.1734146566
Short name T304
Test name
Test status
Simulation time 23787790 ps
CPU time 1.25 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:04 PM PDT 24
Peak memory 219764 kb
Host smart-4fbb0684-7650-4893-9e6f-b5da8c9c35c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734146566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.1734146566
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/47.edn_disable.3576529075
Short name T91
Test name
Test status
Simulation time 13433276 ps
CPU time 0.96 seconds
Started Aug 08 07:44:37 PM PDT 24
Finished Aug 08 07:44:38 PM PDT 24
Peak memory 216720 kb
Host smart-1455298c-0c9b-44b5-8019-4f0d3d4f373c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576529075 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3576529075
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable.736845683
Short name T211
Test name
Test status
Simulation time 19834226 ps
CPU time 0.83 seconds
Started Aug 08 07:44:23 PM PDT 24
Finished Aug 08 07:44:24 PM PDT 24
Peak memory 216452 kb
Host smart-a7cf5dbe-1ae4-4479-b399-e286fbb12fcf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736845683 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.736845683
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/197.edn_alert.3772181779
Short name T296
Test name
Test status
Simulation time 28904101 ps
CPU time 1.26 seconds
Started Aug 08 07:45:34 PM PDT 24
Finished Aug 08 07:45:35 PM PDT 24
Peak memory 219480 kb
Host smart-23518d0a-743c-462e-bcd2-26b4b8c05d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772181779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3772181779
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert.2407554098
Short name T321
Test name
Test status
Simulation time 24662454 ps
CPU time 1.2 seconds
Started Aug 08 07:44:01 PM PDT 24
Finished Aug 08 07:44:03 PM PDT 24
Peak memory 218796 kb
Host smart-ae0ed63e-0c1b-4fd2-a4b3-117c8be6fcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407554098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2407554098
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/65.edn_alert.1308212342
Short name T190
Test name
Test status
Simulation time 48529297 ps
CPU time 1.05 seconds
Started Aug 08 07:44:46 PM PDT 24
Finished Aug 08 07:44:48 PM PDT 24
Peak memory 218392 kb
Host smart-1c17ae32-7a22-493c-af74-2b9c686544af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308212342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1308212342
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/66.edn_alert.3196277724
Short name T9
Test name
Test status
Simulation time 92452628 ps
CPU time 1.23 seconds
Started Aug 08 07:44:46 PM PDT 24
Finished Aug 08 07:44:48 PM PDT 24
Peak memory 218436 kb
Host smart-b8fe0738-7f9b-412e-abae-404516cb7365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196277724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3196277724
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.3539318418
Short name T59
Test name
Test status
Simulation time 48122812 ps
CPU time 1.5 seconds
Started Aug 08 07:45:01 PM PDT 24
Finished Aug 08 07:45:03 PM PDT 24
Peak memory 218728 kb
Host smart-f29faae8-8501-46d9-9524-b75ec65ba999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539318418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3539318418
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.1058874343
Short name T84
Test name
Test status
Simulation time 30468892 ps
CPU time 1.3 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 215600 kb
Host smart-c561a549-ee4b-4a8f-a5e3-1c926cd616af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058874343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1058874343
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/62.edn_alert.2076007985
Short name T106
Test name
Test status
Simulation time 199119132 ps
CPU time 1.32 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:43 PM PDT 24
Peak memory 219324 kb
Host smart-f69f243a-d9f9-44dc-9024-d34ba845c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076007985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2076007985
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert.2122492271
Short name T152
Test name
Test status
Simulation time 26736026 ps
CPU time 1.17 seconds
Started Aug 08 07:43:46 PM PDT 24
Finished Aug 08 07:43:47 PM PDT 24
Peak memory 220676 kb
Host smart-a2b7a33a-53d6-44b7-82b2-c4c79395adf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122492271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2122492271
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/96.edn_alert.1696254587
Short name T200
Test name
Test status
Simulation time 29486458 ps
CPU time 1.35 seconds
Started Aug 08 07:45:04 PM PDT 24
Finished Aug 08 07:45:05 PM PDT 24
Peak memory 219852 kb
Host smart-183e9327-d845-494f-a064-669e5405d114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696254587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1696254587
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/38.edn_intr.1269484108
Short name T33
Test name
Test status
Simulation time 47409925 ps
CPU time 0.9 seconds
Started Aug 08 07:44:13 PM PDT 24
Finished Aug 08 07:44:14 PM PDT 24
Peak memory 215764 kb
Host smart-a2e8d2de-b5a3-40cd-8db5-43c58bf73fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269484108 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1269484108
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/106.edn_genbits.1116313937
Short name T78
Test name
Test status
Simulation time 21052950 ps
CPU time 1.12 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:04 PM PDT 24
Peak memory 217780 kb
Host smart-f7ce2e6c-b772-4bed-a3e3-1b5c1bf34d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116313937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1116313937
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_disable.3021671223
Short name T169
Test name
Test status
Simulation time 28800551 ps
CPU time 0.87 seconds
Started Aug 08 07:44:14 PM PDT 24
Finished Aug 08 07:44:15 PM PDT 24
Peak memory 215372 kb
Host smart-634dc933-68fe-4f6d-b0ef-96b71b56c660
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021671223 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3021671223
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2990693390
Short name T232
Test name
Test status
Simulation time 18943499814 ps
CPU time 471.77 seconds
Started Aug 08 07:43:39 PM PDT 24
Finished Aug 08 07:51:31 PM PDT 24
Peak memory 223684 kb
Host smart-22abbbac-8cb7-4b24-89a7-eb847ae71216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990693390 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2990693390
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_disable.1040557300
Short name T199
Test name
Test status
Simulation time 34301291 ps
CPU time 0.9 seconds
Started Aug 08 07:43:34 PM PDT 24
Finished Aug 08 07:43:35 PM PDT 24
Peak memory 216480 kb
Host smart-ebc2f9ec-1ced-4523-bea8-90678a8937cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040557300 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1040557300
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/133.edn_alert.403666286
Short name T117
Test name
Test status
Simulation time 86044164 ps
CPU time 1.19 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 215568 kb
Host smart-cc58c603-07f4-4291-bf12-7731ca47f06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403666286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.403666286
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/247.edn_genbits.3078689042
Short name T352
Test name
Test status
Simulation time 163881590 ps
CPU time 3.17 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:48 PM PDT 24
Peak memory 220272 kb
Host smart-ba93503e-36d7-4f4d-897f-7bad7406e70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078689042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3078689042
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3125567498
Short name T31
Test name
Test status
Simulation time 19816928 ps
CPU time 1.06 seconds
Started Aug 08 07:43:06 PM PDT 24
Finished Aug 08 07:43:07 PM PDT 24
Peak memory 216260 kb
Host smart-ba9de230-4fe9-44db-83b9-ad07369520eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125567498 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3125567498
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2471474429
Short name T127
Test name
Test status
Simulation time 64386192 ps
CPU time 1.35 seconds
Started Aug 08 07:43:03 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 217184 kb
Host smart-be952d1e-9cb6-4378-b4af-c5ab4106e467
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471474429 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2471474429
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/112.edn_alert.5978890
Short name T719
Test name
Test status
Simulation time 96056330 ps
CPU time 1.24 seconds
Started Aug 08 07:45:07 PM PDT 24
Finished Aug 08 07:45:09 PM PDT 24
Peak memory 219516 kb
Host smart-c54cf680-a97e-4cf5-8320-6d2fa54761ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5978890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.5978890
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.1083914398
Short name T209
Test name
Test status
Simulation time 14251051 ps
CPU time 0.95 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 219488 kb
Host smart-0630278a-5476-4618-a136-a193e2e72325
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083914398 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1083914398
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/139.edn_alert.553972960
Short name T145
Test name
Test status
Simulation time 67591599 ps
CPU time 1.12 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 220404 kb
Host smart-93dcef19-66f1-43d7-9037-7e712d0d5074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553972960 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.553972960
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable.1377264613
Short name T845
Test name
Test status
Simulation time 28699211 ps
CPU time 0.8 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 218244 kb
Host smart-c1dd78b3-fd28-45e0-bbd9-9d7ff30dfe0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377264613 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1377264613
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.2651857241
Short name T62
Test name
Test status
Simulation time 31579939 ps
CPU time 0.92 seconds
Started Aug 08 07:43:38 PM PDT 24
Finished Aug 08 07:43:39 PM PDT 24
Peak memory 219912 kb
Host smart-8d90d43c-4e2e-40b8-be06-13329162e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651857241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2651857241
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.4033320714
Short name T218
Test name
Test status
Simulation time 199422631 ps
CPU time 1.22 seconds
Started Aug 08 07:43:42 PM PDT 24
Finished Aug 08 07:43:43 PM PDT 24
Peak memory 219752 kb
Host smart-a34e9f86-6acf-43a3-9416-841871d66c1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033320714 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.4033320714
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3413536150
Short name T207
Test name
Test status
Simulation time 2806908920 ps
CPU time 74.16 seconds
Started Aug 08 07:43:42 PM PDT 24
Finished Aug 08 07:44:57 PM PDT 24
Peak memory 219924 kb
Host smart-618e0ea9-639a-4a00-a05e-e6f50a5ead7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413536150 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3413536150
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_disable.3304663589
Short name T217
Test name
Test status
Simulation time 13907352 ps
CPU time 0.97 seconds
Started Aug 08 07:43:55 PM PDT 24
Finished Aug 08 07:43:56 PM PDT 24
Peak memory 216700 kb
Host smart-a168e030-82e4-4f9a-8217-e0595bd40daa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304663589 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3304663589
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1472087927
Short name T965
Test name
Test status
Simulation time 123376896 ps
CPU time 1.13 seconds
Started Aug 08 07:43:54 PM PDT 24
Finished Aug 08 07:43:55 PM PDT 24
Peak memory 219388 kb
Host smart-7529e30b-5725-4557-9459-38870310895f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472087927 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1472087927
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.473850388
Short name T137
Test name
Test status
Simulation time 83176605 ps
CPU time 1.17 seconds
Started Aug 08 07:44:18 PM PDT 24
Finished Aug 08 07:44:19 PM PDT 24
Peak memory 217020 kb
Host smart-6066c099-20f8-45f6-97a6-a5085f7e6f0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473850388 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.473850388
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3128056831
Short name T203
Test name
Test status
Simulation time 37545849 ps
CPU time 1.03 seconds
Started Aug 08 07:43:13 PM PDT 24
Finished Aug 08 07:43:14 PM PDT 24
Peak memory 224060 kb
Host smart-804defc0-8e5f-4313-9c13-3a64637c22fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128056831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3128056831
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/9.edn_err.535782174
Short name T191
Test name
Test status
Simulation time 25698712 ps
CPU time 1.08 seconds
Started Aug 08 07:43:26 PM PDT 24
Finished Aug 08 07:43:27 PM PDT 24
Peak memory 224340 kb
Host smart-81ff1d4a-70b9-48b8-86a9-f6b872d10166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535782174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.535782174
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/13.edn_alert_test.2230506597
Short name T247
Test name
Test status
Simulation time 39054892 ps
CPU time 0.9 seconds
Started Aug 08 07:43:35 PM PDT 24
Finished Aug 08 07:43:36 PM PDT 24
Peak memory 206584 kb
Host smart-0f587dd7-e35a-417c-a9df-2db4a9a486f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230506597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2230506597
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/100.edn_genbits.4017600989
Short name T24
Test name
Test status
Simulation time 80630716 ps
CPU time 1.08 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:06 PM PDT 24
Peak memory 217328 kb
Host smart-1e9e0969-4642-4805-8277-7dc29d03014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017600989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4017600989
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_stress_all.575640468
Short name T111
Test name
Test status
Simulation time 226360813 ps
CPU time 2.27 seconds
Started Aug 08 07:43:36 PM PDT 24
Finished Aug 08 07:43:39 PM PDT 24
Peak memory 217356 kb
Host smart-5de8cb5e-2532-4f8f-bed5-ce9f020ddb41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575640468 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.575640468
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_genbits.4214421278
Short name T75
Test name
Test status
Simulation time 67772252 ps
CPU time 1.83 seconds
Started Aug 08 07:45:10 PM PDT 24
Finished Aug 08 07:45:12 PM PDT 24
Peak memory 218804 kb
Host smart-bd009059-9ddc-4a7d-af85-b2208ebfaa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214421278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.4214421278
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2317209526
Short name T35
Test name
Test status
Simulation time 63622661 ps
CPU time 0.88 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:21 PM PDT 24
Peak memory 215508 kb
Host smart-3709bc33-13d2-497b-873f-b48c885fd4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317209526 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2317209526
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/260.edn_genbits.873959848
Short name T351
Test name
Test status
Simulation time 104111104 ps
CPU time 1.45 seconds
Started Aug 08 07:45:46 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 217744 kb
Host smart-3bd12757-56f1-4512-b594-6af8283dfc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873959848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.873959848
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_genbits.73296650
Short name T345
Test name
Test status
Simulation time 38935173 ps
CPU time 1.52 seconds
Started Aug 08 07:44:15 PM PDT 24
Finished Aug 08 07:44:16 PM PDT 24
Peak memory 219840 kb
Host smart-2ae76529-b080-4f93-ad2c-5a3f01bafbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73296650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.73296650
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.65612006
Short name T309
Test name
Test status
Simulation time 77226191 ps
CPU time 2.26 seconds
Started Aug 08 06:04:08 PM PDT 24
Finished Aug 08 06:04:11 PM PDT 24
Peak memory 207228 kb
Host smart-c5680e1a-c5ab-4e9c-90aa-e8e23b8177d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65612006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.65612006
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/10.edn_genbits.204916640
Short name T340
Test name
Test status
Simulation time 32366581 ps
CPU time 1.3 seconds
Started Aug 08 07:43:42 PM PDT 24
Finished Aug 08 07:43:43 PM PDT 24
Peak memory 218708 kb
Host smart-0ddb6fca-775e-4a92-82f7-c2da1bcf6cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204916640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.204916640
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.71291189
Short name T685
Test name
Test status
Simulation time 31183219 ps
CPU time 1.29 seconds
Started Aug 08 07:45:06 PM PDT 24
Finished Aug 08 07:45:07 PM PDT 24
Peak memory 218636 kb
Host smart-8a3b14c0-2684-4f08-81ea-cb5c0295f30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71291189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.71291189
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.162356287
Short name T330
Test name
Test status
Simulation time 141337204 ps
CPU time 1.33 seconds
Started Aug 08 07:45:06 PM PDT 24
Finished Aug 08 07:45:08 PM PDT 24
Peak memory 219048 kb
Host smart-be3df7ae-eec7-484d-a36a-d79eb455623d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162356287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.162356287
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_stress_all.2704973306
Short name T347
Test name
Test status
Simulation time 114135316 ps
CPU time 2.56 seconds
Started Aug 08 07:43:32 PM PDT 24
Finished Aug 08 07:43:35 PM PDT 24
Peak memory 215344 kb
Host smart-642fab75-a9be-4978-ab54-64e0b29e39e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704973306 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2704973306
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_genbits.3173991344
Short name T335
Test name
Test status
Simulation time 34719019 ps
CPU time 1.58 seconds
Started Aug 08 07:43:32 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 218592 kb
Host smart-331742d4-2a86-410e-9879-d0f134214e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173991344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3173991344
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1188244014
Short name T105
Test name
Test status
Simulation time 79712834 ps
CPU time 1.27 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 217412 kb
Host smart-7314ba3c-2de5-4823-86b8-98f657ca82e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188244014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1188244014
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_genbits.3897179495
Short name T341
Test name
Test status
Simulation time 58485990 ps
CPU time 1.97 seconds
Started Aug 08 07:43:44 PM PDT 24
Finished Aug 08 07:43:46 PM PDT 24
Peak memory 217412 kb
Host smart-a1c726cb-e931-4c93-a33c-cc3fc4cfdece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897179495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3897179495
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.4086703924
Short name T76
Test name
Test status
Simulation time 162149590 ps
CPU time 2.04 seconds
Started Aug 08 07:45:33 PM PDT 24
Finished Aug 08 07:45:35 PM PDT 24
Peak memory 220372 kb
Host smart-8f066f3a-a81b-414a-aa15-b24b22d53e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086703924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.4086703924
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.871768254
Short name T349
Test name
Test status
Simulation time 48779449 ps
CPU time 1.19 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:05 PM PDT 24
Peak memory 219124 kb
Host smart-e7d4e122-4502-4e67-85ff-4a15ebe12239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871768254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.871768254
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2673673335
Short name T32
Test name
Test status
Simulation time 27933910 ps
CPU time 0.94 seconds
Started Aug 08 07:43:54 PM PDT 24
Finished Aug 08 07:43:55 PM PDT 24
Peak memory 216100 kb
Host smart-fec3e442-2b30-4b2b-bc13-db8d1681bae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673673335 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2673673335
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/30.edn_alert.1703345506
Short name T224
Test name
Test status
Simulation time 28996673 ps
CPU time 1.34 seconds
Started Aug 08 07:44:05 PM PDT 24
Finished Aug 08 07:44:07 PM PDT 24
Peak memory 219660 kb
Host smart-55182b41-6221-4ac9-aeb5-8627bc08f3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703345506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1703345506
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/103.edn_alert.330122820
Short name T749
Test name
Test status
Simulation time 29467682 ps
CPU time 1.4 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:05 PM PDT 24
Peak memory 218740 kb
Host smart-9b78a5b9-b310-49ef-8d38-a1514797b2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330122820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.330122820
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/50.edn_alert.3707750807
Short name T123
Test name
Test status
Simulation time 27226285 ps
CPU time 1.24 seconds
Started Aug 08 07:44:30 PM PDT 24
Finished Aug 08 07:44:31 PM PDT 24
Peak memory 219764 kb
Host smart-8a6a784d-ad2e-427e-ba6d-67e7b0dc0916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707750807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.3707750807
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1333350931
Short name T391
Test name
Test status
Simulation time 103948814 ps
CPU time 2.2 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 220204 kb
Host smart-4df003fe-0879-4a38-a949-4855d2a6428c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333350931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1333350931
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.991757154
Short name T275
Test name
Test status
Simulation time 64906952 ps
CPU time 0.99 seconds
Started Aug 08 06:03:55 PM PDT 24
Finished Aug 08 06:03:56 PM PDT 24
Peak memory 206812 kb
Host smart-f05afa86-4f60-43c4-bd3c-7a6c0b0c1b7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991757154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.991757154
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.696816943
Short name T1012
Test name
Test status
Simulation time 60319665 ps
CPU time 1.98 seconds
Started Aug 08 06:03:53 PM PDT 24
Finished Aug 08 06:03:55 PM PDT 24
Peak memory 206816 kb
Host smart-5ea44c78-9eca-4bb9-924e-019649c30177
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696816943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.696816943
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2576617074
Short name T269
Test name
Test status
Simulation time 13834983 ps
CPU time 0.86 seconds
Started Aug 08 06:04:10 PM PDT 24
Finished Aug 08 06:04:11 PM PDT 24
Peak memory 206832 kb
Host smart-9fc645ae-e8e6-4276-a018-7e1f356baee0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576617074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2576617074
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1362300261
Short name T1001
Test name
Test status
Simulation time 24357235 ps
CPU time 1.04 seconds
Started Aug 08 06:03:54 PM PDT 24
Finished Aug 08 06:03:55 PM PDT 24
Peak memory 206880 kb
Host smart-bfb26bac-47b3-4b00-891d-26ea8e03f1e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362300261 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1362300261
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.236645633
Short name T1032
Test name
Test status
Simulation time 21337403 ps
CPU time 0.89 seconds
Started Aug 08 06:04:08 PM PDT 24
Finished Aug 08 06:04:09 PM PDT 24
Peak memory 206824 kb
Host smart-9c45fd4b-40a3-42bc-8e0e-dd4f49e5330a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236645633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.236645633
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3071728921
Short name T1105
Test name
Test status
Simulation time 63250268 ps
CPU time 0.89 seconds
Started Aug 08 06:04:05 PM PDT 24
Finished Aug 08 06:04:06 PM PDT 24
Peak memory 206680 kb
Host smart-6b557f05-b70a-44fc-83ba-040aa721a865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071728921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3071728921
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2628143083
Short name T279
Test name
Test status
Simulation time 57357467 ps
CPU time 0.9 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206828 kb
Host smart-d5b82ec4-ac45-4965-9168-7621d3b8f525
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628143083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2628143083
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2716945312
Short name T1080
Test name
Test status
Simulation time 100761069 ps
CPU time 3.47 seconds
Started Aug 08 06:04:04 PM PDT 24
Finished Aug 08 06:04:08 PM PDT 24
Peak memory 215472 kb
Host smart-e3cfe108-09c1-4d5f-8e32-64778892a9e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716945312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2716945312
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3455431031
Short name T273
Test name
Test status
Simulation time 17714752 ps
CPU time 1.09 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206916 kb
Host smart-be0cf478-8e54-4815-8946-b10f780f391d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455431031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3455431031
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2262972492
Short name T276
Test name
Test status
Simulation time 234860497 ps
CPU time 6.26 seconds
Started Aug 08 06:04:07 PM PDT 24
Finished Aug 08 06:04:13 PM PDT 24
Peak memory 206960 kb
Host smart-44e9265a-edf1-405b-bf63-c320d17e7e17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262972492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2262972492
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1664717244
Short name T265
Test name
Test status
Simulation time 105261470 ps
CPU time 0.84 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206560 kb
Host smart-45f9218a-8d2c-4847-84f8-fa31782aef38
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664717244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1664717244
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.986981177
Short name T1124
Test name
Test status
Simulation time 84090049 ps
CPU time 1.27 seconds
Started Aug 08 06:04:05 PM PDT 24
Finished Aug 08 06:04:06 PM PDT 24
Peak memory 215268 kb
Host smart-a61d1202-bc4a-4f44-a2af-5612cce455cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986981177 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.986981177
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.454966738
Short name T274
Test name
Test status
Simulation time 40663298 ps
CPU time 0.82 seconds
Started Aug 08 06:04:09 PM PDT 24
Finished Aug 08 06:04:10 PM PDT 24
Peak memory 206848 kb
Host smart-e00d7602-4083-4ed5-a4c9-6a550ee14cdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454966738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.454966738
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.337514407
Short name T1113
Test name
Test status
Simulation time 38926052 ps
CPU time 0.83 seconds
Started Aug 08 06:04:08 PM PDT 24
Finished Aug 08 06:04:09 PM PDT 24
Peak memory 206552 kb
Host smart-62e92acb-7483-46de-ba94-6d697eea9817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337514407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.337514407
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3248411665
Short name T281
Test name
Test status
Simulation time 269112319 ps
CPU time 1.41 seconds
Started Aug 08 06:04:05 PM PDT 24
Finished Aug 08 06:04:07 PM PDT 24
Peak memory 206904 kb
Host smart-99d30154-0a9f-4371-9e12-b934d2029f87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248411665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3248411665
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.4065019291
Short name T1026
Test name
Test status
Simulation time 76672955 ps
CPU time 2.55 seconds
Started Aug 08 06:04:10 PM PDT 24
Finished Aug 08 06:04:12 PM PDT 24
Peak memory 215084 kb
Host smart-74957636-4609-4829-b491-557c9abf72f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065019291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.4065019291
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1650674228
Short name T1100
Test name
Test status
Simulation time 168008514 ps
CPU time 1.34 seconds
Started Aug 08 06:04:14 PM PDT 24
Finished Aug 08 06:04:16 PM PDT 24
Peak memory 215288 kb
Host smart-0ec9d857-260e-4a08-b99d-2b1b1aef0fce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650674228 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1650674228
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2340621281
Short name T1129
Test name
Test status
Simulation time 14163053 ps
CPU time 0.91 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 206844 kb
Host smart-309ad170-8b23-41fb-82fd-60faeb569433
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340621281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2340621281
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.226515167
Short name T1101
Test name
Test status
Simulation time 12308882 ps
CPU time 0.84 seconds
Started Aug 08 06:04:23 PM PDT 24
Finished Aug 08 06:04:23 PM PDT 24
Peak memory 206716 kb
Host smart-19e18d35-57be-4673-bcb8-842db78815f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226515167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.226515167
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2846351957
Short name T287
Test name
Test status
Simulation time 421908216 ps
CPU time 1.51 seconds
Started Aug 08 06:04:18 PM PDT 24
Finished Aug 08 06:04:20 PM PDT 24
Peak memory 206760 kb
Host smart-ab60e3ea-3e8f-499a-8b1e-45147bad2594
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846351957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2846351957
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1207491013
Short name T1115
Test name
Test status
Simulation time 39697160 ps
CPU time 2.54 seconds
Started Aug 08 06:04:14 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 215120 kb
Host smart-637039e6-813e-43e5-94fc-16b80e83ac26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207491013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1207491013
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1655703604
Short name T313
Test name
Test status
Simulation time 388612890 ps
CPU time 1.59 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 205524 kb
Host smart-b74d0205-c766-4355-8a5b-a3d0df0febc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655703604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1655703604
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.610497521
Short name T1051
Test name
Test status
Simulation time 48572180 ps
CPU time 1.06 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:16 PM PDT 24
Peak memory 215140 kb
Host smart-4c970982-c4e0-4e1a-bbda-4b475665af02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610497521 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.610497521
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.812143216
Short name T1054
Test name
Test status
Simulation time 25451547 ps
CPU time 0.89 seconds
Started Aug 08 06:04:14 PM PDT 24
Finished Aug 08 06:04:15 PM PDT 24
Peak memory 206744 kb
Host smart-1d166283-e75d-408d-a8f1-7365ca4c7093
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812143216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.812143216
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.382359235
Short name T1014
Test name
Test status
Simulation time 18512118 ps
CPU time 0.81 seconds
Started Aug 08 06:04:29 PM PDT 24
Finished Aug 08 06:04:30 PM PDT 24
Peak memory 206748 kb
Host smart-587ddceb-432c-4b43-9256-e20660765dff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382359235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.382359235
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3568275870
Short name T1121
Test name
Test status
Simulation time 46797201 ps
CPU time 0.92 seconds
Started Aug 08 06:04:36 PM PDT 24
Finished Aug 08 06:04:37 PM PDT 24
Peak memory 206972 kb
Host smart-7e99176f-50ed-408a-838f-d5f3d8ed123e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568275870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3568275870
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2695609975
Short name T1000
Test name
Test status
Simulation time 244909863 ps
CPU time 2.4 seconds
Started Aug 08 06:04:14 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 215100 kb
Host smart-cb1974fa-48b5-4011-a487-bdedb14dd253
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695609975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2695609975
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3133835213
Short name T1055
Test name
Test status
Simulation time 287916203 ps
CPU time 2.48 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 215148 kb
Host smart-cc29fcd3-2a51-4748-91b0-f3c7c28ffeab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133835213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3133835213
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.30463894
Short name T1094
Test name
Test status
Simulation time 34726084 ps
CPU time 0.97 seconds
Started Aug 08 06:04:11 PM PDT 24
Finished Aug 08 06:04:12 PM PDT 24
Peak memory 207024 kb
Host smart-51da92d4-92a3-479b-bb83-6536179ed251
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30463894 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.30463894
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2131142950
Short name T1006
Test name
Test status
Simulation time 13907370 ps
CPU time 0.91 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206840 kb
Host smart-c4496b7a-5233-4001-b1cc-fc925dacee2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131142950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2131142950
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.75920605
Short name T1029
Test name
Test status
Simulation time 30976266 ps
CPU time 1.12 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 206736 kb
Host smart-b0265b04-3fe8-43c2-808b-4df6223c3829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75920605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.75920605
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3290477665
Short name T285
Test name
Test status
Simulation time 94452493 ps
CPU time 1.39 seconds
Started Aug 08 06:04:22 PM PDT 24
Finished Aug 08 06:04:24 PM PDT 24
Peak memory 206928 kb
Host smart-0107e31a-d791-4fd6-a613-bf557eb878d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290477665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3290477665
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1811140293
Short name T1108
Test name
Test status
Simulation time 41609367 ps
CPU time 1.69 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:16 PM PDT 24
Peak memory 215148 kb
Host smart-37cd3d2c-1e52-406a-9476-fe7c8f66b1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811140293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1811140293
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3994107604
Short name T302
Test name
Test status
Simulation time 145456918 ps
CPU time 1.52 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:19 PM PDT 24
Peak memory 206908 kb
Host smart-95977c2d-fb1f-4171-948e-fef897179b82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994107604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3994107604
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1623388175
Short name T1065
Test name
Test status
Simulation time 348421922 ps
CPU time 1.21 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 215260 kb
Host smart-652576f1-1aad-4c4e-8bc1-57463241c29d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623388175 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1623388175
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3962530900
Short name T280
Test name
Test status
Simulation time 41080664 ps
CPU time 0.84 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 206792 kb
Host smart-8f7fe87d-56c7-4ad4-ba55-a7d689013850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962530900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3962530900
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2984185314
Short name T1091
Test name
Test status
Simulation time 37500306 ps
CPU time 0.83 seconds
Started Aug 08 06:04:27 PM PDT 24
Finished Aug 08 06:04:28 PM PDT 24
Peak memory 206616 kb
Host smart-a841ae1a-d8c2-4f3c-94ad-e75b3a5b5daa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984185314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2984185314
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.840692460
Short name T284
Test name
Test status
Simulation time 32626306 ps
CPU time 1.15 seconds
Started Aug 08 06:04:13 PM PDT 24
Finished Aug 08 06:04:14 PM PDT 24
Peak memory 206828 kb
Host smart-043ed10e-bec8-44f9-a421-6a3a5639f69c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840692460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.840692460
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.765015716
Short name T1048
Test name
Test status
Simulation time 357270560 ps
CPU time 3.21 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:19 PM PDT 24
Peak memory 215036 kb
Host smart-d2271f6b-7459-4467-a291-22c070b223b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765015716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.765015716
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.4235789348
Short name T310
Test name
Test status
Simulation time 217851423 ps
CPU time 1.61 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206968 kb
Host smart-af555a24-fc5f-40bf-8265-30a9723aea9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235789348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.4235789348
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1460656069
Short name T1004
Test name
Test status
Simulation time 77917699 ps
CPU time 1.4 seconds
Started Aug 08 06:04:14 PM PDT 24
Finished Aug 08 06:04:15 PM PDT 24
Peak memory 215084 kb
Host smart-ea63ce77-b447-4620-a761-e604ae5657de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460656069 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1460656069
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3346791929
Short name T1024
Test name
Test status
Simulation time 32092210 ps
CPU time 0.78 seconds
Started Aug 08 06:04:11 PM PDT 24
Finished Aug 08 06:04:12 PM PDT 24
Peak memory 206496 kb
Host smart-430f1ef7-7d98-4d4e-a49a-2e67652269eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346791929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3346791929
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1079023773
Short name T1061
Test name
Test status
Simulation time 43814696 ps
CPU time 1.12 seconds
Started Aug 08 06:04:18 PM PDT 24
Finished Aug 08 06:04:19 PM PDT 24
Peak memory 206736 kb
Host smart-4be6850e-c01a-4f92-acaa-fbb7656001c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079023773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1079023773
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2675253578
Short name T1070
Test name
Test status
Simulation time 540780217 ps
CPU time 3.86 seconds
Started Aug 08 06:04:11 PM PDT 24
Finished Aug 08 06:04:15 PM PDT 24
Peak memory 219000 kb
Host smart-71444bd5-a265-4053-bc6b-1035d5498e17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675253578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2675253578
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3992606242
Short name T1066
Test name
Test status
Simulation time 104672845 ps
CPU time 2.48 seconds
Started Aug 08 06:04:23 PM PDT 24
Finished Aug 08 06:04:25 PM PDT 24
Peak memory 206980 kb
Host smart-76ecff1c-8641-4510-8799-70ab261c1cac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992606242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3992606242
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2710380494
Short name T1125
Test name
Test status
Simulation time 36708470 ps
CPU time 1.43 seconds
Started Aug 08 06:04:38 PM PDT 24
Finished Aug 08 06:04:40 PM PDT 24
Peak memory 215244 kb
Host smart-eab0c076-e684-41ca-8f5a-f15ae247d745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710380494 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2710380494
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1837472904
Short name T1112
Test name
Test status
Simulation time 24151129 ps
CPU time 0.94 seconds
Started Aug 08 06:04:40 PM PDT 24
Finished Aug 08 06:04:41 PM PDT 24
Peak memory 206728 kb
Host smart-302129cc-9eb7-48f9-ae08-1530044f81a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837472904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1837472904
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.286070787
Short name T1007
Test name
Test status
Simulation time 21763850 ps
CPU time 0.86 seconds
Started Aug 08 06:04:32 PM PDT 24
Finished Aug 08 06:04:33 PM PDT 24
Peak memory 206708 kb
Host smart-bb987920-4805-4444-9b6a-1b6daebf0779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286070787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.286070787
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.482323238
Short name T1058
Test name
Test status
Simulation time 25003538 ps
CPU time 1.11 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:16 PM PDT 24
Peak memory 206880 kb
Host smart-f3d75e23-46b0-4b24-b4ff-dbd2025aed58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482323238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.482323238
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3682458742
Short name T1082
Test name
Test status
Simulation time 97871278 ps
CPU time 3.68 seconds
Started Aug 08 06:04:14 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 215100 kb
Host smart-da05f99a-6b2d-44ce-af2c-4ccfbe47b1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682458742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3682458742
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4063483417
Short name T308
Test name
Test status
Simulation time 225585372 ps
CPU time 4.38 seconds
Started Aug 08 06:04:21 PM PDT 24
Finished Aug 08 06:04:25 PM PDT 24
Peak memory 215108 kb
Host smart-178fbd25-b9ee-4c8f-9f44-a251a7be07eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063483417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.4063483417
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1041257958
Short name T1090
Test name
Test status
Simulation time 25563582 ps
CPU time 1.21 seconds
Started Aug 08 06:04:21 PM PDT 24
Finished Aug 08 06:04:22 PM PDT 24
Peak memory 215156 kb
Host smart-03dd6462-f85b-4b91-9fb9-b5c4a501aa8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041257958 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1041257958
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1975403716
Short name T1041
Test name
Test status
Simulation time 50695748 ps
CPU time 0.83 seconds
Started Aug 08 06:04:40 PM PDT 24
Finished Aug 08 06:04:41 PM PDT 24
Peak memory 206820 kb
Host smart-3b6024d6-d9f3-4cb3-a4d8-632adfe439e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975403716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1975403716
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.364922415
Short name T1059
Test name
Test status
Simulation time 25199619 ps
CPU time 0.88 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 206704 kb
Host smart-7aa39cd5-5e20-4880-8fc4-72b7d243131b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364922415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.364922415
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2569163199
Short name T1045
Test name
Test status
Simulation time 60535866 ps
CPU time 1.36 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:19 PM PDT 24
Peak memory 206864 kb
Host smart-b7662222-95b4-4b4e-b2e7-4670d1e3e8d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569163199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2569163199
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.85086650
Short name T1056
Test name
Test status
Simulation time 117183607 ps
CPU time 4.19 seconds
Started Aug 08 06:04:28 PM PDT 24
Finished Aug 08 06:04:32 PM PDT 24
Peak memory 215016 kb
Host smart-c4d2c41a-7d70-475d-b9e1-40251b02e086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85086650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.85086650
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4147284798
Short name T1126
Test name
Test status
Simulation time 54885695 ps
CPU time 1.74 seconds
Started Aug 08 06:04:41 PM PDT 24
Finished Aug 08 06:04:44 PM PDT 24
Peak memory 206956 kb
Host smart-418f814a-22bb-4e48-9b84-fccabefb885f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147284798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4147284798
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2691177862
Short name T1057
Test name
Test status
Simulation time 14622391 ps
CPU time 1.02 seconds
Started Aug 08 06:04:19 PM PDT 24
Finished Aug 08 06:04:20 PM PDT 24
Peak memory 215140 kb
Host smart-e3c7438a-a6ed-45c7-857a-a0203c7107a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691177862 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2691177862
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.286458778
Short name T286
Test name
Test status
Simulation time 28790460 ps
CPU time 0.93 seconds
Started Aug 08 06:04:30 PM PDT 24
Finished Aug 08 06:04:31 PM PDT 24
Peak memory 206860 kb
Host smart-34ef3bb8-b998-43bf-b885-e1b50ff0a7b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286458778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.286458778
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2674234120
Short name T1052
Test name
Test status
Simulation time 13875204 ps
CPU time 0.9 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 206716 kb
Host smart-ea65c9ad-b87d-464f-a862-1c42253dd0a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674234120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2674234120
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.339262419
Short name T1087
Test name
Test status
Simulation time 123639738 ps
CPU time 1.08 seconds
Started Aug 08 06:04:35 PM PDT 24
Finished Aug 08 06:04:36 PM PDT 24
Peak memory 206920 kb
Host smart-159efa49-87fc-409a-a4ef-3aa1f0bc39e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339262419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.339262419
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2588049846
Short name T1118
Test name
Test status
Simulation time 48395950 ps
CPU time 1.79 seconds
Started Aug 08 06:04:34 PM PDT 24
Finished Aug 08 06:04:36 PM PDT 24
Peak memory 214988 kb
Host smart-a4d83f28-866b-475c-8f9c-d786acd5ea9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588049846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2588049846
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2516171967
Short name T307
Test name
Test status
Simulation time 69700556 ps
CPU time 2.27 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 207280 kb
Host smart-b1115eca-6992-4cbd-8d8a-2637dad1fb87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516171967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2516171967
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4104341073
Short name T1111
Test name
Test status
Simulation time 31558778 ps
CPU time 1.15 seconds
Started Aug 08 06:04:36 PM PDT 24
Finished Aug 08 06:04:38 PM PDT 24
Peak memory 215124 kb
Host smart-d6005fb3-3d5e-4ce0-b3a9-53bbf6e75ad4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104341073 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.4104341073
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1515411984
Short name T1088
Test name
Test status
Simulation time 12980616 ps
CPU time 0.87 seconds
Started Aug 08 06:04:18 PM PDT 24
Finished Aug 08 06:04:19 PM PDT 24
Peak memory 206636 kb
Host smart-6bbc0bf2-8ea5-4a43-8ce4-ae0412672f0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515411984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1515411984
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4103621909
Short name T1079
Test name
Test status
Simulation time 43995280 ps
CPU time 0.84 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 206640 kb
Host smart-040cf92d-96ac-424f-b61c-c71e3a286b86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103621909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4103621909
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3367082045
Short name T283
Test name
Test status
Simulation time 31485319 ps
CPU time 1.28 seconds
Started Aug 08 06:04:18 PM PDT 24
Finished Aug 08 06:04:20 PM PDT 24
Peak memory 206740 kb
Host smart-dbf798f5-f207-45f6-a393-72ada9546d9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367082045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3367082045
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1821317162
Short name T1043
Test name
Test status
Simulation time 349250746 ps
CPU time 3.34 seconds
Started Aug 08 06:04:38 PM PDT 24
Finished Aug 08 06:04:41 PM PDT 24
Peak memory 215344 kb
Host smart-464f3420-4517-4199-a40c-d0dc7d6b358e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821317162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1821317162
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.964221786
Short name T1116
Test name
Test status
Simulation time 212606299 ps
CPU time 1.8 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 207056 kb
Host smart-9396c015-402d-4008-8669-29bdc1a914ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964221786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.964221786
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3374246663
Short name T1110
Test name
Test status
Simulation time 31629132 ps
CPU time 1.46 seconds
Started Aug 08 06:04:37 PM PDT 24
Finished Aug 08 06:04:39 PM PDT 24
Peak memory 215176 kb
Host smart-c14c3750-37b3-407b-8342-2fd8893e0790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374246663 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3374246663
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.564336492
Short name T1062
Test name
Test status
Simulation time 17728332 ps
CPU time 0.84 seconds
Started Aug 08 06:04:35 PM PDT 24
Finished Aug 08 06:04:36 PM PDT 24
Peak memory 206796 kb
Host smart-b331b168-c612-43bd-b111-09a849b9d543
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564336492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.564336492
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2652009147
Short name T1077
Test name
Test status
Simulation time 16248265 ps
CPU time 0.93 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206720 kb
Host smart-c5d5a151-ff7d-4e88-9cb1-771fd4112626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652009147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2652009147
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2385480142
Short name T1086
Test name
Test status
Simulation time 57655616 ps
CPU time 1.06 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206940 kb
Host smart-c6df3e6e-223e-4fd3-b351-dd0e25c51e8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385480142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2385480142
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.4204363466
Short name T1038
Test name
Test status
Simulation time 421415407 ps
CPU time 2.68 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:04:45 PM PDT 24
Peak memory 215100 kb
Host smart-31b586e7-a3ad-4804-84fe-42f570fb5510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204363466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.4204363466
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1077776238
Short name T1072
Test name
Test status
Simulation time 145284981 ps
CPU time 3.08 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:20 PM PDT 24
Peak memory 215136 kb
Host smart-8b87d8ba-9ba9-44d8-88bc-ff96ee19111a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077776238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1077776238
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2676818001
Short name T272
Test name
Test status
Simulation time 16701471 ps
CPU time 1.06 seconds
Started Aug 08 06:04:07 PM PDT 24
Finished Aug 08 06:04:08 PM PDT 24
Peak memory 206856 kb
Host smart-1579fa92-f834-42e3-b009-299dbc61327f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676818001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2676818001
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.743048367
Short name T1034
Test name
Test status
Simulation time 263231209 ps
CPU time 3.75 seconds
Started Aug 08 06:04:08 PM PDT 24
Finished Aug 08 06:04:12 PM PDT 24
Peak memory 206728 kb
Host smart-945e278f-fd05-4d22-b8b6-7e8ddd8506d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743048367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.743048367
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3169323529
Short name T1069
Test name
Test status
Simulation time 26424087 ps
CPU time 0.9 seconds
Started Aug 08 06:04:06 PM PDT 24
Finished Aug 08 06:04:08 PM PDT 24
Peak memory 206872 kb
Host smart-3fb9ee54-b226-45f6-9860-6ff723a00f94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169323529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3169323529
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1445643394
Short name T1044
Test name
Test status
Simulation time 31143093 ps
CPU time 1.22 seconds
Started Aug 08 06:04:07 PM PDT 24
Finished Aug 08 06:04:08 PM PDT 24
Peak memory 215192 kb
Host smart-bb5c18c2-0d8b-4bf6-b038-b3848936de44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445643394 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1445643394
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.4110331929
Short name T1117
Test name
Test status
Simulation time 64929287 ps
CPU time 0.79 seconds
Started Aug 08 06:04:05 PM PDT 24
Finished Aug 08 06:04:06 PM PDT 24
Peak memory 206652 kb
Host smart-46be99f4-244e-4d9e-9573-82d2d46bb9a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110331929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.4110331929
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.397817214
Short name T1047
Test name
Test status
Simulation time 54619878 ps
CPU time 0.88 seconds
Started Aug 08 06:04:00 PM PDT 24
Finished Aug 08 06:04:01 PM PDT 24
Peak memory 206640 kb
Host smart-c25b09ab-80f1-4699-9927-b5e6b6ab0ae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397817214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.397817214
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2727795876
Short name T1109
Test name
Test status
Simulation time 84077356 ps
CPU time 1.05 seconds
Started Aug 08 06:04:10 PM PDT 24
Finished Aug 08 06:04:12 PM PDT 24
Peak memory 206912 kb
Host smart-d8c59d38-d50f-4897-8a82-f17792bb1738
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727795876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2727795876
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3685295499
Short name T1019
Test name
Test status
Simulation time 1234769546 ps
CPU time 3.09 seconds
Started Aug 08 06:04:22 PM PDT 24
Finished Aug 08 06:04:26 PM PDT 24
Peak memory 215088 kb
Host smart-eb85b695-f6d1-454d-8730-af68a38e47e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685295499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3685295499
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.76173805
Short name T301
Test name
Test status
Simulation time 98215349 ps
CPU time 2.35 seconds
Started Aug 08 06:04:05 PM PDT 24
Finished Aug 08 06:04:07 PM PDT 24
Peak memory 207088 kb
Host smart-4bb18429-284f-4407-a48f-eb4569447e52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76173805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.76173805
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1028719575
Short name T1095
Test name
Test status
Simulation time 13303052 ps
CPU time 0.85 seconds
Started Aug 08 06:04:27 PM PDT 24
Finished Aug 08 06:04:28 PM PDT 24
Peak memory 206548 kb
Host smart-1da60c0a-d2ba-468e-9660-9b29a236a79f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028719575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1028719575
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.486994829
Short name T1017
Test name
Test status
Simulation time 19209504 ps
CPU time 0.9 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:04:44 PM PDT 24
Peak memory 206572 kb
Host smart-f2c239de-b135-493b-b07f-995eb6ccca03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486994829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.486994829
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2190518428
Short name T1037
Test name
Test status
Simulation time 21354902 ps
CPU time 0.82 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:04:44 PM PDT 24
Peak memory 206596 kb
Host smart-3a154d69-67f9-4706-8076-9449d9cb7240
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190518428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2190518428
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2104872696
Short name T1003
Test name
Test status
Simulation time 17647282 ps
CPU time 0.99 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206672 kb
Host smart-e768e76c-9bf5-44b3-8ee6-83c39ba603b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104872696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2104872696
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2113708425
Short name T1076
Test name
Test status
Simulation time 27460515 ps
CPU time 0.76 seconds
Started Aug 08 06:04:27 PM PDT 24
Finished Aug 08 06:04:28 PM PDT 24
Peak memory 206500 kb
Host smart-7d08c88b-1305-45ac-9258-0145677ed09c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113708425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2113708425
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1790202897
Short name T1074
Test name
Test status
Simulation time 40502073 ps
CPU time 0.79 seconds
Started Aug 08 06:04:24 PM PDT 24
Finished Aug 08 06:04:25 PM PDT 24
Peak memory 206532 kb
Host smart-dd01bedd-0248-4982-b460-142f1b2cbd2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790202897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1790202897
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3027006396
Short name T1089
Test name
Test status
Simulation time 53886692 ps
CPU time 0.88 seconds
Started Aug 08 06:04:24 PM PDT 24
Finished Aug 08 06:04:25 PM PDT 24
Peak memory 206612 kb
Host smart-daf09a53-0c50-4005-bda5-f3d174e5b9bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027006396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3027006396
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.475912453
Short name T1016
Test name
Test status
Simulation time 29113041 ps
CPU time 0.9 seconds
Started Aug 08 06:04:39 PM PDT 24
Finished Aug 08 06:04:40 PM PDT 24
Peak memory 206712 kb
Host smart-71d4caa1-84d9-4c73-9dde-aa93e33a7703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475912453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.475912453
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.482269538
Short name T1028
Test name
Test status
Simulation time 15682429 ps
CPU time 0.89 seconds
Started Aug 08 06:04:28 PM PDT 24
Finished Aug 08 06:04:29 PM PDT 24
Peak memory 206700 kb
Host smart-146ad53f-434d-4c62-8f10-779a8d90f699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482269538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.482269538
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.4277972653
Short name T1127
Test name
Test status
Simulation time 41048442 ps
CPU time 0.9 seconds
Started Aug 08 06:04:27 PM PDT 24
Finished Aug 08 06:04:28 PM PDT 24
Peak memory 206756 kb
Host smart-c9fd0643-7116-4462-bbc0-24d17d6b2ab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277972653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.4277972653
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3599868427
Short name T1063
Test name
Test status
Simulation time 16202504 ps
CPU time 1.17 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206928 kb
Host smart-b5c1599e-fe40-48f4-a553-ae91c50848c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599868427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3599868427
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2276233362
Short name T1039
Test name
Test status
Simulation time 495708621 ps
CPU time 3.26 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:19 PM PDT 24
Peak memory 206752 kb
Host smart-dd1626dc-35a1-4db8-b42a-09990aa67801
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276233362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2276233362
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2158430374
Short name T268
Test name
Test status
Simulation time 54703332 ps
CPU time 0.83 seconds
Started Aug 08 06:04:05 PM PDT 24
Finished Aug 08 06:04:06 PM PDT 24
Peak memory 206628 kb
Host smart-300ba553-f4af-4c46-9a32-67c74f5219a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158430374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2158430374
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3660687916
Short name T1025
Test name
Test status
Simulation time 50315353 ps
CPU time 1.5 seconds
Started Aug 08 06:04:10 PM PDT 24
Finished Aug 08 06:04:11 PM PDT 24
Peak memory 215172 kb
Host smart-2b55a855-0b3b-4517-85ab-3789637e677c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660687916 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3660687916
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2744908047
Short name T1096
Test name
Test status
Simulation time 28835937 ps
CPU time 0.98 seconds
Started Aug 08 06:03:57 PM PDT 24
Finished Aug 08 06:03:58 PM PDT 24
Peak memory 207020 kb
Host smart-e1381b0e-0fbb-42d9-b1e0-bac18d1dc0b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744908047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2744908047
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.411869054
Short name T1046
Test name
Test status
Simulation time 32437776 ps
CPU time 0.83 seconds
Started Aug 08 06:04:09 PM PDT 24
Finished Aug 08 06:04:10 PM PDT 24
Peak memory 206672 kb
Host smart-d96f9b69-b8bb-4643-8efd-04a0274ef7e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411869054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.411869054
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3571765349
Short name T1085
Test name
Test status
Simulation time 41187621 ps
CPU time 1.19 seconds
Started Aug 08 06:04:00 PM PDT 24
Finished Aug 08 06:04:01 PM PDT 24
Peak memory 206944 kb
Host smart-9b04c0f5-c844-49e7-a789-85d598d83275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571765349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3571765349
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1310533444
Short name T1013
Test name
Test status
Simulation time 115400768 ps
CPU time 2.51 seconds
Started Aug 08 06:04:06 PM PDT 24
Finished Aug 08 06:04:09 PM PDT 24
Peak memory 215088 kb
Host smart-6693d4dd-91f7-463f-9961-443ca7d5ad42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310533444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1310533444
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1281241958
Short name T303
Test name
Test status
Simulation time 222416012 ps
CPU time 1.69 seconds
Started Aug 08 06:04:07 PM PDT 24
Finished Aug 08 06:04:09 PM PDT 24
Peak memory 207092 kb
Host smart-6aba328c-ceb8-413d-8ad2-67e6a1a564e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281241958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1281241958
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2711640489
Short name T1119
Test name
Test status
Simulation time 38602905 ps
CPU time 0.87 seconds
Started Aug 08 06:04:25 PM PDT 24
Finished Aug 08 06:04:26 PM PDT 24
Peak memory 206656 kb
Host smart-9d69001b-d555-4663-94aa-dac8dbabf095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711640489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2711640489
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2799513247
Short name T1093
Test name
Test status
Simulation time 23223723 ps
CPU time 0.88 seconds
Started Aug 08 06:04:39 PM PDT 24
Finished Aug 08 06:04:40 PM PDT 24
Peak memory 206728 kb
Host smart-2869d414-466e-4fad-83a1-e89b51db2212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799513247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2799513247
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2599535695
Short name T1102
Test name
Test status
Simulation time 13395332 ps
CPU time 0.88 seconds
Started Aug 08 06:04:24 PM PDT 24
Finished Aug 08 06:04:25 PM PDT 24
Peak memory 206720 kb
Host smart-8bb9aba5-27e0-4370-a30b-6632a740ecc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599535695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2599535695
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2730113658
Short name T1078
Test name
Test status
Simulation time 23032762 ps
CPU time 0.86 seconds
Started Aug 08 06:04:32 PM PDT 24
Finished Aug 08 06:04:33 PM PDT 24
Peak memory 206720 kb
Host smart-da33f16d-cb19-45eb-98b4-b2228f8cf364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730113658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2730113658
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2953387800
Short name T1083
Test name
Test status
Simulation time 24005816 ps
CPU time 0.86 seconds
Started Aug 08 06:04:24 PM PDT 24
Finished Aug 08 06:04:25 PM PDT 24
Peak memory 206592 kb
Host smart-39d7309d-1408-4c76-bbff-949ce302dbe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953387800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2953387800
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1597052293
Short name T1120
Test name
Test status
Simulation time 30005042 ps
CPU time 0.79 seconds
Started Aug 08 06:04:45 PM PDT 24
Finished Aug 08 06:04:46 PM PDT 24
Peak memory 206528 kb
Host smart-a58be281-a697-46f4-a7f0-ed7ed234055e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597052293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1597052293
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2301526192
Short name T1098
Test name
Test status
Simulation time 49436215 ps
CPU time 0.84 seconds
Started Aug 08 06:04:40 PM PDT 24
Finished Aug 08 06:04:41 PM PDT 24
Peak memory 206748 kb
Host smart-5d497077-63a2-499b-9191-682d9ec7ba60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301526192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2301526192
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.819983183
Short name T1114
Test name
Test status
Simulation time 40814752 ps
CPU time 0.8 seconds
Started Aug 08 06:04:24 PM PDT 24
Finished Aug 08 06:04:25 PM PDT 24
Peak memory 206692 kb
Host smart-8bf1807d-b2e1-4e5c-a28e-dc8d507cb1d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819983183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.819983183
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.4046701152
Short name T1010
Test name
Test status
Simulation time 27893233 ps
CPU time 0.89 seconds
Started Aug 08 06:04:24 PM PDT 24
Finished Aug 08 06:04:25 PM PDT 24
Peak memory 206680 kb
Host smart-5d6cd093-cbfe-42bb-ab56-6d011a1f34aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046701152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.4046701152
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.819494446
Short name T1097
Test name
Test status
Simulation time 19562988 ps
CPU time 0.82 seconds
Started Aug 08 06:04:32 PM PDT 24
Finished Aug 08 06:04:33 PM PDT 24
Peak memory 206568 kb
Host smart-f165799f-4fc1-4e32-bede-d3ccf4ccaaf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819494446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.819494446
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4250187542
Short name T270
Test name
Test status
Simulation time 66306531 ps
CPU time 1.2 seconds
Started Aug 08 06:04:00 PM PDT 24
Finished Aug 08 06:04:02 PM PDT 24
Peak memory 206936 kb
Host smart-3ebc91c4-286d-48ea-8762-52a215d06ea6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250187542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.4250187542
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2888018492
Short name T277
Test name
Test status
Simulation time 260062833 ps
CPU time 6.28 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:21 PM PDT 24
Peak memory 206792 kb
Host smart-b553238c-1e89-45c1-826a-cc3915859354
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888018492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2888018492
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1781009251
Short name T1002
Test name
Test status
Simulation time 50084107 ps
CPU time 0.94 seconds
Started Aug 08 06:04:06 PM PDT 24
Finished Aug 08 06:04:07 PM PDT 24
Peak memory 206828 kb
Host smart-abdb7369-6ffa-446d-be60-a3340911c1a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781009251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1781009251
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.36363923
Short name T1011
Test name
Test status
Simulation time 36889077 ps
CPU time 1.35 seconds
Started Aug 08 06:04:24 PM PDT 24
Finished Aug 08 06:04:30 PM PDT 24
Peak memory 215396 kb
Host smart-11ecd6ba-ac46-4052-a26c-41961b099248
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36363923 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.36363923
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3505672698
Short name T278
Test name
Test status
Simulation time 17446112 ps
CPU time 0.98 seconds
Started Aug 08 06:04:01 PM PDT 24
Finished Aug 08 06:04:02 PM PDT 24
Peak memory 206824 kb
Host smart-56fa04e4-cd76-4d79-8fb8-805bd4889a6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505672698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3505672698
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.401356640
Short name T1040
Test name
Test status
Simulation time 22972205 ps
CPU time 0.82 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206644 kb
Host smart-3da2c178-e516-4296-b602-8d6d9bc8b42f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401356640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.401356640
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1157114148
Short name T1060
Test name
Test status
Simulation time 332565939 ps
CPU time 1.03 seconds
Started Aug 08 06:04:25 PM PDT 24
Finished Aug 08 06:04:26 PM PDT 24
Peak memory 206968 kb
Host smart-ac136d7c-e914-4161-86ca-9f75b2b3e510
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157114148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1157114148
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2897174910
Short name T1018
Test name
Test status
Simulation time 221952355 ps
CPU time 2.26 seconds
Started Aug 08 06:04:10 PM PDT 24
Finished Aug 08 06:04:13 PM PDT 24
Peak memory 215108 kb
Host smart-2f68497f-4161-4261-bb63-4d4945b282b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897174910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2897174910
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1143815766
Short name T1053
Test name
Test status
Simulation time 118011389 ps
CPU time 2.52 seconds
Started Aug 08 06:04:12 PM PDT 24
Finished Aug 08 06:04:15 PM PDT 24
Peak memory 206024 kb
Host smart-aa42e0f7-64cc-4274-bb3d-a419f40baa8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143815766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1143815766
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.913629280
Short name T1130
Test name
Test status
Simulation time 16292618 ps
CPU time 0.88 seconds
Started Aug 08 06:04:29 PM PDT 24
Finished Aug 08 06:04:30 PM PDT 24
Peak memory 206632 kb
Host smart-7fe665af-c1f3-4a3b-a476-2fa620907e9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913629280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.913629280
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3136269086
Short name T1099
Test name
Test status
Simulation time 47470866 ps
CPU time 0.81 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:04:44 PM PDT 24
Peak memory 206496 kb
Host smart-042c782f-be02-469f-a890-2692507fd258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136269086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3136269086
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3512075551
Short name T1022
Test name
Test status
Simulation time 15192844 ps
CPU time 0.89 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:04:43 PM PDT 24
Peak memory 206748 kb
Host smart-e7c54e25-87da-42e6-bb72-ba31ef65aa85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512075551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3512075551
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2872934235
Short name T1123
Test name
Test status
Simulation time 59586217 ps
CPU time 0.85 seconds
Started Aug 08 06:04:27 PM PDT 24
Finished Aug 08 06:04:28 PM PDT 24
Peak memory 206652 kb
Host smart-c5bcba25-be82-478f-8e6a-bd27e983eeac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872934235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2872934235
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.578286711
Short name T1068
Test name
Test status
Simulation time 64797003 ps
CPU time 0.8 seconds
Started Aug 08 06:04:48 PM PDT 24
Finished Aug 08 06:04:48 PM PDT 24
Peak memory 206524 kb
Host smart-dea4d467-a865-4e59-b194-c1dfb8e41c67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578286711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.578286711
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1167009452
Short name T1075
Test name
Test status
Simulation time 15975757 ps
CPU time 0.87 seconds
Started Aug 08 06:04:23 PM PDT 24
Finished Aug 08 06:04:24 PM PDT 24
Peak memory 206620 kb
Host smart-424dad46-47a1-4671-9a5a-bc076a867bb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167009452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1167009452
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.983624654
Short name T1008
Test name
Test status
Simulation time 17471110 ps
CPU time 0.94 seconds
Started Aug 08 06:04:39 PM PDT 24
Finished Aug 08 06:04:40 PM PDT 24
Peak memory 206608 kb
Host smart-371b784a-a7f5-4fbe-a418-8801fe1f44e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983624654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.983624654
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2171991848
Short name T1107
Test name
Test status
Simulation time 15777423 ps
CPU time 0.93 seconds
Started Aug 08 06:04:37 PM PDT 24
Finished Aug 08 06:04:38 PM PDT 24
Peak memory 206888 kb
Host smart-480e5b5f-3247-4d9e-98b1-20636ce87d3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171991848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2171991848
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.773868726
Short name T1036
Test name
Test status
Simulation time 30925054 ps
CPU time 0.82 seconds
Started Aug 08 06:04:35 PM PDT 24
Finished Aug 08 06:04:36 PM PDT 24
Peak memory 206548 kb
Host smart-4b49d057-d40e-43a8-9eb9-827b23a26ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773868726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.773868726
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.57439137
Short name T1035
Test name
Test status
Simulation time 12249276 ps
CPU time 0.87 seconds
Started Aug 08 06:04:39 PM PDT 24
Finished Aug 08 06:04:40 PM PDT 24
Peak memory 206636 kb
Host smart-39c8aa0a-beb1-4223-9d2e-7bc7b7d51fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57439137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.57439137
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3365174427
Short name T1064
Test name
Test status
Simulation time 33712132 ps
CPU time 1.5 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 215208 kb
Host smart-fd91f131-34d0-419e-8f72-f4b04dea282e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365174427 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3365174427
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.152920305
Short name T1020
Test name
Test status
Simulation time 25792460 ps
CPU time 0.87 seconds
Started Aug 08 06:04:18 PM PDT 24
Finished Aug 08 06:04:19 PM PDT 24
Peak memory 206840 kb
Host smart-00d70a58-b965-44d7-a67a-fbdcc2f4554b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152920305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.152920305
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1677266405
Short name T1031
Test name
Test status
Simulation time 10524005 ps
CPU time 0.81 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 206560 kb
Host smart-dd717bd8-f33d-40c1-a305-76191ec5984d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677266405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1677266405
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2576956349
Short name T1049
Test name
Test status
Simulation time 36192355 ps
CPU time 1.12 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 206976 kb
Host smart-a316f04e-2822-4001-ba7e-c15f62a438ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576956349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2576956349
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2967749315
Short name T1084
Test name
Test status
Simulation time 87906897 ps
CPU time 2.96 seconds
Started Aug 08 06:04:17 PM PDT 24
Finished Aug 08 06:04:20 PM PDT 24
Peak memory 215176 kb
Host smart-c11d8258-0517-45ca-83f5-08f71d340b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967749315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2967749315
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3707293292
Short name T312
Test name
Test status
Simulation time 164874246 ps
CPU time 1.55 seconds
Started Aug 08 06:04:20 PM PDT 24
Finished Aug 08 06:04:21 PM PDT 24
Peak memory 207044 kb
Host smart-7ead1780-03c7-4084-b4dc-6b0cb0c693c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707293292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3707293292
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3434634125
Short name T1073
Test name
Test status
Simulation time 31745888 ps
CPU time 1.61 seconds
Started Aug 08 06:04:12 PM PDT 24
Finished Aug 08 06:04:14 PM PDT 24
Peak memory 215208 kb
Host smart-f2270bd1-edcf-445a-8fcc-b8ac6bccbf4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434634125 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3434634125
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2802786113
Short name T271
Test name
Test status
Simulation time 16141461 ps
CPU time 0.91 seconds
Started Aug 08 06:04:13 PM PDT 24
Finished Aug 08 06:04:14 PM PDT 24
Peak memory 206888 kb
Host smart-ca6409e5-582a-47f8-8f0b-9a91311d4cfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802786113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2802786113
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1936315844
Short name T1009
Test name
Test status
Simulation time 98941707 ps
CPU time 0.82 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206448 kb
Host smart-0240fdf0-1425-4dce-958a-a0aa9014ba52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936315844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1936315844
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.661304495
Short name T1071
Test name
Test status
Simulation time 90782013 ps
CPU time 1.26 seconds
Started Aug 08 06:04:13 PM PDT 24
Finished Aug 08 06:04:24 PM PDT 24
Peak memory 206980 kb
Host smart-fe91c0a2-5d7a-4790-9576-2cedcaa53dfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661304495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.661304495
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.227406127
Short name T1067
Test name
Test status
Simulation time 35513337 ps
CPU time 2.25 seconds
Started Aug 08 06:04:13 PM PDT 24
Finished Aug 08 06:04:16 PM PDT 24
Peak memory 215180 kb
Host smart-702a0c1a-26cf-4751-a942-852e609ab94d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227406127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.227406127
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1744229437
Short name T1103
Test name
Test status
Simulation time 55560775 ps
CPU time 1.71 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206880 kb
Host smart-21ec8d26-0bb3-4b5f-a0f7-9d508f8b8e18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744229437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1744229437
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2239363989
Short name T1023
Test name
Test status
Simulation time 17942255 ps
CPU time 1.14 seconds
Started Aug 08 06:04:12 PM PDT 24
Finished Aug 08 06:04:13 PM PDT 24
Peak memory 215228 kb
Host smart-2df218a1-8ea7-48b4-b285-959cf363d164
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239363989 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2239363989
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.6507283
Short name T1042
Test name
Test status
Simulation time 29861380 ps
CPU time 0.93 seconds
Started Aug 08 06:04:14 PM PDT 24
Finished Aug 08 06:04:15 PM PDT 24
Peak memory 206604 kb
Host smart-e7ffe0fe-da55-4146-b98a-c936074a8813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6507283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.6507283
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2598445479
Short name T1005
Test name
Test status
Simulation time 24912471 ps
CPU time 0.87 seconds
Started Aug 08 06:04:13 PM PDT 24
Finished Aug 08 06:04:14 PM PDT 24
Peak memory 206612 kb
Host smart-961d085a-dc8a-4937-8e66-8d6367fe8b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598445479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2598445479
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1419188343
Short name T1092
Test name
Test status
Simulation time 16336758 ps
CPU time 1 seconds
Started Aug 08 06:04:13 PM PDT 24
Finished Aug 08 06:04:14 PM PDT 24
Peak memory 206760 kb
Host smart-e2b2ec84-3e07-4b31-b07e-077961735e2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419188343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1419188343
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2509715164
Short name T1015
Test name
Test status
Simulation time 154078802 ps
CPU time 2.85 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 215008 kb
Host smart-4662840e-fad7-4ec5-8c56-a102cffe08ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509715164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2509715164
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3267727858
Short name T1033
Test name
Test status
Simulation time 316935922 ps
CPU time 2.44 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:18 PM PDT 24
Peak memory 215024 kb
Host smart-10118195-33a2-41d5-9006-dcf632d81e61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267727858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3267727858
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2080287956
Short name T1081
Test name
Test status
Simulation time 480917688 ps
CPU time 1.6 seconds
Started Aug 08 06:04:21 PM PDT 24
Finished Aug 08 06:04:23 PM PDT 24
Peak memory 215260 kb
Host smart-b437c2f0-9e50-46d8-aab4-7fed572ecde6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080287956 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2080287956
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.236310782
Short name T267
Test name
Test status
Simulation time 18760827 ps
CPU time 0.82 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:16 PM PDT 24
Peak memory 206652 kb
Host smart-876dc0f0-4ac8-4a80-8ff3-4163bc7a8474
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236310782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.236310782
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3188588155
Short name T999
Test name
Test status
Simulation time 10727038 ps
CPU time 0.82 seconds
Started Aug 08 06:04:13 PM PDT 24
Finished Aug 08 06:04:14 PM PDT 24
Peak memory 206712 kb
Host smart-e787ab9c-1ce6-493d-a03a-9012fbf58fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188588155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3188588155
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1656188319
Short name T1106
Test name
Test status
Simulation time 15361226 ps
CPU time 1.03 seconds
Started Aug 08 06:04:22 PM PDT 24
Finished Aug 08 06:04:28 PM PDT 24
Peak memory 207012 kb
Host smart-a62869d2-23e2-4701-8cc1-481e3483db47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656188319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1656188319
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2744282561
Short name T1021
Test name
Test status
Simulation time 146059563 ps
CPU time 1.69 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 215564 kb
Host smart-f58248cb-d5b5-4790-bbfc-cabdae34f503
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744282561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2744282561
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.189641394
Short name T1050
Test name
Test status
Simulation time 79177850 ps
CPU time 2.31 seconds
Started Aug 08 06:04:12 PM PDT 24
Finished Aug 08 06:04:15 PM PDT 24
Peak memory 207048 kb
Host smart-f016bc58-618d-4216-8d8d-e2ae6fd7f1ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189641394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.189641394
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4043613878
Short name T1027
Test name
Test status
Simulation time 73817562 ps
CPU time 1.11 seconds
Started Aug 08 06:04:14 PM PDT 24
Finished Aug 08 06:04:15 PM PDT 24
Peak memory 215100 kb
Host smart-72151bb1-4ad4-4050-8662-9797e68a1397
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043613878 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4043613878
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2691151170
Short name T282
Test name
Test status
Simulation time 44381748 ps
CPU time 0.96 seconds
Started Aug 08 06:04:14 PM PDT 24
Finished Aug 08 06:04:15 PM PDT 24
Peak memory 206772 kb
Host smart-3b8b3fbe-81d4-402f-801e-75076def5405
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691151170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2691151170
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.543632849
Short name T1122
Test name
Test status
Simulation time 17019839 ps
CPU time 0.87 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206744 kb
Host smart-81a7de39-9380-4b96-8bba-690d784e45d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543632849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.543632849
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2665924023
Short name T1104
Test name
Test status
Simulation time 25196026 ps
CPU time 1.16 seconds
Started Aug 08 06:04:15 PM PDT 24
Finished Aug 08 06:04:17 PM PDT 24
Peak memory 206964 kb
Host smart-2d1211a9-87d4-48d8-b34d-a7e4265774e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665924023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2665924023
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3255111078
Short name T1030
Test name
Test status
Simulation time 150895436 ps
CPU time 3.14 seconds
Started Aug 08 06:04:16 PM PDT 24
Finished Aug 08 06:04:19 PM PDT 24
Peak memory 215064 kb
Host smart-de008b77-ac12-4a19-a675-6584e213e3e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255111078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3255111078
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1533542329
Short name T1128
Test name
Test status
Simulation time 98218967 ps
CPU time 1.69 seconds
Started Aug 08 06:04:18 PM PDT 24
Finished Aug 08 06:04:19 PM PDT 24
Peak memory 206956 kb
Host smart-7f890d5b-80f0-4a9a-91d7-0d0f70ba05f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533542329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1533542329
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.465576334
Short name T798
Test name
Test status
Simulation time 24083554 ps
CPU time 1.23 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 215536 kb
Host smart-1d876297-c031-4fd4-b9fd-608861dc9388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465576334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.465576334
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1872461481
Short name T966
Test name
Test status
Simulation time 17005503 ps
CPU time 0.94 seconds
Started Aug 08 07:43:03 PM PDT 24
Finished Aug 08 07:43:04 PM PDT 24
Peak memory 206852 kb
Host smart-900c64e4-a0df-457a-9682-30dda008dd55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872461481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1872461481
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2481814619
Short name T222
Test name
Test status
Simulation time 13821105 ps
CPU time 0.94 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 216676 kb
Host smart-1ef6b6b4-9e98-496e-933d-fcf79ba57a63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481814619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2481814619
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.4069703812
Short name T868
Test name
Test status
Simulation time 87141665 ps
CPU time 1.09 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 07:43:06 PM PDT 24
Peak memory 219460 kb
Host smart-20b471b5-96a3-4812-95da-e42c22feeb85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069703812 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.4069703812
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.3678635587
Short name T979
Test name
Test status
Simulation time 27281406 ps
CPU time 1.03 seconds
Started Aug 08 07:43:09 PM PDT 24
Finished Aug 08 07:43:11 PM PDT 24
Peak memory 220168 kb
Host smart-0ca8d861-38b7-4525-b654-4961e7ee18e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678635587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3678635587
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1977937279
Short name T690
Test name
Test status
Simulation time 95762962 ps
CPU time 1.31 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:06 PM PDT 24
Peak memory 217408 kb
Host smart-f72168fe-56ed-4cfb-ad96-a5d785a80536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977937279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1977937279
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2782827127
Short name T689
Test name
Test status
Simulation time 28236062 ps
CPU time 0.95 seconds
Started Aug 08 07:43:12 PM PDT 24
Finished Aug 08 07:43:13 PM PDT 24
Peak memory 216100 kb
Host smart-7887ab3b-e122-425a-84c6-e5dfaf541450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782827127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2782827127
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.788664060
Short name T29
Test name
Test status
Simulation time 15022223 ps
CPU time 0.94 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:06 PM PDT 24
Peak memory 207104 kb
Host smart-c08b166a-95dd-4e7b-9479-b5f7a1784f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788664060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.788664060
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3891081042
Short name T63
Test name
Test status
Simulation time 2801050403 ps
CPU time 9.86 seconds
Started Aug 08 07:43:06 PM PDT 24
Finished Aug 08 07:43:16 PM PDT 24
Peak memory 240864 kb
Host smart-5783a7eb-b781-436b-a8f5-e9be7bcb7d46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891081042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3891081042
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.768429587
Short name T805
Test name
Test status
Simulation time 138975649 ps
CPU time 0.95 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:06 PM PDT 24
Peak memory 215308 kb
Host smart-1db78e16-e8d5-4920-809b-f9eb740dabc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768429587 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.768429587
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2715208432
Short name T598
Test name
Test status
Simulation time 327063822 ps
CPU time 3.66 seconds
Started Aug 08 07:43:02 PM PDT 24
Finished Aug 08 07:43:06 PM PDT 24
Peak memory 215304 kb
Host smart-486bb9cd-53a5-4cc4-b22c-b200ccee0aaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715208432 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2715208432
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.4015952754
Short name T921
Test name
Test status
Simulation time 97465179608 ps
CPU time 1985.01 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 08:16:10 PM PDT 24
Peak memory 228960 kb
Host smart-808055d9-1c92-41b1-ac8e-5b0a9f3bc435
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015952754 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.4015952754
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1149996983
Short name T585
Test name
Test status
Simulation time 20752110 ps
CPU time 1.08 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 219500 kb
Host smart-22e4107b-07af-48e5-b909-17c9b69d51c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149996983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1149996983
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.198998462
Short name T630
Test name
Test status
Simulation time 25724664 ps
CPU time 0.94 seconds
Started Aug 08 07:43:13 PM PDT 24
Finished Aug 08 07:43:15 PM PDT 24
Peak memory 206852 kb
Host smart-dc1dfc23-d384-4a36-91fb-2b912c9dfd35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198998462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.198998462
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2884967745
Short name T183
Test name
Test status
Simulation time 33214206 ps
CPU time 0.86 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 07:43:05 PM PDT 24
Peak memory 216620 kb
Host smart-b90e5a4a-876e-4be2-bda6-44c521b84c64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884967745 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2884967745
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.1613549365
Short name T216
Test name
Test status
Simulation time 33946971 ps
CPU time 1.37 seconds
Started Aug 08 07:43:12 PM PDT 24
Finished Aug 08 07:43:14 PM PDT 24
Peak memory 220016 kb
Host smart-423aba5a-9411-41ed-907c-719c14f9dfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613549365 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1613549365
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.51027818
Short name T646
Test name
Test status
Simulation time 41498272 ps
CPU time 1.44 seconds
Started Aug 08 07:43:02 PM PDT 24
Finished Aug 08 07:43:04 PM PDT 24
Peak memory 218616 kb
Host smart-41f02c4d-1a0d-4f6f-979b-750bb3716a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51027818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.51027818
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.2702952416
Short name T801
Test name
Test status
Simulation time 44187309 ps
CPU time 0.93 seconds
Started Aug 08 07:43:06 PM PDT 24
Finished Aug 08 07:43:07 PM PDT 24
Peak memory 207112 kb
Host smart-f6351765-ce76-4db1-87e6-bdb95af63903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702952416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2702952416
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1609458638
Short name T772
Test name
Test status
Simulation time 38004813 ps
CPU time 0.96 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:06 PM PDT 24
Peak memory 215308 kb
Host smart-3343d0c4-c0ab-4ffd-99c6-12fa4e9d78b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609458638 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1609458638
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2113777110
Short name T947
Test name
Test status
Simulation time 371711108 ps
CPU time 2.56 seconds
Started Aug 08 07:43:05 PM PDT 24
Finished Aug 08 07:43:08 PM PDT 24
Peak memory 218720 kb
Host smart-7b8b6e2d-9dde-4593-89a3-3cca707e37d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113777110 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2113777110
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1829588750
Short name T893
Test name
Test status
Simulation time 57254012934 ps
CPU time 743.59 seconds
Started Aug 08 07:43:04 PM PDT 24
Finished Aug 08 07:55:27 PM PDT 24
Peak memory 221228 kb
Host smart-544008bb-8a3a-4646-b58a-8cc0a555c009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829588750 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1829588750
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2021072313
Short name T539
Test name
Test status
Simulation time 26474727 ps
CPU time 1.18 seconds
Started Aug 08 07:43:35 PM PDT 24
Finished Aug 08 07:43:36 PM PDT 24
Peak memory 218728 kb
Host smart-d27a029f-1ed1-4433-b70e-a9d55c39860e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021072313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2021072313
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.1732901398
Short name T571
Test name
Test status
Simulation time 17410974 ps
CPU time 0.99 seconds
Started Aug 08 07:43:34 PM PDT 24
Finished Aug 08 07:43:35 PM PDT 24
Peak memory 215268 kb
Host smart-198d0afa-0065-4f01-91aa-aff0923c59e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732901398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1732901398
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3464990398
Short name T369
Test name
Test status
Simulation time 84132903 ps
CPU time 1.13 seconds
Started Aug 08 07:43:35 PM PDT 24
Finished Aug 08 07:43:36 PM PDT 24
Peak memory 217332 kb
Host smart-13da2c69-f199-4f65-ac22-77b92be1e85b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464990398 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3464990398
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3932713259
Short name T967
Test name
Test status
Simulation time 20191637 ps
CPU time 1.05 seconds
Started Aug 08 07:43:31 PM PDT 24
Finished Aug 08 07:43:32 PM PDT 24
Peak memory 218756 kb
Host smart-5f3f13ff-09a0-4bef-8e99-32bed5931495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932713259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3932713259
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.3113760969
Short name T469
Test name
Test status
Simulation time 21377663 ps
CPU time 1.09 seconds
Started Aug 08 07:43:40 PM PDT 24
Finished Aug 08 07:43:42 PM PDT 24
Peak memory 215428 kb
Host smart-327e28d4-c827-49c3-be4e-527e0b192f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113760969 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3113760969
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1439891617
Short name T473
Test name
Test status
Simulation time 30510093 ps
CPU time 0.97 seconds
Started Aug 08 07:43:38 PM PDT 24
Finished Aug 08 07:43:39 PM PDT 24
Peak memory 215336 kb
Host smart-d77c5402-c058-4805-8077-30deb6ab7288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439891617 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1439891617
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.4051421359
Short name T379
Test name
Test status
Simulation time 165389937 ps
CPU time 3.72 seconds
Started Aug 08 07:43:36 PM PDT 24
Finished Aug 08 07:43:40 PM PDT 24
Peak memory 217224 kb
Host smart-73552389-0532-4cb5-9056-5eda46b72e39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051421359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.4051421359
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1624331258
Short name T653
Test name
Test status
Simulation time 35576415318 ps
CPU time 125.13 seconds
Started Aug 08 07:43:35 PM PDT 24
Finished Aug 08 07:45:40 PM PDT 24
Peak memory 218036 kb
Host smart-5c6c8821-acbd-4a0c-a7e1-a1a6d0fba7be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624331258 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1624331258
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.595451900
Short name T154
Test name
Test status
Simulation time 39317600 ps
CPU time 1.23 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:07 PM PDT 24
Peak memory 218580 kb
Host smart-321a513a-04d9-47c7-9b2e-289bd2367cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595451900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.595451900
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/102.edn_alert.2977931616
Short name T166
Test name
Test status
Simulation time 39334001 ps
CPU time 1.24 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:04 PM PDT 24
Peak memory 219564 kb
Host smart-994e39f7-c436-4ccf-ac31-1cb3ebfd43fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977931616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.2977931616
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.291561021
Short name T716
Test name
Test status
Simulation time 86213883 ps
CPU time 2.8 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:08 PM PDT 24
Peak memory 220140 kb
Host smart-b46f488a-0b56-408b-8c8c-1150110ad2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291561021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.291561021
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.521441357
Short name T995
Test name
Test status
Simulation time 24985706 ps
CPU time 1.29 seconds
Started Aug 08 07:45:04 PM PDT 24
Finished Aug 08 07:45:05 PM PDT 24
Peak memory 219584 kb
Host smart-a55be287-ec87-4a8f-8225-7f5d8de7560f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521441357 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.521441357
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.912603169
Short name T756
Test name
Test status
Simulation time 97201427 ps
CPU time 1.19 seconds
Started Aug 08 07:45:06 PM PDT 24
Finished Aug 08 07:45:07 PM PDT 24
Peak memory 215312 kb
Host smart-e07bee3b-c0e6-4726-8355-1d3613433cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912603169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.912603169
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.2645946756
Short name T260
Test name
Test status
Simulation time 51224767 ps
CPU time 1.22 seconds
Started Aug 08 07:45:07 PM PDT 24
Finished Aug 08 07:45:08 PM PDT 24
Peak memory 220408 kb
Host smart-11deaca9-341a-4177-9df7-5749a64e1a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645946756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2645946756
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.961364107
Short name T554
Test name
Test status
Simulation time 29817392 ps
CPU time 1.27 seconds
Started Aug 08 07:45:04 PM PDT 24
Finished Aug 08 07:45:06 PM PDT 24
Peak memory 218600 kb
Host smart-0e20b588-9073-4593-b887-f0ba0580674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961364107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.961364107
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.3066521157
Short name T703
Test name
Test status
Simulation time 41914551 ps
CPU time 1.13 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:07 PM PDT 24
Peak memory 220628 kb
Host smart-e7c057c1-abea-4f2c-b089-bdd8c4fa1e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066521157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3066521157
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/107.edn_alert.2505416702
Short name T956
Test name
Test status
Simulation time 40190822 ps
CPU time 1.15 seconds
Started Aug 08 07:45:12 PM PDT 24
Finished Aug 08 07:45:13 PM PDT 24
Peak memory 220740 kb
Host smart-40f3a92f-1a5c-4c32-994d-f920bfe2ccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505416702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2505416702
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.291623265
Short name T398
Test name
Test status
Simulation time 83204483 ps
CPU time 1.11 seconds
Started Aug 08 07:45:06 PM PDT 24
Finished Aug 08 07:45:07 PM PDT 24
Peak memory 218668 kb
Host smart-ea74cdb0-8b8d-421b-8932-4b1bc85c6f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291623265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.291623265
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3304907063
Short name T940
Test name
Test status
Simulation time 48181207 ps
CPU time 1.62 seconds
Started Aug 08 07:45:07 PM PDT 24
Finished Aug 08 07:45:09 PM PDT 24
Peak memory 218364 kb
Host smart-e8a8f582-2c35-4835-8d5f-aecc4c4a0ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304907063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3304907063
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3356411693
Short name T119
Test name
Test status
Simulation time 40282431 ps
CPU time 1.2 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:06 PM PDT 24
Peak memory 219548 kb
Host smart-7b277597-bc2d-4b9b-99f0-4166b99d76a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356411693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3356411693
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1405802405
Short name T549
Test name
Test status
Simulation time 50010000 ps
CPU time 1.35 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:05 PM PDT 24
Peak memory 218328 kb
Host smart-9db8d6d8-5f59-485f-86ae-ef524712498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405802405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1405802405
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1216800381
Short name T748
Test name
Test status
Simulation time 74223785 ps
CPU time 1.07 seconds
Started Aug 08 07:43:32 PM PDT 24
Finished Aug 08 07:43:33 PM PDT 24
Peak memory 219508 kb
Host smart-fbfae5cd-1d15-4532-8d0f-98edc26ad08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216800381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1216800381
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.540388949
Short name T444
Test name
Test status
Simulation time 37527725 ps
CPU time 0.81 seconds
Started Aug 08 07:43:39 PM PDT 24
Finished Aug 08 07:43:40 PM PDT 24
Peak memory 206640 kb
Host smart-22cbb444-2758-4099-a123-f35d0559723a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540388949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.540388949
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3609239348
Short name T601
Test name
Test status
Simulation time 17706056 ps
CPU time 0.82 seconds
Started Aug 08 07:43:32 PM PDT 24
Finished Aug 08 07:43:33 PM PDT 24
Peak memory 215376 kb
Host smart-2d37c20b-e685-4669-9970-1a2dc26592a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609239348 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3609239348
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.807391321
Short name T297
Test name
Test status
Simulation time 40143403 ps
CPU time 1.08 seconds
Started Aug 08 07:43:38 PM PDT 24
Finished Aug 08 07:43:39 PM PDT 24
Peak memory 218392 kb
Host smart-2d9796a4-1b6f-46e9-9f48-70500de4b11d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807391321 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.807391321
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1711254737
Short name T213
Test name
Test status
Simulation time 28894548 ps
CPU time 0.93 seconds
Started Aug 08 07:43:37 PM PDT 24
Finished Aug 08 07:43:38 PM PDT 24
Peak memory 218856 kb
Host smart-296cadfa-fa83-4a46-92b6-9bfb7a872ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711254737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1711254737
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2517043974
Short name T246
Test name
Test status
Simulation time 100291108 ps
CPU time 1.14 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 220148 kb
Host smart-ed5fa97e-e7b6-40e0-bbcd-02553f101ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517043974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2517043974
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2993387605
Short name T34
Test name
Test status
Simulation time 22653413 ps
CPU time 0.96 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 216104 kb
Host smart-ff391439-7a43-4703-b69c-f2c78eb62686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993387605 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2993387605
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.995027585
Short name T519
Test name
Test status
Simulation time 15515976 ps
CPU time 1.03 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 215372 kb
Host smart-f77b9611-640f-4694-a90d-82a73ac7ed1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995027585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.995027585
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3355120450
Short name T957
Test name
Test status
Simulation time 89973162703 ps
CPU time 916.63 seconds
Started Aug 08 07:43:40 PM PDT 24
Finished Aug 08 07:58:57 PM PDT 24
Peak memory 221260 kb
Host smart-912ccc7b-402e-4e42-8468-781b18583689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355120450 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3355120450
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.28207013
Short name T873
Test name
Test status
Simulation time 91221719 ps
CPU time 1.21 seconds
Started Aug 08 07:45:07 PM PDT 24
Finished Aug 08 07:45:09 PM PDT 24
Peak memory 219728 kb
Host smart-409f8f05-8b91-4591-8239-fd40d74e4635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28207013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.28207013
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/111.edn_alert.3255856405
Short name T888
Test name
Test status
Simulation time 91419430 ps
CPU time 1.17 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:07 PM PDT 24
Peak memory 220580 kb
Host smart-327dbe16-bd8d-427a-a36f-8ebb960cf128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255856405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3255856405
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1111256310
Short name T751
Test name
Test status
Simulation time 73871719 ps
CPU time 1.85 seconds
Started Aug 08 07:45:10 PM PDT 24
Finished Aug 08 07:45:12 PM PDT 24
Peak memory 218508 kb
Host smart-1ed765e6-14ef-4f5f-94a0-ad8c57294f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111256310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1111256310
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.3301552834
Short name T415
Test name
Test status
Simulation time 196893638 ps
CPU time 1.17 seconds
Started Aug 08 07:45:06 PM PDT 24
Finished Aug 08 07:45:08 PM PDT 24
Peak memory 217404 kb
Host smart-fadf6c39-4628-42f2-9c84-5c43e66941ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301552834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3301552834
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.3786002423
Short name T77
Test name
Test status
Simulation time 61687614 ps
CPU time 1.36 seconds
Started Aug 08 07:45:06 PM PDT 24
Finished Aug 08 07:45:07 PM PDT 24
Peak memory 215564 kb
Host smart-17a18cfb-98b0-4b7e-9d77-18c233ef20c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786002423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3786002423
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3119733675
Short name T103
Test name
Test status
Simulation time 45072951 ps
CPU time 1.13 seconds
Started Aug 08 07:45:07 PM PDT 24
Finished Aug 08 07:45:08 PM PDT 24
Peak memory 218756 kb
Host smart-8b9a5008-62ed-46ee-bcd0-9038201ba585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119733675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3119733675
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.2748339927
Short name T720
Test name
Test status
Simulation time 88837378 ps
CPU time 1.23 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:07 PM PDT 24
Peak memory 218548 kb
Host smart-2fc0a040-5f44-4f2f-b8fb-fbdf5f64fae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748339927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.2748339927
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/115.edn_alert.3463564341
Short name T453
Test name
Test status
Simulation time 291330390 ps
CPU time 1.32 seconds
Started Aug 08 07:45:12 PM PDT 24
Finished Aug 08 07:45:13 PM PDT 24
Peak memory 219376 kb
Host smart-75272833-52bb-4104-9030-f43f50d871aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463564341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3463564341
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1115095890
Short name T987
Test name
Test status
Simulation time 80828629 ps
CPU time 1.2 seconds
Started Aug 08 07:45:02 PM PDT 24
Finished Aug 08 07:45:03 PM PDT 24
Peak memory 217380 kb
Host smart-3b4ef92e-de20-4f8c-9634-23c140e0f3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115095890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1115095890
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.403578476
Short name T717
Test name
Test status
Simulation time 25722138 ps
CPU time 1.13 seconds
Started Aug 08 07:45:18 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 218500 kb
Host smart-bed0d3fa-e27f-4027-9036-9d8a1c51fd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403578476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.403578476
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.259687371
Short name T652
Test name
Test status
Simulation time 78843127 ps
CPU time 1.17 seconds
Started Aug 08 07:45:16 PM PDT 24
Finished Aug 08 07:45:18 PM PDT 24
Peak memory 215316 kb
Host smart-ac63c047-0957-4407-8763-5d18056cb068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259687371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.259687371
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.3493469723
Short name T112
Test name
Test status
Simulation time 71484485 ps
CPU time 1.06 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 218772 kb
Host smart-a220eff6-5ef8-4d05-888e-a8ade647104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493469723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.3493469723
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3886872840
Short name T427
Test name
Test status
Simulation time 33887933 ps
CPU time 1.11 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 219652 kb
Host smart-c8724f5a-83de-49d1-96ec-8f427fad6ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886872840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3886872840
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.84294091
Short name T642
Test name
Test status
Simulation time 46616356 ps
CPU time 1.21 seconds
Started Aug 08 07:45:24 PM PDT 24
Finished Aug 08 07:45:25 PM PDT 24
Peak memory 215600 kb
Host smart-76ad844c-c850-44c1-a1d4-866d1a174cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84294091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.84294091
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.2631561791
Short name T558
Test name
Test status
Simulation time 40410016 ps
CPU time 1.44 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 215332 kb
Host smart-acecf167-d4d7-4d17-a35e-d29214ae6db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631561791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2631561791
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1764759142
Short name T641
Test name
Test status
Simulation time 25384233 ps
CPU time 1.18 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 219780 kb
Host smart-824ab61c-8a34-4efc-9e7b-8a759f052cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764759142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1764759142
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.1263839397
Short name T651
Test name
Test status
Simulation time 88912799 ps
CPU time 1.14 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 217388 kb
Host smart-a9c183f5-f691-4a00-a123-e07b5bbbd4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263839397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1263839397
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.4218877381
Short name T300
Test name
Test status
Simulation time 25460108 ps
CPU time 1.19 seconds
Started Aug 08 07:43:40 PM PDT 24
Finished Aug 08 07:43:41 PM PDT 24
Peak memory 218568 kb
Host smart-84cddd27-d0dc-4e47-b242-f9b299181364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218877381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4218877381
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3619190922
Short name T745
Test name
Test status
Simulation time 23285396 ps
CPU time 1.04 seconds
Started Aug 08 07:43:35 PM PDT 24
Finished Aug 08 07:43:36 PM PDT 24
Peak memory 215244 kb
Host smart-1e82d9db-320c-4263-86d8-b1f17e2a5f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619190922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3619190922
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.169165154
Short name T901
Test name
Test status
Simulation time 39257097 ps
CPU time 0.9 seconds
Started Aug 08 07:43:39 PM PDT 24
Finished Aug 08 07:43:40 PM PDT 24
Peak memory 215292 kb
Host smart-f31899f1-fd34-4a9d-a65b-397134a8ae8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169165154 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.169165154
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3368126072
Short name T478
Test name
Test status
Simulation time 46778485 ps
CPU time 1.06 seconds
Started Aug 08 07:43:31 PM PDT 24
Finished Aug 08 07:43:32 PM PDT 24
Peak memory 219492 kb
Host smart-e652d1e1-5797-436b-aa85-68caa878cb04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368126072 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3368126072
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.330508827
Short name T143
Test name
Test status
Simulation time 30659078 ps
CPU time 1.01 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 219876 kb
Host smart-d2be4092-29e0-45e5-b36c-be40ef17fb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330508827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.330508827
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1250833556
Short name T452
Test name
Test status
Simulation time 54322061 ps
CPU time 1.21 seconds
Started Aug 08 07:43:35 PM PDT 24
Finished Aug 08 07:43:37 PM PDT 24
Peak memory 219984 kb
Host smart-2c035ab7-a293-46c0-b119-89fdbf400aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250833556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1250833556
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.837711953
Short name T557
Test name
Test status
Simulation time 22932177 ps
CPU time 1.09 seconds
Started Aug 08 07:43:39 PM PDT 24
Finished Aug 08 07:43:40 PM PDT 24
Peak memory 214856 kb
Host smart-de6c8885-9fd5-4f00-8f85-0dc67ce19c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837711953 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.837711953
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2888573583
Short name T795
Test name
Test status
Simulation time 53875263 ps
CPU time 0.87 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 215304 kb
Host smart-f14d0546-4883-4974-bf20-5b5d9cc767fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888573583 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2888573583
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2028007798
Short name T242
Test name
Test status
Simulation time 93996656357 ps
CPU time 1033.57 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 08:00:47 PM PDT 24
Peak memory 223584 kb
Host smart-a5c9a294-651c-4e78-accf-bdd3e4cf2818
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028007798 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2028007798
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.2450695275
Short name T687
Test name
Test status
Simulation time 25280004 ps
CPU time 1.16 seconds
Started Aug 08 07:45:27 PM PDT 24
Finished Aug 08 07:45:28 PM PDT 24
Peak memory 220068 kb
Host smart-616a5bd2-860a-49c6-9946-f4f95bd3c1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450695275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2450695275
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.4218404503
Short name T253
Test name
Test status
Simulation time 29869095 ps
CPU time 1.28 seconds
Started Aug 08 07:45:16 PM PDT 24
Finished Aug 08 07:45:17 PM PDT 24
Peak memory 218656 kb
Host smart-9b74b754-3aee-42e0-9a56-458c92487269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218404503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.4218404503
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1089232314
Short name T992
Test name
Test status
Simulation time 135847806 ps
CPU time 1.26 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 218548 kb
Host smart-738c1c2c-dc2c-401f-aba2-5bc6c1ff7847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089232314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1089232314
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1989571860
Short name T381
Test name
Test status
Simulation time 76513968 ps
CPU time 1.19 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:18 PM PDT 24
Peak memory 217496 kb
Host smart-9152c837-0e00-4b4f-becc-952ddb096a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989571860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1989571860
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.2801324756
Short name T734
Test name
Test status
Simulation time 74433747 ps
CPU time 1.2 seconds
Started Aug 08 07:45:21 PM PDT 24
Finished Aug 08 07:45:23 PM PDT 24
Peak memory 219288 kb
Host smart-1be7d543-3719-4f71-8f6c-3fdf08032fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801324756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2801324756
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.337367858
Short name T42
Test name
Test status
Simulation time 41762987 ps
CPU time 1.64 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:18 PM PDT 24
Peak memory 218888 kb
Host smart-ec97101a-7c19-4361-9ba8-efea395a4893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337367858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.337367858
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2272612251
Short name T951
Test name
Test status
Simulation time 63135462 ps
CPU time 1.1 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 219284 kb
Host smart-59538433-223e-4e13-8b46-3b15756df243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272612251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2272612251
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2235932758
Short name T515
Test name
Test status
Simulation time 69919412 ps
CPU time 1.17 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 217288 kb
Host smart-14dc775f-7e51-4a18-817f-6c4579b76cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235932758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2235932758
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.972439043
Short name T500
Test name
Test status
Simulation time 36974828 ps
CPU time 1.13 seconds
Started Aug 08 07:45:20 PM PDT 24
Finished Aug 08 07:45:21 PM PDT 24
Peak memory 218620 kb
Host smart-87b400df-06f1-41d0-9032-a4ba7898c160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972439043 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.972439043
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.719482960
Short name T423
Test name
Test status
Simulation time 56319825 ps
CPU time 1.69 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 218624 kb
Host smart-95726f4f-d5e0-48c5-8618-b6fd3e9f1735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719482960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.719482960
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2899938009
Short name T442
Test name
Test status
Simulation time 25062947 ps
CPU time 1.2 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:18 PM PDT 24
Peak memory 219444 kb
Host smart-df1bc0df-8b0e-486c-aed3-a9564cf7eb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899938009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2899938009
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.2348651958
Short name T387
Test name
Test status
Simulation time 114492031 ps
CPU time 1.03 seconds
Started Aug 08 07:45:20 PM PDT 24
Finished Aug 08 07:45:21 PM PDT 24
Peak memory 217552 kb
Host smart-cebfb6bc-6b85-4430-b3f1-bf21168e29a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348651958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2348651958
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.1117814284
Short name T16
Test name
Test status
Simulation time 170054010 ps
CPU time 1.21 seconds
Started Aug 08 07:45:18 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 215596 kb
Host smart-0d07ad16-ceae-42bf-9f3e-6814b021a1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117814284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1117814284
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.2094534436
Short name T566
Test name
Test status
Simulation time 37548706 ps
CPU time 1.3 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 217284 kb
Host smart-231f4479-3fea-4f23-9d86-11bd542a920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094534436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2094534436
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.4054656124
Short name T603
Test name
Test status
Simulation time 53965126 ps
CPU time 1.26 seconds
Started Aug 08 07:45:20 PM PDT 24
Finished Aug 08 07:45:21 PM PDT 24
Peak memory 220716 kb
Host smart-10e2558d-e2b5-403e-923a-dd42e6497011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054656124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.4054656124
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.899123887
Short name T406
Test name
Test status
Simulation time 46015146 ps
CPU time 1.48 seconds
Started Aug 08 07:45:18 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 218752 kb
Host smart-81028a2f-0e01-4ab7-9cda-ca5c92b85e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899123887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.899123887
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.4060421922
Short name T228
Test name
Test status
Simulation time 74216550 ps
CPU time 1.15 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 220944 kb
Host smart-0187f986-4e27-440b-9c18-1082c3797dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060421922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.4060421922
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.667382164
Short name T556
Test name
Test status
Simulation time 52033285 ps
CPU time 1.32 seconds
Started Aug 08 07:45:27 PM PDT 24
Finished Aug 08 07:45:28 PM PDT 24
Peak memory 219940 kb
Host smart-33818b36-f448-4f7e-83a1-10ae88f6a31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667382164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.667382164
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.1726220333
Short name T718
Test name
Test status
Simulation time 24178076 ps
CPU time 1.22 seconds
Started Aug 08 07:45:21 PM PDT 24
Finished Aug 08 07:45:22 PM PDT 24
Peak memory 218712 kb
Host smart-21f14865-70d5-4193-9961-4f96a2fdab5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726220333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1726220333
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.2309555451
Short name T90
Test name
Test status
Simulation time 59360144 ps
CPU time 1.58 seconds
Started Aug 08 07:45:18 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 218756 kb
Host smart-2a55b332-0f5e-44c9-985e-e86630e0752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309555451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2309555451
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2292653497
Short name T912
Test name
Test status
Simulation time 46258276 ps
CPU time 1.26 seconds
Started Aug 08 07:43:36 PM PDT 24
Finished Aug 08 07:43:38 PM PDT 24
Peak memory 218496 kb
Host smart-001a689d-bbcd-45f4-b1d6-69f8882e10fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292653497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2292653497
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.990467985
Short name T129
Test name
Test status
Simulation time 124857408 ps
CPU time 1.2 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 217048 kb
Host smart-04ed7fd2-db7d-48d0-8f49-9eb3ad7c1c7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990467985 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.990467985
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.929398427
Short name T220
Test name
Test status
Simulation time 23928362 ps
CPU time 1.3 seconds
Started Aug 08 07:43:41 PM PDT 24
Finished Aug 08 07:43:43 PM PDT 24
Peak memory 221092 kb
Host smart-f29ec5c0-24bc-49d3-a596-6eb430b8f59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929398427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.929398427
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_intr.3357818139
Short name T648
Test name
Test status
Simulation time 22026810 ps
CPU time 1.1 seconds
Started Aug 08 07:43:41 PM PDT 24
Finished Aug 08 07:43:43 PM PDT 24
Peak memory 215380 kb
Host smart-7e849676-b2df-49cf-a416-0f850cf3e185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357818139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3357818139
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.541984357
Short name T495
Test name
Test status
Simulation time 19305383 ps
CPU time 1.05 seconds
Started Aug 08 07:43:38 PM PDT 24
Finished Aug 08 07:43:39 PM PDT 24
Peak memory 215312 kb
Host smart-e790f81a-95ca-4918-9404-316dca4f6ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541984357 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.541984357
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.951743683
Short name T107
Test name
Test status
Simulation time 715361483 ps
CPU time 2.35 seconds
Started Aug 08 07:43:40 PM PDT 24
Finished Aug 08 07:43:42 PM PDT 24
Peak memory 217200 kb
Host smart-2216ded5-8dac-4afd-babc-a4a0c15ac98f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951743683 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.951743683
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2898387222
Short name T824
Test name
Test status
Simulation time 67789022249 ps
CPU time 469.5 seconds
Started Aug 08 07:43:39 PM PDT 24
Finished Aug 08 07:51:29 PM PDT 24
Peak memory 222928 kb
Host smart-e11b5cf9-16a9-49d7-be24-05626cd29e26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898387222 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2898387222
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2449776258
Short name T875
Test name
Test status
Simulation time 196282878 ps
CPU time 1.34 seconds
Started Aug 08 07:45:28 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 218548 kb
Host smart-fb6fa69b-dd94-4f45-993f-a1a27e989f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449776258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2449776258
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.3540184866
Short name T372
Test name
Test status
Simulation time 32566309 ps
CPU time 1.31 seconds
Started Aug 08 07:45:20 PM PDT 24
Finished Aug 08 07:45:21 PM PDT 24
Peak memory 218632 kb
Host smart-33d138da-1fab-4725-aea1-f8cf01be85c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540184866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3540184866
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1752943407
Short name T317
Test name
Test status
Simulation time 87032482 ps
CPU time 1.2 seconds
Started Aug 08 07:45:16 PM PDT 24
Finished Aug 08 07:45:17 PM PDT 24
Peak memory 218560 kb
Host smart-4411330c-8d14-40f5-9118-6662e18bd98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752943407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1752943407
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.3383506636
Short name T553
Test name
Test status
Simulation time 71932379 ps
CPU time 1.14 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:18 PM PDT 24
Peak memory 219756 kb
Host smart-f4ca9acf-bc8d-4a9a-82b5-6c33dc83a4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383506636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3383506636
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1047653936
Short name T638
Test name
Test status
Simulation time 29664127 ps
CPU time 1.14 seconds
Started Aug 08 07:45:16 PM PDT 24
Finished Aug 08 07:45:17 PM PDT 24
Peak memory 218700 kb
Host smart-e3de63e6-103b-4a23-8c45-2c873da3e0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047653936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1047653936
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2493219443
Short name T544
Test name
Test status
Simulation time 31718928 ps
CPU time 1.1 seconds
Started Aug 08 07:45:20 PM PDT 24
Finished Aug 08 07:45:21 PM PDT 24
Peak memory 217404 kb
Host smart-962e8646-4b80-4708-b7a7-119f62220d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493219443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2493219443
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3970144859
Short name T819
Test name
Test status
Simulation time 33281541 ps
CPU time 1.33 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 219924 kb
Host smart-b30dd41d-29e2-45b9-a66f-4ac322d91d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970144859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3970144859
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.283783763
Short name T20
Test name
Test status
Simulation time 99178436 ps
CPU time 1.17 seconds
Started Aug 08 07:45:16 PM PDT 24
Finished Aug 08 07:45:18 PM PDT 24
Peak memory 219984 kb
Host smart-7fbefea1-2006-4a0b-b5ab-9b20a25bef0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283783763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.283783763
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.3179289250
Short name T130
Test name
Test status
Simulation time 27507788 ps
CPU time 1.25 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 219384 kb
Host smart-5d1a7983-379a-4ad2-a2b0-ae770b5fc8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179289250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3179289250
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1076162415
Short name T466
Test name
Test status
Simulation time 63601312 ps
CPU time 1.26 seconds
Started Aug 08 07:45:16 PM PDT 24
Finished Aug 08 07:45:17 PM PDT 24
Peak memory 217528 kb
Host smart-3cc3e511-cb3c-4ee3-979b-8a8d02cd9093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076162415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1076162415
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1531568111
Short name T712
Test name
Test status
Simulation time 144564468 ps
CPU time 1.22 seconds
Started Aug 08 07:45:20 PM PDT 24
Finished Aug 08 07:45:21 PM PDT 24
Peak memory 218644 kb
Host smart-f5655537-230b-4b04-838a-9f5adc058d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531568111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1531568111
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.1629187843
Short name T823
Test name
Test status
Simulation time 31254652 ps
CPU time 1.31 seconds
Started Aug 08 07:45:18 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 217312 kb
Host smart-5f9c1b3e-1e07-477f-b2cf-58e2bfb7c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629187843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1629187843
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.2867399785
Short name T631
Test name
Test status
Simulation time 62339838 ps
CPU time 1.11 seconds
Started Aug 08 07:45:16 PM PDT 24
Finished Aug 08 07:45:18 PM PDT 24
Peak memory 217412 kb
Host smart-6526f58d-947b-4d40-a129-3c81faff3fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867399785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2867399785
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.2109242036
Short name T832
Test name
Test status
Simulation time 22591694 ps
CPU time 1.17 seconds
Started Aug 08 07:45:18 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 220640 kb
Host smart-acbcd14b-1d34-44c2-978d-324fa7350c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109242036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2109242036
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3951493152
Short name T707
Test name
Test status
Simulation time 52436153 ps
CPU time 1.03 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:21 PM PDT 24
Peak memory 217296 kb
Host smart-55acf285-dbe3-4e13-affe-3da3615898a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951493152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3951493152
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3778232
Short name T546
Test name
Test status
Simulation time 76255835 ps
CPU time 1.27 seconds
Started Aug 08 07:45:18 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 217372 kb
Host smart-725f2539-eb54-4100-bd86-c89b778b1021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3778232
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.361419109
Short name T702
Test name
Test status
Simulation time 84387076 ps
CPU time 1.17 seconds
Started Aug 08 07:43:41 PM PDT 24
Finished Aug 08 07:43:43 PM PDT 24
Peak memory 219248 kb
Host smart-3615f113-7a73-4a5f-baa5-55f605dfef74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361419109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.361419109
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3975990517
Short name T581
Test name
Test status
Simulation time 20035655 ps
CPU time 0.82 seconds
Started Aug 08 07:43:32 PM PDT 24
Finished Aug 08 07:43:33 PM PDT 24
Peak memory 215008 kb
Host smart-b98f31f3-5180-4455-9af2-65e98d9e42cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975990517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3975990517
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1722437930
Short name T573
Test name
Test status
Simulation time 11102212 ps
CPU time 0.87 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 215380 kb
Host smart-3cca948a-4d8d-4515-ac96-8b702c0d018c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722437930 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1722437930
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.462922868
Short name T147
Test name
Test status
Simulation time 31351988 ps
CPU time 0.94 seconds
Started Aug 08 07:43:39 PM PDT 24
Finished Aug 08 07:43:40 PM PDT 24
Peak memory 219736 kb
Host smart-7ada9380-bfa8-4889-9b78-331af3aff92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462922868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.462922868
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1681967240
Short name T338
Test name
Test status
Simulation time 35228178 ps
CPU time 1.27 seconds
Started Aug 08 07:43:37 PM PDT 24
Finished Aug 08 07:43:38 PM PDT 24
Peak memory 219720 kb
Host smart-c2cd8d4f-38a4-43d8-a436-31361b0ba1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681967240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1681967240
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3314848638
Short name T451
Test name
Test status
Simulation time 20778532 ps
CPU time 1.09 seconds
Started Aug 08 07:43:37 PM PDT 24
Finished Aug 08 07:43:38 PM PDT 24
Peak memory 215272 kb
Host smart-0dbf0577-c39f-4dee-b55d-e900ad477655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314848638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3314848638
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1757768210
Short name T637
Test name
Test status
Simulation time 53145377 ps
CPU time 0.97 seconds
Started Aug 08 07:43:39 PM PDT 24
Finished Aug 08 07:43:40 PM PDT 24
Peak memory 215344 kb
Host smart-9355cb54-03ea-40d3-92b2-feb5651589bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757768210 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1757768210
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2722144341
Short name T339
Test name
Test status
Simulation time 182844084 ps
CPU time 3.98 seconds
Started Aug 08 07:43:40 PM PDT 24
Finished Aug 08 07:43:44 PM PDT 24
Peak memory 215324 kb
Host smart-689653fe-1607-4a3f-8b65-48b7de65b12c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722144341 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2722144341
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2348698528
Short name T334
Test name
Test status
Simulation time 438404116629 ps
CPU time 2590.96 seconds
Started Aug 08 07:43:37 PM PDT 24
Finished Aug 08 08:26:48 PM PDT 24
Peak memory 228460 kb
Host smart-2e09a7f7-6ee6-4954-9f11-829fb210ae4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348698528 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2348698528
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.2412328340
Short name T324
Test name
Test status
Simulation time 60800904 ps
CPU time 1.1 seconds
Started Aug 08 07:45:24 PM PDT 24
Finished Aug 08 07:45:25 PM PDT 24
Peak memory 220600 kb
Host smart-26351dc0-6a63-4b7e-8de3-068adc3d4dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412328340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.2412328340
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2695807639
Short name T590
Test name
Test status
Simulation time 55844105 ps
CPU time 1.46 seconds
Started Aug 08 07:45:20 PM PDT 24
Finished Aug 08 07:45:22 PM PDT 24
Peak memory 217576 kb
Host smart-6476de92-72c6-4fed-a949-c38a4300f8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695807639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2695807639
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.1015749491
Short name T176
Test name
Test status
Simulation time 45079373 ps
CPU time 1.2 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 218492 kb
Host smart-588a26b7-53f9-4d77-8611-1f5465cbaf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015749491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1015749491
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/142.edn_alert.3243641150
Short name T681
Test name
Test status
Simulation time 29474077 ps
CPU time 1.14 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:21 PM PDT 24
Peak memory 218404 kb
Host smart-679c391a-691c-4fe7-b8c5-b1eae8e3034f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243641150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3243641150
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2562839537
Short name T570
Test name
Test status
Simulation time 33588436 ps
CPU time 1.43 seconds
Started Aug 08 07:45:20 PM PDT 24
Finished Aug 08 07:45:22 PM PDT 24
Peak memory 217392 kb
Host smart-1c4b74f7-ea3f-4e32-808d-6c2a975e8746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562839537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2562839537
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1549564156
Short name T744
Test name
Test status
Simulation time 36336988 ps
CPU time 1.04 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 218548 kb
Host smart-6d134e88-3dd8-4a24-9aee-eb8c216ae2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549564156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1549564156
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.2165075892
Short name T44
Test name
Test status
Simulation time 45218738 ps
CPU time 1.69 seconds
Started Aug 08 07:45:20 PM PDT 24
Finished Aug 08 07:45:22 PM PDT 24
Peak memory 218724 kb
Host smart-bfdd0c30-4234-48a5-ba5f-3aec87117def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165075892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2165075892
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.4261412094
Short name T865
Test name
Test status
Simulation time 59079382 ps
CPU time 1.24 seconds
Started Aug 08 07:45:24 PM PDT 24
Finished Aug 08 07:45:25 PM PDT 24
Peak memory 220048 kb
Host smart-bb60f203-da04-46ee-a63d-c61a7d3b4d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261412094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.4261412094
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.1689671033
Short name T407
Test name
Test status
Simulation time 123093602 ps
CPU time 1.13 seconds
Started Aug 08 07:45:27 PM PDT 24
Finished Aug 08 07:45:28 PM PDT 24
Peak memory 217440 kb
Host smart-a64a817b-5c5d-40df-813b-f6a6dba96b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689671033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1689671033
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.1882348844
Short name T926
Test name
Test status
Simulation time 132997591 ps
CPU time 1.18 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:20 PM PDT 24
Peak memory 218436 kb
Host smart-f1e6005b-8601-4e91-ac52-00154bceccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882348844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1882348844
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.1015731673
Short name T874
Test name
Test status
Simulation time 38601356 ps
CPU time 1.49 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:21 PM PDT 24
Peak memory 218932 kb
Host smart-614d38ff-c389-4583-be96-d86db310f3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015731673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1015731673
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2897702549
Short name T661
Test name
Test status
Simulation time 75889384 ps
CPU time 1.12 seconds
Started Aug 08 07:45:18 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 218520 kb
Host smart-507c5f12-dcdd-466d-b6bc-c52f3b3765f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897702549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2897702549
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2596661705
Short name T848
Test name
Test status
Simulation time 89336094 ps
CPU time 1.17 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:21 PM PDT 24
Peak memory 217472 kb
Host smart-e230bb67-d174-4dbe-b5ab-f930b19b9eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596661705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2596661705
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.1640002157
Short name T817
Test name
Test status
Simulation time 71938388 ps
CPU time 1.25 seconds
Started Aug 08 07:45:17 PM PDT 24
Finished Aug 08 07:45:18 PM PDT 24
Peak memory 219804 kb
Host smart-a101807d-c177-47d0-a4d7-e1289c850e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640002157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1640002157
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1510572372
Short name T982
Test name
Test status
Simulation time 186973025 ps
CPU time 1.07 seconds
Started Aug 08 07:45:18 PM PDT 24
Finished Aug 08 07:45:19 PM PDT 24
Peak memory 217500 kb
Host smart-fa09f528-4a7a-4f2f-bf37-66febe6dd009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510572372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1510572372
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.3803166691
Short name T536
Test name
Test status
Simulation time 29338639 ps
CPU time 1.31 seconds
Started Aug 08 07:45:19 PM PDT 24
Finished Aug 08 07:45:21 PM PDT 24
Peak memory 215564 kb
Host smart-0b0e383d-3fe9-480a-b71a-cffabcb14d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803166691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3803166691
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2494065916
Short name T727
Test name
Test status
Simulation time 47539102 ps
CPU time 1.11 seconds
Started Aug 08 07:45:24 PM PDT 24
Finished Aug 08 07:45:25 PM PDT 24
Peak memory 219748 kb
Host smart-85a8a221-74fc-4e07-9d36-061fca98b76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494065916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2494065916
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3417344457
Short name T640
Test name
Test status
Simulation time 62258679 ps
CPU time 2.46 seconds
Started Aug 08 07:45:21 PM PDT 24
Finished Aug 08 07:45:23 PM PDT 24
Peak memory 218988 kb
Host smart-239921fc-57d2-427a-80c6-89fc5438f663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417344457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3417344457
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.165290829
Short name T262
Test name
Test status
Simulation time 51036675 ps
CPU time 1.23 seconds
Started Aug 08 07:43:34 PM PDT 24
Finished Aug 08 07:43:36 PM PDT 24
Peak memory 219612 kb
Host smart-317a5743-190b-4428-82a3-9c0720e29395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165290829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.165290829
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2066643734
Short name T884
Test name
Test status
Simulation time 19573567 ps
CPU time 0.99 seconds
Started Aug 08 07:43:36 PM PDT 24
Finished Aug 08 07:43:37 PM PDT 24
Peak memory 215160 kb
Host smart-adb41011-ece8-4ea7-9c25-41ed0d0705be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066643734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2066643734
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.279886675
Short name T910
Test name
Test status
Simulation time 17731323 ps
CPU time 0.82 seconds
Started Aug 08 07:43:37 PM PDT 24
Finished Aug 08 07:43:38 PM PDT 24
Peak memory 216240 kb
Host smart-630250c0-f524-453a-b9a5-4c53c6443bde
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279886675 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.279886675
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3635996073
Short name T367
Test name
Test status
Simulation time 32619468 ps
CPU time 1.12 seconds
Started Aug 08 07:43:36 PM PDT 24
Finished Aug 08 07:43:37 PM PDT 24
Peak memory 218472 kb
Host smart-62097802-8d0c-406a-ba65-f54be070ed4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635996073 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3635996073
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2792219812
Short name T124
Test name
Test status
Simulation time 50277885 ps
CPU time 1.15 seconds
Started Aug 08 07:43:35 PM PDT 24
Finished Aug 08 07:43:37 PM PDT 24
Peak memory 217812 kb
Host smart-9fca4fba-6948-42a3-81de-8a211192a567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792219812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2792219812
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1539489817
Short name T688
Test name
Test status
Simulation time 106409953 ps
CPU time 1.33 seconds
Started Aug 08 07:43:38 PM PDT 24
Finished Aug 08 07:43:40 PM PDT 24
Peak memory 217300 kb
Host smart-52f0fc7b-a852-4035-8e90-0f05a0598841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539489817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1539489817
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3937853473
Short name T919
Test name
Test status
Simulation time 23619383 ps
CPU time 0.92 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 216024 kb
Host smart-3732dbf8-9964-426b-8614-803eab33e490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937853473 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3937853473
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2385213521
Short name T505
Test name
Test status
Simulation time 16392406 ps
CPU time 0.97 seconds
Started Aug 08 07:43:42 PM PDT 24
Finished Aug 08 07:43:43 PM PDT 24
Peak memory 215128 kb
Host smart-9aec6f9a-e2f9-4548-8976-8d3c1f3e5701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385213521 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2385213521
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1353514736
Short name T639
Test name
Test status
Simulation time 503235567 ps
CPU time 3.74 seconds
Started Aug 08 07:43:39 PM PDT 24
Finished Aug 08 07:43:43 PM PDT 24
Peak memory 215332 kb
Host smart-c8ed8814-9197-41fb-a077-7599d734b68c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353514736 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1353514736
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_alert.153204806
Short name T778
Test name
Test status
Simulation time 29233211 ps
CPU time 1.26 seconds
Started Aug 08 07:45:30 PM PDT 24
Finished Aug 08 07:45:32 PM PDT 24
Peak memory 218608 kb
Host smart-6d962ae1-c664-4f72-b488-bb5a62523b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153204806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.153204806
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2600864648
Short name T248
Test name
Test status
Simulation time 75782615 ps
CPU time 2.65 seconds
Started Aug 08 07:45:30 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 215484 kb
Host smart-6431b48f-c7bc-4c1e-9d56-b2bc59272cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600864648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2600864648
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.66284599
Short name T677
Test name
Test status
Simulation time 77321354 ps
CPU time 1.13 seconds
Started Aug 08 07:45:28 PM PDT 24
Finished Aug 08 07:45:29 PM PDT 24
Peak memory 218684 kb
Host smart-640ccbfe-aa44-4c81-8ef4-2c9ef82decc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66284599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.66284599
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.312810466
Short name T461
Test name
Test status
Simulation time 164233522 ps
CPU time 1.21 seconds
Started Aug 08 07:45:30 PM PDT 24
Finished Aug 08 07:45:32 PM PDT 24
Peak memory 217508 kb
Host smart-6993c552-d8b9-46bb-ac6b-b4e76c927562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312810466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.312810466
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3967064403
Short name T701
Test name
Test status
Simulation time 45221778 ps
CPU time 1.11 seconds
Started Aug 08 07:45:25 PM PDT 24
Finished Aug 08 07:45:26 PM PDT 24
Peak memory 219564 kb
Host smart-83c44c47-6ed1-44d7-98e9-69f64158687c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967064403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3967064403
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3019027172
Short name T814
Test name
Test status
Simulation time 72034807 ps
CPU time 1.54 seconds
Started Aug 08 07:45:30 PM PDT 24
Finished Aug 08 07:45:32 PM PDT 24
Peak memory 218488 kb
Host smart-45d78dc2-dd10-4af2-957a-ecc4e6ebbac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019027172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3019027172
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1493577166
Short name T497
Test name
Test status
Simulation time 23250804 ps
CPU time 1.19 seconds
Started Aug 08 07:45:30 PM PDT 24
Finished Aug 08 07:45:31 PM PDT 24
Peak memory 219688 kb
Host smart-fb04dcc4-ec3c-4e11-9401-b84acf35ba38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493577166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1493577166
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1729471800
Short name T25
Test name
Test status
Simulation time 59401261 ps
CPU time 1.25 seconds
Started Aug 08 07:45:24 PM PDT 24
Finished Aug 08 07:45:25 PM PDT 24
Peak memory 217364 kb
Host smart-1e7f3795-0eaa-4275-8211-0e430125fe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729471800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1729471800
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1798694076
Short name T498
Test name
Test status
Simulation time 74398566 ps
CPU time 1.23 seconds
Started Aug 08 07:45:27 PM PDT 24
Finished Aug 08 07:45:29 PM PDT 24
Peak memory 220340 kb
Host smart-0a1c1889-c60f-4275-a571-fbe6da934884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798694076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1798694076
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1578590299
Short name T384
Test name
Test status
Simulation time 70312340 ps
CPU time 1.33 seconds
Started Aug 08 07:45:30 PM PDT 24
Finished Aug 08 07:45:31 PM PDT 24
Peak memory 218720 kb
Host smart-d3c43d63-01a7-4041-a33f-e1df84a51659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578590299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1578590299
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3639441359
Short name T522
Test name
Test status
Simulation time 23026409 ps
CPU time 1.17 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:32 PM PDT 24
Peak memory 218508 kb
Host smart-726c9add-c38a-4d1f-aeab-8a693c49dd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639441359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3639441359
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2593687164
Short name T332
Test name
Test status
Simulation time 31890893 ps
CPU time 1.49 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 218448 kb
Host smart-7781f64d-7185-4732-bcf2-bf17b33247da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593687164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2593687164
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.281759108
Short name T132
Test name
Test status
Simulation time 26422474 ps
CPU time 1.26 seconds
Started Aug 08 07:45:28 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 218648 kb
Host smart-dd0c5ce2-565d-4a0f-bac4-70dca381d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281759108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.281759108
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.1809011493
Short name T608
Test name
Test status
Simulation time 31581645 ps
CPU time 1.37 seconds
Started Aug 08 07:45:28 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 218756 kb
Host smart-3fd02fa2-88d2-4194-b941-ceeb559b78c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809011493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1809011493
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.2940065886
Short name T49
Test name
Test status
Simulation time 148765855 ps
CPU time 1.13 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 219704 kb
Host smart-4126416c-da8f-40dc-9488-7d9c311962bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940065886 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2940065886
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.1569009446
Short name T344
Test name
Test status
Simulation time 186345695 ps
CPU time 1.2 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:32 PM PDT 24
Peak memory 217684 kb
Host smart-6fed64df-edcb-40bc-b9d1-45933e2941f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569009446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1569009446
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.978793973
Short name T891
Test name
Test status
Simulation time 40433482 ps
CPU time 1.15 seconds
Started Aug 08 07:45:32 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 220404 kb
Host smart-92a8efbd-e4a3-4a9c-b6cb-c47a66c002a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978793973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.978793973
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1991478526
Short name T459
Test name
Test status
Simulation time 137566989 ps
CPU time 1.73 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 218624 kb
Host smart-d4c048a5-264f-4eeb-a70d-5c24149975fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991478526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1991478526
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.3629459287
Short name T784
Test name
Test status
Simulation time 73441078 ps
CPU time 1.13 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 218300 kb
Host smart-1a5e6d38-547b-4cb7-8414-a67a8f9811dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629459287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3629459287
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.2983093406
Short name T978
Test name
Test status
Simulation time 208972927 ps
CPU time 3.2 seconds
Started Aug 08 07:45:27 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 218832 kb
Host smart-1309a1ea-4178-4383-805d-a3be7c12239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983093406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2983093406
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.891848556
Short name T83
Test name
Test status
Simulation time 29979250 ps
CPU time 1.24 seconds
Started Aug 08 07:43:38 PM PDT 24
Finished Aug 08 07:43:40 PM PDT 24
Peak memory 218464 kb
Host smart-0061b687-2cbd-4dbb-a210-8253b90e934a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891848556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.891848556
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2696388494
Short name T359
Test name
Test status
Simulation time 61204110 ps
CPU time 0.78 seconds
Started Aug 08 07:43:41 PM PDT 24
Finished Aug 08 07:43:42 PM PDT 24
Peak memory 206496 kb
Host smart-dcbe9c45-7f1b-4d13-9087-0a865aacb312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696388494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2696388494
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3428445064
Short name T850
Test name
Test status
Simulation time 30234715 ps
CPU time 1.21 seconds
Started Aug 08 07:43:37 PM PDT 24
Finished Aug 08 07:43:38 PM PDT 24
Peak memory 218472 kb
Host smart-8388545e-02ee-48a2-abd6-64d127b67600
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428445064 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3428445064
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_genbits.479020673
Short name T809
Test name
Test status
Simulation time 42791925 ps
CPU time 1.28 seconds
Started Aug 08 07:43:36 PM PDT 24
Finished Aug 08 07:43:38 PM PDT 24
Peak memory 218396 kb
Host smart-430cdb39-ea88-4d7f-a8a6-048e612a94cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479020673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.479020673
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1477553788
Short name T567
Test name
Test status
Simulation time 36627520 ps
CPU time 0.9 seconds
Started Aug 08 07:43:37 PM PDT 24
Finished Aug 08 07:43:38 PM PDT 24
Peak memory 215276 kb
Host smart-6775eeed-cf16-4c03-bd0e-98bd7cdf03fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477553788 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1477553788
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3582095173
Short name T859
Test name
Test status
Simulation time 25060759 ps
CPU time 0.96 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 207180 kb
Host smart-b4bcfc74-103d-419e-a64e-0366951d45a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582095173 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3582095173
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2616631799
Short name T496
Test name
Test status
Simulation time 206723570 ps
CPU time 4.24 seconds
Started Aug 08 07:43:39 PM PDT 24
Finished Aug 08 07:43:43 PM PDT 24
Peak memory 215324 kb
Host smart-1035f158-aa31-4023-81f2-5ce7b99862b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616631799 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2616631799
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_alert.2953612313
Short name T835
Test name
Test status
Simulation time 94279755 ps
CPU time 1.19 seconds
Started Aug 08 07:45:26 PM PDT 24
Finished Aug 08 07:45:27 PM PDT 24
Peak memory 219604 kb
Host smart-d915e774-f838-4001-8741-4e50978df463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953612313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2953612313
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1914062479
Short name T827
Test name
Test status
Simulation time 120398982 ps
CPU time 1.8 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 218764 kb
Host smart-96932849-a823-422d-a835-dab5ef323a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914062479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1914062479
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3902294273
Short name T904
Test name
Test status
Simulation time 90773932 ps
CPU time 1.35 seconds
Started Aug 08 07:45:30 PM PDT 24
Finished Aug 08 07:45:31 PM PDT 24
Peak memory 215600 kb
Host smart-db1384d0-8ebb-4a4e-b3bb-7cb4a87a4e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902294273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3902294273
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1324469078
Short name T370
Test name
Test status
Simulation time 55849855 ps
CPU time 1.93 seconds
Started Aug 08 07:45:28 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 218612 kb
Host smart-f25974c2-f521-466a-86a5-746ba25b29fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324469078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1324469078
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1050678513
Short name T945
Test name
Test status
Simulation time 78963648 ps
CPU time 1.21 seconds
Started Aug 08 07:45:25 PM PDT 24
Finished Aug 08 07:45:27 PM PDT 24
Peak memory 219460 kb
Host smart-3c6bf4d9-47f1-46c0-9d6d-ebe1ec5a50af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050678513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1050678513
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.706033349
Short name T419
Test name
Test status
Simulation time 111117966 ps
CPU time 1.27 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 219980 kb
Host smart-0dcde9d0-2254-4e83-bf61-3af43562bd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706033349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.706033349
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.3175415403
Short name T475
Test name
Test status
Simulation time 34974466 ps
CPU time 1.24 seconds
Started Aug 08 07:45:27 PM PDT 24
Finished Aug 08 07:45:29 PM PDT 24
Peak memory 218716 kb
Host smart-8f621491-d629-4ab7-9a4b-421d874946f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175415403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.3175415403
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1677886681
Short name T431
Test name
Test status
Simulation time 32698238 ps
CPU time 1.35 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 220076 kb
Host smart-a8677fdb-2093-488b-90f5-8e6b81c7413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677886681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1677886681
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.313850080
Short name T955
Test name
Test status
Simulation time 26732101 ps
CPU time 1.22 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 218444 kb
Host smart-fbd858b5-6865-468b-9f06-b2b0c78ea625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313850080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.313850080
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.421885071
Short name T626
Test name
Test status
Simulation time 42025152 ps
CPU time 1.62 seconds
Started Aug 08 07:45:28 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 217772 kb
Host smart-cd7f023f-0604-465a-8a22-4af34274dcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421885071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.421885071
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3195293565
Short name T892
Test name
Test status
Simulation time 65224839 ps
CPU time 1.04 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:32 PM PDT 24
Peak memory 218220 kb
Host smart-6ddb1bb3-58e2-42af-8e82-d69751c45625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195293565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3195293565
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2765610114
Short name T511
Test name
Test status
Simulation time 89859879 ps
CPU time 1.25 seconds
Started Aug 08 07:45:30 PM PDT 24
Finished Aug 08 07:45:32 PM PDT 24
Peak memory 217292 kb
Host smart-9fce3e0a-f6ce-498a-ba41-755465995fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765610114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2765610114
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.2139125751
Short name T861
Test name
Test status
Simulation time 53219321 ps
CPU time 1.2 seconds
Started Aug 08 07:45:30 PM PDT 24
Finished Aug 08 07:45:31 PM PDT 24
Peak memory 219804 kb
Host smart-1871f7bb-1284-4c7a-ba39-d3cb4eae8309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139125751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2139125751
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.8867197
Short name T252
Test name
Test status
Simulation time 39995261 ps
CPU time 1.47 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:31 PM PDT 24
Peak memory 220104 kb
Host smart-5fc4791e-a632-4589-a715-9d54e5c7c540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8867197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.8867197
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1991150735
Short name T264
Test name
Test status
Simulation time 74788898 ps
CPU time 1.35 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 219844 kb
Host smart-d5b441a0-294b-46e6-9f15-13b5ae7c56f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991150735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1991150735
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2072488258
Short name T993
Test name
Test status
Simulation time 100147964 ps
CPU time 1.45 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:31 PM PDT 24
Peak memory 218624 kb
Host smart-604cfbee-bab4-4256-8f89-95e2fa2a8bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072488258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2072488258
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.661555747
Short name T299
Test name
Test status
Simulation time 400343820 ps
CPU time 1.36 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 218292 kb
Host smart-8dbb4947-c671-474f-a6e3-27f5e740e5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661555747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.661555747
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3081851409
Short name T969
Test name
Test status
Simulation time 44583093 ps
CPU time 2.05 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 218648 kb
Host smart-c40a7c04-9c53-4864-b072-7e32649cff4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081851409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3081851409
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2181764192
Short name T895
Test name
Test status
Simulation time 340714338 ps
CPU time 1.46 seconds
Started Aug 08 07:45:27 PM PDT 24
Finished Aug 08 07:45:29 PM PDT 24
Peak memory 215580 kb
Host smart-f178aae6-3dcf-4c42-ae84-f39f49d31ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181764192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2181764192
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.137499880
Short name T708
Test name
Test status
Simulation time 41647312 ps
CPU time 1.47 seconds
Started Aug 08 07:45:30 PM PDT 24
Finished Aug 08 07:45:32 PM PDT 24
Peak memory 218740 kb
Host smart-f7c787e3-5444-48ac-8ab8-ae6af8bfd6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137499880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.137499880
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3787234586
Short name T193
Test name
Test status
Simulation time 179931507 ps
CPU time 1.27 seconds
Started Aug 08 07:43:50 PM PDT 24
Finished Aug 08 07:43:51 PM PDT 24
Peak memory 219404 kb
Host smart-15d344ae-940e-42be-a0f8-cb07fc71f704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787234586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3787234586
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.624989427
Short name T611
Test name
Test status
Simulation time 19420522 ps
CPU time 0.86 seconds
Started Aug 08 07:43:44 PM PDT 24
Finished Aug 08 07:43:45 PM PDT 24
Peak memory 206852 kb
Host smart-64803896-8e4c-4497-b9cd-a7508ef38bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624989427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.624989427
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_err.1821528172
Short name T880
Test name
Test status
Simulation time 19905408 ps
CPU time 1.14 seconds
Started Aug 08 07:43:43 PM PDT 24
Finished Aug 08 07:43:44 PM PDT 24
Peak memory 219788 kb
Host smart-3ac950a8-8c8c-4eb2-a16a-f1e74346ef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821528172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1821528172
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.200063133
Short name T996
Test name
Test status
Simulation time 22288988 ps
CPU time 1.04 seconds
Started Aug 08 07:43:43 PM PDT 24
Finished Aug 08 07:43:44 PM PDT 24
Peak memory 216404 kb
Host smart-71ed3281-4179-4b23-a4d8-dcde0ab9b1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200063133 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.200063133
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1656597110
Short name T595
Test name
Test status
Simulation time 30464370 ps
CPU time 0.92 seconds
Started Aug 08 07:43:45 PM PDT 24
Finished Aug 08 07:43:46 PM PDT 24
Peak memory 213776 kb
Host smart-727dc7fc-7745-4ebd-abdf-147cac1a4bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656597110 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1656597110
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.734226084
Short name T923
Test name
Test status
Simulation time 620660189 ps
CPU time 5.17 seconds
Started Aug 08 07:43:43 PM PDT 24
Finished Aug 08 07:43:49 PM PDT 24
Peak memory 215460 kb
Host smart-f9a80957-1ee4-4898-b5ca-9444a561d501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734226084 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.734226084
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.130969893
Short name T916
Test name
Test status
Simulation time 28236866940 ps
CPU time 604.25 seconds
Started Aug 08 07:43:53 PM PDT 24
Finished Aug 08 07:53:58 PM PDT 24
Peak memory 223588 kb
Host smart-1322fb72-1d3e-49b2-86ea-7f6868ccf15b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130969893 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.130969893
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1130489438
Short name T559
Test name
Test status
Simulation time 25858360 ps
CPU time 1.24 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:32 PM PDT 24
Peak memory 219688 kb
Host smart-2c3df90b-2fd1-4db6-8595-78a3b77d8a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130489438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1130489438
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/171.edn_alert.4266956045
Short name T97
Test name
Test status
Simulation time 92282782 ps
CPU time 1.14 seconds
Started Aug 08 07:45:32 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 220320 kb
Host smart-b9665790-f397-4f55-8fc5-550e65308555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266956045 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.4266956045
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.2591491574
Short name T954
Test name
Test status
Simulation time 82969337 ps
CPU time 1.33 seconds
Started Aug 08 07:45:27 PM PDT 24
Finished Aug 08 07:45:28 PM PDT 24
Peak memory 218940 kb
Host smart-6d242f9a-7e16-47fd-b881-aa42df7eba7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591491574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2591491574
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.2339651536
Short name T131
Test name
Test status
Simulation time 48847420 ps
CPU time 1.24 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 218536 kb
Host smart-b78bc849-7a32-4946-9f5b-d69c3057b892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339651536 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2339651536
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.4187525332
Short name T501
Test name
Test status
Simulation time 37891682 ps
CPU time 1.65 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 218708 kb
Host smart-96c41c48-295a-47a4-874b-53c5417577c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187525332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.4187525332
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1074086726
Short name T643
Test name
Test status
Simulation time 25323284 ps
CPU time 1.18 seconds
Started Aug 08 07:45:32 PM PDT 24
Finished Aug 08 07:45:34 PM PDT 24
Peak memory 219584 kb
Host smart-cb733d02-7a31-40d0-b7cb-5832ed54025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074086726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1074086726
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.4254895942
Short name T356
Test name
Test status
Simulation time 31101111 ps
CPU time 1.3 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 218648 kb
Host smart-493b3eeb-f031-437e-92fe-4b6fc1338f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254895942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.4254895942
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.3327077509
Short name T915
Test name
Test status
Simulation time 78878957 ps
CPU time 1.18 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 219964 kb
Host smart-db253578-8346-45cd-8b58-a26e40d9234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327077509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3327077509
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2351301138
Short name T382
Test name
Test status
Simulation time 117725695 ps
CPU time 1.42 seconds
Started Aug 08 07:45:33 PM PDT 24
Finished Aug 08 07:45:34 PM PDT 24
Peak memory 218640 kb
Host smart-06e06791-df22-461c-8700-d5e213142d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351301138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2351301138
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3260312354
Short name T807
Test name
Test status
Simulation time 21513631 ps
CPU time 1.09 seconds
Started Aug 08 07:45:27 PM PDT 24
Finished Aug 08 07:45:29 PM PDT 24
Peak memory 218656 kb
Host smart-a8d5044b-67d8-4c30-86bc-fab4af1df2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260312354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3260312354
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.1144277845
Short name T673
Test name
Test status
Simulation time 24637925 ps
CPU time 1.2 seconds
Started Aug 08 07:45:27 PM PDT 24
Finished Aug 08 07:45:28 PM PDT 24
Peak memory 217776 kb
Host smart-5ac81c61-75f4-417d-9caa-f3e0c5745f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144277845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1144277845
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1406560961
Short name T925
Test name
Test status
Simulation time 57473450 ps
CPU time 1.13 seconds
Started Aug 08 07:45:32 PM PDT 24
Finished Aug 08 07:45:34 PM PDT 24
Peak memory 220284 kb
Host smart-f735fafa-6f53-4d36-b0c2-9419189705b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406560961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1406560961
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.484587307
Short name T604
Test name
Test status
Simulation time 85220052 ps
CPU time 1.25 seconds
Started Aug 08 07:45:28 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 219976 kb
Host smart-95e83d81-8f21-48b3-8648-75a3e1235828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484587307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.484587307
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2159721042
Short name T410
Test name
Test status
Simulation time 374080220 ps
CPU time 1.34 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 219452 kb
Host smart-24a3ef2f-5cb1-4d6a-82ef-3e427e6b298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159721042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2159721042
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2994108588
Short name T843
Test name
Test status
Simulation time 163720093 ps
CPU time 2.27 seconds
Started Aug 08 07:45:33 PM PDT 24
Finished Aug 08 07:45:35 PM PDT 24
Peak memory 220328 kb
Host smart-fae521f6-16be-4798-a7f3-a35d9fbfe544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994108588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2994108588
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2954771213
Short name T747
Test name
Test status
Simulation time 54181377 ps
CPU time 1.19 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 219340 kb
Host smart-d6a2b5e1-f128-4bda-82af-47e6bb6447ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954771213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2954771213
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.2298484718
Short name T254
Test name
Test status
Simulation time 59604147 ps
CPU time 1.25 seconds
Started Aug 08 07:45:32 PM PDT 24
Finished Aug 08 07:45:34 PM PDT 24
Peak memory 218960 kb
Host smart-0ed35942-0b2f-4199-a969-ffa4bb0acf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298484718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2298484718
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2752628028
Short name T900
Test name
Test status
Simulation time 72354533 ps
CPU time 1.18 seconds
Started Aug 08 07:45:32 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 219968 kb
Host smart-ac4b7ec1-8fd5-4cd0-8fec-d43a258b4276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752628028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2752628028
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.1225784445
Short name T960
Test name
Test status
Simulation time 50334928 ps
CPU time 1.28 seconds
Started Aug 08 07:45:31 PM PDT 24
Finished Aug 08 07:45:32 PM PDT 24
Peak memory 217620 kb
Host smart-c98bc13b-ff72-446a-b9fd-4e9000b45525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225784445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1225784445
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1480578241
Short name T847
Test name
Test status
Simulation time 27632527 ps
CPU time 1.22 seconds
Started Aug 08 07:43:49 PM PDT 24
Finished Aug 08 07:43:51 PM PDT 24
Peak memory 215568 kb
Host smart-23e6448b-edcb-4bb6-a490-370d053d5401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480578241 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1480578241
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.383461882
Short name T600
Test name
Test status
Simulation time 76815739 ps
CPU time 0.83 seconds
Started Aug 08 07:43:41 PM PDT 24
Finished Aug 08 07:43:42 PM PDT 24
Peak memory 206648 kb
Host smart-cdf7f238-4bbc-44ae-a63b-25ba763ae260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383461882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.383461882
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.426125785
Short name T621
Test name
Test status
Simulation time 12495420 ps
CPU time 0.89 seconds
Started Aug 08 07:43:43 PM PDT 24
Finished Aug 08 07:43:44 PM PDT 24
Peak memory 216492 kb
Host smart-5f4233de-0ab9-4eaf-8616-522228c49484
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426125785 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.426125785
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.869886259
Short name T560
Test name
Test status
Simulation time 81198328 ps
CPU time 1.01 seconds
Started Aug 08 07:43:42 PM PDT 24
Finished Aug 08 07:43:43 PM PDT 24
Peak memory 219364 kb
Host smart-da97e135-1fe2-4bfe-9ba3-365af372cf75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869886259 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.869886259
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2096094454
Short name T173
Test name
Test status
Simulation time 35321899 ps
CPU time 0.96 seconds
Started Aug 08 07:43:51 PM PDT 24
Finished Aug 08 07:43:53 PM PDT 24
Peak memory 223976 kb
Host smart-85af6c05-8069-4a8a-a3b9-958d46f5b43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096094454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2096094454
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3932376231
Short name T939
Test name
Test status
Simulation time 258285173 ps
CPU time 3.55 seconds
Started Aug 08 07:43:53 PM PDT 24
Finished Aug 08 07:43:56 PM PDT 24
Peak memory 220368 kb
Host smart-69b98b5d-866c-4863-8aca-e85fe12289aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932376231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3932376231
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.26841901
Short name T794
Test name
Test status
Simulation time 36565860 ps
CPU time 1.01 seconds
Started Aug 08 07:43:44 PM PDT 24
Finished Aug 08 07:43:45 PM PDT 24
Peak memory 215420 kb
Host smart-7e0c8a1a-5042-40f7-a1f4-0af59ea96b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26841901 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.26841901
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.442216247
Short name T768
Test name
Test status
Simulation time 46477633 ps
CPU time 0.89 seconds
Started Aug 08 07:43:43 PM PDT 24
Finished Aug 08 07:43:44 PM PDT 24
Peak memory 215260 kb
Host smart-034d00ba-87a1-4245-855e-9ef119332e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442216247 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.442216247
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1356239098
Short name T400
Test name
Test status
Simulation time 167955778 ps
CPU time 2.31 seconds
Started Aug 08 07:43:45 PM PDT 24
Finished Aug 08 07:43:48 PM PDT 24
Peak memory 217276 kb
Host smart-672dcf10-1e8e-468a-a15c-97171e39ce71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356239098 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1356239098
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.801289018
Short name T605
Test name
Test status
Simulation time 48290342986 ps
CPU time 1084.15 seconds
Started Aug 08 07:43:42 PM PDT 24
Finished Aug 08 08:01:47 PM PDT 24
Peak memory 219364 kb
Host smart-0f45dccd-68e9-47a0-a7e9-51019ce066a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801289018 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.801289018
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1797510453
Short name T841
Test name
Test status
Simulation time 27762844 ps
CPU time 1.28 seconds
Started Aug 08 07:45:34 PM PDT 24
Finished Aug 08 07:45:35 PM PDT 24
Peak memory 218792 kb
Host smart-7d244008-8873-497e-9066-c25ba28de189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797510453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1797510453
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1488017002
Short name T782
Test name
Test status
Simulation time 42259803 ps
CPU time 1.16 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 217484 kb
Host smart-2569b3c9-f674-4283-94fd-b75ccb6b7dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488017002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1488017002
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2299295826
Short name T986
Test name
Test status
Simulation time 74462202 ps
CPU time 1.15 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 218736 kb
Host smart-b7934765-3182-4858-a313-1f87730f70ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299295826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2299295826
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.2199391786
Short name T785
Test name
Test status
Simulation time 255348237 ps
CPU time 3.15 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:32 PM PDT 24
Peak memory 219996 kb
Host smart-1f3f396a-5d3f-4472-baf5-776d0201a59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199391786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2199391786
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2666337115
Short name T589
Test name
Test status
Simulation time 271165916 ps
CPU time 1.32 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 215564 kb
Host smart-3cf9db63-5f7d-406d-a515-d1298295ca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666337115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2666337115
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1954852328
Short name T890
Test name
Test status
Simulation time 55577146 ps
CPU time 1.84 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:31 PM PDT 24
Peak memory 220092 kb
Host smart-fd835ffe-f43a-47fe-b401-2271ceb2e23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954852328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1954852328
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.2974701607
Short name T741
Test name
Test status
Simulation time 29518260 ps
CPU time 1.21 seconds
Started Aug 08 07:45:35 PM PDT 24
Finished Aug 08 07:45:36 PM PDT 24
Peak memory 215568 kb
Host smart-3fd999e9-6d2e-4857-ac68-cbd9713265cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974701607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2974701607
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/184.edn_alert.3112742172
Short name T102
Test name
Test status
Simulation time 71003302 ps
CPU time 1.08 seconds
Started Aug 08 07:45:35 PM PDT 24
Finished Aug 08 07:45:36 PM PDT 24
Peak memory 218672 kb
Host smart-18d8f7ff-cee7-43d1-b30e-441923022da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112742172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3112742172
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.3545107883
Short name T647
Test name
Test status
Simulation time 81016400 ps
CPU time 1.04 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:37 PM PDT 24
Peak memory 217308 kb
Host smart-5581448f-cd68-443d-99a0-396164327262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545107883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3545107883
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2523225122
Short name T139
Test name
Test status
Simulation time 58093663 ps
CPU time 1.42 seconds
Started Aug 08 07:45:32 PM PDT 24
Finished Aug 08 07:45:34 PM PDT 24
Peak memory 218456 kb
Host smart-b641b928-39cc-42fa-abd7-49daed6af3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523225122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2523225122
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2418435337
Short name T460
Test name
Test status
Simulation time 51559589 ps
CPU time 1.33 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:38 PM PDT 24
Peak memory 218868 kb
Host smart-7541b472-b93c-48c3-9dc1-5a669a53f837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418435337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2418435337
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.1390304847
Short name T177
Test name
Test status
Simulation time 22364734 ps
CPU time 1.15 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:37 PM PDT 24
Peak memory 219584 kb
Host smart-d00c3cc7-14d0-4d0c-afc4-48aa56367b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390304847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.1390304847
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.4140413971
Short name T388
Test name
Test status
Simulation time 75671425 ps
CPU time 1.28 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:37 PM PDT 24
Peak memory 218524 kb
Host smart-2aaa8cb4-83a1-4a4a-8408-5cdbf5dc1441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140413971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4140413971
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.423848409
Short name T657
Test name
Test status
Simulation time 41636280 ps
CPU time 1.17 seconds
Started Aug 08 07:45:28 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 219276 kb
Host smart-a86ac257-9e72-499d-a503-29043c67b18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423848409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.423848409
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.789653264
Short name T555
Test name
Test status
Simulation time 73078909 ps
CPU time 1.31 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:31 PM PDT 24
Peak memory 217104 kb
Host smart-bd751891-d9f8-454a-be7b-c26a33f50738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789653264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.789653264
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.1771782948
Short name T903
Test name
Test status
Simulation time 39297003 ps
CPU time 1.12 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:30 PM PDT 24
Peak memory 219948 kb
Host smart-d7a7cf42-6a84-4370-8b9d-9ae7a064264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771782948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1771782948
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3075212656
Short name T409
Test name
Test status
Simulation time 99244270 ps
CPU time 1.86 seconds
Started Aug 08 07:45:30 PM PDT 24
Finished Aug 08 07:45:33 PM PDT 24
Peak memory 218852 kb
Host smart-b6490238-f8cd-49da-a4c5-e84c2943f33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075212656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3075212656
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.1523150896
Short name T322
Test name
Test status
Simulation time 23365081 ps
CPU time 1.1 seconds
Started Aug 08 07:45:29 PM PDT 24
Finished Aug 08 07:45:31 PM PDT 24
Peak memory 218812 kb
Host smart-e641e39d-f983-4f93-8d83-9415f36b8791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523150896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1523150896
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.780817096
Short name T521
Test name
Test status
Simulation time 128579378 ps
CPU time 1.08 seconds
Started Aug 08 07:45:30 PM PDT 24
Finished Aug 08 07:45:32 PM PDT 24
Peak memory 217432 kb
Host smart-fd6a518a-f485-4ab5-ac95-5162a5fd72c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780817096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.780817096
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2283885419
Short name T40
Test name
Test status
Simulation time 29188381 ps
CPU time 1.24 seconds
Started Aug 08 07:43:41 PM PDT 24
Finished Aug 08 07:43:42 PM PDT 24
Peak memory 219868 kb
Host smart-30b4238c-1ec5-4727-a9e4-6f6c65988e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283885419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2283885419
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1377973806
Short name T455
Test name
Test status
Simulation time 157893388 ps
CPU time 0.95 seconds
Started Aug 08 07:43:41 PM PDT 24
Finished Aug 08 07:43:42 PM PDT 24
Peak memory 206856 kb
Host smart-2954fdee-a366-4c64-ab48-25faf1051a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377973806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1377973806
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.171807119
Short name T72
Test name
Test status
Simulation time 12324882 ps
CPU time 0.86 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:53 PM PDT 24
Peak memory 216472 kb
Host smart-816b6861-59e3-469a-8c35-fbbac8295d53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171807119 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.171807119
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.629033986
Short name T615
Test name
Test status
Simulation time 63895561 ps
CPU time 1.02 seconds
Started Aug 08 07:43:42 PM PDT 24
Finished Aug 08 07:43:43 PM PDT 24
Peak memory 217260 kb
Host smart-cd54ccc6-f54f-4cf6-be87-060615ee4cbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629033986 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.629033986
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.351696543
Short name T433
Test name
Test status
Simulation time 65538941 ps
CPU time 0.99 seconds
Started Aug 08 07:43:43 PM PDT 24
Finished Aug 08 07:43:44 PM PDT 24
Peak memory 218888 kb
Host smart-b701286b-2601-44c1-922a-52789b5d9767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351696543 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.351696543
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3573715529
Short name T676
Test name
Test status
Simulation time 64613545 ps
CPU time 1.39 seconds
Started Aug 08 07:43:45 PM PDT 24
Finished Aug 08 07:43:46 PM PDT 24
Peak memory 216920 kb
Host smart-141c900b-72d0-4690-b87b-f8bce4a87b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573715529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3573715529
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2363588953
Short name T449
Test name
Test status
Simulation time 22612071 ps
CPU time 1.19 seconds
Started Aug 08 07:43:46 PM PDT 24
Finished Aug 08 07:43:47 PM PDT 24
Peak memory 224132 kb
Host smart-8859836e-9de5-4e11-a379-d356bea70c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363588953 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2363588953
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.678441325
Short name T437
Test name
Test status
Simulation time 39934093 ps
CPU time 0.92 seconds
Started Aug 08 07:43:46 PM PDT 24
Finished Aug 08 07:43:47 PM PDT 24
Peak memory 215324 kb
Host smart-f46a5560-db8e-42f0-98b7-7becdd9d538d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678441325 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.678441325
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3334762148
Short name T60
Test name
Test status
Simulation time 284616417 ps
CPU time 5.76 seconds
Started Aug 08 07:43:45 PM PDT 24
Finished Aug 08 07:43:51 PM PDT 24
Peak memory 218724 kb
Host smart-7c9eab1e-95fe-4246-ba99-78b9d9953d47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334762148 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3334762148
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2850205982
Short name T235
Test name
Test status
Simulation time 106273895826 ps
CPU time 1221.94 seconds
Started Aug 08 07:43:41 PM PDT 24
Finished Aug 08 08:04:03 PM PDT 24
Peak memory 224128 kb
Host smart-43f0eb08-4cc0-482f-ab56-c9c9b5c2b9cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850205982 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2850205982
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.4214497729
Short name T886
Test name
Test status
Simulation time 67040749 ps
CPU time 1.08 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:37 PM PDT 24
Peak memory 218504 kb
Host smart-e9eeb550-2d77-4510-afed-aabba063c75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214497729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.4214497729
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.1160146940
Short name T610
Test name
Test status
Simulation time 44931841 ps
CPU time 1.55 seconds
Started Aug 08 07:45:33 PM PDT 24
Finished Aug 08 07:45:35 PM PDT 24
Peak memory 218712 kb
Host smart-23fa97fa-c403-4ffe-b812-39c391bb1a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160146940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1160146940
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.4025343633
Short name T261
Test name
Test status
Simulation time 90814465 ps
CPU time 1.19 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:37 PM PDT 24
Peak memory 219504 kb
Host smart-8040525a-253d-4f72-a0bc-d836cbe1fbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025343633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.4025343633
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.1518218553
Short name T826
Test name
Test status
Simulation time 98911724 ps
CPU time 1.64 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:38 PM PDT 24
Peak memory 218996 kb
Host smart-d6de48d3-459b-4ff4-bb4e-314b9b7e866e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518218553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1518218553
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.414805577
Short name T470
Test name
Test status
Simulation time 39472208 ps
CPU time 1.1 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:38 PM PDT 24
Peak memory 219668 kb
Host smart-4a8bb867-9003-4e99-8b29-e4e5305dd951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414805577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.414805577
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3937155907
Short name T110
Test name
Test status
Simulation time 57974239 ps
CPU time 1.47 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 218772 kb
Host smart-d8f7bb1c-ab9c-4b20-add0-42909e7b70f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937155907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3937155907
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.207988160
Short name T185
Test name
Test status
Simulation time 27442209 ps
CPU time 1.21 seconds
Started Aug 08 07:45:41 PM PDT 24
Finished Aug 08 07:45:42 PM PDT 24
Peak memory 219716 kb
Host smart-e4c859fd-00d1-4282-a86e-07ac6febe8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207988160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.207988160
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2865325227
Short name T487
Test name
Test status
Simulation time 188207276 ps
CPU time 1.75 seconds
Started Aug 08 07:45:41 PM PDT 24
Finished Aug 08 07:45:43 PM PDT 24
Peak memory 218824 kb
Host smart-62c84244-067b-443c-952c-fa5ebb3496ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865325227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2865325227
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2443192546
Short name T759
Test name
Test status
Simulation time 71515792 ps
CPU time 1.09 seconds
Started Aug 08 07:45:40 PM PDT 24
Finished Aug 08 07:45:41 PM PDT 24
Peak memory 220248 kb
Host smart-fa2184f3-f3e3-4024-8ddb-4ece5679edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443192546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2443192546
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2719033119
Short name T375
Test name
Test status
Simulation time 26021013 ps
CPU time 1.03 seconds
Started Aug 08 07:45:37 PM PDT 24
Finished Aug 08 07:45:38 PM PDT 24
Peak memory 217232 kb
Host smart-2f3bb3ef-f36d-4c11-8b3e-735427800bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719033119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2719033119
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.1576561066
Short name T802
Test name
Test status
Simulation time 36379115 ps
CPU time 1.08 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:37 PM PDT 24
Peak memory 218432 kb
Host smart-a612d89e-bd43-42d5-b03a-f7ee4a30ad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576561066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.1576561066
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3900854224
Short name T924
Test name
Test status
Simulation time 54670525 ps
CPU time 1.66 seconds
Started Aug 08 07:45:44 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 218548 kb
Host smart-5357f08f-fa5f-4531-9c97-fb0aa09f130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900854224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3900854224
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.727885922
Short name T889
Test name
Test status
Simulation time 84532245 ps
CPU time 1.2 seconds
Started Aug 08 07:45:34 PM PDT 24
Finished Aug 08 07:45:36 PM PDT 24
Peak memory 219536 kb
Host smart-5ee53ff9-713c-4755-9e48-b17d5bcf957e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727885922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.727885922
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.217956966
Short name T934
Test name
Test status
Simulation time 56852522 ps
CPU time 1.17 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 217336 kb
Host smart-66568159-d901-471a-b07e-3ed0ae14fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217956966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.217956966
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.633087251
Short name T737
Test name
Test status
Simulation time 71377174 ps
CPU time 2.53 seconds
Started Aug 08 07:45:37 PM PDT 24
Finished Aug 08 07:45:40 PM PDT 24
Peak memory 217756 kb
Host smart-1f9c1adf-44e1-42d8-98e4-138ed9d39e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633087251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.633087251
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2776978493
Short name T288
Test name
Test status
Simulation time 65092273 ps
CPU time 1.22 seconds
Started Aug 08 07:45:37 PM PDT 24
Finished Aug 08 07:45:38 PM PDT 24
Peak memory 218476 kb
Host smart-e743956b-2b1e-48a1-9f2e-b70c321d28da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776978493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2776978493
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3710371824
Short name T808
Test name
Test status
Simulation time 49365547 ps
CPU time 1.25 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:38 PM PDT 24
Peak memory 217340 kb
Host smart-b626bc49-0d84-42c3-9f40-6cb9811290d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710371824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3710371824
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1918261277
Short name T769
Test name
Test status
Simulation time 90045779 ps
CPU time 1.22 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:37 PM PDT 24
Peak memory 218708 kb
Host smart-9be45bc2-2e96-4f54-a827-982cbdf39728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918261277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1918261277
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.4091036765
Short name T928
Test name
Test status
Simulation time 97070829 ps
CPU time 2.1 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 217520 kb
Host smart-fb643efa-b859-4bec-9530-4819363a7b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091036765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4091036765
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1355581995
Short name T739
Test name
Test status
Simulation time 33999851 ps
CPU time 1.09 seconds
Started Aug 08 07:43:14 PM PDT 24
Finished Aug 08 07:43:15 PM PDT 24
Peak memory 218248 kb
Host smart-153beaa8-b6f2-4b65-808f-0a1e305c1982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355581995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1355581995
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3128078441
Short name T937
Test name
Test status
Simulation time 11529069 ps
CPU time 0.86 seconds
Started Aug 08 07:43:13 PM PDT 24
Finished Aug 08 07:43:14 PM PDT 24
Peak memory 206880 kb
Host smart-96dcace6-dec8-4aa7-91e8-0bba906f048f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128078441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3128078441
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.268979886
Short name T482
Test name
Test status
Simulation time 25124969 ps
CPU time 0.92 seconds
Started Aug 08 07:43:12 PM PDT 24
Finished Aug 08 07:43:13 PM PDT 24
Peak memory 216272 kb
Host smart-2d0e2dc0-49e8-4c61-8ae4-5b1d760755ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268979886 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.268979886
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.732983598
Short name T679
Test name
Test status
Simulation time 54814107 ps
CPU time 1.09 seconds
Started Aug 08 07:43:11 PM PDT 24
Finished Aug 08 07:43:12 PM PDT 24
Peak memory 219592 kb
Host smart-7644614d-00a2-4c28-89a8-0307341ba3c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732983598 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.732983598
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2024619934
Short name T120
Test name
Test status
Simulation time 35478895 ps
CPU time 1.09 seconds
Started Aug 08 07:43:12 PM PDT 24
Finished Aug 08 07:43:13 PM PDT 24
Peak memory 221000 kb
Host smart-729e09e5-7657-4987-95b7-1df948a7368b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024619934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2024619934
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3485089421
Short name T456
Test name
Test status
Simulation time 43764380 ps
CPU time 1.59 seconds
Started Aug 08 07:43:15 PM PDT 24
Finished Aug 08 07:43:17 PM PDT 24
Peak memory 220256 kb
Host smart-858cc56b-c181-4e25-a8dc-76be83523048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485089421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3485089421
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1112872191
Short name T575
Test name
Test status
Simulation time 28205230 ps
CPU time 0.95 seconds
Started Aug 08 07:43:10 PM PDT 24
Finished Aug 08 07:43:11 PM PDT 24
Peak memory 215496 kb
Host smart-f0a755bb-8293-486d-b751-d79a68727b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112872191 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1112872191
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3363328340
Short name T710
Test name
Test status
Simulation time 54306741 ps
CPU time 0.93 seconds
Started Aug 08 07:43:15 PM PDT 24
Finished Aug 08 07:43:16 PM PDT 24
Peak memory 207128 kb
Host smart-2403c408-6b5c-42ec-ae43-e47520b99770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363328340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3363328340
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.737025275
Short name T17
Test name
Test status
Simulation time 258905207 ps
CPU time 4.97 seconds
Started Aug 08 07:43:16 PM PDT 24
Finished Aug 08 07:43:21 PM PDT 24
Peak memory 240100 kb
Host smart-e9727875-e649-4732-bdc1-cbb0dc28a3f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737025275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.737025275
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2903906441
Short name T877
Test name
Test status
Simulation time 24067496 ps
CPU time 0.92 seconds
Started Aug 08 07:43:12 PM PDT 24
Finished Aug 08 07:43:14 PM PDT 24
Peak memory 215332 kb
Host smart-782685f5-3187-44f6-9a3d-9aa0677669a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903906441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2903906441
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2687984294
Short name T520
Test name
Test status
Simulation time 399289588 ps
CPU time 4.39 seconds
Started Aug 08 07:43:13 PM PDT 24
Finished Aug 08 07:43:18 PM PDT 24
Peak memory 217204 kb
Host smart-bf136067-0c67-4251-a729-4d1d0da49d24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687984294 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2687984294
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1163295935
Short name T238
Test name
Test status
Simulation time 198282984393 ps
CPU time 1128.08 seconds
Started Aug 08 07:43:14 PM PDT 24
Finished Aug 08 08:02:02 PM PDT 24
Peak memory 223632 kb
Host smart-b7bac45e-1100-444a-86e3-ff34a97b2c1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163295935 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1163295935
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2091675916
Short name T118
Test name
Test status
Simulation time 37164057 ps
CPU time 1.11 seconds
Started Aug 08 07:43:43 PM PDT 24
Finished Aug 08 07:43:45 PM PDT 24
Peak memory 218896 kb
Host smart-eb4818a2-66a7-4fbe-8d78-7e1c738d819f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091675916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2091675916
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2432514765
Short name T700
Test name
Test status
Simulation time 48813834 ps
CPU time 0.96 seconds
Started Aug 08 07:43:46 PM PDT 24
Finished Aug 08 07:43:47 PM PDT 24
Peak memory 215248 kb
Host smart-4b4962ef-8c30-4c45-8049-bbdf591d90a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432514765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2432514765
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.695079975
Short name T797
Test name
Test status
Simulation time 24468040 ps
CPU time 0.88 seconds
Started Aug 08 07:43:46 PM PDT 24
Finished Aug 08 07:43:47 PM PDT 24
Peak memory 216528 kb
Host smart-2771700e-6551-42c0-8092-b977f095e068
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695079975 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.695079975
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2217467965
Short name T948
Test name
Test status
Simulation time 24847116 ps
CPU time 1.01 seconds
Started Aug 08 07:43:49 PM PDT 24
Finished Aug 08 07:43:51 PM PDT 24
Peak memory 218364 kb
Host smart-fe2a03f7-b852-41af-9887-fa011e0f4636
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217467965 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2217467965
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2083791471
Short name T426
Test name
Test status
Simulation time 31572701 ps
CPU time 1.02 seconds
Started Aug 08 07:43:43 PM PDT 24
Finished Aug 08 07:43:44 PM PDT 24
Peak memory 218788 kb
Host smart-709d940d-07ba-4ddb-bfa2-75dce551bd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083791471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2083791471
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2773856019
Short name T857
Test name
Test status
Simulation time 69236998 ps
CPU time 1.15 seconds
Started Aug 08 07:43:45 PM PDT 24
Finished Aug 08 07:43:46 PM PDT 24
Peak memory 217404 kb
Host smart-5f82228b-6cde-4100-8731-fcae05c00bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773856019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2773856019
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3470350607
Short name T672
Test name
Test status
Simulation time 32768741 ps
CPU time 1.01 seconds
Started Aug 08 07:43:46 PM PDT 24
Finished Aug 08 07:43:47 PM PDT 24
Peak memory 224164 kb
Host smart-199f27ae-a017-450d-bde3-4c762ad8d1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470350607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3470350607
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.604411205
Short name T838
Test name
Test status
Simulation time 50862117 ps
CPU time 0.9 seconds
Started Aug 08 07:43:44 PM PDT 24
Finished Aug 08 07:43:45 PM PDT 24
Peak memory 215308 kb
Host smart-544f0ac8-5239-4e33-aa02-e825c03d60ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604411205 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.604411205
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1011643511
Short name T976
Test name
Test status
Simulation time 391790296 ps
CPU time 3.94 seconds
Started Aug 08 07:43:44 PM PDT 24
Finished Aug 08 07:43:48 PM PDT 24
Peak memory 215400 kb
Host smart-e8b88f61-9bee-4bc8-a542-f317f7a5b76d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011643511 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1011643511
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/200.edn_genbits.1607275216
Short name T483
Test name
Test status
Simulation time 64537975 ps
CPU time 1 seconds
Started Aug 08 07:45:35 PM PDT 24
Finished Aug 08 07:45:37 PM PDT 24
Peak memory 217304 kb
Host smart-7c5725b9-fc7c-4fa9-8954-30db33fd555a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607275216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1607275216
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2513703960
Short name T108
Test name
Test status
Simulation time 42253290 ps
CPU time 1.48 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:48 PM PDT 24
Peak memory 217636 kb
Host smart-b97e7abe-10a9-4534-abe0-4ed46717d2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513703960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2513703960
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3622144705
Short name T680
Test name
Test status
Simulation time 187261836 ps
CPU time 1.46 seconds
Started Aug 08 07:45:40 PM PDT 24
Finished Aug 08 07:45:41 PM PDT 24
Peak memory 219160 kb
Host smart-f4de4b82-359d-4f59-8bc6-bed063bf09c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622144705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3622144705
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1116524813
Short name T862
Test name
Test status
Simulation time 126693517 ps
CPU time 1.53 seconds
Started Aug 08 07:45:42 PM PDT 24
Finished Aug 08 07:45:43 PM PDT 24
Peak memory 219372 kb
Host smart-2a9afe5e-af84-47d4-9966-d4e7c0d7fdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116524813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1116524813
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.676047183
Short name T896
Test name
Test status
Simulation time 38675082 ps
CPU time 1.1 seconds
Started Aug 08 07:45:46 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 217464 kb
Host smart-07c06b9e-beda-4217-a2f4-c6d6adef5ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676047183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.676047183
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1129978861
Short name T725
Test name
Test status
Simulation time 41639694 ps
CPU time 1.17 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:37 PM PDT 24
Peak memory 217412 kb
Host smart-144f7c68-b822-4d22-b68e-bc396b1e2466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129978861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1129978861
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3242004706
Short name T333
Test name
Test status
Simulation time 55654656 ps
CPU time 1.22 seconds
Started Aug 08 07:45:40 PM PDT 24
Finished Aug 08 07:45:41 PM PDT 24
Peak memory 217296 kb
Host smart-329c3c16-ae9f-4724-8307-65b91c2312b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242004706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3242004706
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.795680241
Short name T412
Test name
Test status
Simulation time 175187968 ps
CPU time 2.74 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:39 PM PDT 24
Peak memory 219264 kb
Host smart-90b86947-6171-4b5d-8381-39e35b2e7154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795680241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.795680241
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2589455795
Short name T499
Test name
Test status
Simulation time 28447488 ps
CPU time 1.19 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 220000 kb
Host smart-43d52422-6ba9-43dd-9201-263b739812a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589455795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2589455795
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.896302065
Short name T972
Test name
Test status
Simulation time 46584923 ps
CPU time 1.66 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 218468 kb
Host smart-38df652c-0022-431d-82ae-eb1876d1204c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896302065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.896302065
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2087463259
Short name T527
Test name
Test status
Simulation time 29465020 ps
CPU time 1.23 seconds
Started Aug 08 07:43:42 PM PDT 24
Finished Aug 08 07:43:43 PM PDT 24
Peak memory 220692 kb
Host smart-22ef8fa1-c449-4497-b734-384d8ebaf7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087463259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2087463259
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2857203628
Short name T446
Test name
Test status
Simulation time 13013672 ps
CPU time 0.89 seconds
Started Aug 08 07:43:45 PM PDT 24
Finished Aug 08 07:43:46 PM PDT 24
Peak memory 206840 kb
Host smart-3ab75e1d-e664-4b39-8665-1459fe79fcdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857203628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2857203628
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2117589604
Short name T991
Test name
Test status
Simulation time 23992569 ps
CPU time 0.82 seconds
Started Aug 08 07:43:44 PM PDT 24
Finished Aug 08 07:43:45 PM PDT 24
Peak memory 216284 kb
Host smart-c4ab66bb-60f0-42c8-9962-4358c16268db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117589604 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2117589604
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3482145686
Short name T562
Test name
Test status
Simulation time 70233830 ps
CPU time 0.95 seconds
Started Aug 08 07:43:45 PM PDT 24
Finished Aug 08 07:43:46 PM PDT 24
Peak memory 219612 kb
Host smart-4bd73b6b-447e-428f-b128-afeadd4b4ae3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482145686 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3482145686
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2578660978
Short name T151
Test name
Test status
Simulation time 91270248 ps
CPU time 0.96 seconds
Started Aug 08 07:43:41 PM PDT 24
Finished Aug 08 07:43:42 PM PDT 24
Peak memory 218716 kb
Host smart-c491642e-c934-4980-bc15-f9edb533d4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578660978 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2578660978
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1593391043
Short name T614
Test name
Test status
Simulation time 44954156 ps
CPU time 1.36 seconds
Started Aug 08 07:43:46 PM PDT 24
Finished Aug 08 07:43:47 PM PDT 24
Peak memory 220140 kb
Host smart-1aadcc69-8b15-43f1-b2ef-d930cb6cf602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593391043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1593391043
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3367173115
Short name T625
Test name
Test status
Simulation time 21000032 ps
CPU time 1.21 seconds
Started Aug 08 07:43:43 PM PDT 24
Finished Aug 08 07:43:44 PM PDT 24
Peak memory 224124 kb
Host smart-73c275df-7803-4246-b535-dceb5020cc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367173115 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3367173115
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3024275273
Short name T393
Test name
Test status
Simulation time 43728319 ps
CPU time 0.93 seconds
Started Aug 08 07:43:44 PM PDT 24
Finished Aug 08 07:43:45 PM PDT 24
Peak memory 215296 kb
Host smart-181e785b-24f1-4d82-b7a3-69e3f0a0154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024275273 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3024275273
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2272341659
Short name T758
Test name
Test status
Simulation time 342645027 ps
CPU time 6.07 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:59 PM PDT 24
Peak memory 215292 kb
Host smart-4afff650-3a4f-4774-90c7-e8348d6313e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272341659 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2272341659
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1312285130
Short name T968
Test name
Test status
Simulation time 88016395686 ps
CPU time 347.19 seconds
Started Aug 08 07:43:44 PM PDT 24
Finished Aug 08 07:49:31 PM PDT 24
Peak memory 217728 kb
Host smart-70c618ca-d85f-4ff5-a43d-0a731a0ad0a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312285130 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1312285130
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3364995737
Short name T722
Test name
Test status
Simulation time 75473355 ps
CPU time 1.28 seconds
Started Aug 08 07:45:36 PM PDT 24
Finished Aug 08 07:45:37 PM PDT 24
Peak memory 218808 kb
Host smart-8fba7b0e-0ae2-479d-aacb-96c77270ece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364995737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3364995737
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.517947994
Short name T906
Test name
Test status
Simulation time 43512243 ps
CPU time 1.79 seconds
Started Aug 08 07:45:35 PM PDT 24
Finished Aug 08 07:45:37 PM PDT 24
Peak memory 218432 kb
Host smart-e13511e7-8675-4f11-8df1-17930dec544f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517947994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.517947994
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2826678037
Short name T649
Test name
Test status
Simulation time 55590074 ps
CPU time 2.04 seconds
Started Aug 08 07:45:44 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 218736 kb
Host smart-65df4ec9-e02e-4dcf-8b6d-a69b50fb2bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826678037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2826678037
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.132313475
Short name T998
Test name
Test status
Simulation time 21869418 ps
CPU time 1.25 seconds
Started Aug 08 07:45:46 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 218564 kb
Host smart-628df397-e164-4228-8a4e-e33959e10271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132313475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.132313475
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3394637976
Short name T764
Test name
Test status
Simulation time 26207052 ps
CPU time 1.12 seconds
Started Aug 08 07:45:40 PM PDT 24
Finished Aug 08 07:45:41 PM PDT 24
Peak memory 217520 kb
Host smart-4338c277-315e-46a1-ba76-809021506768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394637976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3394637976
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.328692833
Short name T440
Test name
Test status
Simulation time 258054659 ps
CPU time 1.6 seconds
Started Aug 08 07:45:38 PM PDT 24
Finished Aug 08 07:45:39 PM PDT 24
Peak memory 220276 kb
Host smart-12299e43-4d37-4b7d-b6be-6c27ac586dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328692833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.328692833
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2862910883
Short name T593
Test name
Test status
Simulation time 42995244 ps
CPU time 1.37 seconds
Started Aug 08 07:45:41 PM PDT 24
Finished Aug 08 07:45:43 PM PDT 24
Peak memory 215332 kb
Host smart-65c2a36c-471d-4200-ac3d-44f378cd2d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862910883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2862910883
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1027562916
Short name T588
Test name
Test status
Simulation time 75142719 ps
CPU time 1.68 seconds
Started Aug 08 07:45:37 PM PDT 24
Finished Aug 08 07:45:39 PM PDT 24
Peak memory 220180 kb
Host smart-6a695358-4488-4c79-9d3e-81307220c8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027562916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1027562916
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3093705883
Short name T292
Test name
Test status
Simulation time 43773287 ps
CPU time 1.58 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 218592 kb
Host smart-c5af3df5-1d23-46e7-9366-882b24bca5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093705883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3093705883
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1719961085
Short name T22
Test name
Test status
Simulation time 50207254 ps
CPU time 1.87 seconds
Started Aug 08 07:45:41 PM PDT 24
Finished Aug 08 07:45:43 PM PDT 24
Peak memory 220200 kb
Host smart-37ab3a28-d088-4c69-9549-03bcc8f5a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719961085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1719961085
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.2458233340
Short name T421
Test name
Test status
Simulation time 60469933 ps
CPU time 0.99 seconds
Started Aug 08 07:43:43 PM PDT 24
Finished Aug 08 07:43:44 PM PDT 24
Peak memory 206884 kb
Host smart-eb5ab6fb-e5d4-45f8-8445-709fc0ed43a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458233340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2458233340
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2007413970
Short name T618
Test name
Test status
Simulation time 34207717 ps
CPU time 0.84 seconds
Started Aug 08 07:43:43 PM PDT 24
Finished Aug 08 07:43:44 PM PDT 24
Peak memory 216488 kb
Host smart-4f493ee5-88a4-46cf-a920-3ddef6cb7170
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007413970 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2007413970
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.4144182719
Short name T815
Test name
Test status
Simulation time 101022445 ps
CPU time 1.15 seconds
Started Aug 08 07:43:46 PM PDT 24
Finished Aug 08 07:43:48 PM PDT 24
Peak memory 219684 kb
Host smart-20617098-0351-4e73-aa9a-36bdb60d1d5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144182719 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.4144182719
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3438814832
Short name T186
Test name
Test status
Simulation time 28010249 ps
CPU time 1.03 seconds
Started Aug 08 07:43:50 PM PDT 24
Finished Aug 08 07:43:51 PM PDT 24
Peak memory 223980 kb
Host smart-c606d3f0-66cc-4614-8efe-c30ead42cdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438814832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3438814832
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2037446976
Short name T705
Test name
Test status
Simulation time 30802862 ps
CPU time 1.08 seconds
Started Aug 08 07:43:42 PM PDT 24
Finished Aug 08 07:43:43 PM PDT 24
Peak memory 217472 kb
Host smart-3ecb0825-f50a-43da-9722-b28afa2b9e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037446976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2037446976
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2413402381
Short name T36
Test name
Test status
Simulation time 20785449 ps
CPU time 1.06 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:53 PM PDT 24
Peak memory 215972 kb
Host smart-9847a327-3486-4b6d-8b8d-8416233bc598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413402381 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2413402381
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.275713832
Short name T365
Test name
Test status
Simulation time 33639261 ps
CPU time 0.91 seconds
Started Aug 08 07:43:47 PM PDT 24
Finished Aug 08 07:43:48 PM PDT 24
Peak memory 207072 kb
Host smart-a401e281-f625-40a9-879c-8bb60c56ce83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275713832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.275713832
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2882141670
Short name T740
Test name
Test status
Simulation time 315464074 ps
CPU time 3.52 seconds
Started Aug 08 07:43:43 PM PDT 24
Finished Aug 08 07:43:47 PM PDT 24
Peak memory 217248 kb
Host smart-9080a1b9-8136-4f2f-b670-2aa280e27c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882141670 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2882141670
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3084861830
Short name T438
Test name
Test status
Simulation time 36767876157 ps
CPU time 709.97 seconds
Started Aug 08 07:43:41 PM PDT 24
Finished Aug 08 07:55:31 PM PDT 24
Peak memory 217836 kb
Host smart-cf35a0aa-9a76-4593-b7c2-99a5907481dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084861830 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3084861830
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.706601572
Short name T386
Test name
Test status
Simulation time 28275964 ps
CPU time 1.17 seconds
Started Aug 08 07:45:35 PM PDT 24
Finished Aug 08 07:45:36 PM PDT 24
Peak memory 215820 kb
Host smart-f655c9f5-a4dd-4bbe-a533-4ef642632f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706601572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.706601572
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3819002258
Short name T564
Test name
Test status
Simulation time 57314012 ps
CPU time 1.44 seconds
Started Aug 08 07:45:41 PM PDT 24
Finished Aug 08 07:45:42 PM PDT 24
Peak memory 218576 kb
Host smart-d646a8cf-4375-40aa-adb5-985244025072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819002258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3819002258
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.579192478
Short name T669
Test name
Test status
Simulation time 39273219 ps
CPU time 1.4 seconds
Started Aug 08 07:45:35 PM PDT 24
Finished Aug 08 07:45:37 PM PDT 24
Peak memory 216988 kb
Host smart-299ceaec-ca54-439c-9750-2e4d9ee61fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579192478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.579192478
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2650500216
Short name T389
Test name
Test status
Simulation time 80396163 ps
CPU time 1.72 seconds
Started Aug 08 07:45:49 PM PDT 24
Finished Aug 08 07:45:51 PM PDT 24
Peak memory 219392 kb
Host smart-1de92887-6da7-42cb-a34c-554efb8a912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650500216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2650500216
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2649054114
Short name T346
Test name
Test status
Simulation time 113915724 ps
CPU time 1.73 seconds
Started Aug 08 07:45:44 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 218628 kb
Host smart-7585ed46-7f08-4f2f-a3b7-93fabe5ab9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649054114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2649054114
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2578638539
Short name T12
Test name
Test status
Simulation time 35743404 ps
CPU time 1.61 seconds
Started Aug 08 07:45:44 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 219976 kb
Host smart-86ff3069-a81e-471b-9044-3043b8e802e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578638539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2578638539
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1757007664
Short name T872
Test name
Test status
Simulation time 35778152 ps
CPU time 1.24 seconds
Started Aug 08 07:45:46 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 218440 kb
Host smart-8e2d0455-75c9-4131-93d5-547b2caacbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757007664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1757007664
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.480601166
Short name T607
Test name
Test status
Simulation time 40767298 ps
CPU time 1.39 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 218436 kb
Host smart-8d5e71b4-7069-4240-b8cc-3816ed35a76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480601166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.480601166
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3107567807
Short name T551
Test name
Test status
Simulation time 86370054 ps
CPU time 1.25 seconds
Started Aug 08 07:45:48 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 218656 kb
Host smart-d9b8f681-9685-42e5-93b7-a6a6f1e68786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107567807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3107567807
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2726193982
Short name T594
Test name
Test status
Simulation time 57614193 ps
CPU time 2.3 seconds
Started Aug 08 07:45:48 PM PDT 24
Finished Aug 08 07:45:51 PM PDT 24
Peak memory 218888 kb
Host smart-a624e29a-5f34-4e49-8fa1-ebb138d324a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726193982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2726193982
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.1870190426
Short name T810
Test name
Test status
Simulation time 58096936 ps
CPU time 0.89 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:53 PM PDT 24
Peak memory 215192 kb
Host smart-f2d43093-0e66-4a71-a243-3683ce8f6371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870190426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1870190426
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.920567728
Short name T816
Test name
Test status
Simulation time 99418101 ps
CPU time 1.08 seconds
Started Aug 08 07:43:54 PM PDT 24
Finished Aug 08 07:43:55 PM PDT 24
Peak memory 219660 kb
Host smart-0a9ba3d9-ecd3-426e-b9a2-f74f05bffd84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920567728 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.920567728
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1138127183
Short name T7
Test name
Test status
Simulation time 25505841 ps
CPU time 1.22 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:54 PM PDT 24
Peak memory 220168 kb
Host smart-c9950cea-bf80-4280-aa49-438f683ff8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138127183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1138127183
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.480073649
Short name T949
Test name
Test status
Simulation time 99279358 ps
CPU time 1.04 seconds
Started Aug 08 07:43:45 PM PDT 24
Finished Aug 08 07:43:47 PM PDT 24
Peak memory 217376 kb
Host smart-26faf245-cc74-463a-8852-97f665a5545e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480073649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.480073649
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.569749039
Short name T355
Test name
Test status
Simulation time 15364720 ps
CPU time 1.01 seconds
Started Aug 08 07:43:45 PM PDT 24
Finished Aug 08 07:43:46 PM PDT 24
Peak memory 215360 kb
Host smart-1b473243-666b-4a97-ab62-10f5f8bb4612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569749039 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.569749039
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2348750134
Short name T962
Test name
Test status
Simulation time 70631075 ps
CPU time 1.91 seconds
Started Aug 08 07:43:53 PM PDT 24
Finished Aug 08 07:43:55 PM PDT 24
Peak memory 217144 kb
Host smart-b18d2361-818b-4707-bf06-8a03eb7f3612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348750134 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2348750134
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.169693071
Short name T950
Test name
Test status
Simulation time 51029601344 ps
CPU time 1247.91 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 08:04:40 PM PDT 24
Peak memory 223636 kb
Host smart-420b60ce-e8ea-4d87-b9ec-6a6976d1961a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169693071 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.169693071
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2220401702
Short name T532
Test name
Test status
Simulation time 123117889 ps
CPU time 1.27 seconds
Started Aug 08 07:45:44 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 219040 kb
Host smart-8edbe53d-347c-4045-b73f-4537862569e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220401702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2220401702
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1805832045
Short name T306
Test name
Test status
Simulation time 106401963 ps
CPU time 1.14 seconds
Started Aug 08 07:45:53 PM PDT 24
Finished Aug 08 07:45:54 PM PDT 24
Peak memory 217512 kb
Host smart-42b2cd3a-1f3b-48ad-aa10-241a643c3187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805832045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1805832045
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.4259817800
Short name T39
Test name
Test status
Simulation time 35172669 ps
CPU time 1.62 seconds
Started Aug 08 07:45:44 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 218616 kb
Host smart-257e6017-509d-4013-b435-b68a76ab5aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259817800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.4259817800
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3418007959
Short name T613
Test name
Test status
Simulation time 131898814 ps
CPU time 1.8 seconds
Started Aug 08 07:45:46 PM PDT 24
Finished Aug 08 07:45:48 PM PDT 24
Peak memory 219156 kb
Host smart-13ca6a02-d34a-4c7d-bc25-4fa303732935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418007959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3418007959
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3645950103
Short name T883
Test name
Test status
Simulation time 109656963 ps
CPU time 1.45 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 218524 kb
Host smart-d2edde97-1061-4abb-bdda-aa2c54e2eae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645950103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3645950103
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2835909377
Short name T852
Test name
Test status
Simulation time 93038563 ps
CPU time 2.95 seconds
Started Aug 08 07:45:44 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 219008 kb
Host smart-232fc9b3-be7d-4251-8733-a4d745020eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835909377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2835909377
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1333134437
Short name T448
Test name
Test status
Simulation time 52706989 ps
CPU time 1.58 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 218576 kb
Host smart-f697f79e-fdb8-4de7-8252-4af49d3c62fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333134437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1333134437
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1653727751
Short name T385
Test name
Test status
Simulation time 130989921 ps
CPU time 1.27 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 219956 kb
Host smart-7a4eb288-5c65-4f51-b0ad-b776378bba54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653727751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1653727751
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3505583747
Short name T828
Test name
Test status
Simulation time 103607435 ps
CPU time 1.33 seconds
Started Aug 08 07:45:41 PM PDT 24
Finished Aug 08 07:45:42 PM PDT 24
Peak memory 218856 kb
Host smart-e0d4e4eb-f07d-49c4-92c9-5a0f0031e5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505583747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3505583747
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1428892907
Short name T464
Test name
Test status
Simulation time 45664641 ps
CPU time 1.63 seconds
Started Aug 08 07:45:43 PM PDT 24
Finished Aug 08 07:45:45 PM PDT 24
Peak memory 217800 kb
Host smart-76555e61-fe50-48b4-9747-0ee1359e5e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428892907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1428892907
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1097199474
Short name T320
Test name
Test status
Simulation time 25598926 ps
CPU time 1.23 seconds
Started Aug 08 07:43:55 PM PDT 24
Finished Aug 08 07:43:57 PM PDT 24
Peak memory 218764 kb
Host smart-f922558c-9568-4f89-b570-49bf7a6fa66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097199474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1097199474
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.731083628
Short name T578
Test name
Test status
Simulation time 22750493 ps
CPU time 0.89 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:53 PM PDT 24
Peak memory 215020 kb
Host smart-f55225bf-5711-43b8-a45d-61120ea10300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731083628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.731083628
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.981267218
Short name T188
Test name
Test status
Simulation time 15791456 ps
CPU time 0.81 seconds
Started Aug 08 07:43:51 PM PDT 24
Finished Aug 08 07:43:52 PM PDT 24
Peak memory 216508 kb
Host smart-0555f04e-d90a-4961-bd83-93d30e8424dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981267218 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.981267218
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.3562686680
Short name T670
Test name
Test status
Simulation time 24669040 ps
CPU time 1.18 seconds
Started Aug 08 07:43:53 PM PDT 24
Finished Aug 08 07:43:55 PM PDT 24
Peak memory 218692 kb
Host smart-47efb969-e95a-4cd9-873a-b885182f63f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562686680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3562686680
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3701950840
Short name T812
Test name
Test status
Simulation time 67656792 ps
CPU time 1.43 seconds
Started Aug 08 07:44:05 PM PDT 24
Finished Aug 08 07:44:07 PM PDT 24
Peak memory 218928 kb
Host smart-c171e5cf-af2f-4392-b490-6e4d81fe5454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701950840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3701950840
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3821167696
Short name T376
Test name
Test status
Simulation time 61511034 ps
CPU time 0.82 seconds
Started Aug 08 07:43:53 PM PDT 24
Finished Aug 08 07:43:54 PM PDT 24
Peak memory 215296 kb
Host smart-e88453f3-4584-4d0a-885d-bf56e254b2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821167696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3821167696
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2511051941
Short name T942
Test name
Test status
Simulation time 42450175 ps
CPU time 0.92 seconds
Started Aug 08 07:44:10 PM PDT 24
Finished Aug 08 07:44:12 PM PDT 24
Peak memory 215332 kb
Host smart-aef08cfc-cc85-41ee-a639-65222bcddaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511051941 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2511051941
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2647781433
Short name T5
Test name
Test status
Simulation time 594803305 ps
CPU time 6.36 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:59 PM PDT 24
Peak memory 217296 kb
Host smart-758fb42f-28c4-45a7-8bcb-ea5de26e4875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647781433 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2647781433
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3656013412
Short name T240
Test name
Test status
Simulation time 257543913529 ps
CPU time 2886.42 seconds
Started Aug 08 07:43:53 PM PDT 24
Finished Aug 08 08:32:00 PM PDT 24
Peak memory 230028 kb
Host smart-e1e3ac44-e603-44b8-881a-5a10c3f3e51d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656013412 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3656013412
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1227792693
Short name T632
Test name
Test status
Simulation time 290258955 ps
CPU time 1.91 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 218676 kb
Host smart-3118cb1b-fffb-4879-8fb3-79cc40e728c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227792693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1227792693
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1446124585
Short name T974
Test name
Test status
Simulation time 90824437 ps
CPU time 3.22 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:48 PM PDT 24
Peak memory 218688 kb
Host smart-eda4250e-5419-485a-9f1a-53d341f86ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446124585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1446124585
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3145507403
Short name T45
Test name
Test status
Simulation time 79544177 ps
CPU time 1.74 seconds
Started Aug 08 07:45:44 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 218784 kb
Host smart-df53f56f-7cf4-4f6c-a99c-d17568e4927e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145507403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3145507403
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3265353554
Short name T457
Test name
Test status
Simulation time 95117215 ps
CPU time 1.45 seconds
Started Aug 08 07:45:44 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 218540 kb
Host smart-66635f25-258c-4711-8b2f-554987de34c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265353554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3265353554
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.224590859
Short name T543
Test name
Test status
Simulation time 62691064 ps
CPU time 1.3 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 215316 kb
Host smart-d8b9fb67-8377-47ab-993a-d1e5406b72fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224590859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.224590859
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3537141880
Short name T591
Test name
Test status
Simulation time 58617847 ps
CPU time 1.32 seconds
Started Aug 08 07:45:46 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 219864 kb
Host smart-9bc0020b-0802-4e31-bd3a-a0a8153f94e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537141880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3537141880
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1664631802
Short name T348
Test name
Test status
Simulation time 41587859 ps
CPU time 1.15 seconds
Started Aug 08 07:45:48 PM PDT 24
Finished Aug 08 07:45:50 PM PDT 24
Peak memory 217240 kb
Host smart-753e339c-89bf-45c9-a05b-2cb62c23b871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664631802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1664631802
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.253420464
Short name T981
Test name
Test status
Simulation time 34996436 ps
CPU time 1.06 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 217712 kb
Host smart-cc5945f3-579f-4643-b32b-a064b9f4e5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253420464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.253420464
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.781018950
Short name T869
Test name
Test status
Simulation time 36887086 ps
CPU time 1.46 seconds
Started Aug 08 07:45:46 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 218440 kb
Host smart-6b92cf58-d698-4469-a9eb-65e0d4b5929a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781018950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.781018950
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.148837291
Short name T10
Test name
Test status
Simulation time 29754940 ps
CPU time 1.29 seconds
Started Aug 08 07:44:03 PM PDT 24
Finished Aug 08 07:44:05 PM PDT 24
Peak memory 219288 kb
Host smart-40bc6020-5a3c-4dfd-a96a-4ba513670ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148837291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.148837291
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3331032919
Short name T576
Test name
Test status
Simulation time 18759635 ps
CPU time 0.99 seconds
Started Aug 08 07:43:59 PM PDT 24
Finished Aug 08 07:44:00 PM PDT 24
Peak memory 215252 kb
Host smart-a033fe93-b1c8-4419-bafa-3984a135f0bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331032919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3331032919
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.53046359
Short name T189
Test name
Test status
Simulation time 13154049 ps
CPU time 0.9 seconds
Started Aug 08 07:43:51 PM PDT 24
Finished Aug 08 07:43:52 PM PDT 24
Peak memory 216660 kb
Host smart-246e7a1c-ac13-487b-8276-946fe77eab03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53046359 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.53046359
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.880665748
Short name T128
Test name
Test status
Simulation time 78447181 ps
CPU time 1.03 seconds
Started Aug 08 07:43:57 PM PDT 24
Finished Aug 08 07:43:58 PM PDT 24
Peak memory 217392 kb
Host smart-65f59058-4992-48e8-be1e-79b91ba28669
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880665748 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.880665748
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.65366348
Short name T56
Test name
Test status
Simulation time 21114311 ps
CPU time 1.17 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:54 PM PDT 24
Peak memory 229736 kb
Host smart-5aa620f1-158b-4702-a98c-5da9649c228e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65366348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.65366348
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3216286045
Short name T512
Test name
Test status
Simulation time 33165384 ps
CPU time 1.37 seconds
Started Aug 08 07:44:06 PM PDT 24
Finished Aug 08 07:44:08 PM PDT 24
Peak memory 218760 kb
Host smart-50552c69-9aa9-49f4-a190-5434af10a95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216286045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3216286045
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2994936410
Short name T205
Test name
Test status
Simulation time 25828732 ps
CPU time 0.98 seconds
Started Aug 08 07:43:54 PM PDT 24
Finished Aug 08 07:43:55 PM PDT 24
Peak memory 213852 kb
Host smart-e2e18ed4-c5a9-47d5-b2ee-1fa18d393a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994936410 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2994936410
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2352919036
Short name T711
Test name
Test status
Simulation time 16156490 ps
CPU time 0.97 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:53 PM PDT 24
Peak memory 215264 kb
Host smart-ffa7b1e1-9e31-4fd3-b9aa-592f2e4de3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352919036 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2352919036
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.4226010899
Short name T416
Test name
Test status
Simulation time 66459700 ps
CPU time 1.29 seconds
Started Aug 08 07:43:50 PM PDT 24
Finished Aug 08 07:43:52 PM PDT 24
Peak memory 215296 kb
Host smart-0c73cb0e-07c1-46e6-a2a8-51e2b9a92916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226010899 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.4226010899
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.855658347
Short name T509
Test name
Test status
Simulation time 490393466252 ps
CPU time 1040.21 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 08:01:13 PM PDT 24
Peak memory 221716 kb
Host smart-95d2a5d4-0b25-42af-ab67-78526bcb730a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855658347 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.855658347
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.375463300
Short name T528
Test name
Test status
Simulation time 37843909 ps
CPU time 1.08 seconds
Started Aug 08 07:45:48 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 217320 kb
Host smart-38bfd539-6ac8-47ce-ad3c-b9fda0460345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375463300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.375463300
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1246794429
Short name T920
Test name
Test status
Simulation time 38187889 ps
CPU time 1.4 seconds
Started Aug 08 07:45:48 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 217364 kb
Host smart-f93a2d39-ea8a-4960-8eb5-ac98809a4c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246794429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1246794429
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.911744480
Short name T362
Test name
Test status
Simulation time 93531732 ps
CPU time 1.35 seconds
Started Aug 08 07:45:48 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 217476 kb
Host smart-4f0de838-a480-4886-a9c8-1e92598937fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911744480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.911744480
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.181129931
Short name T371
Test name
Test status
Simulation time 87974448 ps
CPU time 1.17 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:48 PM PDT 24
Peak memory 217632 kb
Host smart-738f672c-5153-497a-9965-95c5e8faaab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181129931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.181129931
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.107807848
Short name T471
Test name
Test status
Simulation time 70536231 ps
CPU time 1.47 seconds
Started Aug 08 07:45:46 PM PDT 24
Finished Aug 08 07:45:48 PM PDT 24
Peak memory 219976 kb
Host smart-a307a71d-d6b6-4a4a-b623-8a390029a31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107807848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.107807848
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1119901907
Short name T463
Test name
Test status
Simulation time 56926381 ps
CPU time 1.62 seconds
Started Aug 08 07:45:44 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 218548 kb
Host smart-e68997d4-34ce-484d-8c5b-e205abe9160e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119901907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1119901907
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.209083590
Short name T842
Test name
Test status
Simulation time 47528028 ps
CPU time 1.66 seconds
Started Aug 08 07:45:46 PM PDT 24
Finished Aug 08 07:45:48 PM PDT 24
Peak memory 220060 kb
Host smart-e9034c6b-767e-4957-87fd-bc0640fad125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209083590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.209083590
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2568360806
Short name T354
Test name
Test status
Simulation time 37543942 ps
CPU time 1.18 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 219660 kb
Host smart-ae424740-a315-485a-bb45-8bd26b48015c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568360806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2568360806
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.85267070
Short name T730
Test name
Test status
Simulation time 54142613 ps
CPU time 1.57 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 218584 kb
Host smart-3d6e888b-4e23-4cbf-a908-47418c252ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85267070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.85267070
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1852271065
Short name T584
Test name
Test status
Simulation time 235494876 ps
CPU time 3.75 seconds
Started Aug 08 07:45:46 PM PDT 24
Finished Aug 08 07:45:50 PM PDT 24
Peak memory 220224 kb
Host smart-5cee6ecc-9538-4356-9138-27d8f301459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852271065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1852271065
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3237297578
Short name T829
Test name
Test status
Simulation time 26892923 ps
CPU time 1.26 seconds
Started Aug 08 07:43:54 PM PDT 24
Finished Aug 08 07:43:56 PM PDT 24
Peak memory 218600 kb
Host smart-f21f96ba-5e10-45ac-a832-23a8ff6546d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237297578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3237297578
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1048141579
Short name T67
Test name
Test status
Simulation time 23098675 ps
CPU time 0.87 seconds
Started Aug 08 07:43:53 PM PDT 24
Finished Aug 08 07:43:54 PM PDT 24
Peak memory 206872 kb
Host smart-a596289e-82ca-4e1f-8e0a-066405321c72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048141579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1048141579
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1018937924
Short name T479
Test name
Test status
Simulation time 20920642 ps
CPU time 0.82 seconds
Started Aug 08 07:43:54 PM PDT 24
Finished Aug 08 07:43:55 PM PDT 24
Peak memory 216276 kb
Host smart-ab8ea9b5-2dca-4bfe-b407-542a3e39cf19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018937924 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1018937924
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.3663787057
Short name T179
Test name
Test status
Simulation time 30233556 ps
CPU time 1.25 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:53 PM PDT 24
Peak memory 219868 kb
Host smart-665571c6-5b1c-4c1d-b769-206f0c02ae64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663787057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3663787057
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3779136817
Short name T343
Test name
Test status
Simulation time 110744426 ps
CPU time 1.31 seconds
Started Aug 08 07:43:51 PM PDT 24
Finished Aug 08 07:43:53 PM PDT 24
Peak memory 218752 kb
Host smart-ca40450c-76cc-459c-9bf9-2efcd9f04a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779136817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3779136817
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3920417690
Short name T709
Test name
Test status
Simulation time 28486311 ps
CPU time 0.97 seconds
Started Aug 08 07:44:04 PM PDT 24
Finished Aug 08 07:44:05 PM PDT 24
Peak memory 215496 kb
Host smart-e46a3c73-4432-4106-803f-ecf1939ebd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920417690 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3920417690
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.333042205
Short name T458
Test name
Test status
Simulation time 50997043 ps
CPU time 0.88 seconds
Started Aug 08 07:43:53 PM PDT 24
Finished Aug 08 07:43:54 PM PDT 24
Peak memory 215344 kb
Host smart-4d7d6d27-5f9f-438e-875a-8405a156d71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333042205 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.333042205
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1227269080
Short name T104
Test name
Test status
Simulation time 92430892 ps
CPU time 1.64 seconds
Started Aug 08 07:44:11 PM PDT 24
Finished Aug 08 07:44:12 PM PDT 24
Peak memory 217244 kb
Host smart-1db546e8-b3fe-4f04-a2cf-d770d03aa232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227269080 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1227269080
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2650636912
Short name T534
Test name
Test status
Simulation time 167267220204 ps
CPU time 773.48 seconds
Started Aug 08 07:44:09 PM PDT 24
Finished Aug 08 07:57:03 PM PDT 24
Peak memory 222380 kb
Host smart-079e80a3-77ff-4402-b574-98ac5cef3700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650636912 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2650636912
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/261.edn_genbits.3328814484
Short name T337
Test name
Test status
Simulation time 56516162 ps
CPU time 1.44 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 218768 kb
Host smart-86050438-c13a-4d1b-8641-201cc0b37aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328814484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3328814484
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3736993955
Short name T773
Test name
Test status
Simulation time 43491702 ps
CPU time 1.88 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 218528 kb
Host smart-b56f4ba5-9493-4ceb-8a8b-da5385d6a32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736993955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3736993955
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2153492639
Short name T548
Test name
Test status
Simulation time 197447835 ps
CPU time 0.94 seconds
Started Aug 08 07:45:51 PM PDT 24
Finished Aug 08 07:45:52 PM PDT 24
Peak memory 217188 kb
Host smart-4cad6123-bde4-4da3-b741-45ae3b142865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153492639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2153492639
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3603974484
Short name T752
Test name
Test status
Simulation time 326236180 ps
CPU time 1.1 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 217344 kb
Host smart-b186b723-d344-4c1d-9729-f191a9909f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603974484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3603974484
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.4203763418
Short name T985
Test name
Test status
Simulation time 111046880 ps
CPU time 1.57 seconds
Started Aug 08 07:45:46 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 218644 kb
Host smart-8cd15f00-4499-4e53-b1b1-c828f14fd230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203763418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.4203763418
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1801083784
Short name T654
Test name
Test status
Simulation time 45399944 ps
CPU time 1.37 seconds
Started Aug 08 07:45:51 PM PDT 24
Finished Aug 08 07:45:52 PM PDT 24
Peak memory 217104 kb
Host smart-8d00fe7e-e134-46ce-a108-f11433e839a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801083784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1801083784
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2212907070
Short name T396
Test name
Test status
Simulation time 69537858 ps
CPU time 1.4 seconds
Started Aug 08 07:45:51 PM PDT 24
Finished Aug 08 07:45:53 PM PDT 24
Peak memory 218816 kb
Host smart-24803cc9-07fd-4817-969d-82af24bfb8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212907070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2212907070
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2868485745
Short name T977
Test name
Test status
Simulation time 37291524 ps
CPU time 1.65 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 220036 kb
Host smart-f7c0f0e2-373b-4ff6-bbad-cce41ff5b48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868485745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2868485745
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.890069412
Short name T997
Test name
Test status
Simulation time 72375491 ps
CPU time 1.42 seconds
Started Aug 08 07:45:52 PM PDT 24
Finished Aug 08 07:45:53 PM PDT 24
Peak memory 219024 kb
Host smart-15c464a8-cef1-43df-8b81-f2e4d57d5cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890069412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.890069412
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.169568919
Short name T326
Test name
Test status
Simulation time 28647022 ps
CPU time 1.21 seconds
Started Aug 08 07:43:59 PM PDT 24
Finished Aug 08 07:44:00 PM PDT 24
Peak memory 220896 kb
Host smart-30dfcedb-4a33-45a7-99cb-c1898e1fd6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169568919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.169568919
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1198427285
Short name T408
Test name
Test status
Simulation time 20129879 ps
CPU time 1.03 seconds
Started Aug 08 07:43:53 PM PDT 24
Finished Aug 08 07:43:55 PM PDT 24
Peak memory 215184 kb
Host smart-e8f1ef43-e1b2-4c8c-ba48-b76d2bd3cff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198427285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1198427285
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3290584038
Short name T414
Test name
Test status
Simulation time 36760352 ps
CPU time 0.8 seconds
Started Aug 08 07:43:51 PM PDT 24
Finished Aug 08 07:43:52 PM PDT 24
Peak memory 216212 kb
Host smart-57bb4081-f3f4-4c52-a227-cdbcf0a90f55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290584038 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3290584038
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1691311432
Short name T149
Test name
Test status
Simulation time 100370557 ps
CPU time 1.1 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:53 PM PDT 24
Peak memory 218664 kb
Host smart-df835c2a-a5d6-4f99-a2e5-6ea69883bfc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691311432 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1691311432
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.208010367
Short name T597
Test name
Test status
Simulation time 24109250 ps
CPU time 1.11 seconds
Started Aug 08 07:43:53 PM PDT 24
Finished Aug 08 07:43:55 PM PDT 24
Peak memory 218628 kb
Host smart-076ebbf2-aa29-43b3-87ee-b20eef842f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208010367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.208010367
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.399953039
Short name T583
Test name
Test status
Simulation time 62304760 ps
CPU time 1.43 seconds
Started Aug 08 07:43:57 PM PDT 24
Finished Aug 08 07:43:58 PM PDT 24
Peak memory 218456 kb
Host smart-3bfc7c54-9e14-492a-86aa-4050741d855f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399953039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.399953039
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.829324139
Short name T502
Test name
Test status
Simulation time 21314565 ps
CPU time 1.13 seconds
Started Aug 08 07:43:51 PM PDT 24
Finished Aug 08 07:43:52 PM PDT 24
Peak memory 215356 kb
Host smart-f591afe6-64f2-41c8-8d80-92263d6af8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829324139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.829324139
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2222076390
Short name T935
Test name
Test status
Simulation time 179315946 ps
CPU time 0.91 seconds
Started Aug 08 07:43:53 PM PDT 24
Finished Aug 08 07:43:54 PM PDT 24
Peak memory 215300 kb
Host smart-29d55984-1b81-47ed-b9c8-8e1618014496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222076390 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2222076390
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2414808326
Short name T96
Test name
Test status
Simulation time 333912286 ps
CPU time 6.77 seconds
Started Aug 08 07:43:55 PM PDT 24
Finished Aug 08 07:44:02 PM PDT 24
Peak memory 215336 kb
Host smart-714a3e5e-f9d5-4da6-9dcd-a2a90c943238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414808326 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2414808326
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.737124987
Short name T674
Test name
Test status
Simulation time 89407092166 ps
CPU time 933.33 seconds
Started Aug 08 07:43:55 PM PDT 24
Finished Aug 08 07:59:28 PM PDT 24
Peak memory 223612 kb
Host smart-a38c114f-c8c4-450a-ba50-b1aeed97ed5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737124987 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.737124987
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1308857338
Short name T907
Test name
Test status
Simulation time 78033436 ps
CPU time 2.83 seconds
Started Aug 08 07:45:43 PM PDT 24
Finished Aug 08 07:45:46 PM PDT 24
Peak memory 217604 kb
Host smart-a4cf1b01-2dc0-4fad-8473-4393e625e34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308857338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1308857338
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.700193134
Short name T405
Test name
Test status
Simulation time 52769668 ps
CPU time 1.7 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:49 PM PDT 24
Peak memory 217608 kb
Host smart-4aca0e98-9cdf-44ef-9cdc-01cacbd749a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700193134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.700193134
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1820679030
Short name T257
Test name
Test status
Simulation time 844495291 ps
CPU time 6.76 seconds
Started Aug 08 07:45:51 PM PDT 24
Finished Aug 08 07:45:58 PM PDT 24
Peak memory 220232 kb
Host smart-2dc0966e-f517-437f-9132-0aa4012d7075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820679030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1820679030
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.571798664
Short name T629
Test name
Test status
Simulation time 90811773 ps
CPU time 1.2 seconds
Started Aug 08 07:45:46 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 218840 kb
Host smart-1b49418e-1091-4322-9f0c-9cdd14c5a732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571798664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.571798664
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.19169595
Short name T569
Test name
Test status
Simulation time 38131062 ps
CPU time 1.49 seconds
Started Aug 08 07:45:47 PM PDT 24
Finished Aug 08 07:45:48 PM PDT 24
Peak memory 218772 kb
Host smart-3b3ce516-9f8e-49b7-9247-c14b0d8f43b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19169595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.19169595
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2166868123
Short name T361
Test name
Test status
Simulation time 47535714 ps
CPU time 1.26 seconds
Started Aug 08 07:45:51 PM PDT 24
Finished Aug 08 07:45:53 PM PDT 24
Peak memory 218640 kb
Host smart-555b0f06-ff99-407a-875a-8b79ccf0621b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166868123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2166868123
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2892145727
Short name T878
Test name
Test status
Simulation time 32770500 ps
CPU time 1.52 seconds
Started Aug 08 07:45:45 PM PDT 24
Finished Aug 08 07:45:47 PM PDT 24
Peak memory 218644 kb
Host smart-d93c708a-e61b-4772-85d8-82572cab5060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892145727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2892145727
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3866074408
Short name T818
Test name
Test status
Simulation time 181360286 ps
CPU time 1.16 seconds
Started Aug 08 07:45:56 PM PDT 24
Finished Aug 08 07:45:57 PM PDT 24
Peak memory 217164 kb
Host smart-430c4df0-1b21-4a41-a130-5aa320f0eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866074408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3866074408
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1507559780
Short name T860
Test name
Test status
Simulation time 73217781 ps
CPU time 1 seconds
Started Aug 08 07:45:51 PM PDT 24
Finished Aug 08 07:45:52 PM PDT 24
Peak memory 217464 kb
Host smart-f77d3655-09e7-4f8b-96ef-24dce29c7595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507559780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1507559780
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2337416689
Short name T181
Test name
Test status
Simulation time 24242704 ps
CPU time 1.16 seconds
Started Aug 08 07:44:11 PM PDT 24
Finished Aug 08 07:44:12 PM PDT 24
Peak memory 218496 kb
Host smart-c62642de-76d5-47df-89b8-5420bf79bb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337416689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2337416689
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.536443454
Short name T447
Test name
Test status
Simulation time 13915543 ps
CPU time 0.95 seconds
Started Aug 08 07:43:54 PM PDT 24
Finished Aug 08 07:43:55 PM PDT 24
Peak memory 215108 kb
Host smart-cc6e21e2-e98b-4047-9233-bf1cf7ba5b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536443454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.536443454
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3690461977
Short name T290
Test name
Test status
Simulation time 19318371 ps
CPU time 0.91 seconds
Started Aug 08 07:43:55 PM PDT 24
Finished Aug 08 07:43:56 PM PDT 24
Peak memory 219224 kb
Host smart-63041c35-1552-4877-9271-81277f60cea2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690461977 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3690461977
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.4061257582
Short name T840
Test name
Test status
Simulation time 70122041 ps
CPU time 1.04 seconds
Started Aug 08 07:43:54 PM PDT 24
Finished Aug 08 07:43:55 PM PDT 24
Peak memory 218648 kb
Host smart-57a4710f-a7dc-4207-9714-8fb63b506e9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061257582 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.4061257582
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1438082794
Short name T930
Test name
Test status
Simulation time 29477744 ps
CPU time 0.98 seconds
Started Aug 08 07:43:55 PM PDT 24
Finished Aug 08 07:43:56 PM PDT 24
Peak memory 223972 kb
Host smart-daf5b603-1f53-46c8-b033-ccbc077b4352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438082794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1438082794
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.4237996943
Short name T73
Test name
Test status
Simulation time 417841479 ps
CPU time 4.64 seconds
Started Aug 08 07:44:00 PM PDT 24
Finished Aug 08 07:44:05 PM PDT 24
Peak memory 218100 kb
Host smart-d6729ba6-3eeb-4509-a408-263883cbb478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237996943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4237996943
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2228355759
Short name T538
Test name
Test status
Simulation time 57150017 ps
CPU time 0.85 seconds
Started Aug 08 07:43:52 PM PDT 24
Finished Aug 08 07:43:53 PM PDT 24
Peak memory 215256 kb
Host smart-2203450b-5a5c-4102-8122-9a3ad920e69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228355759 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2228355759
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2323716164
Short name T516
Test name
Test status
Simulation time 29105753 ps
CPU time 0.93 seconds
Started Aug 08 07:43:53 PM PDT 24
Finished Aug 08 07:43:54 PM PDT 24
Peak memory 215328 kb
Host smart-f5ff0308-6a6c-46de-95d8-ab306e4b2fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323716164 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2323716164
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3882296598
Short name T256
Test name
Test status
Simulation time 365012913 ps
CPU time 4.27 seconds
Started Aug 08 07:43:56 PM PDT 24
Finished Aug 08 07:44:01 PM PDT 24
Peak memory 215336 kb
Host smart-8e58a14c-aee2-446b-92ea-1198710adbaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882296598 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3882296598
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3864036987
Short name T230
Test name
Test status
Simulation time 140454007648 ps
CPU time 1845.78 seconds
Started Aug 08 07:43:59 PM PDT 24
Finished Aug 08 08:14:45 PM PDT 24
Peak memory 235700 kb
Host smart-a7f95b39-eda4-46dc-81c8-dc45176b6500
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864036987 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3864036987
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.432552205
Short name T606
Test name
Test status
Simulation time 66470500 ps
CPU time 1.59 seconds
Started Aug 08 07:45:59 PM PDT 24
Finished Aug 08 07:46:01 PM PDT 24
Peak memory 218676 kb
Host smart-13cb7503-d65e-4c1e-896d-0b0fe97c63a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432552205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.432552205
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1792229032
Short name T87
Test name
Test status
Simulation time 111167576 ps
CPU time 1.59 seconds
Started Aug 08 07:45:53 PM PDT 24
Finished Aug 08 07:45:55 PM PDT 24
Peak memory 218972 kb
Host smart-3c14c098-ea02-45b2-9eb2-c3bfd1063019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792229032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1792229032
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1326674671
Short name T636
Test name
Test status
Simulation time 31772954 ps
CPU time 1.38 seconds
Started Aug 08 07:45:57 PM PDT 24
Finished Aug 08 07:45:58 PM PDT 24
Peak memory 218620 kb
Host smart-ee3fc62b-02b5-48f0-a3d9-9a12d5957498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326674671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1326674671
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2771697148
Short name T704
Test name
Test status
Simulation time 60030220 ps
CPU time 1.26 seconds
Started Aug 08 07:45:52 PM PDT 24
Finished Aug 08 07:45:54 PM PDT 24
Peak memory 219960 kb
Host smart-c12f83ae-2a10-458d-a125-2ba6f944d783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771697148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2771697148
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2490822386
Short name T86
Test name
Test status
Simulation time 48060900 ps
CPU time 1.12 seconds
Started Aug 08 07:45:59 PM PDT 24
Finished Aug 08 07:46:00 PM PDT 24
Peak memory 217288 kb
Host smart-b441d0a7-4bbd-4c0d-a1ec-3e0be452db14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490822386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2490822386
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1313331003
Short name T837
Test name
Test status
Simulation time 71200026 ps
CPU time 1.17 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:05 PM PDT 24
Peak memory 217372 kb
Host smart-b77fb2b6-99a0-4979-94eb-8f2d968fca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313331003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1313331003
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2579951623
Short name T526
Test name
Test status
Simulation time 29610436 ps
CPU time 1.36 seconds
Started Aug 08 07:46:04 PM PDT 24
Finished Aug 08 07:46:06 PM PDT 24
Peak memory 217264 kb
Host smart-98b47914-9f84-4667-be18-b06342d5e46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579951623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2579951623
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1984206282
Short name T714
Test name
Test status
Simulation time 74056414 ps
CPU time 1.22 seconds
Started Aug 08 07:45:56 PM PDT 24
Finished Aug 08 07:45:57 PM PDT 24
Peak memory 218852 kb
Host smart-a9844213-9f31-476e-aa3e-b1346065e822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984206282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1984206282
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2329026254
Short name T746
Test name
Test status
Simulation time 100893136 ps
CPU time 1.41 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:05 PM PDT 24
Peak memory 217428 kb
Host smart-95972300-0ddb-4fc7-aa92-f10798d88366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329026254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2329026254
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1680330398
Short name T82
Test name
Test status
Simulation time 62235741 ps
CPU time 1.3 seconds
Started Aug 08 07:45:53 PM PDT 24
Finished Aug 08 07:45:54 PM PDT 24
Peak memory 217372 kb
Host smart-c6a583e7-3be3-43a1-9bee-bb6ff01646c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680330398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1680330398
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.750047680
Short name T529
Test name
Test status
Simulation time 30641646 ps
CPU time 1.23 seconds
Started Aug 08 07:43:58 PM PDT 24
Finished Aug 08 07:44:00 PM PDT 24
Peak memory 219596 kb
Host smart-6193d08a-11d9-4f40-bee2-b6b151d18916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750047680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.750047680
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3721779914
Short name T244
Test name
Test status
Simulation time 30670641 ps
CPU time 0.88 seconds
Started Aug 08 07:43:56 PM PDT 24
Finished Aug 08 07:43:57 PM PDT 24
Peak memory 206884 kb
Host smart-53479512-0189-40b9-80bc-635bea83f886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721779914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3721779914
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.44677678
Short name T777
Test name
Test status
Simulation time 19556681 ps
CPU time 0.86 seconds
Started Aug 08 07:43:59 PM PDT 24
Finished Aug 08 07:44:00 PM PDT 24
Peak memory 216268 kb
Host smart-095ab353-4c10-4a5c-b130-b212146b2402
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44677678 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.44677678
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1128310683
Short name T294
Test name
Test status
Simulation time 72365810 ps
CPU time 1.06 seconds
Started Aug 08 07:43:59 PM PDT 24
Finished Aug 08 07:44:00 PM PDT 24
Peak memory 218588 kb
Host smart-259a3c0a-16e6-4fc8-8b8c-73b251fb671d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128310683 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1128310683
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.993407446
Short name T394
Test name
Test status
Simulation time 29907524 ps
CPU time 0.85 seconds
Started Aug 08 07:43:58 PM PDT 24
Finished Aug 08 07:43:59 PM PDT 24
Peak memory 218396 kb
Host smart-74babccd-2aa5-4adb-8709-040d81bd5cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993407446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.993407446
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.777885097
Short name T508
Test name
Test status
Simulation time 48861669 ps
CPU time 1.89 seconds
Started Aug 08 07:43:59 PM PDT 24
Finished Aug 08 07:44:01 PM PDT 24
Peak memory 218728 kb
Host smart-89c078e7-fbc9-4b07-88b3-dcfa6568f3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777885097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.777885097
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.4076249127
Short name T98
Test name
Test status
Simulation time 26785941 ps
CPU time 0.95 seconds
Started Aug 08 07:43:56 PM PDT 24
Finished Aug 08 07:43:58 PM PDT 24
Peak memory 215980 kb
Host smart-8973edf8-d253-43e4-bd1b-127312f4cc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076249127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4076249127
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3539523785
Short name T568
Test name
Test status
Simulation time 19438581 ps
CPU time 0.93 seconds
Started Aug 08 07:44:04 PM PDT 24
Finished Aug 08 07:44:06 PM PDT 24
Peak memory 215312 kb
Host smart-ebe6ecd2-5ef1-4236-a4db-ee8cab73e646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539523785 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3539523785
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1722959513
Short name T525
Test name
Test status
Simulation time 675197216 ps
CPU time 4.04 seconds
Started Aug 08 07:44:00 PM PDT 24
Finished Aug 08 07:44:04 PM PDT 24
Peak memory 214908 kb
Host smart-ebe9ed3f-8e33-4176-a3f4-36d6bebdfa0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722959513 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1722959513
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.482705105
Short name T403
Test name
Test status
Simulation time 135159803151 ps
CPU time 3265.45 seconds
Started Aug 08 07:43:59 PM PDT 24
Finished Aug 08 08:38:25 PM PDT 24
Peak memory 232012 kb
Host smart-60d8bb3c-7dd0-4d6d-a1e9-082d00d75e45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482705105 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.482705105
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1881224963
Short name T602
Test name
Test status
Simulation time 129404423 ps
CPU time 3.06 seconds
Started Aug 08 07:45:56 PM PDT 24
Finished Aug 08 07:45:59 PM PDT 24
Peak memory 219364 kb
Host smart-8ce30e2e-1e5f-4f3c-9e13-78ebc662954d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881224963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1881224963
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.147999096
Short name T467
Test name
Test status
Simulation time 42167068 ps
CPU time 1.44 seconds
Started Aug 08 07:45:57 PM PDT 24
Finished Aug 08 07:45:58 PM PDT 24
Peak memory 217312 kb
Host smart-6c6997db-eff5-401d-abc4-76ee157306ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147999096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.147999096
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3781860109
Short name T894
Test name
Test status
Simulation time 75386225 ps
CPU time 1.32 seconds
Started Aug 08 07:46:02 PM PDT 24
Finished Aug 08 07:46:04 PM PDT 24
Peak memory 219096 kb
Host smart-9d723f4e-95ee-4841-a393-f2b2732dcc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781860109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3781860109
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.4268301777
Short name T255
Test name
Test status
Simulation time 48161111 ps
CPU time 1.65 seconds
Started Aug 08 07:46:03 PM PDT 24
Finished Aug 08 07:46:06 PM PDT 24
Peak memory 218632 kb
Host smart-add46a64-5d1e-4995-bb69-f9bc23346bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268301777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.4268301777
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3996248131
Short name T480
Test name
Test status
Simulation time 57877079 ps
CPU time 1.17 seconds
Started Aug 08 07:46:05 PM PDT 24
Finished Aug 08 07:46:06 PM PDT 24
Peak memory 217440 kb
Host smart-1cdd2f56-83fa-442f-a3dc-3a0ee401d1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996248131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3996248131
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.410509985
Short name T731
Test name
Test status
Simulation time 35230009 ps
CPU time 1.46 seconds
Started Aug 08 07:46:04 PM PDT 24
Finished Aug 08 07:46:06 PM PDT 24
Peak memory 217588 kb
Host smart-50ea2105-e3f5-4d58-9014-b5c2e02f5e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410509985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.410509985
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.548714609
Short name T336
Test name
Test status
Simulation time 49059534 ps
CPU time 1.32 seconds
Started Aug 08 07:45:57 PM PDT 24
Finished Aug 08 07:45:58 PM PDT 24
Peak memory 218928 kb
Host smart-131ee656-8ec1-4e94-bb7e-916227b8acb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548714609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.548714609
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2981647113
Short name T293
Test name
Test status
Simulation time 116218172 ps
CPU time 1.39 seconds
Started Aug 08 07:45:57 PM PDT 24
Finished Aug 08 07:45:59 PM PDT 24
Peak memory 220040 kb
Host smart-8a4617f6-8706-41c7-bc72-ca1dbb39985e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981647113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2981647113
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.583125568
Short name T373
Test name
Test status
Simulation time 91859042 ps
CPU time 1.54 seconds
Started Aug 08 07:45:59 PM PDT 24
Finished Aug 08 07:46:01 PM PDT 24
Peak memory 218636 kb
Host smart-41d0dd52-74d8-4a76-a19f-413d771abe33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583125568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.583125568
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2732730975
Short name T462
Test name
Test status
Simulation time 106491611 ps
CPU time 1.16 seconds
Started Aug 08 07:43:15 PM PDT 24
Finished Aug 08 07:43:16 PM PDT 24
Peak memory 218500 kb
Host smart-b2b6ce20-2173-4598-843f-2fce93e0d4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732730975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2732730975
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3087916948
Short name T417
Test name
Test status
Simulation time 44400167 ps
CPU time 1.39 seconds
Started Aug 08 07:43:15 PM PDT 24
Finished Aug 08 07:43:16 PM PDT 24
Peak memory 207056 kb
Host smart-6d6350c2-5778-4b77-b3a0-b823be301b34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087916948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3087916948
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2894884502
Short name T429
Test name
Test status
Simulation time 11182324 ps
CPU time 0.85 seconds
Started Aug 08 07:43:10 PM PDT 24
Finished Aug 08 07:43:11 PM PDT 24
Peak memory 215368 kb
Host smart-25bb7860-3a65-4c4e-aafb-7962c18356dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894884502 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2894884502
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.843529376
Short name T952
Test name
Test status
Simulation time 83271309 ps
CPU time 0.98 seconds
Started Aug 08 07:43:10 PM PDT 24
Finished Aug 08 07:43:12 PM PDT 24
Peak memory 219728 kb
Host smart-5dc283ab-2c4f-4682-b3e3-20341fc688c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843529376 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.843529376
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.761494864
Short name T854
Test name
Test status
Simulation time 19508854 ps
CPU time 1.16 seconds
Started Aug 08 07:43:11 PM PDT 24
Finished Aug 08 07:43:12 PM PDT 24
Peak memory 224172 kb
Host smart-ca000da0-1dd8-40da-b563-28cf98d514ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761494864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.761494864
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.435114222
Short name T627
Test name
Test status
Simulation time 102422921 ps
CPU time 1.61 seconds
Started Aug 08 07:43:15 PM PDT 24
Finished Aug 08 07:43:17 PM PDT 24
Peak memory 219048 kb
Host smart-caf418e7-5672-4b29-8c33-2a228185fa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435114222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.435114222
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3717508694
Short name T686
Test name
Test status
Simulation time 20886197 ps
CPU time 1.09 seconds
Started Aug 08 07:43:10 PM PDT 24
Finished Aug 08 07:43:11 PM PDT 24
Peak memory 215488 kb
Host smart-394bb1dc-2663-4e20-8d59-8ddd29caaf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717508694 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3717508694
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2190862717
Short name T28
Test name
Test status
Simulation time 18741552 ps
CPU time 0.97 seconds
Started Aug 08 07:43:11 PM PDT 24
Finished Aug 08 07:43:13 PM PDT 24
Peak memory 207120 kb
Host smart-a8993f1e-8cbb-4de1-b14f-76aeb103af55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190862717 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2190862717
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1130030617
Short name T18
Test name
Test status
Simulation time 4807174792 ps
CPU time 6.78 seconds
Started Aug 08 07:43:15 PM PDT 24
Finished Aug 08 07:43:21 PM PDT 24
Peak memory 243244 kb
Host smart-ab5e8083-ba01-4cf6-9974-4c5fd786efd1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130030617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1130030617
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2740900025
Short name T363
Test name
Test status
Simulation time 15695986 ps
CPU time 1 seconds
Started Aug 08 07:43:15 PM PDT 24
Finished Aug 08 07:43:16 PM PDT 24
Peak memory 215328 kb
Host smart-93c06366-1e0a-4904-8fc0-223d3c7d80ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740900025 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2740900025
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3001291988
Short name T249
Test name
Test status
Simulation time 850795185 ps
CPU time 5.05 seconds
Started Aug 08 07:43:13 PM PDT 24
Finished Aug 08 07:43:18 PM PDT 24
Peak memory 215336 kb
Host smart-44f277af-4635-42a2-a48a-7ddb8b1702f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001291988 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3001291988
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.4293131666
Short name T980
Test name
Test status
Simulation time 132571750590 ps
CPU time 904.41 seconds
Started Aug 08 07:43:12 PM PDT 24
Finished Aug 08 07:58:17 PM PDT 24
Peak memory 222224 kb
Host smart-c09c77dd-64dd-4a9c-9783-af11b2dfa9e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293131666 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.4293131666
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert_test.393800100
Short name T465
Test name
Test status
Simulation time 27391696 ps
CPU time 0.92 seconds
Started Aug 08 07:44:02 PM PDT 24
Finished Aug 08 07:44:03 PM PDT 24
Peak memory 215212 kb
Host smart-6710e6cc-5dee-4fe5-ba34-df4a4cdedb83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393800100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.393800100
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1312599531
Short name T92
Test name
Test status
Simulation time 42182287 ps
CPU time 0.9 seconds
Started Aug 08 07:44:01 PM PDT 24
Finished Aug 08 07:44:02 PM PDT 24
Peak memory 215408 kb
Host smart-7b291fdf-4b1d-4e7b-9771-311ccd9cdf21
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312599531 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1312599531
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.302929871
Short name T855
Test name
Test status
Simulation time 57822683 ps
CPU time 1.11 seconds
Started Aug 08 07:44:02 PM PDT 24
Finished Aug 08 07:44:03 PM PDT 24
Peak memory 218288 kb
Host smart-f128d4e7-0b6d-4ef9-a508-da401184aba3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302929871 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.302929871
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.4149705196
Short name T155
Test name
Test status
Simulation time 25549036 ps
CPU time 1.11 seconds
Started Aug 08 07:44:03 PM PDT 24
Finished Aug 08 07:44:04 PM PDT 24
Peak memory 219868 kb
Host smart-2bc4ac31-601c-41f5-8e74-7b9ceb7db04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149705196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.4149705196
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3742021312
Short name T792
Test name
Test status
Simulation time 71911401 ps
CPU time 1.85 seconds
Started Aug 08 07:43:55 PM PDT 24
Finished Aug 08 07:43:57 PM PDT 24
Peak memory 218900 kb
Host smart-72721f4e-1d19-4194-a648-023fadd0aa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742021312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3742021312
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2052115501
Short name T99
Test name
Test status
Simulation time 27290897 ps
CPU time 0.88 seconds
Started Aug 08 07:44:00 PM PDT 24
Finished Aug 08 07:44:01 PM PDT 24
Peak memory 215948 kb
Host smart-ed17e862-7a24-40ff-9b8f-0465a8de45e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052115501 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2052115501
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.243812995
Short name T524
Test name
Test status
Simulation time 16489735 ps
CPU time 1.07 seconds
Started Aug 08 07:43:57 PM PDT 24
Finished Aug 08 07:43:58 PM PDT 24
Peak memory 215320 kb
Host smart-290dd58c-fd39-4007-bdb7-b9f113d4b794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243812995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.243812995
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3701955695
Short name T366
Test name
Test status
Simulation time 295762356 ps
CPU time 5.82 seconds
Started Aug 08 07:43:54 PM PDT 24
Finished Aug 08 07:44:00 PM PDT 24
Peak memory 220424 kb
Host smart-12a7022c-eb8d-4cfd-83db-e58b9a7efa5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701955695 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3701955695
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2704564243
Short name T881
Test name
Test status
Simulation time 42941721871 ps
CPU time 1037.89 seconds
Started Aug 08 07:43:57 PM PDT 24
Finished Aug 08 08:01:15 PM PDT 24
Peak memory 220084 kb
Host smart-54c0c382-a8c5-4329-b48f-c9687d222647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704564243 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2704564243
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert_test.244416923
Short name T691
Test name
Test status
Simulation time 38972721 ps
CPU time 0.88 seconds
Started Aug 08 07:44:03 PM PDT 24
Finished Aug 08 07:44:04 PM PDT 24
Peak memory 215224 kb
Host smart-0e497b6a-341b-470e-acdc-6b038e9ce762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244416923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.244416923
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2548883082
Short name T214
Test name
Test status
Simulation time 11698119 ps
CPU time 0.91 seconds
Started Aug 08 07:44:00 PM PDT 24
Finished Aug 08 07:44:01 PM PDT 24
Peak memory 216536 kb
Host smart-5505c8df-c957-42d9-8ee0-2d9fd2d669f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548883082 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2548883082
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.3257057670
Short name T196
Test name
Test status
Simulation time 24250605 ps
CPU time 1 seconds
Started Aug 08 07:44:01 PM PDT 24
Finished Aug 08 07:44:02 PM PDT 24
Peak memory 218612 kb
Host smart-01cfe303-c0b1-4b26-ba49-66576353d808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257057670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3257057670
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1898884297
Short name T913
Test name
Test status
Simulation time 51436488 ps
CPU time 1.17 seconds
Started Aug 08 07:44:03 PM PDT 24
Finished Aug 08 07:44:04 PM PDT 24
Peak memory 218776 kb
Host smart-8f8dbeca-c98f-4f75-9b61-4bd8bfe5265a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898884297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1898884297
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3155897309
Short name T616
Test name
Test status
Simulation time 35450912 ps
CPU time 1.01 seconds
Started Aug 08 07:44:02 PM PDT 24
Finished Aug 08 07:44:03 PM PDT 24
Peak memory 223936 kb
Host smart-1ac592f2-a46e-4c09-a15b-be3f12f64022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155897309 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3155897309
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.135677573
Short name T786
Test name
Test status
Simulation time 131986387 ps
CPU time 0.92 seconds
Started Aug 08 07:44:02 PM PDT 24
Finished Aug 08 07:44:03 PM PDT 24
Peak memory 215288 kb
Host smart-aefbffcd-8930-4112-9f36-ac5b43beb0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135677573 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.135677573
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4194250840
Short name T750
Test name
Test status
Simulation time 308187340 ps
CPU time 3.7 seconds
Started Aug 08 07:44:02 PM PDT 24
Finished Aug 08 07:44:05 PM PDT 24
Peak memory 217352 kb
Host smart-0adc3294-63de-4807-ba51-f0e4447965d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194250840 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4194250840
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.4047949518
Short name T490
Test name
Test status
Simulation time 114270628893 ps
CPU time 2937.57 seconds
Started Aug 08 07:44:01 PM PDT 24
Finished Aug 08 08:32:59 PM PDT 24
Peak memory 233652 kb
Host smart-f6b0f25f-fac5-48d9-a794-284f7a62f573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047949518 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.4047949518
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1992045480
Short name T572
Test name
Test status
Simulation time 36964246 ps
CPU time 1.18 seconds
Started Aug 08 07:44:02 PM PDT 24
Finished Aug 08 07:44:04 PM PDT 24
Peak memory 220080 kb
Host smart-9ad907f5-713d-49ff-ae23-e353258c6283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992045480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1992045480
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.569032854
Short name T908
Test name
Test status
Simulation time 14209474 ps
CPU time 0.92 seconds
Started Aug 08 07:44:00 PM PDT 24
Finished Aug 08 07:44:01 PM PDT 24
Peak memory 206812 kb
Host smart-e0a58ed3-96b2-41ed-aeea-087353b55432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569032854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.569032854
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2203304666
Short name T866
Test name
Test status
Simulation time 19179741 ps
CPU time 0.87 seconds
Started Aug 08 07:44:03 PM PDT 24
Finished Aug 08 07:44:04 PM PDT 24
Peak memory 216352 kb
Host smart-644ee911-0042-4388-a3e6-d2de3d2876bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203304666 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2203304666
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.30632569
Short name T158
Test name
Test status
Simulation time 31912569 ps
CPU time 1.08 seconds
Started Aug 08 07:44:02 PM PDT 24
Finished Aug 08 07:44:03 PM PDT 24
Peak memory 219424 kb
Host smart-59fa693c-eae0-43cf-860a-9644150fe8a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30632569 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_dis
able_auto_req_mode.30632569
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2542039494
Short name T788
Test name
Test status
Simulation time 61068719 ps
CPU time 1.04 seconds
Started Aug 08 07:44:06 PM PDT 24
Finished Aug 08 07:44:07 PM PDT 24
Peak memory 218844 kb
Host smart-e25198dc-4513-48c1-91f8-926e74c422dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542039494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2542039494
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1646913773
Short name T328
Test name
Test status
Simulation time 42606035 ps
CPU time 1.06 seconds
Started Aug 08 07:44:03 PM PDT 24
Finished Aug 08 07:44:04 PM PDT 24
Peak memory 217520 kb
Host smart-785bc328-0f32-4299-b3a8-19944f487e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646913773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1646913773
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2785149591
Short name T902
Test name
Test status
Simulation time 40713680 ps
CPU time 1.04 seconds
Started Aug 08 07:44:04 PM PDT 24
Finished Aug 08 07:44:05 PM PDT 24
Peak memory 224320 kb
Host smart-cb203498-e53e-4fdf-a038-8eed1fd890f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785149591 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2785149591
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3410692337
Short name T435
Test name
Test status
Simulation time 29390541 ps
CPU time 0.86 seconds
Started Aug 08 07:44:02 PM PDT 24
Finished Aug 08 07:44:03 PM PDT 24
Peak memory 207132 kb
Host smart-c47aab72-16bd-4078-92a8-50e4c575b498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410692337 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3410692337
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.841261175
Short name T580
Test name
Test status
Simulation time 572889589 ps
CPU time 3.48 seconds
Started Aug 08 07:44:03 PM PDT 24
Finished Aug 08 07:44:06 PM PDT 24
Peak memory 217340 kb
Host smart-8b761b69-7945-4102-9faa-a463fc98732b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841261175 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.841261175
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3765144058
Short name T428
Test name
Test status
Simulation time 66044938235 ps
CPU time 1725.93 seconds
Started Aug 08 07:44:00 PM PDT 24
Finished Aug 08 08:12:46 PM PDT 24
Peak memory 225220 kb
Host smart-047117c7-a1a6-4ba0-b31c-2a4d20c7ea16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765144058 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3765144058
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3117743923
Short name T184
Test name
Test status
Simulation time 40234740 ps
CPU time 1.15 seconds
Started Aug 08 07:44:03 PM PDT 24
Finished Aug 08 07:44:05 PM PDT 24
Peak memory 220620 kb
Host smart-4cd0164b-b368-424e-b2b3-58ae48bb2827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117743923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3117743923
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2565971027
Short name T665
Test name
Test status
Simulation time 61775936 ps
CPU time 0.93 seconds
Started Aug 08 07:44:13 PM PDT 24
Finished Aug 08 07:44:14 PM PDT 24
Peak memory 215244 kb
Host smart-c5b065e2-4d44-4b86-9163-66884bbf9ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565971027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2565971027
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3758889320
Short name T943
Test name
Test status
Simulation time 45449516 ps
CPU time 0.85 seconds
Started Aug 08 07:44:10 PM PDT 24
Finished Aug 08 07:44:11 PM PDT 24
Peak memory 216520 kb
Host smart-beda26cf-ab2e-41f1-9e98-dac861ff1d08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758889320 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3758889320
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3332060658
Short name T159
Test name
Test status
Simulation time 71254929 ps
CPU time 1.03 seconds
Started Aug 08 07:44:11 PM PDT 24
Finished Aug 08 07:44:12 PM PDT 24
Peak memory 219388 kb
Host smart-615785c1-9fae-46cb-be41-231214e56e50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332060658 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3332060658
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1255777382
Short name T142
Test name
Test status
Simulation time 44621682 ps
CPU time 1.03 seconds
Started Aug 08 07:44:08 PM PDT 24
Finished Aug 08 07:44:09 PM PDT 24
Peak memory 220060 kb
Host smart-16334176-4832-4b95-a8dc-45b032845c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255777382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1255777382
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1221217840
Short name T771
Test name
Test status
Simulation time 61845095 ps
CPU time 1.84 seconds
Started Aug 08 07:44:02 PM PDT 24
Finished Aug 08 07:44:04 PM PDT 24
Peak memory 218928 kb
Host smart-2e5acd97-b8de-4149-8280-a4cce569d884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221217840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1221217840
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3595832599
Short name T944
Test name
Test status
Simulation time 25029892 ps
CPU time 0.93 seconds
Started Aug 08 07:44:02 PM PDT 24
Finished Aug 08 07:44:03 PM PDT 24
Peak memory 215492 kb
Host smart-d8804095-1039-41de-a870-1b29eabba42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595832599 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3595832599
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1557465029
Short name T662
Test name
Test status
Simulation time 28347802 ps
CPU time 0.93 seconds
Started Aug 08 07:44:03 PM PDT 24
Finished Aug 08 07:44:04 PM PDT 24
Peak memory 215308 kb
Host smart-819cfd1e-3c8e-44fc-969e-1f73e2f95b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557465029 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1557465029
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3910092498
Short name T493
Test name
Test status
Simulation time 530645741 ps
CPU time 5.41 seconds
Started Aug 08 07:44:03 PM PDT 24
Finished Aug 08 07:44:09 PM PDT 24
Peak memory 215316 kb
Host smart-c3708f35-6185-4739-8d51-e40c02cc5268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910092498 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3910092498
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2362992473
Short name T38
Test name
Test status
Simulation time 54262064978 ps
CPU time 1401.71 seconds
Started Aug 08 07:44:06 PM PDT 24
Finished Aug 08 08:07:28 PM PDT 24
Peak memory 222796 kb
Host smart-65eaa199-01bc-4a83-9c0c-45c8c0ebf79d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362992473 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2362992473
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.510133095
Short name T989
Test name
Test status
Simulation time 26680002 ps
CPU time 1.16 seconds
Started Aug 08 07:44:13 PM PDT 24
Finished Aug 08 07:44:15 PM PDT 24
Peak memory 218868 kb
Host smart-a798e2a2-64a1-4678-89f7-1369dbf3c912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510133095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.510133095
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3902197078
Short name T793
Test name
Test status
Simulation time 189096596 ps
CPU time 0.97 seconds
Started Aug 08 07:44:11 PM PDT 24
Finished Aug 08 07:44:12 PM PDT 24
Peak memory 206864 kb
Host smart-d4a254ef-09f4-439c-b665-accca5c6b8ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902197078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3902197078
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1839135645
Short name T612
Test name
Test status
Simulation time 56221945 ps
CPU time 0.85 seconds
Started Aug 08 07:44:10 PM PDT 24
Finished Aug 08 07:44:11 PM PDT 24
Peak memory 216496 kb
Host smart-50535e84-8517-4959-a986-b8bd7020afd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839135645 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1839135645
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2670156470
Short name T163
Test name
Test status
Simulation time 34756058 ps
CPU time 1.27 seconds
Started Aug 08 07:44:18 PM PDT 24
Finished Aug 08 07:44:19 PM PDT 24
Peak memory 217056 kb
Host smart-0ee80780-5aac-427b-97bb-a6868717b6aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670156470 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2670156470
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3345639924
Short name T577
Test name
Test status
Simulation time 23344603 ps
CPU time 0.99 seconds
Started Aug 08 07:44:13 PM PDT 24
Finished Aug 08 07:44:14 PM PDT 24
Peak memory 218748 kb
Host smart-bc1e96a1-ff11-455e-98fc-839f35541849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345639924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3345639924
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3828189330
Short name T518
Test name
Test status
Simulation time 259854305 ps
CPU time 1.15 seconds
Started Aug 08 07:44:14 PM PDT 24
Finished Aug 08 07:44:15 PM PDT 24
Peak memory 217408 kb
Host smart-f375462c-a6d4-4914-99e1-7f2f852ba4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828189330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3828189330
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.630505615
Short name T523
Test name
Test status
Simulation time 21264091 ps
CPU time 1.14 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 215560 kb
Host smart-f1155334-dea5-42fa-8952-7a43ffddbe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630505615 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.630505615
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3126494486
Short name T377
Test name
Test status
Simulation time 186753208 ps
CPU time 0.87 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 215128 kb
Host smart-0cd38d58-f8b6-4556-aeda-8bedbe938f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126494486 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3126494486
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1927209831
Short name T961
Test name
Test status
Simulation time 701725910 ps
CPU time 4.6 seconds
Started Aug 08 07:44:11 PM PDT 24
Finished Aug 08 07:44:16 PM PDT 24
Peak memory 218576 kb
Host smart-6eb8ce52-94f2-4723-be17-dd91a124bccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927209831 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1927209831
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.4174753101
Short name T918
Test name
Test status
Simulation time 21008289316 ps
CPU time 229.57 seconds
Started Aug 08 07:44:13 PM PDT 24
Finished Aug 08 07:48:03 PM PDT 24
Peak memory 217636 kb
Host smart-bbbaad2f-e8cb-4655-b95c-c54161b14fac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174753101 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.4174753101
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2743165467
Short name T15
Test name
Test status
Simulation time 29423230 ps
CPU time 1.19 seconds
Started Aug 08 07:44:11 PM PDT 24
Finished Aug 08 07:44:12 PM PDT 24
Peak memory 220748 kb
Host smart-e7ea6a40-98ae-4c2c-81e1-864607817ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743165467 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2743165467
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3233825109
Short name T650
Test name
Test status
Simulation time 51210704 ps
CPU time 0.88 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 206852 kb
Host smart-eff17f4e-ac77-4ef2-8e74-cd426bb33f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233825109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3233825109
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.971824935
Short name T198
Test name
Test status
Simulation time 31740585 ps
CPU time 0.89 seconds
Started Aug 08 07:44:11 PM PDT 24
Finished Aug 08 07:44:12 PM PDT 24
Peak memory 216532 kb
Host smart-444c5153-adc8-4d6f-956d-fba8ca0e7610
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971824935 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.971824935
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2425686081
Short name T728
Test name
Test status
Simulation time 51865375 ps
CPU time 1.05 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 219564 kb
Host smart-6086df70-096d-4e9d-9962-87ca283eb2dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425686081 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2425686081
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.801800013
Short name T172
Test name
Test status
Simulation time 19065497 ps
CPU time 1.07 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 218692 kb
Host smart-3fe4f777-b45a-41ee-8596-221f99708551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801800013 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.801800013
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1160064152
Short name T399
Test name
Test status
Simulation time 34937415 ps
CPU time 1.35 seconds
Started Aug 08 07:44:11 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 218512 kb
Host smart-9946a8b9-5037-4266-afba-859f669bd448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160064152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1160064152
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.719093094
Short name T565
Test name
Test status
Simulation time 22966706 ps
CPU time 1.22 seconds
Started Aug 08 07:44:18 PM PDT 24
Finished Aug 08 07:44:19 PM PDT 24
Peak memory 224140 kb
Host smart-a2e3ca7b-68bb-4193-b970-cb1c6904bdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719093094 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.719093094
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1321759592
Short name T762
Test name
Test status
Simulation time 24345570 ps
CPU time 0.91 seconds
Started Aug 08 07:44:11 PM PDT 24
Finished Aug 08 07:44:12 PM PDT 24
Peak memory 215316 kb
Host smart-6f8054a5-5940-4740-b72a-7e56bd6a63ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321759592 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1321759592
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2422257888
Short name T489
Test name
Test status
Simulation time 1545449487 ps
CPU time 2.68 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:15 PM PDT 24
Peak memory 220380 kb
Host smart-4f89cd39-9687-48ba-91a9-14e6179c0334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422257888 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2422257888
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.767125947
Short name T563
Test name
Test status
Simulation time 62964056949 ps
CPU time 350.31 seconds
Started Aug 08 07:44:11 PM PDT 24
Finished Aug 08 07:50:02 PM PDT 24
Peak memory 217560 kb
Host smart-95779949-1a5d-4889-9565-3ccaf4cc9555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767125947 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.767125947
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2271899289
Short name T831
Test name
Test status
Simulation time 38274115 ps
CPU time 1.1 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 218676 kb
Host smart-1b2ae4e7-57bd-43ab-b619-8591b6934968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271899289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2271899289
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2882488095
Short name T617
Test name
Test status
Simulation time 25757497 ps
CPU time 1.09 seconds
Started Aug 08 07:44:14 PM PDT 24
Finished Aug 08 07:44:16 PM PDT 24
Peak memory 206896 kb
Host smart-efca37ed-1f5b-4a5e-a3d6-3e4d5ee6c09a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882488095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2882488095
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3750776767
Short name T164
Test name
Test status
Simulation time 136778144 ps
CPU time 1.16 seconds
Started Aug 08 07:44:14 PM PDT 24
Finished Aug 08 07:44:15 PM PDT 24
Peak memory 217444 kb
Host smart-9f08e963-d611-4b7b-bc49-d07537da580c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750776767 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3750776767
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1446546909
Short name T156
Test name
Test status
Simulation time 38214489 ps
CPU time 1.28 seconds
Started Aug 08 07:44:14 PM PDT 24
Finished Aug 08 07:44:15 PM PDT 24
Peak memory 229940 kb
Host smart-fdf6bf19-05bd-4144-a461-826a536c6628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446546909 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1446546909
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1038156719
Short name T402
Test name
Test status
Simulation time 22552474 ps
CPU time 1.18 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 218488 kb
Host smart-374f0926-2836-42bd-8128-975392b3c238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038156719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1038156719
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.4090861232
Short name T101
Test name
Test status
Simulation time 20162841 ps
CPU time 1.07 seconds
Started Aug 08 07:44:11 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 216188 kb
Host smart-4d3dcbd6-dfc0-4739-85e1-35c6d82fa0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090861232 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4090861232
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1748915571
Short name T491
Test name
Test status
Simulation time 95509307 ps
CPU time 0.9 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 215228 kb
Host smart-983f066c-6a67-4fdf-84ea-b4ca743b3ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748915571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1748915571
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1952318297
Short name T813
Test name
Test status
Simulation time 332756481 ps
CPU time 2.35 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:15 PM PDT 24
Peak memory 217144 kb
Host smart-d5a0a531-0f7e-4567-9613-dcbed0b9e57a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952318297 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1952318297
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1459053434
Short name T726
Test name
Test status
Simulation time 82033180782 ps
CPU time 1878.93 seconds
Started Aug 08 07:44:14 PM PDT 24
Finished Aug 08 08:15:33 PM PDT 24
Peak memory 225212 kb
Host smart-9a86fc19-b264-438e-8f41-597c8c70050a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459053434 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1459053434
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2912402993
Short name T766
Test name
Test status
Simulation time 88083017 ps
CPU time 1.17 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 219428 kb
Host smart-9498e650-4179-4553-b2f5-92a3a4a66788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912402993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2912402993
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2868924629
Short name T715
Test name
Test status
Simulation time 23698003 ps
CPU time 0.82 seconds
Started Aug 08 07:44:11 PM PDT 24
Finished Aug 08 07:44:12 PM PDT 24
Peak memory 206824 kb
Host smart-730a9c98-6ba7-49d3-b82a-d89465d99e9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868924629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2868924629
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.968420246
Short name T81
Test name
Test status
Simulation time 10558592 ps
CPU time 0.91 seconds
Started Aug 08 07:44:14 PM PDT 24
Finished Aug 08 07:44:15 PM PDT 24
Peak memory 216500 kb
Host smart-6707ec50-1b8f-4d31-a5e3-61b4e1f6bfc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968420246 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.968420246
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1247311419
Short name T295
Test name
Test status
Simulation time 33498885 ps
CPU time 0.98 seconds
Started Aug 08 07:44:14 PM PDT 24
Finished Aug 08 07:44:15 PM PDT 24
Peak memory 218464 kb
Host smart-4f2f2230-3003-4e63-b224-60801c84a0a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247311419 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1247311419
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.752961745
Short name T683
Test name
Test status
Simulation time 27286941 ps
CPU time 1.12 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:14 PM PDT 24
Peak memory 218892 kb
Host smart-89b381e6-5b64-40e3-aed3-78a02a037c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752961745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.752961745
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.126160530
Short name T392
Test name
Test status
Simulation time 31662977 ps
CPU time 1.47 seconds
Started Aug 08 07:44:13 PM PDT 24
Finished Aug 08 07:44:15 PM PDT 24
Peak memory 218624 kb
Host smart-8c8b68cf-9d4e-446c-bd8a-33556946fc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126160530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.126160530
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2304707970
Short name T100
Test name
Test status
Simulation time 39868051 ps
CPU time 0.86 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 216024 kb
Host smart-f1824ffe-2172-48cc-b943-a298409b569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304707970 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2304707970
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1296139353
Short name T545
Test name
Test status
Simulation time 16441065 ps
CPU time 0.98 seconds
Started Aug 08 07:44:14 PM PDT 24
Finished Aug 08 07:44:16 PM PDT 24
Peak memory 215324 kb
Host smart-bd989399-caec-4db5-bfa1-ef762d1e3ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296139353 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1296139353
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1963582145
Short name T983
Test name
Test status
Simulation time 251724820 ps
CPU time 5.25 seconds
Started Aug 08 07:44:14 PM PDT 24
Finished Aug 08 07:44:20 PM PDT 24
Peak memory 218564 kb
Host smart-5f56bb94-8a2e-496c-b201-b5182b5c4abd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963582145 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1963582145
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.144247141
Short name T721
Test name
Test status
Simulation time 154023352575 ps
CPU time 1596.1 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 08:10:49 PM PDT 24
Peak memory 225080 kb
Host smart-66061c32-af82-48d7-a90f-dd2a5e19227c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144247141 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.144247141
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.834546554
Short name T325
Test name
Test status
Simulation time 94633861 ps
CPU time 1.23 seconds
Started Aug 08 07:44:15 PM PDT 24
Finished Aug 08 07:44:16 PM PDT 24
Peak memory 220680 kb
Host smart-0afe0efc-1f64-4342-89fe-240b0555b64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834546554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.834546554
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1555599757
Short name T596
Test name
Test status
Simulation time 36255171 ps
CPU time 0.82 seconds
Started Aug 08 07:44:14 PM PDT 24
Finished Aug 08 07:44:15 PM PDT 24
Peak memory 206892 kb
Host smart-13871180-a112-4ed3-b100-d9315baaa0cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555599757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1555599757
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2265121177
Short name T547
Test name
Test status
Simulation time 29238538 ps
CPU time 0.83 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:13 PM PDT 24
Peak memory 216192 kb
Host smart-e08ce77e-2466-4bec-8744-c7b13c4f4c4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265121177 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2265121177
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.1107001902
Short name T175
Test name
Test status
Simulation time 35128401 ps
CPU time 1.22 seconds
Started Aug 08 07:44:13 PM PDT 24
Finished Aug 08 07:44:14 PM PDT 24
Peak memory 219944 kb
Host smart-34c86744-3af5-4d1f-8560-b495fb25c85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107001902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1107001902
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_smoke.3311310829
Short name T927
Test name
Test status
Simulation time 18299512 ps
CPU time 1.03 seconds
Started Aug 08 07:44:12 PM PDT 24
Finished Aug 08 07:44:14 PM PDT 24
Peak memory 215324 kb
Host smart-9676909a-8eed-411e-9eea-a9eff3cd188c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311310829 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3311310829
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.848877292
Short name T579
Test name
Test status
Simulation time 132966758 ps
CPU time 1.98 seconds
Started Aug 08 07:44:16 PM PDT 24
Finished Aug 08 07:44:18 PM PDT 24
Peak memory 217252 kb
Host smart-291c4901-8d72-4e57-9188-57515dd257fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848877292 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.848877292
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.446297159
Short name T851
Test name
Test status
Simulation time 64123110186 ps
CPU time 254.1 seconds
Started Aug 08 07:44:09 PM PDT 24
Finished Aug 08 07:48:23 PM PDT 24
Peak memory 218760 kb
Host smart-f7633706-717c-49a2-a296-d0830e974c34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446297159 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.446297159
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2006044025
Short name T975
Test name
Test status
Simulation time 42515284 ps
CPU time 1.2 seconds
Started Aug 08 07:44:24 PM PDT 24
Finished Aug 08 07:44:25 PM PDT 24
Peak memory 219184 kb
Host smart-6d5c4f76-b5c2-4bce-a2f0-b093a044330e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006044025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2006044025
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2544438083
Short name T245
Test name
Test status
Simulation time 34233753 ps
CPU time 0.9 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:21 PM PDT 24
Peak memory 206828 kb
Host smart-f7f4249c-c943-44ff-ad23-925968cf1b6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544438083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2544438083
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2044102931
Short name T74
Test name
Test status
Simulation time 67938392 ps
CPU time 1.13 seconds
Started Aug 08 07:44:21 PM PDT 24
Finished Aug 08 07:44:22 PM PDT 24
Peak memory 218332 kb
Host smart-3e3bbc19-ab8f-4b52-a3a0-64ea137b4e14
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044102931 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2044102931
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.71859367
Short name T187
Test name
Test status
Simulation time 18948753 ps
CPU time 1 seconds
Started Aug 08 07:44:24 PM PDT 24
Finished Aug 08 07:44:25 PM PDT 24
Peak memory 218888 kb
Host smart-69ce5098-9b95-4e4d-900c-57e0702bc48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71859367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.71859367
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.214360230
Short name T353
Test name
Test status
Simulation time 491850323 ps
CPU time 4.94 seconds
Started Aug 08 07:44:23 PM PDT 24
Finished Aug 08 07:44:28 PM PDT 24
Peak memory 218580 kb
Host smart-ee7ad079-60c3-4946-a285-83a7e9268598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214360230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.214360230
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2389287633
Short name T513
Test name
Test status
Simulation time 68183386 ps
CPU time 0.96 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:21 PM PDT 24
Peak memory 223980 kb
Host smart-ecbf55b6-f1ba-460c-b054-1087be4e62df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389287633 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2389287633
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.84533800
Short name T357
Test name
Test status
Simulation time 16635098 ps
CPU time 0.96 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:21 PM PDT 24
Peak memory 215312 kb
Host smart-ffbda1dc-3574-442c-8b90-0867c9d2c659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84533800 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.84533800
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1651715134
Short name T329
Test name
Test status
Simulation time 456526825 ps
CPU time 1.3 seconds
Started Aug 08 07:44:24 PM PDT 24
Finished Aug 08 07:44:25 PM PDT 24
Peak memory 217244 kb
Host smart-1397560e-c00a-4cf8-9cd3-c40645ae61a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651715134 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1651715134
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1412208190
Short name T234
Test name
Test status
Simulation time 721804595825 ps
CPU time 1371.82 seconds
Started Aug 08 07:44:19 PM PDT 24
Finished Aug 08 08:07:11 PM PDT 24
Peak memory 224812 kb
Host smart-aa6597e7-896d-43c9-aa7e-ae6afffa3ed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412208190 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1412208190
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.4026119853
Short name T259
Test name
Test status
Simulation time 52728077 ps
CPU time 1.3 seconds
Started Aug 08 07:43:11 PM PDT 24
Finished Aug 08 07:43:12 PM PDT 24
Peak memory 215624 kb
Host smart-b320a2f7-a00f-486a-ba49-8b67fb7461bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026119853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.4026119853
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3399152930
Short name T783
Test name
Test status
Simulation time 25684868 ps
CPU time 0.93 seconds
Started Aug 08 07:43:11 PM PDT 24
Finished Aug 08 07:43:12 PM PDT 24
Peak memory 215224 kb
Host smart-a88a4d16-486b-4d9e-9145-7860aa6d628c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399152930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3399152930
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1769852390
Short name T226
Test name
Test status
Simulation time 12716764 ps
CPU time 0.81 seconds
Started Aug 08 07:43:11 PM PDT 24
Finished Aug 08 07:43:12 PM PDT 24
Peak memory 216540 kb
Host smart-f391754c-50a5-40a0-9eec-5e02fbf74492
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769852390 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1769852390
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.4118093199
Short name T867
Test name
Test status
Simulation time 100416843 ps
CPU time 1.06 seconds
Started Aug 08 07:43:14 PM PDT 24
Finished Aug 08 07:43:15 PM PDT 24
Peak memory 218228 kb
Host smart-91c23d5a-e4a4-471b-80c1-1c292a8bf522
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118093199 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.4118093199
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_genbits.1348891378
Short name T713
Test name
Test status
Simulation time 62172000 ps
CPU time 2.4 seconds
Started Aug 08 07:43:13 PM PDT 24
Finished Aug 08 07:43:15 PM PDT 24
Peak memory 220256 kb
Host smart-b6e863a5-767d-45e6-b520-c9f9d75f1da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348891378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1348891378
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2516207187
Short name T70
Test name
Test status
Simulation time 21975970 ps
CPU time 1.15 seconds
Started Aug 08 07:43:12 PM PDT 24
Finished Aug 08 07:43:13 PM PDT 24
Peak memory 215516 kb
Host smart-fe21e917-4370-4ca3-bf62-8e007bcad645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516207187 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2516207187
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.4110537730
Short name T316
Test name
Test status
Simulation time 24894110 ps
CPU time 0.94 seconds
Started Aug 08 07:43:15 PM PDT 24
Finished Aug 08 07:43:16 PM PDT 24
Peak memory 207084 kb
Host smart-00422350-2d2b-483c-aa1e-bc686269acfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110537730 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.4110537730
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3131334805
Short name T492
Test name
Test status
Simulation time 75101883 ps
CPU time 0.82 seconds
Started Aug 08 07:43:11 PM PDT 24
Finished Aug 08 07:43:12 PM PDT 24
Peak memory 215088 kb
Host smart-8a31ad9b-2898-4ff0-946a-6bbd24a57374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131334805 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3131334805
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1949411681
Short name T899
Test name
Test status
Simulation time 271772523 ps
CPU time 5.17 seconds
Started Aug 08 07:43:15 PM PDT 24
Finished Aug 08 07:43:21 PM PDT 24
Peak memory 215316 kb
Host smart-da3ee30e-db26-4734-a6d2-f9e649ff5d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949411681 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1949411681
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3016385046
Short name T445
Test name
Test status
Simulation time 105018186559 ps
CPU time 1029.89 seconds
Started Aug 08 07:43:11 PM PDT 24
Finished Aug 08 08:00:21 PM PDT 24
Peak memory 222024 kb
Host smart-20194ee6-439e-4063-893e-2c6f1bcc40c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016385046 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3016385046
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1281791927
Short name T660
Test name
Test status
Simulation time 43377047 ps
CPU time 1.15 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:22 PM PDT 24
Peak memory 219676 kb
Host smart-f275d9c8-d7ac-4e97-b5fa-22c0500029b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281791927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1281791927
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2697647731
Short name T51
Test name
Test status
Simulation time 14710096 ps
CPU time 0.89 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:21 PM PDT 24
Peak memory 215216 kb
Host smart-ce91fb30-49bf-4c29-8ed6-13055b60f2d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697647731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2697647731
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.4002388178
Short name T197
Test name
Test status
Simulation time 11871162 ps
CPU time 0.88 seconds
Started Aug 08 07:44:25 PM PDT 24
Finished Aug 08 07:44:25 PM PDT 24
Peak memory 216632 kb
Host smart-11a61936-3f5b-4871-bb31-edccc10ef28e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002388178 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.4002388178
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2986783572
Short name T561
Test name
Test status
Simulation time 32619509 ps
CPU time 1.16 seconds
Started Aug 08 07:44:22 PM PDT 24
Finished Aug 08 07:44:23 PM PDT 24
Peak memory 218724 kb
Host smart-7c69cc37-4764-416b-b218-ab651a2e954f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986783572 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2986783572
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.416005775
Short name T658
Test name
Test status
Simulation time 33317270 ps
CPU time 0.96 seconds
Started Aug 08 07:44:25 PM PDT 24
Finished Aug 08 07:44:26 PM PDT 24
Peak memory 219932 kb
Host smart-4ac97ab7-306c-4be9-9aea-46741d2fd71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416005775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.416005775
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2785507612
Short name T11
Test name
Test status
Simulation time 58098328 ps
CPU time 1.41 seconds
Started Aug 08 07:44:23 PM PDT 24
Finished Aug 08 07:44:24 PM PDT 24
Peak memory 219816 kb
Host smart-85ee9964-ac4d-4bc3-a32d-bf0187893eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785507612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2785507612
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_smoke.2543448740
Short name T533
Test name
Test status
Simulation time 19779887 ps
CPU time 1.05 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:21 PM PDT 24
Peak memory 215300 kb
Host smart-5517fd76-8a37-4d6e-b1e2-67437c338fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543448740 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2543448740
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.4229487835
Short name T552
Test name
Test status
Simulation time 125142865 ps
CPU time 2.85 seconds
Started Aug 08 07:44:21 PM PDT 24
Finished Aug 08 07:44:24 PM PDT 24
Peak memory 217216 kb
Host smart-1e58c325-3b23-4815-a608-3453e67bbd8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229487835 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.4229487835
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.209841649
Short name T237
Test name
Test status
Simulation time 12798208797 ps
CPU time 282.92 seconds
Started Aug 08 07:44:21 PM PDT 24
Finished Aug 08 07:49:04 PM PDT 24
Peak memory 220956 kb
Host smart-bebf0303-24bc-491a-b7f9-c88103a2f9df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209841649 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.209841649
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.4085685129
Short name T424
Test name
Test status
Simulation time 165558352 ps
CPU time 1.03 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:22 PM PDT 24
Peak memory 218504 kb
Host smart-1b390a95-e383-47c8-939d-059d89b89f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085685129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.4085685129
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2937819707
Short name T503
Test name
Test status
Simulation time 35588709 ps
CPU time 0.94 seconds
Started Aug 08 07:44:25 PM PDT 24
Finished Aug 08 07:44:26 PM PDT 24
Peak memory 215160 kb
Host smart-f46362f0-0725-4b4b-882e-75af5539970f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937819707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2937819707
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.936619338
Short name T853
Test name
Test status
Simulation time 22832808 ps
CPU time 0.87 seconds
Started Aug 08 07:44:19 PM PDT 24
Finished Aug 08 07:44:20 PM PDT 24
Peak memory 216500 kb
Host smart-c1d593c2-ced3-43dd-b3dc-473d42129697
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936619338 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.936619338
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.365522752
Short name T666
Test name
Test status
Simulation time 52783434 ps
CPU time 1.07 seconds
Started Aug 08 07:44:23 PM PDT 24
Finished Aug 08 07:44:25 PM PDT 24
Peak memory 219480 kb
Host smart-6fbe9066-0f0a-4e59-aff5-100520db6412
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365522752 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.365522752
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.834996364
Short name T150
Test name
Test status
Simulation time 27044773 ps
CPU time 1.18 seconds
Started Aug 08 07:44:23 PM PDT 24
Finished Aug 08 07:44:25 PM PDT 24
Peak memory 218748 kb
Host smart-9aaff31d-fd45-4dd6-a1a0-b5df3208e2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834996364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.834996364
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1259530593
Short name T929
Test name
Test status
Simulation time 41736169 ps
CPU time 1.08 seconds
Started Aug 08 07:44:23 PM PDT 24
Finished Aug 08 07:44:25 PM PDT 24
Peak memory 217208 kb
Host smart-c6235e57-23b8-4f17-8780-c0d2266327f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259530593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1259530593
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1519720747
Short name T53
Test name
Test status
Simulation time 39652913 ps
CPU time 1.04 seconds
Started Aug 08 07:44:19 PM PDT 24
Finished Aug 08 07:44:21 PM PDT 24
Peak memory 224108 kb
Host smart-0db110d2-d146-40a0-b298-7aba16d59fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519720747 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1519720747
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3911498124
Short name T486
Test name
Test status
Simulation time 192626307 ps
CPU time 0.95 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:21 PM PDT 24
Peak memory 207160 kb
Host smart-13276147-c93e-48c0-9a56-b36c3c96eb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911498124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3911498124
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.894640098
Short name T65
Test name
Test status
Simulation time 569541250 ps
CPU time 3.6 seconds
Started Aug 08 07:44:23 PM PDT 24
Finished Aug 08 07:44:27 PM PDT 24
Peak memory 217500 kb
Host smart-483b9769-f1bf-4e66-98c3-e5cf5741e9df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894640098 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.894640098
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.307577023
Short name T236
Test name
Test status
Simulation time 29813937946 ps
CPU time 414.17 seconds
Started Aug 08 07:44:23 PM PDT 24
Finished Aug 08 07:51:18 PM PDT 24
Peak memory 218268 kb
Host smart-e904fed5-880c-49c4-9293-0e3db73c1485
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307577023 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.307577023
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.12219451
Short name T50
Test name
Test status
Simulation time 28191526 ps
CPU time 1.24 seconds
Started Aug 08 07:44:19 PM PDT 24
Finished Aug 08 07:44:20 PM PDT 24
Peak memory 219728 kb
Host smart-b379ece2-20a8-4e2b-be00-bf584a5ea092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12219451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.12219451
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2176211325
Short name T668
Test name
Test status
Simulation time 47653446 ps
CPU time 0.86 seconds
Started Aug 08 07:44:24 PM PDT 24
Finished Aug 08 07:44:25 PM PDT 24
Peak memory 215136 kb
Host smart-93cdff7c-490b-42a8-9312-3387c42f9cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176211325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2176211325
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3115317474
Short name T970
Test name
Test status
Simulation time 13011024 ps
CPU time 0.88 seconds
Started Aug 08 07:44:21 PM PDT 24
Finished Aug 08 07:44:22 PM PDT 24
Peak memory 216440 kb
Host smart-9a512ceb-2687-4107-9c9d-d99f85a3ed8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115317474 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3115317474
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3681839327
Short name T162
Test name
Test status
Simulation time 117639093 ps
CPU time 1.13 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:22 PM PDT 24
Peak memory 217288 kb
Host smart-7cd689c3-f3fb-42fd-93d8-9cf281d7d245
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681839327 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3681839327
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1267066823
Short name T971
Test name
Test status
Simulation time 30897015 ps
CPU time 1.38 seconds
Started Aug 08 07:44:21 PM PDT 24
Finished Aug 08 07:44:23 PM PDT 24
Peak memory 225784 kb
Host smart-6b807257-4d78-4c3a-9501-e44470501927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267066823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1267066823
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1922825138
Short name T743
Test name
Test status
Simulation time 30848522 ps
CPU time 1.3 seconds
Started Aug 08 07:44:24 PM PDT 24
Finished Aug 08 07:44:26 PM PDT 24
Peak memory 217472 kb
Host smart-ab55ae53-d1a6-493e-9243-7e06c3113e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922825138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1922825138
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.818725869
Short name T434
Test name
Test status
Simulation time 23022594 ps
CPU time 1.13 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:21 PM PDT 24
Peak memory 215372 kb
Host smart-1f2e7e74-8257-4b5c-af06-e782b67b5259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818725869 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.818725869
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.590424832
Short name T374
Test name
Test status
Simulation time 24443350 ps
CPU time 0.87 seconds
Started Aug 08 07:44:24 PM PDT 24
Finished Aug 08 07:44:25 PM PDT 24
Peak memory 215344 kb
Host smart-a936d3df-39c3-4280-9d71-3ec30fe460b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590424832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.590424832
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.423464640
Short name T791
Test name
Test status
Simulation time 182242853 ps
CPU time 3.93 seconds
Started Aug 08 07:44:24 PM PDT 24
Finished Aug 08 07:44:28 PM PDT 24
Peak memory 220452 kb
Host smart-20e63402-fa7f-4c5c-b52a-56e39da6974c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423464640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.423464640
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.331365066
Short name T243
Test name
Test status
Simulation time 48763314020 ps
CPU time 777.83 seconds
Started Aug 08 07:44:23 PM PDT 24
Finished Aug 08 07:57:22 PM PDT 24
Peak memory 223776 kb
Host smart-fc912589-6932-4d1a-a73d-ec01cf0e1952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331365066 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.331365066
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2259457139
Short name T753
Test name
Test status
Simulation time 26036951 ps
CPU time 1.24 seconds
Started Aug 08 07:44:25 PM PDT 24
Finished Aug 08 07:44:26 PM PDT 24
Peak memory 219328 kb
Host smart-0ae7aeba-cf12-453c-802e-24c5594ed0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259457139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2259457139
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3440134296
Short name T364
Test name
Test status
Simulation time 23464726 ps
CPU time 0.84 seconds
Started Aug 08 07:44:25 PM PDT 24
Finished Aug 08 07:44:26 PM PDT 24
Peak memory 206656 kb
Host smart-925da978-5c23-427a-8cc6-ecf3eadd0ba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440134296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3440134296
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1947567352
Short name T69
Test name
Test status
Simulation time 111041231 ps
CPU time 1.15 seconds
Started Aug 08 07:44:25 PM PDT 24
Finished Aug 08 07:44:27 PM PDT 24
Peak memory 218324 kb
Host smart-b6bf3ef0-0ba6-49c2-ab4d-413adc0c1eec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947567352 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1947567352
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3401375062
Short name T202
Test name
Test status
Simulation time 21901866 ps
CPU time 0.94 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:21 PM PDT 24
Peak memory 218812 kb
Host smart-d0cf3424-b82c-432b-85b3-4a90820fd8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401375062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3401375062
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1445250919
Short name T305
Test name
Test status
Simulation time 111367024 ps
CPU time 1.64 seconds
Started Aug 08 07:44:20 PM PDT 24
Finished Aug 08 07:44:22 PM PDT 24
Peak memory 219060 kb
Host smart-ce6c6e03-fce9-42d7-9672-ea1b08de5f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445250919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1445250919
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3096656655
Short name T380
Test name
Test status
Simulation time 22540998 ps
CPU time 1.12 seconds
Started Aug 08 07:44:23 PM PDT 24
Finished Aug 08 07:44:24 PM PDT 24
Peak memory 215164 kb
Host smart-e7670148-2c17-4a75-83be-f397c3e3bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096656655 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3096656655
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3974342260
Short name T506
Test name
Test status
Simulation time 41411302 ps
CPU time 0.92 seconds
Started Aug 08 07:44:25 PM PDT 24
Finished Aug 08 07:44:26 PM PDT 24
Peak memory 215268 kb
Host smart-3abfdf7e-ebf4-4ad2-a3ab-6e9e4a1b9aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974342260 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3974342260
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.18108973
Short name T774
Test name
Test status
Simulation time 959745906 ps
CPU time 4.75 seconds
Started Aug 08 07:44:24 PM PDT 24
Finished Aug 08 07:44:29 PM PDT 24
Peak memory 217472 kb
Host smart-24dfc6e7-fa3e-47da-a12d-2207a0c56b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18108973 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.18108973
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3820997086
Short name T241
Test name
Test status
Simulation time 35248110930 ps
CPU time 769.38 seconds
Started Aug 08 07:44:24 PM PDT 24
Finished Aug 08 07:57:13 PM PDT 24
Peak memory 223612 kb
Host smart-5595833b-b039-4041-978f-1b070691a0a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820997086 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3820997086
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2413347776
Short name T258
Test name
Test status
Simulation time 31416234 ps
CPU time 1.26 seconds
Started Aug 08 07:44:23 PM PDT 24
Finished Aug 08 07:44:24 PM PDT 24
Peak memory 219812 kb
Host smart-5473badd-ffd9-45a9-9cb6-8a5472faa8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413347776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2413347776
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1898671218
Short name T432
Test name
Test status
Simulation time 51503650 ps
CPU time 0.88 seconds
Started Aug 08 07:44:29 PM PDT 24
Finished Aug 08 07:44:30 PM PDT 24
Peak memory 206808 kb
Host smart-c9823e74-4450-40f4-8949-c4c8651aaa2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898671218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1898671218
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.343589348
Short name T221
Test name
Test status
Simulation time 128398432 ps
CPU time 0.86 seconds
Started Aug 08 07:44:27 PM PDT 24
Finished Aug 08 07:44:28 PM PDT 24
Peak memory 216588 kb
Host smart-6774ca2f-d61d-475b-91af-fc5eb91a5d42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343589348 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.343589348
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3608172628
Short name T136
Test name
Test status
Simulation time 65537698 ps
CPU time 1.07 seconds
Started Aug 08 07:44:29 PM PDT 24
Finished Aug 08 07:44:30 PM PDT 24
Peak memory 219344 kb
Host smart-3893ad69-c807-4896-a2f7-9951075473e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608172628 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3608172628
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3385198799
Short name T413
Test name
Test status
Simulation time 29006394 ps
CPU time 0.85 seconds
Started Aug 08 07:44:24 PM PDT 24
Finished Aug 08 07:44:25 PM PDT 24
Peak memory 218444 kb
Host smart-b4703c22-80ac-4001-841c-849c0abee230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385198799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3385198799
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3818514549
Short name T898
Test name
Test status
Simulation time 52239726 ps
CPU time 1.1 seconds
Started Aug 08 07:44:26 PM PDT 24
Finished Aug 08 07:44:27 PM PDT 24
Peak memory 217308 kb
Host smart-5712a64a-6d20-47db-8881-cc8dd92a75fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818514549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3818514549
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.688473573
Short name T30
Test name
Test status
Simulation time 38016736 ps
CPU time 0.84 seconds
Started Aug 08 07:44:25 PM PDT 24
Finished Aug 08 07:44:26 PM PDT 24
Peak memory 215916 kb
Host smart-fa9fa0ac-9db4-4e2f-86ba-24c85eb5fd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688473573 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.688473573
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3151267739
Short name T799
Test name
Test status
Simulation time 15138582 ps
CPU time 0.97 seconds
Started Aug 08 07:44:25 PM PDT 24
Finished Aug 08 07:44:26 PM PDT 24
Peak memory 215268 kb
Host smart-910070c7-506b-4400-9c7a-8e64c36f1d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151267739 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3151267739
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1069237526
Short name T52
Test name
Test status
Simulation time 696974976 ps
CPU time 4 seconds
Started Aug 08 07:44:24 PM PDT 24
Finished Aug 08 07:44:28 PM PDT 24
Peak memory 217200 kb
Host smart-49e9bfff-4057-414a-97a8-bd72e6ec452f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069237526 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1069237526
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2443900174
Short name T693
Test name
Test status
Simulation time 74525393877 ps
CPU time 847.55 seconds
Started Aug 08 07:44:26 PM PDT 24
Finished Aug 08 07:58:34 PM PDT 24
Peak memory 221112 kb
Host smart-1a43a2d1-ff38-4a61-bff4-bde5dc227d52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443900174 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2443900174
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2352315836
Short name T958
Test name
Test status
Simulation time 41551225 ps
CPU time 1.12 seconds
Started Aug 08 07:44:24 PM PDT 24
Finished Aug 08 07:44:26 PM PDT 24
Peak memory 218440 kb
Host smart-c84c935e-0ebc-49ee-867a-05e747b15ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352315836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2352315836
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1270650352
Short name T443
Test name
Test status
Simulation time 21647998 ps
CPU time 0.9 seconds
Started Aug 08 07:44:33 PM PDT 24
Finished Aug 08 07:44:34 PM PDT 24
Peak memory 215204 kb
Host smart-2f09a46c-3e38-4bd7-be97-177bd56fc0f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270650352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1270650352
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1557951173
Short name T212
Test name
Test status
Simulation time 39742337 ps
CPU time 0.89 seconds
Started Aug 08 07:44:33 PM PDT 24
Finished Aug 08 07:44:34 PM PDT 24
Peak memory 216512 kb
Host smart-38467d0a-3150-4cfc-a273-de63887a8dac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557951173 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1557951173
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.4167087842
Short name T148
Test name
Test status
Simulation time 57310838 ps
CPU time 1.04 seconds
Started Aug 08 07:44:32 PM PDT 24
Finished Aug 08 07:44:33 PM PDT 24
Peak memory 219712 kb
Host smart-9559875d-ec7f-4046-b696-0e33a157abf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167087842 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.4167087842
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1038962623
Short name T182
Test name
Test status
Simulation time 21563804 ps
CPU time 0.93 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:32 PM PDT 24
Peak memory 218664 kb
Host smart-79a97926-ecb7-4e92-95bf-bccf323e9503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038962623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1038962623
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3705051703
Short name T89
Test name
Test status
Simulation time 80262525 ps
CPU time 1.97 seconds
Started Aug 08 07:44:29 PM PDT 24
Finished Aug 08 07:44:31 PM PDT 24
Peak memory 217264 kb
Host smart-f8153816-cf76-4664-a59e-8a68f105a517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705051703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3705051703
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2388271073
Short name T953
Test name
Test status
Simulation time 20224854 ps
CPU time 1.12 seconds
Started Aug 08 07:44:25 PM PDT 24
Finished Aug 08 07:44:26 PM PDT 24
Peak memory 215992 kb
Host smart-13e60635-9dfe-4521-87be-45523638554d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388271073 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2388271073
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3494823681
Short name T383
Test name
Test status
Simulation time 49552796 ps
CPU time 0.95 seconds
Started Aug 08 07:44:25 PM PDT 24
Finished Aug 08 07:44:26 PM PDT 24
Peak memory 215336 kb
Host smart-395d9b9c-2262-4a5c-a004-7916a24bb72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494823681 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3494823681
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.922688981
Short name T450
Test name
Test status
Simulation time 1071365128 ps
CPU time 3.84 seconds
Started Aug 08 07:44:29 PM PDT 24
Finished Aug 08 07:44:33 PM PDT 24
Peak memory 217116 kb
Host smart-6359793b-fbde-4ece-881c-26beb8ed98a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922688981 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.922688981
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.4168322040
Short name T765
Test name
Test status
Simulation time 11114691273 ps
CPU time 293.61 seconds
Started Aug 08 07:44:26 PM PDT 24
Finished Aug 08 07:49:19 PM PDT 24
Peak memory 218136 kb
Host smart-9f294bc9-a23a-4cc4-9dd3-f3acc64d2a20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168322040 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.4168322040
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.111554968
Short name T932
Test name
Test status
Simulation time 70655529 ps
CPU time 1.13 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:32 PM PDT 24
Peak memory 215564 kb
Host smart-ac8f64a8-b07c-4e6a-8be5-d9faea25ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111554968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.111554968
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2018458443
Short name T742
Test name
Test status
Simulation time 45835337 ps
CPU time 0.85 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:32 PM PDT 24
Peak memory 215196 kb
Host smart-8bc04a84-3322-4a38-ae35-870e8ff4b1c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018458443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2018458443
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2946443146
Short name T454
Test name
Test status
Simulation time 44862782 ps
CPU time 0.82 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:31 PM PDT 24
Peak memory 216272 kb
Host smart-2bcc4e88-e60e-4ce6-b747-30a6e5dc2236
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946443146 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2946443146
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3336384603
Short name T80
Test name
Test status
Simulation time 74228025 ps
CPU time 1.07 seconds
Started Aug 08 07:44:28 PM PDT 24
Finished Aug 08 07:44:29 PM PDT 24
Peak memory 219584 kb
Host smart-5f362c14-ff13-459e-894e-223e1280ba6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336384603 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3336384603
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2985756865
Short name T619
Test name
Test status
Simulation time 24963415 ps
CPU time 1.21 seconds
Started Aug 08 07:44:30 PM PDT 24
Finished Aug 08 07:44:31 PM PDT 24
Peak memory 220820 kb
Host smart-3236abe2-d72f-4041-8e05-a3976eff05d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985756865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2985756865
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2814051590
Short name T735
Test name
Test status
Simulation time 36454830 ps
CPU time 1.07 seconds
Started Aug 08 07:44:32 PM PDT 24
Finished Aug 08 07:44:33 PM PDT 24
Peak memory 217256 kb
Host smart-0691d44c-5338-4646-93af-f7412b2883ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814051590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2814051590
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.479365353
Short name T574
Test name
Test status
Simulation time 21382890 ps
CPU time 1.12 seconds
Started Aug 08 07:44:33 PM PDT 24
Finished Aug 08 07:44:34 PM PDT 24
Peak memory 216096 kb
Host smart-dfeb1d49-37fe-49bd-bce7-fc754d1397d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479365353 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.479365353
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1204734282
Short name T418
Test name
Test status
Simulation time 116277311 ps
CPU time 0.9 seconds
Started Aug 08 07:44:34 PM PDT 24
Finished Aug 08 07:44:35 PM PDT 24
Peak memory 215332 kb
Host smart-5e135046-18fa-47a6-b00b-59e7deffad95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204734282 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1204734282
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1595921774
Short name T770
Test name
Test status
Simulation time 250307080 ps
CPU time 2.91 seconds
Started Aug 08 07:44:33 PM PDT 24
Finished Aug 08 07:44:36 PM PDT 24
Peak memory 219760 kb
Host smart-22c6d3db-da03-4e1b-94bc-46a296ca5408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595921774 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1595921774
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3333451304
Short name T946
Test name
Test status
Simulation time 104275505912 ps
CPU time 1201.7 seconds
Started Aug 08 07:44:30 PM PDT 24
Finished Aug 08 08:04:32 PM PDT 24
Peak memory 222556 kb
Host smart-c203b5be-2723-4b7c-831b-20c3611db4b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333451304 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3333451304
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.454015003
Short name T699
Test name
Test status
Simulation time 68296899 ps
CPU time 1.2 seconds
Started Aug 08 07:44:38 PM PDT 24
Finished Aug 08 07:44:39 PM PDT 24
Peak memory 220448 kb
Host smart-cdee6c2b-7cec-4371-83fe-1ad0627eb4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454015003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.454015003
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.611903094
Short name T358
Test name
Test status
Simulation time 16563968 ps
CPU time 0.84 seconds
Started Aug 08 07:44:37 PM PDT 24
Finished Aug 08 07:44:38 PM PDT 24
Peak memory 206848 kb
Host smart-5086e179-fb36-4d91-ac47-9324b3836f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611903094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.611903094
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1209702859
Short name T879
Test name
Test status
Simulation time 34127125 ps
CPU time 1.23 seconds
Started Aug 08 07:44:34 PM PDT 24
Finished Aug 08 07:44:35 PM PDT 24
Peak memory 219740 kb
Host smart-2f60b239-2d32-4506-9d17-2992f5b14548
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209702859 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1209702859
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3419349833
Short name T620
Test name
Test status
Simulation time 35946639 ps
CPU time 0.93 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:32 PM PDT 24
Peak memory 218900 kb
Host smart-baf33438-9f22-423f-987d-c3ff752beba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419349833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3419349833
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.917297592
Short name T609
Test name
Test status
Simulation time 36642499 ps
CPU time 1.77 seconds
Started Aug 08 07:44:37 PM PDT 24
Finished Aug 08 07:44:39 PM PDT 24
Peak memory 218736 kb
Host smart-3fff050c-e7b3-48d7-b589-725b2387a629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917297592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.917297592
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2288650045
Short name T395
Test name
Test status
Simulation time 23389727 ps
CPU time 0.97 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:32 PM PDT 24
Peak memory 216172 kb
Host smart-27a75db6-0709-4e0e-b6bd-cfea47ded76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288650045 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2288650045
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3220342368
Short name T732
Test name
Test status
Simulation time 27571210 ps
CPU time 1.02 seconds
Started Aug 08 07:44:37 PM PDT 24
Finished Aug 08 07:44:38 PM PDT 24
Peak memory 215492 kb
Host smart-f6f68d61-7a14-4667-bf8e-4103921d5b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220342368 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3220342368
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2986436537
Short name T115
Test name
Test status
Simulation time 694356371 ps
CPU time 3.38 seconds
Started Aug 08 07:44:30 PM PDT 24
Finished Aug 08 07:44:34 PM PDT 24
Peak memory 217284 kb
Host smart-15f721ec-b5da-4ba9-b35e-22c9b64ab610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986436537 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2986436537
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2083462470
Short name T231
Test name
Test status
Simulation time 36019842718 ps
CPU time 811.15 seconds
Started Aug 08 07:44:33 PM PDT 24
Finished Aug 08 07:58:04 PM PDT 24
Peak memory 219916 kb
Host smart-b0653849-9daa-4e7e-995e-90a820c4fd46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083462470 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2083462470
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3406807776
Short name T624
Test name
Test status
Simulation time 47830256 ps
CPU time 1.15 seconds
Started Aug 08 07:44:28 PM PDT 24
Finished Aug 08 07:44:30 PM PDT 24
Peak memory 219620 kb
Host smart-2b1b4204-e2df-4e62-8454-f11de2e7778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406807776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3406807776
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2319029688
Short name T984
Test name
Test status
Simulation time 49543001 ps
CPU time 0.88 seconds
Started Aug 08 07:44:38 PM PDT 24
Finished Aug 08 07:44:39 PM PDT 24
Peak memory 206796 kb
Host smart-0d28b29c-2419-4f34-bf71-6c39d15daad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319029688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2319029688
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3454721050
Short name T47
Test name
Test status
Simulation time 34623523 ps
CPU time 0.86 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:32 PM PDT 24
Peak memory 216292 kb
Host smart-bca6e625-c5b7-4ced-a648-ded0914d5998
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454721050 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3454721050
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.493771718
Short name T439
Test name
Test status
Simulation time 111939285 ps
CPU time 1.16 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:33 PM PDT 24
Peak memory 218508 kb
Host smart-eb758d45-9e0c-4a33-bea6-bcd6b60d2859
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493771718 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.493771718
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1661327383
Short name T133
Test name
Test status
Simulation time 37069492 ps
CPU time 1.05 seconds
Started Aug 08 07:44:35 PM PDT 24
Finished Aug 08 07:44:36 PM PDT 24
Peak memory 220888 kb
Host smart-0954adbe-72c6-47ea-a5bc-490068380b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661327383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1661327383
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3083775613
Short name T85
Test name
Test status
Simulation time 32507323 ps
CPU time 1.39 seconds
Started Aug 08 07:44:30 PM PDT 24
Finished Aug 08 07:44:31 PM PDT 24
Peak memory 217192 kb
Host smart-29e8bdb5-1ea6-4cd0-97b2-014f26c87c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083775613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3083775613
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2522307741
Short name T481
Test name
Test status
Simulation time 108991299 ps
CPU time 0.92 seconds
Started Aug 08 07:44:37 PM PDT 24
Finished Aug 08 07:44:38 PM PDT 24
Peak memory 215568 kb
Host smart-b352cb28-02fd-4bb7-89e5-89a4e81484c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522307741 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2522307741
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.527950194
Short name T404
Test name
Test status
Simulation time 41635145 ps
CPU time 0.91 seconds
Started Aug 08 07:44:29 PM PDT 24
Finished Aug 08 07:44:30 PM PDT 24
Peak memory 215364 kb
Host smart-00231ca4-8aa3-4f25-bb6a-017c7b9166e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527950194 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.527950194
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1804258451
Short name T724
Test name
Test status
Simulation time 206557241 ps
CPU time 4.23 seconds
Started Aug 08 07:44:33 PM PDT 24
Finished Aug 08 07:44:37 PM PDT 24
Peak memory 215344 kb
Host smart-eb6d63d1-ab84-4454-8753-c9fa6b27f150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804258451 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1804258451
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.143052408
Short name T239
Test name
Test status
Simulation time 17489792903 ps
CPU time 199.85 seconds
Started Aug 08 07:44:38 PM PDT 24
Finished Aug 08 07:47:58 PM PDT 24
Peak memory 217264 kb
Host smart-a3402e80-86a2-4c49-bce2-0647057f42e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143052408 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.143052408
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2614981668
Short name T510
Test name
Test status
Simulation time 140774434 ps
CPU time 1.15 seconds
Started Aug 08 07:44:32 PM PDT 24
Finished Aug 08 07:44:33 PM PDT 24
Peak memory 218588 kb
Host smart-25ebfb40-afb1-499e-85d1-38fff92cf9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614981668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2614981668
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1917387124
Short name T425
Test name
Test status
Simulation time 76704475 ps
CPU time 0.84 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:32 PM PDT 24
Peak memory 206644 kb
Host smart-744dae16-a81b-41b0-a126-8de468cc915e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917387124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1917387124
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.439446193
Short name T215
Test name
Test status
Simulation time 15724059 ps
CPU time 0.85 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:32 PM PDT 24
Peak memory 216580 kb
Host smart-589177b5-3def-4321-a741-23683eb6cfc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439446193 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.439446193
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1441721444
Short name T644
Test name
Test status
Simulation time 189693389 ps
CPU time 1.21 seconds
Started Aug 08 07:44:35 PM PDT 24
Finished Aug 08 07:44:37 PM PDT 24
Peak memory 217164 kb
Host smart-f22d40b6-a3e9-4e4d-ba8d-afb52c81d5f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441721444 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1441721444
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1644977226
Short name T210
Test name
Test status
Simulation time 41244508 ps
CPU time 0.96 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:32 PM PDT 24
Peak memory 229128 kb
Host smart-364ea21f-f0fd-453f-b37a-324d1164c14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644977226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1644977226
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1696751463
Short name T48
Test name
Test status
Simulation time 30781957 ps
CPU time 1.3 seconds
Started Aug 08 07:44:35 PM PDT 24
Finished Aug 08 07:44:36 PM PDT 24
Peak memory 218652 kb
Host smart-0d147e8a-205a-4452-9360-431d1ffe702b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696751463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1696751463
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.4141731706
Short name T54
Test name
Test status
Simulation time 24175080 ps
CPU time 1.05 seconds
Started Aug 08 07:44:30 PM PDT 24
Finished Aug 08 07:44:31 PM PDT 24
Peak memory 224172 kb
Host smart-06dca123-4873-463e-87d2-6b71e7408799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141731706 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.4141731706
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.929568754
Short name T796
Test name
Test status
Simulation time 25430367 ps
CPU time 0.92 seconds
Started Aug 08 07:44:27 PM PDT 24
Finished Aug 08 07:44:28 PM PDT 24
Peak memory 215320 kb
Host smart-70caa114-8e93-4b70-91fb-38e69f3aeda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929568754 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.929568754
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2945793674
Short name T692
Test name
Test status
Simulation time 2474395550 ps
CPU time 5.29 seconds
Started Aug 08 07:44:33 PM PDT 24
Finished Aug 08 07:44:39 PM PDT 24
Peak memory 217500 kb
Host smart-9d531bcb-2773-4649-bec5-29b0396725e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945793674 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2945793674
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1595521348
Short name T233
Test name
Test status
Simulation time 190011624283 ps
CPU time 1247.43 seconds
Started Aug 08 07:44:35 PM PDT 24
Finished Aug 08 08:05:23 PM PDT 24
Peak memory 225568 kb
Host smart-a7637f1d-faa4-4364-bdce-ea1df89a0f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595521348 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1595521348
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3932570006
Short name T811
Test name
Test status
Simulation time 30576352 ps
CPU time 1.24 seconds
Started Aug 08 07:43:40 PM PDT 24
Finished Aug 08 07:43:42 PM PDT 24
Peak memory 219716 kb
Host smart-f7026ef2-0f2b-4c04-b31d-52c29582a86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932570006 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3932570006
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2651294639
Short name T905
Test name
Test status
Simulation time 15878059 ps
CPU time 0.89 seconds
Started Aug 08 07:43:20 PM PDT 24
Finished Aug 08 07:43:21 PM PDT 24
Peak memory 206828 kb
Host smart-f2765c50-c4b0-4efe-be10-3ee566ba6a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651294639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2651294639
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2007419505
Short name T645
Test name
Test status
Simulation time 39836955 ps
CPU time 0.87 seconds
Started Aug 08 07:43:31 PM PDT 24
Finished Aug 08 07:43:32 PM PDT 24
Peak memory 219124 kb
Host smart-73b9c004-2797-4f0a-8ef7-1e73190895f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007419505 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2007419505
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.880886036
Short name T863
Test name
Test status
Simulation time 50497130 ps
CPU time 1.46 seconds
Started Aug 08 07:43:22 PM PDT 24
Finished Aug 08 07:43:24 PM PDT 24
Peak memory 217076 kb
Host smart-a77a189e-92fa-4ce4-bd47-84b9866eac95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880886036 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.880886036
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1949044727
Short name T757
Test name
Test status
Simulation time 22401153 ps
CPU time 1.29 seconds
Started Aug 08 07:43:23 PM PDT 24
Finished Aug 08 07:43:25 PM PDT 24
Peak memory 229728 kb
Host smart-909f5867-7034-4d8f-97cb-0c7c8b49b517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949044727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1949044727
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2476685166
Short name T706
Test name
Test status
Simulation time 204218780 ps
CPU time 1.5 seconds
Started Aug 08 07:43:31 PM PDT 24
Finished Aug 08 07:43:33 PM PDT 24
Peak memory 219044 kb
Host smart-856f9113-a8af-4f96-80da-edc9e0bca0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476685166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2476685166
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2201448850
Short name T430
Test name
Test status
Simulation time 24907677 ps
CPU time 1.03 seconds
Started Aug 08 07:43:24 PM PDT 24
Finished Aug 08 07:43:25 PM PDT 24
Peak memory 215532 kb
Host smart-6b7122a0-caa3-4bd9-a6de-f4768e3ebb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201448850 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2201448850
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2835105788
Short name T27
Test name
Test status
Simulation time 15686274 ps
CPU time 1 seconds
Started Aug 08 07:43:24 PM PDT 24
Finished Aug 08 07:43:25 PM PDT 24
Peak memory 207144 kb
Host smart-64b53fac-800d-4b59-ad2d-4f1f517ef9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835105788 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2835105788
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2428870611
Short name T530
Test name
Test status
Simulation time 42769763 ps
CPU time 0.91 seconds
Started Aug 08 07:43:24 PM PDT 24
Finished Aug 08 07:43:25 PM PDT 24
Peak memory 215344 kb
Host smart-6b837052-54ee-46ed-a22c-711a3ec35fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428870611 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2428870611
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2977125365
Short name T113
Test name
Test status
Simulation time 227625996 ps
CPU time 3.78 seconds
Started Aug 08 07:43:31 PM PDT 24
Finished Aug 08 07:43:35 PM PDT 24
Peak memory 219932 kb
Host smart-0a3e80c9-cd8f-4577-a39f-3d593e29115d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977125365 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2977125365
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/50.edn_err.2911306556
Short name T781
Test name
Test status
Simulation time 33479101 ps
CPU time 0.91 seconds
Started Aug 08 07:44:32 PM PDT 24
Finished Aug 08 07:44:33 PM PDT 24
Peak memory 218512 kb
Host smart-49d0024a-af8a-4e67-bc48-13ddd63ddc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911306556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2911306556
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3209720637
Short name T494
Test name
Test status
Simulation time 33211981 ps
CPU time 1.27 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:33 PM PDT 24
Peak memory 218620 kb
Host smart-6e8a6862-f0d5-4619-b112-3b8a9b406e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209720637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3209720637
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2179291805
Short name T870
Test name
Test status
Simulation time 40178393 ps
CPU time 1.11 seconds
Started Aug 08 07:44:35 PM PDT 24
Finished Aug 08 07:44:36 PM PDT 24
Peak memory 219236 kb
Host smart-181fe2e2-2b36-464a-aeb9-b30f16dff101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179291805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2179291805
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.594529585
Short name T684
Test name
Test status
Simulation time 20185705 ps
CPU time 0.96 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:32 PM PDT 24
Peak memory 218776 kb
Host smart-51cd3741-4360-41f3-8153-25309671f917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594529585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.594529585
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3694919861
Short name T803
Test name
Test status
Simulation time 72427283 ps
CPU time 1.28 seconds
Started Aug 08 07:44:31 PM PDT 24
Finished Aug 08 07:44:33 PM PDT 24
Peak memory 218816 kb
Host smart-c5d37901-69a4-4457-bb97-c2317a349fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694919861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3694919861
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3129815097
Short name T849
Test name
Test status
Simulation time 65519005 ps
CPU time 1.25 seconds
Started Aug 08 07:44:37 PM PDT 24
Finished Aug 08 07:44:39 PM PDT 24
Peak memory 219188 kb
Host smart-22df0cb2-0ef4-4994-b7f2-71d166b9d13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129815097 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3129815097
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.1856262168
Short name T4
Test name
Test status
Simulation time 18910604 ps
CPU time 1.05 seconds
Started Aug 08 07:44:41 PM PDT 24
Finished Aug 08 07:44:42 PM PDT 24
Peak memory 218852 kb
Host smart-4de3f848-4f72-4e66-a5f7-acc0cc6a6da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856262168 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1856262168
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.972317902
Short name T659
Test name
Test status
Simulation time 201528220 ps
CPU time 1.37 seconds
Started Aug 08 07:44:34 PM PDT 24
Finished Aug 08 07:44:36 PM PDT 24
Peak memory 219708 kb
Host smart-162d0500-8d40-4379-a8b5-f7585957e9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972317902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.972317902
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.792530301
Short name T23
Test name
Test status
Simulation time 145192955 ps
CPU time 1.32 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 215628 kb
Host smart-1ea21fe4-4a65-4f37-b9c9-50a70144f38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792530301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.792530301
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2856832382
Short name T911
Test name
Test status
Simulation time 29120786 ps
CPU time 0.87 seconds
Started Aug 08 07:44:41 PM PDT 24
Finished Aug 08 07:44:42 PM PDT 24
Peak memory 218772 kb
Host smart-a7b3e02d-394b-4224-979b-c495181b06c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856832382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2856832382
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.14579382
Short name T822
Test name
Test status
Simulation time 62523574 ps
CPU time 1.26 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 217356 kb
Host smart-902f9a22-2cca-4e90-b8b1-d1dc73cc618b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14579382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.14579382
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.852774994
Short name T229
Test name
Test status
Simulation time 115718170 ps
CPU time 1.26 seconds
Started Aug 08 07:44:44 PM PDT 24
Finished Aug 08 07:44:45 PM PDT 24
Peak memory 218508 kb
Host smart-885cd76b-0b5f-44c9-85bb-5c0fa9155cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852774994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.852774994
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.3728043801
Short name T698
Test name
Test status
Simulation time 32778932 ps
CPU time 1.03 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:45 PM PDT 24
Peak memory 220172 kb
Host smart-fb04eb0a-e7e0-4cba-8a74-f2b9e445089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728043801 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3728043801
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1244278503
Short name T422
Test name
Test status
Simulation time 86825417 ps
CPU time 2.87 seconds
Started Aug 08 07:44:49 PM PDT 24
Finished Aug 08 07:44:52 PM PDT 24
Peak memory 220180 kb
Host smart-43dce815-6ee0-44c3-a442-d5cf679cbac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244278503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1244278503
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.4249839249
Short name T973
Test name
Test status
Simulation time 27418804 ps
CPU time 1.33 seconds
Started Aug 08 07:44:40 PM PDT 24
Finished Aug 08 07:44:42 PM PDT 24
Peak memory 219744 kb
Host smart-b041b682-5aea-4dc9-bb72-58806454260e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249839249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.4249839249
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2246759264
Short name T126
Test name
Test status
Simulation time 56915951 ps
CPU time 1 seconds
Started Aug 08 07:44:44 PM PDT 24
Finished Aug 08 07:44:45 PM PDT 24
Peak memory 220724 kb
Host smart-83605bee-b6ca-42e0-a9fb-4c1b546085e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246759264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2246759264
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.894303371
Short name T436
Test name
Test status
Simulation time 88620376 ps
CPU time 1.31 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 220144 kb
Host smart-778c4bc2-c83e-4cce-803a-ca21189c60c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894303371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.894303371
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3621450558
Short name T821
Test name
Test status
Simulation time 36190958 ps
CPU time 1.11 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:43 PM PDT 24
Peak memory 218656 kb
Host smart-0a82e6e2-7054-4efd-87e1-b7617100c3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621450558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3621450558
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.4136655767
Short name T787
Test name
Test status
Simulation time 19001359 ps
CPU time 1.08 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 218940 kb
Host smart-b1033429-be6e-40cd-a5ba-fdb657255d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136655767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.4136655767
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.306569229
Short name T342
Test name
Test status
Simulation time 60420156 ps
CPU time 1.28 seconds
Started Aug 08 07:44:41 PM PDT 24
Finished Aug 08 07:44:42 PM PDT 24
Peak memory 218824 kb
Host smart-12aba9a7-c24f-47da-8a7c-b37ba673fd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306569229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.306569229
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3872522276
Short name T885
Test name
Test status
Simulation time 87663040 ps
CPU time 1.25 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:45 PM PDT 24
Peak memory 218464 kb
Host smart-2d5273d7-abc2-49dd-b8e3-165592015026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872522276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3872522276
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.3399595125
Short name T178
Test name
Test status
Simulation time 29284533 ps
CPU time 1.2 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:45 PM PDT 24
Peak memory 219880 kb
Host smart-bbed58d0-ced0-477d-a72c-855633016c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399595125 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3399595125
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3553382969
Short name T485
Test name
Test status
Simulation time 62169036 ps
CPU time 1.24 seconds
Started Aug 08 07:44:41 PM PDT 24
Finished Aug 08 07:44:42 PM PDT 24
Peak memory 217584 kb
Host smart-1d7638fd-4beb-4f7d-998f-946b0bea870d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553382969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3553382969
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.4117132290
Short name T318
Test name
Test status
Simulation time 59225246 ps
CPU time 1.07 seconds
Started Aug 08 07:44:46 PM PDT 24
Finished Aug 08 07:44:47 PM PDT 24
Peak memory 219508 kb
Host smart-991c4843-22e0-4e49-a3da-9236abf50c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117132290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.4117132290
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3977589804
Short name T917
Test name
Test status
Simulation time 38194362 ps
CPU time 1.28 seconds
Started Aug 08 07:44:40 PM PDT 24
Finished Aug 08 07:44:42 PM PDT 24
Peak memory 225752 kb
Host smart-7375a9a9-4571-4d80-ae62-2be4221627bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977589804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3977589804
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.48730096
Short name T21
Test name
Test status
Simulation time 657265456 ps
CPU time 3.38 seconds
Started Aug 08 07:44:41 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 219808 kb
Host smart-4f5031f3-793b-47a7-93be-20a2e390e400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48730096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.48730096
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.803499523
Short name T476
Test name
Test status
Simulation time 41640580 ps
CPU time 1.15 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 219640 kb
Host smart-86e74460-de80-4dc5-b5e9-bdacc37c3081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803499523 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.803499523
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.666704236
Short name T8
Test name
Test status
Simulation time 33870503 ps
CPU time 0.92 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 220116 kb
Host smart-34c555fc-db65-4fcc-81f5-ef0ee88a7619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666704236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.666704236
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3472291054
Short name T678
Test name
Test status
Simulation time 54762643 ps
CPU time 1.63 seconds
Started Aug 08 07:44:48 PM PDT 24
Finished Aug 08 07:44:50 PM PDT 24
Peak memory 218792 kb
Host smart-0de00ca6-118a-484b-aade-d8be7ecf1561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472291054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3472291054
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2589573344
Short name T790
Test name
Test status
Simulation time 49037090 ps
CPU time 1.22 seconds
Started Aug 08 07:43:32 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 218284 kb
Host smart-f2706fc6-7bc8-4128-91b8-62f82001b856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589573344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2589573344
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.538395444
Short name T655
Test name
Test status
Simulation time 40942370 ps
CPU time 0.99 seconds
Started Aug 08 07:43:23 PM PDT 24
Finished Aug 08 07:43:24 PM PDT 24
Peak memory 215228 kb
Host smart-6f56cb0d-c794-480a-bba5-8e62f1693f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538395444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.538395444
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1046531340
Short name T633
Test name
Test status
Simulation time 31940823 ps
CPU time 0.84 seconds
Started Aug 08 07:43:25 PM PDT 24
Finished Aug 08 07:43:26 PM PDT 24
Peak memory 216508 kb
Host smart-b58133a2-c2d1-4982-bc73-0222fb561045
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046531340 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1046531340
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2925236737
Short name T88
Test name
Test status
Simulation time 84496723 ps
CPU time 1.14 seconds
Started Aug 08 07:43:29 PM PDT 24
Finished Aug 08 07:43:30 PM PDT 24
Peak memory 217032 kb
Host smart-e92f07d0-9f3b-4b2d-899e-cb9ef0c3e7e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925236737 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2925236737
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.4068660287
Short name T195
Test name
Test status
Simulation time 34999666 ps
CPU time 0.95 seconds
Started Aug 08 07:43:23 PM PDT 24
Finished Aug 08 07:43:24 PM PDT 24
Peak memory 223952 kb
Host smart-1df2f7e5-6195-4af9-a671-b05b5b82ee6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068660287 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.4068660287
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.407088267
Short name T420
Test name
Test status
Simulation time 114202998 ps
CPU time 1.33 seconds
Started Aug 08 07:43:40 PM PDT 24
Finished Aug 08 07:43:41 PM PDT 24
Peak memory 217592 kb
Host smart-0ae5b6c6-e1bd-4a09-be65-befbc9cffa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407088267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.407088267
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.632206318
Short name T537
Test name
Test status
Simulation time 21979446 ps
CPU time 1.07 seconds
Started Aug 08 07:43:29 PM PDT 24
Finished Aug 08 07:43:30 PM PDT 24
Peak memory 215416 kb
Host smart-4d59c46f-490b-49d9-ba77-537fa60fbb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632206318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.632206318
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.3186353913
Short name T95
Test name
Test status
Simulation time 25428544 ps
CPU time 0.99 seconds
Started Aug 08 07:43:23 PM PDT 24
Finished Aug 08 07:43:25 PM PDT 24
Peak memory 215324 kb
Host smart-5b759106-ecd8-49c4-a6e4-9d675b5c0836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186353913 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3186353913
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.855555006
Short name T250
Test name
Test status
Simulation time 190724582 ps
CPU time 2.41 seconds
Started Aug 08 07:43:26 PM PDT 24
Finished Aug 08 07:43:29 PM PDT 24
Peak memory 217252 kb
Host smart-5cab90f1-74fd-41ac-9aef-37e984f38f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855555006 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.855555006
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2225350175
Short name T754
Test name
Test status
Simulation time 53966586828 ps
CPU time 1203.67 seconds
Started Aug 08 07:43:24 PM PDT 24
Finished Aug 08 08:03:27 PM PDT 24
Peak memory 220348 kb
Host smart-b01e43c3-b79b-48e6-b5fd-46f21a85b6cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225350175 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2225350175
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1732537754
Short name T180
Test name
Test status
Simulation time 27813653 ps
CPU time 1.17 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 219572 kb
Host smart-a89eb1c2-5e8f-48db-8910-324d7368bcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732537754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1732537754
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.2999209614
Short name T219
Test name
Test status
Simulation time 31825962 ps
CPU time 0.86 seconds
Started Aug 08 07:44:41 PM PDT 24
Finished Aug 08 07:44:41 PM PDT 24
Peak memory 218848 kb
Host smart-3ca21632-bc7a-40c7-b690-d5f04fdda992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999209614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2999209614
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1808777848
Short name T504
Test name
Test status
Simulation time 50607185 ps
CPU time 1.22 seconds
Started Aug 08 07:44:45 PM PDT 24
Finished Aug 08 07:44:46 PM PDT 24
Peak memory 215376 kb
Host smart-96f60f5a-3ae2-4566-82e4-0422fa96e0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808777848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1808777848
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1215253072
Short name T592
Test name
Test status
Simulation time 27584129 ps
CPU time 1.32 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 219708 kb
Host smart-d3f0e5c8-d0c9-4942-9d08-277f2e9f1963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215253072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1215253072
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2959723695
Short name T635
Test name
Test status
Simulation time 28580623 ps
CPU time 0.88 seconds
Started Aug 08 07:44:48 PM PDT 24
Finished Aug 08 07:44:49 PM PDT 24
Peak memory 215340 kb
Host smart-1fe5271d-d318-4ece-84c2-3d6487b02ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959723695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2959723695
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.460881672
Short name T994
Test name
Test status
Simulation time 48025417 ps
CPU time 1.4 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 217268 kb
Host smart-4b21d97a-0ac0-4e9c-a74a-7eee45df52c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460881672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.460881672
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1358783957
Short name T174
Test name
Test status
Simulation time 19163667 ps
CPU time 1.05 seconds
Started Aug 08 07:44:48 PM PDT 24
Finished Aug 08 07:44:49 PM PDT 24
Peak memory 218896 kb
Host smart-4f461193-aca4-4d4e-9339-7390f7232c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358783957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1358783957
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2140206763
Short name T360
Test name
Test status
Simulation time 98454277 ps
CPU time 1.1 seconds
Started Aug 08 07:44:46 PM PDT 24
Finished Aug 08 07:44:47 PM PDT 24
Peak memory 217364 kb
Host smart-03417bdc-2635-4c77-a76c-cca69df4783e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140206763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2140206763
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.613646370
Short name T314
Test name
Test status
Simulation time 29569109 ps
CPU time 1.08 seconds
Started Aug 08 07:44:46 PM PDT 24
Finished Aug 08 07:44:47 PM PDT 24
Peak memory 218600 kb
Host smart-8cb8fe22-6293-43f4-b512-723ef971526e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613646370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.613646370
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.2313792629
Short name T767
Test name
Test status
Simulation time 18121171 ps
CPU time 1 seconds
Started Aug 08 07:44:46 PM PDT 24
Finished Aug 08 07:44:47 PM PDT 24
Peak memory 218940 kb
Host smart-98264600-e0a0-457b-b069-b9ad4f02cec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313792629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2313792629
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3495184679
Short name T755
Test name
Test status
Simulation time 48863450 ps
CPU time 1.74 seconds
Started Aug 08 07:44:47 PM PDT 24
Finished Aug 08 07:44:49 PM PDT 24
Peak memory 220212 kb
Host smart-5404713e-9981-40f5-9663-fb667670e842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495184679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3495184679
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.872586733
Short name T315
Test name
Test status
Simulation time 101856049 ps
CPU time 1.27 seconds
Started Aug 08 07:44:44 PM PDT 24
Finished Aug 08 07:44:46 PM PDT 24
Peak memory 215560 kb
Host smart-1a06a17b-adcd-4de9-a51a-857a568a2131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872586733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.872586733
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3744868952
Short name T664
Test name
Test status
Simulation time 23987681 ps
CPU time 0.96 seconds
Started Aug 08 07:44:45 PM PDT 24
Finished Aug 08 07:44:47 PM PDT 24
Peak memory 219080 kb
Host smart-7b63d4dc-8ede-42c4-97a9-9ec7201382a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744868952 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3744868952
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.158748250
Short name T331
Test name
Test status
Simulation time 120342907 ps
CPU time 1.39 seconds
Started Aug 08 07:44:44 PM PDT 24
Finished Aug 08 07:44:46 PM PDT 24
Peak memory 218800 kb
Host smart-f1fb7fcb-afe9-4a0b-b9bb-15504bf96c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158748250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.158748250
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3694506705
Short name T161
Test name
Test status
Simulation time 27029313 ps
CPU time 1 seconds
Started Aug 08 07:44:40 PM PDT 24
Finished Aug 08 07:44:41 PM PDT 24
Peak memory 220000 kb
Host smart-d5b88f3d-3ea7-4184-8b04-262974b7b58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694506705 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3694506705
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1691730214
Short name T390
Test name
Test status
Simulation time 37966506 ps
CPU time 1.53 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:43 PM PDT 24
Peak memory 218704 kb
Host smart-8e1da4ec-35cb-40c9-8388-99651d46afe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691730214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1691730214
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.2283789600
Short name T167
Test name
Test status
Simulation time 74331792 ps
CPU time 1.1 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 219956 kb
Host smart-22cde60a-6c63-4c8a-a674-18fc7a35175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283789600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2283789600
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3772831638
Short name T830
Test name
Test status
Simulation time 52898970 ps
CPU time 2.24 seconds
Started Aug 08 07:44:44 PM PDT 24
Finished Aug 08 07:44:46 PM PDT 24
Peak memory 215344 kb
Host smart-a9117f6a-629f-45fe-bda4-44c9f299487f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772831638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3772831638
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.235637744
Short name T763
Test name
Test status
Simulation time 30308977 ps
CPU time 1.26 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 215600 kb
Host smart-72900d51-69c3-432c-bbb5-9fbb7d5bcb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235637744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.235637744
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1071930359
Short name T208
Test name
Test status
Simulation time 47195028 ps
CPU time 0.86 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:43 PM PDT 24
Peak memory 218764 kb
Host smart-57287f0e-6fa3-4caa-a297-cf7064d9aa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071930359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1071930359
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1345376225
Short name T858
Test name
Test status
Simulation time 26552302 ps
CPU time 1.03 seconds
Started Aug 08 07:44:41 PM PDT 24
Finished Aug 08 07:44:43 PM PDT 24
Peak memory 217688 kb
Host smart-1905095a-4e7b-4e02-b32c-c3fbc511622e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345376225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1345376225
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.2589167914
Short name T144
Test name
Test status
Simulation time 26995947 ps
CPU time 1.22 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:43 PM PDT 24
Peak memory 218656 kb
Host smart-c423b2de-7d3c-4a8b-944e-1bfd48b272ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589167914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.2589167914
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1656638613
Short name T582
Test name
Test status
Simulation time 31775175 ps
CPU time 0.92 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 219044 kb
Host smart-057badf6-e570-4e8a-8f14-71bb59fed783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656638613 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1656638613
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2805720003
Short name T914
Test name
Test status
Simulation time 33793586 ps
CPU time 1.18 seconds
Started Aug 08 07:44:41 PM PDT 24
Finished Aug 08 07:44:43 PM PDT 24
Peak memory 217260 kb
Host smart-883e2d54-97f8-4d25-8fd4-f2ff6dc40b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805720003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2805720003
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1392844279
Short name T667
Test name
Test status
Simulation time 43388879 ps
CPU time 1.12 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 218916 kb
Host smart-a9fb5d31-ae62-49f5-9e6c-1c5130912cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392844279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1392844279
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2733520160
Short name T776
Test name
Test status
Simulation time 37377150 ps
CPU time 1.19 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:43 PM PDT 24
Peak memory 232376 kb
Host smart-35c2bd13-3f70-4e2e-b045-b39c45922250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733520160 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2733520160
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3269708286
Short name T114
Test name
Test status
Simulation time 36398960 ps
CPU time 1.45 seconds
Started Aug 08 07:44:45 PM PDT 24
Finished Aug 08 07:44:47 PM PDT 24
Peak memory 218740 kb
Host smart-800998cc-5ada-4803-8200-d3e25e7bf171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269708286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3269708286
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3865768949
Short name T856
Test name
Test status
Simulation time 23665056 ps
CPU time 1.14 seconds
Started Aug 08 07:43:22 PM PDT 24
Finished Aug 08 07:43:23 PM PDT 24
Peak memory 218512 kb
Host smart-9eac5941-6c47-4061-a671-0e71abf7371a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865768949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3865768949
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1671498743
Short name T397
Test name
Test status
Simulation time 18058809 ps
CPU time 0.93 seconds
Started Aug 08 07:43:30 PM PDT 24
Finished Aug 08 07:43:31 PM PDT 24
Peak memory 215168 kb
Host smart-fefeb837-e775-4403-aa9a-9d3fa08691db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671498743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1671498743
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.608885581
Short name T779
Test name
Test status
Simulation time 13834858 ps
CPU time 0.95 seconds
Started Aug 08 07:43:24 PM PDT 24
Finished Aug 08 07:43:25 PM PDT 24
Peak memory 216712 kb
Host smart-e8d1876c-9747-4cdc-93f9-45adcfee72ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608885581 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.608885581
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.250761135
Short name T472
Test name
Test status
Simulation time 41946870 ps
CPU time 1.21 seconds
Started Aug 08 07:43:28 PM PDT 24
Finished Aug 08 07:43:30 PM PDT 24
Peak memory 218624 kb
Host smart-abb8f80e-c4fb-451a-afcf-bd52bcb70f58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250761135 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.250761135
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.4142565422
Short name T55
Test name
Test status
Simulation time 73114528 ps
CPU time 1.22 seconds
Started Aug 08 07:43:29 PM PDT 24
Finished Aug 08 07:43:31 PM PDT 24
Peak memory 225988 kb
Host smart-03193094-1909-4ab5-970b-eea98fc6d2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142565422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.4142565422
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.954915394
Short name T876
Test name
Test status
Simulation time 38145512 ps
CPU time 1.16 seconds
Started Aug 08 07:43:23 PM PDT 24
Finished Aug 08 07:43:24 PM PDT 24
Peak memory 218808 kb
Host smart-0527db74-f7d1-4db8-87ee-b9600ea5c7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954915394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.954915394
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1233117220
Short name T733
Test name
Test status
Simulation time 26840874 ps
CPU time 1.02 seconds
Started Aug 08 07:43:30 PM PDT 24
Finished Aug 08 07:43:32 PM PDT 24
Peak memory 224156 kb
Host smart-82e6ff88-b2ba-405d-a9f8-adeddd7d8a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233117220 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1233117220
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2843296631
Short name T675
Test name
Test status
Simulation time 14030101 ps
CPU time 0.95 seconds
Started Aug 08 07:43:24 PM PDT 24
Finished Aug 08 07:43:25 PM PDT 24
Peak memory 207132 kb
Host smart-d62560e1-7513-4199-815a-2ea69cef46bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843296631 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2843296631
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1921100010
Short name T474
Test name
Test status
Simulation time 29180199 ps
CPU time 0.99 seconds
Started Aug 08 07:43:31 PM PDT 24
Finished Aug 08 07:43:32 PM PDT 24
Peak memory 215264 kb
Host smart-f3ad5417-5981-418d-9de8-f115e77df264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921100010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1921100010
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1594240807
Short name T761
Test name
Test status
Simulation time 416860786 ps
CPU time 4.2 seconds
Started Aug 08 07:43:30 PM PDT 24
Finished Aug 08 07:43:35 PM PDT 24
Peak memory 217428 kb
Host smart-335081f4-0cf5-47a4-bdbd-a747175cecba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594240807 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1594240807
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3399234795
Short name T401
Test name
Test status
Simulation time 32381482978 ps
CPU time 840.83 seconds
Started Aug 08 07:43:30 PM PDT 24
Finished Aug 08 07:57:31 PM PDT 24
Peak memory 223668 kb
Host smart-c6e1ee45-f765-4dae-911d-187b5626fd5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399234795 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3399234795
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2455633172
Short name T656
Test name
Test status
Simulation time 101801423 ps
CPU time 1.31 seconds
Started Aug 08 07:44:47 PM PDT 24
Finished Aug 08 07:44:48 PM PDT 24
Peak memory 221600 kb
Host smart-fa9f6958-a43e-49a0-b9b3-b3efa5d37286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455633172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2455633172
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1779711528
Short name T146
Test name
Test status
Simulation time 32746054 ps
CPU time 1.16 seconds
Started Aug 08 07:44:44 PM PDT 24
Finished Aug 08 07:44:45 PM PDT 24
Peak memory 220860 kb
Host smart-cac77ed8-9f08-4392-aa56-51def4e7b3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779711528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1779711528
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1714173422
Short name T586
Test name
Test status
Simulation time 90088765 ps
CPU time 1.31 seconds
Started Aug 08 07:44:43 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 219004 kb
Host smart-4dd456f4-b680-4b8c-8395-6ba0d77e7f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714173422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1714173422
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.1770114630
Short name T125
Test name
Test status
Simulation time 85450067 ps
CPU time 1.22 seconds
Started Aug 08 07:44:44 PM PDT 24
Finished Aug 08 07:44:45 PM PDT 24
Peak memory 219256 kb
Host smart-87c45464-99cc-4f93-a68a-f2bc970ed445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770114630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.1770114630
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2704638701
Short name T109
Test name
Test status
Simulation time 33178355 ps
CPU time 0.9 seconds
Started Aug 08 07:44:44 PM PDT 24
Finished Aug 08 07:44:45 PM PDT 24
Peak memory 217232 kb
Host smart-4798c9e4-09e0-491d-b4e1-dda6cc9d2524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704638701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2704638701
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1030980806
Short name T663
Test name
Test status
Simulation time 43574909 ps
CPU time 1.16 seconds
Started Aug 08 07:44:48 PM PDT 24
Finished Aug 08 07:44:50 PM PDT 24
Peak memory 217400 kb
Host smart-d935a5b5-1503-4d6e-a75e-49eea0f5de17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030980806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1030980806
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.834414717
Short name T941
Test name
Test status
Simulation time 48529452 ps
CPU time 1.27 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 218132 kb
Host smart-df84491d-5a3b-47d2-bfa3-94f11e67cc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834414717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.834414717
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.4076442116
Short name T204
Test name
Test status
Simulation time 24196999 ps
CPU time 0.89 seconds
Started Aug 08 07:44:41 PM PDT 24
Finished Aug 08 07:44:42 PM PDT 24
Peak memory 218872 kb
Host smart-5b7a8752-b902-471d-8217-58a18ccf924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076442116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.4076442116
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3488673068
Short name T41
Test name
Test status
Simulation time 43144915 ps
CPU time 1.34 seconds
Started Aug 08 07:44:49 PM PDT 24
Finished Aug 08 07:44:50 PM PDT 24
Peak memory 218600 kb
Host smart-739a5fb3-2e09-4514-b4f1-392fda46110d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488673068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3488673068
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.1842060838
Short name T682
Test name
Test status
Simulation time 24778380 ps
CPU time 1.2 seconds
Started Aug 08 07:44:44 PM PDT 24
Finished Aug 08 07:44:45 PM PDT 24
Peak memory 214036 kb
Host smart-d752269c-3cf9-47a9-95b2-d7fed367197a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842060838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.1842060838
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.4136073523
Short name T14
Test name
Test status
Simulation time 74044151 ps
CPU time 1.21 seconds
Started Aug 08 07:44:49 PM PDT 24
Finished Aug 08 07:44:51 PM PDT 24
Peak memory 225984 kb
Host smart-b0b531f8-dc56-4251-aebc-d7bc0ed54eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136073523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.4136073523
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1894416135
Short name T542
Test name
Test status
Simulation time 52833954 ps
CPU time 1.91 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 218836 kb
Host smart-0f4a5361-7d1b-4034-9e02-2d700bbc4b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894416135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1894416135
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.265911205
Short name T806
Test name
Test status
Simulation time 24760881 ps
CPU time 1.3 seconds
Started Aug 08 07:44:42 PM PDT 24
Finished Aug 08 07:44:44 PM PDT 24
Peak memory 220888 kb
Host smart-f155b70c-23a2-42eb-a42f-2576ccddaaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265911205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.265911205
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3267972056
Short name T622
Test name
Test status
Simulation time 24260373 ps
CPU time 0.93 seconds
Started Aug 08 07:44:52 PM PDT 24
Finished Aug 08 07:44:53 PM PDT 24
Peak memory 218896 kb
Host smart-6af1267a-c763-4387-b8f2-13e9b285f9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267972056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3267972056
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/75.edn_alert.3902671671
Short name T488
Test name
Test status
Simulation time 81783965 ps
CPU time 1.2 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 220776 kb
Host smart-8ff7d3b3-6f2e-42d7-89cc-155f4e8c2f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902671671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.3902671671
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.145163339
Short name T58
Test name
Test status
Simulation time 22760889 ps
CPU time 1.14 seconds
Started Aug 08 07:44:50 PM PDT 24
Finished Aug 08 07:44:52 PM PDT 24
Peak memory 229700 kb
Host smart-432a7390-3428-4d20-a207-f2a959a74c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145163339 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.145163339
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1891755006
Short name T897
Test name
Test status
Simulation time 27249548 ps
CPU time 1.26 seconds
Started Aug 08 07:44:52 PM PDT 24
Finished Aug 08 07:44:54 PM PDT 24
Peak memory 219684 kb
Host smart-29d83bed-ffa5-4b4c-89c9-c1748c9a065c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891755006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1891755006
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1337971330
Short name T298
Test name
Test status
Simulation time 26036475 ps
CPU time 1.26 seconds
Started Aug 08 07:44:52 PM PDT 24
Finished Aug 08 07:44:54 PM PDT 24
Peak memory 219432 kb
Host smart-8fb57913-b3cb-443f-9aae-6fc372a060df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337971330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1337971330
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.921412181
Short name T194
Test name
Test status
Simulation time 37847548 ps
CPU time 0.85 seconds
Started Aug 08 07:44:51 PM PDT 24
Finished Aug 08 07:44:52 PM PDT 24
Peak memory 218532 kb
Host smart-2448d04a-7338-4243-8dd0-dc99890bc468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921412181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.921412181
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2978448836
Short name T3
Test name
Test status
Simulation time 74876039 ps
CPU time 1.38 seconds
Started Aug 08 07:44:51 PM PDT 24
Finished Aug 08 07:44:52 PM PDT 24
Peak memory 218920 kb
Host smart-e9d59d43-1c2f-4a6b-92f2-5aa32af64fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978448836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2978448836
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.3320211624
Short name T909
Test name
Test status
Simulation time 25117420 ps
CPU time 1.18 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 219608 kb
Host smart-8a3a8ecb-c2d7-44c3-be7d-3c18317062e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320211624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3320211624
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.1096198325
Short name T922
Test name
Test status
Simulation time 24158516 ps
CPU time 1.21 seconds
Started Aug 08 07:44:50 PM PDT 24
Finished Aug 08 07:44:52 PM PDT 24
Peak memory 224092 kb
Host smart-e1ccfe11-669b-492f-8359-4cbe7947aa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096198325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1096198325
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.4002507770
Short name T116
Test name
Test status
Simulation time 77339634 ps
CPU time 1.41 seconds
Started Aug 08 07:44:52 PM PDT 24
Finished Aug 08 07:44:53 PM PDT 24
Peak memory 219120 kb
Host smart-4b243404-19c2-4ff4-a041-02c794673488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002507770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.4002507770
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3775699528
Short name T140
Test name
Test status
Simulation time 86834610 ps
CPU time 1.17 seconds
Started Aug 08 07:44:49 PM PDT 24
Finished Aug 08 07:44:50 PM PDT 24
Peak memory 219496 kb
Host smart-dc8a1ed6-9898-41a9-a0c2-5361fc094145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775699528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3775699528
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2179494111
Short name T599
Test name
Test status
Simulation time 47974950 ps
CPU time 1.15 seconds
Started Aug 08 07:44:51 PM PDT 24
Finished Aug 08 07:44:52 PM PDT 24
Peak memory 232420 kb
Host smart-63159428-bb0a-4f51-aa3e-99e6e5f1e54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179494111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2179494111
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3708706734
Short name T990
Test name
Test status
Simulation time 92022813 ps
CPU time 1.21 seconds
Started Aug 08 07:44:51 PM PDT 24
Finished Aug 08 07:44:52 PM PDT 24
Peak memory 218904 kb
Host smart-0b3c4dee-7b04-4526-aded-7356df76ad75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708706734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3708706734
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.855729046
Short name T789
Test name
Test status
Simulation time 102489271 ps
CPU time 1.32 seconds
Started Aug 08 07:44:52 PM PDT 24
Finished Aug 08 07:44:54 PM PDT 24
Peak memory 219788 kb
Host smart-d9d55b75-c1f7-4385-aed1-4bb1b283005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855729046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.855729046
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.470775946
Short name T57
Test name
Test status
Simulation time 31508141 ps
CPU time 1.16 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:54 PM PDT 24
Peak memory 224100 kb
Host smart-37d6ed74-3a46-458f-81d5-0ddf70f19fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470775946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.470775946
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1728087656
Short name T350
Test name
Test status
Simulation time 159674601 ps
CPU time 1.28 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 217576 kb
Host smart-0ad1d4b3-f148-4c07-9c10-76cd896619d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728087656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1728087656
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2902970622
Short name T225
Test name
Test status
Simulation time 232783369 ps
CPU time 1.21 seconds
Started Aug 08 07:43:25 PM PDT 24
Finished Aug 08 07:43:26 PM PDT 24
Peak memory 219200 kb
Host smart-3d5cf3a9-ba03-4595-af03-29c8d4ee86fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902970622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2902970622
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.50178908
Short name T963
Test name
Test status
Simulation time 54606991 ps
CPU time 0.95 seconds
Started Aug 08 07:43:24 PM PDT 24
Finished Aug 08 07:43:25 PM PDT 24
Peak memory 214992 kb
Host smart-e3253551-1470-401b-aa8f-49ed7ba95966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50178908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.50178908
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4051364948
Short name T170
Test name
Test status
Simulation time 114094813 ps
CPU time 0.9 seconds
Started Aug 08 07:43:32 PM PDT 24
Finished Aug 08 07:43:33 PM PDT 24
Peak memory 215380 kb
Host smart-631f472d-132e-44bd-a1de-b5f99c91c7db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051364948 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4051364948
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.366587313
Short name T760
Test name
Test status
Simulation time 59170384 ps
CPU time 1.05 seconds
Started Aug 08 07:43:23 PM PDT 24
Finished Aug 08 07:43:24 PM PDT 24
Peak memory 216976 kb
Host smart-4fd1c615-460a-4793-aaae-c0fdd3c07000
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366587313 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.366587313
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.684407153
Short name T168
Test name
Test status
Simulation time 30706232 ps
CPU time 1.33 seconds
Started Aug 08 07:43:22 PM PDT 24
Finished Aug 08 07:43:24 PM PDT 24
Peak memory 225932 kb
Host smart-8985ed55-24ba-4517-a7d6-20a8a6287294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684407153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.684407153
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2091571398
Short name T696
Test name
Test status
Simulation time 31569391 ps
CPU time 1.26 seconds
Started Aug 08 07:43:23 PM PDT 24
Finished Aug 08 07:43:25 PM PDT 24
Peak memory 218520 kb
Host smart-d8a9ba44-2b2b-4638-bfbb-e7a4c0f09152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091571398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2091571398
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3391327894
Short name T517
Test name
Test status
Simulation time 22876970 ps
CPU time 0.95 seconds
Started Aug 08 07:43:22 PM PDT 24
Finished Aug 08 07:43:23 PM PDT 24
Peak memory 216220 kb
Host smart-61126432-ae38-435b-8eb0-c04d835a8fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391327894 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3391327894
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.4090892921
Short name T628
Test name
Test status
Simulation time 114590448 ps
CPU time 0.93 seconds
Started Aug 08 07:43:24 PM PDT 24
Finished Aug 08 07:43:25 PM PDT 24
Peak memory 207092 kb
Host smart-85041f9c-5b0d-45c5-90ae-f93b3a2a2abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090892921 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.4090892921
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1803847030
Short name T671
Test name
Test status
Simulation time 19085875 ps
CPU time 1.1 seconds
Started Aug 08 07:43:40 PM PDT 24
Finished Aug 08 07:43:42 PM PDT 24
Peak memory 215352 kb
Host smart-405fe6a1-acea-4264-b00e-5b4355cd0ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803847030 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1803847030
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3210335760
Short name T738
Test name
Test status
Simulation time 146600992 ps
CPU time 2.03 seconds
Started Aug 08 07:43:24 PM PDT 24
Finished Aug 08 07:43:26 PM PDT 24
Peak memory 215260 kb
Host smart-78becd81-b4a8-40e3-b27f-573d65bbd9d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210335760 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3210335760
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3023094137
Short name T477
Test name
Test status
Simulation time 36367717404 ps
CPU time 465.86 seconds
Started Aug 08 07:43:23 PM PDT 24
Finished Aug 08 07:51:09 PM PDT 24
Peak memory 223620 kb
Host smart-50c7cb83-5ab1-4b0f-bec3-d0ec005820d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023094137 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3023094137
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.3883247537
Short name T729
Test name
Test status
Simulation time 261866010 ps
CPU time 1.22 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 219536 kb
Host smart-d141281e-818d-4251-a957-e4a0bfd15536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883247537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3883247537
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1122639428
Short name T825
Test name
Test status
Simulation time 136372896 ps
CPU time 1.05 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:54 PM PDT 24
Peak memory 220056 kb
Host smart-a6d294fb-0586-4319-a94e-31d03a143c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122639428 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1122639428
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.4015328886
Short name T61
Test name
Test status
Simulation time 72618469 ps
CPU time 1.06 seconds
Started Aug 08 07:44:50 PM PDT 24
Finished Aug 08 07:44:51 PM PDT 24
Peak memory 217588 kb
Host smart-27e43801-bcb9-4dc2-834b-8d323d4c7677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015328886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4015328886
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2650425296
Short name T844
Test name
Test status
Simulation time 42724685 ps
CPU time 1.08 seconds
Started Aug 08 07:44:49 PM PDT 24
Finished Aug 08 07:44:50 PM PDT 24
Peak memory 218472 kb
Host smart-9446cad1-ee0b-44ca-8968-c48c2c0bb8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650425296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2650425296
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1908086420
Short name T820
Test name
Test status
Simulation time 18680729 ps
CPU time 0.99 seconds
Started Aug 08 07:44:51 PM PDT 24
Finished Aug 08 07:44:52 PM PDT 24
Peak memory 218820 kb
Host smart-a32382ee-46a0-4dab-8239-9bee2f7a5a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908086420 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1908086420
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1094130112
Short name T378
Test name
Test status
Simulation time 53176529 ps
CPU time 1.36 seconds
Started Aug 08 07:44:52 PM PDT 24
Finished Aug 08 07:44:53 PM PDT 24
Peak memory 218716 kb
Host smart-1ca31291-0915-441f-921c-363a633bcf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094130112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1094130112
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3149503385
Short name T192
Test name
Test status
Simulation time 31312326 ps
CPU time 1.38 seconds
Started Aug 08 07:44:51 PM PDT 24
Finished Aug 08 07:44:53 PM PDT 24
Peak memory 215632 kb
Host smart-d78ee45d-6d0b-4eef-9160-8bdfb6b1a89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149503385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3149503385
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3700255516
Short name T887
Test name
Test status
Simulation time 21208783 ps
CPU time 0.92 seconds
Started Aug 08 07:44:50 PM PDT 24
Finished Aug 08 07:44:51 PM PDT 24
Peak memory 218776 kb
Host smart-a7a5e2be-e7ae-4e78-839b-271fe852447f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700255516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3700255516
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3576490399
Short name T550
Test name
Test status
Simulation time 25055311 ps
CPU time 1.28 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:54 PM PDT 24
Peak memory 217192 kb
Host smart-111fa3db-8c63-4bcd-9e34-70b097068380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576490399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3576490399
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.322863189
Short name T800
Test name
Test status
Simulation time 45424269 ps
CPU time 1.22 seconds
Started Aug 08 07:44:54 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 220152 kb
Host smart-1422aef6-7ea9-4c24-aa62-505aa4a7565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322863189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.322863189
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2021699983
Short name T695
Test name
Test status
Simulation time 18747085 ps
CPU time 1.08 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:54 PM PDT 24
Peak memory 218592 kb
Host smart-ee12cb8b-d544-4909-8398-6868fca556db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021699983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2021699983
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2047443211
Short name T484
Test name
Test status
Simulation time 56381700 ps
CPU time 2.2 seconds
Started Aug 08 07:44:52 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 217580 kb
Host smart-69107216-a20f-4fb6-aa82-de84bd3810b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047443211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2047443211
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.3490918968
Short name T411
Test name
Test status
Simulation time 169808733 ps
CPU time 1.27 seconds
Started Aug 08 07:44:52 PM PDT 24
Finished Aug 08 07:44:53 PM PDT 24
Peak memory 220708 kb
Host smart-5448f4e6-3102-41a9-811c-d2fd0f3c9b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490918968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.3490918968
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2857643534
Short name T71
Test name
Test status
Simulation time 19679858 ps
CPU time 1.08 seconds
Started Aug 08 07:44:51 PM PDT 24
Finished Aug 08 07:44:52 PM PDT 24
Peak memory 218652 kb
Host smart-ac4ced44-ab70-4538-ac44-eb44b6e2fa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857643534 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2857643534
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2073678138
Short name T833
Test name
Test status
Simulation time 60523103 ps
CPU time 1.26 seconds
Started Aug 08 07:44:52 PM PDT 24
Finished Aug 08 07:44:54 PM PDT 24
Peak memory 217328 kb
Host smart-cb6cead8-c853-4017-8ac8-696d2e583851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073678138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2073678138
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2244802194
Short name T165
Test name
Test status
Simulation time 71069337 ps
CPU time 1.24 seconds
Started Aug 08 07:44:54 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 219652 kb
Host smart-5f178a39-8637-4260-9c61-ac85b6c1f4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244802194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2244802194
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.389412208
Short name T834
Test name
Test status
Simulation time 22985560 ps
CPU time 0.93 seconds
Started Aug 08 07:44:52 PM PDT 24
Finished Aug 08 07:44:53 PM PDT 24
Peak memory 218720 kb
Host smart-79635429-9438-4d4f-a9c0-e251b2297c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389412208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.389412208
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2335260016
Short name T839
Test name
Test status
Simulation time 98502112 ps
CPU time 1.27 seconds
Started Aug 08 07:44:52 PM PDT 24
Finished Aug 08 07:44:54 PM PDT 24
Peak memory 218832 kb
Host smart-f8195e05-d1f5-40c5-a8af-e4b1a229d85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335260016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2335260016
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1578193479
Short name T263
Test name
Test status
Simulation time 48005746 ps
CPU time 1.21 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 219400 kb
Host smart-e9c474ed-0bb6-460a-b7d4-1d4cb08c460f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578193479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1578193479
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2226875185
Short name T882
Test name
Test status
Simulation time 18583346 ps
CPU time 1.22 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 224200 kb
Host smart-313f676c-d0a5-413d-9a18-89824548dfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226875185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2226875185
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2901124543
Short name T936
Test name
Test status
Simulation time 65099452 ps
CPU time 1.35 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 218424 kb
Host smart-5e47acfb-f5bd-4729-aeb6-0949ce557e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901124543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2901124543
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.4269452425
Short name T323
Test name
Test status
Simulation time 38530804 ps
CPU time 1.15 seconds
Started Aug 08 07:44:52 PM PDT 24
Finished Aug 08 07:44:53 PM PDT 24
Peak memory 219812 kb
Host smart-2ee8319b-7ba0-4510-96dd-fa599cdd1488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269452425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.4269452425
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2104464403
Short name T134
Test name
Test status
Simulation time 57448828 ps
CPU time 0.94 seconds
Started Aug 08 07:44:54 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 219776 kb
Host smart-2e045a21-e3e1-422f-badf-f04e0ff28c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104464403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2104464403
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3982782809
Short name T531
Test name
Test status
Simulation time 89166114 ps
CPU time 1.24 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:54 PM PDT 24
Peak memory 220128 kb
Host smart-2e85aa05-0c86-4714-89e9-0e675db497a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982782809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3982782809
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3843362344
Short name T160
Test name
Test status
Simulation time 50368750 ps
CPU time 1.27 seconds
Started Aug 08 07:44:54 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 218584 kb
Host smart-ff88c1fd-07bc-4f42-ba78-fea4263eb14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843362344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3843362344
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3395010453
Short name T933
Test name
Test status
Simulation time 20781547 ps
CPU time 0.97 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:54 PM PDT 24
Peak memory 218728 kb
Host smart-116883d1-7d57-4f39-aa73-b09ab67790a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395010453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3395010453
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3620811458
Short name T775
Test name
Test status
Simulation time 50961412 ps
CPU time 1.25 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 217380 kb
Host smart-1f4de6a0-e57d-4565-a2fa-bd40f19cbc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620811458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3620811458
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.3928281030
Short name T541
Test name
Test status
Simulation time 29635944 ps
CPU time 1.3 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 219824 kb
Host smart-cc7f8288-6213-4731-8fd6-2c1e70f8e62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928281030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3928281030
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_genbits.693903356
Short name T291
Test name
Test status
Simulation time 23284480 ps
CPU time 1.23 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 219876 kb
Host smart-f316193b-a670-4d35-90b7-e1987afd9b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693903356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.693903356
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1956040150
Short name T121
Test name
Test status
Simulation time 87139213 ps
CPU time 1.3 seconds
Started Aug 08 07:43:30 PM PDT 24
Finished Aug 08 07:43:32 PM PDT 24
Peak memory 218672 kb
Host smart-259a9ea7-a0fc-46b5-bab2-af6d4b90fd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956040150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1956040150
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1591065225
Short name T68
Test name
Test status
Simulation time 20041806 ps
CPU time 0.91 seconds
Started Aug 08 07:43:34 PM PDT 24
Finished Aug 08 07:43:35 PM PDT 24
Peak memory 206768 kb
Host smart-1d1a80c0-cc01-4ede-b494-6eb8219cf95f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591065225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1591065225
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2383870224
Short name T514
Test name
Test status
Simulation time 16260446 ps
CPU time 0.99 seconds
Started Aug 08 07:43:40 PM PDT 24
Finished Aug 08 07:43:41 PM PDT 24
Peak memory 216480 kb
Host smart-4207a139-1085-4e9a-95d3-deea379ec0c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383870224 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2383870224
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3084143235
Short name T138
Test name
Test status
Simulation time 38912453 ps
CPU time 1.23 seconds
Started Aug 08 07:43:36 PM PDT 24
Finished Aug 08 07:43:37 PM PDT 24
Peak memory 219488 kb
Host smart-14c4ac82-90a9-4973-a3be-a008a439c8a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084143235 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3084143235
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_genbits.2663020324
Short name T535
Test name
Test status
Simulation time 134935648 ps
CPU time 2.56 seconds
Started Aug 08 07:43:30 PM PDT 24
Finished Aug 08 07:43:32 PM PDT 24
Peak memory 219940 kb
Host smart-8fe14d3b-37cc-42dc-b552-3baa28c85721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663020324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2663020324
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1818220953
Short name T122
Test name
Test status
Simulation time 20399619 ps
CPU time 1.1 seconds
Started Aug 08 07:43:25 PM PDT 24
Finished Aug 08 07:43:26 PM PDT 24
Peak memory 216684 kb
Host smart-b054c6aa-e2f2-4fd9-96ae-23ba29728c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818220953 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1818220953
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1608977167
Short name T736
Test name
Test status
Simulation time 27748057 ps
CPU time 0.97 seconds
Started Aug 08 07:43:31 PM PDT 24
Finished Aug 08 07:43:32 PM PDT 24
Peak memory 207120 kb
Host smart-7f1f8882-4ced-434a-80c9-9b35af22f26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608977167 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1608977167
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3057834060
Short name T94
Test name
Test status
Simulation time 24446887 ps
CPU time 0.92 seconds
Started Aug 08 07:43:33 PM PDT 24
Finished Aug 08 07:43:34 PM PDT 24
Peak memory 215300 kb
Host smart-27bb9472-a472-49b2-b52d-ac66d8945318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057834060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3057834060
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2929256163
Short name T468
Test name
Test status
Simulation time 280518670 ps
CPU time 2.79 seconds
Started Aug 08 07:43:29 PM PDT 24
Finished Aug 08 07:43:32 PM PDT 24
Peak memory 217544 kb
Host smart-3f9a17bc-eb59-4e4d-ae88-3a1b4551ea16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929256163 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2929256163
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3668768135
Short name T836
Test name
Test status
Simulation time 77923078275 ps
CPU time 1015.01 seconds
Started Aug 08 07:43:30 PM PDT 24
Finished Aug 08 08:00:26 PM PDT 24
Peak memory 223584 kb
Host smart-7b2ba0c7-8083-4a62-bc16-78793cc6868f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668768135 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3668768135
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.1406276263
Short name T227
Test name
Test status
Simulation time 35906882 ps
CPU time 1.13 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:54 PM PDT 24
Peak memory 218496 kb
Host smart-d3df18a6-a498-41b0-bc8b-6e8f5d34611d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406276263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.1406276263
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1622161178
Short name T871
Test name
Test status
Simulation time 22873286 ps
CPU time 0.91 seconds
Started Aug 08 07:44:54 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 218672 kb
Host smart-2472034a-88ea-4b3e-8e84-91abb3afa177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622161178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1622161178
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1743944089
Short name T623
Test name
Test status
Simulation time 197897067 ps
CPU time 3.25 seconds
Started Aug 08 07:44:54 PM PDT 24
Finished Aug 08 07:44:58 PM PDT 24
Peak memory 220164 kb
Host smart-4b4cd265-a9a2-4186-819f-aee55a55ec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743944089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1743944089
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.4176654511
Short name T153
Test name
Test status
Simulation time 82778964 ps
CPU time 1.2 seconds
Started Aug 08 07:45:02 PM PDT 24
Finished Aug 08 07:45:03 PM PDT 24
Peak memory 220588 kb
Host smart-2693d8ff-494a-47e7-a878-1cf440641842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176654511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.4176654511
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2613358347
Short name T223
Test name
Test status
Simulation time 28636749 ps
CPU time 0.83 seconds
Started Aug 08 07:45:06 PM PDT 24
Finished Aug 08 07:45:07 PM PDT 24
Peak memory 218764 kb
Host smart-0e3b6b51-f121-4017-ba82-54c82a1c768c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613358347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2613358347
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1409479101
Short name T988
Test name
Test status
Simulation time 58369486 ps
CPU time 1.42 seconds
Started Aug 08 07:44:53 PM PDT 24
Finished Aug 08 07:44:55 PM PDT 24
Peak memory 220284 kb
Host smart-11158141-12e0-40a2-a1b5-f4173901db9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409479101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1409479101
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.1520458586
Short name T507
Test name
Test status
Simulation time 101899972 ps
CPU time 1.22 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:05 PM PDT 24
Peak memory 215620 kb
Host smart-84b2140f-0afa-4fe8-b9d5-53571809d117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520458586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.1520458586
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.4121077659
Short name T804
Test name
Test status
Simulation time 18176349 ps
CPU time 1.17 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:04 PM PDT 24
Peak memory 224304 kb
Host smart-25ca6f53-c9b0-46e9-adf9-0cb8cc2d3de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121077659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4121077659
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.976669926
Short name T694
Test name
Test status
Simulation time 34574456 ps
CPU time 1.36 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:06 PM PDT 24
Peak memory 218408 kb
Host smart-78260133-295f-4603-93f2-73c874a0882c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976669926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.976669926
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.3635641453
Short name T368
Test name
Test status
Simulation time 91706773 ps
CPU time 1.23 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:05 PM PDT 24
Peak memory 218960 kb
Host smart-e8277b52-dc1b-45bb-a15b-7c54da07db74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635641453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3635641453
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.320665689
Short name T780
Test name
Test status
Simulation time 20022564 ps
CPU time 1.06 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:07 PM PDT 24
Peak memory 218616 kb
Host smart-4f1b7ff3-a541-475b-b615-cd6f40e2557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320665689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.320665689
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2736123157
Short name T289
Test name
Test status
Simulation time 42442932 ps
CPU time 1.49 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:07 PM PDT 24
Peak memory 219896 kb
Host smart-a47bd55e-30a8-4c3f-a4cb-2a74e0abb579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736123157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2736123157
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1282423351
Short name T959
Test name
Test status
Simulation time 61755937 ps
CPU time 1.26 seconds
Started Aug 08 07:45:06 PM PDT 24
Finished Aug 08 07:45:07 PM PDT 24
Peak memory 215576 kb
Host smart-15347f68-fbb4-4c9d-bd07-578a5ca79a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282423351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1282423351
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1015764741
Short name T587
Test name
Test status
Simulation time 37010106 ps
CPU time 1.3 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:04 PM PDT 24
Peak memory 225856 kb
Host smart-344024b1-102c-49f6-bd63-5c4ee9bb2589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015764741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1015764741
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2519625344
Short name T697
Test name
Test status
Simulation time 47700480 ps
CPU time 1.54 seconds
Started Aug 08 07:45:08 PM PDT 24
Finished Aug 08 07:45:10 PM PDT 24
Peak memory 218412 kb
Host smart-ab3d93ac-9cfb-4bfb-8aa1-3577898c69d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519625344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2519625344
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2303222591
Short name T723
Test name
Test status
Simulation time 28216321 ps
CPU time 1.31 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:06 PM PDT 24
Peak memory 219584 kb
Host smart-21c865c8-07eb-45c8-99a9-1e3066e358df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303222591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2303222591
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.3074446563
Short name T441
Test name
Test status
Simulation time 53388333 ps
CPU time 1.05 seconds
Started Aug 08 07:45:07 PM PDT 24
Finished Aug 08 07:45:08 PM PDT 24
Peak memory 218964 kb
Host smart-70a5cafd-ed06-46b8-950d-8d34367c5a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074446563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3074446563
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.419477414
Short name T964
Test name
Test status
Simulation time 39373226 ps
CPU time 1.46 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:04 PM PDT 24
Peak memory 219772 kb
Host smart-23830920-64ab-42c4-8456-841bce194eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419477414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.419477414
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.1799288347
Short name T141
Test name
Test status
Simulation time 21607862 ps
CPU time 1.1 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:06 PM PDT 24
Peak memory 220112 kb
Host smart-08fe106f-7d2a-4aeb-b3a5-cc776c7c6f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799288347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1799288347
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2796467805
Short name T931
Test name
Test status
Simulation time 103695301 ps
CPU time 1.11 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:04 PM PDT 24
Peak memory 217368 kb
Host smart-f28a4e3b-cdd8-4282-a511-471fd838dd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796467805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2796467805
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.842579274
Short name T201
Test name
Test status
Simulation time 90649168 ps
CPU time 1.15 seconds
Started Aug 08 07:45:12 PM PDT 24
Finished Aug 08 07:45:13 PM PDT 24
Peak memory 219084 kb
Host smart-8e71b87c-5a5d-4e39-978f-3e482756373d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842579274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.842579274
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.169668225
Short name T135
Test name
Test status
Simulation time 66984077 ps
CPU time 1.12 seconds
Started Aug 08 07:45:04 PM PDT 24
Finished Aug 08 07:45:05 PM PDT 24
Peak memory 229844 kb
Host smart-d782d385-8583-4575-aa0c-c3aa59dff207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169668225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.169668225
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3236884541
Short name T634
Test name
Test status
Simulation time 31848400 ps
CPU time 1.38 seconds
Started Aug 08 07:45:04 PM PDT 24
Finished Aug 08 07:45:06 PM PDT 24
Peak memory 217340 kb
Host smart-8e325de5-ce94-416b-bec2-034e72887be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236884541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3236884541
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.1065511732
Short name T171
Test name
Test status
Simulation time 36383163 ps
CPU time 1.17 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:06 PM PDT 24
Peak memory 221440 kb
Host smart-c2c3eee7-a96e-443a-b65b-fec433ec93ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065511732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.1065511732
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1294264481
Short name T938
Test name
Test status
Simulation time 48792820 ps
CPU time 0.9 seconds
Started Aug 08 07:45:05 PM PDT 24
Finished Aug 08 07:45:06 PM PDT 24
Peak memory 220172 kb
Host smart-2b734027-d5bd-4e9c-b9c3-0bc1ffaaf3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294264481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1294264481
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2314892576
Short name T846
Test name
Test status
Simulation time 29841069 ps
CPU time 1.21 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:05 PM PDT 24
Peak memory 217504 kb
Host smart-cc98b826-1ac0-4a3e-a6ec-e94715f87d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314892576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2314892576
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1899678379
Short name T327
Test name
Test status
Simulation time 26506208 ps
CPU time 1.3 seconds
Started Aug 08 07:45:03 PM PDT 24
Finished Aug 08 07:45:05 PM PDT 24
Peak memory 219944 kb
Host smart-e929bf11-8998-4d85-89fd-2ffecd8a9955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899678379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1899678379
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.1241649264
Short name T864
Test name
Test status
Simulation time 50309444 ps
CPU time 1.1 seconds
Started Aug 08 07:45:04 PM PDT 24
Finished Aug 08 07:45:05 PM PDT 24
Peak memory 220816 kb
Host smart-65a539db-69a2-489c-83f9-ebce89c37f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241649264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1241649264
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.700491894
Short name T540
Test name
Test status
Simulation time 44939323 ps
CPU time 1.17 seconds
Started Aug 08 07:45:02 PM PDT 24
Finished Aug 08 07:45:04 PM PDT 24
Peak memory 217360 kb
Host smart-d62a4f49-0e74-4aef-9d3b-01c47608b290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700491894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.700491894
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%