Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.52 98.25 93.91 97.02 91.28 96.37 99.77 92.06


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T285 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3525419036 Aug 09 07:44:03 PM PDT 24 Aug 09 07:44:04 PM PDT 24 52535110 ps
T286 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3101966072 Aug 09 07:44:11 PM PDT 24 Aug 09 07:44:12 PM PDT 24 37642644 ps
T270 /workspace/coverage/cover_reg_top/15.edn_csr_rw.570748726 Aug 09 07:44:08 PM PDT 24 Aug 09 07:44:09 PM PDT 24 15205534 ps
T1021 /workspace/coverage/cover_reg_top/11.edn_intr_test.2759889724 Aug 09 07:44:05 PM PDT 24 Aug 09 07:44:06 PM PDT 24 11464957 ps
T1022 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2926630333 Aug 09 07:43:53 PM PDT 24 Aug 09 07:43:55 PM PDT 24 88968930 ps
T287 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2873320598 Aug 09 07:43:45 PM PDT 24 Aug 09 07:43:46 PM PDT 24 12778976 ps
T1023 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3738730002 Aug 09 07:44:02 PM PDT 24 Aug 09 07:44:03 PM PDT 24 18728906 ps
T271 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3112797316 Aug 09 07:43:56 PM PDT 24 Aug 09 07:43:58 PM PDT 24 19412000 ps
T1024 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3946934502 Aug 09 07:44:03 PM PDT 24 Aug 09 07:44:04 PM PDT 24 11761551 ps
T1025 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2937294850 Aug 09 07:43:45 PM PDT 24 Aug 09 07:43:50 PM PDT 24 588060743 ps
T1026 /workspace/coverage/cover_reg_top/10.edn_tl_errors.822559776 Aug 09 07:43:56 PM PDT 24 Aug 09 07:44:00 PM PDT 24 431660445 ps
T303 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2992986282 Aug 09 07:44:06 PM PDT 24 Aug 09 07:44:09 PM PDT 24 316719388 ps
T1027 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.227707688 Aug 09 07:43:54 PM PDT 24 Aug 09 07:43:55 PM PDT 24 63235696 ps
T1028 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3650772478 Aug 09 07:44:04 PM PDT 24 Aug 09 07:44:05 PM PDT 24 19229022 ps
T1029 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.234767760 Aug 09 07:43:57 PM PDT 24 Aug 09 07:43:58 PM PDT 24 24108963 ps
T272 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.817238920 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:56 PM PDT 24 12743224 ps
T1030 /workspace/coverage/cover_reg_top/44.edn_intr_test.62521627 Aug 09 07:44:09 PM PDT 24 Aug 09 07:44:10 PM PDT 24 52025570 ps
T1031 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1148016382 Aug 09 07:43:46 PM PDT 24 Aug 09 07:43:47 PM PDT 24 125711830 ps
T1032 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1726951593 Aug 09 07:44:11 PM PDT 24 Aug 09 07:44:14 PM PDT 24 123927294 ps
T1033 /workspace/coverage/cover_reg_top/19.edn_intr_test.2128581280 Aug 09 07:44:09 PM PDT 24 Aug 09 07:44:10 PM PDT 24 37288024 ps
T1034 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.729805064 Aug 09 07:43:57 PM PDT 24 Aug 09 07:43:59 PM PDT 24 58862439 ps
T1035 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2791399545 Aug 09 07:44:08 PM PDT 24 Aug 09 07:44:11 PM PDT 24 96128435 ps
T1036 /workspace/coverage/cover_reg_top/22.edn_intr_test.55039742 Aug 09 07:44:13 PM PDT 24 Aug 09 07:44:15 PM PDT 24 17358587 ps
T1037 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2374882806 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:57 PM PDT 24 292032001 ps
T1038 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4150333366 Aug 09 07:43:56 PM PDT 24 Aug 09 07:43:58 PM PDT 24 279684055 ps
T1039 /workspace/coverage/cover_reg_top/17.edn_tl_errors.809073467 Aug 09 07:44:02 PM PDT 24 Aug 09 07:44:05 PM PDT 24 193059251 ps
T1040 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3612540454 Aug 09 07:44:03 PM PDT 24 Aug 09 07:44:05 PM PDT 24 168918768 ps
T1041 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2703024043 Aug 09 07:44:03 PM PDT 24 Aug 09 07:44:05 PM PDT 24 33885818 ps
T1042 /workspace/coverage/cover_reg_top/38.edn_intr_test.687845324 Aug 09 07:44:14 PM PDT 24 Aug 09 07:44:15 PM PDT 24 37852134 ps
T1043 /workspace/coverage/cover_reg_top/30.edn_intr_test.3291882410 Aug 09 07:44:12 PM PDT 24 Aug 09 07:44:13 PM PDT 24 15993655 ps
T1044 /workspace/coverage/cover_reg_top/25.edn_intr_test.971538557 Aug 09 07:44:12 PM PDT 24 Aug 09 07:44:13 PM PDT 24 23470912 ps
T304 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.438169207 Aug 09 07:44:03 PM PDT 24 Aug 09 07:44:06 PM PDT 24 156473848 ps
T1045 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1845295115 Aug 09 07:43:48 PM PDT 24 Aug 09 07:43:51 PM PDT 24 359230710 ps
T1046 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1579901333 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:56 PM PDT 24 14049299 ps
T1047 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.823477091 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:56 PM PDT 24 68301500 ps
T306 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1454806437 Aug 09 07:44:04 PM PDT 24 Aug 09 07:44:06 PM PDT 24 53083329 ps
T273 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3130216074 Aug 09 07:43:47 PM PDT 24 Aug 09 07:43:48 PM PDT 24 12795154 ps
T1048 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1680816025 Aug 09 07:43:47 PM PDT 24 Aug 09 07:43:50 PM PDT 24 386592446 ps
T1049 /workspace/coverage/cover_reg_top/5.edn_intr_test.2068848285 Aug 09 07:43:56 PM PDT 24 Aug 09 07:43:57 PM PDT 24 28063390 ps
T305 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2539121337 Aug 09 07:44:07 PM PDT 24 Aug 09 07:44:09 PM PDT 24 107695803 ps
T1050 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3760501307 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:57 PM PDT 24 43989353 ps
T1051 /workspace/coverage/cover_reg_top/12.edn_intr_test.2024324230 Aug 09 07:44:10 PM PDT 24 Aug 09 07:44:12 PM PDT 24 13071560 ps
T1052 /workspace/coverage/cover_reg_top/21.edn_intr_test.2613619037 Aug 09 07:44:13 PM PDT 24 Aug 09 07:44:13 PM PDT 24 14083828 ps
T1053 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1113977062 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:57 PM PDT 24 50127065 ps
T1054 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2669868898 Aug 09 07:43:46 PM PDT 24 Aug 09 07:43:47 PM PDT 24 53114299 ps
T1055 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3338560875 Aug 09 07:43:48 PM PDT 24 Aug 09 07:43:49 PM PDT 24 48392481 ps
T274 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3593250514 Aug 09 07:43:42 PM PDT 24 Aug 09 07:43:43 PM PDT 24 18747946 ps
T1056 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.792664880 Aug 09 07:43:53 PM PDT 24 Aug 09 07:43:55 PM PDT 24 198959685 ps
T1057 /workspace/coverage/cover_reg_top/3.edn_tl_errors.438475237 Aug 09 07:43:45 PM PDT 24 Aug 09 07:43:48 PM PDT 24 251931986 ps
T1058 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1298272115 Aug 09 07:43:57 PM PDT 24 Aug 09 07:43:58 PM PDT 24 120144692 ps
T1059 /workspace/coverage/cover_reg_top/14.edn_csr_rw.281040852 Aug 09 07:44:04 PM PDT 24 Aug 09 07:44:05 PM PDT 24 11905122 ps
T1060 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3387076828 Aug 09 07:44:09 PM PDT 24 Aug 09 07:44:10 PM PDT 24 23353881 ps
T1061 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3397922013 Aug 09 07:43:57 PM PDT 24 Aug 09 07:43:58 PM PDT 24 34708282 ps
T1062 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3287377208 Aug 09 07:44:09 PM PDT 24 Aug 09 07:44:12 PM PDT 24 99658981 ps
T1063 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2036685173 Aug 09 07:43:46 PM PDT 24 Aug 09 07:43:47 PM PDT 24 70919644 ps
T1064 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2994456737 Aug 09 07:44:10 PM PDT 24 Aug 09 07:44:12 PM PDT 24 88081239 ps
T1065 /workspace/coverage/cover_reg_top/43.edn_intr_test.2296440942 Aug 09 07:44:12 PM PDT 24 Aug 09 07:44:13 PM PDT 24 17967824 ps
T1066 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.637015397 Aug 09 07:43:46 PM PDT 24 Aug 09 07:43:47 PM PDT 24 37900339 ps
T1067 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3729267307 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:57 PM PDT 24 27619583 ps
T1068 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3651669235 Aug 09 07:43:57 PM PDT 24 Aug 09 07:43:58 PM PDT 24 71051050 ps
T1069 /workspace/coverage/cover_reg_top/49.edn_intr_test.3569274016 Aug 09 07:44:13 PM PDT 24 Aug 09 07:44:14 PM PDT 24 23085082 ps
T1070 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3826277886 Aug 09 07:43:46 PM PDT 24 Aug 09 07:43:48 PM PDT 24 95496302 ps
T1071 /workspace/coverage/cover_reg_top/23.edn_intr_test.3885129274 Aug 09 07:44:13 PM PDT 24 Aug 09 07:44:14 PM PDT 24 16386069 ps
T1072 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.499278627 Aug 09 07:44:04 PM PDT 24 Aug 09 07:44:06 PM PDT 24 27590496 ps
T1073 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3638838450 Aug 09 07:44:09 PM PDT 24 Aug 09 07:44:14 PM PDT 24 117612429 ps
T1074 /workspace/coverage/cover_reg_top/9.edn_intr_test.3201962860 Aug 09 07:43:56 PM PDT 24 Aug 09 07:43:57 PM PDT 24 24779832 ps
T1075 /workspace/coverage/cover_reg_top/13.edn_tl_errors.370979685 Aug 09 07:44:04 PM PDT 24 Aug 09 07:44:08 PM PDT 24 106866011 ps
T1076 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.734812154 Aug 09 07:44:09 PM PDT 24 Aug 09 07:44:12 PM PDT 24 101538942 ps
T1077 /workspace/coverage/cover_reg_top/6.edn_intr_test.245016517 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:56 PM PDT 24 13326967 ps
T1078 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1049994848 Aug 09 07:43:47 PM PDT 24 Aug 09 07:43:49 PM PDT 24 52068384 ps
T1079 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2038995951 Aug 09 07:43:54 PM PDT 24 Aug 09 07:43:57 PM PDT 24 128585242 ps
T1080 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2659404450 Aug 09 07:43:57 PM PDT 24 Aug 09 07:43:59 PM PDT 24 111814321 ps
T1081 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1231818471 Aug 09 07:44:09 PM PDT 24 Aug 09 07:44:15 PM PDT 24 603909280 ps
T1082 /workspace/coverage/cover_reg_top/16.edn_intr_test.3600093162 Aug 09 07:44:07 PM PDT 24 Aug 09 07:44:08 PM PDT 24 14890770 ps
T1083 /workspace/coverage/cover_reg_top/42.edn_intr_test.4277664198 Aug 09 07:44:13 PM PDT 24 Aug 09 07:44:14 PM PDT 24 76390617 ps
T1084 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1724480258 Aug 09 07:44:04 PM PDT 24 Aug 09 07:44:06 PM PDT 24 77591540 ps
T1085 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2529653931 Aug 09 07:43:44 PM PDT 24 Aug 09 07:43:45 PM PDT 24 50834354 ps
T275 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.306636 Aug 09 07:43:48 PM PDT 24 Aug 09 07:43:49 PM PDT 24 100462698 ps
T1086 /workspace/coverage/cover_reg_top/1.edn_intr_test.3184139520 Aug 09 07:43:45 PM PDT 24 Aug 09 07:43:46 PM PDT 24 10918415 ps
T1087 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3468376898 Aug 09 07:44:11 PM PDT 24 Aug 09 07:44:12 PM PDT 24 20658327 ps
T276 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1125235928 Aug 09 07:43:47 PM PDT 24 Aug 09 07:43:48 PM PDT 24 75844232 ps
T1088 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3026676448 Aug 09 07:43:48 PM PDT 24 Aug 09 07:43:50 PM PDT 24 157182109 ps
T1089 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1832834180 Aug 09 07:44:09 PM PDT 24 Aug 09 07:44:11 PM PDT 24 86372778 ps
T1090 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2480793193 Aug 09 07:44:05 PM PDT 24 Aug 09 07:44:07 PM PDT 24 24721062 ps
T1091 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2415785300 Aug 09 07:44:09 PM PDT 24 Aug 09 07:44:10 PM PDT 24 37883364 ps
T1092 /workspace/coverage/cover_reg_top/47.edn_intr_test.925955523 Aug 09 07:44:10 PM PDT 24 Aug 09 07:44:11 PM PDT 24 31901618 ps
T1093 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2357663579 Aug 09 07:44:08 PM PDT 24 Aug 09 07:44:10 PM PDT 24 27646102 ps
T1094 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2041169957 Aug 09 07:44:07 PM PDT 24 Aug 09 07:44:08 PM PDT 24 88343719 ps
T1095 /workspace/coverage/cover_reg_top/39.edn_intr_test.4285219317 Aug 09 07:44:13 PM PDT 24 Aug 09 07:44:14 PM PDT 24 48710718 ps
T1096 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.929348940 Aug 09 07:43:54 PM PDT 24 Aug 09 07:43:56 PM PDT 24 20598244 ps
T1097 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1502451456 Aug 09 07:44:08 PM PDT 24 Aug 09 07:44:10 PM PDT 24 74043197 ps
T279 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.228186976 Aug 09 07:43:46 PM PDT 24 Aug 09 07:43:47 PM PDT 24 13178905 ps
T1098 /workspace/coverage/cover_reg_top/18.edn_intr_test.821176683 Aug 09 07:44:09 PM PDT 24 Aug 09 07:44:10 PM PDT 24 12343695 ps
T1099 /workspace/coverage/cover_reg_top/35.edn_intr_test.1458905646 Aug 09 07:44:12 PM PDT 24 Aug 09 07:44:13 PM PDT 24 23573365 ps
T1100 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3686109120 Aug 09 07:43:46 PM PDT 24 Aug 09 07:43:47 PM PDT 24 76304174 ps
T1101 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3047367845 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:57 PM PDT 24 103571250 ps
T1102 /workspace/coverage/cover_reg_top/46.edn_intr_test.2944944195 Aug 09 07:44:11 PM PDT 24 Aug 09 07:44:12 PM PDT 24 13366104 ps
T1103 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1458943047 Aug 09 07:44:10 PM PDT 24 Aug 09 07:44:10 PM PDT 24 42693774 ps
T280 /workspace/coverage/cover_reg_top/0.edn_csr_rw.42273625 Aug 09 07:43:46 PM PDT 24 Aug 09 07:43:47 PM PDT 24 11781497 ps
T1104 /workspace/coverage/cover_reg_top/14.edn_intr_test.3832357116 Aug 09 07:44:06 PM PDT 24 Aug 09 07:44:07 PM PDT 24 14612453 ps
T1105 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.142327234 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:59 PM PDT 24 579849641 ps
T1106 /workspace/coverage/cover_reg_top/15.edn_intr_test.4284148779 Aug 09 07:44:03 PM PDT 24 Aug 09 07:44:04 PM PDT 24 31838147 ps
T1107 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2457645 Aug 09 07:43:42 PM PDT 24 Aug 09 07:43:43 PM PDT 24 13528651 ps
T1108 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.492295810 Aug 09 07:43:56 PM PDT 24 Aug 09 07:43:59 PM PDT 24 73998425 ps
T1109 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1957328204 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:57 PM PDT 24 106021581 ps
T1110 /workspace/coverage/cover_reg_top/17.edn_intr_test.106023647 Aug 09 07:44:02 PM PDT 24 Aug 09 07:44:03 PM PDT 24 106641193 ps
T1111 /workspace/coverage/cover_reg_top/45.edn_intr_test.2277551193 Aug 09 07:44:13 PM PDT 24 Aug 09 07:44:14 PM PDT 24 27659285 ps
T1112 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2808378185 Aug 09 07:44:02 PM PDT 24 Aug 09 07:44:05 PM PDT 24 280755897 ps
T1113 /workspace/coverage/cover_reg_top/7.edn_intr_test.3237430560 Aug 09 07:43:57 PM PDT 24 Aug 09 07:43:58 PM PDT 24 26953315 ps
T1114 /workspace/coverage/cover_reg_top/37.edn_intr_test.4277121471 Aug 09 07:44:15 PM PDT 24 Aug 09 07:44:16 PM PDT 24 11164853 ps
T1115 /workspace/coverage/cover_reg_top/36.edn_intr_test.2924283143 Aug 09 07:44:12 PM PDT 24 Aug 09 07:44:13 PM PDT 24 28599494 ps
T1116 /workspace/coverage/cover_reg_top/8.edn_intr_test.3219292213 Aug 09 07:43:56 PM PDT 24 Aug 09 07:43:57 PM PDT 24 140733275 ps
T1117 /workspace/coverage/cover_reg_top/41.edn_intr_test.4054639931 Aug 09 07:44:11 PM PDT 24 Aug 09 07:44:13 PM PDT 24 74247350 ps
T1118 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2505017715 Aug 09 07:44:03 PM PDT 24 Aug 09 07:44:04 PM PDT 24 19188104 ps
T1119 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2555226472 Aug 09 07:43:54 PM PDT 24 Aug 09 07:43:55 PM PDT 24 82374145 ps
T1120 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2115194102 Aug 09 07:44:07 PM PDT 24 Aug 09 07:44:08 PM PDT 24 26934093 ps
T1121 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.4144013011 Aug 09 07:43:47 PM PDT 24 Aug 09 07:43:51 PM PDT 24 215470498 ps
T1122 /workspace/coverage/cover_reg_top/32.edn_intr_test.3573546667 Aug 09 07:44:10 PM PDT 24 Aug 09 07:44:11 PM PDT 24 20410224 ps
T277 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1984613287 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:58 PM PDT 24 36227669 ps
T281 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1218115398 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:57 PM PDT 24 15073648 ps
T1123 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3030853006 Aug 09 07:43:54 PM PDT 24 Aug 09 07:43:55 PM PDT 24 142378166 ps
T278 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.165443392 Aug 09 07:43:55 PM PDT 24 Aug 09 07:43:56 PM PDT 24 65267328 ps
T1124 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3164101847 Aug 09 07:44:07 PM PDT 24 Aug 09 07:44:08 PM PDT 24 104062315 ps
T282 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3605335394 Aug 09 07:43:57 PM PDT 24 Aug 09 07:43:58 PM PDT 24 33148904 ps
T1125 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3912013310 Aug 09 07:44:06 PM PDT 24 Aug 09 07:44:07 PM PDT 24 85182092 ps
T1126 /workspace/coverage/cover_reg_top/26.edn_intr_test.4033026287 Aug 09 07:44:14 PM PDT 24 Aug 09 07:44:15 PM PDT 24 65037043 ps
T1127 /workspace/coverage/cover_reg_top/10.edn_intr_test.2355264723 Aug 09 07:43:56 PM PDT 24 Aug 09 07:43:57 PM PDT 24 46734957 ps
T1128 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1114256290 Aug 09 07:43:53 PM PDT 24 Aug 09 07:43:57 PM PDT 24 85417232 ps
T1129 /workspace/coverage/cover_reg_top/0.edn_intr_test.899802579 Aug 09 07:43:46 PM PDT 24 Aug 09 07:43:47 PM PDT 24 24253576 ps
T1130 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1278544502 Aug 09 07:43:53 PM PDT 24 Aug 09 07:43:55 PM PDT 24 25751784 ps

Test location /workspace/coverage/default/182.edn_alert.3503594342
Short name T19
Test name
Test status
Simulation time 47324790 ps
CPU time 1.19 seconds
Started Aug 09 07:52:42 PM PDT 24
Finished Aug 09 07:52:44 PM PDT 24
Peak memory 220592 kb
Host smart-490f93c1-ed17-4baa-b98a-f6ba8dc39d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503594342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3503594342
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/59.edn_genbits.290215747
Short name T46
Test name
Test status
Simulation time 54006763 ps
CPU time 1.4 seconds
Started Aug 09 07:51:53 PM PDT 24
Finished Aug 09 07:51:55 PM PDT 24
Peak memory 217324 kb
Host smart-4c0bbf32-1730-4804-a491-f38c9fd2d461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290215747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.290215747
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4047414993
Short name T43
Test name
Test status
Simulation time 738226205638 ps
CPU time 2120.3 seconds
Started Aug 09 07:51:47 PM PDT 24
Finished Aug 09 08:27:08 PM PDT 24
Peak memory 225620 kb
Host smart-abbabc8d-d0ee-433d-ac0e-952233c72a1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047414993 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4047414993
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.980433868
Short name T10
Test name
Test status
Simulation time 86877147 ps
CPU time 1.19 seconds
Started Aug 09 07:51:41 PM PDT 24
Finished Aug 09 07:51:42 PM PDT 24
Peak memory 219804 kb
Host smart-9d66250c-a35d-467d-992c-259f1fa0c91c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980433868 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.980433868
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2554440234
Short name T5
Test name
Test status
Simulation time 22969654 ps
CPU time 1.03 seconds
Started Aug 09 07:52:03 PM PDT 24
Finished Aug 09 07:52:04 PM PDT 24
Peak memory 218964 kb
Host smart-beb5adbf-3b5e-4690-9802-a512296ef707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554440234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2554440234
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1289216676
Short name T22
Test name
Test status
Simulation time 512891125 ps
CPU time 4.7 seconds
Started Aug 09 07:50:52 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 239696 kb
Host smart-34114d81-cbcf-4520-9c63-63ac8a61d3e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289216676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1289216676
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/189.edn_alert.653528729
Short name T55
Test name
Test status
Simulation time 26005039 ps
CPU time 1.28 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218648 kb
Host smart-76409c2a-a1a6-423e-9be1-a4c17b986970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653528729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.653528729
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/5.edn_disable.3910092625
Short name T102
Test name
Test status
Simulation time 133963191 ps
CPU time 0.91 seconds
Started Aug 09 07:50:49 PM PDT 24
Finished Aug 09 07:50:50 PM PDT 24
Peak memory 219308 kb
Host smart-c9978597-5c71-407c-bc3b-f03f1dec59bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910092625 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3910092625
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/54.edn_err.4252667684
Short name T62
Test name
Test status
Simulation time 20388809 ps
CPU time 1.12 seconds
Started Aug 09 07:52:14 PM PDT 24
Finished Aug 09 07:52:15 PM PDT 24
Peak memory 224120 kb
Host smart-3cc59af8-fbae-4b54-ad41-d08be233bca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252667684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.4252667684
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/199.edn_genbits.213141702
Short name T23
Test name
Test status
Simulation time 60814894 ps
CPU time 2.29 seconds
Started Aug 09 07:52:44 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 220472 kb
Host smart-b1a7bd23-eaae-4311-8966-68d67e24ed97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213141702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.213141702
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.2562934194
Short name T66
Test name
Test status
Simulation time 25683932 ps
CPU time 1.36 seconds
Started Aug 09 07:52:01 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 218776 kb
Host smart-780f36e0-daca-4cc3-a780-b8ae830936ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562934194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2562934194
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/1.edn_regwen.4217213864
Short name T31
Test name
Test status
Simulation time 14780035 ps
CPU time 1.06 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 07:50:43 PM PDT 24
Peak memory 207116 kb
Host smart-3944acff-cd0f-4de8-a0c6-0b74510bd26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217213864 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.4217213864
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/113.edn_alert.2694962703
Short name T98
Test name
Test status
Simulation time 93067661 ps
CPU time 1.25 seconds
Started Aug 09 07:52:41 PM PDT 24
Finished Aug 09 07:52:42 PM PDT 24
Peak memory 220064 kb
Host smart-e5006d61-df3f-49e7-91f8-0f253697e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694962703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2694962703
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2992986282
Short name T303
Test name
Test status
Simulation time 316719388 ps
CPU time 2.36 seconds
Started Aug 09 07:44:06 PM PDT 24
Finished Aug 09 07:44:09 PM PDT 24
Peak memory 207036 kb
Host smart-937fc68b-cf58-4672-a6fc-97238f8cb66b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992986282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2992986282
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/default/142.edn_alert.2887981010
Short name T179
Test name
Test status
Simulation time 161888763 ps
CPU time 1.28 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 219556 kb
Host smart-efbc8352-6a64-4525-8de1-95b0e5ed7e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887981010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2887981010
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.4189973137
Short name T266
Test name
Test status
Simulation time 21691347 ps
CPU time 0.86 seconds
Started Aug 09 07:43:56 PM PDT 24
Finished Aug 09 07:43:58 PM PDT 24
Peak memory 206776 kb
Host smart-73678571-116c-4b70-b41f-d415412465b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189973137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.4189973137
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/default/25.edn_disable.2958555325
Short name T48
Test name
Test status
Simulation time 12705899 ps
CPU time 0.87 seconds
Started Aug 09 07:51:20 PM PDT 24
Finished Aug 09 07:51:21 PM PDT 24
Peak memory 216492 kb
Host smart-bdaefe07-9d01-4db9-84ed-8df97fa743c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958555325 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2958555325
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/27.edn_intr.2456496715
Short name T38
Test name
Test status
Simulation time 20734391 ps
CPU time 1.1 seconds
Started Aug 09 07:51:22 PM PDT 24
Finished Aug 09 07:51:23 PM PDT 24
Peak memory 216184 kb
Host smart-02fd2c73-a57c-4451-817c-030f955efcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456496715 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2456496715
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/14.edn_disable.2803653305
Short name T107
Test name
Test status
Simulation time 12395277 ps
CPU time 0.89 seconds
Started Aug 09 07:51:01 PM PDT 24
Finished Aug 09 07:51:02 PM PDT 24
Peak memory 216644 kb
Host smart-6dcbb385-9df1-466a-b30d-7ee9a7dcf15a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803653305 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2803653305
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3198926809
Short name T86
Test name
Test status
Simulation time 66783348 ps
CPU time 1.02 seconds
Started Aug 09 07:51:21 PM PDT 24
Finished Aug 09 07:51:22 PM PDT 24
Peak memory 217256 kb
Host smart-aeb28d09-698d-452a-b39a-ee467e43e956
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198926809 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3198926809
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_intr.2446114044
Short name T60
Test name
Test status
Simulation time 25266535 ps
CPU time 1.17 seconds
Started Aug 09 07:50:38 PM PDT 24
Finished Aug 09 07:50:40 PM PDT 24
Peak memory 224176 kb
Host smart-2ecd3daa-7dad-49cd-8639-962ac940774a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446114044 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2446114044
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/150.edn_alert.2072549836
Short name T235
Test name
Test status
Simulation time 79843253 ps
CPU time 1.21 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 220824 kb
Host smart-7552ac45-36c7-4445-9b38-9ccd37f6fe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072549836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2072549836
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.2710941474
Short name T14
Test name
Test status
Simulation time 68716216 ps
CPU time 1.36 seconds
Started Aug 09 07:52:34 PM PDT 24
Finished Aug 09 07:52:35 PM PDT 24
Peak memory 219832 kb
Host smart-4eb12554-9e6b-4c19-a214-f37e5bbe685e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710941474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2710941474
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.313202094
Short name T159
Test name
Test status
Simulation time 38608518 ps
CPU time 1.27 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 219756 kb
Host smart-d2f2aabb-1d34-479e-bc39-5941fb670f0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313202094 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.313202094
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_genbits.3316080179
Short name T91
Test name
Test status
Simulation time 57366922 ps
CPU time 1.7 seconds
Started Aug 09 07:50:48 PM PDT 24
Finished Aug 09 07:50:50 PM PDT 24
Peak memory 218428 kb
Host smart-f04234b7-3cd4-4488-b37c-e13570552e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316080179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3316080179
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/70.edn_alert.1252904288
Short name T261
Test name
Test status
Simulation time 49674658 ps
CPU time 1.25 seconds
Started Aug 09 07:51:58 PM PDT 24
Finished Aug 09 07:51:59 PM PDT 24
Peak memory 218472 kb
Host smart-bd15cd33-2a15-4e70-97eb-54596dd8413a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252904288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1252904288
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/58.edn_alert.759390399
Short name T133
Test name
Test status
Simulation time 45935110 ps
CPU time 1.3 seconds
Started Aug 09 07:51:57 PM PDT 24
Finished Aug 09 07:51:59 PM PDT 24
Peak memory 218348 kb
Host smart-452a33f2-15eb-48b4-9ef6-5d9392d69b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759390399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.759390399
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/230.edn_genbits.2627109870
Short name T344
Test name
Test status
Simulation time 66728198 ps
CPU time 1.52 seconds
Started Aug 09 07:52:52 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 219948 kb
Host smart-e2ee5ad8-8e4e-451c-ba56-6f1cfd5c3413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627109870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2627109870
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert.1320053286
Short name T191
Test name
Test status
Simulation time 43669758 ps
CPU time 1.17 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 07:50:42 PM PDT 24
Peak memory 219772 kb
Host smart-aa98ea45-ebe2-462a-859d-4ce38478ba15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320053286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1320053286
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/102.edn_alert.884735115
Short name T185
Test name
Test status
Simulation time 25387151 ps
CPU time 1.21 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 218408 kb
Host smart-a614319d-f3d5-44cd-981a-7cfdd89ea430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884735115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.884735115
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/139.edn_alert.3605832593
Short name T161
Test name
Test status
Simulation time 93123397 ps
CPU time 1.11 seconds
Started Aug 09 07:52:46 PM PDT 24
Finished Aug 09 07:52:47 PM PDT 24
Peak memory 219652 kb
Host smart-1682b025-6a4a-4e00-b4f1-f6026ba518bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605832593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.3605832593
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3035856758
Short name T813
Test name
Test status
Simulation time 20829044064 ps
CPU time 464.3 seconds
Started Aug 09 07:51:47 PM PDT 24
Finished Aug 09 07:59:31 PM PDT 24
Peak memory 223556 kb
Host smart-a808e2ae-7ea3-4c56-a06b-a8872eee5351
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035856758 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3035856758
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.edn_alert.768119116
Short name T157
Test name
Test status
Simulation time 25086465 ps
CPU time 1.19 seconds
Started Aug 09 07:52:10 PM PDT 24
Finished Aug 09 07:52:16 PM PDT 24
Peak memory 220456 kb
Host smart-eabacf0f-8e45-4b9c-a2d7-a83c4dbccf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768119116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.768119116
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/45.edn_intr.200108435
Short name T40
Test name
Test status
Simulation time 36461375 ps
CPU time 0.86 seconds
Started Aug 09 07:51:50 PM PDT 24
Finished Aug 09 07:51:51 PM PDT 24
Peak memory 215892 kb
Host smart-810cb8a5-c64b-4539-bcc3-2a3ed05fa077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200108435 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.200108435
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/43.edn_alert.59111776
Short name T203
Test name
Test status
Simulation time 275122886 ps
CPU time 1.2 seconds
Started Aug 09 07:51:51 PM PDT 24
Finished Aug 09 07:51:53 PM PDT 24
Peak memory 220236 kb
Host smart-15cca827-378e-4b60-a467-cc24d47a0b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59111776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.59111776
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/15.edn_genbits.1162588761
Short name T248
Test name
Test status
Simulation time 267212356 ps
CPU time 3.42 seconds
Started Aug 09 07:51:04 PM PDT 24
Finished Aug 09 07:51:07 PM PDT 24
Peak memory 219992 kb
Host smart-6c3efe8f-5bbf-4d98-845b-95439b7968bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162588761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1162588761
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable.773274996
Short name T914
Test name
Test status
Simulation time 10700673 ps
CPU time 0.91 seconds
Started Aug 09 07:50:42 PM PDT 24
Finished Aug 09 07:50:43 PM PDT 24
Peak memory 215344 kb
Host smart-8f035363-f2d6-47b2-973f-2a6044227164
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773274996 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.773274996
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/45.edn_stress_all.3269535273
Short name T2
Test name
Test status
Simulation time 332621771 ps
CPU time 6.31 seconds
Started Aug 09 07:51:57 PM PDT 24
Finished Aug 09 07:52:03 PM PDT 24
Peak memory 217116 kb
Host smart-23b066d7-346c-41ba-b6ca-755d29c73eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269535273 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3269535273
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/101.edn_alert.2316421532
Short name T941
Test name
Test status
Simulation time 123493675 ps
CPU time 1.1 seconds
Started Aug 09 07:52:22 PM PDT 24
Finished Aug 09 07:52:23 PM PDT 24
Peak memory 218272 kb
Host smart-ce3bed96-c803-49f6-8593-fe9ff20487ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316421532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2316421532
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/134.edn_alert.387988483
Short name T151
Test name
Test status
Simulation time 25014971 ps
CPU time 1.24 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 220188 kb
Host smart-1bdee0e4-e471-42d8-adcd-f0f2d0be09f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387988483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.387988483
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/151.edn_alert.2876179072
Short name T643
Test name
Test status
Simulation time 32134187 ps
CPU time 1.18 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 218596 kb
Host smart-d2222ec0-e3c5-48ea-a938-73c94a2139c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876179072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.2876179072
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/17.edn_disable.2084284616
Short name T223
Test name
Test status
Simulation time 48278407 ps
CPU time 0.85 seconds
Started Aug 09 07:51:15 PM PDT 24
Finished Aug 09 07:51:16 PM PDT 24
Peak memory 216480 kb
Host smart-f371bec2-3e94-4127-bdfa-5c28835e1ee0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084284616 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2084284616
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable.4251703086
Short name T213
Test name
Test status
Simulation time 13277520 ps
CPU time 0.97 seconds
Started Aug 09 07:51:13 PM PDT 24
Finished Aug 09 07:51:14 PM PDT 24
Peak memory 216628 kb
Host smart-3b73706a-9939-4b47-823c-c427c47931dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251703086 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4251703086
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.277171001
Short name T206
Test name
Test status
Simulation time 18756262 ps
CPU time 1.06 seconds
Started Aug 09 07:51:20 PM PDT 24
Finished Aug 09 07:51:22 PM PDT 24
Peak memory 218840 kb
Host smart-d2ad4f81-c168-4263-91aa-5381e88a63a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277171001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.277171001
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.4137660658
Short name T170
Test name
Test status
Simulation time 69984819 ps
CPU time 0.96 seconds
Started Aug 09 07:51:39 PM PDT 24
Finished Aug 09 07:51:40 PM PDT 24
Peak memory 219456 kb
Host smart-c7df1556-58ab-4446-b6ef-1866eb00c402
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137660658 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.4137660658
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_disable.1817090923
Short name T220
Test name
Test status
Simulation time 14237782 ps
CPU time 0.93 seconds
Started Aug 09 07:51:43 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 216668 kb
Host smart-a47d0b21-e71e-4ed8-9eac-d9f7f57a51ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817090923 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1817090923
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable.2476821176
Short name T218
Test name
Test status
Simulation time 17494581 ps
CPU time 0.84 seconds
Started Aug 09 07:51:41 PM PDT 24
Finished Aug 09 07:51:42 PM PDT 24
Peak memory 218268 kb
Host smart-29e7fe50-273b-4a73-843f-4af47aa122ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476821176 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2476821176
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2191784326
Short name T165
Test name
Test status
Simulation time 35675259 ps
CPU time 1.04 seconds
Started Aug 09 07:51:36 PM PDT 24
Finished Aug 09 07:51:37 PM PDT 24
Peak memory 217264 kb
Host smart-798cbbe9-8b5d-4f1e-8413-f8a774225f24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191784326 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2191784326
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_disable.4264502892
Short name T225
Test name
Test status
Simulation time 57226556 ps
CPU time 0.9 seconds
Started Aug 09 07:51:45 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 216468 kb
Host smart-091641aa-dd96-4121-b11c-53569c9a2146
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264502892 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.4264502892
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/52.edn_err.1018414380
Short name T209
Test name
Test status
Simulation time 28273893 ps
CPU time 0.91 seconds
Started Aug 09 07:52:13 PM PDT 24
Finished Aug 09 07:52:14 PM PDT 24
Peak memory 219716 kb
Host smart-cd7d3b0a-d582-4b56-9c36-e4e15a688ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018414380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1018414380
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/59.edn_err.3550106108
Short name T199
Test name
Test status
Simulation time 20505775 ps
CPU time 1.08 seconds
Started Aug 09 07:51:57 PM PDT 24
Finished Aug 09 07:51:58 PM PDT 24
Peak memory 218776 kb
Host smart-557d9fcf-c48a-4211-abe1-824b6d5e2fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550106108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3550106108
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/1.edn_alert_test.4149213948
Short name T393
Test name
Test status
Simulation time 32063459 ps
CPU time 0.99 seconds
Started Aug 09 07:50:39 PM PDT 24
Finished Aug 09 07:50:40 PM PDT 24
Peak memory 206820 kb
Host smart-8a0ad931-401a-4d5c-ae94-ff0dcb8c4169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149213948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.4149213948
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/185.edn_alert.750820885
Short name T309
Test name
Test status
Simulation time 110007000 ps
CPU time 1.23 seconds
Started Aug 09 07:52:49 PM PDT 24
Finished Aug 09 07:52:50 PM PDT 24
Peak memory 215560 kb
Host smart-e0c2f2fe-a973-49c5-ba6e-13192e9f3389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750820885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.750820885
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/10.edn_genbits.1175802435
Short name T346
Test name
Test status
Simulation time 36086404 ps
CPU time 1.31 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 07:50:56 PM PDT 24
Peak memory 217468 kb
Host smart-515b7e72-1e7c-40ea-8f8b-924b9d047582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175802435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1175802435
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_genbits.3874963596
Short name T95
Test name
Test status
Simulation time 95930133 ps
CPU time 1.22 seconds
Started Aug 09 07:51:03 PM PDT 24
Finished Aug 09 07:51:04 PM PDT 24
Peak memory 219852 kb
Host smart-8cbaae9d-946e-48e5-bd32-98ec25d6f1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874963596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3874963596
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3745347381
Short name T465
Test name
Test status
Simulation time 132090253743 ps
CPU time 1668.09 seconds
Started Aug 09 07:51:05 PM PDT 24
Finished Aug 09 08:18:54 PM PDT 24
Peak memory 226428 kb
Host smart-e4ab768f-5bf1-456b-8c52-835ff1f53d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745347381 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3745347381
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_intr.3333879117
Short name T109
Test name
Test status
Simulation time 24766600 ps
CPU time 0.94 seconds
Started Aug 09 07:50:39 PM PDT 24
Finished Aug 09 07:50:40 PM PDT 24
Peak memory 216164 kb
Host smart-9313d48f-fc96-45d8-b552-d4022baf2f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333879117 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3333879117
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/19.edn_err.284544722
Short name T8
Test name
Test status
Simulation time 55152409 ps
CPU time 1.02 seconds
Started Aug 09 07:51:09 PM PDT 24
Finished Aug 09 07:51:10 PM PDT 24
Peak memory 218948 kb
Host smart-21362521-8359-4a4a-8444-1421734a52fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284544722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.284544722
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/112.edn_genbits.1710208534
Short name T377
Test name
Test status
Simulation time 26608357 ps
CPU time 1.23 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 218584 kb
Host smart-dcf79f2f-ce90-43a4-b580-4dec44a737fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710208534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1710208534
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_genbits.2752039474
Short name T49
Test name
Test status
Simulation time 81115406 ps
CPU time 1.73 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 218536 kb
Host smart-00f33fa4-64f6-429d-b251-324d06c7cfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752039474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2752039474
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.42273625
Short name T280
Test name
Test status
Simulation time 11781497 ps
CPU time 0.88 seconds
Started Aug 09 07:43:46 PM PDT 24
Finished Aug 09 07:43:47 PM PDT 24
Peak memory 206824 kb
Host smart-14ea74c7-1011-4690-8591-c4bb8a5368e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42273625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.42273625
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.4093304319
Short name T928
Test name
Test status
Simulation time 110905419337 ps
CPU time 634.84 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 08:01:16 PM PDT 24
Peak memory 219768 kb
Host smart-74f96455-207d-45e3-9ad2-323ada6b8c66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093304319 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.4093304319
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.edn_alert.1131594726
Short name T526
Test name
Test status
Simulation time 38155435 ps
CPU time 1.18 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 219936 kb
Host smart-eafa0175-6af6-4197-8f28-ca7ab2d7b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131594726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1131594726
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/14.edn_stress_all.2234392454
Short name T122
Test name
Test status
Simulation time 895347416 ps
CPU time 5.3 seconds
Started Aug 09 07:51:03 PM PDT 24
Finished Aug 09 07:51:09 PM PDT 24
Peak memory 217372 kb
Host smart-c13a3d69-e001-4abf-bfcf-f397b045bf56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234392454 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2234392454
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/142.edn_genbits.4236361444
Short name T330
Test name
Test status
Simulation time 86634779 ps
CPU time 1.13 seconds
Started Aug 09 07:52:33 PM PDT 24
Finished Aug 09 07:52:34 PM PDT 24
Peak memory 220120 kb
Host smart-5d952a60-ed5e-412e-b15f-57295ca50bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236361444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.4236361444
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1195311014
Short name T702
Test name
Test status
Simulation time 40734032 ps
CPU time 1.4 seconds
Started Aug 09 07:52:31 PM PDT 24
Finished Aug 09 07:52:32 PM PDT 24
Peak memory 218536 kb
Host smart-aa409e4f-a53c-4316-be4f-60978ce3c529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195311014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1195311014
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.73496576
Short name T333
Test name
Test status
Simulation time 44197988 ps
CPU time 1.69 seconds
Started Aug 09 07:52:43 PM PDT 24
Finished Aug 09 07:52:45 PM PDT 24
Peak memory 218784 kb
Host smart-9877164c-61e6-494e-b446-d983b194b4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73496576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.73496576
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.441103756
Short name T319
Test name
Test status
Simulation time 37129688 ps
CPU time 1.15 seconds
Started Aug 09 07:52:40 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218656 kb
Host smart-cd0d41b7-7e76-44bb-9fbf-0d5b819142f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441103756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.441103756
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/200.edn_genbits.3511442696
Short name T956
Test name
Test status
Simulation time 40917721 ps
CPU time 1.19 seconds
Started Aug 09 07:52:50 PM PDT 24
Finished Aug 09 07:52:51 PM PDT 24
Peak memory 218836 kb
Host smart-8a945de5-5b4e-4668-8f5e-ba4aed67915e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511442696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3511442696
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.793339118
Short name T42
Test name
Test status
Simulation time 25323018 ps
CPU time 1.05 seconds
Started Aug 09 07:50:40 PM PDT 24
Finished Aug 09 07:50:41 PM PDT 24
Peak memory 215932 kb
Host smart-03b3c6c6-f72b-4141-839b-33596b37ecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793339118 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.793339118
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/107.edn_alert.2821285151
Short name T575
Test name
Test status
Simulation time 50384909 ps
CPU time 1.22 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 220116 kb
Host smart-98d4eb9a-d02c-43eb-9dab-a58e0018e3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821285151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2821285151
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/2.edn_genbits.1101038671
Short name T940
Test name
Test status
Simulation time 219630880 ps
CPU time 1.53 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 07:50:42 PM PDT 24
Peak memory 219796 kb
Host smart-b96db306-4a64-4136-8d0e-0574c0e4926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101038671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1101038671
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1125235928
Short name T276
Test name
Test status
Simulation time 75844232 ps
CPU time 1.13 seconds
Started Aug 09 07:43:47 PM PDT 24
Finished Aug 09 07:43:48 PM PDT 24
Peak memory 206820 kb
Host smart-8f5a72f2-8d35-4e81-ada9-7efb3ca8e508
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125235928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1125235928
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3026676448
Short name T1088
Test name
Test status
Simulation time 157182109 ps
CPU time 1.98 seconds
Started Aug 09 07:43:48 PM PDT 24
Finished Aug 09 07:43:50 PM PDT 24
Peak memory 206748 kb
Host smart-21edc3b5-9501-4d05-b8d7-4718d839db00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026676448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3026676448
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3130216074
Short name T273
Test name
Test status
Simulation time 12795154 ps
CPU time 0.9 seconds
Started Aug 09 07:43:47 PM PDT 24
Finished Aug 09 07:43:48 PM PDT 24
Peak memory 206812 kb
Host smart-4dc39fc1-9d2e-484e-a9e5-07da06451069
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130216074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3130216074
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2529653931
Short name T1085
Test name
Test status
Simulation time 50834354 ps
CPU time 1.06 seconds
Started Aug 09 07:43:44 PM PDT 24
Finished Aug 09 07:43:45 PM PDT 24
Peak memory 215156 kb
Host smart-afd1c8a0-fc0e-47eb-a5ab-33727322943a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529653931 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2529653931
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.899802579
Short name T1129
Test name
Test status
Simulation time 24253576 ps
CPU time 0.88 seconds
Started Aug 09 07:43:46 PM PDT 24
Finished Aug 09 07:43:47 PM PDT 24
Peak memory 206708 kb
Host smart-c5a9cf45-a4e0-4f5b-a537-40f121a1cf75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899802579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.899802579
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4224845746
Short name T265
Test name
Test status
Simulation time 16531414 ps
CPU time 1.02 seconds
Started Aug 09 07:43:45 PM PDT 24
Finished Aug 09 07:43:46 PM PDT 24
Peak memory 207088 kb
Host smart-d9ac6b1a-4f25-465e-9a38-0182bc940ffe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224845746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.4224845746
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2937294850
Short name T1025
Test name
Test status
Simulation time 588060743 ps
CPU time 4.93 seconds
Started Aug 09 07:43:45 PM PDT 24
Finished Aug 09 07:43:50 PM PDT 24
Peak memory 215064 kb
Host smart-99c3a2dd-66d3-4f14-99b2-57e505bdc42d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937294850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2937294850
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2669868898
Short name T1054
Test name
Test status
Simulation time 53114299 ps
CPU time 1.71 seconds
Started Aug 09 07:43:46 PM PDT 24
Finished Aug 09 07:43:47 PM PDT 24
Peak memory 206924 kb
Host smart-071e7d0d-529f-48a3-a0b1-212320acc711
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669868898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2669868898
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.306636
Short name T275
Test name
Test status
Simulation time 100462698 ps
CPU time 1.25 seconds
Started Aug 09 07:43:48 PM PDT 24
Finished Aug 09 07:43:49 PM PDT 24
Peak memory 206828 kb
Host smart-c0d45a41-c5a5-48e0-9252-5d482dbaccdf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.306636
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.4144013011
Short name T1121
Test name
Test status
Simulation time 215470498 ps
CPU time 3.3 seconds
Started Aug 09 07:43:47 PM PDT 24
Finished Aug 09 07:43:51 PM PDT 24
Peak memory 206876 kb
Host smart-c324ea1b-2cde-4e0b-9359-6ad2d8388b26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144013011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.4144013011
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2457645
Short name T1107
Test name
Test status
Simulation time 13528651 ps
CPU time 0.91 seconds
Started Aug 09 07:43:42 PM PDT 24
Finished Aug 09 07:43:43 PM PDT 24
Peak memory 206780 kb
Host smart-ef04c2f4-4173-4fd6-90ea-dbffd5f4583a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2457645
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3338560875
Short name T1055
Test name
Test status
Simulation time 48392481 ps
CPU time 1.24 seconds
Started Aug 09 07:43:48 PM PDT 24
Finished Aug 09 07:43:49 PM PDT 24
Peak memory 215084 kb
Host smart-b7b99fcd-bd53-469d-b334-74e29c6864bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338560875 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3338560875
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2873320598
Short name T287
Test name
Test status
Simulation time 12778976 ps
CPU time 0.9 seconds
Started Aug 09 07:43:45 PM PDT 24
Finished Aug 09 07:43:46 PM PDT 24
Peak memory 206844 kb
Host smart-473ee73e-f99d-478b-a13e-8d4f0cb21412
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873320598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2873320598
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3184139520
Short name T1086
Test name
Test status
Simulation time 10918415 ps
CPU time 0.87 seconds
Started Aug 09 07:43:45 PM PDT 24
Finished Aug 09 07:43:46 PM PDT 24
Peak memory 206664 kb
Host smart-8d92e41f-3d4c-4ff3-baae-e18661df2950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184139520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3184139520
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2394577767
Short name T283
Test name
Test status
Simulation time 90015641 ps
CPU time 1.12 seconds
Started Aug 09 07:43:46 PM PDT 24
Finished Aug 09 07:43:48 PM PDT 24
Peak memory 206972 kb
Host smart-b10b1527-52c5-4004-a153-5090305ddc72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394577767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2394577767
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3968304743
Short name T1020
Test name
Test status
Simulation time 177358740 ps
CPU time 3.47 seconds
Started Aug 09 07:43:47 PM PDT 24
Finished Aug 09 07:43:50 PM PDT 24
Peak memory 215068 kb
Host smart-326779e6-e682-4c49-b86e-f9771500606b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968304743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3968304743
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3826277886
Short name T1070
Test name
Test status
Simulation time 95496302 ps
CPU time 1.7 seconds
Started Aug 09 07:43:46 PM PDT 24
Finished Aug 09 07:43:48 PM PDT 24
Peak memory 206884 kb
Host smart-25390166-3273-4907-b207-1c9545a2a16f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826277886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3826277886
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2994456737
Short name T1064
Test name
Test status
Simulation time 88081239 ps
CPU time 1.43 seconds
Started Aug 09 07:44:10 PM PDT 24
Finished Aug 09 07:44:12 PM PDT 24
Peak memory 215176 kb
Host smart-fef711f1-14ad-4350-a985-78c6b3074393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994456737 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2994456737
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.323997831
Short name T1003
Test name
Test status
Simulation time 15750847 ps
CPU time 1.04 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:11 PM PDT 24
Peak memory 206788 kb
Host smart-2dce3800-994f-41d4-93f1-f7abd232b000
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323997831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.323997831
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2355264723
Short name T1127
Test name
Test status
Simulation time 46734957 ps
CPU time 0.86 seconds
Started Aug 09 07:43:56 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 206504 kb
Host smart-03f09161-0341-4067-bf42-bc0838cce977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355264723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2355264723
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3525419036
Short name T285
Test name
Test status
Simulation time 52535110 ps
CPU time 1.07 seconds
Started Aug 09 07:44:03 PM PDT 24
Finished Aug 09 07:44:04 PM PDT 24
Peak memory 206888 kb
Host smart-748226c2-6aa4-4ef8-834e-b704d667fb04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525419036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3525419036
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.822559776
Short name T1026
Test name
Test status
Simulation time 431660445 ps
CPU time 4.06 seconds
Started Aug 09 07:43:56 PM PDT 24
Finished Aug 09 07:44:00 PM PDT 24
Peak memory 215364 kb
Host smart-c6de8c64-ea69-4b63-85a4-1dc6ae6ac181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822559776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.822559776
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4150333366
Short name T1038
Test name
Test status
Simulation time 279684055 ps
CPU time 2.3 seconds
Started Aug 09 07:43:56 PM PDT 24
Finished Aug 09 07:43:58 PM PDT 24
Peak memory 206976 kb
Host smart-f466e24f-7b08-463b-b286-3ba13988e695
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150333366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.4150333366
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3164101847
Short name T1124
Test name
Test status
Simulation time 104062315 ps
CPU time 1.17 seconds
Started Aug 09 07:44:07 PM PDT 24
Finished Aug 09 07:44:08 PM PDT 24
Peak memory 215168 kb
Host smart-1fa31975-2ae0-4f24-baf4-55c06cd4e22e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164101847 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3164101847
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3946934502
Short name T1024
Test name
Test status
Simulation time 11761551 ps
CPU time 0.99 seconds
Started Aug 09 07:44:03 PM PDT 24
Finished Aug 09 07:44:04 PM PDT 24
Peak memory 206740 kb
Host smart-76a47e8d-a35e-47c0-87af-ae39131b652f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946934502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3946934502
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2759889724
Short name T1021
Test name
Test status
Simulation time 11464957 ps
CPU time 0.84 seconds
Started Aug 09 07:44:05 PM PDT 24
Finished Aug 09 07:44:06 PM PDT 24
Peak memory 206708 kb
Host smart-5bd0d61e-efbb-4bdd-9efe-207454212c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759889724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2759889724
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2703024043
Short name T1041
Test name
Test status
Simulation time 33885818 ps
CPU time 1.32 seconds
Started Aug 09 07:44:03 PM PDT 24
Finished Aug 09 07:44:05 PM PDT 24
Peak memory 206856 kb
Host smart-78d2990d-0e6f-4e90-9520-365dded53289
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703024043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2703024043
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2791399545
Short name T1035
Test name
Test status
Simulation time 96128435 ps
CPU time 3.18 seconds
Started Aug 09 07:44:08 PM PDT 24
Finished Aug 09 07:44:11 PM PDT 24
Peak memory 215080 kb
Host smart-1cf4a830-dcdf-4dda-99f5-51b0669d8412
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791399545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2791399545
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.438169207
Short name T304
Test name
Test status
Simulation time 156473848 ps
CPU time 2.37 seconds
Started Aug 09 07:44:03 PM PDT 24
Finished Aug 09 07:44:06 PM PDT 24
Peak memory 206868 kb
Host smart-8617b47a-a970-4041-8c80-6d094aeb0a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438169207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.438169207
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3522678710
Short name T1015
Test name
Test status
Simulation time 58407227 ps
CPU time 1.04 seconds
Started Aug 09 07:44:03 PM PDT 24
Finished Aug 09 07:44:04 PM PDT 24
Peak memory 206904 kb
Host smart-eac13fbb-b691-4f1a-9e83-51db1b3e5e97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522678710 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3522678710
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.909575236
Short name T1017
Test name
Test status
Simulation time 63875446 ps
CPU time 0.86 seconds
Started Aug 09 07:44:02 PM PDT 24
Finished Aug 09 07:44:03 PM PDT 24
Peak memory 206656 kb
Host smart-5ef5e608-dc20-460a-b500-d3d0701aeb1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909575236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.909575236
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2024324230
Short name T1051
Test name
Test status
Simulation time 13071560 ps
CPU time 0.84 seconds
Started Aug 09 07:44:10 PM PDT 24
Finished Aug 09 07:44:12 PM PDT 24
Peak memory 206552 kb
Host smart-dbd0f334-25c4-4062-ad22-c5045158f3fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024324230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2024324230
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3387076828
Short name T1060
Test name
Test status
Simulation time 23353881 ps
CPU time 1.01 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:10 PM PDT 24
Peak memory 206916 kb
Host smart-2cee5966-e479-4881-ab33-752b1eb6fc74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387076828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3387076828
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1832834180
Short name T1089
Test name
Test status
Simulation time 86372778 ps
CPU time 1.54 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:11 PM PDT 24
Peak memory 215076 kb
Host smart-5e23f8f7-935d-4be1-b7a5-4d623cb05747
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832834180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1832834180
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2278245439
Short name T295
Test name
Test status
Simulation time 186736707 ps
CPU time 1.86 seconds
Started Aug 09 07:44:04 PM PDT 24
Finished Aug 09 07:44:07 PM PDT 24
Peak memory 207040 kb
Host smart-d1d52b86-8b09-4008-a092-5891e3f22996
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278245439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2278245439
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.277027527
Short name T1002
Test name
Test status
Simulation time 28655340 ps
CPU time 1.38 seconds
Started Aug 09 07:44:05 PM PDT 24
Finished Aug 09 07:44:07 PM PDT 24
Peak memory 215144 kb
Host smart-cda26cc7-06a6-4946-958b-33a6aaff436f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277027527 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.277027527
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3738730002
Short name T1023
Test name
Test status
Simulation time 18728906 ps
CPU time 0.92 seconds
Started Aug 09 07:44:02 PM PDT 24
Finished Aug 09 07:44:03 PM PDT 24
Peak memory 206636 kb
Host smart-e132f1ac-ef05-4603-9370-ddf8f278c877
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738730002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3738730002
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.599299187
Short name T998
Test name
Test status
Simulation time 16154039 ps
CPU time 0.97 seconds
Started Aug 09 07:44:04 PM PDT 24
Finished Aug 09 07:44:05 PM PDT 24
Peak memory 206712 kb
Host smart-f63643e1-1a57-40e5-a0e0-4a6f17e62b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599299187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.599299187
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3912013310
Short name T1125
Test name
Test status
Simulation time 85182092 ps
CPU time 1.08 seconds
Started Aug 09 07:44:06 PM PDT 24
Finished Aug 09 07:44:07 PM PDT 24
Peak memory 206980 kb
Host smart-c1d0cd24-2ef7-438c-93fb-0734839e04ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912013310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3912013310
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.370979685
Short name T1075
Test name
Test status
Simulation time 106866011 ps
CPU time 3.8 seconds
Started Aug 09 07:44:04 PM PDT 24
Finished Aug 09 07:44:08 PM PDT 24
Peak memory 215068 kb
Host smart-b1eb96a0-c3a6-4527-91ff-e85a102463da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370979685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.370979685
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1454806437
Short name T306
Test name
Test status
Simulation time 53083329 ps
CPU time 1.77 seconds
Started Aug 09 07:44:04 PM PDT 24
Finished Aug 09 07:44:06 PM PDT 24
Peak memory 215084 kb
Host smart-2272937d-4eec-47ce-bead-f6371018520d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454806437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1454806437
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2041169957
Short name T1094
Test name
Test status
Simulation time 88343719 ps
CPU time 1.21 seconds
Started Aug 09 07:44:07 PM PDT 24
Finished Aug 09 07:44:08 PM PDT 24
Peak memory 215220 kb
Host smart-0092bb1d-8096-4f77-aa7f-c34b761d3e53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041169957 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2041169957
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.281040852
Short name T1059
Test name
Test status
Simulation time 11905122 ps
CPU time 0.94 seconds
Started Aug 09 07:44:04 PM PDT 24
Finished Aug 09 07:44:05 PM PDT 24
Peak memory 206764 kb
Host smart-65da1c47-34a5-458f-a62d-d6288dc07081
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281040852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.281040852
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3832357116
Short name T1104
Test name
Test status
Simulation time 14612453 ps
CPU time 0.89 seconds
Started Aug 09 07:44:06 PM PDT 24
Finished Aug 09 07:44:07 PM PDT 24
Peak memory 206908 kb
Host smart-738100f1-3f44-410c-82b0-727c60a57fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832357116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3832357116
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2505017715
Short name T1118
Test name
Test status
Simulation time 19188104 ps
CPU time 1.09 seconds
Started Aug 09 07:44:03 PM PDT 24
Finished Aug 09 07:44:04 PM PDT 24
Peak memory 206908 kb
Host smart-678d5c38-f292-41da-bb20-d22007953b14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505017715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2505017715
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1724480258
Short name T1084
Test name
Test status
Simulation time 77591540 ps
CPU time 1.57 seconds
Started Aug 09 07:44:04 PM PDT 24
Finished Aug 09 07:44:06 PM PDT 24
Peak memory 215048 kb
Host smart-2414fa08-62af-48bc-8dfa-6ee2b01f42b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724480258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1724480258
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4033581170
Short name T997
Test name
Test status
Simulation time 34706433 ps
CPU time 1.46 seconds
Started Aug 09 07:44:07 PM PDT 24
Finished Aug 09 07:44:09 PM PDT 24
Peak memory 215408 kb
Host smart-8b8ef919-a8f9-44fb-8510-dcc3ef25c6e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033581170 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.4033581170
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.570748726
Short name T270
Test name
Test status
Simulation time 15205534 ps
CPU time 0.9 seconds
Started Aug 09 07:44:08 PM PDT 24
Finished Aug 09 07:44:09 PM PDT 24
Peak memory 206776 kb
Host smart-99cf60ee-ada1-4fc2-be93-5dd44c2e0701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570748726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.570748726
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.4284148779
Short name T1106
Test name
Test status
Simulation time 31838147 ps
CPU time 0.83 seconds
Started Aug 09 07:44:03 PM PDT 24
Finished Aug 09 07:44:04 PM PDT 24
Peak memory 206528 kb
Host smart-23b9d618-7d3e-46c9-bf26-2386f61979d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284148779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.4284148779
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3468376898
Short name T1087
Test name
Test status
Simulation time 20658327 ps
CPU time 1.05 seconds
Started Aug 09 07:44:11 PM PDT 24
Finished Aug 09 07:44:12 PM PDT 24
Peak memory 206848 kb
Host smart-9a230655-1b5a-4006-bbd0-9ff8bbd57c7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468376898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3468376898
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3612540454
Short name T1040
Test name
Test status
Simulation time 168918768 ps
CPU time 1.73 seconds
Started Aug 09 07:44:03 PM PDT 24
Finished Aug 09 07:44:05 PM PDT 24
Peak memory 215144 kb
Host smart-f82b3986-77db-459f-be71-1ad89d7cac8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612540454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3612540454
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2539121337
Short name T305
Test name
Test status
Simulation time 107695803 ps
CPU time 1.53 seconds
Started Aug 09 07:44:07 PM PDT 24
Finished Aug 09 07:44:09 PM PDT 24
Peak memory 206896 kb
Host smart-a6736679-fa51-4ffd-bc01-6b10b39b10c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539121337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2539121337
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2480793193
Short name T1090
Test name
Test status
Simulation time 24721062 ps
CPU time 1.67 seconds
Started Aug 09 07:44:05 PM PDT 24
Finished Aug 09 07:44:07 PM PDT 24
Peak memory 215248 kb
Host smart-755efc1d-a956-4022-a3b1-4c45536413c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480793193 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2480793193
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2415785300
Short name T1091
Test name
Test status
Simulation time 37883364 ps
CPU time 0.87 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:10 PM PDT 24
Peak memory 206776 kb
Host smart-7593df2f-7dde-4e26-9825-075d985ec0f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415785300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2415785300
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3600093162
Short name T1082
Test name
Test status
Simulation time 14890770 ps
CPU time 0.9 seconds
Started Aug 09 07:44:07 PM PDT 24
Finished Aug 09 07:44:08 PM PDT 24
Peak memory 206628 kb
Host smart-1cb82491-fcb1-41c6-a4ef-5e262cb3f931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600093162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3600093162
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.597301007
Short name T267
Test name
Test status
Simulation time 128057294 ps
CPU time 1.33 seconds
Started Aug 09 07:44:05 PM PDT 24
Finished Aug 09 07:44:07 PM PDT 24
Peak memory 206924 kb
Host smart-3dd65ade-c545-4900-89a0-bef21e2d852f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597301007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.597301007
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3638838450
Short name T1073
Test name
Test status
Simulation time 117612429 ps
CPU time 4.51 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:14 PM PDT 24
Peak memory 215156 kb
Host smart-7e3cf77a-2a78-41b5-95e9-9fc48231edf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638838450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3638838450
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2808378185
Short name T1112
Test name
Test status
Simulation time 280755897 ps
CPU time 2.68 seconds
Started Aug 09 07:44:02 PM PDT 24
Finished Aug 09 07:44:05 PM PDT 24
Peak memory 206960 kb
Host smart-4c89a6d9-ace2-49f2-a156-5960963e577d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808378185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2808378185
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1526654125
Short name T1012
Test name
Test status
Simulation time 26139999 ps
CPU time 1.36 seconds
Started Aug 09 07:44:03 PM PDT 24
Finished Aug 09 07:44:04 PM PDT 24
Peak memory 217968 kb
Host smart-14eb1758-1890-4428-b214-b99c77a33f78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526654125 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1526654125
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2115194102
Short name T1120
Test name
Test status
Simulation time 26934093 ps
CPU time 0.83 seconds
Started Aug 09 07:44:07 PM PDT 24
Finished Aug 09 07:44:08 PM PDT 24
Peak memory 206564 kb
Host smart-41535444-e98c-42b3-83b2-51052233b5b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115194102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2115194102
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.106023647
Short name T1110
Test name
Test status
Simulation time 106641193 ps
CPU time 0.88 seconds
Started Aug 09 07:44:02 PM PDT 24
Finished Aug 09 07:44:03 PM PDT 24
Peak memory 206884 kb
Host smart-67a51228-8a0c-47a7-9721-b254a3389b24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106023647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.106023647
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.499278627
Short name T1072
Test name
Test status
Simulation time 27590496 ps
CPU time 1.29 seconds
Started Aug 09 07:44:04 PM PDT 24
Finished Aug 09 07:44:06 PM PDT 24
Peak memory 206992 kb
Host smart-f3242fe1-182d-462a-852e-dceb4ef11fae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499278627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.499278627
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.809073467
Short name T1039
Test name
Test status
Simulation time 193059251 ps
CPU time 1.88 seconds
Started Aug 09 07:44:02 PM PDT 24
Finished Aug 09 07:44:05 PM PDT 24
Peak memory 215132 kb
Host smart-14c2affa-77cb-44b1-9863-a2c75756fea5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809073467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.809073467
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1502451456
Short name T1097
Test name
Test status
Simulation time 74043197 ps
CPU time 2.32 seconds
Started Aug 09 07:44:08 PM PDT 24
Finished Aug 09 07:44:10 PM PDT 24
Peak memory 207444 kb
Host smart-b913ab23-0e1d-4254-9b7a-4aba75ccd739
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502451456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1502451456
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2357663579
Short name T1093
Test name
Test status
Simulation time 27646102 ps
CPU time 1.36 seconds
Started Aug 09 07:44:08 PM PDT 24
Finished Aug 09 07:44:10 PM PDT 24
Peak memory 215184 kb
Host smart-fb10a054-ca6d-43b6-a82f-52a84f100f98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357663579 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2357663579
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1458943047
Short name T1103
Test name
Test status
Simulation time 42693774 ps
CPU time 0.84 seconds
Started Aug 09 07:44:10 PM PDT 24
Finished Aug 09 07:44:10 PM PDT 24
Peak memory 206616 kb
Host smart-681b95d4-b989-431d-94ea-6c98c08bc812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458943047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1458943047
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.821176683
Short name T1098
Test name
Test status
Simulation time 12343695 ps
CPU time 0.85 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:10 PM PDT 24
Peak memory 206652 kb
Host smart-0d0d1ee4-6ca5-473d-9fae-43bb49e0e35d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821176683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.821176683
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3650772478
Short name T1028
Test name
Test status
Simulation time 19229022 ps
CPU time 1.05 seconds
Started Aug 09 07:44:04 PM PDT 24
Finished Aug 09 07:44:05 PM PDT 24
Peak memory 206892 kb
Host smart-9c69f616-dea8-4d9a-b608-6a527e85fd68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650772478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3650772478
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1231818471
Short name T1081
Test name
Test status
Simulation time 603909280 ps
CPU time 5.43 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:15 PM PDT 24
Peak memory 215060 kb
Host smart-aaee51b6-b565-4893-acea-cfd02fed9c54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231818471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1231818471
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.734812154
Short name T1076
Test name
Test status
Simulation time 101538942 ps
CPU time 2.64 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:12 PM PDT 24
Peak memory 206856 kb
Host smart-d82e4675-3cda-4b01-8901-bd97a9d13f49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734812154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.734812154
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1655180288
Short name T1007
Test name
Test status
Simulation time 21179044 ps
CPU time 1.3 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:11 PM PDT 24
Peak memory 215344 kb
Host smart-0f76198b-1ca0-4cfb-86d5-c54e76afca44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655180288 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1655180288
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3101966072
Short name T286
Test name
Test status
Simulation time 37642644 ps
CPU time 0.83 seconds
Started Aug 09 07:44:11 PM PDT 24
Finished Aug 09 07:44:12 PM PDT 24
Peak memory 206620 kb
Host smart-9cf72832-62ef-4df5-afc6-f862fa25b478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101966072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3101966072
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2128581280
Short name T1033
Test name
Test status
Simulation time 37288024 ps
CPU time 0.84 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:10 PM PDT 24
Peak memory 206516 kb
Host smart-12326c87-35d0-48d7-8bea-e46adcecd890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128581280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2128581280
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.737425104
Short name T284
Test name
Test status
Simulation time 31788177 ps
CPU time 1.15 seconds
Started Aug 09 07:44:07 PM PDT 24
Finished Aug 09 07:44:08 PM PDT 24
Peak memory 207176 kb
Host smart-7b5f0369-aed7-4ca7-8eff-a3cd9f6e1f89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737425104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.737425104
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1726951593
Short name T1032
Test name
Test status
Simulation time 123927294 ps
CPU time 2.42 seconds
Started Aug 09 07:44:11 PM PDT 24
Finished Aug 09 07:44:14 PM PDT 24
Peak memory 215088 kb
Host smart-8c562152-0f49-4bf6-88a0-9b3474daca0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726951593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1726951593
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3287377208
Short name T1062
Test name
Test status
Simulation time 99658981 ps
CPU time 2.72 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:12 PM PDT 24
Peak memory 206972 kb
Host smart-05e46888-51d9-4ac2-a7e9-c990cccd87e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287377208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3287377208
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3593250514
Short name T274
Test name
Test status
Simulation time 18747946 ps
CPU time 1.19 seconds
Started Aug 09 07:43:42 PM PDT 24
Finished Aug 09 07:43:43 PM PDT 24
Peak memory 206908 kb
Host smart-f33fdb06-d853-4385-8a1d-03a132f47afe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593250514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3593250514
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1845295115
Short name T1045
Test name
Test status
Simulation time 359230710 ps
CPU time 2.08 seconds
Started Aug 09 07:43:48 PM PDT 24
Finished Aug 09 07:43:51 PM PDT 24
Peak memory 206840 kb
Host smart-9eac72b7-3bcf-4c6e-b3d5-c111072f7013
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845295115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1845295115
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.228186976
Short name T279
Test name
Test status
Simulation time 13178905 ps
CPU time 0.86 seconds
Started Aug 09 07:43:46 PM PDT 24
Finished Aug 09 07:43:47 PM PDT 24
Peak memory 206784 kb
Host smart-64a877eb-bbc2-415a-be40-2c93f842f50d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228186976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.228186976
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3686109120
Short name T1100
Test name
Test status
Simulation time 76304174 ps
CPU time 1.11 seconds
Started Aug 09 07:43:46 PM PDT 24
Finished Aug 09 07:43:47 PM PDT 24
Peak memory 215144 kb
Host smart-f36cf8fb-0f75-4907-a1cc-28e850ae19fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686109120 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3686109120
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1148016382
Short name T1031
Test name
Test status
Simulation time 125711830 ps
CPU time 0.9 seconds
Started Aug 09 07:43:46 PM PDT 24
Finished Aug 09 07:43:47 PM PDT 24
Peak memory 206660 kb
Host smart-9744753d-7ceb-4617-aa80-9c05caabf924
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148016382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1148016382
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2603315194
Short name T1000
Test name
Test status
Simulation time 48448945 ps
CPU time 0.87 seconds
Started Aug 09 07:43:44 PM PDT 24
Finished Aug 09 07:43:44 PM PDT 24
Peak memory 206656 kb
Host smart-5f2365c3-d67f-4ee2-a9cb-fb4b60969202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603315194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2603315194
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2036685173
Short name T1063
Test name
Test status
Simulation time 70919644 ps
CPU time 1.02 seconds
Started Aug 09 07:43:46 PM PDT 24
Finished Aug 09 07:43:47 PM PDT 24
Peak memory 206960 kb
Host smart-00a44357-8d77-49f4-a704-a697faf46353
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036685173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2036685173
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1049994848
Short name T1078
Test name
Test status
Simulation time 52068384 ps
CPU time 1.76 seconds
Started Aug 09 07:43:47 PM PDT 24
Finished Aug 09 07:43:49 PM PDT 24
Peak memory 215192 kb
Host smart-e0b31171-495d-4e0e-982c-3265e7c03a69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049994848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1049994848
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1920191470
Short name T293
Test name
Test status
Simulation time 100578082 ps
CPU time 1.76 seconds
Started Aug 09 07:43:48 PM PDT 24
Finished Aug 09 07:43:49 PM PDT 24
Peak memory 207108 kb
Host smart-90f2496a-a2dc-436f-ad1f-5f7221eb1fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920191470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1920191470
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1968690642
Short name T1014
Test name
Test status
Simulation time 38372668 ps
CPU time 0.83 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:11 PM PDT 24
Peak memory 206496 kb
Host smart-84536d40-577d-4464-a4da-c0a01a41bebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968690642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1968690642
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2613619037
Short name T1052
Test name
Test status
Simulation time 14083828 ps
CPU time 0.9 seconds
Started Aug 09 07:44:13 PM PDT 24
Finished Aug 09 07:44:13 PM PDT 24
Peak memory 206724 kb
Host smart-75496452-ade3-4fc7-a731-06496d19f8a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613619037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2613619037
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.55039742
Short name T1036
Test name
Test status
Simulation time 17358587 ps
CPU time 0.97 seconds
Started Aug 09 07:44:13 PM PDT 24
Finished Aug 09 07:44:15 PM PDT 24
Peak memory 206676 kb
Host smart-66a69da6-b5d3-4f39-9046-9a98feef9cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55039742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.55039742
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3885129274
Short name T1071
Test name
Test status
Simulation time 16386069 ps
CPU time 0.96 seconds
Started Aug 09 07:44:13 PM PDT 24
Finished Aug 09 07:44:14 PM PDT 24
Peak memory 206664 kb
Host smart-9c0827e4-ba4d-433e-ad9d-cecb5569abb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885129274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3885129274
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.534001872
Short name T999
Test name
Test status
Simulation time 26619619 ps
CPU time 0.89 seconds
Started Aug 09 07:44:13 PM PDT 24
Finished Aug 09 07:44:14 PM PDT 24
Peak memory 206704 kb
Host smart-ca6d0379-789f-456e-8bc1-4c41d9bde12d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534001872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.534001872
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.971538557
Short name T1044
Test name
Test status
Simulation time 23470912 ps
CPU time 0.83 seconds
Started Aug 09 07:44:12 PM PDT 24
Finished Aug 09 07:44:13 PM PDT 24
Peak memory 206552 kb
Host smart-b7689c5f-6ff8-4183-a6bf-a7398966a967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971538557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.971538557
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4033026287
Short name T1126
Test name
Test status
Simulation time 65037043 ps
CPU time 0.84 seconds
Started Aug 09 07:44:14 PM PDT 24
Finished Aug 09 07:44:15 PM PDT 24
Peak memory 206668 kb
Host smart-e790b4ed-db02-4ba1-bd37-736c83ca8aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033026287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4033026287
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3631673833
Short name T1009
Test name
Test status
Simulation time 18642418 ps
CPU time 0.92 seconds
Started Aug 09 07:44:13 PM PDT 24
Finished Aug 09 07:44:14 PM PDT 24
Peak memory 206704 kb
Host smart-a540395b-9712-4914-af9b-c15a72461a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631673833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3631673833
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2158316021
Short name T996
Test name
Test status
Simulation time 16593816 ps
CPU time 0.95 seconds
Started Aug 09 07:44:12 PM PDT 24
Finished Aug 09 07:44:13 PM PDT 24
Peak memory 206700 kb
Host smart-c04b0f43-7a24-4097-9fb2-08354f4bbbdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158316021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2158316021
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2589396030
Short name T1013
Test name
Test status
Simulation time 26051037 ps
CPU time 0.98 seconds
Started Aug 09 07:44:13 PM PDT 24
Finished Aug 09 07:44:14 PM PDT 24
Peak memory 206668 kb
Host smart-9e22cc2d-3905-43b8-9515-1e179f6a0232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589396030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2589396030
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1218115398
Short name T281
Test name
Test status
Simulation time 15073648 ps
CPU time 1.05 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 206876 kb
Host smart-1bf598e2-d489-448b-a54d-1c0768058a39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218115398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1218115398
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.942143616
Short name T1018
Test name
Test status
Simulation time 278991336 ps
CPU time 3.68 seconds
Started Aug 09 07:43:54 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 206820 kb
Host smart-d7af0a4a-3128-476d-a425-e5ebe00bdc75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942143616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.942143616
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.637015397
Short name T1066
Test name
Test status
Simulation time 37900339 ps
CPU time 0.94 seconds
Started Aug 09 07:43:46 PM PDT 24
Finished Aug 09 07:43:47 PM PDT 24
Peak memory 206828 kb
Host smart-325d7e91-9cb0-48a7-95b8-3bd5d0465548
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637015397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.637015397
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.929348940
Short name T1096
Test name
Test status
Simulation time 20598244 ps
CPU time 1.37 seconds
Started Aug 09 07:43:54 PM PDT 24
Finished Aug 09 07:43:56 PM PDT 24
Peak memory 215116 kb
Host smart-4c9666ca-ced7-4e8c-9836-94f80372d669
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929348940 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.929348940
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3123595628
Short name T268
Test name
Test status
Simulation time 14125130 ps
CPU time 0.88 seconds
Started Aug 09 07:43:48 PM PDT 24
Finished Aug 09 07:43:49 PM PDT 24
Peak memory 206828 kb
Host smart-5f452ad0-e5eb-40bd-a8b2-0e2880d92fc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123595628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3123595628
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1831846175
Short name T1011
Test name
Test status
Simulation time 12419409 ps
CPU time 0.91 seconds
Started Aug 09 07:43:43 PM PDT 24
Finished Aug 09 07:43:44 PM PDT 24
Peak memory 206676 kb
Host smart-1b48122d-6e7f-40ce-867d-70d33ab33ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831846175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1831846175
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2555226472
Short name T1119
Test name
Test status
Simulation time 82374145 ps
CPU time 1.09 seconds
Started Aug 09 07:43:54 PM PDT 24
Finished Aug 09 07:43:55 PM PDT 24
Peak memory 206904 kb
Host smart-754306e0-1200-4813-8357-27cf9e159ff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555226472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2555226472
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.438475237
Short name T1057
Test name
Test status
Simulation time 251931986 ps
CPU time 2.73 seconds
Started Aug 09 07:43:45 PM PDT 24
Finished Aug 09 07:43:48 PM PDT 24
Peak memory 215088 kb
Host smart-15d4de62-ad8b-4159-9424-50016d3f36d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438475237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.438475237
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1680816025
Short name T1048
Test name
Test status
Simulation time 386592446 ps
CPU time 2.65 seconds
Started Aug 09 07:43:47 PM PDT 24
Finished Aug 09 07:43:50 PM PDT 24
Peak memory 206888 kb
Host smart-4043cc4f-0823-40ea-ba16-a117063b23ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680816025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1680816025
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3291882410
Short name T1043
Test name
Test status
Simulation time 15993655 ps
CPU time 0.86 seconds
Started Aug 09 07:44:12 PM PDT 24
Finished Aug 09 07:44:13 PM PDT 24
Peak memory 206676 kb
Host smart-3b6b4c7b-15f0-4e31-b28a-44f45e4f2d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291882410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3291882410
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2159856401
Short name T1001
Test name
Test status
Simulation time 147691916 ps
CPU time 0.89 seconds
Started Aug 09 07:44:12 PM PDT 24
Finished Aug 09 07:44:13 PM PDT 24
Peak memory 206700 kb
Host smart-69030c2e-8eb9-4432-9233-0f3bd806a9b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159856401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2159856401
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3573546667
Short name T1122
Test name
Test status
Simulation time 20410224 ps
CPU time 0.83 seconds
Started Aug 09 07:44:10 PM PDT 24
Finished Aug 09 07:44:11 PM PDT 24
Peak memory 206516 kb
Host smart-e79a8dbe-501b-41af-b098-d51e2bb114dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573546667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3573546667
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2247850054
Short name T1016
Test name
Test status
Simulation time 16528678 ps
CPU time 0.89 seconds
Started Aug 09 07:44:14 PM PDT 24
Finished Aug 09 07:44:16 PM PDT 24
Peak memory 206684 kb
Host smart-14e0bb6f-bacb-4f9a-a57f-cfc6b779e4fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247850054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2247850054
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1920609157
Short name T1004
Test name
Test status
Simulation time 14386818 ps
CPU time 0.9 seconds
Started Aug 09 07:44:11 PM PDT 24
Finished Aug 09 07:44:13 PM PDT 24
Peak memory 206692 kb
Host smart-e51b9072-9357-453b-9bf7-e6d5da7ce0a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920609157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1920609157
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1458905646
Short name T1099
Test name
Test status
Simulation time 23573365 ps
CPU time 0.89 seconds
Started Aug 09 07:44:12 PM PDT 24
Finished Aug 09 07:44:13 PM PDT 24
Peak memory 206772 kb
Host smart-3b8e4b65-6425-491f-9b8e-6e2888a89834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458905646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1458905646
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2924283143
Short name T1115
Test name
Test status
Simulation time 28599494 ps
CPU time 0.93 seconds
Started Aug 09 07:44:12 PM PDT 24
Finished Aug 09 07:44:13 PM PDT 24
Peak memory 206660 kb
Host smart-436f2721-d1f1-4f9a-b06c-776b7123fb39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924283143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2924283143
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.4277121471
Short name T1114
Test name
Test status
Simulation time 11164853 ps
CPU time 0.89 seconds
Started Aug 09 07:44:15 PM PDT 24
Finished Aug 09 07:44:16 PM PDT 24
Peak memory 206656 kb
Host smart-92565e0f-39ab-447d-bddf-d177e779f5a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277121471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.4277121471
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.687845324
Short name T1042
Test name
Test status
Simulation time 37852134 ps
CPU time 0.92 seconds
Started Aug 09 07:44:14 PM PDT 24
Finished Aug 09 07:44:15 PM PDT 24
Peak memory 206700 kb
Host smart-513cdfd8-d882-494d-bd8f-101d075b6c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687845324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.687845324
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.4285219317
Short name T1095
Test name
Test status
Simulation time 48710718 ps
CPU time 0.91 seconds
Started Aug 09 07:44:13 PM PDT 24
Finished Aug 09 07:44:14 PM PDT 24
Peak memory 206656 kb
Host smart-08079797-f219-41b4-952b-f8bf7c6f6095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285219317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.4285219317
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.165443392
Short name T278
Test name
Test status
Simulation time 65267328 ps
CPU time 1.23 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:56 PM PDT 24
Peak memory 206804 kb
Host smart-6412378c-ce2a-44bc-8dc6-b4e465f0adda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165443392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.165443392
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1984613287
Short name T277
Test name
Test status
Simulation time 36227669 ps
CPU time 2.09 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:58 PM PDT 24
Peak memory 206880 kb
Host smart-c6d7f4fd-ac7f-4f32-afc3-b6a7eca71291
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984613287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1984613287
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.817238920
Short name T272
Test name
Test status
Simulation time 12743224 ps
CPU time 0.89 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:56 PM PDT 24
Peak memory 206756 kb
Host smart-f54f011d-47a5-408c-a179-ff64e9be649f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817238920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.817238920
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4257779875
Short name T1006
Test name
Test status
Simulation time 26239936 ps
CPU time 1.41 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 215204 kb
Host smart-13969040-ed56-4c51-ae13-362cd3185a24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257779875 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.4257779875
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3112797316
Short name T271
Test name
Test status
Simulation time 19412000 ps
CPU time 0.97 seconds
Started Aug 09 07:43:56 PM PDT 24
Finished Aug 09 07:43:58 PM PDT 24
Peak memory 206832 kb
Host smart-614d6f2a-170a-44dc-881f-95fb0022afb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112797316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3112797316
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.4294725868
Short name T1010
Test name
Test status
Simulation time 28225390 ps
CPU time 0.83 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:56 PM PDT 24
Peak memory 206708 kb
Host smart-1fc4e870-82eb-4bea-b5bc-4cf65aec50ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294725868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.4294725868
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1298272115
Short name T1058
Test name
Test status
Simulation time 120144692 ps
CPU time 1.38 seconds
Started Aug 09 07:43:57 PM PDT 24
Finished Aug 09 07:43:58 PM PDT 24
Peak memory 206868 kb
Host smart-03a582d1-c193-462a-b209-80481141067a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298272115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1298272115
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3047367845
Short name T1101
Test name
Test status
Simulation time 103571250 ps
CPU time 2.06 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 215284 kb
Host smart-ce5937f1-cca3-45e2-a4b4-8643af9e69c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047367845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3047367845
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1113977062
Short name T1053
Test name
Test status
Simulation time 50127065 ps
CPU time 1.69 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 206940 kb
Host smart-ade7f107-b19e-4352-a9c5-73192d5ce4ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113977062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1113977062
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2988193009
Short name T1005
Test name
Test status
Simulation time 13502319 ps
CPU time 0.89 seconds
Started Aug 09 07:44:11 PM PDT 24
Finished Aug 09 07:44:12 PM PDT 24
Peak memory 206692 kb
Host smart-e2d28283-552d-4884-9eae-eb4e7de627e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988193009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2988193009
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.4054639931
Short name T1117
Test name
Test status
Simulation time 74247350 ps
CPU time 0.91 seconds
Started Aug 09 07:44:11 PM PDT 24
Finished Aug 09 07:44:13 PM PDT 24
Peak memory 206676 kb
Host smart-91f8a543-f612-4993-a89c-29d551f0bac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054639931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.4054639931
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.4277664198
Short name T1083
Test name
Test status
Simulation time 76390617 ps
CPU time 0.88 seconds
Started Aug 09 07:44:13 PM PDT 24
Finished Aug 09 07:44:14 PM PDT 24
Peak memory 206528 kb
Host smart-2b416f6f-d592-4d6c-8c03-b093b5976d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277664198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.4277664198
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2296440942
Short name T1065
Test name
Test status
Simulation time 17967824 ps
CPU time 0.91 seconds
Started Aug 09 07:44:12 PM PDT 24
Finished Aug 09 07:44:13 PM PDT 24
Peak memory 206540 kb
Host smart-882f219c-60c5-468a-aa65-6480174b7be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296440942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2296440942
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.62521627
Short name T1030
Test name
Test status
Simulation time 52025570 ps
CPU time 0.85 seconds
Started Aug 09 07:44:09 PM PDT 24
Finished Aug 09 07:44:10 PM PDT 24
Peak memory 206676 kb
Host smart-8b8b0a91-46c8-4d19-99ed-5e275b9e197c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62521627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.62521627
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2277551193
Short name T1111
Test name
Test status
Simulation time 27659285 ps
CPU time 0.86 seconds
Started Aug 09 07:44:13 PM PDT 24
Finished Aug 09 07:44:14 PM PDT 24
Peak memory 206688 kb
Host smart-a7083f89-4ce9-451d-9f97-17e899804ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277551193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2277551193
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2944944195
Short name T1102
Test name
Test status
Simulation time 13366104 ps
CPU time 0.91 seconds
Started Aug 09 07:44:11 PM PDT 24
Finished Aug 09 07:44:12 PM PDT 24
Peak memory 206684 kb
Host smart-1dfe7ca0-a5bb-4a41-87de-8b96414304fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944944195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2944944195
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.925955523
Short name T1092
Test name
Test status
Simulation time 31901618 ps
CPU time 0.9 seconds
Started Aug 09 07:44:10 PM PDT 24
Finished Aug 09 07:44:11 PM PDT 24
Peak memory 206660 kb
Host smart-f435cb50-d3dc-45b2-ae8f-edd19bffd567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925955523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.925955523
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1491340794
Short name T1019
Test name
Test status
Simulation time 106972854 ps
CPU time 0.91 seconds
Started Aug 09 07:44:14 PM PDT 24
Finished Aug 09 07:44:15 PM PDT 24
Peak memory 206528 kb
Host smart-2e28e0f6-cfe5-43cc-967c-e93b2d6d1946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491340794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1491340794
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3569274016
Short name T1069
Test name
Test status
Simulation time 23085082 ps
CPU time 0.98 seconds
Started Aug 09 07:44:13 PM PDT 24
Finished Aug 09 07:44:14 PM PDT 24
Peak memory 206628 kb
Host smart-03be91a0-102e-4842-991d-218640c05980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569274016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3569274016
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3729267307
Short name T1067
Test name
Test status
Simulation time 27619583 ps
CPU time 1.6 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 215148 kb
Host smart-7e69c221-0fb2-4d58-93bd-8094d5ddcb3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729267307 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3729267307
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2068848285
Short name T1049
Test name
Test status
Simulation time 28063390 ps
CPU time 0.79 seconds
Started Aug 09 07:43:56 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 206548 kb
Host smart-0b48c6be-c832-47d1-8cd3-faf97061c7ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068848285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2068848285
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.729805064
Short name T1034
Test name
Test status
Simulation time 58862439 ps
CPU time 1.18 seconds
Started Aug 09 07:43:57 PM PDT 24
Finished Aug 09 07:43:59 PM PDT 24
Peak memory 206976 kb
Host smart-3f6991e7-5d36-46ca-900e-0faebeae706b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729805064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.729805064
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2926630333
Short name T1022
Test name
Test status
Simulation time 88968930 ps
CPU time 1.87 seconds
Started Aug 09 07:43:53 PM PDT 24
Finished Aug 09 07:43:55 PM PDT 24
Peak memory 215140 kb
Host smart-5293ad22-8f4a-417b-9bc6-4bc12a62a32c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926630333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2926630333
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.792664880
Short name T1056
Test name
Test status
Simulation time 198959685 ps
CPU time 1.71 seconds
Started Aug 09 07:43:53 PM PDT 24
Finished Aug 09 07:43:55 PM PDT 24
Peak memory 206860 kb
Host smart-86b974e2-8845-430a-816e-3dd722cf4309
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792664880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.792664880
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3760501307
Short name T1050
Test name
Test status
Simulation time 43989353 ps
CPU time 1.17 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 216544 kb
Host smart-e3c956c9-4f78-4b98-a5a1-dd424c0447e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760501307 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3760501307
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3605335394
Short name T282
Test name
Test status
Simulation time 33148904 ps
CPU time 0.88 seconds
Started Aug 09 07:43:57 PM PDT 24
Finished Aug 09 07:43:58 PM PDT 24
Peak memory 206844 kb
Host smart-3f7bd93f-afe1-43cb-beb5-6dc851d070b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605335394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3605335394
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.245016517
Short name T1077
Test name
Test status
Simulation time 13326967 ps
CPU time 0.88 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:56 PM PDT 24
Peak memory 206656 kb
Host smart-231aa189-a966-4c63-9ecf-e417746150b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245016517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.245016517
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.227707688
Short name T1027
Test name
Test status
Simulation time 63235696 ps
CPU time 1.17 seconds
Started Aug 09 07:43:54 PM PDT 24
Finished Aug 09 07:43:55 PM PDT 24
Peak memory 206916 kb
Host smart-798b1647-a2de-4203-beb9-3d4b3b9d19e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227707688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.227707688
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2374882806
Short name T1037
Test name
Test status
Simulation time 292032001 ps
CPU time 2.74 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 215088 kb
Host smart-a1b703ce-d0e2-4fdf-9b2c-d7a556758564
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374882806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2374882806
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1409144563
Short name T294
Test name
Test status
Simulation time 394441382 ps
CPU time 2.42 seconds
Started Aug 09 07:44:02 PM PDT 24
Finished Aug 09 07:44:04 PM PDT 24
Peak memory 206820 kb
Host smart-7df207ac-fec5-40d7-b1fb-dc88cc7f887c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409144563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1409144563
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1278544502
Short name T1130
Test name
Test status
Simulation time 25751784 ps
CPU time 1.7 seconds
Started Aug 09 07:43:53 PM PDT 24
Finished Aug 09 07:43:55 PM PDT 24
Peak memory 215180 kb
Host smart-91e68f6e-a81f-404b-8430-299dce9f411a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278544502 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1278544502
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3030853006
Short name T1123
Test name
Test status
Simulation time 142378166 ps
CPU time 0.83 seconds
Started Aug 09 07:43:54 PM PDT 24
Finished Aug 09 07:43:55 PM PDT 24
Peak memory 206616 kb
Host smart-c4767dc5-4eb7-464b-8e27-3cdb2e376015
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030853006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3030853006
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3237430560
Short name T1113
Test name
Test status
Simulation time 26953315 ps
CPU time 0.88 seconds
Started Aug 09 07:43:57 PM PDT 24
Finished Aug 09 07:43:58 PM PDT 24
Peak memory 206664 kb
Host smart-f731de12-d1da-47e4-8220-fac415f5cc92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237430560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3237430560
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3397922013
Short name T1061
Test name
Test status
Simulation time 34708282 ps
CPU time 1.07 seconds
Started Aug 09 07:43:57 PM PDT 24
Finished Aug 09 07:43:58 PM PDT 24
Peak memory 206908 kb
Host smart-04c026ad-6c70-4e4e-a8f4-774caac4ce4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397922013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3397922013
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2659404450
Short name T1080
Test name
Test status
Simulation time 111814321 ps
CPU time 2.23 seconds
Started Aug 09 07:43:57 PM PDT 24
Finished Aug 09 07:43:59 PM PDT 24
Peak memory 215056 kb
Host smart-cb39e9c9-9cdf-4a68-9d49-5a1b2fcdc111
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659404450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2659404450
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.492295810
Short name T1108
Test name
Test status
Simulation time 73998425 ps
CPU time 2.1 seconds
Started Aug 09 07:43:56 PM PDT 24
Finished Aug 09 07:43:59 PM PDT 24
Peak memory 215096 kb
Host smart-5a0c4d1d-fa1d-481d-a42b-53fc44f43213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492295810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.492295810
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3651669235
Short name T1068
Test name
Test status
Simulation time 71051050 ps
CPU time 1.12 seconds
Started Aug 09 07:43:57 PM PDT 24
Finished Aug 09 07:43:58 PM PDT 24
Peak memory 215144 kb
Host smart-886089b0-1d3f-4f90-8ef6-52998ca1fb59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651669235 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3651669235
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2763052979
Short name T269
Test name
Test status
Simulation time 24717161 ps
CPU time 0.92 seconds
Started Aug 09 07:43:54 PM PDT 24
Finished Aug 09 07:43:55 PM PDT 24
Peak memory 206836 kb
Host smart-27472712-7f45-4534-b958-8a5d8567ffca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763052979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2763052979
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3219292213
Short name T1116
Test name
Test status
Simulation time 140733275 ps
CPU time 0.84 seconds
Started Aug 09 07:43:56 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 206660 kb
Host smart-494b90b3-5aa8-49e0-9ed9-336d28242ad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219292213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3219292213
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.823477091
Short name T1047
Test name
Test status
Simulation time 68301500 ps
CPU time 1.21 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:56 PM PDT 24
Peak memory 206908 kb
Host smart-0a302c17-4e91-4f94-8ee2-03d3000943ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823477091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.823477091
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1114256290
Short name T1128
Test name
Test status
Simulation time 85417232 ps
CPU time 3.27 seconds
Started Aug 09 07:43:53 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 215136 kb
Host smart-d48c7db8-9d3d-4572-be75-b635e5345ddd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114256290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1114256290
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1957328204
Short name T1109
Test name
Test status
Simulation time 106021581 ps
CPU time 1.59 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 206956 kb
Host smart-eeeb311f-7d76-4d90-901b-ab12274c313e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957328204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1957328204
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.141644337
Short name T1008
Test name
Test status
Simulation time 19973296 ps
CPU time 1.36 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 215184 kb
Host smart-f10cec9b-d9fe-4dc6-8a5e-320b84671744
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141644337 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.141644337
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1579901333
Short name T1046
Test name
Test status
Simulation time 14049299 ps
CPU time 0.87 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:56 PM PDT 24
Peak memory 206708 kb
Host smart-dfb17135-8e1d-4b3f-bff0-5e321ef8d0ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579901333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1579901333
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3201962860
Short name T1074
Test name
Test status
Simulation time 24779832 ps
CPU time 0.86 seconds
Started Aug 09 07:43:56 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 206668 kb
Host smart-0f48e233-01f2-4b67-b693-0a56dc1b6c99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201962860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3201962860
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.234767760
Short name T1029
Test name
Test status
Simulation time 24108963 ps
CPU time 0.99 seconds
Started Aug 09 07:43:57 PM PDT 24
Finished Aug 09 07:43:58 PM PDT 24
Peak memory 206924 kb
Host smart-b4c161ed-f723-4973-af20-2f2307a7caa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234767760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.234767760
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2038995951
Short name T1079
Test name
Test status
Simulation time 128585242 ps
CPU time 2.44 seconds
Started Aug 09 07:43:54 PM PDT 24
Finished Aug 09 07:43:57 PM PDT 24
Peak memory 215104 kb
Host smart-dd8a09c1-8693-487b-9552-7f3c05717836
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038995951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2038995951
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.142327234
Short name T1105
Test name
Test status
Simulation time 579849641 ps
CPU time 3.1 seconds
Started Aug 09 07:43:55 PM PDT 24
Finished Aug 09 07:43:59 PM PDT 24
Peak memory 207068 kb
Host smart-a61349f8-174e-4fce-9e0c-8f360c948101
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142327234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.142327234
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.2346222330
Short name T988
Test name
Test status
Simulation time 13153298 ps
CPU time 0.91 seconds
Started Aug 09 07:50:40 PM PDT 24
Finished Aug 09 07:50:41 PM PDT 24
Peak memory 215176 kb
Host smart-ff23144c-ece5-479e-9819-1dda3b5166cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346222330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2346222330
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2944464570
Short name T3
Test name
Test status
Simulation time 13144839 ps
CPU time 0.86 seconds
Started Aug 09 07:50:39 PM PDT 24
Finished Aug 09 07:50:40 PM PDT 24
Peak memory 216468 kb
Host smart-f87af64a-316d-407e-ba13-1fb31b22c251
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944464570 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2944464570
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1352785011
Short name T684
Test name
Test status
Simulation time 115422795 ps
CPU time 1.08 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 07:50:42 PM PDT 24
Peak memory 217008 kb
Host smart-b4cbfb2b-2390-45b1-bf3d-3707d5c95b83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352785011 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1352785011
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.767369876
Short name T863
Test name
Test status
Simulation time 28841159 ps
CPU time 0.88 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 07:50:42 PM PDT 24
Peak memory 218572 kb
Host smart-91d0befe-e0ba-4dae-8b2e-ffb53a9fcdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767369876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.767369876
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.85943782
Short name T636
Test name
Test status
Simulation time 42145821 ps
CPU time 1.26 seconds
Started Aug 09 07:50:34 PM PDT 24
Finished Aug 09 07:50:35 PM PDT 24
Peak memory 218180 kb
Host smart-d0064e7a-2ba2-496f-abcd-07f5d8c348e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85943782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.85943782
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.1094646538
Short name T32
Test name
Test status
Simulation time 19032622 ps
CPU time 1.04 seconds
Started Aug 09 07:50:36 PM PDT 24
Finished Aug 09 07:50:37 PM PDT 24
Peak memory 207064 kb
Host smart-794d9ea8-a2a4-4a1d-ae73-b658975069d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094646538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1094646538
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.734152339
Short name T20
Test name
Test status
Simulation time 1508758896 ps
CPU time 5.19 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 07:50:46 PM PDT 24
Peak memory 239932 kb
Host smart-6b443923-8ffb-4afa-87ef-da3d517b2b63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734152339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.734152339
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2505482474
Short name T372
Test name
Test status
Simulation time 21215206 ps
CPU time 1 seconds
Started Aug 09 07:50:34 PM PDT 24
Finished Aug 09 07:50:35 PM PDT 24
Peak memory 214828 kb
Host smart-de0ea334-e872-44f0-8cf9-61178feb746e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505482474 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2505482474
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1420587474
Short name T946
Test name
Test status
Simulation time 616386144 ps
CPU time 3.31 seconds
Started Aug 09 07:50:35 PM PDT 24
Finished Aug 09 07:50:38 PM PDT 24
Peak memory 217208 kb
Host smart-b984f17c-ec43-45fa-88ac-4dff08fe87d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420587474 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1420587474
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.1638809453
Short name T807
Test name
Test status
Simulation time 44914702 ps
CPU time 1.25 seconds
Started Aug 09 07:50:38 PM PDT 24
Finished Aug 09 07:50:39 PM PDT 24
Peak memory 220632 kb
Host smart-5169ca40-dbe0-4a6d-b4c5-6763d6932720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638809453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1638809453
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1461633598
Short name T871
Test name
Test status
Simulation time 34265294 ps
CPU time 1.31 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 07:50:43 PM PDT 24
Peak memory 216984 kb
Host smart-d3ea1ee6-d9d2-414f-a7e8-6f0483013416
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461633598 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1461633598
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.661056874
Short name T175
Test name
Test status
Simulation time 19388009 ps
CPU time 1.11 seconds
Started Aug 09 07:50:39 PM PDT 24
Finished Aug 09 07:50:40 PM PDT 24
Peak memory 224148 kb
Host smart-c41a3578-b05e-4cf7-b636-649eb739dbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661056874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.661056874
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3695624966
Short name T387
Test name
Test status
Simulation time 65584820 ps
CPU time 1.3 seconds
Started Aug 09 07:50:38 PM PDT 24
Finished Aug 09 07:50:39 PM PDT 24
Peak memory 217456 kb
Host smart-fbcc2721-fcea-4a59-a30d-32dfc40c6f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695624966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3695624966
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2009397463
Short name T75
Test name
Test status
Simulation time 261405035 ps
CPU time 4.94 seconds
Started Aug 09 07:50:39 PM PDT 24
Finished Aug 09 07:50:44 PM PDT 24
Peak memory 239904 kb
Host smart-6c7783b9-9d51-466f-953e-907bd48e7b35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009397463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2009397463
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2470337371
Short name T854
Test name
Test status
Simulation time 18751920 ps
CPU time 1.03 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 07:50:42 PM PDT 24
Peak memory 207120 kb
Host smart-39538a73-c4d3-47ee-967d-daa2bae7a895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470337371 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2470337371
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2432665079
Short name T336
Test name
Test status
Simulation time 291314528 ps
CPU time 6.26 seconds
Started Aug 09 07:50:42 PM PDT 24
Finished Aug 09 07:50:49 PM PDT 24
Peak memory 215292 kb
Host smart-c68cf1df-65b6-4f10-a72a-7782b574ea58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432665079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2432665079
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.166647934
Short name T246
Test name
Test status
Simulation time 269577936605 ps
CPU time 1459.24 seconds
Started Aug 09 07:50:40 PM PDT 24
Finished Aug 09 08:15:00 PM PDT 24
Peak memory 230928 kb
Host smart-e01ef084-4c4c-4d34-8fa0-ac4bb29b7415
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166647934 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.166647934
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3168246138
Short name T866
Test name
Test status
Simulation time 38397368 ps
CPU time 1.25 seconds
Started Aug 09 07:50:56 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 219472 kb
Host smart-33046fec-5eaf-4254-a660-3ba04f386822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168246138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3168246138
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3299581182
Short name T503
Test name
Test status
Simulation time 21677456 ps
CPU time 0.86 seconds
Started Aug 09 07:50:57 PM PDT 24
Finished Aug 09 07:50:58 PM PDT 24
Peak memory 206724 kb
Host smart-d13d324b-50b9-418f-9b69-de3fe2b71964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299581182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3299581182
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1949445908
Short name T744
Test name
Test status
Simulation time 76275914 ps
CPU time 0.84 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 07:50:55 PM PDT 24
Peak memory 216456 kb
Host smart-06c12387-56e0-44f7-9870-341c5210b8b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949445908 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1949445908
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3028490126
Short name T88
Test name
Test status
Simulation time 135791041 ps
CPU time 1.09 seconds
Started Aug 09 07:50:56 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 218728 kb
Host smart-a24bdd99-1d80-49fb-83e0-6b20a4318201
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028490126 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3028490126
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2313549643
Short name T58
Test name
Test status
Simulation time 35589318 ps
CPU time 1.07 seconds
Started Aug 09 07:50:57 PM PDT 24
Finished Aug 09 07:50:59 PM PDT 24
Peak memory 224092 kb
Host smart-9a7049ab-0f8f-4d4b-8d0e-ec45bc2d6729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313549643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2313549643
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.3630266246
Short name T4
Test name
Test status
Simulation time 40744252 ps
CPU time 0.88 seconds
Started Aug 09 07:50:56 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 215280 kb
Host smart-27203387-442e-427d-90e8-c5178a63caae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630266246 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3630266246
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.693768706
Short name T577
Test name
Test status
Simulation time 37873537 ps
CPU time 0.92 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 07:50:55 PM PDT 24
Peak memory 215312 kb
Host smart-4c017ba1-cc12-43eb-8304-5460e0140f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693768706 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.693768706
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3328896163
Short name T87
Test name
Test status
Simulation time 124272569 ps
CPU time 2.7 seconds
Started Aug 09 07:51:04 PM PDT 24
Finished Aug 09 07:51:07 PM PDT 24
Peak memory 219604 kb
Host smart-28849ad2-efaa-4d13-8c37-bf4fe3bbf1e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328896163 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3328896163
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2152639920
Short name T240
Test name
Test status
Simulation time 10584691923 ps
CPU time 224.82 seconds
Started Aug 09 07:50:58 PM PDT 24
Finished Aug 09 07:54:43 PM PDT 24
Peak memory 221924 kb
Host smart-67ce7d9b-f308-4ac2-8c08-cbe17c754240
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152639920 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2152639920
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.1050059829
Short name T706
Test name
Test status
Simulation time 26191111 ps
CPU time 1.16 seconds
Started Aug 09 07:52:29 PM PDT 24
Finished Aug 09 07:52:31 PM PDT 24
Peak memory 218784 kb
Host smart-57400a44-2caa-436d-8fde-c459340dfe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050059829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.1050059829
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.2476866022
Short name T358
Test name
Test status
Simulation time 56730758 ps
CPU time 1.19 seconds
Started Aug 09 07:52:28 PM PDT 24
Finished Aug 09 07:52:29 PM PDT 24
Peak memory 217376 kb
Host smart-b5a66871-e6a4-41b9-a589-288d9719be8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476866022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2476866022
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.744544327
Short name T515
Test name
Test status
Simulation time 68089906 ps
CPU time 1.12 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 217320 kb
Host smart-b07e9178-3074-4a5f-96d8-914814b3f260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744544327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.744544327
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.2012866498
Short name T354
Test name
Test status
Simulation time 44353161 ps
CPU time 1.41 seconds
Started Aug 09 07:52:31 PM PDT 24
Finished Aug 09 07:52:33 PM PDT 24
Peak memory 218332 kb
Host smart-42d14f43-2b7d-478b-9c39-30b8fb2b4809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012866498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2012866498
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.770778869
Short name T856
Test name
Test status
Simulation time 38138149 ps
CPU time 1.11 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 218620 kb
Host smart-391bc99b-908a-48e4-84d3-583b3ef2fb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770778869 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.770778869
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.1020372658
Short name T413
Test name
Test status
Simulation time 58685209 ps
CPU time 2.1 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 215308 kb
Host smart-203ff865-cb25-453a-be72-2f481dc20785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020372658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1020372658
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.362265939
Short name T729
Test name
Test status
Simulation time 41889080 ps
CPU time 1.07 seconds
Started Aug 09 07:52:24 PM PDT 24
Finished Aug 09 07:52:25 PM PDT 24
Peak memory 218588 kb
Host smart-09c50026-43ea-4493-99fc-d93e9e1f423f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362265939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.362265939
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.3053535942
Short name T878
Test name
Test status
Simulation time 105212197 ps
CPU time 1.26 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 217476 kb
Host smart-cb6287b8-934f-4092-be27-ecad565d1ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053535942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3053535942
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.1343662169
Short name T190
Test name
Test status
Simulation time 232594093 ps
CPU time 1.38 seconds
Started Aug 09 07:52:20 PM PDT 24
Finished Aug 09 07:52:26 PM PDT 24
Peak memory 215544 kb
Host smart-82925011-2125-4b0a-9d77-720126f5b5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343662169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1343662169
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.21245809
Short name T370
Test name
Test status
Simulation time 267381600 ps
CPU time 4.23 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 220356 kb
Host smart-1321107b-50d1-4625-a772-e6019c9538bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21245809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.21245809
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.3354558141
Short name T966
Test name
Test status
Simulation time 46374237 ps
CPU time 1.2 seconds
Started Aug 09 07:52:22 PM PDT 24
Finished Aug 09 07:52:23 PM PDT 24
Peak memory 219588 kb
Host smart-2f890ef5-8ddf-4958-8494-4dd465f4f91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354558141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3354558141
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.2139591645
Short name T592
Test name
Test status
Simulation time 43672281 ps
CPU time 1.67 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 218716 kb
Host smart-ef7e25f7-012c-4d8a-b223-cf05e5aaef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139591645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2139591645
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.141627030
Short name T524
Test name
Test status
Simulation time 60030089 ps
CPU time 1.86 seconds
Started Aug 09 07:52:27 PM PDT 24
Finished Aug 09 07:52:29 PM PDT 24
Peak memory 220284 kb
Host smart-5d088396-8869-4f02-a84c-bed01e88bd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141627030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.141627030
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.2718370814
Short name T435
Test name
Test status
Simulation time 22619637 ps
CPU time 1.16 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 219468 kb
Host smart-bb4eac77-5234-49cd-9b09-33161d0bdf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718370814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2718370814
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.3122791013
Short name T764
Test name
Test status
Simulation time 25405045 ps
CPU time 1.18 seconds
Started Aug 09 07:52:32 PM PDT 24
Finished Aug 09 07:52:33 PM PDT 24
Peak memory 217356 kb
Host smart-0743ad05-fe01-45ad-be60-74c50a60f5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122791013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3122791013
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3932786688
Short name T289
Test name
Test status
Simulation time 83125358 ps
CPU time 1.18 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 218604 kb
Host smart-f829b2ef-9854-45a4-a3c4-185d156b388a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932786688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3932786688
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3890850063
Short name T436
Test name
Test status
Simulation time 107085861 ps
CPU time 1.63 seconds
Started Aug 09 07:52:28 PM PDT 24
Finished Aug 09 07:52:30 PM PDT 24
Peak memory 218936 kb
Host smart-d7436826-2931-4e6b-80ef-3b288c5ec94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890850063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3890850063
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2638103797
Short name T307
Test name
Test status
Simulation time 95039913 ps
CPU time 1.29 seconds
Started Aug 09 07:50:59 PM PDT 24
Finished Aug 09 07:51:00 PM PDT 24
Peak memory 219468 kb
Host smart-8552228a-10bf-494a-8d49-c4a7d6138352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638103797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2638103797
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2316016076
Short name T398
Test name
Test status
Simulation time 21632939 ps
CPU time 0.82 seconds
Started Aug 09 07:50:59 PM PDT 24
Finished Aug 09 07:51:00 PM PDT 24
Peak memory 206520 kb
Host smart-5438654b-db96-4ded-a298-2e6ff4467d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316016076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2316016076
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3190982148
Short name T547
Test name
Test status
Simulation time 17876764 ps
CPU time 0.91 seconds
Started Aug 09 07:50:57 PM PDT 24
Finished Aug 09 07:50:58 PM PDT 24
Peak memory 216460 kb
Host smart-97f6e924-6819-4109-95cd-380aff5b2225
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190982148 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3190982148
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1178671036
Short name T725
Test name
Test status
Simulation time 41438305 ps
CPU time 1.05 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 07:50:55 PM PDT 24
Peak memory 219720 kb
Host smart-84c20779-4dd1-4bcb-b0f6-c2181ad868e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178671036 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1178671036
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2022368340
Short name T514
Test name
Test status
Simulation time 32908313 ps
CPU time 1.04 seconds
Started Aug 09 07:51:00 PM PDT 24
Finished Aug 09 07:51:02 PM PDT 24
Peak memory 218696 kb
Host smart-ff3aece3-5adb-4da6-9192-86acd749f5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022368340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2022368340
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.394638349
Short name T350
Test name
Test status
Simulation time 477521412 ps
CPU time 3.97 seconds
Started Aug 09 07:50:58 PM PDT 24
Finished Aug 09 07:51:02 PM PDT 24
Peak memory 220164 kb
Host smart-6b4cddcc-4a24-4706-bdb5-ebac415c3c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394638349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.394638349
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2556835119
Short name T923
Test name
Test status
Simulation time 27941478 ps
CPU time 1.08 seconds
Started Aug 09 07:50:56 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 224172 kb
Host smart-0170a692-8ed6-4dee-b948-2e52f56a1fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556835119 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2556835119
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1550104934
Short name T661
Test name
Test status
Simulation time 15092228 ps
CPU time 0.95 seconds
Started Aug 09 07:50:55 PM PDT 24
Finished Aug 09 07:50:56 PM PDT 24
Peak memory 215284 kb
Host smart-fdc6d3bb-1611-40d4-b839-27292103edfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550104934 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1550104934
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2337666066
Short name T57
Test name
Test status
Simulation time 507241902 ps
CPU time 3.44 seconds
Started Aug 09 07:50:57 PM PDT 24
Finished Aug 09 07:51:01 PM PDT 24
Peak memory 215284 kb
Host smart-729d355f-656e-4e48-9665-87dc5fade4fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337666066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2337666066
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.763178016
Short name T78
Test name
Test status
Simulation time 84179388163 ps
CPU time 480.47 seconds
Started Aug 09 07:50:58 PM PDT 24
Finished Aug 09 07:58:58 PM PDT 24
Peak memory 223688 kb
Host smart-3e709a68-6342-4d77-9638-0d93c7dad631
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763178016 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.763178016
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1892104944
Short name T146
Test name
Test status
Simulation time 90333806 ps
CPU time 1.21 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 218268 kb
Host smart-691842b6-6a30-4b6e-9657-823adb545766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892104944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1892104944
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.770276757
Short name T641
Test name
Test status
Simulation time 44100454 ps
CPU time 1.19 seconds
Started Aug 09 07:52:22 PM PDT 24
Finished Aug 09 07:52:24 PM PDT 24
Peak memory 217240 kb
Host smart-3c161ca7-5866-47c0-ad2c-81dfc7916d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770276757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.770276757
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.4230811616
Short name T501
Test name
Test status
Simulation time 30824621 ps
CPU time 1.32 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 215544 kb
Host smart-2b3295bd-5bc6-49ec-a4bb-2d16d04c5719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230811616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.4230811616
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.36684205
Short name T476
Test name
Test status
Simulation time 90699977 ps
CPU time 1.45 seconds
Started Aug 09 07:52:41 PM PDT 24
Finished Aug 09 07:52:43 PM PDT 24
Peak memory 218980 kb
Host smart-2c86d33b-1945-4d5e-832a-69c7b1a4944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36684205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.36684205
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.2590310731
Short name T189
Test name
Test status
Simulation time 435367562 ps
CPU time 1.18 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 215580 kb
Host smart-cef783a1-66c8-405c-9fcd-86bd90c217f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590310731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2590310731
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.1574617897
Short name T624
Test name
Test status
Simulation time 69110220 ps
CPU time 2.55 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 219628 kb
Host smart-93dd41a3-6f77-4ff5-a9ae-30238d31f118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574617897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1574617897
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.624686915
Short name T849
Test name
Test status
Simulation time 29664529 ps
CPU time 1.27 seconds
Started Aug 09 07:52:40 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218520 kb
Host smart-ddc30dac-9c7d-40a8-ad31-5b1d10c46aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624686915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.624686915
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.679902594
Short name T648
Test name
Test status
Simulation time 35882868 ps
CPU time 1.42 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218456 kb
Host smart-bc619af5-b914-4439-bac2-4fc091185bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679902594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.679902594
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.710204387
Short name T787
Test name
Test status
Simulation time 80833123 ps
CPU time 1.2 seconds
Started Aug 09 07:52:33 PM PDT 24
Finished Aug 09 07:52:34 PM PDT 24
Peak memory 215568 kb
Host smart-59d01e49-43ff-423c-b85b-40e517d7f29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710204387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.710204387
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1405518775
Short name T364
Test name
Test status
Simulation time 46623343 ps
CPU time 1.82 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 217680 kb
Host smart-cb42f9fb-450e-41fe-8886-8364681045f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405518775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1405518775
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1528555436
Short name T604
Test name
Test status
Simulation time 29825411 ps
CPU time 1.32 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 219984 kb
Host smart-b6c480e5-e306-44ed-b8fa-2a57b7b47d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528555436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1528555436
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.144938597
Short name T948
Test name
Test status
Simulation time 46531950 ps
CPU time 1.34 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 218508 kb
Host smart-e184a18a-207a-4d1e-b087-3afd651a7e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144938597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.144938597
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1798460465
Short name T234
Test name
Test status
Simulation time 38078906 ps
CPU time 1.11 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 221188 kb
Host smart-07c7f800-c0e8-413e-afe1-952ce1b3f190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798460465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1798460465
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.2463734136
Short name T376
Test name
Test status
Simulation time 83708483 ps
CPU time 1.23 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 218628 kb
Host smart-81dc71b5-e80d-4690-8aa3-6cc47d97ca09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463734136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2463734136
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1185671644
Short name T566
Test name
Test status
Simulation time 42419245 ps
CPU time 1.19 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 218992 kb
Host smart-564487c7-14f3-43e2-b862-b72a503552bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185671644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1185671644
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.69051722
Short name T709
Test name
Test status
Simulation time 135552198 ps
CPU time 1.37 seconds
Started Aug 09 07:52:40 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218544 kb
Host smart-46600aa1-e189-4817-90e3-f6c7d7cfad76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69051722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.69051722
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3339491091
Short name T715
Test name
Test status
Simulation time 48076218 ps
CPU time 1.27 seconds
Started Aug 09 07:52:32 PM PDT 24
Finished Aug 09 07:52:34 PM PDT 24
Peak memory 219700 kb
Host smart-1f01d097-eccc-4a22-b32c-cad4f06c2e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339491091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3339491091
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.2740710876
Short name T24
Test name
Test status
Simulation time 68202660 ps
CPU time 1.22 seconds
Started Aug 09 07:52:43 PM PDT 24
Finished Aug 09 07:52:44 PM PDT 24
Peak memory 219440 kb
Host smart-3fc48102-76df-4c99-bc4b-b5733649f67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740710876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2740710876
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2795271025
Short name T608
Test name
Test status
Simulation time 24049371 ps
CPU time 1.18 seconds
Started Aug 09 07:50:55 PM PDT 24
Finished Aug 09 07:50:56 PM PDT 24
Peak memory 220884 kb
Host smart-42118ff3-f0d0-45f3-b7f8-ca0b48937404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795271025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2795271025
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1655433108
Short name T85
Test name
Test status
Simulation time 99022905 ps
CPU time 0.85 seconds
Started Aug 09 07:50:58 PM PDT 24
Finished Aug 09 07:50:59 PM PDT 24
Peak memory 206596 kb
Host smart-4ccfbe4b-4bda-4581-9ef0-049a05b5e6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655433108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1655433108
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2370625456
Short name T79
Test name
Test status
Simulation time 29606213 ps
CPU time 0.85 seconds
Started Aug 09 07:50:55 PM PDT 24
Finished Aug 09 07:50:56 PM PDT 24
Peak memory 218000 kb
Host smart-47f96e70-b122-415c-8936-0e0e52b354e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370625456 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2370625456
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.507443594
Short name T230
Test name
Test status
Simulation time 59551090 ps
CPU time 1.24 seconds
Started Aug 09 07:51:01 PM PDT 24
Finished Aug 09 07:51:02 PM PDT 24
Peak memory 217064 kb
Host smart-b4523cc6-44a2-42c6-8fcd-605c1cc86bf4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507443594 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.507443594
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1411592541
Short name T210
Test name
Test status
Simulation time 65966202 ps
CPU time 0.83 seconds
Started Aug 09 07:51:01 PM PDT 24
Finished Aug 09 07:51:02 PM PDT 24
Peak memory 218440 kb
Host smart-c32e7ea7-28e3-4723-a55c-76b242c6fb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411592541 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1411592541
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1634568866
Short name T490
Test name
Test status
Simulation time 46184143 ps
CPU time 1.46 seconds
Started Aug 09 07:50:58 PM PDT 24
Finished Aug 09 07:50:59 PM PDT 24
Peak memory 217392 kb
Host smart-46874e4d-8abe-4f69-b29a-463dafad3ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634568866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1634568866
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1581357026
Short name T867
Test name
Test status
Simulation time 21886321 ps
CPU time 1.2 seconds
Started Aug 09 07:50:56 PM PDT 24
Finished Aug 09 07:50:58 PM PDT 24
Peak memory 224084 kb
Host smart-c6d50635-ae97-498b-9bfa-aa6fcd3e500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581357026 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1581357026
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1571846456
Short name T368
Test name
Test status
Simulation time 41113614 ps
CPU time 0.88 seconds
Started Aug 09 07:51:01 PM PDT 24
Finished Aug 09 07:51:02 PM PDT 24
Peak memory 214920 kb
Host smart-28de4060-4ca3-48aa-8662-d79ced4659d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571846456 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1571846456
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2445860457
Short name T975
Test name
Test status
Simulation time 667594037 ps
CPU time 4.17 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 07:50:59 PM PDT 24
Peak memory 217216 kb
Host smart-21f225c2-1aab-4a5e-8dc6-507935464514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445860457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2445860457
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3555317709
Short name T927
Test name
Test status
Simulation time 58584853639 ps
CPU time 679.54 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 08:02:14 PM PDT 24
Peak memory 218932 kb
Host smart-e15ac9c7-e7a9-4b80-b99d-c6d3ba93ab37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555317709 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3555317709
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.4016279719
Short name T136
Test name
Test status
Simulation time 59097116 ps
CPU time 1.18 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 220760 kb
Host smart-dfe710b1-32ba-4e53-bee0-389ac54cb115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016279719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.4016279719
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3851420738
Short name T578
Test name
Test status
Simulation time 89124639 ps
CPU time 1.45 seconds
Started Aug 09 07:52:40 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218632 kb
Host smart-528c6ada-b61b-4433-b099-6209e4931906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851420738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3851420738
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.820067611
Short name T434
Test name
Test status
Simulation time 23959562 ps
CPU time 1.14 seconds
Started Aug 09 07:52:34 PM PDT 24
Finished Aug 09 07:52:35 PM PDT 24
Peak memory 218600 kb
Host smart-d3f1e55c-ef74-4561-becd-32682fff6c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820067611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.820067611
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1035571587
Short name T53
Test name
Test status
Simulation time 48417802 ps
CPU time 1.53 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 218348 kb
Host smart-524a2dfb-c1c1-4adf-b6e1-d0163eee9777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035571587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1035571587
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3181230679
Short name T990
Test name
Test status
Simulation time 96410365 ps
CPU time 1.22 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 219248 kb
Host smart-693946e6-5de6-4ee7-96cb-3a809118fee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181230679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3181230679
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3110381116
Short name T978
Test name
Test status
Simulation time 39094820 ps
CPU time 1.64 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 218588 kb
Host smart-b58e3587-74e5-4fa5-9382-26bd29caa8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110381116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3110381116
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.3450710544
Short name T876
Test name
Test status
Simulation time 31124447 ps
CPU time 1.3 seconds
Started Aug 09 07:52:33 PM PDT 24
Finished Aug 09 07:52:35 PM PDT 24
Peak memory 220576 kb
Host smart-40316e32-9fe9-4a8e-8886-d2bf6a580607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450710544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.3450710544
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.4167437729
Short name T28
Test name
Test status
Simulation time 64785781 ps
CPU time 1.24 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 218700 kb
Host smart-1ecd0a04-44ad-4528-bb68-f8b3651247e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167437729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.4167437729
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.1067993316
Short name T290
Test name
Test status
Simulation time 186546053 ps
CPU time 1.2 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 218496 kb
Host smart-942d036e-e13b-49b7-bc35-cd6be22d611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067993316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1067993316
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.3575831535
Short name T747
Test name
Test status
Simulation time 30683291 ps
CPU time 1.19 seconds
Started Aug 09 07:52:34 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 217524 kb
Host smart-61666ad6-ad15-49cb-b9e9-11e624abf79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575831535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3575831535
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2523936063
Short name T794
Test name
Test status
Simulation time 73913222 ps
CPU time 1.14 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 218824 kb
Host smart-fca5a909-971d-4055-bb67-ff951b48d1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523936063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2523936063
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.3723465653
Short name T699
Test name
Test status
Simulation time 44569893 ps
CPU time 1.75 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 218616 kb
Host smart-da1d32fc-ed46-41c0-9502-7de38269457a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723465653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3723465653
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.3745694822
Short name T574
Test name
Test status
Simulation time 86932519 ps
CPU time 1.2 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 215584 kb
Host smart-20e11dae-024a-47e7-8046-69ff475dc9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745694822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3745694822
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.764449450
Short name T302
Test name
Test status
Simulation time 43712476 ps
CPU time 1.2 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 217420 kb
Host smart-b0317446-3114-4aac-aa99-eae0831303aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764449450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.764449450
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.3306682581
Short name T256
Test name
Test status
Simulation time 36489098 ps
CPU time 1.06 seconds
Started Aug 09 07:52:34 PM PDT 24
Finished Aug 09 07:52:35 PM PDT 24
Peak memory 219764 kb
Host smart-aa31ea0a-3e6b-4bfc-8566-7a45eec4de94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306682581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.3306682581
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/128.edn_alert.1090031791
Short name T829
Test name
Test status
Simulation time 147500447 ps
CPU time 1.24 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 219408 kb
Host smart-d94a2340-6bac-4232-8f7d-7ac9463e4a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090031791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.1090031791
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.2911367717
Short name T663
Test name
Test status
Simulation time 62683155 ps
CPU time 2.08 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 219856 kb
Host smart-40488f37-d46a-4b1e-b9fc-867948466bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911367717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2911367717
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.2918828782
Short name T308
Test name
Test status
Simulation time 103533997 ps
CPU time 1.4 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 220768 kb
Host smart-7d499fd2-f5f4-400a-ac9c-e8034fc0bd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918828782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2918828782
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.3831433828
Short name T797
Test name
Test status
Simulation time 54313077 ps
CPU time 1.31 seconds
Started Aug 09 07:52:41 PM PDT 24
Finished Aug 09 07:52:42 PM PDT 24
Peak memory 219828 kb
Host smart-0d3ee830-06a8-4fe6-8220-14d9388daf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831433828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3831433828
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3003157387
Short name T805
Test name
Test status
Simulation time 23238600 ps
CPU time 1.2 seconds
Started Aug 09 07:51:03 PM PDT 24
Finished Aug 09 07:51:05 PM PDT 24
Peak memory 218524 kb
Host smart-37c38be1-7f26-4a61-8ee9-4611717a5b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003157387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3003157387
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2287273012
Short name T461
Test name
Test status
Simulation time 13601967 ps
CPU time 0.93 seconds
Started Aug 09 07:51:03 PM PDT 24
Finished Aug 09 07:51:04 PM PDT 24
Peak memory 206800 kb
Host smart-6ea9b5b0-9a6d-4a91-a572-1142b906d353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287273012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2287273012
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.533076999
Short name T176
Test name
Test status
Simulation time 21517572 ps
CPU time 0.92 seconds
Started Aug 09 07:51:03 PM PDT 24
Finished Aug 09 07:51:04 PM PDT 24
Peak memory 215368 kb
Host smart-9817baeb-a83e-4115-a667-116ff021ba08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533076999 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.533076999
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2539677259
Short name T69
Test name
Test status
Simulation time 177883617 ps
CPU time 1.05 seconds
Started Aug 09 07:51:08 PM PDT 24
Finished Aug 09 07:51:10 PM PDT 24
Peak memory 218276 kb
Host smart-4e35cf27-c23d-45aa-aa76-80c6e266d4d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539677259 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2539677259
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3041173253
Short name T718
Test name
Test status
Simulation time 24712726 ps
CPU time 0.85 seconds
Started Aug 09 07:51:04 PM PDT 24
Finished Aug 09 07:51:06 PM PDT 24
Peak memory 218456 kb
Host smart-ee0317f0-a265-4c94-9f24-cb44cc8f586f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041173253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3041173253
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_intr.804270012
Short name T532
Test name
Test status
Simulation time 24282943 ps
CPU time 1.05 seconds
Started Aug 09 07:51:04 PM PDT 24
Finished Aug 09 07:51:05 PM PDT 24
Peak memory 215500 kb
Host smart-d3c69915-6b5f-455d-8dfc-e3daba61ef81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804270012 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.804270012
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1878191194
Short name T432
Test name
Test status
Simulation time 14506665 ps
CPU time 1.03 seconds
Started Aug 09 07:50:57 PM PDT 24
Finished Aug 09 07:50:58 PM PDT 24
Peak memory 215312 kb
Host smart-86fab014-de3d-41f7-bad5-f4d02b94f655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878191194 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1878191194
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2861281317
Short name T475
Test name
Test status
Simulation time 209681934 ps
CPU time 4.32 seconds
Started Aug 09 07:51:03 PM PDT 24
Finished Aug 09 07:51:07 PM PDT 24
Peak memory 217100 kb
Host smart-19cea158-c274-4c00-bbff-0271caca9dcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861281317 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2861281317
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_alert.102991664
Short name T156
Test name
Test status
Simulation time 56161763 ps
CPU time 1.32 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 215584 kb
Host smart-046ad31e-d71c-4a31-a84b-7aeb74b038ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102991664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.102991664
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.3404723004
Short name T301
Test name
Test status
Simulation time 117281591 ps
CPU time 1.04 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 217164 kb
Host smart-3e2a8994-6aec-45bd-82cb-a90bd871c216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404723004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3404723004
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.2825484949
Short name T11
Test name
Test status
Simulation time 226609908 ps
CPU time 1.27 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 218380 kb
Host smart-9f442aff-1cff-4747-af24-8ddea9b419a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825484949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.2825484949
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.1664708972
Short name T800
Test name
Test status
Simulation time 53805485 ps
CPU time 1.26 seconds
Started Aug 09 07:52:34 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 217344 kb
Host smart-b1ed662c-129a-4d48-8868-01b2068b4461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664708972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1664708972
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.2326098151
Short name T731
Test name
Test status
Simulation time 29491973 ps
CPU time 1.31 seconds
Started Aug 09 07:52:41 PM PDT 24
Finished Aug 09 07:52:42 PM PDT 24
Peak memory 220100 kb
Host smart-1cd47fe2-06dc-445a-a528-4afddc90c6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326098151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.2326098151
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1116104580
Short name T791
Test name
Test status
Simulation time 42005943 ps
CPU time 1.48 seconds
Started Aug 09 07:52:30 PM PDT 24
Finished Aug 09 07:52:31 PM PDT 24
Peak memory 218560 kb
Host smart-4d3036e4-c997-46ff-bd99-35ff8a56ca7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116104580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1116104580
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.443405773
Short name T417
Test name
Test status
Simulation time 27926844 ps
CPU time 1.22 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 220232 kb
Host smart-f83ea0a5-8edb-41b2-bef9-bdad19811001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443405773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.443405773
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3593509818
Short name T537
Test name
Test status
Simulation time 59253604 ps
CPU time 1.34 seconds
Started Aug 09 07:52:34 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 218428 kb
Host smart-90e493f6-4e0a-421d-903c-1473213f8f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593509818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3593509818
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.1711231913
Short name T420
Test name
Test status
Simulation time 39279243 ps
CPU time 1.37 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 217492 kb
Host smart-0ca97941-be39-4500-82d3-a6f43004d36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711231913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1711231913
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.1647382508
Short name T606
Test name
Test status
Simulation time 124290280 ps
CPU time 1.2 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 219104 kb
Host smart-73bc5d03-cbb8-4b78-a5b7-a8bcc04d254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647382508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1647382508
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1321925662
Short name T117
Test name
Test status
Simulation time 28270220 ps
CPU time 1.26 seconds
Started Aug 09 07:52:41 PM PDT 24
Finished Aug 09 07:52:42 PM PDT 24
Peak memory 218472 kb
Host smart-12fc28a1-14e3-4982-ac39-ddcfe97a5c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321925662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1321925662
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.876495848
Short name T90
Test name
Test status
Simulation time 70764720 ps
CPU time 1.39 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 219576 kb
Host smart-ec137f95-89da-4c89-9cab-d30582daa03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876495848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.876495848
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.659706193
Short name T145
Test name
Test status
Simulation time 39465199 ps
CPU time 1.17 seconds
Started Aug 09 07:52:40 PM PDT 24
Finished Aug 09 07:52:42 PM PDT 24
Peak memory 219464 kb
Host smart-b52fe8ba-259b-4463-9bdc-76b46afc9078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659706193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.659706193
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2517319842
Short name T939
Test name
Test status
Simulation time 56798872 ps
CPU time 1.76 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 218472 kb
Host smart-3d5ee796-45bd-46af-9ad3-6fe762a4bd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517319842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2517319842
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.2093136443
Short name T873
Test name
Test status
Simulation time 26951113 ps
CPU time 1.25 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 220416 kb
Host smart-725612e7-7260-4039-81b3-5437841e8dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093136443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2093136443
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3232424661
Short name T384
Test name
Test status
Simulation time 79608440 ps
CPU time 1.76 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 220264 kb
Host smart-0cc7c9a6-99dc-4017-aa8c-56630d7cca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232424661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3232424661
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1771408346
Short name T495
Test name
Test status
Simulation time 101790526 ps
CPU time 1.62 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 218832 kb
Host smart-5ed32cbf-1b09-43f5-b773-95f16cc84bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771408346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1771408346
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3891962672
Short name T80
Test name
Test status
Simulation time 29771978 ps
CPU time 1.25 seconds
Started Aug 09 07:51:02 PM PDT 24
Finished Aug 09 07:51:03 PM PDT 24
Peak memory 218976 kb
Host smart-bab4c6ec-8386-475b-a130-af805bb87b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891962672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3891962672
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.510077124
Short name T779
Test name
Test status
Simulation time 30408666 ps
CPU time 0.93 seconds
Started Aug 09 07:51:00 PM PDT 24
Finished Aug 09 07:51:01 PM PDT 24
Peak memory 215380 kb
Host smart-580bc6f7-eebb-4bc4-a514-271130254f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510077124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.510077124
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.748096919
Short name T150
Test name
Test status
Simulation time 75951523 ps
CPU time 1.09 seconds
Started Aug 09 07:51:03 PM PDT 24
Finished Aug 09 07:51:04 PM PDT 24
Peak memory 219524 kb
Host smart-bbeb0afc-975b-4e5b-bc7c-7ff805c993a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748096919 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.748096919
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3163497943
Short name T649
Test name
Test status
Simulation time 42237764 ps
CPU time 0.86 seconds
Started Aug 09 07:51:01 PM PDT 24
Finished Aug 09 07:51:02 PM PDT 24
Peak memory 218620 kb
Host smart-d1a1740d-8fe8-4fbb-9767-5dc68eaf311b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163497943 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3163497943
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1594521305
Short name T646
Test name
Test status
Simulation time 143680145 ps
CPU time 1.06 seconds
Started Aug 09 07:51:03 PM PDT 24
Finished Aug 09 07:51:04 PM PDT 24
Peak memory 217368 kb
Host smart-4a2aaf8b-71a4-492f-9e9e-7d8b33c7885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594521305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1594521305
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1165757071
Short name T259
Test name
Test status
Simulation time 26399046 ps
CPU time 0.92 seconds
Started Aug 09 07:51:05 PM PDT 24
Finished Aug 09 07:51:06 PM PDT 24
Peak memory 215340 kb
Host smart-f2eb4b23-ecc7-47b4-8a5b-fd5977fef504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165757071 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1165757071
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2704382647
Short name T952
Test name
Test status
Simulation time 17327340 ps
CPU time 0.98 seconds
Started Aug 09 07:51:03 PM PDT 24
Finished Aug 09 07:51:04 PM PDT 24
Peak memory 215272 kb
Host smart-ed3033fb-c29d-4dec-a4f9-b88e1ec7ea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704382647 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2704382647
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2494798875
Short name T491
Test name
Test status
Simulation time 156417242573 ps
CPU time 989.37 seconds
Started Aug 09 07:51:07 PM PDT 24
Finished Aug 09 08:07:36 PM PDT 24
Peak memory 221264 kb
Host smart-6761d5c0-a495-4877-9087-386e88319d94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494798875 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2494798875
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.2865130178
Short name T703
Test name
Test status
Simulation time 61406094 ps
CPU time 1.06 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 218212 kb
Host smart-b421e9f1-d462-4d85-a85d-edda55dcce31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865130178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.2865130178
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2623448614
Short name T785
Test name
Test status
Simulation time 78286230 ps
CPU time 1.63 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 220076 kb
Host smart-8a3de535-191e-4857-a17c-f1ccd34a6df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623448614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2623448614
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2219452860
Short name T523
Test name
Test status
Simulation time 88846971 ps
CPU time 1.2 seconds
Started Aug 09 07:52:40 PM PDT 24
Finished Aug 09 07:52:42 PM PDT 24
Peak memory 220616 kb
Host smart-3ae9ab3b-39ad-4ce8-b455-0d6e56b78095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219452860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2219452860
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3989887144
Short name T470
Test name
Test status
Simulation time 112158780 ps
CPU time 1.56 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218692 kb
Host smart-06e689f0-fb11-419e-80be-78079d2d59b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989887144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3989887144
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.3476865985
Short name T623
Test name
Test status
Simulation time 33339300 ps
CPU time 1.29 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 218584 kb
Host smart-4a61c99d-7d37-401d-b66c-aa3ccc4e7688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476865985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3476865985
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.2477937568
Short name T99
Test name
Test status
Simulation time 127189949 ps
CPU time 1.32 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 219016 kb
Host smart-2058b3ac-78e0-4ab4-a879-8bb60baf791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477937568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2477937568
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.3227263557
Short name T204
Test name
Test status
Simulation time 49747296 ps
CPU time 1.21 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 218504 kb
Host smart-4b6805a0-b10c-4b8d-ba95-661f048ccedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227263557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.3227263557
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.3281239801
Short name T334
Test name
Test status
Simulation time 34831113 ps
CPU time 1.23 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 219828 kb
Host smart-ff73357b-57f6-4666-a784-131637630d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281239801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3281239801
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3806523501
Short name T980
Test name
Test status
Simulation time 116913427 ps
CPU time 1.15 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 220664 kb
Host smart-d071c1f9-48a6-4331-bc43-025d0edaedc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806523501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3806523501
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.581294875
Short name T353
Test name
Test status
Simulation time 49810326 ps
CPU time 1.16 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 217336 kb
Host smart-d475625f-2724-418a-8c72-46d30726f04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581294875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.581294875
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2274969068
Short name T162
Test name
Test status
Simulation time 96875703 ps
CPU time 1.12 seconds
Started Aug 09 07:52:33 PM PDT 24
Finished Aug 09 07:52:34 PM PDT 24
Peak memory 218484 kb
Host smart-146f5132-3551-4b9b-80f4-61efa584f740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274969068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2274969068
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/147.edn_alert.2399732855
Short name T803
Test name
Test status
Simulation time 26946834 ps
CPU time 1.28 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 219680 kb
Host smart-1489ffe6-cd9d-4ebb-be39-c8d128e16a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399732855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.2399732855
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.2837715581
Short name T483
Test name
Test status
Simulation time 95964897 ps
CPU time 1.2 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 217404 kb
Host smart-d0251fb3-4f74-4003-be72-d53f7fa27a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837715581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2837715581
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.1763524661
Short name T591
Test name
Test status
Simulation time 21740549 ps
CPU time 1.17 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 215608 kb
Host smart-85439236-4374-49e6-8eda-f1ce8756933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763524661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1763524661
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3306635829
Short name T366
Test name
Test status
Simulation time 43001835 ps
CPU time 1.47 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 218524 kb
Host smart-1fb18769-2f42-41b6-877e-413e29d6ee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306635829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3306635829
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.1540052687
Short name T563
Test name
Test status
Simulation time 47514638 ps
CPU time 1.14 seconds
Started Aug 09 07:52:41 PM PDT 24
Finished Aug 09 07:52:43 PM PDT 24
Peak memory 218868 kb
Host smart-c9588e37-2ccc-439c-8188-44876dd15094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540052687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1540052687
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.1640390445
Short name T94
Test name
Test status
Simulation time 61900088 ps
CPU time 1.26 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 218468 kb
Host smart-ec80b8f5-e0b9-424b-800d-54ff46716181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640390445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1640390445
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3930003908
Short name T197
Test name
Test status
Simulation time 25055612 ps
CPU time 1.21 seconds
Started Aug 09 07:51:06 PM PDT 24
Finished Aug 09 07:51:07 PM PDT 24
Peak memory 218416 kb
Host smart-4b1edcc0-3b47-43a9-a69b-5b1d30447493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930003908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3930003908
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2788082008
Short name T629
Test name
Test status
Simulation time 39823474 ps
CPU time 0.9 seconds
Started Aug 09 07:51:01 PM PDT 24
Finished Aug 09 07:51:02 PM PDT 24
Peak memory 215184 kb
Host smart-40df4f5c-97d7-416a-bb5f-afda0ad4e4a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788082008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2788082008
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1351348244
Short name T520
Test name
Test status
Simulation time 25368316 ps
CPU time 0.9 seconds
Started Aug 09 07:51:05 PM PDT 24
Finished Aug 09 07:51:06 PM PDT 24
Peak memory 215408 kb
Host smart-1cb0ab33-72d1-4aa6-8ade-173b3df3d41a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351348244 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1351348244
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3309243799
Short name T951
Test name
Test status
Simulation time 98128984 ps
CPU time 1.14 seconds
Started Aug 09 07:51:04 PM PDT 24
Finished Aug 09 07:51:06 PM PDT 24
Peak memory 216844 kb
Host smart-330adf2a-b849-421b-95f1-62e7ef603093
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309243799 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3309243799
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1425706288
Short name T64
Test name
Test status
Simulation time 44668463 ps
CPU time 1.01 seconds
Started Aug 09 07:51:00 PM PDT 24
Finished Aug 09 07:51:01 PM PDT 24
Peak memory 229732 kb
Host smart-d6fd5160-2001-418d-a676-a4d6ce7761c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425706288 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1425706288
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_intr.1608086751
Short name T696
Test name
Test status
Simulation time 38644043 ps
CPU time 0.95 seconds
Started Aug 09 07:51:02 PM PDT 24
Finished Aug 09 07:51:03 PM PDT 24
Peak memory 215360 kb
Host smart-90e38ad7-01a0-4d48-8cdd-1c966f29aa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608086751 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1608086751
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.350330355
Short name T673
Test name
Test status
Simulation time 19094879 ps
CPU time 1.09 seconds
Started Aug 09 07:51:06 PM PDT 24
Finished Aug 09 07:51:08 PM PDT 24
Peak memory 215288 kb
Host smart-4abeb197-b0b7-40d7-a5f9-991f1a8b9064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350330355 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.350330355
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.160109671
Short name T934
Test name
Test status
Simulation time 346559991 ps
CPU time 2.43 seconds
Started Aug 09 07:51:02 PM PDT 24
Finished Aug 09 07:51:05 PM PDT 24
Peak memory 220036 kb
Host smart-23d2625e-81ab-48d1-9bc4-7be9947511e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160109671 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.160109671
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3736141862
Short name T808
Test name
Test status
Simulation time 20518275669 ps
CPU time 219.25 seconds
Started Aug 09 07:51:04 PM PDT 24
Finished Aug 09 07:54:44 PM PDT 24
Peak memory 222844 kb
Host smart-a098abc6-168e-4679-92fe-6633b77605d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736141862 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3736141862
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2899089686
Short name T843
Test name
Test status
Simulation time 37825920 ps
CPU time 1.4 seconds
Started Aug 09 07:52:40 PM PDT 24
Finished Aug 09 07:52:42 PM PDT 24
Peak memory 217560 kb
Host smart-94171dbb-b482-4412-b88d-9f42b335a63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899089686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2899089686
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.878230723
Short name T945
Test name
Test status
Simulation time 41651320 ps
CPU time 1.45 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 217516 kb
Host smart-a8270ef1-76a5-406d-a868-51153fec2cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878230723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.878230723
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.1052272999
Short name T609
Test name
Test status
Simulation time 90735136 ps
CPU time 1.22 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 219764 kb
Host smart-aed69d23-abf9-4850-ba47-57952c87e7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052272999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1052272999
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.893426601
Short name T822
Test name
Test status
Simulation time 66325762 ps
CPU time 1.36 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 218388 kb
Host smart-4938c93c-a931-47f5-aba0-39b737f42c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893426601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.893426601
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3938936127
Short name T252
Test name
Test status
Simulation time 43538906 ps
CPU time 1.25 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 220256 kb
Host smart-78dfd515-0b58-4ca3-840f-3760e0f1f6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938936127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3938936127
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3027999498
Short name T720
Test name
Test status
Simulation time 93642248 ps
CPU time 1.11 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 217292 kb
Host smart-e4347ea0-4857-413d-8927-237d11cd9bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027999498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3027999498
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1561187605
Short name T799
Test name
Test status
Simulation time 46725679 ps
CPU time 1.22 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218664 kb
Host smart-58ff742e-2984-497a-a076-71cc7d505b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561187605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1561187605
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.3649093635
Short name T619
Test name
Test status
Simulation time 143498441 ps
CPU time 1.22 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 217360 kb
Host smart-b8a1542b-1ea2-4f2e-ba2f-aef00ceeceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649093635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3649093635
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.1857852121
Short name T778
Test name
Test status
Simulation time 22806636 ps
CPU time 1.18 seconds
Started Aug 09 07:52:41 PM PDT 24
Finished Aug 09 07:52:42 PM PDT 24
Peak memory 219448 kb
Host smart-6384ddde-ebaf-4f5d-b48f-a0b44dd924f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857852121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.1857852121
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3105304476
Short name T979
Test name
Test status
Simulation time 58854028 ps
CPU time 2.22 seconds
Started Aug 09 07:52:33 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 218916 kb
Host smart-7031307a-c1d8-4364-a295-2cb4e3e2f98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105304476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3105304476
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1928157164
Short name T637
Test name
Test status
Simulation time 74090344 ps
CPU time 1.22 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 218340 kb
Host smart-e688f18b-bdb3-43ad-ab37-1d4070b2f20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928157164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1928157164
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.1536950057
Short name T442
Test name
Test status
Simulation time 30643199 ps
CPU time 1.28 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218516 kb
Host smart-d5f7e5a7-ef66-4ff4-acb7-c3bbd3971b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536950057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1536950057
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.2130952111
Short name T260
Test name
Test status
Simulation time 345476238 ps
CPU time 1.43 seconds
Started Aug 09 07:52:42 PM PDT 24
Finished Aug 09 07:52:44 PM PDT 24
Peak memory 219580 kb
Host smart-cad969ea-134c-4c69-bd2c-223c4655441c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130952111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2130952111
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.447787807
Short name T84
Test name
Test status
Simulation time 163906921 ps
CPU time 1.18 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 217424 kb
Host smart-4dd3ed4c-a400-4d75-84ee-b52950658c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447787807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.447787807
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1132235138
Short name T160
Test name
Test status
Simulation time 51526661 ps
CPU time 1.24 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 219548 kb
Host smart-56293fc2-8259-43eb-b007-4dc478916e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132235138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1132235138
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.2775930269
Short name T738
Test name
Test status
Simulation time 108094337 ps
CPU time 1.32 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 218912 kb
Host smart-0b8860d2-32c0-40bd-a889-59045d0521c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775930269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2775930269
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.417979151
Short name T471
Test name
Test status
Simulation time 22479951 ps
CPU time 1.16 seconds
Started Aug 09 07:52:43 PM PDT 24
Finished Aug 09 07:52:44 PM PDT 24
Peak memory 218504 kb
Host smart-4c94770d-8e9f-4a26-9abd-f8df84932221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417979151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.417979151
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.3180393498
Short name T710
Test name
Test status
Simulation time 86465299 ps
CPU time 2.94 seconds
Started Aug 09 07:52:50 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 220292 kb
Host smart-2b2ef07f-4532-48dc-8a1d-91645b8fea0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180393498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3180393498
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2684734053
Short name T458
Test name
Test status
Simulation time 224372869 ps
CPU time 1.27 seconds
Started Aug 09 07:51:04 PM PDT 24
Finished Aug 09 07:51:06 PM PDT 24
Peak memory 219508 kb
Host smart-20a151d3-bf4c-4dac-860b-71cdbfa90a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684734053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2684734053
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1508702196
Short name T933
Test name
Test status
Simulation time 23695606 ps
CPU time 0.9 seconds
Started Aug 09 07:51:04 PM PDT 24
Finished Aug 09 07:51:05 PM PDT 24
Peak memory 206792 kb
Host smart-0dd030d2-2f0b-4f06-b9b3-b4fa5dbf163b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508702196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1508702196
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1413119774
Short name T561
Test name
Test status
Simulation time 30693748 ps
CPU time 0.88 seconds
Started Aug 09 07:51:02 PM PDT 24
Finished Aug 09 07:51:03 PM PDT 24
Peak memory 215524 kb
Host smart-d92c8283-536d-4695-8dba-e074ff2bd57d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413119774 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1413119774
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1759597110
Short name T144
Test name
Test status
Simulation time 47664452 ps
CPU time 1.16 seconds
Started Aug 09 07:51:03 PM PDT 24
Finished Aug 09 07:51:04 PM PDT 24
Peak memory 218424 kb
Host smart-ebc83661-f150-4449-bd61-cec74bec038f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759597110 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1759597110
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1507233225
Short name T221
Test name
Test status
Simulation time 25088769 ps
CPU time 1.41 seconds
Started Aug 09 07:51:05 PM PDT 24
Finished Aug 09 07:51:07 PM PDT 24
Peak memory 224124 kb
Host smart-3b3a7aab-abbf-4a59-8998-ff87423d797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507233225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1507233225
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.42932986
Short name T650
Test name
Test status
Simulation time 4595866508 ps
CPU time 79.68 seconds
Started Aug 09 07:51:06 PM PDT 24
Finished Aug 09 07:52:26 PM PDT 24
Peak memory 220552 kb
Host smart-2b9eb206-55d8-4b88-9ce8-b29283ad5691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42932986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.42932986
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1826909102
Short name T728
Test name
Test status
Simulation time 35980855 ps
CPU time 0.89 seconds
Started Aug 09 07:51:03 PM PDT 24
Finished Aug 09 07:51:04 PM PDT 24
Peak memory 215172 kb
Host smart-c7617c7f-419d-4c69-8f52-1cc59dda9f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826909102 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1826909102
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1684820420
Short name T549
Test name
Test status
Simulation time 22039116 ps
CPU time 0.92 seconds
Started Aug 09 07:51:04 PM PDT 24
Finished Aug 09 07:51:05 PM PDT 24
Peak memory 215280 kb
Host smart-be4de2a1-a652-4b2c-839b-1056c257ff57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684820420 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1684820420
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3383662582
Short name T378
Test name
Test status
Simulation time 152385326 ps
CPU time 3.56 seconds
Started Aug 09 07:51:04 PM PDT 24
Finished Aug 09 07:51:08 PM PDT 24
Peak memory 216892 kb
Host smart-9aab0dcf-4391-4a27-95ea-fb3aab5ec0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383662582 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3383662582
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1443834097
Short name T875
Test name
Test status
Simulation time 41055353734 ps
CPU time 406.75 seconds
Started Aug 09 07:51:02 PM PDT 24
Finished Aug 09 07:57:49 PM PDT 24
Peak memory 217816 kb
Host smart-a3013073-6dcd-4742-8490-3a60e227ebdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443834097 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1443834097
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3980559456
Short name T890
Test name
Test status
Simulation time 28244951 ps
CPU time 1.27 seconds
Started Aug 09 07:52:42 PM PDT 24
Finished Aug 09 07:52:43 PM PDT 24
Peak memory 215556 kb
Host smart-b741ea97-9040-46e1-9ac7-4adbfe807d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980559456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3980559456
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.2725549736
Short name T974
Test name
Test status
Simulation time 85567398 ps
CPU time 1.24 seconds
Started Aug 09 07:52:34 PM PDT 24
Finished Aug 09 07:52:35 PM PDT 24
Peak memory 218720 kb
Host smart-f09776e8-52bb-452d-9ad3-38afc96e2ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725549736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2725549736
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2712856876
Short name T745
Test name
Test status
Simulation time 28606282 ps
CPU time 1.28 seconds
Started Aug 09 07:52:55 PM PDT 24
Finished Aug 09 07:52:57 PM PDT 24
Peak memory 219788 kb
Host smart-bae22922-399f-43ff-bd64-2773851d760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712856876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2712856876
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2999715765
Short name T601
Test name
Test status
Simulation time 43224451 ps
CPU time 1.57 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:47 PM PDT 24
Peak memory 215284 kb
Host smart-51f9e162-d939-44d0-a64d-8975f423b6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999715765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2999715765
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.2404676810
Short name T119
Test name
Test status
Simulation time 33539431 ps
CPU time 1.17 seconds
Started Aug 09 07:52:46 PM PDT 24
Finished Aug 09 07:52:48 PM PDT 24
Peak memory 219808 kb
Host smart-51571d40-a296-402a-925d-1006a711ebd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404676810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2404676810
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.2196405624
Short name T441
Test name
Test status
Simulation time 63708559 ps
CPU time 1.17 seconds
Started Aug 09 07:52:46 PM PDT 24
Finished Aug 09 07:52:47 PM PDT 24
Peak memory 218620 kb
Host smart-03fef5bb-e5f8-493a-b657-c0ffd465dd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196405624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2196405624
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1760544537
Short name T429
Test name
Test status
Simulation time 38460041 ps
CPU time 1.09 seconds
Started Aug 09 07:52:44 PM PDT 24
Finished Aug 09 07:52:45 PM PDT 24
Peak memory 219740 kb
Host smart-6dde027d-7cc7-4c3b-8058-e3022e1f7bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760544537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1760544537
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.3056054263
Short name T357
Test name
Test status
Simulation time 38004099 ps
CPU time 1.04 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 218420 kb
Host smart-f7263176-1e74-4c46-acc3-3499a20d8377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056054263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3056054263
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.397288417
Short name T104
Test name
Test status
Simulation time 53264654 ps
CPU time 1.23 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218400 kb
Host smart-0c8a18b8-7fa2-43e3-9c7d-593e79bf43c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397288417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.397288417
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/165.edn_alert.4260522340
Short name T68
Test name
Test status
Simulation time 65715110 ps
CPU time 1.15 seconds
Started Aug 09 07:53:04 PM PDT 24
Finished Aug 09 07:53:05 PM PDT 24
Peak memory 219968 kb
Host smart-ca9e5645-d20f-4d30-9dc4-b2a0fc88db90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260522340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.4260522340
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3691274711
Short name T332
Test name
Test status
Simulation time 34100167 ps
CPU time 1.44 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 218492 kb
Host smart-feac2668-b4f0-4b07-850d-21141cef2060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691274711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3691274711
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.994702730
Short name T314
Test name
Test status
Simulation time 76260459 ps
CPU time 1.14 seconds
Started Aug 09 07:52:40 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218800 kb
Host smart-2b9a76f6-fa1a-4e6d-877d-68ecb956cf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994702730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.994702730
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.3589812353
Short name T356
Test name
Test status
Simulation time 37497196 ps
CPU time 1.15 seconds
Started Aug 09 07:52:43 PM PDT 24
Finished Aug 09 07:52:44 PM PDT 24
Peak memory 218580 kb
Host smart-dd0e321e-1c3a-4f37-8c39-8f921483a4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589812353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3589812353
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1774651008
Short name T437
Test name
Test status
Simulation time 70624086 ps
CPU time 1.05 seconds
Started Aug 09 07:52:41 PM PDT 24
Finished Aug 09 07:52:42 PM PDT 24
Peak memory 220608 kb
Host smart-80ee9f48-e43f-4baa-b8d4-8d58cd9ad493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774651008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1774651008
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.264655489
Short name T766
Test name
Test status
Simulation time 119967904 ps
CPU time 1.42 seconds
Started Aug 09 07:52:44 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 218820 kb
Host smart-0ca0781e-15af-47a7-be1c-3c0344fa5c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264655489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.264655489
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.456662596
Short name T249
Test name
Test status
Simulation time 27969221 ps
CPU time 1.2 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 218336 kb
Host smart-55de50d8-659c-4d9b-b059-5e23ce149b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456662596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.456662596
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.620582443
Short name T337
Test name
Test status
Simulation time 29355429 ps
CPU time 1.03 seconds
Started Aug 09 07:52:43 PM PDT 24
Finished Aug 09 07:52:44 PM PDT 24
Peak memory 217288 kb
Host smart-c1287e10-3140-458d-91fa-1593a421afad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620582443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.620582443
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2039844914
Short name T292
Test name
Test status
Simulation time 88758990 ps
CPU time 1.23 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 219996 kb
Host smart-bf365bd6-f895-49f7-9d62-9d575912521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039844914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2039844914
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.1467079590
Short name T845
Test name
Test status
Simulation time 121999940 ps
CPU time 1.16 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 218796 kb
Host smart-c7fa0ae5-aab3-436a-b82e-cc0b9d1db816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467079590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1467079590
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3034858749
Short name T316
Test name
Test status
Simulation time 23119563 ps
CPU time 1.17 seconds
Started Aug 09 07:51:14 PM PDT 24
Finished Aug 09 07:51:21 PM PDT 24
Peak memory 220640 kb
Host smart-a24e27fc-cbe3-4e92-a312-1c33dada3e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034858749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3034858749
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1847157987
Short name T502
Test name
Test status
Simulation time 21646445 ps
CPU time 1.02 seconds
Started Aug 09 07:51:10 PM PDT 24
Finished Aug 09 07:51:11 PM PDT 24
Peak memory 215152 kb
Host smart-21680a37-8250-4a26-b0c8-cfd22fba47a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847157987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1847157987
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2343462181
Short name T743
Test name
Test status
Simulation time 131575242 ps
CPU time 1.01 seconds
Started Aug 09 07:51:15 PM PDT 24
Finished Aug 09 07:51:16 PM PDT 24
Peak memory 219688 kb
Host smart-1ed365be-2721-44df-94a1-bbc8e97ab138
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343462181 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2343462181
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.4162584781
Short name T748
Test name
Test status
Simulation time 49957176 ps
CPU time 1.1 seconds
Started Aug 09 07:51:10 PM PDT 24
Finished Aug 09 07:51:11 PM PDT 24
Peak memory 224244 kb
Host smart-28a9b442-7079-4d12-9b1d-9954f192056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162584781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4162584781
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1854974407
Short name T487
Test name
Test status
Simulation time 85007721 ps
CPU time 1.26 seconds
Started Aug 09 07:51:04 PM PDT 24
Finished Aug 09 07:51:05 PM PDT 24
Peak memory 215284 kb
Host smart-9a674bc0-3416-47cc-9cf8-9198db16b2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854974407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1854974407
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3117181881
Short name T693
Test name
Test status
Simulation time 35331008 ps
CPU time 0.91 seconds
Started Aug 09 07:51:12 PM PDT 24
Finished Aug 09 07:51:13 PM PDT 24
Peak memory 215168 kb
Host smart-027bc628-523e-41cc-83b0-78970249a79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117181881 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3117181881
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2568606792
Short name T758
Test name
Test status
Simulation time 47808853 ps
CPU time 0.97 seconds
Started Aug 09 07:51:04 PM PDT 24
Finished Aug 09 07:51:05 PM PDT 24
Peak memory 215204 kb
Host smart-8d401a59-b20b-45c8-9311-544d0805d24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568606792 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2568606792
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1146074299
Short name T506
Test name
Test status
Simulation time 977045182 ps
CPU time 2.94 seconds
Started Aug 09 07:51:02 PM PDT 24
Finished Aug 09 07:51:05 PM PDT 24
Peak memory 217468 kb
Host smart-37d9a0f5-790f-445f-9be6-639979b6dd62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146074299 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1146074299
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2503647508
Short name T242
Test name
Test status
Simulation time 102911226420 ps
CPU time 2223.46 seconds
Started Aug 09 07:51:17 PM PDT 24
Finished Aug 09 08:28:20 PM PDT 24
Peak memory 227312 kb
Host smart-e63a527c-4a6b-4ca5-9cb3-92fdd0ea2928
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503647508 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2503647508
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2509371029
Short name T740
Test name
Test status
Simulation time 27701500 ps
CPU time 1.29 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 220664 kb
Host smart-7fde50d8-277c-49b9-8a32-2de992736093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509371029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2509371029
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1446885537
Short name T802
Test name
Test status
Simulation time 129246798 ps
CPU time 1.86 seconds
Started Aug 09 07:52:43 PM PDT 24
Finished Aug 09 07:52:45 PM PDT 24
Peak memory 218720 kb
Host smart-2830e6e5-b91c-430f-a415-00b047072c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446885537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1446885537
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1425802585
Short name T971
Test name
Test status
Simulation time 35012492 ps
CPU time 1.09 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 219928 kb
Host smart-cd243a4a-3493-4747-81aa-b1af21c4d38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425802585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1425802585
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.95639977
Short name T110
Test name
Test status
Simulation time 38379286 ps
CPU time 1.18 seconds
Started Aug 09 07:52:41 PM PDT 24
Finished Aug 09 07:52:43 PM PDT 24
Peak memory 220100 kb
Host smart-57ed2f39-f2bf-492a-afa4-3230a60bc72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95639977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.95639977
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.3468929339
Short name T163
Test name
Test status
Simulation time 36528816 ps
CPU time 1.11 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 218592 kb
Host smart-87e3e578-f05c-4b16-8a7c-177453714a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468929339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.3468929339
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.2956244968
Short name T691
Test name
Test status
Simulation time 27933347 ps
CPU time 1.29 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 217244 kb
Host smart-3e2127ac-b516-4971-b5e9-f8fd5fbe6ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956244968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2956244968
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.416384120
Short name T317
Test name
Test status
Simulation time 28643785 ps
CPU time 1.21 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 218284 kb
Host smart-86d3b19a-702f-44b1-b230-74898dbcf1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416384120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.416384120
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1757842353
Short name T607
Test name
Test status
Simulation time 98871262 ps
CPU time 1.42 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218908 kb
Host smart-3d663e11-1948-481b-9111-bcb55f8ee71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757842353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1757842353
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.4159267163
Short name T877
Test name
Test status
Simulation time 23651375 ps
CPU time 1.18 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 219464 kb
Host smart-ba96134d-1740-4431-9dab-e85fc919585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159267163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.4159267163
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.1350561278
Short name T950
Test name
Test status
Simulation time 40563081 ps
CPU time 1.42 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:47 PM PDT 24
Peak memory 217332 kb
Host smart-882d21a7-c6aa-42ce-b5a5-edea44ff2392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350561278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1350561278
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3149854858
Short name T444
Test name
Test status
Simulation time 26089951 ps
CPU time 1.21 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 220756 kb
Host smart-413b8083-d81b-4e16-9b90-a7bf07bd3b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149854858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3149854858
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.998070007
Short name T627
Test name
Test status
Simulation time 29856135 ps
CPU time 1.27 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 219580 kb
Host smart-9d0b87e7-1ada-4e5e-bb99-652eb887cdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998070007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.998070007
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2436122833
Short name T884
Test name
Test status
Simulation time 43180037 ps
CPU time 1.27 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 215560 kb
Host smart-4b150ac8-d9e8-4480-8a19-cb86d19986c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436122833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2436122833
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.746037908
Short name T567
Test name
Test status
Simulation time 43395750 ps
CPU time 1.44 seconds
Started Aug 09 07:52:47 PM PDT 24
Finished Aug 09 07:52:48 PM PDT 24
Peak memory 218640 kb
Host smart-3df928f9-94cc-45fa-b711-168ce5f1a4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746037908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.746037908
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1818791015
Short name T576
Test name
Test status
Simulation time 408760219 ps
CPU time 1.43 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 218288 kb
Host smart-44cf2b5c-fa11-499b-a007-0409e8e27264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818791015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1818791015
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.3060260905
Short name T1
Test name
Test status
Simulation time 41394173 ps
CPU time 1.3 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 217352 kb
Host smart-bec94997-484f-42c2-85de-d7885f77794d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060260905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3060260905
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2587810253
Short name T311
Test name
Test status
Simulation time 96561695 ps
CPU time 1.22 seconds
Started Aug 09 07:52:55 PM PDT 24
Finished Aug 09 07:52:56 PM PDT 24
Peak memory 218280 kb
Host smart-0a426fb2-6118-47d4-9478-439e6a1a0257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587810253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2587810253
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.231330389
Short name T399
Test name
Test status
Simulation time 48614210 ps
CPU time 1.84 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218692 kb
Host smart-1dd0fead-34de-4292-a78c-38f4f4a2afdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231330389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.231330389
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.527741693
Short name T891
Test name
Test status
Simulation time 75568674 ps
CPU time 1.22 seconds
Started Aug 09 07:52:44 PM PDT 24
Finished Aug 09 07:52:45 PM PDT 24
Peak memory 220152 kb
Host smart-fe2aa29d-6f71-4952-b4f0-1a7b19a35774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527741693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.527741693
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2445920419
Short name T662
Test name
Test status
Simulation time 109935703 ps
CPU time 1.02 seconds
Started Aug 09 07:52:42 PM PDT 24
Finished Aug 09 07:52:43 PM PDT 24
Peak memory 217260 kb
Host smart-30f229f2-28e6-40b0-a895-e39df24f6197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445920419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2445920419
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1697963970
Short name T960
Test name
Test status
Simulation time 88650484 ps
CPU time 1.1 seconds
Started Aug 09 07:51:14 PM PDT 24
Finished Aug 09 07:51:21 PM PDT 24
Peak memory 219684 kb
Host smart-600b5491-2940-43d7-9864-215af1cae6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697963970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1697963970
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3155786967
Short name T361
Test name
Test status
Simulation time 48654488 ps
CPU time 0.93 seconds
Started Aug 09 07:51:12 PM PDT 24
Finished Aug 09 07:51:13 PM PDT 24
Peak memory 206832 kb
Host smart-3e7b37f8-f24e-4fb2-ac89-a7324119cd94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155786967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3155786967
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3620750410
Short name T584
Test name
Test status
Simulation time 17952558 ps
CPU time 0.85 seconds
Started Aug 09 07:51:14 PM PDT 24
Finished Aug 09 07:51:15 PM PDT 24
Peak memory 216452 kb
Host smart-846a6bcc-8568-4012-b19a-fe51c6d3241b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620750410 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3620750410
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3055972800
Short name T783
Test name
Test status
Simulation time 107442829 ps
CPU time 1.14 seconds
Started Aug 09 07:51:13 PM PDT 24
Finished Aug 09 07:51:15 PM PDT 24
Peak memory 219680 kb
Host smart-776380de-5869-4ff3-ac9b-e76156904335
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055972800 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3055972800
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2284850005
Short name T154
Test name
Test status
Simulation time 24071780 ps
CPU time 1.21 seconds
Started Aug 09 07:51:11 PM PDT 24
Finished Aug 09 07:51:12 PM PDT 24
Peak memory 219996 kb
Host smart-b83bf415-a3b9-4aa3-a25f-3bdfc387eab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284850005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2284850005
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3435574505
Short name T347
Test name
Test status
Simulation time 94179559 ps
CPU time 1.27 seconds
Started Aug 09 07:51:18 PM PDT 24
Finished Aug 09 07:51:19 PM PDT 24
Peak memory 218976 kb
Host smart-446157d5-a839-4461-b836-2596910dc587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435574505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3435574505
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.392305430
Short name T138
Test name
Test status
Simulation time 41316846 ps
CPU time 0.91 seconds
Started Aug 09 07:51:10 PM PDT 24
Finished Aug 09 07:51:11 PM PDT 24
Peak memory 216000 kb
Host smart-901fcd7c-adda-4b6f-b088-062256f9ab91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392305430 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.392305430
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.64086462
Short name T443
Test name
Test status
Simulation time 44972652 ps
CPU time 0.89 seconds
Started Aug 09 07:51:09 PM PDT 24
Finished Aug 09 07:51:10 PM PDT 24
Peak memory 215276 kb
Host smart-eed666da-2431-496f-8d87-eb63867c9cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64086462 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.64086462
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.4181328506
Short name T478
Test name
Test status
Simulation time 3077958280 ps
CPU time 6.59 seconds
Started Aug 09 07:51:24 PM PDT 24
Finished Aug 09 07:51:30 PM PDT 24
Peak memory 215340 kb
Host smart-3e1ec145-74be-4405-ba34-013da4f1d7a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181328506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.4181328506
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3529800691
Short name T116
Test name
Test status
Simulation time 58206820995 ps
CPU time 353.95 seconds
Started Aug 09 07:51:08 PM PDT 24
Finished Aug 09 07:57:02 PM PDT 24
Peak memory 221824 kb
Host smart-c1f99730-4d7e-44e2-b87a-af56a7379675
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529800691 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3529800691
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.3535864601
Short name T310
Test name
Test status
Simulation time 87289370 ps
CPU time 1.19 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 218412 kb
Host smart-98d50914-a2b2-43a8-9c23-50716496bfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535864601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.3535864601
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3404564613
Short name T961
Test name
Test status
Simulation time 23982150 ps
CPU time 1.12 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 217476 kb
Host smart-b98dc9c3-f904-4847-ac7b-deea024eb41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404564613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3404564613
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2551670065
Short name T858
Test name
Test status
Simulation time 46150934 ps
CPU time 1.21 seconds
Started Aug 09 07:52:44 PM PDT 24
Finished Aug 09 07:52:45 PM PDT 24
Peak memory 220540 kb
Host smart-a2db6b16-3df9-4cf4-b3be-f96acbc4f4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551670065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2551670065
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.748857216
Short name T67
Test name
Test status
Simulation time 88197990 ps
CPU time 1.1 seconds
Started Aug 09 07:52:40 PM PDT 24
Finished Aug 09 07:52:42 PM PDT 24
Peak memory 217424 kb
Host smart-d980d626-f02d-4847-a8f4-a8e9a1d62c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748857216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.748857216
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2028490403
Short name T841
Test name
Test status
Simulation time 77369576 ps
CPU time 1.22 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 218860 kb
Host smart-1d2a98d7-83d0-4a92-b116-cda4a4220b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028490403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2028490403
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1801925907
Short name T237
Test name
Test status
Simulation time 22866622 ps
CPU time 1.18 seconds
Started Aug 09 07:52:50 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 218724 kb
Host smart-bd8fbad0-d4f0-44be-9ae9-a7bb5c3cff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801925907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1801925907
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.3120995367
Short name T548
Test name
Test status
Simulation time 33107510 ps
CPU time 1.37 seconds
Started Aug 09 07:52:44 PM PDT 24
Finished Aug 09 07:52:45 PM PDT 24
Peak memory 218912 kb
Host smart-9697a0dc-9cc6-4372-ac33-d5a6970bb6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120995367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3120995367
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.742582490
Short name T915
Test name
Test status
Simulation time 60838516 ps
CPU time 1.24 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 215264 kb
Host smart-a39ac46e-8337-431a-a181-2679fc695e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742582490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.742582490
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3270812691
Short name T329
Test name
Test status
Simulation time 36322909 ps
CPU time 1.51 seconds
Started Aug 09 07:52:42 PM PDT 24
Finished Aug 09 07:52:44 PM PDT 24
Peak memory 218500 kb
Host smart-d3b4e328-f629-4608-aceb-27c731f2896a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270812691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3270812691
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.3183849315
Short name T233
Test name
Test status
Simulation time 29484115 ps
CPU time 1.27 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 218428 kb
Host smart-d147e88c-1dcd-4631-953b-d0ae4e950cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183849315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3183849315
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3833694420
Short name T12
Test name
Test status
Simulation time 87764551 ps
CPU time 1.17 seconds
Started Aug 09 07:52:46 PM PDT 24
Finished Aug 09 07:52:48 PM PDT 24
Peak memory 220096 kb
Host smart-fb9bf2f5-113f-4ef1-a26c-132be053e28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833694420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3833694420
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.4091632837
Short name T844
Test name
Test status
Simulation time 65365599 ps
CPU time 1.04 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218392 kb
Host smart-810f3f28-0dcb-423c-a32d-53ac87cbd5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091632837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.4091632837
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.4242576739
Short name T519
Test name
Test status
Simulation time 212935623 ps
CPU time 2.94 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:54 PM PDT 24
Peak memory 217508 kb
Host smart-2b8f2a73-4ef8-4ea6-a536-c6e4105e3af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242576739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4242576739
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2256163730
Short name T810
Test name
Test status
Simulation time 75698630 ps
CPU time 1.16 seconds
Started Aug 09 07:52:47 PM PDT 24
Finished Aug 09 07:52:49 PM PDT 24
Peak memory 218368 kb
Host smart-362671c4-877e-4c44-932b-84efd0459506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256163730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2256163730
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.1207718116
Short name T485
Test name
Test status
Simulation time 66987256 ps
CPU time 1.21 seconds
Started Aug 09 07:52:49 PM PDT 24
Finished Aug 09 07:52:50 PM PDT 24
Peak memory 220028 kb
Host smart-015488a1-1e5b-4103-b523-92789e818f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207718116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1207718116
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.3647001906
Short name T530
Test name
Test status
Simulation time 37763184 ps
CPU time 1.07 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 219236 kb
Host smart-922d736a-331e-4140-acba-3e15e170809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647001906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3647001906
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.848412311
Short name T759
Test name
Test status
Simulation time 71039493 ps
CPU time 1.21 seconds
Started Aug 09 07:51:13 PM PDT 24
Finished Aug 09 07:51:19 PM PDT 24
Peak memory 219440 kb
Host smart-b94295af-094c-4963-89f7-36aeccbd7d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848412311 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.848412311
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1902379291
Short name T403
Test name
Test status
Simulation time 63903494 ps
CPU time 0.85 seconds
Started Aug 09 07:51:14 PM PDT 24
Finished Aug 09 07:51:15 PM PDT 24
Peak memory 206812 kb
Host smart-5368cbd7-67da-4c7c-b790-a449611cec2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902379291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1902379291
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.4108927647
Short name T644
Test name
Test status
Simulation time 31922931 ps
CPU time 0.84 seconds
Started Aug 09 07:51:11 PM PDT 24
Finished Aug 09 07:51:12 PM PDT 24
Peak memory 216264 kb
Host smart-d9d3ea93-ba6b-427e-bc70-eb5c9c29a5be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108927647 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.4108927647
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1086734138
Short name T528
Test name
Test status
Simulation time 32409238 ps
CPU time 1.22 seconds
Started Aug 09 07:51:14 PM PDT 24
Finished Aug 09 07:51:16 PM PDT 24
Peak memory 217524 kb
Host smart-9dc91b00-9d02-46bc-b038-cf535e88da1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086734138 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1086734138
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_genbits.3154536686
Short name T52
Test name
Test status
Simulation time 114839312 ps
CPU time 1.47 seconds
Started Aug 09 07:51:15 PM PDT 24
Finished Aug 09 07:51:16 PM PDT 24
Peak memory 219768 kb
Host smart-74b3d3f8-6c60-4ba7-8256-90f0d0bf0116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154536686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3154536686
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.378188357
Short name T395
Test name
Test status
Simulation time 23529763 ps
CPU time 0.92 seconds
Started Aug 09 07:51:14 PM PDT 24
Finished Aug 09 07:51:25 PM PDT 24
Peak memory 215492 kb
Host smart-0946ec70-7faa-4e31-9f80-090cea61d388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378188357 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.378188357
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3508667193
Short name T670
Test name
Test status
Simulation time 62988308 ps
CPU time 0.91 seconds
Started Aug 09 07:51:13 PM PDT 24
Finished Aug 09 07:51:14 PM PDT 24
Peak memory 215312 kb
Host smart-dc38e707-e4d0-411a-8216-988300466140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508667193 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3508667193
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2859718636
Short name T380
Test name
Test status
Simulation time 707478541 ps
CPU time 5.19 seconds
Started Aug 09 07:51:09 PM PDT 24
Finished Aug 09 07:51:15 PM PDT 24
Peak memory 217240 kb
Host smart-2f1e94b3-725b-4e18-9e5f-303d9f3165e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859718636 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2859718636
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3000183271
Short name T555
Test name
Test status
Simulation time 86610899787 ps
CPU time 582.06 seconds
Started Aug 09 07:51:12 PM PDT 24
Finished Aug 09 08:00:54 PM PDT 24
Peak memory 220352 kb
Host smart-2347f6d8-1f3b-4fb1-ab6e-a7d3f1020deb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000183271 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3000183271
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2492473350
Short name T300
Test name
Test status
Simulation time 177593071 ps
CPU time 1.23 seconds
Started Aug 09 07:52:46 PM PDT 24
Finished Aug 09 07:52:47 PM PDT 24
Peak memory 218256 kb
Host smart-253e41fe-e245-4648-82c2-5e97c02e8524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492473350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2492473350
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3363759174
Short name T806
Test name
Test status
Simulation time 58679851 ps
CPU time 1.19 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 219972 kb
Host smart-fc62c0e1-1de4-42b3-b305-b5fb66936140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363759174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3363759174
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3897887898
Short name T416
Test name
Test status
Simulation time 73071795 ps
CPU time 1.21 seconds
Started Aug 09 07:52:46 PM PDT 24
Finished Aug 09 07:52:47 PM PDT 24
Peak memory 220352 kb
Host smart-990a0808-c3ce-4ca1-a444-8f6b905dc9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897887898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3897887898
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2556293793
Short name T798
Test name
Test status
Simulation time 85611196 ps
CPU time 1.48 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:47 PM PDT 24
Peak memory 219036 kb
Host smart-d2e40be5-890a-4089-81c1-6ca158cdf17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556293793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2556293793
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3062780755
Short name T255
Test name
Test status
Simulation time 48922875 ps
CPU time 1.21 seconds
Started Aug 09 07:52:50 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 219524 kb
Host smart-d50e542f-8336-436a-b679-f7327febfc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062780755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3062780755
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3605718364
Short name T615
Test name
Test status
Simulation time 63758094 ps
CPU time 1.61 seconds
Started Aug 09 07:52:47 PM PDT 24
Finished Aug 09 07:52:49 PM PDT 24
Peak memory 218884 kb
Host smart-ba6e521a-998d-4a96-9ec8-90f644350988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605718364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3605718364
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2365348318
Short name T106
Test name
Test status
Simulation time 121370959 ps
CPU time 1.12 seconds
Started Aug 09 07:52:50 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 220124 kb
Host smart-2bff2610-922e-4574-a9e4-5c97eea683fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365348318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2365348318
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.3993185596
Short name T33
Test name
Test status
Simulation time 38500493 ps
CPU time 1.77 seconds
Started Aug 09 07:52:44 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 218568 kb
Host smart-1c7595ce-3acf-4ce3-9a5c-5bc59a310268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993185596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3993185596
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2803893139
Short name T396
Test name
Test status
Simulation time 28048805 ps
CPU time 1.26 seconds
Started Aug 09 07:52:49 PM PDT 24
Finished Aug 09 07:52:50 PM PDT 24
Peak memory 218632 kb
Host smart-1f346756-a6ac-44d7-a528-b26be27448ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803893139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2803893139
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2882878486
Short name T678
Test name
Test status
Simulation time 57579713 ps
CPU time 1.27 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:39 PM PDT 24
Peak memory 217272 kb
Host smart-66a8bd3c-fec2-4e54-9ac1-e519a5eb5ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882878486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2882878486
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.4145070235
Short name T551
Test name
Test status
Simulation time 86885426 ps
CPU time 1.26 seconds
Started Aug 09 07:52:47 PM PDT 24
Finished Aug 09 07:52:49 PM PDT 24
Peak memory 218532 kb
Host smart-0b612c4b-ebe1-4f7a-b506-900d1733c035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145070235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.4145070235
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3011779064
Short name T741
Test name
Test status
Simulation time 80752973 ps
CPU time 1.26 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 218716 kb
Host smart-6abe4f7a-1ee4-4443-998b-f710b705aead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011779064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3011779064
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1583418918
Short name T911
Test name
Test status
Simulation time 102031423 ps
CPU time 1.16 seconds
Started Aug 09 07:52:59 PM PDT 24
Finished Aug 09 07:53:00 PM PDT 24
Peak memory 218372 kb
Host smart-343055d7-74f9-4ac6-8d21-165bc98296ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583418918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1583418918
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3077343021
Short name T340
Test name
Test status
Simulation time 84902739 ps
CPU time 2.46 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:54 PM PDT 24
Peak memory 220108 kb
Host smart-0911de9c-9d4b-495e-afb6-218f77d9ac70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077343021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3077343021
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.409511596
Short name T438
Test name
Test status
Simulation time 45925081 ps
CPU time 1.24 seconds
Started Aug 09 07:52:49 PM PDT 24
Finished Aug 09 07:52:51 PM PDT 24
Peak memory 219696 kb
Host smart-ca777b37-7f65-4542-ab91-fcca0fb52766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409511596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.409511596
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3829192017
Short name T968
Test name
Test status
Simulation time 31546577 ps
CPU time 1.28 seconds
Started Aug 09 07:52:55 PM PDT 24
Finished Aug 09 07:52:56 PM PDT 24
Peak memory 215328 kb
Host smart-aa6357de-2519-4a7b-9e5e-8cc2c609e1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829192017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3829192017
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.4190817602
Short name T840
Test name
Test status
Simulation time 27814594 ps
CPU time 1.38 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 218528 kb
Host smart-11e2a0d4-b9b0-465c-8fe5-c33582cc9648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190817602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.4190817602
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3504942099
Short name T618
Test name
Test status
Simulation time 64186197 ps
CPU time 1.34 seconds
Started Aug 09 07:52:56 PM PDT 24
Finished Aug 09 07:52:57 PM PDT 24
Peak memory 218608 kb
Host smart-5f5f992e-2ae9-45af-a548-1e4bcdddb62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504942099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3504942099
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1642739462
Short name T736
Test name
Test status
Simulation time 29392345 ps
CPU time 1.24 seconds
Started Aug 09 07:52:44 PM PDT 24
Finished Aug 09 07:52:45 PM PDT 24
Peak memory 218840 kb
Host smart-15670c32-ba21-43d9-bb49-a62799d97075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642739462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1642739462
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert.3539503237
Short name T318
Test name
Test status
Simulation time 78335399 ps
CPU time 1.23 seconds
Started Aug 09 07:50:39 PM PDT 24
Finished Aug 09 07:50:41 PM PDT 24
Peak memory 219392 kb
Host smart-943489d8-0da0-4681-a168-d49f1bc4a0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539503237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3539503237
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1572814049
Short name T772
Test name
Test status
Simulation time 36548561 ps
CPU time 0.92 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 07:50:42 PM PDT 24
Peak memory 215040 kb
Host smart-a70226b4-8f04-4b50-96c8-06ee0358668a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572814049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1572814049
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.574886470
Short name T177
Test name
Test status
Simulation time 16632826 ps
CPU time 0.93 seconds
Started Aug 09 07:50:38 PM PDT 24
Finished Aug 09 07:50:39 PM PDT 24
Peak memory 215356 kb
Host smart-9071314f-e34a-42d8-922e-ab3d59fdd7ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574886470 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.574886470
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.169630707
Short name T776
Test name
Test status
Simulation time 26101877 ps
CPU time 1.1 seconds
Started Aug 09 07:50:40 PM PDT 24
Finished Aug 09 07:50:42 PM PDT 24
Peak memory 218668 kb
Host smart-943ce248-e7e3-41de-b261-c8c4f9cd29b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169630707 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.169630707
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.4162498196
Short name T219
Test name
Test status
Simulation time 26286506 ps
CPU time 1.27 seconds
Started Aug 09 07:50:39 PM PDT 24
Finished Aug 09 07:50:40 PM PDT 24
Peak memory 221152 kb
Host smart-b5163ee0-5471-4c05-b623-fd3e73e184c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162498196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4162498196
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_regwen.2022667003
Short name T313
Test name
Test status
Simulation time 16103481 ps
CPU time 0.99 seconds
Started Aug 09 07:50:40 PM PDT 24
Finished Aug 09 07:50:41 PM PDT 24
Peak memory 207072 kb
Host smart-2c46049a-9c32-4112-97e6-65caea5db8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022667003 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2022667003
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1213778167
Short name T74
Test name
Test status
Simulation time 1391043177 ps
CPU time 5.15 seconds
Started Aug 09 07:50:39 PM PDT 24
Finished Aug 09 07:50:44 PM PDT 24
Peak memory 237840 kb
Host smart-b7625994-3740-4315-92d4-c353d886baef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213778167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1213778167
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3331718687
Short name T598
Test name
Test status
Simulation time 18336006 ps
CPU time 1.01 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 07:50:42 PM PDT 24
Peak memory 215316 kb
Host smart-65070df9-4bfd-4d5b-9269-341388f95d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331718687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3331718687
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.4174869690
Short name T415
Test name
Test status
Simulation time 100827385 ps
CPU time 1.72 seconds
Started Aug 09 07:50:40 PM PDT 24
Finished Aug 09 07:50:42 PM PDT 24
Peak memory 217092 kb
Host smart-f6e417f4-b145-4316-9609-e310727d243b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174869690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.4174869690
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.219450578
Short name T247
Test name
Test status
Simulation time 54159347541 ps
CPU time 1149.74 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 08:09:51 PM PDT 24
Peak memory 219960 kb
Host smart-4f329fa0-b2ba-4933-b53b-6d6211b933a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219450578 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.219450578
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1232000147
Short name T128
Test name
Test status
Simulation time 34204509 ps
CPU time 1.43 seconds
Started Aug 09 07:51:16 PM PDT 24
Finished Aug 09 07:51:18 PM PDT 24
Peak memory 220268 kb
Host smart-acfdace3-f12d-467b-89a7-1ec5f21ec7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232000147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1232000147
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3009780654
Short name T602
Test name
Test status
Simulation time 33648618 ps
CPU time 0.94 seconds
Started Aug 09 07:51:13 PM PDT 24
Finished Aug 09 07:51:14 PM PDT 24
Peak memory 215152 kb
Host smart-9dfcfd26-a937-4603-8eb4-4b90244732e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009780654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3009780654
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3888783848
Short name T374
Test name
Test status
Simulation time 12569631 ps
CPU time 0.91 seconds
Started Aug 09 07:51:17 PM PDT 24
Finished Aug 09 07:51:18 PM PDT 24
Peak memory 216396 kb
Host smart-19f69a06-1e54-49fa-a84c-02eff6cbb981
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888783848 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3888783848
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1695192069
Short name T655
Test name
Test status
Simulation time 41736312 ps
CPU time 1.37 seconds
Started Aug 09 07:51:13 PM PDT 24
Finished Aug 09 07:51:15 PM PDT 24
Peak memory 217208 kb
Host smart-80bf3828-f72d-4db2-9427-b71349e588e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695192069 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1695192069
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2788713209
Short name T6
Test name
Test status
Simulation time 79927975 ps
CPU time 1.04 seconds
Started Aug 09 07:51:11 PM PDT 24
Finished Aug 09 07:51:12 PM PDT 24
Peak memory 221072 kb
Host smart-1b2abe90-872c-49b9-8e3f-f06b05084ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788713209 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2788713209
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2446939658
Short name T348
Test name
Test status
Simulation time 164872401 ps
CPU time 2.41 seconds
Started Aug 09 07:51:15 PM PDT 24
Finished Aug 09 07:51:17 PM PDT 24
Peak memory 220152 kb
Host smart-83d06baa-1380-4acd-b76c-9827443ea617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446939658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2446939658
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.285239085
Short name T837
Test name
Test status
Simulation time 37825301 ps
CPU time 0.86 seconds
Started Aug 09 07:51:12 PM PDT 24
Finished Aug 09 07:51:13 PM PDT 24
Peak memory 215276 kb
Host smart-845c3d05-a925-46f1-82a8-5763ae63f022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285239085 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.285239085
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2777924405
Short name T450
Test name
Test status
Simulation time 22589025 ps
CPU time 1.01 seconds
Started Aug 09 07:51:15 PM PDT 24
Finished Aug 09 07:51:21 PM PDT 24
Peak memory 215292 kb
Host smart-4079a697-e15b-4fe3-864f-8b4449bc3ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777924405 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2777924405
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1754578574
Short name T801
Test name
Test status
Simulation time 339158006 ps
CPU time 6.58 seconds
Started Aug 09 07:51:21 PM PDT 24
Finished Aug 09 07:51:28 PM PDT 24
Peak memory 220200 kb
Host smart-81bab69d-a7ae-446f-b606-93802761575f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754578574 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1754578574
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3456099152
Short name T796
Test name
Test status
Simulation time 201438950732 ps
CPU time 639.6 seconds
Started Aug 09 07:51:14 PM PDT 24
Finished Aug 09 08:01:54 PM PDT 24
Peak memory 220764 kb
Host smart-5c0395c1-6331-4e08-91f3-fc75c5204d47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456099152 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3456099152
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/201.edn_genbits.3211641063
Short name T25
Test name
Test status
Simulation time 90004016 ps
CPU time 3.13 seconds
Started Aug 09 07:52:53 PM PDT 24
Finished Aug 09 07:52:57 PM PDT 24
Peak memory 220424 kb
Host smart-55136a53-71ed-4175-b1a6-143958acc781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211641063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3211641063
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.4110303565
Short name T682
Test name
Test status
Simulation time 92229561 ps
CPU time 1.42 seconds
Started Aug 09 07:52:42 PM PDT 24
Finished Aug 09 07:52:44 PM PDT 24
Peak memory 217612 kb
Host smart-9eb9d835-5b06-4828-9f67-cfb80ae77101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110303565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.4110303565
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3683677358
Short name T298
Test name
Test status
Simulation time 45712438 ps
CPU time 1.49 seconds
Started Aug 09 07:53:06 PM PDT 24
Finished Aug 09 07:53:08 PM PDT 24
Peak memory 218392 kb
Host smart-04908f72-bfc2-4fce-9dd9-016463c4f0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683677358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3683677358
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.577573962
Short name T339
Test name
Test status
Simulation time 94735142 ps
CPU time 1.56 seconds
Started Aug 09 07:53:00 PM PDT 24
Finished Aug 09 07:53:02 PM PDT 24
Peak memory 218548 kb
Host smart-c5b9e312-2a8d-4338-aabd-c0b5c9b22eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577573962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.577573962
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3426856877
Short name T733
Test name
Test status
Simulation time 45563079 ps
CPU time 1.26 seconds
Started Aug 09 07:52:47 PM PDT 24
Finished Aug 09 07:52:48 PM PDT 24
Peak memory 218756 kb
Host smart-67a8314d-9c25-4582-a86d-6495643c2738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426856877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3426856877
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.678867267
Short name T343
Test name
Test status
Simulation time 173126339 ps
CPU time 3.3 seconds
Started Aug 09 07:52:41 PM PDT 24
Finished Aug 09 07:52:45 PM PDT 24
Peak memory 220424 kb
Host smart-6eed6437-a2dd-4520-9b7f-c09db7340967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678867267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.678867267
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3784999595
Short name T730
Test name
Test status
Simulation time 121897843 ps
CPU time 1.21 seconds
Started Aug 09 07:52:59 PM PDT 24
Finished Aug 09 07:53:00 PM PDT 24
Peak memory 218692 kb
Host smart-39a1ac72-ad27-44c5-bb2f-e7bfa2d9ca53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784999595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3784999595
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.848486056
Short name T392
Test name
Test status
Simulation time 157420238 ps
CPU time 2.12 seconds
Started Aug 09 07:52:50 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 217672 kb
Host smart-21c9a519-8ae0-461b-a445-3934e1339f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848486056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.848486056
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.624530383
Short name T385
Test name
Test status
Simulation time 45981118 ps
CPU time 1.63 seconds
Started Aug 09 07:52:54 PM PDT 24
Finished Aug 09 07:52:55 PM PDT 24
Peak memory 220188 kb
Host smart-9aeda0f8-b19e-4769-ad13-8a05178653b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624530383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.624530383
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.4220498284
Short name T492
Test name
Test status
Simulation time 23779999 ps
CPU time 1.19 seconds
Started Aug 09 07:51:14 PM PDT 24
Finished Aug 09 07:51:15 PM PDT 24
Peak memory 220184 kb
Host smart-6e304013-9705-4687-a5f1-4df954a8f485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220498284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.4220498284
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.929018656
Short name T397
Test name
Test status
Simulation time 53081307 ps
CPU time 0.9 seconds
Started Aug 09 07:51:09 PM PDT 24
Finished Aug 09 07:51:10 PM PDT 24
Peak memory 215148 kb
Host smart-03db9e40-952a-4579-81c0-38f7c4965286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929018656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.929018656
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1064002614
Short name T777
Test name
Test status
Simulation time 81503549 ps
CPU time 1.23 seconds
Started Aug 09 07:51:08 PM PDT 24
Finished Aug 09 07:51:09 PM PDT 24
Peak memory 217112 kb
Host smart-90fb7493-8e00-44d6-9f81-264170448321
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064002614 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1064002614
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.369661608
Short name T93
Test name
Test status
Simulation time 22521014 ps
CPU time 0.88 seconds
Started Aug 09 07:51:07 PM PDT 24
Finished Aug 09 07:51:08 PM PDT 24
Peak memory 218768 kb
Host smart-985e7cb8-f6c8-4e56-a08c-e8a6c8abf269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369661608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.369661608
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1386056267
Short name T782
Test name
Test status
Simulation time 77967000 ps
CPU time 1.35 seconds
Started Aug 09 07:51:10 PM PDT 24
Finished Aug 09 07:51:11 PM PDT 24
Peak memory 219092 kb
Host smart-9be3ad86-fab7-4ce1-a167-ad8fe04d751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386056267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1386056267
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1570325141
Short name T428
Test name
Test status
Simulation time 64129713 ps
CPU time 0.85 seconds
Started Aug 09 07:51:13 PM PDT 24
Finished Aug 09 07:51:14 PM PDT 24
Peak memory 215204 kb
Host smart-991943d2-9e31-4ba7-8381-81ddd476df15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570325141 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1570325141
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.609454004
Short name T947
Test name
Test status
Simulation time 29393002 ps
CPU time 0.94 seconds
Started Aug 09 07:51:12 PM PDT 24
Finished Aug 09 07:51:13 PM PDT 24
Peak memory 215280 kb
Host smart-4dadd3ce-680f-4d28-a42f-3cd4a8dedc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609454004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.609454004
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1478421377
Short name T789
Test name
Test status
Simulation time 299682592 ps
CPU time 2.18 seconds
Started Aug 09 07:51:12 PM PDT 24
Finished Aug 09 07:51:14 PM PDT 24
Peak memory 217624 kb
Host smart-0e3cee6d-af62-446b-b03f-13f3589532d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478421377 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1478421377
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.4252615153
Short name T768
Test name
Test status
Simulation time 54983872706 ps
CPU time 618.38 seconds
Started Aug 09 07:51:28 PM PDT 24
Finished Aug 09 08:01:47 PM PDT 24
Peak memory 223648 kb
Host smart-6528ae15-876a-4ef2-94ec-4c50cbd6c31a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252615153 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.4252615153
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1414508742
Short name T899
Test name
Test status
Simulation time 100451613 ps
CPU time 1.91 seconds
Started Aug 09 07:52:38 PM PDT 24
Finished Aug 09 07:52:41 PM PDT 24
Peak memory 219312 kb
Host smart-c1c4822e-fed6-4e22-b769-f6866e79104f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414508742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1414508742
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1889821404
Short name T296
Test name
Test status
Simulation time 240318463 ps
CPU time 1.13 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 217340 kb
Host smart-3ec0df66-3e3e-43e8-86cd-3672c1b6befe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889821404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1889821404
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1433708183
Short name T494
Test name
Test status
Simulation time 30564734 ps
CPU time 1.27 seconds
Started Aug 09 07:52:43 PM PDT 24
Finished Aug 09 07:52:44 PM PDT 24
Peak memory 217548 kb
Host smart-aedac525-0d69-4615-b3d7-024c2eb596d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433708183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1433708183
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.866031692
Short name T770
Test name
Test status
Simulation time 52413471 ps
CPU time 1.62 seconds
Started Aug 09 07:52:57 PM PDT 24
Finished Aug 09 07:52:59 PM PDT 24
Peak memory 218512 kb
Host smart-46f1cc8e-da39-461e-b68f-0b14fc7d3490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866031692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.866031692
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2466353540
Short name T828
Test name
Test status
Simulation time 38663960 ps
CPU time 1.35 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 217544 kb
Host smart-9a88cb9c-0be0-42e3-a010-906481561532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466353540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2466353540
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2920503190
Short name T657
Test name
Test status
Simulation time 45308935 ps
CPU time 1.46 seconds
Started Aug 09 07:52:54 PM PDT 24
Finished Aug 09 07:52:55 PM PDT 24
Peak memory 218768 kb
Host smart-6408ef0d-470d-410d-8c81-1b1eac8ce5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920503190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2920503190
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3923263822
Short name T750
Test name
Test status
Simulation time 99593493 ps
CPU time 1.15 seconds
Started Aug 09 07:52:49 PM PDT 24
Finished Aug 09 07:52:50 PM PDT 24
Peak memory 218528 kb
Host smart-2272befd-5173-46e8-bffb-a8612486d405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923263822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3923263822
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2656511722
Short name T463
Test name
Test status
Simulation time 40753781 ps
CPU time 1.49 seconds
Started Aug 09 07:52:49 PM PDT 24
Finished Aug 09 07:52:51 PM PDT 24
Peak memory 218596 kb
Host smart-ae5dbbbd-4841-4255-a68e-a22addeefb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656511722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2656511722
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.427954552
Short name T937
Test name
Test status
Simulation time 92697875 ps
CPU time 1.14 seconds
Started Aug 09 07:52:52 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 218864 kb
Host smart-8255bc6c-bd68-4807-b0f3-02a226510bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427954552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.427954552
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1215882317
Short name T760
Test name
Test status
Simulation time 116958456 ps
CPU time 1.36 seconds
Started Aug 09 07:52:54 PM PDT 24
Finished Aug 09 07:52:55 PM PDT 24
Peak memory 219100 kb
Host smart-b1785299-9ef0-41ac-af57-2c70834e2388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215882317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1215882317
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2959672301
Short name T168
Test name
Test status
Simulation time 118480811 ps
CPU time 1.28 seconds
Started Aug 09 07:51:14 PM PDT 24
Finished Aug 09 07:51:15 PM PDT 24
Peak memory 218424 kb
Host smart-915e5168-dc23-4f57-943a-c41298271ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959672301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2959672301
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2369639982
Short name T970
Test name
Test status
Simulation time 114653656 ps
CPU time 0.85 seconds
Started Aug 09 07:51:25 PM PDT 24
Finished Aug 09 07:51:26 PM PDT 24
Peak memory 206616 kb
Host smart-7b0ff39e-e9a5-4a29-ae53-404488953210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369639982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2369639982
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2906178929
Short name T756
Test name
Test status
Simulation time 23897510 ps
CPU time 0.88 seconds
Started Aug 09 07:51:16 PM PDT 24
Finished Aug 09 07:51:17 PM PDT 24
Peak memory 216536 kb
Host smart-434cb1fa-1f04-4a7c-a822-ea4c9622f20c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906178929 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2906178929
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1853566582
Short name T89
Test name
Test status
Simulation time 80100525 ps
CPU time 1.16 seconds
Started Aug 09 07:51:10 PM PDT 24
Finished Aug 09 07:51:11 PM PDT 24
Peak memory 217104 kb
Host smart-9b78d9eb-5ca9-49df-b874-8abe8327365a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853566582 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1853566582
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1800338393
Short name T780
Test name
Test status
Simulation time 21607124 ps
CPU time 1.11 seconds
Started Aug 09 07:51:27 PM PDT 24
Finished Aug 09 07:51:28 PM PDT 24
Peak memory 224128 kb
Host smart-0b6f6a4f-3f5d-4b29-a9d4-e5c055cbfb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800338393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1800338393
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1953974772
Short name T586
Test name
Test status
Simulation time 119950616 ps
CPU time 1.57 seconds
Started Aug 09 07:51:08 PM PDT 24
Finished Aug 09 07:51:10 PM PDT 24
Peak memory 218444 kb
Host smart-b4869e8a-3120-4baf-8aa2-aff7a11ac55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953974772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1953974772
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1905186021
Short name T900
Test name
Test status
Simulation time 31872566 ps
CPU time 0.9 seconds
Started Aug 09 07:51:13 PM PDT 24
Finished Aug 09 07:51:14 PM PDT 24
Peak memory 216296 kb
Host smart-b50f84e3-facb-4f93-94c4-83bb01173101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905186021 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1905186021
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1092900133
Short name T390
Test name
Test status
Simulation time 35614341 ps
CPU time 0.87 seconds
Started Aug 09 07:51:26 PM PDT 24
Finished Aug 09 07:51:26 PM PDT 24
Peak memory 215288 kb
Host smart-3d5c9893-3a18-4879-b972-a5955df06dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092900133 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1092900133
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3891175292
Short name T525
Test name
Test status
Simulation time 364278647 ps
CPU time 2.66 seconds
Started Aug 09 07:51:11 PM PDT 24
Finished Aug 09 07:51:14 PM PDT 24
Peak memory 217372 kb
Host smart-8609debc-4840-47ff-97dd-7f1ac3fc7ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891175292 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3891175292
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2648998813
Short name T241
Test name
Test status
Simulation time 414916224838 ps
CPU time 1291.87 seconds
Started Aug 09 07:51:13 PM PDT 24
Finished Aug 09 08:12:45 PM PDT 24
Peak memory 223612 kb
Host smart-750472e5-c7f2-49ac-8f1e-74e5abf20845
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648998813 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2648998813
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1537149753
Short name T560
Test name
Test status
Simulation time 51490009 ps
CPU time 1.3 seconds
Started Aug 09 07:53:00 PM PDT 24
Finished Aug 09 07:53:01 PM PDT 24
Peak memory 218680 kb
Host smart-9aaa2e76-cb87-4d3b-98f3-65e30ec6243c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537149753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1537149753
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2259821455
Short name T26
Test name
Test status
Simulation time 134002065 ps
CPU time 1.09 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 219940 kb
Host smart-87e6986e-7c38-458d-be4c-31675e8d5235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259821455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2259821455
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1620089658
Short name T127
Test name
Test status
Simulation time 46761279 ps
CPU time 1.49 seconds
Started Aug 09 07:52:46 PM PDT 24
Finished Aug 09 07:52:48 PM PDT 24
Peak memory 218472 kb
Host smart-f3428a00-9585-418f-a69b-84414bd9798d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620089658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1620089658
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.809774240
Short name T326
Test name
Test status
Simulation time 36473673 ps
CPU time 1.44 seconds
Started Aug 09 07:52:55 PM PDT 24
Finished Aug 09 07:52:57 PM PDT 24
Peak memory 218572 kb
Host smart-f6be3b50-51d2-41ab-83a9-6abdd55f861e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809774240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.809774240
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2610071583
Short name T424
Test name
Test status
Simulation time 277939288 ps
CPU time 2.72 seconds
Started Aug 09 07:52:49 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 220148 kb
Host smart-83652d62-65bb-4479-a651-eed0403b85d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610071583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2610071583
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.562011427
Short name T658
Test name
Test status
Simulation time 62441067 ps
CPU time 1.32 seconds
Started Aug 09 07:52:48 PM PDT 24
Finished Aug 09 07:52:50 PM PDT 24
Peak memory 218592 kb
Host smart-f686e8ef-0034-47e5-a3bd-a403e9d923ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562011427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.562011427
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1027865006
Short name T909
Test name
Test status
Simulation time 42785285 ps
CPU time 1.25 seconds
Started Aug 09 07:52:50 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 217492 kb
Host smart-638d0249-e409-4c64-8f36-24d3e94f8375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027865006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1027865006
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2490375596
Short name T335
Test name
Test status
Simulation time 37639417 ps
CPU time 1.37 seconds
Started Aug 09 07:52:48 PM PDT 24
Finished Aug 09 07:52:54 PM PDT 24
Peak memory 217484 kb
Host smart-20c94bee-73c8-459d-b12f-c19d77211fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490375596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2490375596
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2667680443
Short name T121
Test name
Test status
Simulation time 95036412 ps
CPU time 1.27 seconds
Started Aug 09 07:52:49 PM PDT 24
Finished Aug 09 07:52:50 PM PDT 24
Peak memory 217456 kb
Host smart-23560e60-7cb1-4714-9ac1-049cf7912a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667680443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2667680443
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3525728750
Short name T874
Test name
Test status
Simulation time 82347684 ps
CPU time 1.29 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 217340 kb
Host smart-a9c68e28-bb42-477b-b9fa-48d880122605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525728750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3525728750
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3453889744
Short name T262
Test name
Test status
Simulation time 333472824 ps
CPU time 1.55 seconds
Started Aug 09 07:51:12 PM PDT 24
Finished Aug 09 07:51:14 PM PDT 24
Peak memory 219736 kb
Host smart-e1ee7324-6a40-4036-8b4b-e1b2ca29aa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453889744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3453889744
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.957474752
Short name T788
Test name
Test status
Simulation time 22741502 ps
CPU time 1.04 seconds
Started Aug 09 07:51:26 PM PDT 24
Finished Aug 09 07:51:27 PM PDT 24
Peak memory 206868 kb
Host smart-48bc16c0-574b-4e53-9fd8-48ee6712ea7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957474752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.957474752
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.162980197
Short name T907
Test name
Test status
Simulation time 12014151 ps
CPU time 0.9 seconds
Started Aug 09 07:51:23 PM PDT 24
Finished Aug 09 07:51:24 PM PDT 24
Peak memory 216652 kb
Host smart-8672ecf0-38b2-41b0-80f6-ca6f749572b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162980197 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.162980197
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2412970740
Short name T105
Test name
Test status
Simulation time 276760066 ps
CPU time 1.01 seconds
Started Aug 09 07:51:20 PM PDT 24
Finished Aug 09 07:51:21 PM PDT 24
Peak memory 219688 kb
Host smart-752b7e53-d7cd-4a8d-a6fe-88a3ed6e2f12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412970740 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2412970740
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.660837706
Short name T132
Test name
Test status
Simulation time 20715714 ps
CPU time 1.17 seconds
Started Aug 09 07:51:21 PM PDT 24
Finished Aug 09 07:51:22 PM PDT 24
Peak memory 220040 kb
Host smart-a29f40d9-be0b-470f-ba57-f3fe6a7c0939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660837706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.660837706
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1792190898
Short name T445
Test name
Test status
Simulation time 27395935 ps
CPU time 1.14 seconds
Started Aug 09 07:51:22 PM PDT 24
Finished Aug 09 07:51:23 PM PDT 24
Peak memory 217192 kb
Host smart-05876551-39ca-421e-9f76-878217a4ba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792190898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1792190898
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2323732921
Short name T112
Test name
Test status
Simulation time 21374241 ps
CPU time 1.05 seconds
Started Aug 09 07:51:12 PM PDT 24
Finished Aug 09 07:51:13 PM PDT 24
Peak memory 215924 kb
Host smart-a4db45b0-f627-479e-b9a8-9f133b26596a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323732921 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2323732921
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2445202228
Short name T489
Test name
Test status
Simulation time 29317033 ps
CPU time 0.93 seconds
Started Aug 09 07:51:12 PM PDT 24
Finished Aug 09 07:51:13 PM PDT 24
Peak memory 215264 kb
Host smart-7aa1a200-7407-40c4-9e17-3a1fdc901d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445202228 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2445202228
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1451894640
Short name T690
Test name
Test status
Simulation time 987353064 ps
CPU time 4.98 seconds
Started Aug 09 07:51:17 PM PDT 24
Finished Aug 09 07:51:22 PM PDT 24
Peak memory 217428 kb
Host smart-9e467bf6-ac79-4a72-8d2f-0870c6567c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451894640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1451894640
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3516259728
Short name T757
Test name
Test status
Simulation time 378314195536 ps
CPU time 1466.89 seconds
Started Aug 09 07:51:09 PM PDT 24
Finished Aug 09 08:15:36 PM PDT 24
Peak memory 223576 kb
Host smart-eaff37e9-6156-4266-8187-a09317e8be3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516259728 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3516259728
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/231.edn_genbits.2259665330
Short name T569
Test name
Test status
Simulation time 236935272 ps
CPU time 3.21 seconds
Started Aug 09 07:52:58 PM PDT 24
Finished Aug 09 07:53:01 PM PDT 24
Peak memory 218896 kb
Host smart-7bedf533-373e-415c-a075-7fc90f31bc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259665330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2259665330
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.936467351
Short name T446
Test name
Test status
Simulation time 48797380 ps
CPU time 1.08 seconds
Started Aug 09 07:52:47 PM PDT 24
Finished Aug 09 07:52:49 PM PDT 24
Peak memory 217192 kb
Host smart-68eed0a6-d9ec-40fb-914d-f9450b57c7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936467351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.936467351
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1891755072
Short name T562
Test name
Test status
Simulation time 57620635 ps
CPU time 2.07 seconds
Started Aug 09 07:53:03 PM PDT 24
Finished Aug 09 07:53:05 PM PDT 24
Peak memory 219392 kb
Host smart-8ba13aee-2858-42b3-9540-0c0848ac7003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891755072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1891755072
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2751213568
Short name T926
Test name
Test status
Simulation time 41225542 ps
CPU time 1.5 seconds
Started Aug 09 07:53:00 PM PDT 24
Finished Aug 09 07:53:02 PM PDT 24
Peak memory 217328 kb
Host smart-c29fef39-c723-403b-8c85-6868d15dc1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751213568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2751213568
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3051261594
Short name T735
Test name
Test status
Simulation time 310038228 ps
CPU time 1.2 seconds
Started Aug 09 07:53:05 PM PDT 24
Finished Aug 09 07:53:06 PM PDT 24
Peak memory 217292 kb
Host smart-225c9a77-e383-4364-8464-d3c1179560aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051261594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3051261594
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.223743225
Short name T508
Test name
Test status
Simulation time 237048771 ps
CPU time 3.2 seconds
Started Aug 09 07:52:46 PM PDT 24
Finished Aug 09 07:52:49 PM PDT 24
Peak memory 218596 kb
Host smart-c800c07b-2eff-4604-b033-b689f8264c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223743225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.223743225
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3445668748
Short name T595
Test name
Test status
Simulation time 55249686 ps
CPU time 1.8 seconds
Started Aug 09 07:52:58 PM PDT 24
Finished Aug 09 07:53:00 PM PDT 24
Peak memory 220200 kb
Host smart-afb0f7c6-2ca1-469c-bffd-b8e8f765603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445668748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3445668748
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1932934433
Short name T72
Test name
Test status
Simulation time 37784688 ps
CPU time 1.29 seconds
Started Aug 09 07:53:05 PM PDT 24
Finished Aug 09 07:53:06 PM PDT 24
Peak memory 218832 kb
Host smart-552e042e-403d-4b6a-924c-35a4e6593d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932934433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1932934433
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2532346018
Short name T15
Test name
Test status
Simulation time 262395639 ps
CPU time 3.06 seconds
Started Aug 09 07:53:03 PM PDT 24
Finished Aug 09 07:53:07 PM PDT 24
Peak memory 220348 kb
Host smart-d6dc534c-04b6-4e53-87ac-169ecf06a3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532346018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2532346018
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1977802130
Short name T848
Test name
Test status
Simulation time 73110865 ps
CPU time 1.18 seconds
Started Aug 09 07:51:26 PM PDT 24
Finished Aug 09 07:51:28 PM PDT 24
Peak memory 219516 kb
Host smart-30184b39-3d23-42cb-b73d-07265362efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977802130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1977802130
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3684286598
Short name T882
Test name
Test status
Simulation time 18143070 ps
CPU time 0.96 seconds
Started Aug 09 07:51:24 PM PDT 24
Finished Aug 09 07:51:25 PM PDT 24
Peak memory 215168 kb
Host smart-b30380be-e87d-46c9-82b3-86a47292a926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684286598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3684286598
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1191229964
Short name T672
Test name
Test status
Simulation time 12782374 ps
CPU time 0.95 seconds
Started Aug 09 07:51:23 PM PDT 24
Finished Aug 09 07:51:24 PM PDT 24
Peak memory 216644 kb
Host smart-ab1cebf1-a56d-44fa-9dd4-7cf0389b3e1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191229964 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1191229964
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3872658228
Short name T439
Test name
Test status
Simulation time 108672159 ps
CPU time 1.09 seconds
Started Aug 09 07:51:18 PM PDT 24
Finished Aug 09 07:51:20 PM PDT 24
Peak memory 218304 kb
Host smart-98bd3970-f04a-4718-bf4e-dabfe54247ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872658228 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3872658228
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.422421883
Short name T410
Test name
Test status
Simulation time 22986807 ps
CPU time 0.97 seconds
Started Aug 09 07:51:34 PM PDT 24
Finished Aug 09 07:51:35 PM PDT 24
Peak memory 218948 kb
Host smart-526b8a47-0d5c-4d3c-b1b2-1d543df9a846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422421883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.422421883
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1590744398
Short name T363
Test name
Test status
Simulation time 93906802 ps
CPU time 1.08 seconds
Started Aug 09 07:51:30 PM PDT 24
Finished Aug 09 07:51:32 PM PDT 24
Peak memory 217336 kb
Host smart-9d3759ec-0361-4415-88ec-381902a42810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590744398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1590744398
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2887996726
Short name T115
Test name
Test status
Simulation time 33507916 ps
CPU time 0.93 seconds
Started Aug 09 07:51:32 PM PDT 24
Finished Aug 09 07:51:33 PM PDT 24
Peak memory 216012 kb
Host smart-fc770389-94dc-43cc-adf8-cf88ba0eb3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887996726 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2887996726
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.913083599
Short name T918
Test name
Test status
Simulation time 46627825 ps
CPU time 0.97 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:43 PM PDT 24
Peak memory 215284 kb
Host smart-8a13d174-a111-432a-835e-bfd4464a73ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913083599 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.913083599
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2099095430
Short name T386
Test name
Test status
Simulation time 47552520 ps
CPU time 1.55 seconds
Started Aug 09 07:51:22 PM PDT 24
Finished Aug 09 07:51:23 PM PDT 24
Peak memory 217244 kb
Host smart-a68428ae-9311-470c-95f2-148f3a1c2380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099095430 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2099095430
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.324345149
Short name T645
Test name
Test status
Simulation time 68042291835 ps
CPU time 513.92 seconds
Started Aug 09 07:51:19 PM PDT 24
Finished Aug 09 07:59:53 PM PDT 24
Peak memory 218340 kb
Host smart-62fd2425-4716-4b90-b5e3-6b54133c3188
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324345149 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.324345149
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2422439378
Short name T324
Test name
Test status
Simulation time 169809286 ps
CPU time 1.24 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:46 PM PDT 24
Peak memory 217248 kb
Host smart-4a367507-250f-4d6c-82a3-bcb4674b3c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422439378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2422439378
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3750143699
Short name T834
Test name
Test status
Simulation time 46962924 ps
CPU time 1.48 seconds
Started Aug 09 07:52:46 PM PDT 24
Finished Aug 09 07:52:48 PM PDT 24
Peak memory 218704 kb
Host smart-1bca6281-4dcf-4eb3-b7fe-71ca427a41af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750143699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3750143699
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.4088244532
Short name T51
Test name
Test status
Simulation time 98358845 ps
CPU time 1.36 seconds
Started Aug 09 07:52:49 PM PDT 24
Finished Aug 09 07:52:51 PM PDT 24
Peak memory 218684 kb
Host smart-68fc5f6d-0858-4bf0-985c-8e0aed9999fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088244532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.4088244532
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.419982617
Short name T488
Test name
Test status
Simulation time 47054881 ps
CPU time 1.16 seconds
Started Aug 09 07:52:58 PM PDT 24
Finished Aug 09 07:53:00 PM PDT 24
Peak memory 219584 kb
Host smart-f67b62cc-9f9e-4542-acb5-dfb97560ed8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419982617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.419982617
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.4191433812
Short name T679
Test name
Test status
Simulation time 64279399 ps
CPU time 1.4 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 216120 kb
Host smart-52ed0bad-03dd-42c4-a858-0463d013d8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191433812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.4191433812
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1473504197
Short name T633
Test name
Test status
Simulation time 126317627 ps
CPU time 1.54 seconds
Started Aug 09 07:52:47 PM PDT 24
Finished Aug 09 07:52:49 PM PDT 24
Peak memory 218572 kb
Host smart-c4d0d89c-6167-420f-bd99-83829323a585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473504197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1473504197
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1471259654
Short name T589
Test name
Test status
Simulation time 232206259 ps
CPU time 3.07 seconds
Started Aug 09 07:52:57 PM PDT 24
Finished Aug 09 07:53:00 PM PDT 24
Peak memory 220196 kb
Host smart-073e43ca-4ad3-47d8-91a3-b15243047d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471259654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1471259654
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1121579074
Short name T460
Test name
Test status
Simulation time 111735590 ps
CPU time 1.27 seconds
Started Aug 09 07:52:47 PM PDT 24
Finished Aug 09 07:52:48 PM PDT 24
Peak memory 217436 kb
Host smart-e959f0a2-0936-4956-a5b5-ef0705b6b626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121579074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1121579074
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3606799756
Short name T542
Test name
Test status
Simulation time 42187632 ps
CPU time 1.57 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 220120 kb
Host smart-badc3af7-c753-4bee-988f-47c0ea7f4309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606799756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3606799756
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.993375450
Short name T635
Test name
Test status
Simulation time 81740735 ps
CPU time 1.12 seconds
Started Aug 09 07:52:56 PM PDT 24
Finished Aug 09 07:52:58 PM PDT 24
Peak memory 217368 kb
Host smart-041791cb-1b51-40ef-af84-ba68db14e20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993375450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.993375450
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2153822714
Short name T737
Test name
Test status
Simulation time 101140133 ps
CPU time 1.33 seconds
Started Aug 09 07:51:31 PM PDT 24
Finished Aug 09 07:51:32 PM PDT 24
Peak memory 215580 kb
Host smart-7d27e45d-2dcb-44a9-bdcc-da583258c609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153822714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2153822714
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3429226647
Short name T389
Test name
Test status
Simulation time 28878324 ps
CPU time 0.89 seconds
Started Aug 09 07:51:19 PM PDT 24
Finished Aug 09 07:51:20 PM PDT 24
Peak memory 215144 kb
Host smart-6eda56ed-c91d-4eed-bfc3-8835196cfb41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429226647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3429226647
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1941269448
Short name T967
Test name
Test status
Simulation time 134875659 ps
CPU time 1.13 seconds
Started Aug 09 07:51:21 PM PDT 24
Finished Aug 09 07:51:22 PM PDT 24
Peak memory 219536 kb
Host smart-dfc23de8-12cf-4b19-9371-d6011751d903
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941269448 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1941269448
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3459868554
Short name T689
Test name
Test status
Simulation time 23371766 ps
CPU time 1.05 seconds
Started Aug 09 07:51:32 PM PDT 24
Finished Aug 09 07:51:33 PM PDT 24
Peak memory 224092 kb
Host smart-3e3c3d30-e469-4ca7-8777-53e7dcef364c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459868554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3459868554
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2049663824
Short name T906
Test name
Test status
Simulation time 143892567 ps
CPU time 3.16 seconds
Started Aug 09 07:51:25 PM PDT 24
Finished Aug 09 07:51:28 PM PDT 24
Peak memory 218916 kb
Host smart-c780a093-31a5-481a-9a87-879cfa158735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049663824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2049663824
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.4198881977
Short name T34
Test name
Test status
Simulation time 21311165 ps
CPU time 1.08 seconds
Started Aug 09 07:51:20 PM PDT 24
Finished Aug 09 07:51:22 PM PDT 24
Peak memory 215964 kb
Host smart-73075ed3-3e8c-40db-864c-273fd81457b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198881977 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.4198881977
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.122444019
Short name T754
Test name
Test status
Simulation time 63428912 ps
CPU time 0.92 seconds
Started Aug 09 07:51:19 PM PDT 24
Finished Aug 09 07:51:20 PM PDT 24
Peak memory 215252 kb
Host smart-d7563b59-f1eb-4bfa-a1aa-4ad8cdb54959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122444019 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.122444019
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3915089640
Short name T447
Test name
Test status
Simulation time 691363555 ps
CPU time 4.31 seconds
Started Aug 09 07:51:32 PM PDT 24
Finished Aug 09 07:51:36 PM PDT 24
Peak memory 215372 kb
Host smart-d92f66af-e4bc-4962-a696-cd96d94fe1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915089640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3915089640
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.4155910032
Short name T245
Test name
Test status
Simulation time 33098150119 ps
CPU time 712.95 seconds
Started Aug 09 07:51:36 PM PDT 24
Finished Aug 09 08:03:30 PM PDT 24
Peak memory 223572 kb
Host smart-ffd12043-1ebc-469d-b06c-b77a61d5d1a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155910032 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.4155910032
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2338306195
Short name T421
Test name
Test status
Simulation time 46418936 ps
CPU time 1.47 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 215264 kb
Host smart-7ab0a2de-2866-419c-8dc4-251c675851a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338306195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2338306195
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2134423162
Short name T257
Test name
Test status
Simulation time 111086801 ps
CPU time 1.27 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 218696 kb
Host smart-dfe1f9f5-4f60-4641-a498-9c2c70528daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134423162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2134423162
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.287574278
Short name T919
Test name
Test status
Simulation time 76401458 ps
CPU time 1.07 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 217540 kb
Host smart-62ccd8c7-4c4d-458b-a45e-d9325c99da92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287574278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.287574278
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2631728653
Short name T639
Test name
Test status
Simulation time 42128576 ps
CPU time 1.09 seconds
Started Aug 09 07:52:48 PM PDT 24
Finished Aug 09 07:52:49 PM PDT 24
Peak memory 217308 kb
Host smart-875c026c-e4fd-4ec2-a87c-9d02d5399287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631728653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2631728653
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1326175059
Short name T793
Test name
Test status
Simulation time 265359693 ps
CPU time 3.04 seconds
Started Aug 09 07:52:46 PM PDT 24
Finished Aug 09 07:52:50 PM PDT 24
Peak memory 219232 kb
Host smart-f5851902-c825-41ac-98ef-9c967503367b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326175059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1326175059
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3373207683
Short name T881
Test name
Test status
Simulation time 39470809 ps
CPU time 1.64 seconds
Started Aug 09 07:52:48 PM PDT 24
Finished Aug 09 07:52:49 PM PDT 24
Peak memory 220272 kb
Host smart-a0dc04fd-2ff6-4595-9ced-fdf41b76d011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373207683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3373207683
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.205201437
Short name T957
Test name
Test status
Simulation time 142274441 ps
CPU time 2.74 seconds
Started Aug 09 07:53:05 PM PDT 24
Finished Aug 09 07:53:08 PM PDT 24
Peak memory 219576 kb
Host smart-ee9cd5e2-d86f-4304-b35c-851ee7058866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205201437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.205201437
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1946134091
Short name T847
Test name
Test status
Simulation time 46863206 ps
CPU time 1.73 seconds
Started Aug 09 07:52:59 PM PDT 24
Finished Aug 09 07:53:00 PM PDT 24
Peak memory 218696 kb
Host smart-33d7448f-bf86-4496-877a-5a4ac55b1a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946134091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1946134091
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1324513970
Short name T820
Test name
Test status
Simulation time 35680528 ps
CPU time 1.35 seconds
Started Aug 09 07:52:53 PM PDT 24
Finished Aug 09 07:52:54 PM PDT 24
Peak memory 218588 kb
Host smart-fb519807-39fe-4793-bef3-f4aaa6d9c48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324513970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1324513970
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3473727868
Short name T572
Test name
Test status
Simulation time 68940243 ps
CPU time 1.14 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 218756 kb
Host smart-efddce9e-4267-4611-bf1b-6df8294137cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473727868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3473727868
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.665830766
Short name T323
Test name
Test status
Simulation time 26123157 ps
CPU time 1.16 seconds
Started Aug 09 07:51:20 PM PDT 24
Finished Aug 09 07:51:21 PM PDT 24
Peak memory 218488 kb
Host smart-39a27d7b-aa08-4b9c-bb33-9077272776c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665830766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.665830766
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1155517643
Short name T698
Test name
Test status
Simulation time 14684752 ps
CPU time 0.92 seconds
Started Aug 09 07:51:23 PM PDT 24
Finished Aug 09 07:51:24 PM PDT 24
Peak memory 206804 kb
Host smart-1c8291b4-b226-4176-8307-e8f2c9f73f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155517643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1155517643
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1677352533
Short name T228
Test name
Test status
Simulation time 34681953 ps
CPU time 0.87 seconds
Started Aug 09 07:51:20 PM PDT 24
Finished Aug 09 07:51:21 PM PDT 24
Peak memory 216584 kb
Host smart-11a3fa61-47cb-4fe3-aa2b-e9f8ac13cdb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677352533 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1677352533
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.1009341918
Short name T819
Test name
Test status
Simulation time 18441614 ps
CPU time 1.09 seconds
Started Aug 09 07:51:40 PM PDT 24
Finished Aug 09 07:51:42 PM PDT 24
Peak memory 224156 kb
Host smart-1c466a1c-10ab-42aa-952f-3d013d2aaf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009341918 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1009341918
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3453257165
Short name T995
Test name
Test status
Simulation time 217392363 ps
CPU time 1.33 seconds
Started Aug 09 07:51:45 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 220460 kb
Host smart-e8f0faae-4329-4463-9ece-013fd33cb480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453257165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3453257165
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.370170837
Short name T652
Test name
Test status
Simulation time 25589147 ps
CPU time 0.95 seconds
Started Aug 09 07:51:33 PM PDT 24
Finished Aug 09 07:51:34 PM PDT 24
Peak memory 215480 kb
Host smart-81852ff7-0089-4b76-9837-e38cf0e8fcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370170837 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.370170837
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.738057218
Short name T360
Test name
Test status
Simulation time 32098507 ps
CPU time 0.99 seconds
Started Aug 09 07:51:21 PM PDT 24
Finished Aug 09 07:51:22 PM PDT 24
Peak memory 215268 kb
Host smart-f0c1f2e0-06d5-41ec-b5cf-78346c94d38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738057218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.738057218
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3972075885
Short name T402
Test name
Test status
Simulation time 713856469 ps
CPU time 2.4 seconds
Started Aug 09 07:51:37 PM PDT 24
Finished Aug 09 07:51:40 PM PDT 24
Peak memory 217460 kb
Host smart-3b78b08b-67c2-48ed-b1e5-df0e10de61cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972075885 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3972075885
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.289562352
Short name T895
Test name
Test status
Simulation time 20414221271 ps
CPU time 444.92 seconds
Started Aug 09 07:51:39 PM PDT 24
Finished Aug 09 07:59:04 PM PDT 24
Peak memory 223480 kb
Host smart-ab979569-bc93-46d8-89b1-57676a4b1978
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289562352 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.289562352
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1311830850
Short name T82
Test name
Test status
Simulation time 63972790 ps
CPU time 1.49 seconds
Started Aug 09 07:52:56 PM PDT 24
Finished Aug 09 07:52:57 PM PDT 24
Peak memory 218768 kb
Host smart-1d685edc-3fdb-4850-96cc-f009e8bed07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311830850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1311830850
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.816448767
Short name T872
Test name
Test status
Simulation time 91505643 ps
CPU time 2.15 seconds
Started Aug 09 07:52:57 PM PDT 24
Finished Aug 09 07:52:59 PM PDT 24
Peak memory 218976 kb
Host smart-7a2dc89c-c0ce-499f-b258-28721dd5bb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816448767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.816448767
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2489124968
Short name T861
Test name
Test status
Simulation time 67463521 ps
CPU time 1.19 seconds
Started Aug 09 07:52:52 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 217520 kb
Host smart-cb044edb-2dd9-4b83-8206-cfe5abe3ba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489124968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2489124968
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1519792142
Short name T54
Test name
Test status
Simulation time 305696208 ps
CPU time 1.69 seconds
Started Aug 09 07:52:56 PM PDT 24
Finished Aug 09 07:52:58 PM PDT 24
Peak memory 218696 kb
Host smart-ecc257bd-c39c-4357-b167-ee4f8d2a6242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519792142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1519792142
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.908126603
Short name T516
Test name
Test status
Simulation time 45609733 ps
CPU time 1.31 seconds
Started Aug 09 07:53:05 PM PDT 24
Finished Aug 09 07:53:07 PM PDT 24
Peak memory 219824 kb
Host smart-2a3ab765-607d-4ec0-b173-0d2a796423df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908126603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.908126603
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3567475713
Short name T77
Test name
Test status
Simulation time 45194093 ps
CPU time 1.61 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 220104 kb
Host smart-10eb4f6b-012a-456f-a91e-069c5c916fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567475713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3567475713
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.4112044814
Short name T638
Test name
Test status
Simulation time 83252382 ps
CPU time 1.14 seconds
Started Aug 09 07:52:50 PM PDT 24
Finished Aug 09 07:52:51 PM PDT 24
Peak memory 215316 kb
Host smart-7f758985-995d-4eaf-b620-4312971de8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112044814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.4112044814
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2031908306
Short name T462
Test name
Test status
Simulation time 114254608 ps
CPU time 1.52 seconds
Started Aug 09 07:52:56 PM PDT 24
Finished Aug 09 07:52:57 PM PDT 24
Peak memory 220008 kb
Host smart-e924a6cd-db58-4217-9440-14f836dee9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031908306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2031908306
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1045679061
Short name T922
Test name
Test status
Simulation time 102926561 ps
CPU time 1.12 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 217328 kb
Host smart-6de08e9e-2460-4d63-a19a-c19545ea7111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045679061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1045679061
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3157774476
Short name T511
Test name
Test status
Simulation time 89911459 ps
CPU time 1.24 seconds
Started Aug 09 07:52:50 PM PDT 24
Finished Aug 09 07:52:52 PM PDT 24
Peak memory 218860 kb
Host smart-76e0f960-e5fd-4be3-91e1-47a6b44820d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157774476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3157774476
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.988166691
Short name T70
Test name
Test status
Simulation time 39169407 ps
CPU time 1.05 seconds
Started Aug 09 07:51:31 PM PDT 24
Finished Aug 09 07:51:33 PM PDT 24
Peak memory 218548 kb
Host smart-862cb87c-8381-4637-8bff-3bf3eabf884c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988166691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.988166691
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3967136840
Short name T400
Test name
Test status
Simulation time 21729609 ps
CPU time 0.85 seconds
Started Aug 09 07:51:14 PM PDT 24
Finished Aug 09 07:51:15 PM PDT 24
Peak memory 206828 kb
Host smart-dc8833e2-4fa2-4049-9cc1-0b780cc16cf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967136840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3967136840
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3809603608
Short name T367
Test name
Test status
Simulation time 23958322 ps
CPU time 0.9 seconds
Started Aug 09 07:51:23 PM PDT 24
Finished Aug 09 07:51:24 PM PDT 24
Peak memory 216592 kb
Host smart-8b1b7a86-439f-4053-8e00-60292ebbaf88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809603608 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3809603608
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2492646239
Short name T351
Test name
Test status
Simulation time 42889391 ps
CPU time 1.31 seconds
Started Aug 09 07:51:22 PM PDT 24
Finished Aug 09 07:51:24 PM PDT 24
Peak memory 217124 kb
Host smart-fc2bda7c-ef6d-47d7-bd4c-808ad6c285a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492646239 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2492646239
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_genbits.4094034104
Short name T749
Test name
Test status
Simulation time 35283201 ps
CPU time 1.08 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 219904 kb
Host smart-5e7f5c63-07a0-4f2f-b86d-c5c6b22d1005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094034104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.4094034104
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_smoke.2727574294
Short name T452
Test name
Test status
Simulation time 53449980 ps
CPU time 0.92 seconds
Started Aug 09 07:51:23 PM PDT 24
Finished Aug 09 07:51:29 PM PDT 24
Peak memory 215288 kb
Host smart-8c2f5a92-a1fb-4794-98dd-a8dd2318e988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727574294 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2727574294
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2932501971
Short name T559
Test name
Test status
Simulation time 138741909 ps
CPU time 3.19 seconds
Started Aug 09 07:51:38 PM PDT 24
Finished Aug 09 07:51:42 PM PDT 24
Peak memory 217092 kb
Host smart-8a7902ce-0628-491c-b4a8-dbc583d37e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932501971 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2932501971
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1933038244
Short name T427
Test name
Test status
Simulation time 28418457698 ps
CPU time 344.58 seconds
Started Aug 09 07:51:30 PM PDT 24
Finished Aug 09 07:57:15 PM PDT 24
Peak memory 218264 kb
Host smart-cdd1e4f3-6ecf-490c-b4b8-b737a890ed7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933038244 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1933038244
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3661950634
Short name T108
Test name
Test status
Simulation time 172061273 ps
CPU time 2.07 seconds
Started Aug 09 07:53:00 PM PDT 24
Finished Aug 09 07:53:02 PM PDT 24
Peak memory 219884 kb
Host smart-9addd67d-dff5-4614-a179-e9e8f32b1ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661950634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3661950634
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2828323060
Short name T480
Test name
Test status
Simulation time 54119126 ps
CPU time 2.19 seconds
Started Aug 09 07:52:57 PM PDT 24
Finished Aug 09 07:53:00 PM PDT 24
Peak memory 218836 kb
Host smart-5a28f351-6ad3-4743-8566-8c2866be6a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828323060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2828323060
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2842519415
Short name T665
Test name
Test status
Simulation time 37697197 ps
CPU time 1.37 seconds
Started Aug 09 07:52:46 PM PDT 24
Finished Aug 09 07:52:48 PM PDT 24
Peak memory 219776 kb
Host smart-5e5f341a-35a8-4212-a430-befa6a5c201b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842519415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2842519415
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.585136114
Short name T804
Test name
Test status
Simulation time 79624042 ps
CPU time 1.52 seconds
Started Aug 09 07:52:45 PM PDT 24
Finished Aug 09 07:52:47 PM PDT 24
Peak memory 215288 kb
Host smart-2ca3d0da-3d9d-45b1-8338-dbf3d1104291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585136114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.585136114
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.621452013
Short name T594
Test name
Test status
Simulation time 54479399 ps
CPU time 1.92 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 220220 kb
Host smart-e7fe56cb-a953-4955-9f6f-755e96b42987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621452013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.621452013
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.796806142
Short name T626
Test name
Test status
Simulation time 52947446 ps
CPU time 2.18 seconds
Started Aug 09 07:53:01 PM PDT 24
Finished Aug 09 07:53:04 PM PDT 24
Peak memory 217872 kb
Host smart-5b3f9070-2086-44a6-afb3-07d837a4cda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796806142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.796806142
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3691895098
Short name T81
Test name
Test status
Simulation time 61094035 ps
CPU time 1.27 seconds
Started Aug 09 07:52:49 PM PDT 24
Finished Aug 09 07:52:50 PM PDT 24
Peak memory 218848 kb
Host smart-315c9875-2bec-4ee5-973f-1fd8d929d6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691895098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3691895098
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2492896438
Short name T630
Test name
Test status
Simulation time 239014339 ps
CPU time 3.47 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:55 PM PDT 24
Peak memory 218596 kb
Host smart-b5ae945d-c625-4b34-b405-206521077d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492896438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2492896438
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1002394785
Short name T982
Test name
Test status
Simulation time 35735014 ps
CPU time 1.35 seconds
Started Aug 09 07:52:56 PM PDT 24
Finished Aug 09 07:52:58 PM PDT 24
Peak memory 220012 kb
Host smart-21272769-313a-44ab-bb6e-c0a5de168df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002394785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1002394785
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3777649807
Short name T862
Test name
Test status
Simulation time 94839020 ps
CPU time 1.03 seconds
Started Aug 09 07:53:01 PM PDT 24
Finished Aug 09 07:53:02 PM PDT 24
Peak memory 217324 kb
Host smart-bdbfbff8-6280-4985-a925-cd5e4975079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777649807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3777649807
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1555331963
Short name T953
Test name
Test status
Simulation time 81286828 ps
CPU time 1.13 seconds
Started Aug 09 07:51:23 PM PDT 24
Finished Aug 09 07:51:24 PM PDT 24
Peak memory 219668 kb
Host smart-6bfa4990-8f81-4f03-9266-8be6e6f6446e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555331963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1555331963
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1717768762
Short name T355
Test name
Test status
Simulation time 22221512 ps
CPU time 0.89 seconds
Started Aug 09 07:51:24 PM PDT 24
Finished Aug 09 07:51:25 PM PDT 24
Peak memory 215168 kb
Host smart-8ecf6c47-48ad-42f4-93f0-543768677301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717768762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1717768762
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.459485273
Short name T640
Test name
Test status
Simulation time 14949055 ps
CPU time 0.89 seconds
Started Aug 09 07:51:38 PM PDT 24
Finished Aug 09 07:51:39 PM PDT 24
Peak memory 216528 kb
Host smart-1536ce6c-ca4c-4681-8cde-e645eadd79b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459485273 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.459485273
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.91676961
Short name T535
Test name
Test status
Simulation time 49775025 ps
CPU time 1.09 seconds
Started Aug 09 07:51:24 PM PDT 24
Finished Aug 09 07:51:25 PM PDT 24
Peak memory 219700 kb
Host smart-f55f5fc2-e46d-4961-87b8-d761a48ba052
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91676961 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_dis
able_auto_req_mode.91676961
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2683734224
Short name T423
Test name
Test status
Simulation time 32494336 ps
CPU time 0.88 seconds
Started Aug 09 07:51:20 PM PDT 24
Finished Aug 09 07:51:21 PM PDT 24
Peak memory 218744 kb
Host smart-ec435a9b-eaf5-44b3-83a6-991c618276d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683734224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2683734224
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.29375713
Short name T47
Test name
Test status
Simulation time 52170592 ps
CPU time 1.24 seconds
Started Aug 09 07:51:39 PM PDT 24
Finished Aug 09 07:51:40 PM PDT 24
Peak memory 217440 kb
Host smart-eae7de30-2ae4-4ca2-a4ea-6c3ae3638c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29375713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.29375713
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2036676626
Short name T763
Test name
Test status
Simulation time 26759450 ps
CPU time 0.98 seconds
Started Aug 09 07:51:24 PM PDT 24
Finished Aug 09 07:51:25 PM PDT 24
Peak memory 215560 kb
Host smart-9018bbc5-7aea-4d3a-80af-8e7172f5d07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036676626 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2036676626
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3575276003
Short name T579
Test name
Test status
Simulation time 21743904 ps
CPU time 0.95 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 215272 kb
Host smart-b07a510b-5dc3-4dd7-9254-3dafea1fd6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575276003 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3575276003
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3110715396
Short name T773
Test name
Test status
Simulation time 66512970 ps
CPU time 1.77 seconds
Started Aug 09 07:51:40 PM PDT 24
Finished Aug 09 07:51:42 PM PDT 24
Peak memory 215308 kb
Host smart-a666b978-3d47-4439-81d9-fcadf5fc5952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110715396 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3110715396
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1417861945
Short name T888
Test name
Test status
Simulation time 166321648191 ps
CPU time 959.93 seconds
Started Aug 09 07:51:21 PM PDT 24
Finished Aug 09 08:07:21 PM PDT 24
Peak memory 221156 kb
Host smart-5569ea88-5385-469d-94d5-8c0ab6d2b92c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417861945 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1417861945
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1395033262
Short name T883
Test name
Test status
Simulation time 48310946 ps
CPU time 1.86 seconds
Started Aug 09 07:53:04 PM PDT 24
Finished Aug 09 07:53:06 PM PDT 24
Peak memory 220236 kb
Host smart-d5b8dd82-cb20-405a-b98a-e6b9b8731476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395033262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1395033262
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.4253952499
Short name T687
Test name
Test status
Simulation time 72019554 ps
CPU time 1.09 seconds
Started Aug 09 07:53:04 PM PDT 24
Finished Aug 09 07:53:05 PM PDT 24
Peak memory 217372 kb
Host smart-931b6d69-a254-46f1-bacb-a89b63c6901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253952499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4253952499
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.187167510
Short name T365
Test name
Test status
Simulation time 42402222 ps
CPU time 1.13 seconds
Started Aug 09 07:53:08 PM PDT 24
Finished Aug 09 07:53:09 PM PDT 24
Peak memory 217464 kb
Host smart-d3edb525-7c84-4541-9e71-ff4357ef771a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187167510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.187167510
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.705250830
Short name T597
Test name
Test status
Simulation time 62940816 ps
CPU time 1.82 seconds
Started Aug 09 07:53:23 PM PDT 24
Finished Aug 09 07:53:25 PM PDT 24
Peak memory 218592 kb
Host smart-b967fd74-a817-4e42-8659-0b6bb2f89840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705250830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.705250830
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3421457572
Short name T391
Test name
Test status
Simulation time 54393423 ps
CPU time 1.67 seconds
Started Aug 09 07:53:05 PM PDT 24
Finished Aug 09 07:53:07 PM PDT 24
Peak memory 218520 kb
Host smart-b1ef9a28-afb2-4cfd-9e4a-1e37f20648f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421457572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3421457572
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.935672798
Short name T692
Test name
Test status
Simulation time 211749001 ps
CPU time 1.2 seconds
Started Aug 09 07:52:53 PM PDT 24
Finished Aug 09 07:52:55 PM PDT 24
Peak memory 217460 kb
Host smart-a39864a7-b2d3-4f81-ba1e-b36ba4f7dd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935672798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.935672798
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2560386709
Short name T719
Test name
Test status
Simulation time 101384373 ps
CPU time 1.15 seconds
Started Aug 09 07:52:52 PM PDT 24
Finished Aug 09 07:52:54 PM PDT 24
Peak memory 217212 kb
Host smart-b306d85e-6db2-4407-ac80-3c6b3a5d76ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560386709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2560386709
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3659958435
Short name T479
Test name
Test status
Simulation time 58659036 ps
CPU time 1.14 seconds
Started Aug 09 07:53:20 PM PDT 24
Finished Aug 09 07:53:21 PM PDT 24
Peak memory 219996 kb
Host smart-88e3ee6e-0c1f-467f-9b7c-c733bcd7452a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659958435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3659958435
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1071213034
Short name T529
Test name
Test status
Simulation time 76652133 ps
CPU time 1.18 seconds
Started Aug 09 07:52:53 PM PDT 24
Finished Aug 09 07:52:55 PM PDT 24
Peak memory 218516 kb
Host smart-4542a4db-a865-4ee2-88f6-7c3dd27716cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071213034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1071213034
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1239029384
Short name T382
Test name
Test status
Simulation time 32315791 ps
CPU time 1.45 seconds
Started Aug 09 07:52:57 PM PDT 24
Finished Aug 09 07:52:58 PM PDT 24
Peak memory 217388 kb
Host smart-36f9e96e-876a-4de7-b641-65132eadf3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239029384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1239029384
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3644263786
Short name T815
Test name
Test status
Simulation time 32166158 ps
CPU time 1.24 seconds
Started Aug 09 07:51:21 PM PDT 24
Finished Aug 09 07:51:22 PM PDT 24
Peak memory 220396 kb
Host smart-115c4f31-ef94-4347-86e8-985ae9d4cd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644263786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3644263786
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1667917364
Short name T727
Test name
Test status
Simulation time 13651514 ps
CPU time 0.95 seconds
Started Aug 09 07:51:31 PM PDT 24
Finished Aug 09 07:51:32 PM PDT 24
Peak memory 206808 kb
Host smart-b743da66-274c-4c6b-8fd4-b21138ea1240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667917364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1667917364
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3785125539
Short name T359
Test name
Test status
Simulation time 12318263 ps
CPU time 0.89 seconds
Started Aug 09 07:51:36 PM PDT 24
Finished Aug 09 07:51:37 PM PDT 24
Peak memory 216444 kb
Host smart-9471e73f-374d-4a5d-9764-573e64674aea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785125539 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3785125539
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.1639743338
Short name T677
Test name
Test status
Simulation time 42362698 ps
CPU time 0.94 seconds
Started Aug 09 07:51:38 PM PDT 24
Finished Aug 09 07:51:39 PM PDT 24
Peak memory 220104 kb
Host smart-360d49a3-f090-439d-9b4f-9b2c89bd04a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639743338 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1639743338
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.4098372100
Short name T885
Test name
Test status
Simulation time 31780833 ps
CPU time 1.35 seconds
Started Aug 09 07:51:34 PM PDT 24
Finished Aug 09 07:51:36 PM PDT 24
Peak memory 217284 kb
Host smart-dddcc5f3-ecc0-45a6-b14e-2b5a5d2c996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098372100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.4098372100
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1453259582
Short name T212
Test name
Test status
Simulation time 26826935 ps
CPU time 1.03 seconds
Started Aug 09 07:51:35 PM PDT 24
Finished Aug 09 07:51:36 PM PDT 24
Peak memory 215424 kb
Host smart-143d22a1-909e-4cf4-b584-965fa455a25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453259582 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1453259582
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1600309868
Short name T103
Test name
Test status
Simulation time 24801340 ps
CPU time 0.98 seconds
Started Aug 09 07:51:22 PM PDT 24
Finished Aug 09 07:51:23 PM PDT 24
Peak memory 215316 kb
Host smart-eccf2c90-7bfe-4ecc-a3a8-11e2855a9ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600309868 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1600309868
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.470433538
Short name T654
Test name
Test status
Simulation time 371309346 ps
CPU time 7.24 seconds
Started Aug 09 07:51:22 PM PDT 24
Finished Aug 09 07:51:29 PM PDT 24
Peak memory 215304 kb
Host smart-be6d55f0-cf91-49ed-8657-4109368c5098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470433538 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.470433538
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3204073040
Short name T239
Test name
Test status
Simulation time 52615712873 ps
CPU time 636.49 seconds
Started Aug 09 07:51:21 PM PDT 24
Finished Aug 09 08:01:58 PM PDT 24
Peak memory 223576 kb
Host smart-bfcb3e45-f3ab-4600-a3e1-6317e35d815d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204073040 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3204073040
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2242969156
Short name T394
Test name
Test status
Simulation time 59855817 ps
CPU time 1.05 seconds
Started Aug 09 07:52:56 PM PDT 24
Finished Aug 09 07:52:57 PM PDT 24
Peak memory 219868 kb
Host smart-141d8db2-cfa2-4927-bb5d-94974f14b386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242969156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2242969156
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3567355049
Short name T664
Test name
Test status
Simulation time 95244685 ps
CPU time 1.61 seconds
Started Aug 09 07:52:55 PM PDT 24
Finished Aug 09 07:52:57 PM PDT 24
Peak memory 219108 kb
Host smart-eeadbb2d-0ac7-484c-bf46-b2045a7d3a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567355049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3567355049
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.84733842
Short name T669
Test name
Test status
Simulation time 215837825 ps
CPU time 1.01 seconds
Started Aug 09 07:53:08 PM PDT 24
Finished Aug 09 07:53:09 PM PDT 24
Peak memory 217368 kb
Host smart-9d5fb7c1-cd21-4142-8c84-d4a3775b53de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84733842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.84733842
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.286973528
Short name T552
Test name
Test status
Simulation time 161026487 ps
CPU time 1.29 seconds
Started Aug 09 07:53:27 PM PDT 24
Finished Aug 09 07:53:29 PM PDT 24
Peak memory 217272 kb
Host smart-2e67de22-ce67-4d5b-b51a-23d68b802d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286973528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.286973528
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1822279774
Short name T912
Test name
Test status
Simulation time 148026881 ps
CPU time 1.12 seconds
Started Aug 09 07:53:05 PM PDT 24
Finished Aug 09 07:53:06 PM PDT 24
Peak memory 217304 kb
Host smart-0325487b-d8aa-470b-9dd0-a79ec3bc4131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822279774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1822279774
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2226365938
Short name T582
Test name
Test status
Simulation time 80661266 ps
CPU time 3.14 seconds
Started Aug 09 07:53:08 PM PDT 24
Finished Aug 09 07:53:11 PM PDT 24
Peak memory 217608 kb
Host smart-b4d6c5ae-465d-43bf-bf22-5ac1bc30587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226365938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2226365938
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.4288535797
Short name T675
Test name
Test status
Simulation time 75704525 ps
CPU time 0.98 seconds
Started Aug 09 07:53:09 PM PDT 24
Finished Aug 09 07:53:11 PM PDT 24
Peak memory 217296 kb
Host smart-d26b9246-58df-41b0-a939-a2c9dc0bb797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288535797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.4288535797
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.575697835
Short name T455
Test name
Test status
Simulation time 244417274 ps
CPU time 1.56 seconds
Started Aug 09 07:53:12 PM PDT 24
Finished Aug 09 07:53:14 PM PDT 24
Peak memory 218712 kb
Host smart-8e3824c9-1c92-4525-b0a9-1fcece3de72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575697835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.575697835
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2583576496
Short name T929
Test name
Test status
Simulation time 49443815 ps
CPU time 1.19 seconds
Started Aug 09 07:52:51 PM PDT 24
Finished Aug 09 07:52:53 PM PDT 24
Peak memory 217224 kb
Host smart-ed952efa-fa8b-4307-bb2d-3c324b4b67c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583576496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2583576496
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2584418820
Short name T965
Test name
Test status
Simulation time 84034756 ps
CPU time 3.11 seconds
Started Aug 09 07:52:56 PM PDT 24
Finished Aug 09 07:52:59 PM PDT 24
Peak memory 215324 kb
Host smart-fb0d9d02-be6a-4c6c-97d3-3629464e4146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584418820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2584418820
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3746187119
Short name T671
Test name
Test status
Simulation time 23267763 ps
CPU time 1.22 seconds
Started Aug 09 07:50:52 PM PDT 24
Finished Aug 09 07:50:53 PM PDT 24
Peak memory 219248 kb
Host smart-dfdd1b0a-ec2e-4dd8-aea5-6c5315c292e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746187119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3746187119
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3545310998
Short name T599
Test name
Test status
Simulation time 80411451 ps
CPU time 0.98 seconds
Started Aug 09 07:50:48 PM PDT 24
Finished Aug 09 07:50:50 PM PDT 24
Peak memory 206892 kb
Host smart-b97cce45-3056-4887-9d6b-831685622a31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545310998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3545310998
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.4088300292
Short name T553
Test name
Test status
Simulation time 11238598 ps
CPU time 0.92 seconds
Started Aug 09 07:50:50 PM PDT 24
Finished Aug 09 07:50:51 PM PDT 24
Peak memory 215376 kb
Host smart-85fb18a6-8d5b-432d-b234-09e211450158
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088300292 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.4088300292
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2284371289
Short name T962
Test name
Test status
Simulation time 35643941 ps
CPU time 1.01 seconds
Started Aug 09 07:50:52 PM PDT 24
Finished Aug 09 07:50:54 PM PDT 24
Peak memory 219316 kb
Host smart-a605cedf-ad76-49a8-8759-795a1aa428ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284371289 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2284371289
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2621056820
Short name T994
Test name
Test status
Simulation time 28309113 ps
CPU time 1.34 seconds
Started Aug 09 07:50:52 PM PDT 24
Finished Aug 09 07:50:54 PM PDT 24
Peak memory 217500 kb
Host smart-1e038c14-8a17-4626-81e4-4c84fe09b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621056820 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2621056820
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_intr.2378377786
Short name T217
Test name
Test status
Simulation time 22293107 ps
CPU time 1.07 seconds
Started Aug 09 07:50:49 PM PDT 24
Finished Aug 09 07:50:51 PM PDT 24
Peak memory 215520 kb
Host smart-761dcbcd-4e96-45bb-974e-659d772a8684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378377786 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2378377786
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.4291474641
Short name T989
Test name
Test status
Simulation time 44850451 ps
CPU time 0.87 seconds
Started Aug 09 07:50:50 PM PDT 24
Finished Aug 09 07:50:51 PM PDT 24
Peak memory 207164 kb
Host smart-8bb505d0-367d-419d-ae0e-df1e0b8ad047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291474641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4291474641
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.2972647495
Short name T987
Test name
Test status
Simulation time 126663173 ps
CPU time 0.93 seconds
Started Aug 09 07:50:41 PM PDT 24
Finished Aug 09 07:50:42 PM PDT 24
Peak memory 213940 kb
Host smart-79e85543-54df-4c24-b7ec-a03cd6036794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972647495 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2972647495
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.4196328497
Short name T651
Test name
Test status
Simulation time 723435761 ps
CPU time 4.47 seconds
Started Aug 09 07:50:51 PM PDT 24
Finished Aug 09 07:50:55 PM PDT 24
Peak memory 215312 kb
Host smart-626e49be-57cf-408d-85a6-be24033cf541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196328497 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.4196328497
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.761536737
Short name T44
Test name
Test status
Simulation time 22965730859 ps
CPU time 512.35 seconds
Started Aug 09 07:50:52 PM PDT 24
Finished Aug 09 07:59:24 PM PDT 24
Peak memory 217868 kb
Host smart-c6567afb-a027-4bad-9e8b-efff6740ab70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761536737 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.761536737
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2976729571
Short name T56
Test name
Test status
Simulation time 26686373 ps
CPU time 1.13 seconds
Started Aug 09 07:51:38 PM PDT 24
Finished Aug 09 07:51:40 PM PDT 24
Peak memory 219772 kb
Host smart-b7c417c1-a971-44d0-a4a2-85359f9cc629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976729571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2976729571
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.4070593801
Short name T908
Test name
Test status
Simulation time 40100371 ps
CPU time 0.94 seconds
Started Aug 09 07:51:52 PM PDT 24
Finished Aug 09 07:51:53 PM PDT 24
Peak memory 206820 kb
Host smart-4a82c7ba-5bf4-4f73-9389-038f713b1d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070593801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4070593801
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.93960280
Short name T202
Test name
Test status
Simulation time 13857667 ps
CPU time 0.89 seconds
Started Aug 09 07:51:31 PM PDT 24
Finished Aug 09 07:51:32 PM PDT 24
Peak memory 216664 kb
Host smart-0ca03a27-98e8-466c-b67a-36f7edec3b6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93960280 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.93960280
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1638036379
Short name T534
Test name
Test status
Simulation time 58806041 ps
CPU time 0.98 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 218412 kb
Host smart-94865029-8488-44e3-8d37-e07916664d52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638036379 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1638036379
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3090567409
Short name T831
Test name
Test status
Simulation time 24713778 ps
CPU time 1.07 seconds
Started Aug 09 07:51:37 PM PDT 24
Finished Aug 09 07:51:38 PM PDT 24
Peak memory 220204 kb
Host smart-cfe8ceb4-3c03-400d-9226-9b4f6006539b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090567409 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3090567409
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.4243409042
Short name T83
Test name
Test status
Simulation time 90752932 ps
CPU time 1.49 seconds
Started Aug 09 07:51:43 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 218712 kb
Host smart-1a3cc9f6-05cb-4af4-914c-d63b450d71c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243409042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.4243409042
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.923093313
Short name T37
Test name
Test status
Simulation time 25110937 ps
CPU time 0.95 seconds
Started Aug 09 07:51:41 PM PDT 24
Finished Aug 09 07:51:42 PM PDT 24
Peak memory 216060 kb
Host smart-a5421db4-2c60-4400-bced-906a00ced9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923093313 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.923093313
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.81361244
Short name T457
Test name
Test status
Simulation time 45482023 ps
CPU time 0.99 seconds
Started Aug 09 07:51:40 PM PDT 24
Finished Aug 09 07:51:41 PM PDT 24
Peak memory 207136 kb
Host smart-3f91918e-fef5-4f51-9016-fb870870f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81361244 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.81361244
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1977305539
Short name T833
Test name
Test status
Simulation time 1321964337 ps
CPU time 4.03 seconds
Started Aug 09 07:51:40 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 217160 kb
Host smart-2976f183-0171-42b7-a2b6-d4409c6d3007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977305539 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1977305539
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.524052303
Short name T984
Test name
Test status
Simulation time 513009737168 ps
CPU time 2239.97 seconds
Started Aug 09 07:51:34 PM PDT 24
Finished Aug 09 08:28:55 PM PDT 24
Peak memory 224360 kb
Host smart-51a7b82a-3f4f-4440-a212-44b1c2bc20eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524052303 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.524052303
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2380787770
Short name T369
Test name
Test status
Simulation time 90837560 ps
CPU time 1.22 seconds
Started Aug 09 07:51:41 PM PDT 24
Finished Aug 09 07:51:43 PM PDT 24
Peak memory 219644 kb
Host smart-fffdcb00-33ef-4c16-8e80-ae87f59480b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380787770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2380787770
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3058320978
Short name T955
Test name
Test status
Simulation time 31217839 ps
CPU time 0.94 seconds
Started Aug 09 07:51:41 PM PDT 24
Finished Aug 09 07:51:42 PM PDT 24
Peak memory 206788 kb
Host smart-6c035f56-03aa-4a05-8f40-bb584185ab24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058320978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3058320978
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2959272227
Short name T893
Test name
Test status
Simulation time 16937848 ps
CPU time 0.88 seconds
Started Aug 09 07:51:43 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 216472 kb
Host smart-470ff5b1-b09b-4369-b224-d2cd434ebb66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959272227 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2959272227
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.4242636630
Short name T910
Test name
Test status
Simulation time 36660877 ps
CPU time 1.23 seconds
Started Aug 09 07:51:39 PM PDT 24
Finished Aug 09 07:51:40 PM PDT 24
Peak memory 217184 kb
Host smart-544c4471-3d1c-47fa-abeb-a59c584eb7cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242636630 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.4242636630
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1572303950
Short name T711
Test name
Test status
Simulation time 72380713 ps
CPU time 1.19 seconds
Started Aug 09 07:51:37 PM PDT 24
Finished Aug 09 07:51:39 PM PDT 24
Peak memory 225936 kb
Host smart-29d0084e-469d-4366-8684-3f9221a36676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572303950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1572303950
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.450797612
Short name T916
Test name
Test status
Simulation time 42139968 ps
CPU time 1.21 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 218608 kb
Host smart-4db55c86-2ffe-4909-86f0-c50909290e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450797612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.450797612
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1185096495
Short name T681
Test name
Test status
Simulation time 27259867 ps
CPU time 0.97 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:47 PM PDT 24
Peak memory 215348 kb
Host smart-3ca9e278-dc14-4f8e-a74c-3f64a7da20f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185096495 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1185096495
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.881749271
Short name T826
Test name
Test status
Simulation time 21431195 ps
CPU time 0.87 seconds
Started Aug 09 07:51:49 PM PDT 24
Finished Aug 09 07:51:50 PM PDT 24
Peak memory 215276 kb
Host smart-fb528b93-d82c-4e5b-bfe4-4726c45110fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881749271 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.881749271
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1119338812
Short name T790
Test name
Test status
Simulation time 341529683 ps
CPU time 6.69 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:51 PM PDT 24
Peak memory 215316 kb
Host smart-69ea8e0e-d56f-45b5-b8ba-c700902cde49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119338812 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1119338812
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3534631023
Short name T238
Test name
Test status
Simulation time 7667314214 ps
CPU time 176.33 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:54:43 PM PDT 24
Peak memory 218256 kb
Host smart-82c6b262-c0b1-4978-9732-75d2bbf238f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534631023 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3534631023
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.18203102
Short name T656
Test name
Test status
Simulation time 66520458 ps
CPU time 1.16 seconds
Started Aug 09 07:51:39 PM PDT 24
Finished Aug 09 07:51:40 PM PDT 24
Peak memory 219724 kb
Host smart-d50004e9-b1c4-4cde-bc83-65c14a66dbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18203102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.18203102
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.643946779
Short name T795
Test name
Test status
Simulation time 43869716 ps
CPU time 0.9 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 206816 kb
Host smart-d6ad4f01-1d99-4b0e-8cce-96b0ca5dc289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643946779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.643946779
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3203474733
Short name T194
Test name
Test status
Simulation time 21574387 ps
CPU time 0.95 seconds
Started Aug 09 07:51:43 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 216460 kb
Host smart-19785cc1-46d5-42de-bb0f-89afb8f67669
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203474733 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3203474733
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3941929761
Short name T449
Test name
Test status
Simulation time 128964112 ps
CPU time 1.23 seconds
Started Aug 09 07:51:47 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 217328 kb
Host smart-497514de-bcab-4b93-8111-b74247f026dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941929761 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3941929761
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2545814171
Short name T823
Test name
Test status
Simulation time 21325644 ps
CPU time 1.09 seconds
Started Aug 09 07:51:33 PM PDT 24
Finished Aug 09 07:51:34 PM PDT 24
Peak memory 220044 kb
Host smart-c8320a34-de6e-4aa9-83ea-8f969840cd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545814171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2545814171
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.24539162
Short name T120
Test name
Test status
Simulation time 50121046 ps
CPU time 1.36 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 218468 kb
Host smart-282e6406-3e8c-49da-86a8-cff085c20bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24539162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.24539162
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2716094749
Short name T557
Test name
Test status
Simulation time 23823805 ps
CPU time 1.02 seconds
Started Aug 09 07:51:36 PM PDT 24
Finished Aug 09 07:51:38 PM PDT 24
Peak memory 215500 kb
Host smart-571b7335-9524-41b5-83de-c09495e6bdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716094749 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2716094749
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.558005415
Short name T482
Test name
Test status
Simulation time 22522303 ps
CPU time 0.92 seconds
Started Aug 09 07:51:47 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 215312 kb
Host smart-7d8263ae-01e0-44a1-8ad9-60e2602a9bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558005415 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.558005415
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2530090451
Short name T288
Test name
Test status
Simulation time 41491428 ps
CPU time 1.36 seconds
Started Aug 09 07:51:38 PM PDT 24
Finished Aug 09 07:51:40 PM PDT 24
Peak memory 207128 kb
Host smart-4f89a2cd-f40a-4bdd-8fd2-5d3b7ae5c195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530090451 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2530090451
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2898812043
Short name T517
Test name
Test status
Simulation time 212074883752 ps
CPU time 1890.13 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 08:23:15 PM PDT 24
Peak memory 227584 kb
Host smart-860519b9-8957-4582-bf05-24908fbb0d74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898812043 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2898812043
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1063045894
Short name T726
Test name
Test status
Simulation time 26564758 ps
CPU time 1.22 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 219488 kb
Host smart-45f0f45e-135a-4927-b9b7-0c4c1d614881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063045894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1063045894
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.4139032032
Short name T739
Test name
Test status
Simulation time 39407305 ps
CPU time 0.83 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:43 PM PDT 24
Peak memory 206608 kb
Host smart-c0bc7c58-cbef-41d9-a573-4df23b5a9aec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139032032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.4139032032
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2912063470
Short name T855
Test name
Test status
Simulation time 89781512 ps
CPU time 1.37 seconds
Started Aug 09 07:51:52 PM PDT 24
Finished Aug 09 07:51:53 PM PDT 24
Peak memory 218276 kb
Host smart-ed3e4b55-f31d-4575-b980-424921481aeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912063470 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2912063470
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.457885294
Short name T868
Test name
Test status
Simulation time 20310077 ps
CPU time 1.05 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 218952 kb
Host smart-a591daee-1829-4c0b-922c-a4a48d455396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457885294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.457885294
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.4049322831
Short name T832
Test name
Test status
Simulation time 29745071 ps
CPU time 1.39 seconds
Started Aug 09 07:51:39 PM PDT 24
Finished Aug 09 07:51:40 PM PDT 24
Peak memory 217200 kb
Host smart-5f71c0c4-b8fa-4170-ba81-cd879e288306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049322831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4049322831
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.636958708
Short name T836
Test name
Test status
Simulation time 68602690 ps
CPU time 0.84 seconds
Started Aug 09 07:51:40 PM PDT 24
Finished Aug 09 07:51:40 PM PDT 24
Peak memory 215452 kb
Host smart-7eda2823-559b-4d2f-a938-df715b098946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636958708 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.636958708
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.245131082
Short name T522
Test name
Test status
Simulation time 48328104 ps
CPU time 0.94 seconds
Started Aug 09 07:51:49 PM PDT 24
Finished Aug 09 07:51:50 PM PDT 24
Peak memory 215332 kb
Host smart-0d7a9c80-906d-47cc-a751-4a1f5074ca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245131082 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.245131082
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.427222898
Short name T707
Test name
Test status
Simulation time 1395367083 ps
CPU time 3.73 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 217236 kb
Host smart-61ac8659-808c-406d-9e9a-a132a7fc074d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427222898 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.427222898
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2606654946
Short name T904
Test name
Test status
Simulation time 120535986715 ps
CPU time 655.24 seconds
Started Aug 09 07:51:43 PM PDT 24
Finished Aug 09 08:02:38 PM PDT 24
Peak memory 220876 kb
Host smart-fbe73005-8ed8-449d-a325-c486eaa5d896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606654946 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2606654946
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.981481095
Short name T467
Test name
Test status
Simulation time 89437847 ps
CPU time 1.22 seconds
Started Aug 09 07:51:41 PM PDT 24
Finished Aug 09 07:51:43 PM PDT 24
Peak memory 218400 kb
Host smart-460909a8-b8c9-4a13-96f7-c17a0ca72299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981481095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.981481095
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.305557946
Short name T704
Test name
Test status
Simulation time 199998552 ps
CPU time 0.85 seconds
Started Aug 09 07:51:40 PM PDT 24
Finished Aug 09 07:51:41 PM PDT 24
Peak memory 214948 kb
Host smart-6a6ab011-810d-409e-9093-cd48315233b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305557946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.305557946
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_err.1874642091
Short name T63
Test name
Test status
Simulation time 34781048 ps
CPU time 1.05 seconds
Started Aug 09 07:51:28 PM PDT 24
Finished Aug 09 07:51:30 PM PDT 24
Peak memory 224120 kb
Host smart-69fcc67a-b235-4e8b-9c30-8883f79d8657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874642091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1874642091
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.346034397
Short name T342
Test name
Test status
Simulation time 24728257 ps
CPU time 1.18 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:47 PM PDT 24
Peak memory 218824 kb
Host smart-f488a606-5cd9-4cb6-bf6a-f745b2a6a7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346034397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.346034397
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2628768358
Short name T113
Test name
Test status
Simulation time 34035027 ps
CPU time 0.91 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 215964 kb
Host smart-a57693f4-cba0-4756-a6c7-bd17635a2d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628768358 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2628768358
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1079664237
Short name T65
Test name
Test status
Simulation time 48351599 ps
CPU time 0.97 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 215320 kb
Host smart-8d60ae1e-3470-456e-8330-c8ad830c89b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079664237 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1079664237
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.700981000
Short name T973
Test name
Test status
Simulation time 150096841 ps
CPU time 1.35 seconds
Started Aug 09 07:51:40 PM PDT 24
Finished Aug 09 07:51:42 PM PDT 24
Peak memory 215268 kb
Host smart-4dbea6f3-7b7c-46ae-93e9-8caf8da03750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700981000 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.700981000
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1687561632
Short name T124
Test name
Test status
Simulation time 314292761664 ps
CPU time 1039.15 seconds
Started Aug 09 07:51:38 PM PDT 24
Finished Aug 09 08:08:58 PM PDT 24
Peak memory 223196 kb
Host smart-ef305e26-bed8-4f00-9f40-85424600e5b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687561632 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1687561632
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3312027148
Short name T152
Test name
Test status
Simulation time 42652714 ps
CPU time 1.22 seconds
Started Aug 09 07:51:47 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 219096 kb
Host smart-122741eb-dbe9-4b36-9892-ebfaf01b4705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312027148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3312027148
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1697478761
Short name T486
Test name
Test status
Simulation time 61625603 ps
CPU time 0.82 seconds
Started Aug 09 07:51:45 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 206748 kb
Host smart-0c68fd33-77c5-4646-86cf-b61d60afeee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697478761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1697478761
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2266407052
Short name T942
Test name
Test status
Simulation time 23129032 ps
CPU time 0.9 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:43 PM PDT 24
Peak memory 219444 kb
Host smart-25ad1931-2380-48cf-bd1c-5f6ea919255b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266407052 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2266407052
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2600166532
Short name T512
Test name
Test status
Simulation time 287503573 ps
CPU time 1.05 seconds
Started Aug 09 07:51:47 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 218440 kb
Host smart-c4ec9f0d-12ff-4c38-bda2-bd06dd8764d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600166532 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2600166532
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1224793999
Short name T7
Test name
Test status
Simulation time 65418798 ps
CPU time 1.07 seconds
Started Aug 09 07:51:53 PM PDT 24
Finished Aug 09 07:51:54 PM PDT 24
Peak memory 224164 kb
Host smart-b03bcb09-53f5-4b28-8ab5-f426429178b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224793999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1224793999
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.4052719343
Short name T473
Test name
Test status
Simulation time 31704850 ps
CPU time 1.24 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:43 PM PDT 24
Peak memory 218576 kb
Host smart-10cbe06d-0e4d-439a-97d7-7addd83764cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052719343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.4052719343
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2306974309
Short name T41
Test name
Test status
Simulation time 24424187 ps
CPU time 0.94 seconds
Started Aug 09 07:51:50 PM PDT 24
Finished Aug 09 07:51:52 PM PDT 24
Peak memory 216120 kb
Host smart-40859f39-64b0-44a8-ab84-196f5cea848c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306974309 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2306974309
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1294409182
Short name T811
Test name
Test status
Simulation time 28574750 ps
CPU time 0.98 seconds
Started Aug 09 07:51:43 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 215288 kb
Host smart-19f78722-2474-48c3-b1b6-1ab209b7fa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294409182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1294409182
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3481654082
Short name T889
Test name
Test status
Simulation time 73784947 ps
CPU time 1.2 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 215280 kb
Host smart-a888f35e-1640-4f50-8c0a-ac19a16aae67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481654082 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3481654082
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_alert.436326526
Short name T166
Test name
Test status
Simulation time 30560108 ps
CPU time 1.31 seconds
Started Aug 09 07:51:51 PM PDT 24
Finished Aug 09 07:51:53 PM PDT 24
Peak memory 218592 kb
Host smart-862fa1a6-af52-42f4-9a6d-6f13c9334ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436326526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.436326526
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2417899944
Short name T477
Test name
Test status
Simulation time 28370018 ps
CPU time 0.91 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:43 PM PDT 24
Peak memory 206848 kb
Host smart-d66e5edb-3618-4282-9ba0-f278aa499812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417899944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2417899944
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2938126370
Short name T963
Test name
Test status
Simulation time 20983980 ps
CPU time 0.88 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:47 PM PDT 24
Peak memory 216456 kb
Host smart-3e6a255d-f7ab-4c4e-880e-58b1a2333e8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938126370 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2938126370
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1505104802
Short name T143
Test name
Test status
Simulation time 34923916 ps
CPU time 1.23 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 216996 kb
Host smart-cb5b852d-6c16-4dbc-a010-1b9d8354c272
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505104802 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1505104802
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1990884097
Short name T411
Test name
Test status
Simulation time 22746876 ps
CPU time 0.9 seconds
Started Aug 09 07:51:41 PM PDT 24
Finished Aug 09 07:51:42 PM PDT 24
Peak memory 218352 kb
Host smart-fd67eae8-5c38-4240-8aa5-9792005974e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990884097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1990884097
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.995423966
Short name T620
Test name
Test status
Simulation time 42870745 ps
CPU time 1.25 seconds
Started Aug 09 07:51:43 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 218872 kb
Host smart-8483b79f-a4b5-4ca6-af75-1f02ab34d6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995423966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.995423966
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1813873525
Short name T972
Test name
Test status
Simulation time 29383473 ps
CPU time 1.01 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 215356 kb
Host smart-9aa4dcc4-c180-4d16-ab87-19ffb09cc570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813873525 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1813873525
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1675193965
Short name T388
Test name
Test status
Simulation time 27789542 ps
CPU time 0.97 seconds
Started Aug 09 07:51:47 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 215332 kb
Host smart-376f825d-8e25-4bc7-a1b0-0a54727cbb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675193965 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1675193965
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.218652763
Short name T250
Test name
Test status
Simulation time 48084330 ps
CPU time 1.02 seconds
Started Aug 09 07:51:43 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 206960 kb
Host smart-f572dae7-d093-464f-a8d3-4cd98e823b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218652763 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.218652763
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.4024575406
Short name T827
Test name
Test status
Simulation time 29421388567 ps
CPU time 421.46 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:58:48 PM PDT 24
Peak memory 223628 kb
Host smart-317cb5a8-798e-4c78-bd2f-66aa645f42a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024575406 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.4024575406
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3683788964
Short name T857
Test name
Test status
Simulation time 26877467 ps
CPU time 1.11 seconds
Started Aug 09 07:51:43 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 219548 kb
Host smart-87cf4008-3a64-4b4f-b7cd-2e4fd4b76fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683788964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3683788964
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2072309985
Short name T422
Test name
Test status
Simulation time 24180059 ps
CPU time 0.94 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 206812 kb
Host smart-29edab56-767b-4a63-bdc3-04de953cef6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072309985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2072309985
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3721264857
Short name T510
Test name
Test status
Simulation time 38601121 ps
CPU time 1.08 seconds
Started Aug 09 07:51:45 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 218560 kb
Host smart-c70f9cc8-4525-48e4-ba28-4f436a8da016
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721264857 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3721264857
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2999381147
Short name T603
Test name
Test status
Simulation time 30322326 ps
CPU time 1 seconds
Started Aug 09 07:51:45 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 219836 kb
Host smart-6e66705b-c6d5-48b7-8978-38f15e7728d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999381147 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2999381147
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3587566938
Short name T752
Test name
Test status
Simulation time 33549194 ps
CPU time 1.46 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 217760 kb
Host smart-4c946b97-38b3-429d-8e44-b85ee598f616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587566938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3587566938
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3166335878
Short name T986
Test name
Test status
Simulation time 21898858 ps
CPU time 1.2 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:43 PM PDT 24
Peak memory 215364 kb
Host smart-2a850800-7eb3-41ad-a380-8dc83f4ce317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166335878 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3166335878
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3809670459
Short name T694
Test name
Test status
Simulation time 48700996 ps
CPU time 0.91 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 215276 kb
Host smart-3b0d7808-d22f-482b-99be-78e88dd9c711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809670459 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3809670459
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.969995972
Short name T379
Test name
Test status
Simulation time 173562173 ps
CPU time 1.46 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 217308 kb
Host smart-c2fa7a76-6ee8-4c99-822e-a9d86d77fa53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969995972 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.969995972
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1354302557
Short name T812
Test name
Test status
Simulation time 335121153302 ps
CPU time 1546.59 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 08:17:33 PM PDT 24
Peak memory 224300 kb
Host smart-8d422abc-58a6-4958-8bba-d30c4fac112e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354302557 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1354302557
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2063768539
Short name T137
Test name
Test status
Simulation time 90265187 ps
CPU time 1.13 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:43 PM PDT 24
Peak memory 220124 kb
Host smart-9cadd80d-b2db-4cd7-b8a6-cd57fca853d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063768539 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2063768539
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.179041708
Short name T373
Test name
Test status
Simulation time 21098369 ps
CPU time 1.09 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:43 PM PDT 24
Peak memory 215200 kb
Host smart-961f2537-f05e-4eee-8452-155572e29c26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179041708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.179041708
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.290180405
Short name T187
Test name
Test status
Simulation time 14282038 ps
CPU time 0.89 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 216644 kb
Host smart-2436bdda-62c7-44a6-969b-e6c6c4f48c68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290180405 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.290180405
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.474053913
Short name T39
Test name
Test status
Simulation time 22883724 ps
CPU time 0.93 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:50 PM PDT 24
Peak memory 218776 kb
Host smart-866bbf88-bde1-44af-91bc-1d03ed15936d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474053913 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.474053913
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.442807436
Short name T869
Test name
Test status
Simulation time 44915652 ps
CPU time 1.22 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 219932 kb
Host smart-1f3b94d4-7d6e-4189-b36d-0b59d9612481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442807436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.442807436
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.866600059
Short name T36
Test name
Test status
Simulation time 20806679 ps
CPU time 1.06 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 215952 kb
Host smart-19205470-01df-46ce-a838-95214df9b633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866600059 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.866600059
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.837677149
Short name T498
Test name
Test status
Simulation time 23042936 ps
CPU time 0.86 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:43 PM PDT 24
Peak memory 215280 kb
Host smart-a49bd1ee-5b02-432e-8508-0baf298ef6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837677149 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.837677149
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.746755694
Short name T580
Test name
Test status
Simulation time 495246429 ps
CPU time 3 seconds
Started Aug 09 07:51:49 PM PDT 24
Finished Aug 09 07:51:53 PM PDT 24
Peak memory 217452 kb
Host smart-06522f09-096c-4c16-874a-888dc04ff4a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746755694 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.746755694
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3191971014
Short name T659
Test name
Test status
Simulation time 50379682946 ps
CPU time 206.14 seconds
Started Aug 09 07:51:41 PM PDT 24
Finished Aug 09 07:55:07 PM PDT 24
Peak memory 218932 kb
Host smart-295838e4-a770-4a05-be98-1f824cf0e95c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191971014 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3191971014
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.4011894716
Short name T981
Test name
Test status
Simulation time 88824150 ps
CPU time 1.18 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 218500 kb
Host smart-bb1f5801-5825-4876-a22b-bab4a9dde4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011894716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.4011894716
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.4130392727
Short name T431
Test name
Test status
Simulation time 36232647 ps
CPU time 0.86 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:47 PM PDT 24
Peak memory 206796 kb
Host smart-d808d456-9984-41ef-97a0-8904034f0155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130392727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.4130392727
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1040047973
Short name T924
Test name
Test status
Simulation time 14810286 ps
CPU time 0.92 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:52 PM PDT 24
Peak memory 219524 kb
Host smart-a76f2269-969c-4415-8758-bb1d60dae1e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040047973 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1040047973
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.912348707
Short name T226
Test name
Test status
Simulation time 30239143 ps
CPU time 1.24 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 219800 kb
Host smart-9abf16c0-987b-4904-b80f-ebaa8435ea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912348707 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.912348707
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1825576125
Short name T497
Test name
Test status
Simulation time 36139994 ps
CPU time 1.33 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 218592 kb
Host smart-0a3f8280-1fc6-4e1f-928c-ebdb1713822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825576125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1825576125
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3176314908
Short name T114
Test name
Test status
Simulation time 34492575 ps
CPU time 0.85 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 215732 kb
Host smart-aba7b6ca-c2e2-4f78-b3cc-6241b6684347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176314908 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3176314908
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.614986211
Short name T505
Test name
Test status
Simulation time 61945280 ps
CPU time 0.92 seconds
Started Aug 09 07:51:43 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 215284 kb
Host smart-a1a281d2-b65b-40b0-8de8-1688daf081c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614986211 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.614986211
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.907403073
Short name T755
Test name
Test status
Simulation time 614819978 ps
CPU time 2.1 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:47 PM PDT 24
Peak memory 217036 kb
Host smart-defab5ce-d17e-4d37-a14e-121299d09c82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907403073 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.907403073
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1677974590
Short name T685
Test name
Test status
Simulation time 34783572795 ps
CPU time 822.36 seconds
Started Aug 09 07:51:41 PM PDT 24
Finished Aug 09 08:05:24 PM PDT 24
Peak memory 217912 kb
Host smart-ca7c6463-67dc-490f-800b-3c98164ec608
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677974590 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1677974590
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3414759171
Short name T931
Test name
Test status
Simulation time 27998418 ps
CPU time 1.21 seconds
Started Aug 09 07:50:52 PM PDT 24
Finished Aug 09 07:50:54 PM PDT 24
Peak memory 218568 kb
Host smart-90e71348-07f9-4735-9f2b-ffa560a68ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414759171 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3414759171
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.4193053113
Short name T507
Test name
Test status
Simulation time 29785171 ps
CPU time 1.13 seconds
Started Aug 09 07:50:50 PM PDT 24
Finished Aug 09 07:50:51 PM PDT 24
Peak memory 215184 kb
Host smart-f9c6adb9-bf57-4522-9ae5-76a590c8df85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193053113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.4193053113
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3269390294
Short name T540
Test name
Test status
Simulation time 13196854 ps
CPU time 0.88 seconds
Started Aug 09 07:50:48 PM PDT 24
Finished Aug 09 07:50:50 PM PDT 24
Peak memory 216636 kb
Host smart-7d1ef29d-f35c-4a9d-ac62-962d1130c451
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269390294 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3269390294
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2090507846
Short name T224
Test name
Test status
Simulation time 35770868 ps
CPU time 1.32 seconds
Started Aug 09 07:50:55 PM PDT 24
Finished Aug 09 07:50:56 PM PDT 24
Peak memory 217200 kb
Host smart-68ba3bfb-f8ed-4fcd-a3ee-81e976f32bac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090507846 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2090507846
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2158418726
Short name T153
Test name
Test status
Simulation time 24369533 ps
CPU time 1.13 seconds
Started Aug 09 07:50:48 PM PDT 24
Finished Aug 09 07:50:50 PM PDT 24
Peak memory 220884 kb
Host smart-63cc843f-bbe8-4f15-a0ea-1403203931d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158418726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2158418726
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3941776050
Short name T258
Test name
Test status
Simulation time 82871235 ps
CPU time 1.15 seconds
Started Aug 09 07:50:49 PM PDT 24
Finished Aug 09 07:50:51 PM PDT 24
Peak memory 217428 kb
Host smart-1d972b71-55da-4b46-ab95-fa8e256ecb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941776050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3941776050
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3732859964
Short name T571
Test name
Test status
Simulation time 45516624 ps
CPU time 0.86 seconds
Started Aug 09 07:50:53 PM PDT 24
Finished Aug 09 07:50:54 PM PDT 24
Peak memory 215920 kb
Host smart-c078b334-d10d-454f-9dab-9d6632980562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732859964 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3732859964
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2070029244
Short name T30
Test name
Test status
Simulation time 181506233 ps
CPU time 0.97 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 07:50:55 PM PDT 24
Peak memory 207072 kb
Host smart-42c0cf80-0da6-4f12-8c61-f5671579ac8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070029244 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2070029244
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2448520883
Short name T21
Test name
Test status
Simulation time 430899164 ps
CPU time 7.26 seconds
Started Aug 09 07:50:50 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 241928 kb
Host smart-770c6a2d-31d4-4fae-af33-f54acba32e00
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448520883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2448520883
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1663744614
Short name T839
Test name
Test status
Simulation time 50688345 ps
CPU time 0.93 seconds
Started Aug 09 07:50:47 PM PDT 24
Finished Aug 09 07:50:48 PM PDT 24
Peak memory 215284 kb
Host smart-63eaa57d-3b0c-4594-a01d-826998c2c332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663744614 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1663744614
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2075916221
Short name T712
Test name
Test status
Simulation time 350662029 ps
CPU time 2.51 seconds
Started Aug 09 07:50:50 PM PDT 24
Finished Aug 09 07:50:52 PM PDT 24
Peak memory 215440 kb
Host smart-5ff620b1-b7b9-4c25-b963-0e176db71b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075916221 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2075916221
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1550338334
Short name T244
Test name
Test status
Simulation time 132314151895 ps
CPU time 422.95 seconds
Started Aug 09 07:50:52 PM PDT 24
Finished Aug 09 07:57:56 PM PDT 24
Peak memory 218688 kb
Host smart-cafb81a5-7db6-4b24-8802-7f3ad611fa7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550338334 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1550338334
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.470890807
Short name T583
Test name
Test status
Simulation time 41792736 ps
CPU time 1.1 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 218492 kb
Host smart-e93f537e-e2aa-4f46-8cf1-c50f41fd11e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470890807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.470890807
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2645873117
Short name T545
Test name
Test status
Simulation time 20967928 ps
CPU time 1.04 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:47 PM PDT 24
Peak memory 206996 kb
Host smart-fdccc416-d473-4080-aab5-dd63c4f60f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645873117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2645873117
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.730987193
Short name T371
Test name
Test status
Simulation time 24159465 ps
CPU time 0.86 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 216352 kb
Host smart-3ef2ca78-d119-4125-811a-1dbe29fb722a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730987193 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.730987193
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3415438089
Short name T570
Test name
Test status
Simulation time 26890692 ps
CPU time 1.1 seconds
Started Aug 09 07:51:50 PM PDT 24
Finished Aug 09 07:51:51 PM PDT 24
Peak memory 217008 kb
Host smart-3c61b58f-ba41-4207-9bf0-0ba4c721a723
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415438089 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3415438089
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3641188833
Short name T612
Test name
Test status
Simulation time 20781012 ps
CPU time 0.95 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 218468 kb
Host smart-6c1f03e3-fce2-46d4-9133-0676fcaf64f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641188833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3641188833
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_intr.350757706
Short name T459
Test name
Test status
Simulation time 37667210 ps
CPU time 0.9 seconds
Started Aug 09 07:51:47 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 215360 kb
Host smart-cb97ce92-7e30-4a60-bc19-f11f687ecf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350757706 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.350757706
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.224967020
Short name T902
Test name
Test status
Simulation time 48012623 ps
CPU time 0.89 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 215208 kb
Host smart-2065b061-4e04-4b31-85c3-7708163889d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224967020 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.224967020
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2024985620
Short name T610
Test name
Test status
Simulation time 33600660 ps
CPU time 1.23 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:47 PM PDT 24
Peak memory 215332 kb
Host smart-d379e461-cd6d-4759-9ae0-f520e62fbac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024985620 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2024985620
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2780471890
Short name T243
Test name
Test status
Simulation time 123541973540 ps
CPU time 1191.31 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 08:11:37 PM PDT 24
Peak memory 221700 kb
Host smart-9f4e82ed-1a4f-4c5c-af49-cba0d073da96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780471890 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2780471890
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3310246236
Short name T746
Test name
Test status
Simulation time 47955057 ps
CPU time 1.14 seconds
Started Aug 09 07:51:43 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 218472 kb
Host smart-cab34980-e626-49f0-86c6-578161cc1748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310246236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3310246236
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2095287817
Short name T825
Test name
Test status
Simulation time 51138270 ps
CPU time 0.83 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 206736 kb
Host smart-a66b458e-b7fe-4e24-8839-63f290602945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095287817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2095287817
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2281880754
Short name T628
Test name
Test status
Simulation time 17328066 ps
CPU time 0.88 seconds
Started Aug 09 07:51:45 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 216468 kb
Host smart-673c7534-e37e-4420-a8d6-42dffdb0882e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281880754 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2281880754
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.893523474
Short name T164
Test name
Test status
Simulation time 37196794 ps
CPU time 1.22 seconds
Started Aug 09 07:51:45 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 217224 kb
Host smart-f4a9fd0b-2d31-43a9-8086-8a117d41bf69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893523474 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.893523474
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1882378395
Short name T193
Test name
Test status
Simulation time 19580175 ps
CPU time 1.15 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:47 PM PDT 24
Peak memory 224308 kb
Host smart-b91c116b-4de8-4dff-bb0e-e0cfde1b6d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882378395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1882378395
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2177370929
Short name T499
Test name
Test status
Simulation time 44493315 ps
CPU time 1.26 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 219060 kb
Host smart-1f972fe1-a308-4c5a-9786-193e19fa2ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177370929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2177370929
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.63228641
Short name T753
Test name
Test status
Simulation time 101363154 ps
CPU time 0.99 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:47 PM PDT 24
Peak memory 224092 kb
Host smart-7d093793-151c-4d52-8041-3477c507d2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63228641 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.63228641
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.356389966
Short name T383
Test name
Test status
Simulation time 77657912 ps
CPU time 0.88 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 215308 kb
Host smart-c49fd94b-1f02-43f7-852a-8afe9675c02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356389966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.356389966
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2465371208
Short name T251
Test name
Test status
Simulation time 398427942 ps
CPU time 7.32 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:52 PM PDT 24
Peak memory 217324 kb
Host smart-07c03d0c-989f-47bd-8992-c262e6d803e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465371208 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2465371208
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3313162252
Short name T125
Test name
Test status
Simulation time 44574773836 ps
CPU time 1173.88 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 08:11:16 PM PDT 24
Peak memory 221536 kb
Host smart-2202639c-ce1a-4ac5-93c2-3c5518f77520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313162252 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3313162252
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1899217304
Short name T558
Test name
Test status
Simulation time 41562621 ps
CPU time 1.41 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 221692 kb
Host smart-c8a73655-6544-4b1b-ad29-8ea50eb27e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899217304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1899217304
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2991750557
Short name T767
Test name
Test status
Simulation time 57294353 ps
CPU time 0.9 seconds
Started Aug 09 07:52:02 PM PDT 24
Finished Aug 09 07:52:03 PM PDT 24
Peak memory 206872 kb
Host smart-87ccf4c2-ae82-455c-b357-1e7a8b3ba92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991750557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2991750557
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1477481404
Short name T660
Test name
Test status
Simulation time 17701594 ps
CPU time 0.86 seconds
Started Aug 09 07:51:47 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 216472 kb
Host smart-4b85d1ee-3520-47fd-8ba5-b26016d756fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477481404 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1477481404
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1708833515
Short name T375
Test name
Test status
Simulation time 55475366 ps
CPU time 1.2 seconds
Started Aug 09 07:51:47 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 218732 kb
Host smart-86ef9f7e-e8a3-4773-bba7-4f1ff67a9669
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708833515 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1708833515
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2600472718
Short name T985
Test name
Test status
Simulation time 94124028 ps
CPU time 0.81 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 218512 kb
Host smart-f607f55f-f7c5-4147-8f8c-38501bcde538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600472718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2600472718
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2317565738
Short name T71
Test name
Test status
Simulation time 65843672 ps
CPU time 1.37 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 218844 kb
Host smart-cbbf7527-31ff-4907-827f-78ed2d4543ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317565738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2317565738
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2185053394
Short name T254
Test name
Test status
Simulation time 24816000 ps
CPU time 1.07 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 215380 kb
Host smart-4ef4080d-028a-4d4c-8a09-16a7c0029fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185053394 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2185053394
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2332042150
Short name T898
Test name
Test status
Simulation time 142271812 ps
CPU time 0.94 seconds
Started Aug 09 07:51:47 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 215280 kb
Host smart-42adb855-cd7b-45f2-bf8f-14bab04c793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332042150 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2332042150
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3264957121
Short name T496
Test name
Test status
Simulation time 513798081 ps
CPU time 5.26 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:52 PM PDT 24
Peak memory 217236 kb
Host smart-16ee3395-a43a-480d-983c-59cfac1e52dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264957121 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3264957121
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3521977795
Short name T573
Test name
Test status
Simulation time 606723695673 ps
CPU time 1243.36 seconds
Started Aug 09 07:51:43 PM PDT 24
Finished Aug 09 08:12:26 PM PDT 24
Peak memory 222640 kb
Host smart-0e02bd9a-30ea-4152-bff1-b13b1735515b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521977795 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3521977795
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert_test.1227880521
Short name T131
Test name
Test status
Simulation time 16671410 ps
CPU time 0.95 seconds
Started Aug 09 07:51:52 PM PDT 24
Finished Aug 09 07:51:53 PM PDT 24
Peak memory 215152 kb
Host smart-5e2430ca-d930-4a0d-8f2b-f5cab1a334ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227880521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1227880521
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1326639515
Short name T201
Test name
Test status
Simulation time 10045833 ps
CPU time 0.86 seconds
Started Aug 09 07:51:47 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 219060 kb
Host smart-5b95c743-dbe8-4748-81e2-a79c0fddd347
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326639515 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1326639515
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2148594986
Short name T171
Test name
Test status
Simulation time 101099423 ps
CPU time 1.11 seconds
Started Aug 09 07:51:49 PM PDT 24
Finished Aug 09 07:51:51 PM PDT 24
Peak memory 215712 kb
Host smart-e4bcacff-51d8-400c-9295-d22bd5916f02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148594986 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2148594986
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1541393446
Short name T214
Test name
Test status
Simulation time 24740429 ps
CPU time 0.98 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:47 PM PDT 24
Peak memory 218756 kb
Host smart-dca8a55d-e2a4-4a77-9ae9-184b27d4093e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541393446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1541393446
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1740047180
Short name T27
Test name
Test status
Simulation time 32836211 ps
CPU time 1.3 seconds
Started Aug 09 07:51:55 PM PDT 24
Finished Aug 09 07:51:57 PM PDT 24
Peak memory 218432 kb
Host smart-e2ce0a3f-dcaf-48ce-93c7-dc5c3cdcd6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740047180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1740047180
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2626077545
Short name T593
Test name
Test status
Simulation time 42471988 ps
CPU time 1 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:50 PM PDT 24
Peak memory 224136 kb
Host smart-8b6239bd-aef9-478f-b105-4079c029ee0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626077545 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2626077545
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2667491998
Short name T493
Test name
Test status
Simulation time 18344034 ps
CPU time 1 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 215256 kb
Host smart-cbcf9e94-bb34-49d7-a61e-e2432b1a8d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667491998 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2667491998
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3134810305
Short name T983
Test name
Test status
Simulation time 225721294 ps
CPU time 2.58 seconds
Started Aug 09 07:51:45 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 215232 kb
Host smart-ab507892-2b32-4cf4-aab2-411c36f72a03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134810305 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3134810305
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1954052834
Short name T897
Test name
Test status
Simulation time 74434898448 ps
CPU time 1959.1 seconds
Started Aug 09 07:51:41 PM PDT 24
Finished Aug 09 08:24:21 PM PDT 24
Peak memory 228492 kb
Host smart-fc02de8d-5a11-4b47-a6fe-1a7610e754b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954052834 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1954052834
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1969179409
Short name T892
Test name
Test status
Simulation time 68928709 ps
CPU time 1.05 seconds
Started Aug 09 07:51:50 PM PDT 24
Finished Aug 09 07:51:52 PM PDT 24
Peak memory 220076 kb
Host smart-2aceac89-c25f-4c79-9fc5-20ac544c8846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969179409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1969179409
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1990535540
Short name T716
Test name
Test status
Simulation time 20093421 ps
CPU time 0.97 seconds
Started Aug 09 07:51:53 PM PDT 24
Finished Aug 09 07:51:54 PM PDT 24
Peak memory 206840 kb
Host smart-1a523ca2-d20a-44cf-a854-13b00c037cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990535540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1990535540
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2485324154
Short name T195
Test name
Test status
Simulation time 10880488 ps
CPU time 0.87 seconds
Started Aug 09 07:51:50 PM PDT 24
Finished Aug 09 07:51:51 PM PDT 24
Peak memory 216468 kb
Host smart-d1920fd7-35bc-41a2-85a0-341d9e2b25c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485324154 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2485324154
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2148433604
Short name T533
Test name
Test status
Simulation time 101413695 ps
CPU time 1.08 seconds
Started Aug 09 07:52:02 PM PDT 24
Finished Aug 09 07:52:03 PM PDT 24
Peak memory 219552 kb
Host smart-f16d9ed8-eccf-43f0-8d48-bb0e4fe190fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148433604 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2148433604
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1495905845
Short name T686
Test name
Test status
Simulation time 74664493 ps
CPU time 0.96 seconds
Started Aug 09 07:51:57 PM PDT 24
Finished Aug 09 07:51:58 PM PDT 24
Peak memory 219980 kb
Host smart-f03413a6-01f7-411f-b8bf-0fc0910f6360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495905845 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1495905845
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1459479835
Short name T440
Test name
Test status
Simulation time 30586314 ps
CPU time 1.33 seconds
Started Aug 09 07:51:54 PM PDT 24
Finished Aug 09 07:51:56 PM PDT 24
Peak memory 217248 kb
Host smart-b9827406-7505-4cdf-a8a8-ba3180d1db9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459479835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1459479835
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.88887643
Short name T616
Test name
Test status
Simulation time 56085246 ps
CPU time 0.88 seconds
Started Aug 09 07:51:52 PM PDT 24
Finished Aug 09 07:51:53 PM PDT 24
Peak memory 215280 kb
Host smart-726ca0c8-f8bf-4495-b3a8-bedbe9d7fbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88887643 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.88887643
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3826414908
Short name T590
Test name
Test status
Simulation time 16261244 ps
CPU time 1.01 seconds
Started Aug 09 07:51:59 PM PDT 24
Finished Aug 09 07:52:00 PM PDT 24
Peak memory 215372 kb
Host smart-f08c78a3-4a44-403c-8b51-f9def572a5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826414908 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3826414908
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2200440488
Short name T614
Test name
Test status
Simulation time 788310035 ps
CPU time 4.14 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:51 PM PDT 24
Peak memory 215304 kb
Host smart-cb050910-bc46-4e95-a0d6-65ca1bd5766c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200440488 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2200440488
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.614003137
Short name T723
Test name
Test status
Simulation time 77387115989 ps
CPU time 837.77 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 08:05:42 PM PDT 24
Peak memory 220284 kb
Host smart-f04f3fe5-7055-4801-84f4-719e01dee4cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614003137 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.614003137
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.949630333
Short name T930
Test name
Test status
Simulation time 38859979 ps
CPU time 1.18 seconds
Started Aug 09 07:51:50 PM PDT 24
Finished Aug 09 07:51:52 PM PDT 24
Peak memory 219092 kb
Host smart-470fd297-af5b-4911-98d7-ef5d6632dc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949630333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.949630333
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1556946183
Short name T761
Test name
Test status
Simulation time 73341736 ps
CPU time 0.89 seconds
Started Aug 09 07:51:54 PM PDT 24
Finished Aug 09 07:51:54 PM PDT 24
Peak memory 215168 kb
Host smart-4c4e2d12-9656-4fd2-930f-2514f8ec3882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556946183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1556946183
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2649171403
Short name T631
Test name
Test status
Simulation time 41681006 ps
CPU time 0.86 seconds
Started Aug 09 07:51:45 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 216408 kb
Host smart-64599284-c1bd-4160-84ad-3611c049ba0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649171403 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2649171403
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2151584396
Short name T852
Test name
Test status
Simulation time 48341701 ps
CPU time 1.16 seconds
Started Aug 09 07:51:56 PM PDT 24
Finished Aug 09 07:51:58 PM PDT 24
Peak memory 218520 kb
Host smart-1c0a9602-28a0-40bb-8681-57f4c47e9301
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151584396 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2151584396
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1233304499
Short name T722
Test name
Test status
Simulation time 21428798 ps
CPU time 1.11 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 220028 kb
Host smart-95f44475-371a-4777-8819-9d972e60d778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233304499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1233304499
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1317589501
Short name T327
Test name
Test status
Simulation time 58950344 ps
CPU time 1.47 seconds
Started Aug 09 07:51:42 PM PDT 24
Finished Aug 09 07:51:44 PM PDT 24
Peak memory 218644 kb
Host smart-26f6a576-d7ae-4e1c-91db-fe3f50197291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317589501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1317589501
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_smoke.1393069066
Short name T118
Test name
Test status
Simulation time 46274445 ps
CPU time 0.89 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:45 PM PDT 24
Peak memory 215312 kb
Host smart-40969178-7c76-4aa3-a9e4-ce25be1e6d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393069066 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1393069066
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3656218844
Short name T954
Test name
Test status
Simulation time 38239864303 ps
CPU time 491.31 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:59:59 PM PDT 24
Peak memory 217944 kb
Host smart-1eba7232-0fae-406e-93ac-9bf372b265fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656218844 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3656218844
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1487859005
Short name T751
Test name
Test status
Simulation time 28499183 ps
CPU time 1.23 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 219392 kb
Host smart-3de7ba4f-c6cd-4ef2-bc72-77b290f29213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487859005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1487859005
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4243548249
Short name T130
Test name
Test status
Simulation time 46118135 ps
CPU time 0.93 seconds
Started Aug 09 07:51:49 PM PDT 24
Finished Aug 09 07:51:50 PM PDT 24
Peak memory 206776 kb
Host smart-3ad2ccc8-83ec-4d86-909c-6a7ff4c571d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243548249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4243548249
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.16638656
Short name T835
Test name
Test status
Simulation time 79800373 ps
CPU time 0.86 seconds
Started Aug 09 07:51:49 PM PDT 24
Finished Aug 09 07:51:50 PM PDT 24
Peak memory 215340 kb
Host smart-2b4f1d08-a0c3-4584-88ce-c24d34937e81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16638656 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.16638656
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2489356630
Short name T509
Test name
Test status
Simulation time 59768117 ps
CPU time 1.08 seconds
Started Aug 09 07:52:01 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 219808 kb
Host smart-9a494860-b8eb-43a0-b6f6-a0f5592a87d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489356630 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2489356630
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_genbits.2428527287
Short name T771
Test name
Test status
Simulation time 79159356 ps
CPU time 1.46 seconds
Started Aug 09 07:51:51 PM PDT 24
Finished Aug 09 07:51:52 PM PDT 24
Peak memory 218848 kb
Host smart-d0ffb846-7388-49f4-b474-5a521b5820d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428527287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2428527287
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3586664648
Short name T666
Test name
Test status
Simulation time 21525386 ps
CPU time 1.04 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 214124 kb
Host smart-0dd793e4-cf62-48ac-b8fe-59527b1a8f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586664648 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3586664648
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2139810629
Short name T705
Test name
Test status
Simulation time 21542163 ps
CPU time 0.92 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 215324 kb
Host smart-5860cae5-ed0a-43d1-b8f0-2dfc907e21dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139810629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2139810629
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3142096264
Short name T992
Test name
Test status
Simulation time 336877953 ps
CPU time 2.04 seconds
Started Aug 09 07:52:00 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 215228 kb
Host smart-4b813a9a-84b0-4a63-a090-23b9a4d93930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142096264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3142096264
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.499677829
Short name T216
Test name
Test status
Simulation time 38106938180 ps
CPU time 978.95 seconds
Started Aug 09 07:51:54 PM PDT 24
Finished Aug 09 08:08:13 PM PDT 24
Peak memory 219736 kb
Host smart-5dc1955e-0f89-4795-bbcd-b1e024233729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499677829 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.499677829
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1223837090
Short name T100
Test name
Test status
Simulation time 41453909 ps
CPU time 1.27 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 218484 kb
Host smart-da31b652-24e6-4585-bd30-43b49e481c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223837090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1223837090
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.350263146
Short name T564
Test name
Test status
Simulation time 66443418 ps
CPU time 0.91 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 206828 kb
Host smart-009adcc0-ee2e-433f-af3b-65b2a9aa7749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350263146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.350263146
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1859214632
Short name T188
Test name
Test status
Simulation time 10626386 ps
CPU time 0.92 seconds
Started Aug 09 07:51:51 PM PDT 24
Finished Aug 09 07:51:52 PM PDT 24
Peak memory 216452 kb
Host smart-87f968c6-e575-4ebe-9629-531d3df7ba53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859214632 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1859214632
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2343364030
Short name T96
Test name
Test status
Simulation time 79041998 ps
CPU time 1.06 seconds
Started Aug 09 07:51:55 PM PDT 24
Finished Aug 09 07:51:56 PM PDT 24
Peak memory 217140 kb
Host smart-a3e21342-3179-4cd5-a5ce-f067cca472f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343364030 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2343364030
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3103318865
Short name T504
Test name
Test status
Simulation time 28819241 ps
CPU time 1.23 seconds
Started Aug 09 07:51:57 PM PDT 24
Finished Aug 09 07:51:58 PM PDT 24
Peak memory 219996 kb
Host smart-e6112941-bbff-4662-9cdb-1ea1dc3d3c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103318865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3103318865
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.4046195708
Short name T938
Test name
Test status
Simulation time 186224875 ps
CPU time 1.82 seconds
Started Aug 09 07:51:44 PM PDT 24
Finished Aug 09 07:51:46 PM PDT 24
Peak memory 218680 kb
Host smart-5348d928-97bf-42e9-b9e8-94903db29f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046195708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.4046195708
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2010874616
Short name T554
Test name
Test status
Simulation time 21396082 ps
CPU time 1.09 seconds
Started Aug 09 07:52:04 PM PDT 24
Finished Aug 09 07:52:05 PM PDT 24
Peak memory 215360 kb
Host smart-0a318b70-30e5-455a-9b86-0917d9c2c727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010874616 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2010874616
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2653836431
Short name T73
Test name
Test status
Simulation time 36845191 ps
CPU time 0.96 seconds
Started Aug 09 07:51:52 PM PDT 24
Finished Aug 09 07:51:53 PM PDT 24
Peak memory 215312 kb
Host smart-81cbc87b-ff4d-4d8a-a3fd-c1f916ae558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653836431 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2653836431
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3605527820
Short name T850
Test name
Test status
Simulation time 147620174 ps
CPU time 2.19 seconds
Started Aug 09 07:51:53 PM PDT 24
Finished Aug 09 07:51:55 PM PDT 24
Peak memory 215304 kb
Host smart-8e64373c-1794-41fb-8430-6f8627400fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605527820 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3605527820
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2150519133
Short name T45
Test name
Test status
Simulation time 157012485491 ps
CPU time 2049.2 seconds
Started Aug 09 07:51:58 PM PDT 24
Finished Aug 09 08:26:08 PM PDT 24
Peak memory 228184 kb
Host smart-3af6b709-1171-41b9-a94a-b3c42560cf3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150519133 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2150519133
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1783671400
Short name T853
Test name
Test status
Simulation time 304346940 ps
CPU time 1.57 seconds
Started Aug 09 07:51:52 PM PDT 24
Finished Aug 09 07:51:54 PM PDT 24
Peak memory 219652 kb
Host smart-d57ad4cd-c44c-4e1c-ae44-76f1c0b4617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783671400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1783671400
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3645454991
Short name T456
Test name
Test status
Simulation time 16956108 ps
CPU time 0.82 seconds
Started Aug 09 07:52:00 PM PDT 24
Finished Aug 09 07:52:01 PM PDT 24
Peak memory 206764 kb
Host smart-8c0ccd5b-22a1-4157-b9ac-0b022c8ec05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645454991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3645454991
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.444306612
Short name T809
Test name
Test status
Simulation time 18623237 ps
CPU time 0.86 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 215404 kb
Host smart-6cccdbe0-e0e9-42f9-bd54-910a90613833
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444306612 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.444306612
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.93773058
Short name T464
Test name
Test status
Simulation time 54116108 ps
CPU time 1.07 seconds
Started Aug 09 07:51:50 PM PDT 24
Finished Aug 09 07:51:51 PM PDT 24
Peak memory 218460 kb
Host smart-212db5f1-0606-421f-a87e-1042d912f52e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93773058 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_dis
able_auto_req_mode.93773058
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.895209135
Short name T824
Test name
Test status
Simulation time 23370375 ps
CPU time 1.09 seconds
Started Aug 09 07:51:49 PM PDT 24
Finished Aug 09 07:51:50 PM PDT 24
Peak memory 224116 kb
Host smart-aa01da7f-8907-4ae0-919d-4652cbaed588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895209135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.895209135
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2808004787
Short name T401
Test name
Test status
Simulation time 47068893 ps
CPU time 1.36 seconds
Started Aug 09 07:52:05 PM PDT 24
Finished Aug 09 07:52:07 PM PDT 24
Peak memory 219980 kb
Host smart-99564ccb-d361-49ac-bb86-4848e754bb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808004787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2808004787
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1788789938
Short name T816
Test name
Test status
Simulation time 35690560 ps
CPU time 0.94 seconds
Started Aug 09 07:51:54 PM PDT 24
Finished Aug 09 07:51:55 PM PDT 24
Peak memory 223956 kb
Host smart-0b956d46-514a-4a15-a1a3-42381dfc8045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788789938 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1788789938
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.195618299
Short name T621
Test name
Test status
Simulation time 31606344 ps
CPU time 0.99 seconds
Started Aug 09 07:51:48 PM PDT 24
Finished Aug 09 07:51:49 PM PDT 24
Peak memory 215288 kb
Host smart-e4294f83-0541-4568-b7c4-fef0f0c73381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195618299 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.195618299
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1203903307
Short name T568
Test name
Test status
Simulation time 155256462 ps
CPU time 2.18 seconds
Started Aug 09 07:51:46 PM PDT 24
Finished Aug 09 07:51:48 PM PDT 24
Peak memory 217304 kb
Host smart-ba90cb92-701b-487f-a04c-357916f6d118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203903307 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1203903307
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_alert.3528411958
Short name T701
Test name
Test status
Simulation time 85612638 ps
CPU time 1.26 seconds
Started Aug 09 07:52:02 PM PDT 24
Finished Aug 09 07:52:04 PM PDT 24
Peak memory 218296 kb
Host smart-5f525b1b-8c75-41d1-8ae2-7f7c82fdc53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528411958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3528411958
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1850373083
Short name T683
Test name
Test status
Simulation time 81118953 ps
CPU time 0.9 seconds
Started Aug 09 07:52:14 PM PDT 24
Finished Aug 09 07:52:15 PM PDT 24
Peak memory 206820 kb
Host smart-e8921995-ebc2-401f-b0f8-a0fc767cbfe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850373083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1850373083
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2206765575
Short name T647
Test name
Test status
Simulation time 63409057 ps
CPU time 0.94 seconds
Started Aug 09 07:52:01 PM PDT 24
Finished Aug 09 07:52:03 PM PDT 24
Peak memory 216476 kb
Host smart-2caac544-1920-44dd-9a1b-079884dbe6eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206765575 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2206765575
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.903984024
Short name T536
Test name
Test status
Simulation time 274686901 ps
CPU time 1.05 seconds
Started Aug 09 07:52:04 PM PDT 24
Finished Aug 09 07:52:06 PM PDT 24
Peak memory 218272 kb
Host smart-2b0dfeac-cc73-4d12-b81f-c49efb16ee21
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903984024 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.903984024
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.4070108079
Short name T842
Test name
Test status
Simulation time 23908425 ps
CPU time 1.09 seconds
Started Aug 09 07:52:05 PM PDT 24
Finished Aug 09 07:52:06 PM PDT 24
Peak memory 228320 kb
Host smart-51dfff3e-17fd-4add-82ca-f41ee34169e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070108079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.4070108079
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1077089969
Short name T331
Test name
Test status
Simulation time 100479091 ps
CPU time 1.09 seconds
Started Aug 09 07:52:15 PM PDT 24
Finished Aug 09 07:52:16 PM PDT 24
Peak memory 217260 kb
Host smart-ea8f0d10-7649-41ab-aeb7-2b6604ce4bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077089969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1077089969
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.797754064
Short name T859
Test name
Test status
Simulation time 88101060 ps
CPU time 0.82 seconds
Started Aug 09 07:52:13 PM PDT 24
Finished Aug 09 07:52:14 PM PDT 24
Peak memory 215292 kb
Host smart-b0e35559-8699-46f3-acdb-9dd9f9eb9794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797754064 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.797754064
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1815725731
Short name T913
Test name
Test status
Simulation time 25506710 ps
CPU time 0.94 seconds
Started Aug 09 07:51:56 PM PDT 24
Finished Aug 09 07:51:57 PM PDT 24
Peak memory 215280 kb
Host smart-20f6712e-e4ab-4c15-bcf1-94832bc678d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815725731 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1815725731
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2065974974
Short name T781
Test name
Test status
Simulation time 318539023 ps
CPU time 6.49 seconds
Started Aug 09 07:51:49 PM PDT 24
Finished Aug 09 07:51:56 PM PDT 24
Peak memory 215300 kb
Host smart-720cccfb-92cd-4d39-9bcd-83265e753170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065974974 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2065974974
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.457711325
Short name T123
Test name
Test status
Simulation time 110867349318 ps
CPU time 1416.72 seconds
Started Aug 09 07:51:52 PM PDT 24
Finished Aug 09 08:15:29 PM PDT 24
Peak memory 226140 kb
Host smart-adf1fa9b-7a6d-4202-be4f-0137095987c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457711325 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.457711325
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3960505563
Short name T198
Test name
Test status
Simulation time 101898916 ps
CPU time 1.29 seconds
Started Aug 09 07:50:52 PM PDT 24
Finished Aug 09 07:50:54 PM PDT 24
Peak memory 218500 kb
Host smart-530c0b29-cccb-4632-8458-a2b964f3349c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960505563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3960505563
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.4019092489
Short name T792
Test name
Test status
Simulation time 13185687 ps
CPU time 0.89 seconds
Started Aug 09 07:50:51 PM PDT 24
Finished Aug 09 07:50:52 PM PDT 24
Peak memory 207028 kb
Host smart-958cf33c-bc53-48a1-898c-9bf457ae6588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019092489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.4019092489
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2413726877
Short name T642
Test name
Test status
Simulation time 23513647 ps
CPU time 1.1 seconds
Started Aug 09 07:50:49 PM PDT 24
Finished Aug 09 07:50:50 PM PDT 24
Peak memory 219468 kb
Host smart-8727b4e7-7cc7-4476-a61b-b020e01c4d78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413726877 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2413726877
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2742325428
Short name T141
Test name
Test status
Simulation time 155705856 ps
CPU time 1.03 seconds
Started Aug 09 07:50:51 PM PDT 24
Finished Aug 09 07:50:52 PM PDT 24
Peak memory 229892 kb
Host smart-e3d7622e-296a-4274-b5fd-daa3969bf803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742325428 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2742325428
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1585811336
Short name T695
Test name
Test status
Simulation time 40166016 ps
CPU time 1.45 seconds
Started Aug 09 07:50:50 PM PDT 24
Finished Aug 09 07:50:52 PM PDT 24
Peak memory 219944 kb
Host smart-a4214588-15de-4973-916d-09bef7a63533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585811336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1585811336
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1267892694
Short name T454
Test name
Test status
Simulation time 38310056 ps
CPU time 0.84 seconds
Started Aug 09 07:50:50 PM PDT 24
Finished Aug 09 07:50:51 PM PDT 24
Peak memory 215972 kb
Host smart-d606984e-b9da-4423-a5cd-7f9c16626834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267892694 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1267892694
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3420566163
Short name T936
Test name
Test status
Simulation time 47762214 ps
CPU time 0.91 seconds
Started Aug 09 07:50:51 PM PDT 24
Finished Aug 09 07:50:52 PM PDT 24
Peak memory 207108 kb
Host smart-3cc68c20-7d96-4b28-88f2-c5422cdabb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420566163 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3420566163
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3177201167
Short name T632
Test name
Test status
Simulation time 28306250 ps
CPU time 0.92 seconds
Started Aug 09 07:50:51 PM PDT 24
Finished Aug 09 07:50:52 PM PDT 24
Peak memory 215252 kb
Host smart-129e4d47-5f8a-4431-9542-7096dcf9ee5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177201167 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3177201167
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.439643669
Short name T404
Test name
Test status
Simulation time 373977933 ps
CPU time 2.64 seconds
Started Aug 09 07:50:53 PM PDT 24
Finished Aug 09 07:50:56 PM PDT 24
Peak memory 215292 kb
Host smart-49a701c3-6b3d-44d0-9176-f34f55507ace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439643669 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.439643669
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.821617720
Short name T714
Test name
Test status
Simulation time 77403519831 ps
CPU time 1026.18 seconds
Started Aug 09 07:50:49 PM PDT 24
Finished Aug 09 08:07:56 PM PDT 24
Peak memory 222936 kb
Host smart-73c76e7d-22cc-4fce-97a2-20797f101dea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821617720 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.821617720
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.523387698
Short name T236
Test name
Test status
Simulation time 32235837 ps
CPU time 1.17 seconds
Started Aug 09 07:51:55 PM PDT 24
Finished Aug 09 07:51:57 PM PDT 24
Peak memory 218904 kb
Host smart-8ff4d3b4-dad5-4512-84bd-d33ab4f1a160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523387698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.523387698
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.991651021
Short name T211
Test name
Test status
Simulation time 28652346 ps
CPU time 0.91 seconds
Started Aug 09 07:51:52 PM PDT 24
Finished Aug 09 07:51:53 PM PDT 24
Peak memory 218244 kb
Host smart-cfc27ef7-2449-4728-a767-3f69586b2cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991651021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.991651021
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1508023299
Short name T539
Test name
Test status
Simulation time 93184395 ps
CPU time 1.09 seconds
Started Aug 09 07:52:13 PM PDT 24
Finished Aug 09 07:52:15 PM PDT 24
Peak memory 219940 kb
Host smart-a3cf706a-51f3-405d-bc51-ad04e56261cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508023299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1508023299
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1461073791
Short name T76
Test name
Test status
Simulation time 19965898 ps
CPU time 1.21 seconds
Started Aug 09 07:51:56 PM PDT 24
Finished Aug 09 07:51:57 PM PDT 24
Peak memory 222684 kb
Host smart-ae68e70f-cb06-487b-b67d-0aeaa438f7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461073791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1461073791
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2319023760
Short name T469
Test name
Test status
Simulation time 123895744 ps
CPU time 3 seconds
Started Aug 09 07:51:56 PM PDT 24
Finished Aug 09 07:52:00 PM PDT 24
Peak memory 219016 kb
Host smart-28e7fe63-b86e-4d6c-84c1-ee865668e416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319023760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2319023760
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.986877297
Short name T484
Test name
Test status
Simulation time 23987787 ps
CPU time 1.23 seconds
Started Aug 09 07:52:01 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 220484 kb
Host smart-c4da48f4-726e-4528-9469-d6b8f93a7a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986877297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.986877297
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_genbits.1703165811
Short name T352
Test name
Test status
Simulation time 133165702 ps
CPU time 1.09 seconds
Started Aug 09 07:51:53 PM PDT 24
Finished Aug 09 07:51:54 PM PDT 24
Peak memory 217280 kb
Host smart-9d35a351-29fc-41c0-9696-877a05338cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703165811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1703165811
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2025849165
Short name T596
Test name
Test status
Simulation time 75408328 ps
CPU time 1.07 seconds
Started Aug 09 07:52:13 PM PDT 24
Finished Aug 09 07:52:15 PM PDT 24
Peak memory 219676 kb
Host smart-85bae1ba-2a73-4305-a251-2bbfbe59b332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025849165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2025849165
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.4169831314
Short name T140
Test name
Test status
Simulation time 41160388 ps
CPU time 1.06 seconds
Started Aug 09 07:52:03 PM PDT 24
Finished Aug 09 07:52:04 PM PDT 24
Peak memory 229700 kb
Host smart-476876d8-234d-47de-9f90-e3189261282a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169831314 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.4169831314
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1695471937
Short name T667
Test name
Test status
Simulation time 50339007 ps
CPU time 1.09 seconds
Started Aug 09 07:51:57 PM PDT 24
Finished Aug 09 07:51:58 PM PDT 24
Peak memory 219652 kb
Host smart-2b52136d-3ec3-45fb-a6bd-2add4dfe950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695471937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1695471937
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2721125610
Short name T315
Test name
Test status
Simulation time 37083984 ps
CPU time 1.19 seconds
Started Aug 09 07:51:52 PM PDT 24
Finished Aug 09 07:51:53 PM PDT 24
Peak memory 219472 kb
Host smart-f763a57b-0060-4c30-b800-95626bb96b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721125610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2721125610
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_genbits.1863092312
Short name T111
Test name
Test status
Simulation time 51130540 ps
CPU time 1.71 seconds
Started Aug 09 07:51:53 PM PDT 24
Finished Aug 09 07:51:55 PM PDT 24
Peak memory 215288 kb
Host smart-59b7fe5e-0e40-449a-a005-0c4ee1d52555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863092312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1863092312
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2391273989
Short name T925
Test name
Test status
Simulation time 25184081 ps
CPU time 1.23 seconds
Started Aug 09 07:52:02 PM PDT 24
Finished Aug 09 07:52:04 PM PDT 24
Peak memory 219720 kb
Host smart-c408905c-8650-44fd-8ad0-88e06fe5b93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391273989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2391273989
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2904783448
Short name T149
Test name
Test status
Simulation time 26397837 ps
CPU time 1.43 seconds
Started Aug 09 07:51:53 PM PDT 24
Finished Aug 09 07:51:55 PM PDT 24
Peak memory 229668 kb
Host smart-da165035-ecd7-4401-8589-0d96cca8d25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904783448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2904783448
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2093850970
Short name T412
Test name
Test status
Simulation time 49070299 ps
CPU time 1.96 seconds
Started Aug 09 07:51:53 PM PDT 24
Finished Aug 09 07:51:55 PM PDT 24
Peak memory 220020 kb
Host smart-d772b986-e0c5-465e-85c9-b3bbfc451c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093850970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2093850970
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2740179961
Short name T774
Test name
Test status
Simulation time 96892513 ps
CPU time 1.26 seconds
Started Aug 09 07:51:59 PM PDT 24
Finished Aug 09 07:52:00 PM PDT 24
Peak memory 220736 kb
Host smart-3250c3bf-9711-4d7c-b5c1-5421a219f61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740179961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2740179961
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.3847617574
Short name T481
Test name
Test status
Simulation time 25093278 ps
CPU time 1.05 seconds
Started Aug 09 07:51:53 PM PDT 24
Finished Aug 09 07:51:54 PM PDT 24
Peak memory 220164 kb
Host smart-8a784954-a080-4cf2-b1ad-5355e5678dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847617574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3847617574
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3308180943
Short name T345
Test name
Test status
Simulation time 54390156 ps
CPU time 1.77 seconds
Started Aug 09 07:51:58 PM PDT 24
Finished Aug 09 07:51:59 PM PDT 24
Peak memory 220128 kb
Host smart-2934a1cc-9369-4065-9871-26324411467c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308180943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3308180943
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3874537492
Short name T587
Test name
Test status
Simulation time 69821351 ps
CPU time 1.2 seconds
Started Aug 09 07:52:01 PM PDT 24
Finished Aug 09 07:52:03 PM PDT 24
Peak memory 219760 kb
Host smart-9220a3f4-ae9c-486f-a717-b06d286177a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874537492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3874537492
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.2796705003
Short name T838
Test name
Test status
Simulation time 24480019 ps
CPU time 0.95 seconds
Started Aug 09 07:51:52 PM PDT 24
Finished Aug 09 07:51:53 PM PDT 24
Peak memory 218760 kb
Host smart-4fcbe25d-fc7c-4634-827e-ab031d02a210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796705003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2796705003
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.939010830
Short name T338
Test name
Test status
Simulation time 73366171 ps
CPU time 1.55 seconds
Started Aug 09 07:52:09 PM PDT 24
Finished Aug 09 07:52:11 PM PDT 24
Peak memory 218548 kb
Host smart-5c32cab4-e660-4ebc-9de8-616bd734f13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939010830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.939010830
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.288880900
Short name T405
Test name
Test status
Simulation time 31850426 ps
CPU time 0.91 seconds
Started Aug 09 07:51:56 PM PDT 24
Finished Aug 09 07:51:57 PM PDT 24
Peak memory 219692 kb
Host smart-08788c0a-5ea9-470b-a2a8-b670b961518e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288880900 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.288880900
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.975882853
Short name T556
Test name
Test status
Simulation time 66905996 ps
CPU time 1.1 seconds
Started Aug 09 07:51:56 PM PDT 24
Finished Aug 09 07:51:58 PM PDT 24
Peak memory 218992 kb
Host smart-8d2422ff-cc92-4155-9452-a418dcf147f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975882853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.975882853
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.214416168
Short name T880
Test name
Test status
Simulation time 228844218 ps
CPU time 1.13 seconds
Started Aug 09 07:51:50 PM PDT 24
Finished Aug 09 07:51:51 PM PDT 24
Peak memory 219660 kb
Host smart-8da547d6-0041-44fb-84e5-9d84c05b578c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214416168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.214416168
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert.3670609597
Short name T622
Test name
Test status
Simulation time 37838995 ps
CPU time 1.11 seconds
Started Aug 09 07:50:52 PM PDT 24
Finished Aug 09 07:50:53 PM PDT 24
Peak memory 218572 kb
Host smart-2bb578e9-ec00-4849-a071-33a27d54884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670609597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3670609597
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2789724360
Short name T762
Test name
Test status
Simulation time 125532695 ps
CPU time 0.95 seconds
Started Aug 09 07:50:50 PM PDT 24
Finished Aug 09 07:50:52 PM PDT 24
Peak memory 215264 kb
Host smart-e9f3f652-b2e9-4cf8-ad38-f72849a98f54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789724360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2789724360
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1452616263
Short name T935
Test name
Test status
Simulation time 46460518 ps
CPU time 0.82 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 07:50:55 PM PDT 24
Peak memory 217996 kb
Host smart-fa21a553-647d-45e8-83c0-b286f6fed64c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452616263 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1452616263
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.4082243490
Short name T474
Test name
Test status
Simulation time 38548696 ps
CPU time 1.03 seconds
Started Aug 09 07:50:52 PM PDT 24
Finished Aug 09 07:50:54 PM PDT 24
Peak memory 218476 kb
Host smart-7174bda9-c0fb-4cce-a19e-c31bf3fd51d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082243490 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.4082243490
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.4263665342
Short name T708
Test name
Test status
Simulation time 18225205 ps
CPU time 1.11 seconds
Started Aug 09 07:50:52 PM PDT 24
Finished Aug 09 07:50:53 PM PDT 24
Peak memory 224132 kb
Host smart-3eb3c73a-d8fe-4aa4-b2d5-c9030fc13832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263665342 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.4263665342
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.4223463228
Short name T472
Test name
Test status
Simulation time 72174020 ps
CPU time 1.01 seconds
Started Aug 09 07:50:56 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 217316 kb
Host smart-73327fc2-04c4-430a-9e74-808378449f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223463228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.4223463228
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1890491989
Short name T35
Test name
Test status
Simulation time 24072926 ps
CPU time 1.02 seconds
Started Aug 09 07:50:50 PM PDT 24
Finished Aug 09 07:50:51 PM PDT 24
Peak memory 215976 kb
Host smart-a828b666-ed5f-4d6d-a74d-e2d0206b9fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890491989 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1890491989
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2783622487
Short name T949
Test name
Test status
Simulation time 27602347 ps
CPU time 0.92 seconds
Started Aug 09 07:50:50 PM PDT 24
Finished Aug 09 07:50:52 PM PDT 24
Peak memory 207052 kb
Host smart-f24af378-c709-4549-ad1b-aada4541dbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783622487 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2783622487
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1043915621
Short name T894
Test name
Test status
Simulation time 46015548 ps
CPU time 0.89 seconds
Started Aug 09 07:50:52 PM PDT 24
Finished Aug 09 07:50:53 PM PDT 24
Peak memory 215240 kb
Host smart-c3d2cff3-7716-40f6-949f-d0cb2b4760e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043915621 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1043915621
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.4034079744
Short name T742
Test name
Test status
Simulation time 947294287 ps
CPU time 3.65 seconds
Started Aug 09 07:50:53 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 215376 kb
Host smart-f57f6919-1b35-49a2-bb0d-0c2298fc5322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034079744 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.4034079744
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3026099947
Short name T527
Test name
Test status
Simulation time 150766279853 ps
CPU time 2067.36 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 08:25:22 PM PDT 24
Peak memory 228272 kb
Host smart-662790bc-ffa0-4573-825c-0da4e675d2d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026099947 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3026099947
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1661449281
Short name T769
Test name
Test status
Simulation time 27151194 ps
CPU time 1.28 seconds
Started Aug 09 07:52:06 PM PDT 24
Finished Aug 09 07:52:07 PM PDT 24
Peak memory 218680 kb
Host smart-3fa10b1e-318e-4749-8702-19249fc0eebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661449281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1661449281
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.259988401
Short name T181
Test name
Test status
Simulation time 81117380 ps
CPU time 0.86 seconds
Started Aug 09 07:51:56 PM PDT 24
Finished Aug 09 07:51:57 PM PDT 24
Peak memory 218736 kb
Host smart-3575e2e3-1dc0-483a-8034-0323af28e936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259988401 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.259988401
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.4139450351
Short name T901
Test name
Test status
Simulation time 125557833 ps
CPU time 1.63 seconds
Started Aug 09 07:51:52 PM PDT 24
Finished Aug 09 07:51:54 PM PDT 24
Peak memory 218684 kb
Host smart-ff33836a-2cea-4b7a-a406-2bae91b2563b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139450351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.4139450351
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.3845582825
Short name T944
Test name
Test status
Simulation time 36105786 ps
CPU time 1.05 seconds
Started Aug 09 07:52:08 PM PDT 24
Finished Aug 09 07:52:09 PM PDT 24
Peak memory 219644 kb
Host smart-1f7a37c9-3354-40dd-be04-8fe544e80c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845582825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.3845582825
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.947509032
Short name T232
Test name
Test status
Simulation time 22317201 ps
CPU time 0.92 seconds
Started Aug 09 07:51:56 PM PDT 24
Finished Aug 09 07:51:57 PM PDT 24
Peak memory 218796 kb
Host smart-c1f5e180-b0a0-499b-b086-234d237f3b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947509032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.947509032
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3302979678
Short name T430
Test name
Test status
Simulation time 55406240 ps
CPU time 1.41 seconds
Started Aug 09 07:52:12 PM PDT 24
Finished Aug 09 07:52:13 PM PDT 24
Peak memory 218712 kb
Host smart-443967c7-9b65-4194-8e19-5b052c9dd373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302979678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3302979678
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.915434748
Short name T600
Test name
Test status
Simulation time 81420436 ps
CPU time 1.15 seconds
Started Aug 09 07:52:01 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 219824 kb
Host smart-d96339f5-4884-4eaf-85fc-8206839e77b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915434748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.915434748
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2750820961
Short name T222
Test name
Test status
Simulation time 31658197 ps
CPU time 1.17 seconds
Started Aug 09 07:52:07 PM PDT 24
Finished Aug 09 07:52:08 PM PDT 24
Peak memory 219816 kb
Host smart-54a980b1-42c5-47d4-a11a-85047325334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750820961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2750820961
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.585270760
Short name T700
Test name
Test status
Simulation time 44389396 ps
CPU time 1.28 seconds
Started Aug 09 07:52:03 PM PDT 24
Finished Aug 09 07:52:04 PM PDT 24
Peak memory 218884 kb
Host smart-bea5ce3f-ed21-4a51-bc08-d847331898c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585270760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.585270760
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.146125708
Short name T531
Test name
Test status
Simulation time 284038002 ps
CPU time 1.17 seconds
Started Aug 09 07:52:05 PM PDT 24
Finished Aug 09 07:52:06 PM PDT 24
Peak memory 221444 kb
Host smart-6d1a2169-226d-4b50-bd67-f87ecf788071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146125708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.146125708
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1083491724
Short name T215
Test name
Test status
Simulation time 23866344 ps
CPU time 1.21 seconds
Started Aug 09 07:52:06 PM PDT 24
Finished Aug 09 07:52:07 PM PDT 24
Peak memory 218884 kb
Host smart-436c2be0-f45e-40f3-bbdb-c42c1f0d7a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083491724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1083491724
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2126434804
Short name T969
Test name
Test status
Simulation time 85415606 ps
CPU time 1.08 seconds
Started Aug 09 07:52:05 PM PDT 24
Finished Aug 09 07:52:06 PM PDT 24
Peak memory 217440 kb
Host smart-7f61399f-7069-4280-b872-f63445b1e872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126434804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2126434804
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1502900072
Short name T291
Test name
Test status
Simulation time 112385669 ps
CPU time 1.09 seconds
Started Aug 09 07:52:09 PM PDT 24
Finished Aug 09 07:52:11 PM PDT 24
Peak memory 218304 kb
Host smart-868d8120-2255-4780-bbb4-a27f0ed4d396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502900072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1502900072
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1322860934
Short name T786
Test name
Test status
Simulation time 21329285 ps
CPU time 1 seconds
Started Aug 09 07:52:06 PM PDT 24
Finished Aug 09 07:52:07 PM PDT 24
Peak memory 219912 kb
Host smart-680b4c30-271a-48c7-81b9-9c07a603dc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322860934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1322860934
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2811833032
Short name T325
Test name
Test status
Simulation time 50174236 ps
CPU time 1.23 seconds
Started Aug 09 07:51:59 PM PDT 24
Finished Aug 09 07:52:01 PM PDT 24
Peak memory 219924 kb
Host smart-1b9d4284-6aa3-4be2-a284-13dd0a5eef0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811833032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2811833032
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3631842960
Short name T860
Test name
Test status
Simulation time 24091240 ps
CPU time 1.3 seconds
Started Aug 09 07:52:09 PM PDT 24
Finished Aug 09 07:52:11 PM PDT 24
Peak memory 224120 kb
Host smart-c814ab20-4368-488d-b3c3-b64b4668ea70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631842960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3631842960
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.186716894
Short name T341
Test name
Test status
Simulation time 42637398 ps
CPU time 1.52 seconds
Started Aug 09 07:52:00 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 218736 kb
Host smart-4eec91f0-db8d-4635-acb1-b4b8ab02a4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186716894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.186716894
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.290185347
Short name T183
Test name
Test status
Simulation time 69932628 ps
CPU time 1.12 seconds
Started Aug 09 07:52:01 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 219448 kb
Host smart-1ce8783f-9a7b-4a73-8aa7-8b36e686f90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290185347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.290185347
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1085589773
Short name T231
Test name
Test status
Simulation time 28628487 ps
CPU time 0.88 seconds
Started Aug 09 07:52:03 PM PDT 24
Finished Aug 09 07:52:04 PM PDT 24
Peak memory 219624 kb
Host smart-6bd8f914-05cc-42a4-a86c-30cc08fba8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085589773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1085589773
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2710115258
Short name T581
Test name
Test status
Simulation time 68469556 ps
CPU time 1.19 seconds
Started Aug 09 07:52:09 PM PDT 24
Finished Aug 09 07:52:11 PM PDT 24
Peak memory 219220 kb
Host smart-b5b1b81b-3ac6-486f-a6c4-7f33cee39ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710115258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2710115258
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1916937479
Short name T713
Test name
Test status
Simulation time 29348670 ps
CPU time 1.37 seconds
Started Aug 09 07:52:04 PM PDT 24
Finished Aug 09 07:52:05 PM PDT 24
Peak memory 219684 kb
Host smart-4e7b810c-0775-45b4-9527-4731fb1a7958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916937479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1916937479
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3536290137
Short name T192
Test name
Test status
Simulation time 31806750 ps
CPU time 0.87 seconds
Started Aug 09 07:51:59 PM PDT 24
Finished Aug 09 07:52:00 PM PDT 24
Peak memory 218540 kb
Host smart-cefd8a0b-9386-4174-b5ad-61cc9d6a0122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536290137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3536290137
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1531662061
Short name T920
Test name
Test status
Simulation time 33793608 ps
CPU time 1.42 seconds
Started Aug 09 07:52:08 PM PDT 24
Finished Aug 09 07:52:10 PM PDT 24
Peak memory 218680 kb
Host smart-b90155a5-4d61-4656-b738-3164c23064fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531662061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1531662061
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.3690098401
Short name T991
Test name
Test status
Simulation time 53070603 ps
CPU time 1.21 seconds
Started Aug 09 07:52:00 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 219200 kb
Host smart-441d5299-12a6-4b99-8361-d1f0fc1aaa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690098401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3690098401
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1310689662
Short name T59
Test name
Test status
Simulation time 45275252 ps
CPU time 1.17 seconds
Started Aug 09 07:52:01 PM PDT 24
Finished Aug 09 07:52:03 PM PDT 24
Peak memory 229924 kb
Host smart-b6741bed-a12c-4521-a88a-b2e01a7875da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310689662 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1310689662
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.118971059
Short name T426
Test name
Test status
Simulation time 179913816 ps
CPU time 2.44 seconds
Started Aug 09 07:52:02 PM PDT 24
Finished Aug 09 07:52:04 PM PDT 24
Peak memory 218652 kb
Host smart-0343a570-71e8-44ef-b99b-79c7cc7f772c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118971059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.118971059
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.85360853
Short name T167
Test name
Test status
Simulation time 23539104 ps
CPU time 1.18 seconds
Started Aug 09 07:52:02 PM PDT 24
Finished Aug 09 07:52:04 PM PDT 24
Peak memory 218644 kb
Host smart-fdc67330-83f8-44d3-a405-9a4a11c9dfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85360853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.85360853
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3383398055
Short name T92
Test name
Test status
Simulation time 20280124 ps
CPU time 1.06 seconds
Started Aug 09 07:52:08 PM PDT 24
Finished Aug 09 07:52:09 PM PDT 24
Peak memory 218640 kb
Host smart-75fe4ba9-6c2e-47e9-b565-90c5914bfcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383398055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3383398055
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2241917752
Short name T605
Test name
Test status
Simulation time 138324785 ps
CPU time 2.27 seconds
Started Aug 09 07:51:59 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 220184 kb
Host smart-e7285951-10e6-436f-836d-221d86817233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241917752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2241917752
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2515504842
Short name T196
Test name
Test status
Simulation time 35095184 ps
CPU time 1.2 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 07:50:56 PM PDT 24
Peak memory 218416 kb
Host smart-e596c10d-2934-4b15-9f9d-c6da0b1416df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515504842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2515504842
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.4155829115
Short name T518
Test name
Test status
Simulation time 15777187 ps
CPU time 0.98 seconds
Started Aug 09 07:50:55 PM PDT 24
Finished Aug 09 07:50:56 PM PDT 24
Peak memory 206848 kb
Host smart-e0bcaaca-017f-4a6d-92ea-feb3b5619079
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155829115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4155829115
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3984062900
Short name T227
Test name
Test status
Simulation time 25882889 ps
CPU time 0.87 seconds
Started Aug 09 07:50:57 PM PDT 24
Finished Aug 09 07:50:58 PM PDT 24
Peak memory 216472 kb
Host smart-4eff6dd4-9240-4386-98e6-a908de72f4ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984062900 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3984062900
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3131448983
Short name T362
Test name
Test status
Simulation time 28972946 ps
CPU time 1.04 seconds
Started Aug 09 07:50:56 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 218452 kb
Host smart-3193d915-9197-490f-90da-c6f53d8c9241
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131448983 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3131448983
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2610207559
Short name T717
Test name
Test status
Simulation time 26406428 ps
CPU time 0.95 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 07:50:55 PM PDT 24
Peak memory 218884 kb
Host smart-cce3190c-8ef0-4110-ba56-99bc320fb240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610207559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2610207559
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.4046452275
Short name T993
Test name
Test status
Simulation time 49549997 ps
CPU time 1.58 seconds
Started Aug 09 07:51:01 PM PDT 24
Finished Aug 09 07:51:03 PM PDT 24
Peak memory 218504 kb
Host smart-71d8f541-942f-4ae7-92a5-b063881f4ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046452275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.4046452275
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2566727612
Short name T585
Test name
Test status
Simulation time 28291418 ps
CPU time 1 seconds
Started Aug 09 07:50:57 PM PDT 24
Finished Aug 09 07:50:58 PM PDT 24
Peak memory 215496 kb
Host smart-299ece61-03ed-4b9b-b239-7bd62a7b5a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566727612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2566727612
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3846687960
Short name T674
Test name
Test status
Simulation time 22293677 ps
CPU time 0.91 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 07:50:55 PM PDT 24
Peak memory 207076 kb
Host smart-e36572bf-5605-4a0f-8006-7d02f0ec8044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846687960 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3846687960
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.463433702
Short name T721
Test name
Test status
Simulation time 19320975 ps
CPU time 0.99 seconds
Started Aug 09 07:50:53 PM PDT 24
Finished Aug 09 07:50:55 PM PDT 24
Peak memory 215244 kb
Host smart-b6c0f2c0-c9dd-48c8-abb2-1ee8bd8f3df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463433702 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.463433702
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1430708519
Short name T406
Test name
Test status
Simulation time 162816709 ps
CPU time 2.23 seconds
Started Aug 09 07:50:57 PM PDT 24
Finished Aug 09 07:50:59 PM PDT 24
Peak memory 215308 kb
Host smart-c85e3fd1-5eea-469c-aa4c-36f28d9d7a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430708519 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1430708519
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1930417545
Short name T959
Test name
Test status
Simulation time 62539422468 ps
CPU time 1375.67 seconds
Started Aug 09 07:50:55 PM PDT 24
Finished Aug 09 08:13:50 PM PDT 24
Peak memory 222160 kb
Host smart-67b1d36b-8334-4a48-aeef-ae4c8b3b77cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930417545 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1930417545
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2480958834
Short name T851
Test name
Test status
Simulation time 19334364 ps
CPU time 1.03 seconds
Started Aug 09 07:52:10 PM PDT 24
Finished Aug 09 07:52:11 PM PDT 24
Peak memory 218996 kb
Host smart-c5b32b27-7f50-430b-8c87-b29785dcca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480958834 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2480958834
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.552890146
Short name T625
Test name
Test status
Simulation time 53691952 ps
CPU time 1.43 seconds
Started Aug 09 07:52:01 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 218432 kb
Host smart-aca64af6-14b2-4a14-81bd-3028be1a55f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552890146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.552890146
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.474960998
Short name T129
Test name
Test status
Simulation time 48293891 ps
CPU time 1.23 seconds
Started Aug 09 07:52:03 PM PDT 24
Finished Aug 09 07:52:04 PM PDT 24
Peak memory 220604 kb
Host smart-3e6f622d-ea2c-4608-af37-e30f18475b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474960998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.474960998
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2498465032
Short name T16
Test name
Test status
Simulation time 29774870 ps
CPU time 1.07 seconds
Started Aug 09 07:52:00 PM PDT 24
Finished Aug 09 07:52:01 PM PDT 24
Peak memory 224148 kb
Host smart-cd4b08e6-3385-470f-bf06-d5834a70105d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498465032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2498465032
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1250066086
Short name T676
Test name
Test status
Simulation time 29836100 ps
CPU time 1.23 seconds
Started Aug 09 07:51:58 PM PDT 24
Finished Aug 09 07:51:59 PM PDT 24
Peak memory 217376 kb
Host smart-241f360a-9420-481a-b5fd-e8da3a2c5464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250066086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1250066086
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1635369010
Short name T173
Test name
Test status
Simulation time 30419829 ps
CPU time 1.41 seconds
Started Aug 09 07:52:00 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 220168 kb
Host smart-9b6ad29f-ac56-485b-a3c8-1c83abf3dbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635369010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1635369010
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.2700922278
Short name T182
Test name
Test status
Simulation time 34027044 ps
CPU time 1.01 seconds
Started Aug 09 07:52:02 PM PDT 24
Finished Aug 09 07:52:03 PM PDT 24
Peak memory 224000 kb
Host smart-e11d2d64-0c0e-4a98-b109-7511172fe599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700922278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2700922278
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.341067009
Short name T818
Test name
Test status
Simulation time 72663944 ps
CPU time 1.4 seconds
Started Aug 09 07:52:01 PM PDT 24
Finished Aug 09 07:52:02 PM PDT 24
Peak memory 218360 kb
Host smart-536700ca-7df6-4c17-bea5-056beceea02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341067009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.341067009
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2417915575
Short name T814
Test name
Test status
Simulation time 242567011 ps
CPU time 1.32 seconds
Started Aug 09 07:52:00 PM PDT 24
Finished Aug 09 07:52:01 PM PDT 24
Peak memory 219528 kb
Host smart-a145de82-eaed-4b47-99e7-ee2f914d53ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417915575 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2417915575
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2218886861
Short name T917
Test name
Test status
Simulation time 21344266 ps
CPU time 1.1 seconds
Started Aug 09 07:52:08 PM PDT 24
Finished Aug 09 07:52:09 PM PDT 24
Peak memory 224096 kb
Host smart-8ebabb40-6f98-4762-a1cd-143f3fc15f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218886861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2218886861
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.377044992
Short name T97
Test name
Test status
Simulation time 59013858 ps
CPU time 1.42 seconds
Started Aug 09 07:52:07 PM PDT 24
Finished Aug 09 07:52:09 PM PDT 24
Peak memory 218532 kb
Host smart-92903890-4205-4d19-9aa5-39873d745e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377044992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.377044992
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.171871382
Short name T205
Test name
Test status
Simulation time 45277416 ps
CPU time 1.17 seconds
Started Aug 09 07:52:11 PM PDT 24
Finished Aug 09 07:52:12 PM PDT 24
Peak memory 218732 kb
Host smart-7dccaf49-82d4-478b-9309-9823a621d8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171871382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.171871382
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2509192818
Short name T903
Test name
Test status
Simulation time 24491554 ps
CPU time 0.95 seconds
Started Aug 09 07:52:09 PM PDT 24
Finished Aug 09 07:52:10 PM PDT 24
Peak memory 219596 kb
Host smart-a8a193c7-f1e0-43b9-8fec-64ca5163a888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509192818 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2509192818
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3867338725
Short name T565
Test name
Test status
Simulation time 94458387 ps
CPU time 1.24 seconds
Started Aug 09 07:52:10 PM PDT 24
Finished Aug 09 07:52:16 PM PDT 24
Peak memory 219084 kb
Host smart-2ec75528-c273-44be-9bf2-8cfbdf28d385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867338725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3867338725
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.2045984592
Short name T101
Test name
Test status
Simulation time 32290387 ps
CPU time 1.28 seconds
Started Aug 09 07:52:07 PM PDT 24
Finished Aug 09 07:52:08 PM PDT 24
Peak memory 215548 kb
Host smart-e2eba0f0-4011-4564-a5a4-2fd2f93d8468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045984592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2045984592
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3017100313
Short name T521
Test name
Test status
Simulation time 19046372 ps
CPU time 1.24 seconds
Started Aug 09 07:52:04 PM PDT 24
Finished Aug 09 07:52:06 PM PDT 24
Peak memory 224156 kb
Host smart-94664b3b-6707-49c7-950f-1f297ae8e5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017100313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3017100313
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.945068264
Short name T543
Test name
Test status
Simulation time 97601339 ps
CPU time 2.29 seconds
Started Aug 09 07:52:06 PM PDT 24
Finished Aug 09 07:52:09 PM PDT 24
Peak memory 220004 kb
Host smart-d42e89de-b7d4-428a-92cc-d1b804fb5dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945068264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.945068264
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.4122892497
Short name T541
Test name
Test status
Simulation time 26027412 ps
CPU time 1.14 seconds
Started Aug 09 07:52:05 PM PDT 24
Finished Aug 09 07:52:06 PM PDT 24
Peak memory 220704 kb
Host smart-486b8266-dd86-478b-807d-09483bc60a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122892497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.4122892497
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.2879933994
Short name T419
Test name
Test status
Simulation time 22968460 ps
CPU time 0.96 seconds
Started Aug 09 07:52:11 PM PDT 24
Finished Aug 09 07:52:12 PM PDT 24
Peak memory 218736 kb
Host smart-cb5f2546-5c06-4484-ac0e-f795020e15d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879933994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2879933994
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3497286312
Short name T905
Test name
Test status
Simulation time 79301834 ps
CPU time 1.54 seconds
Started Aug 09 07:52:06 PM PDT 24
Finished Aug 09 07:52:08 PM PDT 24
Peak memory 218788 kb
Host smart-95bc8275-d956-4d06-857a-a9207305e4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497286312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3497286312
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2473763665
Short name T9
Test name
Test status
Simulation time 23870621 ps
CPU time 1.21 seconds
Started Aug 09 07:52:08 PM PDT 24
Finished Aug 09 07:52:09 PM PDT 24
Peak memory 220512 kb
Host smart-2a9ae09e-c4a2-4301-9649-24701f2b6183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473763665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2473763665
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.766012803
Short name T180
Test name
Test status
Simulation time 22234933 ps
CPU time 1.01 seconds
Started Aug 09 07:52:06 PM PDT 24
Finished Aug 09 07:52:13 PM PDT 24
Peak memory 218808 kb
Host smart-547dc018-3782-4163-8649-6765212595b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766012803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.766012803
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2668592047
Short name T724
Test name
Test status
Simulation time 45733456 ps
CPU time 1.44 seconds
Started Aug 09 07:52:12 PM PDT 24
Finished Aug 09 07:52:13 PM PDT 24
Peak memory 217244 kb
Host smart-f125c317-3363-41f2-bb0b-a8939911dc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668592047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2668592047
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.2711184010
Short name T135
Test name
Test status
Simulation time 44576863 ps
CPU time 1.21 seconds
Started Aug 09 07:52:10 PM PDT 24
Finished Aug 09 07:52:11 PM PDT 24
Peak memory 220404 kb
Host smart-04da8956-4cc2-4e78-a41c-6a84d5f13cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711184010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.2711184010
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.3603325841
Short name T174
Test name
Test status
Simulation time 19729916 ps
CPU time 1.05 seconds
Started Aug 09 07:52:26 PM PDT 24
Finished Aug 09 07:52:27 PM PDT 24
Peak memory 218916 kb
Host smart-6fa3f03a-7304-4b64-841a-9f733b708bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603325841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3603325841
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3694554016
Short name T546
Test name
Test status
Simulation time 52579421 ps
CPU time 1.25 seconds
Started Aug 09 07:52:06 PM PDT 24
Finished Aug 09 07:52:07 PM PDT 24
Peak memory 218624 kb
Host smart-127a6082-8136-4aeb-a01f-74869e855969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694554016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3694554016
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.4027253491
Short name T734
Test name
Test status
Simulation time 58043884 ps
CPU time 1.06 seconds
Started Aug 09 07:52:08 PM PDT 24
Finished Aug 09 07:52:09 PM PDT 24
Peak memory 219664 kb
Host smart-16781cb7-5113-4dbf-8fec-05e29596355d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027253491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.4027253491
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.4164804485
Short name T653
Test name
Test status
Simulation time 19386968 ps
CPU time 1.1 seconds
Started Aug 09 07:52:05 PM PDT 24
Finished Aug 09 07:52:06 PM PDT 24
Peak memory 218928 kb
Host smart-2ab87e82-eefe-461d-b5d1-33cf9fed4ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164804485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.4164804485
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.854607611
Short name T887
Test name
Test status
Simulation time 96792862 ps
CPU time 1.19 seconds
Started Aug 09 07:52:12 PM PDT 24
Finished Aug 09 07:52:13 PM PDT 24
Peak memory 217476 kb
Host smart-c4923ae4-ccf9-4380-8871-2e3731142dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854607611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.854607611
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2570326907
Short name T299
Test name
Test status
Simulation time 72863487 ps
CPU time 1.14 seconds
Started Aug 09 07:50:55 PM PDT 24
Finished Aug 09 07:50:56 PM PDT 24
Peak memory 218440 kb
Host smart-9687167a-c907-42f6-997e-b17ec68d779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570326907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2570326907
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3933861059
Short name T896
Test name
Test status
Simulation time 219907421 ps
CPU time 0.91 seconds
Started Aug 09 07:50:58 PM PDT 24
Finished Aug 09 07:50:59 PM PDT 24
Peak memory 206784 kb
Host smart-b22c649b-50d6-4cc1-9bda-5b20d4cde261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933861059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3933861059
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.747410430
Short name T453
Test name
Test status
Simulation time 27047637 ps
CPU time 0.84 seconds
Started Aug 09 07:50:56 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 215364 kb
Host smart-e4653858-29ec-4e17-97ae-f99f5a18f1c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747410430 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.747410430
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1255089735
Short name T976
Test name
Test status
Simulation time 46330681 ps
CPU time 1.08 seconds
Started Aug 09 07:50:57 PM PDT 24
Finished Aug 09 07:50:58 PM PDT 24
Peak memory 218628 kb
Host smart-35ba7636-2215-40f5-8d8e-ba04618137d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255089735 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1255089735
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1842210828
Short name T134
Test name
Test status
Simulation time 172683936 ps
CPU time 0.97 seconds
Started Aug 09 07:50:57 PM PDT 24
Finished Aug 09 07:50:58 PM PDT 24
Peak memory 220840 kb
Host smart-62633e02-9221-4c6f-93bf-3c24dc769436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842210828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1842210828
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2536402537
Short name T29
Test name
Test status
Simulation time 48226869 ps
CPU time 1.62 seconds
Started Aug 09 07:50:55 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 218488 kb
Host smart-e18dfa23-8c2c-4879-b009-1abdb8d237dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536402537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2536402537
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2825364875
Short name T821
Test name
Test status
Simulation time 32591384 ps
CPU time 1.02 seconds
Started Aug 09 07:51:01 PM PDT 24
Finished Aug 09 07:51:02 PM PDT 24
Peak memory 224108 kb
Host smart-815155c4-a1eb-4e03-aec4-f8c320e3e365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825364875 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2825364875
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2498930937
Short name T921
Test name
Test status
Simulation time 17573337 ps
CPU time 1.02 seconds
Started Aug 09 07:50:56 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 207120 kb
Host smart-0d2ceea1-1b37-46c6-8898-c0bd56e96010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498930937 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2498930937
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2931411733
Short name T588
Test name
Test status
Simulation time 16211176 ps
CPU time 0.98 seconds
Started Aug 09 07:51:02 PM PDT 24
Finished Aug 09 07:51:03 PM PDT 24
Peak memory 215332 kb
Host smart-a9f6a8e4-ee92-4500-96a1-f8511e22df8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931411733 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2931411733
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1232903862
Short name T425
Test name
Test status
Simulation time 319194394 ps
CPU time 3.47 seconds
Started Aug 09 07:50:53 PM PDT 24
Finished Aug 09 07:50:56 PM PDT 24
Peak memory 217372 kb
Host smart-8fd5e3a5-b9fa-4e8a-a78e-97404ed93314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232903862 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1232903862
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2429504675
Short name T408
Test name
Test status
Simulation time 9297905715 ps
CPU time 124.8 seconds
Started Aug 09 07:50:59 PM PDT 24
Finished Aug 09 07:53:04 PM PDT 24
Peak memory 218880 kb
Host smart-606cb003-5af0-4adb-9d3d-9584eb323bf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429504675 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2429504675
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2050129974
Short name T321
Test name
Test status
Simulation time 32350473 ps
CPU time 1.32 seconds
Started Aug 09 07:52:06 PM PDT 24
Finished Aug 09 07:52:07 PM PDT 24
Peak memory 215724 kb
Host smart-61442447-f252-470c-aebb-1304193d0cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050129974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2050129974
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3895247375
Short name T155
Test name
Test status
Simulation time 46022508 ps
CPU time 1.07 seconds
Started Aug 09 07:52:19 PM PDT 24
Finished Aug 09 07:52:20 PM PDT 24
Peak memory 229720 kb
Host smart-fdccf401-a020-47d5-b5ae-2bd99f33492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895247375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3895247375
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3334944540
Short name T846
Test name
Test status
Simulation time 95102142 ps
CPU time 1.56 seconds
Started Aug 09 07:52:21 PM PDT 24
Finished Aug 09 07:52:23 PM PDT 24
Peak memory 219044 kb
Host smart-17f7d41a-7af7-4b66-acad-37943e251adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334944540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3334944540
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.919141674
Short name T414
Test name
Test status
Simulation time 71537411 ps
CPU time 1.13 seconds
Started Aug 09 07:52:09 PM PDT 24
Finished Aug 09 07:52:10 PM PDT 24
Peak memory 219544 kb
Host smart-51471d4b-c599-4c26-82aa-4d5958314255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919141674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.919141674
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.4118945021
Short name T147
Test name
Test status
Simulation time 67814381 ps
CPU time 1.18 seconds
Started Aug 09 07:52:09 PM PDT 24
Finished Aug 09 07:52:10 PM PDT 24
Peak memory 229876 kb
Host smart-60e33aaa-a1bb-4107-8a70-bac8d38e4407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118945021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.4118945021
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.935241987
Short name T253
Test name
Test status
Simulation time 45492535 ps
CPU time 1.51 seconds
Started Aug 09 07:52:07 PM PDT 24
Finished Aug 09 07:52:08 PM PDT 24
Peak memory 218392 kb
Host smart-3f00965c-fb57-4d7c-8260-e036f51007f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935241987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.935241987
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.213308682
Short name T500
Test name
Test status
Simulation time 76457128 ps
CPU time 1.22 seconds
Started Aug 09 07:52:05 PM PDT 24
Finished Aug 09 07:52:07 PM PDT 24
Peak memory 219432 kb
Host smart-43d7be61-4db1-474c-b65b-e301776809f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213308682 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.213308682
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.494385086
Short name T148
Test name
Test status
Simulation time 27073733 ps
CPU time 1.41 seconds
Started Aug 09 07:52:25 PM PDT 24
Finished Aug 09 07:52:27 PM PDT 24
Peak memory 229920 kb
Host smart-0fa2ae9d-57e1-48f1-8ddb-581f879c86e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494385086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.494385086
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2245783818
Short name T448
Test name
Test status
Simulation time 60551266 ps
CPU time 1.35 seconds
Started Aug 09 07:52:09 PM PDT 24
Finished Aug 09 07:52:11 PM PDT 24
Peak memory 218396 kb
Host smart-94e24a81-882a-40fe-9593-78746fa69157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245783818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2245783818
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.4156616599
Short name T200
Test name
Test status
Simulation time 73658282 ps
CPU time 1.2 seconds
Started Aug 09 07:52:06 PM PDT 24
Finished Aug 09 07:52:08 PM PDT 24
Peak memory 220024 kb
Host smart-bae917cf-e5c3-4d3d-99a5-64fb4d3b9c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156616599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.4156616599
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2285317822
Short name T451
Test name
Test status
Simulation time 18224738 ps
CPU time 1.09 seconds
Started Aug 09 07:52:10 PM PDT 24
Finished Aug 09 07:52:11 PM PDT 24
Peak memory 218572 kb
Host smart-f6a605ee-4b96-4e07-8613-c62ecbd7c081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285317822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2285317822
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3254257015
Short name T409
Test name
Test status
Simulation time 106966806 ps
CPU time 1.54 seconds
Started Aug 09 07:52:10 PM PDT 24
Finished Aug 09 07:52:13 PM PDT 24
Peak memory 218840 kb
Host smart-678ac06a-42d1-48a6-94de-cd0955938db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254257015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3254257015
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.245582210
Short name T668
Test name
Test status
Simulation time 55786356 ps
CPU time 1.13 seconds
Started Aug 09 07:52:10 PM PDT 24
Finished Aug 09 07:52:12 PM PDT 24
Peak memory 219656 kb
Host smart-59e64dd9-767a-40fc-ba2b-06538b518cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245582210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.245582210
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1698075119
Short name T169
Test name
Test status
Simulation time 26795525 ps
CPU time 1.03 seconds
Started Aug 09 07:52:08 PM PDT 24
Finished Aug 09 07:52:10 PM PDT 24
Peak memory 219952 kb
Host smart-1752d2be-7f62-45a0-8a66-4c20f99dfcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698075119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1698075119
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2210367902
Short name T50
Test name
Test status
Simulation time 33999904 ps
CPU time 1.56 seconds
Started Aug 09 07:52:12 PM PDT 24
Finished Aug 09 07:52:13 PM PDT 24
Peak memory 218660 kb
Host smart-510bdfcb-11b0-483f-b369-0018b02df2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210367902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2210367902
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2943933823
Short name T977
Test name
Test status
Simulation time 89503926 ps
CPU time 1.23 seconds
Started Aug 09 07:52:11 PM PDT 24
Finished Aug 09 07:52:13 PM PDT 24
Peak memory 218472 kb
Host smart-330749d1-5833-47ac-b760-e3e7a0053789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943933823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2943933823
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1641816555
Short name T17
Test name
Test status
Simulation time 25294926 ps
CPU time 1.06 seconds
Started Aug 09 07:52:21 PM PDT 24
Finished Aug 09 07:52:22 PM PDT 24
Peak memory 224468 kb
Host smart-70b1e6a5-296e-4af3-a0b0-a5d543a5ecf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641816555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1641816555
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1566084577
Short name T297
Test name
Test status
Simulation time 22070285 ps
CPU time 1.1 seconds
Started Aug 09 07:52:06 PM PDT 24
Finished Aug 09 07:52:12 PM PDT 24
Peak memory 217348 kb
Host smart-ba0ecdd1-6522-41a8-b005-fc72a542c24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566084577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1566084577
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2190664388
Short name T864
Test name
Test status
Simulation time 82202023 ps
CPU time 1.2 seconds
Started Aug 09 07:52:12 PM PDT 24
Finished Aug 09 07:52:13 PM PDT 24
Peak memory 218380 kb
Host smart-9c8e884f-577e-4d75-bf95-6e1220a019bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190664388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2190664388
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3927514137
Short name T142
Test name
Test status
Simulation time 179023106 ps
CPU time 1.23 seconds
Started Aug 09 07:52:16 PM PDT 24
Finished Aug 09 07:52:17 PM PDT 24
Peak memory 229736 kb
Host smart-071fbc81-9188-4a28-b491-51763fc70bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927514137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3927514137
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1102010307
Short name T765
Test name
Test status
Simulation time 68088946 ps
CPU time 2.15 seconds
Started Aug 09 07:52:13 PM PDT 24
Finished Aug 09 07:52:15 PM PDT 24
Peak memory 220000 kb
Host smart-0e364d90-e446-4911-a295-421e4e9f6656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102010307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1102010307
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.4093445464
Short name T320
Test name
Test status
Simulation time 26371836 ps
CPU time 1.27 seconds
Started Aug 09 07:52:17 PM PDT 24
Finished Aug 09 07:52:18 PM PDT 24
Peak memory 215720 kb
Host smart-68e634c7-4f38-4d06-b2cf-b8dd5f20a6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093445464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.4093445464
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.4074985874
Short name T513
Test name
Test status
Simulation time 18130107 ps
CPU time 1.02 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 218632 kb
Host smart-fc1d0b2b-85a0-4b90-b899-2e1b41621e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074985874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.4074985874
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.107919185
Short name T870
Test name
Test status
Simulation time 159637845 ps
CPU time 1.43 seconds
Started Aug 09 07:52:13 PM PDT 24
Finished Aug 09 07:52:15 PM PDT 24
Peak memory 218684 kb
Host smart-f17f4a60-d09f-45e2-a851-cca9f28a2977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107919185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.107919185
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.4775746
Short name T184
Test name
Test status
Simulation time 62780229 ps
CPU time 1.15 seconds
Started Aug 09 07:52:16 PM PDT 24
Finished Aug 09 07:52:17 PM PDT 24
Peak memory 219540 kb
Host smart-05ea7aac-4ba8-4b72-8c82-61aac78ebbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4775746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.4775746
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2377847826
Short name T207
Test name
Test status
Simulation time 22112701 ps
CPU time 0.95 seconds
Started Aug 09 07:52:14 PM PDT 24
Finished Aug 09 07:52:15 PM PDT 24
Peak memory 219716 kb
Host smart-3f721a33-fe9e-4415-aae1-978996ef60fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377847826 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2377847826
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.137230856
Short name T964
Test name
Test status
Simulation time 105218006 ps
CPU time 1.15 seconds
Started Aug 09 07:52:12 PM PDT 24
Finished Aug 09 07:52:14 PM PDT 24
Peak memory 217256 kb
Host smart-e80a2e15-243b-4bc8-9f9a-c39e3c10e38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137230856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.137230856
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2214377429
Short name T18
Test name
Test status
Simulation time 53969016 ps
CPU time 1.24 seconds
Started Aug 09 07:52:11 PM PDT 24
Finished Aug 09 07:52:13 PM PDT 24
Peak memory 219744 kb
Host smart-dce2129f-1bea-4ac6-bae5-ee012b6ac5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214377429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2214377429
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.3392488075
Short name T139
Test name
Test status
Simulation time 25818196 ps
CPU time 1.1 seconds
Started Aug 09 07:52:21 PM PDT 24
Finished Aug 09 07:52:22 PM PDT 24
Peak memory 220068 kb
Host smart-2db2c007-43a3-47ae-bdf8-e3f1984102a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392488075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3392488075
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3855802957
Short name T13
Test name
Test status
Simulation time 101694921 ps
CPU time 1.29 seconds
Started Aug 09 07:52:12 PM PDT 24
Finished Aug 09 07:52:13 PM PDT 24
Peak memory 220092 kb
Host smart-7e5e0447-cbf9-41a3-8f82-77007a3bd5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855802957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3855802957
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3827162696
Short name T865
Test name
Test status
Simulation time 85816401 ps
CPU time 1.3 seconds
Started Aug 09 07:50:55 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 220820 kb
Host smart-2d6a06cd-2d73-47ec-876b-6ab6fd564968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827162696 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3827162696
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2718293305
Short name T784
Test name
Test status
Simulation time 26126040 ps
CPU time 0.83 seconds
Started Aug 09 07:50:54 PM PDT 24
Finished Aug 09 07:50:55 PM PDT 24
Peak memory 206848 kb
Host smart-7e4e57c8-a764-4bcc-8ec9-8cbc6c434f45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718293305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2718293305
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.555547068
Short name T775
Test name
Test status
Simulation time 20290271 ps
CPU time 0.83 seconds
Started Aug 09 07:50:56 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 216596 kb
Host smart-d5b1bf4b-6e3e-45b3-b4fc-12fe22f4e636
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555547068 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.555547068
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.4173144389
Short name T172
Test name
Test status
Simulation time 58373224 ps
CPU time 1.08 seconds
Started Aug 09 07:50:53 PM PDT 24
Finished Aug 09 07:50:55 PM PDT 24
Peak memory 217176 kb
Host smart-38052b86-468b-49ed-8da0-5eaa0a6c01f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173144389 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.4173144389
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.4021611077
Short name T958
Test name
Test status
Simulation time 29620264 ps
CPU time 0.93 seconds
Started Aug 09 07:50:55 PM PDT 24
Finished Aug 09 07:50:56 PM PDT 24
Peak memory 218712 kb
Host smart-0c7dd16a-7bb3-45e0-8205-d3114a9d4e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021611077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.4021611077
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2786309009
Short name T312
Test name
Test status
Simulation time 54371765 ps
CPU time 1.19 seconds
Started Aug 09 07:50:56 PM PDT 24
Finished Aug 09 07:50:57 PM PDT 24
Peak memory 220056 kb
Host smart-eb1d17d2-f025-4c9c-8828-b52a6b0e9369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786309009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2786309009
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1367354492
Short name T634
Test name
Test status
Simulation time 25961606 ps
CPU time 1 seconds
Started Aug 09 07:50:53 PM PDT 24
Finished Aug 09 07:50:55 PM PDT 24
Peak memory 215348 kb
Host smart-d4a88611-16e7-4745-9253-a74c14e915c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367354492 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1367354492
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1465688744
Short name T879
Test name
Test status
Simulation time 31842545 ps
CPU time 0.91 seconds
Started Aug 09 07:50:58 PM PDT 24
Finished Aug 09 07:50:59 PM PDT 24
Peak memory 207096 kb
Host smart-4eda233e-f644-4422-8d30-f53704ec86a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465688744 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1465688744
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3915397989
Short name T680
Test name
Test status
Simulation time 19521225 ps
CPU time 0.99 seconds
Started Aug 09 07:51:01 PM PDT 24
Finished Aug 09 07:51:02 PM PDT 24
Peak memory 215208 kb
Host smart-0822bf59-65d4-4547-ad29-2b458fe8ba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915397989 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3915397989
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3498290068
Short name T830
Test name
Test status
Simulation time 516599063 ps
CPU time 5.23 seconds
Started Aug 09 07:50:55 PM PDT 24
Finished Aug 09 07:51:01 PM PDT 24
Peak memory 215316 kb
Host smart-cd66fd40-640f-46d9-92a6-8da5b474773c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498290068 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3498290068
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.495679467
Short name T688
Test name
Test status
Simulation time 36252067961 ps
CPU time 423.09 seconds
Started Aug 09 07:51:00 PM PDT 24
Finished Aug 09 07:58:03 PM PDT 24
Peak memory 223644 kb
Host smart-5114c463-ae08-4e79-a021-39050726d67c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495679467 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.495679467
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.44157979
Short name T322
Test name
Test status
Simulation time 120070247 ps
CPU time 1.17 seconds
Started Aug 09 07:52:13 PM PDT 24
Finished Aug 09 07:52:14 PM PDT 24
Peak memory 221280 kb
Host smart-fbf4f2dd-3530-438e-a6df-ac9253e8d0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44157979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.44157979
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1391320492
Short name T208
Test name
Test status
Simulation time 19961410 ps
CPU time 1.12 seconds
Started Aug 09 07:52:16 PM PDT 24
Finished Aug 09 07:52:17 PM PDT 24
Peak memory 219792 kb
Host smart-89be5eae-bcc3-4afc-a5f5-2cf826d2340a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391320492 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1391320492
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.813570760
Short name T418
Test name
Test status
Simulation time 24851345 ps
CPU time 1.1 seconds
Started Aug 09 07:52:09 PM PDT 24
Finished Aug 09 07:52:10 PM PDT 24
Peak memory 219176 kb
Host smart-78639cdb-e580-46d5-9cdc-8e3ca5895d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813570760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.813570760
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1846796469
Short name T817
Test name
Test status
Simulation time 47370945 ps
CPU time 1.2 seconds
Started Aug 09 07:52:25 PM PDT 24
Finished Aug 09 07:52:27 PM PDT 24
Peak memory 218468 kb
Host smart-50fe0a83-792e-49b3-a516-08e975e69cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846796469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1846796469
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.286970673
Short name T468
Test name
Test status
Simulation time 75651207 ps
CPU time 1.22 seconds
Started Aug 09 07:52:28 PM PDT 24
Finished Aug 09 07:52:29 PM PDT 24
Peak memory 225696 kb
Host smart-7391ecdf-5c0d-4d35-b8f8-902ac4025efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286970673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.286970673
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1860753076
Short name T550
Test name
Test status
Simulation time 185072320 ps
CPU time 1.32 seconds
Started Aug 09 07:52:12 PM PDT 24
Finished Aug 09 07:52:14 PM PDT 24
Peak memory 218700 kb
Host smart-704e6e9d-b151-41db-9ce9-1ca9739d4ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860753076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1860753076
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.3550124915
Short name T264
Test name
Test status
Simulation time 29066212 ps
CPU time 1.21 seconds
Started Aug 09 07:52:30 PM PDT 24
Finished Aug 09 07:52:31 PM PDT 24
Peak memory 219668 kb
Host smart-c964d2bc-9b30-42f8-b544-2b87c2abcc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550124915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.3550124915
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.649752996
Short name T544
Test name
Test status
Simulation time 55767667 ps
CPU time 1.25 seconds
Started Aug 09 07:52:20 PM PDT 24
Finished Aug 09 07:52:21 PM PDT 24
Peak memory 225720 kb
Host smart-496b85b7-cc92-4803-b8b8-611c70c65846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649752996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.649752996
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3686796243
Short name T943
Test name
Test status
Simulation time 58869652 ps
CPU time 1.25 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 217332 kb
Host smart-904a095c-b5d8-4d1c-a82a-be27300a8d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686796243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3686796243
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2236965680
Short name T178
Test name
Test status
Simulation time 24585881 ps
CPU time 1.2 seconds
Started Aug 09 07:52:37 PM PDT 24
Finished Aug 09 07:52:38 PM PDT 24
Peak memory 219664 kb
Host smart-ed438893-fd5c-407e-a450-14f7296af03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236965680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2236965680
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3773122137
Short name T186
Test name
Test status
Simulation time 25246629 ps
CPU time 1.05 seconds
Started Aug 09 07:52:34 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 224164 kb
Host smart-2945909b-a605-4f36-9776-5daf43a33b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773122137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3773122137
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.426474379
Short name T932
Test name
Test status
Simulation time 78861587 ps
CPU time 1.38 seconds
Started Aug 09 07:52:33 PM PDT 24
Finished Aug 09 07:52:34 PM PDT 24
Peak memory 218944 kb
Host smart-22618389-87e5-41c6-b044-5ec9fc964dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426474379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.426474379
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.3905671341
Short name T263
Test name
Test status
Simulation time 215507416 ps
CPU time 1.29 seconds
Started Aug 09 07:52:36 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 218356 kb
Host smart-76af8fa8-219d-43ca-899a-f327805436ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905671341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3905671341
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3092746581
Short name T538
Test name
Test status
Simulation time 79476225 ps
CPU time 1.09 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 220072 kb
Host smart-6751c1e2-f152-46b2-9f26-e82edf5d8f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092746581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3092746581
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2680098244
Short name T126
Test name
Test status
Simulation time 35898065 ps
CPU time 1.69 seconds
Started Aug 09 07:52:27 PM PDT 24
Finished Aug 09 07:52:29 PM PDT 24
Peak memory 218800 kb
Host smart-66184c8e-ba22-4a74-915f-299f0c3f6af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680098244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2680098244
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.400176244
Short name T466
Test name
Test status
Simulation time 29082635 ps
CPU time 1.11 seconds
Started Aug 09 07:52:33 PM PDT 24
Finished Aug 09 07:52:34 PM PDT 24
Peak memory 218732 kb
Host smart-d36e5546-b3e5-488d-9e5c-2a1c60b86396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400176244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.400176244
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1902078273
Short name T61
Test name
Test status
Simulation time 60115870 ps
CPU time 1.44 seconds
Started Aug 09 07:52:31 PM PDT 24
Finished Aug 09 07:52:33 PM PDT 24
Peak memory 226020 kb
Host smart-9afa0411-090e-4328-b515-361bbc8946ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902078273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1902078273
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2650862581
Short name T349
Test name
Test status
Simulation time 174087087 ps
CPU time 2.17 seconds
Started Aug 09 07:52:29 PM PDT 24
Finished Aug 09 07:52:31 PM PDT 24
Peak memory 219396 kb
Host smart-ad407de6-aed6-45f3-a7c0-152d0a5e4a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650862581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2650862581
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1148690244
Short name T613
Test name
Test status
Simulation time 110388052 ps
CPU time 1.12 seconds
Started Aug 09 07:52:39 PM PDT 24
Finished Aug 09 07:52:40 PM PDT 24
Peak memory 219508 kb
Host smart-27b24584-222c-4ad8-ba8f-6ac24d0cd9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148690244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1148690244
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3565321880
Short name T158
Test name
Test status
Simulation time 71917703 ps
CPU time 0.91 seconds
Started Aug 09 07:52:30 PM PDT 24
Finished Aug 09 07:52:31 PM PDT 24
Peak memory 219784 kb
Host smart-2c67c68c-6b07-42cd-b4c5-a74ab976df54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565321880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3565321880
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.893422006
Short name T617
Test name
Test status
Simulation time 58692544 ps
CPU time 1.79 seconds
Started Aug 09 07:52:28 PM PDT 24
Finished Aug 09 07:52:30 PM PDT 24
Peak memory 218836 kb
Host smart-3d093aae-2245-45ff-9e09-d54c0d1f9520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893422006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.893422006
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3466266212
Short name T381
Test name
Test status
Simulation time 34877176 ps
CPU time 1.06 seconds
Started Aug 09 07:52:35 PM PDT 24
Finished Aug 09 07:52:37 PM PDT 24
Peak memory 219604 kb
Host smart-c872cedb-a4a1-4e55-a29a-36c8b05ed819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466266212 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3466266212
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1469644906
Short name T697
Test name
Test status
Simulation time 34758198 ps
CPU time 0.89 seconds
Started Aug 09 07:52:27 PM PDT 24
Finished Aug 09 07:52:28 PM PDT 24
Peak memory 219744 kb
Host smart-068e4c0c-875f-424a-9d64-2dfeb256d41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469644906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1469644906
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2898402697
Short name T328
Test name
Test status
Simulation time 36397594 ps
CPU time 1.59 seconds
Started Aug 09 07:52:34 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 217744 kb
Host smart-dceebc9b-7124-4170-9319-fedb0f4b461d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898402697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2898402697
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.913874687
Short name T611
Test name
Test status
Simulation time 27943628 ps
CPU time 1.35 seconds
Started Aug 09 07:52:33 PM PDT 24
Finished Aug 09 07:52:34 PM PDT 24
Peak memory 220420 kb
Host smart-da1bcc7b-1f2e-4094-8a4a-ab1f7a74abbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913874687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.913874687
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.4117326968
Short name T732
Test name
Test status
Simulation time 35658067 ps
CPU time 0.79 seconds
Started Aug 09 07:52:23 PM PDT 24
Finished Aug 09 07:52:23 PM PDT 24
Peak memory 215192 kb
Host smart-034b5547-bab5-4388-b0d9-c3a00de5a516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117326968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.4117326968
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.635922342
Short name T433
Test name
Test status
Simulation time 44572638 ps
CPU time 1.67 seconds
Started Aug 09 07:52:34 PM PDT 24
Finished Aug 09 07:52:36 PM PDT 24
Peak memory 218604 kb
Host smart-5e327497-16a1-4240-a151-c3767b97e9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635922342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.635922342
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.908767030
Short name T886
Test name
Test status
Simulation time 55417020 ps
CPU time 1.04 seconds
Started Aug 09 07:52:18 PM PDT 24
Finished Aug 09 07:52:19 PM PDT 24
Peak memory 219720 kb
Host smart-6ed470df-4881-4ce4-83a0-5aa8d5668d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908767030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.908767030
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3242922184
Short name T229
Test name
Test status
Simulation time 18573558 ps
CPU time 1.04 seconds
Started Aug 09 07:52:34 PM PDT 24
Finished Aug 09 07:52:35 PM PDT 24
Peak memory 218736 kb
Host smart-b0529a8c-a15a-4d1d-b3ea-1810fe02b450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242922184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3242922184
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.931203103
Short name T407
Test name
Test status
Simulation time 60324204 ps
CPU time 1.24 seconds
Started Aug 09 07:52:31 PM PDT 24
Finished Aug 09 07:52:32 PM PDT 24
Peak memory 218816 kb
Host smart-0725c8fa-90f1-4e94-8f49-aec5de8493cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931203103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.931203103
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%