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 LINE       702
 EXPRESSION (cmd_fifo_rst_fo[1] || main_sm_done_pulse)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       704
 SUB-EXPRESSION (sfifo_rescmd_push && sfifo_rescmd_full)
                 --------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T91,T92,T93
1	0	Covered	T4,T10,T7
1	1	Covered	T30,T95

 LINE       704
 SUB-EXPRESSION (sfifo_rescmd_pop && ((!sfifo_rescmd_not_empty)))
                 --------1-------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T15
1	1	Covered	T35

 LINE       704
 SUB-EXPRESSION ((sfifo_rescmd_full && ((!sfifo_rescmd_not_empty))) || sfifo_rescmd_int_err)
                 -------------------------1------------------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T18,T19
1	0	Covered	T30,T109,T110

 LINE       704
 SUB-EXPRESSION (sfifo_rescmd_full && ((!sfifo_rescmd_not_empty)))
                 --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T91,T92,T30
1	1	Covered	T30,T109,T110

 LINE       733
 EXPRESSION ((send_gencmd || capt_gencmd_fifo_cnt) && csrng_cmd_i.csrng_req_ready)
             ------------------1------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T15
1	1	Covered	T10,T11,T15

 LINE       733
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T15
1	0	Covered	T10,T11,T15

 LINE       735
 EXPRESSION (gencmd_handshake ? 1'b1 : generate_cmd_load)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T15

 LINE       739
 EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : generate_cmd_bus)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T15

 LINE       743
 EXPRESSION ((gencmd_handshake && ((!cmd_sent))) || capt_gencmd_fifo_cnt)
             -----------------1-----------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T15
1	0	Covered	T20,T69,T105

 LINE       743
 SUB-EXPRESSION (gencmd_handshake && ((!cmd_sent)))
                 --------1-------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T15
1	1	Covered	T20,T69,T105

 LINE       745
 EXPRESSION (cmd_fifo_rst_fo[2] || main_sm_done_pulse)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       747
 SUB-EXPRESSION (sfifo_gencmd_push && sfifo_gencmd_full)
                 --------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T10,T26,T7
1	0	Covered	T4,T10,T7
1	1	Covered	T31,T33,T89

 LINE       747
 SUB-EXPRESSION (sfifo_gencmd_pop && ((!sfifo_gencmd_not_empty)))
                 --------1-------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T15
1	1	Covered	T5,T34,T94

 LINE       747
 SUB-EXPRESSION ((sfifo_gencmd_full && ((!sfifo_gencmd_not_empty))) || sfifo_gencmd_int_err)
                 -------------------------1------------------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T18,T19
1	0	Covered	T26,T31,T111

 LINE       747
 SUB-EXPRESSION (sfifo_gencmd_full && ((!sfifo_gencmd_not_empty)))
                 --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T7,T31
1	1	Covered	T26,T31,T111

 LINE       791
 EXPRESSION (send_gencmd && cmd_sent)
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T15
1	0	Covered	T10,T11,T15
1	1	Covered	T10,T11,T15

 LINE       807
 EXPRESSION (max_reqs_between_reseed_load || (send_rescmd && cmd_sent) || main_sm_done_pulse)
             --------------1-------------    ------------2------------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T10,T11,T15
1	0	0	Covered	T10,T7,T11

 LINE       807
 SUB-EXPRESSION (send_rescmd && cmd_sent)
                 -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T15
1	0	Covered	T10,T15,T20
1	1	Covered	T10,T11,T15

 LINE       811
 EXPRESSION (max_reqs_cnt == '0)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       814
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CmdFifoCnt])) ? '0 : ((cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 : (capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       814
 SUB-EXPRESSION 
 Number  Term
      1  (cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 : (capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       814
 SUB-EXPRESSION (cmd_fifo_rst_fo[3] || main_sm_done_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       814
 SUB-EXPRESSION 
 Number  Term
      1  capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T15

 LINE       814
 SUB-EXPRESSION (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T15

 LINE       814
 SUB-EXPRESSION ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)
                 -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T5,T15

 LINE       814
 SUB-EXPRESSION (sfifo_gencmd_pop || sfifo_rescmd_pop)
                 --------1-------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T15,T20
1	0	Covered	T5,T20,T69

 LINE       824
 EXPRESSION ((cmd_fifo_cnt_q == 4'(1)) && (gencmd_handshake || rescmd_handshake))
             ------------1------------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T20
1	0	Covered	T10,T11,T15
1	1	Covered	T10,T11,T15

 LINE       824
 SUB-EXPRESSION (cmd_fifo_cnt_q == 4'(1))
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T15

 LINE       824
 SUB-EXPRESSION (gencmd_handshake || rescmd_handshake)
                 --------1-------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T15
1	0	Covered	T10,T11,T15

 LINE       829
 EXPRESSION ((capt_gencmd_fifo_cnt || capt_rescmd_fifo_cnt) ? 1'b1 : (cs_hw_cmd_handshake ? 1'b0 : cmd_hdr_busy_q))
             -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T15

 LINE       829
 SUB-EXPRESSION (capt_gencmd_fifo_cnt || capt_rescmd_fifo_cnt)
                 ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T15
1	0	Covered	T10,T11,T15

 LINE       829
 SUB-EXPRESSION (cs_hw_cmd_handshake ? 1'b0 : cmd_hdr_busy_q)
                 ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       877
 EXPRESSION (((!packer_ep_rvalid[0])) && edn_i[0].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T24,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T24,T10

 LINE       877
 EXPRESSION (((!packer_ep_rvalid[1])) && edn_i[1].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T38,T39,T40

 LINE       877
 EXPRESSION (((!packer_ep_rvalid[2])) && edn_i[2].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T38,T41,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T38,T41

 LINE       877
 EXPRESSION (((!packer_ep_rvalid[3])) && edn_i[3].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T41,T16,T42

 LINE       877
 EXPRESSION (((!packer_ep_rvalid[4])) && edn_i[4].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T24

 LINE       877
 EXPRESSION (((!packer_ep_rvalid[5])) && edn_i[5].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T24,T43,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T24,T16,T43

 LINE       877
 EXPRESSION (((!packer_ep_rvalid[6])) && edn_i[6].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T41,T43
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T41,T16

 LINE       902
 EXPRESSION (csrng_cmd_i.genbits_valid && ((!reject_csrng_entropy)) && ( ! ((csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS) && csrng_cmd_i.csrng_rsp_ack) ))
             ------------1------------    ------------2------------    -----------------------------------------3-----------------------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T112
1	1	1	Covered	T1,T2,T3

 LINE       902
 SUB-EXPRESSION ( ! ((csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS) && csrng_cmd_i.csrng_rsp_ack) )
                    --------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       902
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS) && csrng_cmd_i.csrng_rsp_ack)
                 -----------------------1----------------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       902
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       906
 EXPRESSION (packer_cs_wready && ((!reject_csrng_entropy)))
             --------1-------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       910
 EXPRESSION (((!edn_enable_fo[CsrngFipsEn])) ? 1'b0 : ((packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips : csrng_fips_q))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       910
 SUB-EXPRESSION ((packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips : csrng_fips_q)
                 ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       910
 SUB-EXPRESSION (packer_cs_push && packer_cs_wready)
                 -------1------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       925
 EXPRESSION (packer_cs_rvalid && packer_cs_rready)
             --------1-------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T24
1	1	Covered	T1,T2,T3

 LINE       927
 EXPRESSION (cs_rdata_capt_vld ? packer_cs_rdata[63:0] : cs_rdata_capt_q)
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       929
 EXPRESSION (((!edn_enable_fo[CsrngDataVld])) ? 1'b0 : (cs_rdata_capt_vld ? 1'b1 : cs_rdata_capt_vld_q))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       929
 SUB-EXPRESSION (cs_rdata_capt_vld ? 1'b1 : cs_rdata_capt_vld_q)
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       935
 EXPRESSION (cs_rdata_capt_vld && cs_rdata_capt_vld_q && (cs_rdata_capt_q == packer_cs_rdata[63:0]))
             --------1--------    ---------2---------    ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T24,T10,T6
1	1	1	Covered	T1,T2,T3

 LINE       935
 SUB-EXPRESSION (cs_rdata_capt_q == packer_cs_rdata[63:0])
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       963
 EXPRESSION (packer_arb_valid && packer_ep_wready[0] && packer_arb_gnt[0])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T3,T24,T10

 LINE       963
 EXPRESSION (packer_arb_valid && packer_ep_wready[1] && packer_arb_gnt[1])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T38,T39,T40

 LINE       963
 EXPRESSION (packer_arb_valid && packer_ep_wready[2] && packer_arb_gnt[2])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T38,T41,T15

 LINE       963
 EXPRESSION (packer_arb_valid && packer_ep_wready[3] && packer_arb_gnt[3])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T41,T42,T47

 LINE       963
 EXPRESSION (packer_arb_valid && packer_ep_wready[4] && packer_arb_gnt[4])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T24

 LINE       963
 EXPRESSION (packer_arb_valid && packer_ep_wready[5] && packer_arb_gnt[5])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T24,T43,T42

 LINE       963
 EXPRESSION (packer_arb_valid && packer_ep_wready[6] && packer_arb_gnt[6])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T5,T41,T43

 LINE       967
 EXPRESSION (packer_ep_clr[0] ? 1'b0 : ((packer_ep_push[0] && packer_ep_wready[0]) ? csrng_fips_q : edn_fips_q[0]))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       967
 SUB-EXPRESSION ((packer_ep_push[0] && packer_ep_wready[0]) ? csrng_fips_q : edn_fips_q[0])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T24,T10

 LINE       967
 SUB-EXPRESSION (packer_ep_push[0] && packer_ep_wready[0])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T24,T10

 LINE       967
 EXPRESSION (packer_ep_clr[1] ? 1'b0 : ((packer_ep_push[1] && packer_ep_wready[1]) ? csrng_fips_q : edn_fips_q[1]))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       967
 SUB-EXPRESSION ((packer_ep_push[1] && packer_ep_wready[1]) ? csrng_fips_q : edn_fips_q[1])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T39,T40

 LINE       967
 SUB-EXPRESSION (packer_ep_push[1] && packer_ep_wready[1])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T38,T39,T40

 LINE       967
 EXPRESSION (packer_ep_clr[2] ? 1'b0 : ((packer_ep_push[2] && packer_ep_wready[2]) ? csrng_fips_q : edn_fips_q[2]))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       967
 SUB-EXPRESSION ((packer_ep_push[2] && packer_ep_wready[2]) ? csrng_fips_q : edn_fips_q[2])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T41,T15

 LINE       967
 SUB-EXPRESSION (packer_ep_push[2] && packer_ep_wready[2])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T38,T41,T15

 LINE       967
 EXPRESSION (packer_ep_clr[3] ? 1'b0 : ((packer_ep_push[3] && packer_ep_wready[3]) ? csrng_fips_q : edn_fips_q[3]))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       967
 SUB-EXPRESSION ((packer_ep_push[3] && packer_ep_wready[3]) ? csrng_fips_q : edn_fips_q[3])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T42,T47

 LINE       967
 SUB-EXPRESSION (packer_ep_push[3] && packer_ep_wready[3])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T41,T42,T47

 LINE       967
 EXPRESSION (packer_ep_clr[4] ? 1'b0 : ((packer_ep_push[4] && packer_ep_wready[4]) ? csrng_fips_q : edn_fips_q[4]))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       967
 SUB-EXPRESSION ((packer_ep_push[4] && packer_ep_wready[4]) ? csrng_fips_q : edn_fips_q[4])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T24

 LINE       967
 SUB-EXPRESSION (packer_ep_push[4] && packer_ep_wready[4])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T24

 LINE       967
 EXPRESSION (packer_ep_clr[5] ? 1'b0 : ((packer_ep_push[5] && packer_ep_wready[5]) ? csrng_fips_q : edn_fips_q[5]))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       967
 SUB-EXPRESSION ((packer_ep_push[5] && packer_ep_wready[5]) ? csrng_fips_q : edn_fips_q[5])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T24,T43,T42

 LINE       967
 SUB-EXPRESSION (packer_ep_push[5] && packer_ep_wready[5])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T24,T43,T42

 LINE       967
 EXPRESSION (packer_ep_clr[6] ? 1'b0 : ((packer_ep_push[6] && packer_ep_wready[6]) ? csrng_fips_q : edn_fips_q[6]))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       967
 SUB-EXPRESSION ((packer_ep_push[6] && packer_ep_wready[6]) ? csrng_fips_q : edn_fips_q[6])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T41,T43

 LINE       967
 SUB-EXPRESSION (packer_ep_push[6] && packer_ep_wready[6])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T41,T43

 LINE       1012
 EXPRESSION (((|err_code_test_bit[19:2])) || ((|err_code_test_bit[27:22])))
             --------------1-------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T6
1	0	Covered	T4,T5,T6