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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.52 98.25 93.91 97.02 91.28 96.37 99.77 92.06


Total test records in report: 1129
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T1022 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1634285330 Aug 10 05:58:38 PM PDT 24 Aug 10 05:58:40 PM PDT 24 558490086 ps
T1023 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2690632200 Aug 10 05:58:54 PM PDT 24 Aug 10 05:58:55 PM PDT 24 154786371 ps
T1024 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1347747716 Aug 10 05:58:48 PM PDT 24 Aug 10 05:58:50 PM PDT 24 49842966 ps
T1025 /workspace/coverage/cover_reg_top/14.edn_intr_test.1070337265 Aug 10 05:58:47 PM PDT 24 Aug 10 05:58:48 PM PDT 24 47341416 ps
T290 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1661547069 Aug 10 05:59:03 PM PDT 24 Aug 10 05:59:04 PM PDT 24 25207363 ps
T274 /workspace/coverage/cover_reg_top/17.edn_csr_rw.754621668 Aug 10 05:58:55 PM PDT 24 Aug 10 05:59:01 PM PDT 24 41977746 ps
T1026 /workspace/coverage/cover_reg_top/44.edn_intr_test.200908378 Aug 10 05:59:16 PM PDT 24 Aug 10 05:59:17 PM PDT 24 16707688 ps
T1027 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1019176068 Aug 10 05:58:37 PM PDT 24 Aug 10 05:58:40 PM PDT 24 437322214 ps
T1028 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1080070440 Aug 10 05:58:42 PM PDT 24 Aug 10 05:58:43 PM PDT 24 66508009 ps
T1029 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3794721354 Aug 10 05:58:38 PM PDT 24 Aug 10 05:58:39 PM PDT 24 55569093 ps
T275 /workspace/coverage/cover_reg_top/14.edn_csr_rw.927657138 Aug 10 05:58:40 PM PDT 24 Aug 10 05:58:41 PM PDT 24 29165973 ps
T1030 /workspace/coverage/cover_reg_top/16.edn_intr_test.761225385 Aug 10 05:58:49 PM PDT 24 Aug 10 05:58:49 PM PDT 24 22912789 ps
T1031 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2684761057 Aug 10 05:58:56 PM PDT 24 Aug 10 05:58:57 PM PDT 24 60591767 ps
T307 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4199699917 Aug 10 05:58:37 PM PDT 24 Aug 10 05:58:40 PM PDT 24 120498904 ps
T1032 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1745194561 Aug 10 05:58:53 PM PDT 24 Aug 10 05:58:55 PM PDT 24 228043578 ps
T1033 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4112599047 Aug 10 05:58:43 PM PDT 24 Aug 10 05:58:49 PM PDT 24 1777962755 ps
T1034 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2160628336 Aug 10 05:58:40 PM PDT 24 Aug 10 05:58:41 PM PDT 24 14588620 ps
T1035 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3763705797 Aug 10 05:58:56 PM PDT 24 Aug 10 05:58:57 PM PDT 24 46167127 ps
T1036 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2984995801 Aug 10 05:58:41 PM PDT 24 Aug 10 05:58:43 PM PDT 24 246567220 ps
T291 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.164183946 Aug 10 05:58:49 PM PDT 24 Aug 10 05:58:50 PM PDT 24 34669549 ps
T1037 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4203686716 Aug 10 05:58:28 PM PDT 24 Aug 10 05:58:29 PM PDT 24 72259913 ps
T292 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1518432380 Aug 10 05:58:50 PM PDT 24 Aug 10 05:58:51 PM PDT 24 133866087 ps
T1038 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.4024471920 Aug 10 05:58:28 PM PDT 24 Aug 10 05:58:30 PM PDT 24 128511059 ps
T1039 /workspace/coverage/cover_reg_top/10.edn_tl_errors.190641952 Aug 10 05:59:05 PM PDT 24 Aug 10 05:59:09 PM PDT 24 123378599 ps
T1040 /workspace/coverage/cover_reg_top/48.edn_intr_test.3737750697 Aug 10 05:58:57 PM PDT 24 Aug 10 05:58:58 PM PDT 24 75629789 ps
T1041 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.608836796 Aug 10 05:58:47 PM PDT 24 Aug 10 05:58:49 PM PDT 24 29090151 ps
T1042 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.25440568 Aug 10 05:58:48 PM PDT 24 Aug 10 05:58:50 PM PDT 24 136046117 ps
T1043 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1781214971 Aug 10 05:58:29 PM PDT 24 Aug 10 05:58:30 PM PDT 24 27900205 ps
T1044 /workspace/coverage/cover_reg_top/35.edn_intr_test.1562971494 Aug 10 05:58:48 PM PDT 24 Aug 10 05:58:49 PM PDT 24 40949786 ps
T1045 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2426193328 Aug 10 05:58:47 PM PDT 24 Aug 10 05:58:48 PM PDT 24 182736263 ps
T1046 /workspace/coverage/cover_reg_top/36.edn_intr_test.1758226037 Aug 10 05:59:08 PM PDT 24 Aug 10 05:59:09 PM PDT 24 14259127 ps
T311 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2290820608 Aug 10 05:58:28 PM PDT 24 Aug 10 05:58:31 PM PDT 24 177939860 ps
T1047 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3598580915 Aug 10 05:59:12 PM PDT 24 Aug 10 05:59:15 PM PDT 24 417964689 ps
T1048 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1073738979 Aug 10 05:58:59 PM PDT 24 Aug 10 05:59:01 PM PDT 24 158891786 ps
T1049 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1277511910 Aug 10 05:58:36 PM PDT 24 Aug 10 05:58:39 PM PDT 24 71461798 ps
T308 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1274897920 Aug 10 05:59:02 PM PDT 24 Aug 10 05:59:10 PM PDT 24 450954854 ps
T312 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3804750186 Aug 10 05:58:48 PM PDT 24 Aug 10 05:58:50 PM PDT 24 160177056 ps
T1050 /workspace/coverage/cover_reg_top/46.edn_intr_test.2107979565 Aug 10 05:58:48 PM PDT 24 Aug 10 05:58:49 PM PDT 24 35422770 ps
T1051 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3222197451 Aug 10 05:58:28 PM PDT 24 Aug 10 05:58:32 PM PDT 24 468987217 ps
T1052 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2526750745 Aug 10 05:58:29 PM PDT 24 Aug 10 05:58:30 PM PDT 24 46670907 ps
T1053 /workspace/coverage/cover_reg_top/19.edn_intr_test.228750825 Aug 10 05:58:47 PM PDT 24 Aug 10 05:58:48 PM PDT 24 21827381 ps
T276 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2667548844 Aug 10 05:58:52 PM PDT 24 Aug 10 05:58:53 PM PDT 24 37602994 ps
T1054 /workspace/coverage/cover_reg_top/26.edn_intr_test.254530328 Aug 10 05:58:55 PM PDT 24 Aug 10 05:58:56 PM PDT 24 27579422 ps
T1055 /workspace/coverage/cover_reg_top/0.edn_intr_test.2529498707 Aug 10 05:58:52 PM PDT 24 Aug 10 05:58:53 PM PDT 24 37998498 ps
T1056 /workspace/coverage/cover_reg_top/34.edn_intr_test.3880725507 Aug 10 05:58:50 PM PDT 24 Aug 10 05:58:51 PM PDT 24 18984271 ps
T1057 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4150330489 Aug 10 05:58:50 PM PDT 24 Aug 10 05:58:52 PM PDT 24 37765742 ps
T277 /workspace/coverage/cover_reg_top/3.edn_csr_rw.13930593 Aug 10 05:58:28 PM PDT 24 Aug 10 05:58:30 PM PDT 24 16508766 ps
T309 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3865725899 Aug 10 05:58:43 PM PDT 24 Aug 10 05:58:45 PM PDT 24 270667542 ps
T1058 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.967285910 Aug 10 05:59:00 PM PDT 24 Aug 10 05:59:01 PM PDT 24 16638970 ps
T1059 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1807409613 Aug 10 05:58:51 PM PDT 24 Aug 10 05:58:55 PM PDT 24 216382380 ps
T1060 /workspace/coverage/cover_reg_top/41.edn_intr_test.1649946841 Aug 10 05:58:52 PM PDT 24 Aug 10 05:58:53 PM PDT 24 79491885 ps
T1061 /workspace/coverage/cover_reg_top/19.edn_tl_errors.4046833633 Aug 10 05:58:45 PM PDT 24 Aug 10 05:58:49 PM PDT 24 242562820 ps
T1062 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1749758443 Aug 10 05:58:44 PM PDT 24 Aug 10 05:58:46 PM PDT 24 45878465 ps
T278 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2983255653 Aug 10 05:58:35 PM PDT 24 Aug 10 05:58:36 PM PDT 24 13354382 ps
T1063 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3032549017 Aug 10 05:58:38 PM PDT 24 Aug 10 05:58:39 PM PDT 24 69694550 ps
T1064 /workspace/coverage/cover_reg_top/28.edn_intr_test.1507202872 Aug 10 05:58:48 PM PDT 24 Aug 10 05:58:49 PM PDT 24 23218407 ps
T1065 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.691213559 Aug 10 05:58:55 PM PDT 24 Aug 10 05:58:57 PM PDT 24 135126403 ps
T279 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1222834983 Aug 10 05:58:29 PM PDT 24 Aug 10 05:58:30 PM PDT 24 22507021 ps
T1066 /workspace/coverage/cover_reg_top/5.edn_intr_test.3029942784 Aug 10 05:58:38 PM PDT 24 Aug 10 05:58:39 PM PDT 24 13426319 ps
T1067 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3628359768 Aug 10 05:58:52 PM PDT 24 Aug 10 05:58:53 PM PDT 24 15297411 ps
T310 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.216687288 Aug 10 05:58:37 PM PDT 24 Aug 10 05:58:40 PM PDT 24 85435357 ps
T1068 /workspace/coverage/cover_reg_top/10.edn_intr_test.3536798111 Aug 10 05:58:54 PM PDT 24 Aug 10 05:58:55 PM PDT 24 11479634 ps
T1069 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3823592583 Aug 10 05:58:44 PM PDT 24 Aug 10 05:58:46 PM PDT 24 30651724 ps
T1070 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.321702476 Aug 10 05:58:28 PM PDT 24 Aug 10 05:58:32 PM PDT 24 373218170 ps
T1071 /workspace/coverage/cover_reg_top/40.edn_intr_test.4200171872 Aug 10 05:58:48 PM PDT 24 Aug 10 05:58:49 PM PDT 24 14430165 ps
T1072 /workspace/coverage/cover_reg_top/43.edn_intr_test.2688001817 Aug 10 05:58:48 PM PDT 24 Aug 10 05:58:49 PM PDT 24 21395863 ps
T1073 /workspace/coverage/cover_reg_top/42.edn_intr_test.1077217627 Aug 10 05:58:45 PM PDT 24 Aug 10 05:58:46 PM PDT 24 70755634 ps
T1074 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.399706751 Aug 10 05:58:35 PM PDT 24 Aug 10 05:58:37 PM PDT 24 92475022 ps
T1075 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.5750721 Aug 10 05:58:57 PM PDT 24 Aug 10 05:58:58 PM PDT 24 77572834 ps
T1076 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3873496258 Aug 10 05:58:41 PM PDT 24 Aug 10 05:58:42 PM PDT 24 42052070 ps
T1077 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2193882900 Aug 10 05:58:58 PM PDT 24 Aug 10 05:58:59 PM PDT 24 39745035 ps
T1078 /workspace/coverage/cover_reg_top/17.edn_intr_test.4251052687 Aug 10 05:58:47 PM PDT 24 Aug 10 05:58:48 PM PDT 24 10826985 ps
T1079 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.25686454 Aug 10 05:58:51 PM PDT 24 Aug 10 05:58:53 PM PDT 24 65584730 ps
T1080 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2882455563 Aug 10 05:58:37 PM PDT 24 Aug 10 05:58:39 PM PDT 24 76881883 ps
T1081 /workspace/coverage/cover_reg_top/29.edn_intr_test.715217446 Aug 10 05:58:52 PM PDT 24 Aug 10 05:58:53 PM PDT 24 33672500 ps
T1082 /workspace/coverage/cover_reg_top/0.edn_tl_errors.805743938 Aug 10 05:58:31 PM PDT 24 Aug 10 05:58:33 PM PDT 24 51695151 ps
T1083 /workspace/coverage/cover_reg_top/23.edn_intr_test.3252294823 Aug 10 05:58:45 PM PDT 24 Aug 10 05:58:46 PM PDT 24 17094311 ps
T1084 /workspace/coverage/cover_reg_top/6.edn_intr_test.467247989 Aug 10 05:58:49 PM PDT 24 Aug 10 05:58:50 PM PDT 24 14400083 ps
T1085 /workspace/coverage/cover_reg_top/25.edn_intr_test.2408733685 Aug 10 05:59:06 PM PDT 24 Aug 10 05:59:07 PM PDT 24 17834662 ps
T1086 /workspace/coverage/cover_reg_top/31.edn_intr_test.3831145691 Aug 10 05:58:53 PM PDT 24 Aug 10 05:58:54 PM PDT 24 56299506 ps
T1087 /workspace/coverage/cover_reg_top/20.edn_intr_test.3254762481 Aug 10 05:59:02 PM PDT 24 Aug 10 05:59:03 PM PDT 24 31192855 ps
T1088 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.915529215 Aug 10 05:58:29 PM PDT 24 Aug 10 05:58:30 PM PDT 24 20537349 ps
T1089 /workspace/coverage/cover_reg_top/9.edn_intr_test.2063444102 Aug 10 05:59:00 PM PDT 24 Aug 10 05:59:01 PM PDT 24 86677623 ps
T1090 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.635825386 Aug 10 05:58:52 PM PDT 24 Aug 10 05:58:54 PM PDT 24 27506550 ps
T1091 /workspace/coverage/cover_reg_top/27.edn_intr_test.300953647 Aug 10 05:58:48 PM PDT 24 Aug 10 05:58:49 PM PDT 24 12963556 ps
T1092 /workspace/coverage/cover_reg_top/24.edn_intr_test.1464736547 Aug 10 05:58:49 PM PDT 24 Aug 10 05:58:50 PM PDT 24 36796892 ps
T1093 /workspace/coverage/cover_reg_top/2.edn_intr_test.697543128 Aug 10 05:58:41 PM PDT 24 Aug 10 05:58:42 PM PDT 24 20804273 ps
T1094 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3719512655 Aug 10 05:58:47 PM PDT 24 Aug 10 05:58:48 PM PDT 24 64193510 ps
T1095 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3873563337 Aug 10 05:59:03 PM PDT 24 Aug 10 05:59:04 PM PDT 24 25405352 ps
T1096 /workspace/coverage/cover_reg_top/33.edn_intr_test.319596229 Aug 10 05:58:54 PM PDT 24 Aug 10 05:58:55 PM PDT 24 31744871 ps
T1097 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.170433222 Aug 10 05:58:43 PM PDT 24 Aug 10 05:58:44 PM PDT 24 387467665 ps
T1098 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2345208398 Aug 10 05:58:49 PM PDT 24 Aug 10 05:58:57 PM PDT 24 477697896 ps
T1099 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.170276606 Aug 10 05:59:00 PM PDT 24 Aug 10 05:59:01 PM PDT 24 53988120 ps
T1100 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2157009948 Aug 10 05:58:57 PM PDT 24 Aug 10 05:59:00 PM PDT 24 281584069 ps
T280 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3887467857 Aug 10 05:58:31 PM PDT 24 Aug 10 05:58:32 PM PDT 24 18050391 ps
T1101 /workspace/coverage/cover_reg_top/7.edn_intr_test.2452250822 Aug 10 05:58:50 PM PDT 24 Aug 10 05:58:52 PM PDT 24 12958796 ps
T1102 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.804775407 Aug 10 05:58:54 PM PDT 24 Aug 10 05:58:56 PM PDT 24 29352982 ps
T281 /workspace/coverage/cover_reg_top/6.edn_csr_rw.73825291 Aug 10 05:58:51 PM PDT 24 Aug 10 05:58:52 PM PDT 24 57126112 ps
T1103 /workspace/coverage/cover_reg_top/16.edn_tl_errors.459121196 Aug 10 05:58:36 PM PDT 24 Aug 10 05:58:39 PM PDT 24 38510708 ps
T1104 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.848944849 Aug 10 05:58:38 PM PDT 24 Aug 10 05:58:39 PM PDT 24 20382846 ps
T1105 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1912004360 Aug 10 05:58:41 PM PDT 24 Aug 10 05:58:43 PM PDT 24 76148388 ps
T1106 /workspace/coverage/cover_reg_top/13.edn_intr_test.3923129096 Aug 10 05:58:44 PM PDT 24 Aug 10 05:58:45 PM PDT 24 23989546 ps
T1107 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.398954740 Aug 10 05:58:40 PM PDT 24 Aug 10 05:58:41 PM PDT 24 31937783 ps
T1108 /workspace/coverage/cover_reg_top/1.edn_intr_test.3528201844 Aug 10 05:58:39 PM PDT 24 Aug 10 05:58:40 PM PDT 24 28423599 ps
T1109 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.614515458 Aug 10 05:58:43 PM PDT 24 Aug 10 05:58:45 PM PDT 24 36431635 ps
T1110 /workspace/coverage/cover_reg_top/18.edn_intr_test.241433331 Aug 10 05:58:45 PM PDT 24 Aug 10 05:58:46 PM PDT 24 14214358 ps
T1111 /workspace/coverage/cover_reg_top/12.edn_intr_test.1528739400 Aug 10 05:58:42 PM PDT 24 Aug 10 05:58:43 PM PDT 24 11907933 ps
T282 /workspace/coverage/cover_reg_top/10.edn_csr_rw.4211415530 Aug 10 05:58:37 PM PDT 24 Aug 10 05:58:38 PM PDT 24 20038626 ps
T1112 /workspace/coverage/cover_reg_top/15.edn_intr_test.3582645487 Aug 10 05:58:40 PM PDT 24 Aug 10 05:58:41 PM PDT 24 51820574 ps
T1113 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4231653841 Aug 10 05:58:44 PM PDT 24 Aug 10 05:58:51 PM PDT 24 54834365 ps
T1114 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1934030516 Aug 10 05:58:29 PM PDT 24 Aug 10 05:58:32 PM PDT 24 72305028 ps
T1115 /workspace/coverage/cover_reg_top/39.edn_intr_test.3440754009 Aug 10 05:58:46 PM PDT 24 Aug 10 05:58:47 PM PDT 24 48342208 ps
T285 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2384131318 Aug 10 05:58:47 PM PDT 24 Aug 10 05:58:48 PM PDT 24 31295150 ps
T1116 /workspace/coverage/cover_reg_top/11.edn_intr_test.2740680098 Aug 10 05:58:39 PM PDT 24 Aug 10 05:58:40 PM PDT 24 20224986 ps
T1117 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1982100357 Aug 10 05:58:29 PM PDT 24 Aug 10 05:58:31 PM PDT 24 78827840 ps
T1118 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2796216178 Aug 10 05:58:43 PM PDT 24 Aug 10 05:58:46 PM PDT 24 101988239 ps
T283 /workspace/coverage/cover_reg_top/5.edn_csr_rw.67438292 Aug 10 05:58:48 PM PDT 24 Aug 10 05:58:49 PM PDT 24 24893911 ps
T284 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3927710544 Aug 10 05:59:03 PM PDT 24 Aug 10 05:59:04 PM PDT 24 21273258 ps
T1119 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1911943422 Aug 10 05:58:57 PM PDT 24 Aug 10 05:58:58 PM PDT 24 31651053 ps
T1120 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.839683530 Aug 10 05:58:51 PM PDT 24 Aug 10 05:58:52 PM PDT 24 54040595 ps
T1121 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1838916808 Aug 10 05:58:48 PM PDT 24 Aug 10 05:58:49 PM PDT 24 63566571 ps
T1122 /workspace/coverage/cover_reg_top/21.edn_intr_test.1657450494 Aug 10 05:58:57 PM PDT 24 Aug 10 05:58:58 PM PDT 24 13935633 ps
T1123 /workspace/coverage/cover_reg_top/47.edn_intr_test.4124932961 Aug 10 05:58:53 PM PDT 24 Aug 10 05:58:54 PM PDT 24 11448775 ps
T1124 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3820495412 Aug 10 05:58:36 PM PDT 24 Aug 10 05:58:38 PM PDT 24 23320469 ps
T1125 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3905896587 Aug 10 05:58:36 PM PDT 24 Aug 10 05:58:39 PM PDT 24 78199442 ps
T1126 /workspace/coverage/cover_reg_top/45.edn_intr_test.2887931357 Aug 10 05:58:47 PM PDT 24 Aug 10 05:58:47 PM PDT 24 32959025 ps
T1127 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.353110629 Aug 10 05:58:45 PM PDT 24 Aug 10 05:58:47 PM PDT 24 150044894 ps
T1128 /workspace/coverage/cover_reg_top/49.edn_intr_test.1895964599 Aug 10 05:58:53 PM PDT 24 Aug 10 05:58:54 PM PDT 24 44311635 ps
T1129 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1388466293 Aug 10 05:58:29 PM PDT 24 Aug 10 05:58:30 PM PDT 24 13557296 ps

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1707024179
Short name T6
Test name
Test status
Simulation time 103635319794 ps
CPU time 2673.75 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 08:07:08 PM PDT 24
Peak memory 232016 kb
Host smart-2c41b930-9318-4535-a528-5a90f34d9327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707024179 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1707024179
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_genbits.2623773680
Short name T21
Test name
Test status
Simulation time 69700612 ps
CPU time 1.41 seconds
Started Aug 10 07:22:21 PM PDT 24
Finished Aug 10 07:22:22 PM PDT 24
Peak memory 219972 kb
Host smart-a11f3284-3ccc-4f01-8958-48c39884c98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623773680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2623773680
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3776020906
Short name T16
Test name
Test status
Simulation time 476824406 ps
CPU time 4.79 seconds
Started Aug 10 07:21:27 PM PDT 24
Finished Aug 10 07:21:32 PM PDT 24
Peak memory 239812 kb
Host smart-407fd87f-2a77-4ad9-af25-23488238fbd7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776020906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3776020906
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/173.edn_alert.2783326942
Short name T38
Test name
Test status
Simulation time 47382906 ps
CPU time 1.15 seconds
Started Aug 10 07:24:14 PM PDT 24
Finished Aug 10 07:24:15 PM PDT 24
Peak memory 218716 kb
Host smart-93fccc22-233a-4774-a7f3-51c00f75f560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783326942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2783326942
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/193.edn_alert.1763299153
Short name T45
Test name
Test status
Simulation time 118306742 ps
CPU time 1.3 seconds
Started Aug 10 07:24:18 PM PDT 24
Finished Aug 10 07:24:19 PM PDT 24
Peak memory 220308 kb
Host smart-dedd9dec-4804-41a5-9468-aa1ac117591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763299153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1763299153
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/2.edn_disable.1899319518
Short name T77
Test name
Test status
Simulation time 13440011 ps
CPU time 0.92 seconds
Started Aug 10 07:21:37 PM PDT 24
Finished Aug 10 07:21:38 PM PDT 24
Peak memory 216804 kb
Host smart-06658479-5a0e-4014-a3f7-67c99f2fcf0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899319518 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1899319518
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/177.edn_alert.3405528046
Short name T56
Test name
Test status
Simulation time 70794845 ps
CPU time 1.27 seconds
Started Aug 10 07:24:09 PM PDT 24
Finished Aug 10 07:24:10 PM PDT 24
Peak memory 218452 kb
Host smart-7e90b700-c047-41d2-b308-14c494e91043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405528046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3405528046
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/170.edn_alert.443378385
Short name T2
Test name
Test status
Simulation time 74469658 ps
CPU time 1.06 seconds
Started Aug 10 07:24:12 PM PDT 24
Finished Aug 10 07:24:13 PM PDT 24
Peak memory 219512 kb
Host smart-74bde6ab-3e32-42ec-89b8-b5e0f694ee6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443378385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.443378385
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3531246928
Short name T54
Test name
Test status
Simulation time 67540669 ps
CPU time 1 seconds
Started Aug 10 07:23:02 PM PDT 24
Finished Aug 10 07:23:03 PM PDT 24
Peak memory 219708 kb
Host smart-04d6f1af-32bc-4b73-95dc-4521394bf319
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531246928 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3531246928
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_regwen.2104234330
Short name T29
Test name
Test status
Simulation time 31451842 ps
CPU time 0.97 seconds
Started Aug 10 07:21:26 PM PDT 24
Finished Aug 10 07:21:28 PM PDT 24
Peak memory 207140 kb
Host smart-d5cdd354-5f15-4cd2-b65d-9a331720cfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104234330 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2104234330
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1013684007
Short name T142
Test name
Test status
Simulation time 55795329 ps
CPU time 1.46 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 219504 kb
Host smart-567ab6e1-fef9-4b66-8e58-21eb49793959
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013684007 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1013684007
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_disable.797723287
Short name T215
Test name
Test status
Simulation time 28816990 ps
CPU time 0.81 seconds
Started Aug 10 07:23:10 PM PDT 24
Finished Aug 10 07:23:11 PM PDT 24
Peak memory 216484 kb
Host smart-2b105c26-be13-4d39-8206-adcd9ca99f7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797723287 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.797723287
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4233882162
Short name T306
Test name
Test status
Simulation time 66929140 ps
CPU time 2.25 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:31 PM PDT 24
Peak memory 207396 kb
Host smart-87a1419a-f97f-4df0-a94d-1a4f9b9fb8eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233882162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.4233882162
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/default/159.edn_alert.1922799122
Short name T255
Test name
Test status
Simulation time 63438693 ps
CPU time 1.06 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 218700 kb
Host smart-02fe8382-b58f-49f9-a99b-3b5b6761fb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922799122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.1922799122
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert.13133930
Short name T11
Test name
Test status
Simulation time 287538408 ps
CPU time 1.47 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:25 PM PDT 24
Peak memory 220084 kb
Host smart-b151f5e3-35d7-4fcd-b254-1fe512786f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13133930 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.13133930
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1070257282
Short name T237
Test name
Test status
Simulation time 28766073221 ps
CPU time 327.4 seconds
Started Aug 10 07:22:49 PM PDT 24
Finished Aug 10 07:28:17 PM PDT 24
Peak memory 217788 kb
Host smart-77947c13-b63d-4961-b645-cb73c5fd10e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070257282 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1070257282
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_disable.465441038
Short name T160
Test name
Test status
Simulation time 72565855 ps
CPU time 0.91 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:16 PM PDT 24
Peak memory 219216 kb
Host smart-31b6c047-6cf5-46a4-b326-7378e0ef6189
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465441038 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.465441038
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable.3407111072
Short name T201
Test name
Test status
Simulation time 39534572 ps
CPU time 0.88 seconds
Started Aug 10 07:22:11 PM PDT 24
Finished Aug 10 07:22:12 PM PDT 24
Peak memory 219188 kb
Host smart-1934d4bc-f029-40ae-9c6d-9f964cf3deca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407111072 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3407111072
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable.3918250554
Short name T219
Test name
Test status
Simulation time 11028485 ps
CPU time 0.87 seconds
Started Aug 10 07:22:25 PM PDT 24
Finished Aug 10 07:22:26 PM PDT 24
Peak memory 216508 kb
Host smart-356faca1-0a82-4a20-9108-5b4ad71c1fee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918250554 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3918250554
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/65.edn_err.1354298594
Short name T194
Test name
Test status
Simulation time 35709856 ps
CPU time 0.86 seconds
Started Aug 10 07:23:20 PM PDT 24
Finished Aug 10 07:23:20 PM PDT 24
Peak memory 218652 kb
Host smart-6ef70532-bb76-4bca-a999-d2624d274a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354298594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1354298594
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2983255653
Short name T278
Test name
Test status
Simulation time 13354382 ps
CPU time 0.92 seconds
Started Aug 10 05:58:35 PM PDT 24
Finished Aug 10 05:58:36 PM PDT 24
Peak memory 206796 kb
Host smart-bded7929-5107-483a-92f6-d787d1357f94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983255653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2983255653
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/default/177.edn_genbits.1875742975
Short name T250
Test name
Test status
Simulation time 40446736 ps
CPU time 1.41 seconds
Started Aug 10 07:24:18 PM PDT 24
Finished Aug 10 07:24:19 PM PDT 24
Peak memory 220284 kb
Host smart-c89c5ffd-9b3b-48fc-8066-12467428087b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875742975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1875742975
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.1063319956
Short name T269
Test name
Test status
Simulation time 145306269 ps
CPU time 1.22 seconds
Started Aug 10 07:24:11 PM PDT 24
Finished Aug 10 07:24:13 PM PDT 24
Peak memory 218284 kb
Host smart-1bfd2e86-51f6-4e25-870c-a11a7560c38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063319956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.1063319956
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2237556819
Short name T233
Test name
Test status
Simulation time 214079485667 ps
CPU time 1256.92 seconds
Started Aug 10 07:22:10 PM PDT 24
Finished Aug 10 07:43:07 PM PDT 24
Peak memory 225544 kb
Host smart-44ba5f86-e157-4e98-a21f-ab91c888fbbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237556819 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2237556819
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.3009068527
Short name T190
Test name
Test status
Simulation time 69750541 ps
CPU time 1.16 seconds
Started Aug 10 07:23:53 PM PDT 24
Finished Aug 10 07:23:54 PM PDT 24
Peak memory 219652 kb
Host smart-f1c12708-1a54-4d08-a12f-6b6aa296eefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009068527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3009068527
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/262.edn_genbits.825485812
Short name T295
Test name
Test status
Simulation time 96347502 ps
CPU time 1.29 seconds
Started Aug 10 07:24:34 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 218676 kb
Host smart-d836b24f-b4bb-4ba4-9a10-3e29d8d19621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825485812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.825485812
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3330687479
Short name T722
Test name
Test status
Simulation time 34607596 ps
CPU time 1.18 seconds
Started Aug 10 07:23:44 PM PDT 24
Finished Aug 10 07:23:45 PM PDT 24
Peak memory 218696 kb
Host smart-031c2957-489e-42ca-90d5-37e733866f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330687479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3330687479
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/192.edn_alert.2299644274
Short name T746
Test name
Test status
Simulation time 67793700 ps
CPU time 1.27 seconds
Started Aug 10 07:24:17 PM PDT 24
Finished Aug 10 07:24:18 PM PDT 24
Peak memory 219680 kb
Host smart-ae8d6de1-aee9-4540-8138-5ec4147ca1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299644274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2299644274
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/11.edn_intr.527555415
Short name T5
Test name
Test status
Simulation time 22708011 ps
CPU time 0.97 seconds
Started Aug 10 07:22:02 PM PDT 24
Finished Aug 10 07:22:03 PM PDT 24
Peak memory 216180 kb
Host smart-1030367e-cd45-4f0d-87b2-48e45a68f39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527555415 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.527555415
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/128.edn_alert.3621557799
Short name T442
Test name
Test status
Simulation time 48395103 ps
CPU time 1.21 seconds
Started Aug 10 07:23:57 PM PDT 24
Finished Aug 10 07:23:59 PM PDT 24
Peak memory 219180 kb
Host smart-743ea833-b524-45b2-9ebe-6037953f0977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621557799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3621557799
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.2729710508
Short name T128
Test name
Test status
Simulation time 91476287 ps
CPU time 1.4 seconds
Started Aug 10 07:23:51 PM PDT 24
Finished Aug 10 07:23:52 PM PDT 24
Peak memory 219688 kb
Host smart-71648482-4559-4a3d-a6f8-a0ced13f2067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729710508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2729710508
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/183.edn_alert.507556724
Short name T646
Test name
Test status
Simulation time 73653089 ps
CPU time 1.22 seconds
Started Aug 10 07:24:09 PM PDT 24
Finished Aug 10 07:24:10 PM PDT 24
Peak memory 218672 kb
Host smart-f05a9f67-2fcb-4656-afa6-d69b729ef709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507556724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.507556724
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/54.edn_alert.4068817810
Short name T350
Test name
Test status
Simulation time 23459507 ps
CPU time 1.12 seconds
Started Aug 10 07:23:22 PM PDT 24
Finished Aug 10 07:23:23 PM PDT 24
Peak memory 218440 kb
Host smart-634ba55a-f68c-4493-8577-950e041dc39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068817810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.4068817810
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.883112388
Short name T182
Test name
Test status
Simulation time 20124387 ps
CPU time 1.13 seconds
Started Aug 10 07:23:38 PM PDT 24
Finished Aug 10 07:23:39 PM PDT 24
Peak memory 215364 kb
Host smart-d0978bac-8210-4352-a139-2a533c5f556b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883112388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.883112388
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/0.edn_disable.3335668435
Short name T208
Test name
Test status
Simulation time 32730795 ps
CPU time 0.83 seconds
Started Aug 10 07:21:29 PM PDT 24
Finished Aug 10 07:21:30 PM PDT 24
Peak memory 219248 kb
Host smart-d13c3560-106c-4928-9e74-331f4682b079
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335668435 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3335668435
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/33.edn_intr.3757150613
Short name T90
Test name
Test status
Simulation time 26477507 ps
CPU time 0.91 seconds
Started Aug 10 07:22:55 PM PDT 24
Finished Aug 10 07:22:57 PM PDT 24
Peak memory 216112 kb
Host smart-973642d1-ee82-4b6d-8f92-0e6a4ac5220b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757150613 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3757150613
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/289.edn_genbits.2178815944
Short name T337
Test name
Test status
Simulation time 83993906 ps
CPU time 1.82 seconds
Started Aug 10 07:24:28 PM PDT 24
Finished Aug 10 07:24:30 PM PDT 24
Peak memory 220044 kb
Host smart-ab011c44-5926-4227-9fd6-6e3ac1c84414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178815944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2178815944
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.810284761
Short name T74
Test name
Test status
Simulation time 48305898 ps
CPU time 1.67 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 218480 kb
Host smart-3a6567a8-4799-4173-ba4b-cae2ced6b1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810284761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.810284761
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert.4151419013
Short name T556
Test name
Test status
Simulation time 44892516 ps
CPU time 1.13 seconds
Started Aug 10 07:21:29 PM PDT 24
Finished Aug 10 07:21:30 PM PDT 24
Peak memory 219704 kb
Host smart-d4292390-8a4b-4d1a-ac12-1273f7cc46af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151419013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.4151419013
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.901294381
Short name T123
Test name
Test status
Simulation time 38967663 ps
CPU time 1.08 seconds
Started Aug 10 07:21:56 PM PDT 24
Finished Aug 10 07:21:58 PM PDT 24
Peak memory 217024 kb
Host smart-c2bc0851-ab49-4b48-8582-71ed481d3476
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901294381 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.901294381
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/118.edn_alert.1910478681
Short name T173
Test name
Test status
Simulation time 26674530 ps
CPU time 1.21 seconds
Started Aug 10 07:23:48 PM PDT 24
Finished Aug 10 07:23:50 PM PDT 24
Peak memory 219536 kb
Host smart-1dff4e88-d588-4a5f-adb9-fa938683e110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910478681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1910478681
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/122.edn_alert.3840738799
Short name T178
Test name
Test status
Simulation time 26379669 ps
CPU time 1.26 seconds
Started Aug 10 07:23:50 PM PDT 24
Finished Aug 10 07:23:51 PM PDT 24
Peak memory 219584 kb
Host smart-05980daf-67e4-4aaf-91bb-62200d96650c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840738799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3840738799
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3182983642
Short name T866
Test name
Test status
Simulation time 264055071 ps
CPU time 1.11 seconds
Started Aug 10 07:22:11 PM PDT 24
Finished Aug 10 07:22:12 PM PDT 24
Peak memory 219460 kb
Host smart-c6c0fd5a-6df4-4c32-9331-8d60230719e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182983642 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3182983642
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3351926503
Short name T144
Test name
Test status
Simulation time 55804930 ps
CPU time 1 seconds
Started Aug 10 07:22:43 PM PDT 24
Finished Aug 10 07:22:44 PM PDT 24
Peak memory 219360 kb
Host smart-d3619a7d-42f5-4cc9-8a3f-75fa7d18b904
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351926503 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3351926503
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1376637213
Short name T207
Test name
Test status
Simulation time 66410754 ps
CPU time 1.2 seconds
Started Aug 10 07:22:33 PM PDT 24
Finished Aug 10 07:22:35 PM PDT 24
Peak memory 217004 kb
Host smart-2545367c-44b5-471c-9275-27939f92f61d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376637213 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1376637213
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3739957050
Short name T116
Test name
Test status
Simulation time 265084602 ps
CPU time 1.08 seconds
Started Aug 10 07:22:56 PM PDT 24
Finished Aug 10 07:22:57 PM PDT 24
Peak memory 219640 kb
Host smart-c111856f-43ae-47ea-8373-7d523c16c97f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739957050 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3739957050
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_disable.3501293436
Short name T223
Test name
Test status
Simulation time 16190553 ps
CPU time 0.86 seconds
Started Aug 10 07:21:50 PM PDT 24
Finished Aug 10 07:21:51 PM PDT 24
Peak memory 215772 kb
Host smart-eb6c26a1-7952-423a-b1b0-02ce189d6671
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501293436 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3501293436
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.3175148764
Short name T198
Test name
Test status
Simulation time 19465165 ps
CPU time 1 seconds
Started Aug 10 07:21:48 PM PDT 24
Finished Aug 10 07:21:49 PM PDT 24
Peak memory 219944 kb
Host smart-c705a84c-f6ca-4813-9980-8f78c3f6c7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175148764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3175148764
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/13.edn_alert_test.2809697608
Short name T71
Test name
Test status
Simulation time 78628618 ps
CPU time 0.89 seconds
Started Aug 10 07:22:12 PM PDT 24
Finished Aug 10 07:22:13 PM PDT 24
Peak memory 206580 kb
Host smart-99b4abcf-38d0-4d08-b03d-2bd701995353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809697608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2809697608
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/180.edn_genbits.481175316
Short name T53
Test name
Test status
Simulation time 73393143 ps
CPU time 1.55 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:20 PM PDT 24
Peak memory 218928 kb
Host smart-ee2c5823-a7c3-46c8-9496-5d51d0bba9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481175316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.481175316
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2755382893
Short name T316
Test name
Test status
Simulation time 40035896 ps
CPU time 1.18 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 220968 kb
Host smart-401ef05d-048d-4f12-a982-c6a8e261511c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755382893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2755382893
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/0.edn_err.1284074618
Short name T200
Test name
Test status
Simulation time 52185022 ps
CPU time 0.87 seconds
Started Aug 10 07:21:26 PM PDT 24
Finished Aug 10 07:21:27 PM PDT 24
Peak memory 219948 kb
Host smart-1c4409ea-4731-4e16-b06c-9fa8d27dd04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284074618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1284074618
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/121.edn_genbits.3561971061
Short name T329
Test name
Test status
Simulation time 51953199 ps
CPU time 1.66 seconds
Started Aug 10 07:23:50 PM PDT 24
Finished Aug 10 07:23:52 PM PDT 24
Peak memory 219836 kb
Host smart-51ac3092-f6bd-4798-bd06-33fc88383087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561971061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3561971061
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2231402359
Short name T30
Test name
Test status
Simulation time 29596635 ps
CPU time 0.91 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:47 PM PDT 24
Peak memory 215912 kb
Host smart-8e54f6a1-36dd-4e9a-b91e-898916e6c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231402359 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2231402359
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1248603383
Short name T286
Test name
Test status
Simulation time 21235044 ps
CPU time 1.22 seconds
Started Aug 10 05:58:38 PM PDT 24
Finished Aug 10 05:58:40 PM PDT 24
Peak memory 207028 kb
Host smart-2651cec1-cf7e-4174-9a58-844681f13d4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248603383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1248603383
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4231653841
Short name T1113
Test name
Test status
Simulation time 54834365 ps
CPU time 1.68 seconds
Started Aug 10 05:58:44 PM PDT 24
Finished Aug 10 05:58:51 PM PDT 24
Peak memory 215304 kb
Host smart-370b0e99-c371-4cb2-a98b-e402ac7655b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231653841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4231653841
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1735259638
Short name T304
Test name
Test status
Simulation time 76912582 ps
CPU time 1.02 seconds
Started Aug 10 07:21:36 PM PDT 24
Finished Aug 10 07:21:37 PM PDT 24
Peak memory 219360 kb
Host smart-00c9cac5-eb66-463b-9ea4-21bf4a8f7f3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735259638 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1735259638
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_smoke.267591551
Short name T65
Test name
Test status
Simulation time 55217832 ps
CPU time 0.87 seconds
Started Aug 10 07:21:29 PM PDT 24
Finished Aug 10 07:21:30 PM PDT 24
Peak memory 215324 kb
Host smart-0da8216d-fbc3-4313-a3ca-f5d8c1c0c3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267591551 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.267591551
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/100.edn_alert.3885842596
Short name T303
Test name
Test status
Simulation time 48970918 ps
CPU time 1.27 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 219528 kb
Host smart-407c6652-22fe-4f97-b247-eafdbd8a33b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885842596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3885842596
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3061193378
Short name T883
Test name
Test status
Simulation time 106670418 ps
CPU time 1.19 seconds
Started Aug 10 07:23:50 PM PDT 24
Finished Aug 10 07:23:51 PM PDT 24
Peak memory 217536 kb
Host smart-f0133737-656b-4495-94b8-acfe2e2c68e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061193378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3061193378
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1991208808
Short name T41
Test name
Test status
Simulation time 35465711 ps
CPU time 1.47 seconds
Started Aug 10 07:23:38 PM PDT 24
Finished Aug 10 07:23:39 PM PDT 24
Peak memory 218496 kb
Host smart-8bd57001-223b-43e9-9799-6620b9f6226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991208808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1991208808
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1615139566
Short name T333
Test name
Test status
Simulation time 113733393 ps
CPU time 1.81 seconds
Started Aug 10 07:23:48 PM PDT 24
Finished Aug 10 07:23:50 PM PDT 24
Peak memory 218932 kb
Host smart-542eedeb-bf95-4a56-b730-e9c5bbd069c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615139566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1615139566
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1296711238
Short name T321
Test name
Test status
Simulation time 64478139 ps
CPU time 1.33 seconds
Started Aug 10 07:23:54 PM PDT 24
Finished Aug 10 07:23:55 PM PDT 24
Peak memory 218944 kb
Host smart-c1af888f-70a0-4e0a-8fb7-fbe1be64b13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296711238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1296711238
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3656552206
Short name T335
Test name
Test status
Simulation time 36394333 ps
CPU time 1.17 seconds
Started Aug 10 07:23:54 PM PDT 24
Finished Aug 10 07:23:56 PM PDT 24
Peak memory 218632 kb
Host smart-c0703cf3-03bc-46ee-9527-81744170c876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656552206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3656552206
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.4279796202
Short name T486
Test name
Test status
Simulation time 28094962 ps
CPU time 1.27 seconds
Started Aug 10 07:23:52 PM PDT 24
Finished Aug 10 07:23:53 PM PDT 24
Peak memory 218460 kb
Host smart-820c945c-eb92-445b-b299-2ff5dcda7fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279796202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.4279796202
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.748001723
Short name T935
Test name
Test status
Simulation time 41490293322 ps
CPU time 930.19 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:37:46 PM PDT 24
Peak memory 223648 kb
Host smart-2e1a21f5-e5a2-4813-84a0-1ad7706be6a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748001723 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.748001723
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.edn_genbits.1749411611
Short name T326
Test name
Test status
Simulation time 40687284 ps
CPU time 1.6 seconds
Started Aug 10 07:24:03 PM PDT 24
Finished Aug 10 07:24:05 PM PDT 24
Peak memory 218508 kb
Host smart-8d2b015f-736c-4343-9634-c019a48c0369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749411611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1749411611
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.173315800
Short name T340
Test name
Test status
Simulation time 42815111 ps
CPU time 1.7 seconds
Started Aug 10 07:24:13 PM PDT 24
Finished Aug 10 07:24:15 PM PDT 24
Peak memory 218564 kb
Host smart-dc51b11a-59ed-4e0f-8578-2055acb1ac49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173315800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.173315800
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3547426590
Short name T35
Test name
Test status
Simulation time 33174409 ps
CPU time 0.84 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 216028 kb
Host smart-6198d0b3-d5db-4ab2-9ef7-66f6c697f4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547426590 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3547426590
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/255.edn_genbits.133317111
Short name T488
Test name
Test status
Simulation time 77925098 ps
CPU time 1.46 seconds
Started Aug 10 07:24:29 PM PDT 24
Finished Aug 10 07:24:30 PM PDT 24
Peak memory 220076 kb
Host smart-52c894c5-48d2-46c4-a1a7-bc59efbe384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133317111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.133317111
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.2632937716
Short name T112
Test name
Test status
Simulation time 22917900 ps
CPU time 1.19 seconds
Started Aug 10 07:23:56 PM PDT 24
Finished Aug 10 07:23:57 PM PDT 24
Peak memory 220448 kb
Host smart-39293e40-e74f-4013-8fb4-2543b61f35c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632937716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2632937716
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/153.edn_alert.764386396
Short name T967
Test name
Test status
Simulation time 26316840 ps
CPU time 1.25 seconds
Started Aug 10 07:23:59 PM PDT 24
Finished Aug 10 07:24:01 PM PDT 24
Peak memory 219732 kb
Host smart-187b9bb0-cf63-43f2-acb6-5890ddd0e73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764386396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.764386396
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3286842416
Short name T1004
Test name
Test status
Simulation time 25919166 ps
CPU time 1.16 seconds
Started Aug 10 05:58:46 PM PDT 24
Finished Aug 10 05:58:48 PM PDT 24
Peak memory 206868 kb
Host smart-cdae0cfa-e175-4b4b-b08c-f657020d6522
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286842416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3286842416
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.4024471920
Short name T1038
Test name
Test status
Simulation time 128511059 ps
CPU time 1.98 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:30 PM PDT 24
Peak memory 206964 kb
Host smart-84c26091-5112-48bf-aade-0fd63fa88dca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024471920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.4024471920
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2384131318
Short name T285
Test name
Test status
Simulation time 31295150 ps
CPU time 0.95 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:48 PM PDT 24
Peak memory 206720 kb
Host smart-d65cea23-b730-42a3-9802-4cf1dcdcc7bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384131318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2384131318
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.915529215
Short name T1088
Test name
Test status
Simulation time 20537349 ps
CPU time 1.03 seconds
Started Aug 10 05:58:29 PM PDT 24
Finished Aug 10 05:58:30 PM PDT 24
Peak memory 206908 kb
Host smart-4f4fff28-69b9-4bc5-9bf0-d2ce7750ac2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915529215 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.915529215
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2526750745
Short name T1052
Test name
Test status
Simulation time 46670907 ps
CPU time 0.9 seconds
Started Aug 10 05:58:29 PM PDT 24
Finished Aug 10 05:58:30 PM PDT 24
Peak memory 206732 kb
Host smart-f5e451fe-b795-4c39-87c4-e36271481a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526750745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2526750745
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2529498707
Short name T1055
Test name
Test status
Simulation time 37998498 ps
CPU time 0.77 seconds
Started Aug 10 05:58:52 PM PDT 24
Finished Aug 10 05:58:53 PM PDT 24
Peak memory 206336 kb
Host smart-8fc47afb-018f-421e-bf22-e5d46d977c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529498707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2529498707
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3873496258
Short name T1076
Test name
Test status
Simulation time 42052070 ps
CPU time 1.04 seconds
Started Aug 10 05:58:41 PM PDT 24
Finished Aug 10 05:58:42 PM PDT 24
Peak memory 207016 kb
Host smart-5dae71fa-4977-4740-be16-4eed3804487b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873496258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3873496258
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.805743938
Short name T1082
Test name
Test status
Simulation time 51695151 ps
CPU time 2.06 seconds
Started Aug 10 05:58:31 PM PDT 24
Finished Aug 10 05:58:33 PM PDT 24
Peak memory 215136 kb
Host smart-cc401aad-dfef-4c74-8d01-2823a0b0e7a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805743938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.805743938
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3887467857
Short name T280
Test name
Test status
Simulation time 18050391 ps
CPU time 1.26 seconds
Started Aug 10 05:58:31 PM PDT 24
Finished Aug 10 05:58:32 PM PDT 24
Peak memory 206924 kb
Host smart-f6bf8c24-1ba5-4317-aab4-0d9d2a55be18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887467857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3887467857
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.321702476
Short name T1070
Test name
Test status
Simulation time 373218170 ps
CPU time 3.04 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:32 PM PDT 24
Peak memory 206900 kb
Host smart-7ff22e84-b672-4bc1-89f2-3369ddff2970
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321702476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.321702476
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4203686716
Short name T1037
Test name
Test status
Simulation time 72259913 ps
CPU time 0.93 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:29 PM PDT 24
Peak memory 206884 kb
Host smart-4795959a-38be-4534-8b38-a2c863811f87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203686716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.4203686716
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.170433222
Short name T1097
Test name
Test status
Simulation time 387467665 ps
CPU time 1.62 seconds
Started Aug 10 05:58:43 PM PDT 24
Finished Aug 10 05:58:44 PM PDT 24
Peak memory 215284 kb
Host smart-a050d268-a955-4f4b-984a-0df483e3f92a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170433222 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.170433222
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.4119075189
Short name T1011
Test name
Test status
Simulation time 20755528 ps
CPU time 0.95 seconds
Started Aug 10 05:58:29 PM PDT 24
Finished Aug 10 05:58:30 PM PDT 24
Peak memory 206884 kb
Host smart-ebeb9f1b-5c9e-4069-894d-0ee88bf0bc88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119075189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.4119075189
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3528201844
Short name T1108
Test name
Test status
Simulation time 28423599 ps
CPU time 0.93 seconds
Started Aug 10 05:58:39 PM PDT 24
Finished Aug 10 05:58:40 PM PDT 24
Peak memory 206652 kb
Host smart-1549762c-0a33-4993-aee6-df92375fbd09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528201844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3528201844
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.25440568
Short name T1042
Test name
Test status
Simulation time 136046117 ps
CPU time 1.29 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:50 PM PDT 24
Peak memory 206784 kb
Host smart-e54b76f7-72ed-4c51-a96e-5363e4e1a25f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25440568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outs
tanding.25440568
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1934030516
Short name T1114
Test name
Test status
Simulation time 72305028 ps
CPU time 1.86 seconds
Started Aug 10 05:58:29 PM PDT 24
Finished Aug 10 05:58:32 PM PDT 24
Peak memory 215208 kb
Host smart-62569550-eaee-4fbd-8688-6946c991ce56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934030516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1934030516
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2290820608
Short name T311
Test name
Test status
Simulation time 177939860 ps
CPU time 2.39 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:31 PM PDT 24
Peak memory 207064 kb
Host smart-23e5ad1d-c89f-4cc4-b5a7-149aeb30cdb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290820608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2290820608
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1749758443
Short name T1062
Test name
Test status
Simulation time 45878465 ps
CPU time 1.63 seconds
Started Aug 10 05:58:44 PM PDT 24
Finished Aug 10 05:58:46 PM PDT 24
Peak memory 215532 kb
Host smart-4773d628-34d8-4233-98da-5a614de93015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749758443 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1749758443
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.4211415530
Short name T282
Test name
Test status
Simulation time 20038626 ps
CPU time 0.86 seconds
Started Aug 10 05:58:37 PM PDT 24
Finished Aug 10 05:58:38 PM PDT 24
Peak memory 206608 kb
Host smart-68391d58-10cd-41fe-8f53-a82ab8346251
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211415530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.4211415530
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3536798111
Short name T1068
Test name
Test status
Simulation time 11479634 ps
CPU time 0.86 seconds
Started Aug 10 05:58:54 PM PDT 24
Finished Aug 10 05:58:55 PM PDT 24
Peak memory 206716 kb
Host smart-48c24273-0b6c-4ccf-b1f7-296f04ec2384
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536798111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3536798111
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.839683530
Short name T1120
Test name
Test status
Simulation time 54040595 ps
CPU time 1.13 seconds
Started Aug 10 05:58:51 PM PDT 24
Finished Aug 10 05:58:52 PM PDT 24
Peak memory 206956 kb
Host smart-8da2b809-804e-4bae-8960-bdba08bda7de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839683530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.839683530
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.190641952
Short name T1039
Test name
Test status
Simulation time 123378599 ps
CPU time 4.03 seconds
Started Aug 10 05:59:05 PM PDT 24
Finished Aug 10 05:59:09 PM PDT 24
Peak memory 215068 kb
Host smart-06d5e7aa-5ecf-410d-b43f-225576416ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190641952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.190641952
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1745194561
Short name T1032
Test name
Test status
Simulation time 228043578 ps
CPU time 1.6 seconds
Started Aug 10 05:58:53 PM PDT 24
Finished Aug 10 05:58:55 PM PDT 24
Peak memory 207028 kb
Host smart-26571416-996f-4810-85ac-c8af4173e14f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745194561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1745194561
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1080070440
Short name T1028
Test name
Test status
Simulation time 66508009 ps
CPU time 1.1 seconds
Started Aug 10 05:58:42 PM PDT 24
Finished Aug 10 05:58:43 PM PDT 24
Peak memory 215212 kb
Host smart-e2c30d2f-5d03-44f6-b2bc-be2c015fe99b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080070440 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1080070440
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2740680098
Short name T1116
Test name
Test status
Simulation time 20224986 ps
CPU time 0.93 seconds
Started Aug 10 05:58:39 PM PDT 24
Finished Aug 10 05:58:40 PM PDT 24
Peak memory 206852 kb
Host smart-66b55378-ea0f-4b33-970e-c1e6ee7df276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740680098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2740680098
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.608836796
Short name T1041
Test name
Test status
Simulation time 29090151 ps
CPU time 1.03 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 206840 kb
Host smart-9379f0de-ad9c-416a-ae44-283f0b5a7803
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608836796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.608836796
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1634285330
Short name T1022
Test name
Test status
Simulation time 558490086 ps
CPU time 2.56 seconds
Started Aug 10 05:58:38 PM PDT 24
Finished Aug 10 05:58:40 PM PDT 24
Peak memory 214984 kb
Host smart-08dd9da0-3c63-4c3f-a1cb-fecd7ce936a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634285330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1634285330
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4271441409
Short name T313
Test name
Test status
Simulation time 353751266 ps
CPU time 1.48 seconds
Started Aug 10 05:59:00 PM PDT 24
Finished Aug 10 05:59:01 PM PDT 24
Peak memory 206820 kb
Host smart-70db7c24-37c8-4681-a212-57ba1cf8433b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271441409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.4271441409
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3794721354
Short name T1029
Test name
Test status
Simulation time 55569093 ps
CPU time 1.03 seconds
Started Aug 10 05:58:38 PM PDT 24
Finished Aug 10 05:58:39 PM PDT 24
Peak memory 206940 kb
Host smart-f7064bfa-1e25-48ac-9af9-53420783a30b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794721354 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3794721354
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2160628336
Short name T1034
Test name
Test status
Simulation time 14588620 ps
CPU time 0.93 seconds
Started Aug 10 05:58:40 PM PDT 24
Finished Aug 10 05:58:41 PM PDT 24
Peak memory 206788 kb
Host smart-034de48a-f3c9-44f5-8977-26aa932dc71e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160628336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2160628336
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1528739400
Short name T1111
Test name
Test status
Simulation time 11907933 ps
CPU time 0.87 seconds
Started Aug 10 05:58:42 PM PDT 24
Finished Aug 10 05:58:43 PM PDT 24
Peak memory 206740 kb
Host smart-1840b87a-e285-46fb-91ee-5290f9f66d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528739400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1528739400
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.967285910
Short name T1058
Test name
Test status
Simulation time 16638970 ps
CPU time 0.99 seconds
Started Aug 10 05:59:00 PM PDT 24
Finished Aug 10 05:59:01 PM PDT 24
Peak memory 206748 kb
Host smart-cfb6cffa-839c-438b-8097-453b4bb1fab9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967285910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.967285910
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2693557878
Short name T1013
Test name
Test status
Simulation time 103478072 ps
CPU time 2.14 seconds
Started Aug 10 05:58:37 PM PDT 24
Finished Aug 10 05:58:39 PM PDT 24
Peak memory 214996 kb
Host smart-7b1616b0-74ac-4536-906c-7d79bc28c75a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693557878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2693557878
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.826646425
Short name T302
Test name
Test status
Simulation time 160552608 ps
CPU time 1.53 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 215084 kb
Host smart-6aa02bdb-f509-404b-8b96-f7063b1973e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826646425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.826646425
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.170276606
Short name T1099
Test name
Test status
Simulation time 53988120 ps
CPU time 0.96 seconds
Started Aug 10 05:59:00 PM PDT 24
Finished Aug 10 05:59:01 PM PDT 24
Peak memory 206820 kb
Host smart-8763e78a-8d25-4d10-987d-f24528f18b6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170276606 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.170276606
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3538848084
Short name T1015
Test name
Test status
Simulation time 21836760 ps
CPU time 0.99 seconds
Started Aug 10 05:59:00 PM PDT 24
Finished Aug 10 05:59:01 PM PDT 24
Peak memory 206672 kb
Host smart-58102c8a-2c61-4aa7-ab40-04b5232a89e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538848084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3538848084
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3923129096
Short name T1106
Test name
Test status
Simulation time 23989546 ps
CPU time 0.83 seconds
Started Aug 10 05:58:44 PM PDT 24
Finished Aug 10 05:58:45 PM PDT 24
Peak memory 206684 kb
Host smart-a292629e-e1b1-4dac-9d4f-0d4c9b5783c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923129096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3923129096
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.5750721
Short name T1075
Test name
Test status
Simulation time 77572834 ps
CPU time 1.36 seconds
Started Aug 10 05:58:57 PM PDT 24
Finished Aug 10 05:58:58 PM PDT 24
Peak memory 206728 kb
Host smart-188581df-daca-4ce2-bf44-5e9364bf4279
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5750721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outs
tanding.5750721
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1019176068
Short name T1027
Test name
Test status
Simulation time 437322214 ps
CPU time 2.52 seconds
Started Aug 10 05:58:37 PM PDT 24
Finished Aug 10 05:58:40 PM PDT 24
Peak memory 215152 kb
Host smart-7ea6b5f3-0ee7-498c-9571-f047ebe86163
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019176068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1019176068
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2882455563
Short name T1080
Test name
Test status
Simulation time 76881883 ps
CPU time 1.51 seconds
Started Aug 10 05:58:37 PM PDT 24
Finished Aug 10 05:58:39 PM PDT 24
Peak memory 207176 kb
Host smart-b69c2d8e-913a-4479-ae11-dc3c87a7126e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882455563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2882455563
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2224783084
Short name T1003
Test name
Test status
Simulation time 94617801 ps
CPU time 1.49 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 215232 kb
Host smart-67fdb982-8da1-4c8c-94e0-95897baa4451
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224783084 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2224783084
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.927657138
Short name T275
Test name
Test status
Simulation time 29165973 ps
CPU time 0.92 seconds
Started Aug 10 05:58:40 PM PDT 24
Finished Aug 10 05:58:41 PM PDT 24
Peak memory 206800 kb
Host smart-c6496095-4831-42bb-bc74-0ad58a9c0fbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927657138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.927657138
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1070337265
Short name T1025
Test name
Test status
Simulation time 47341416 ps
CPU time 0.86 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:48 PM PDT 24
Peak memory 206720 kb
Host smart-bd510f94-8424-42a7-91ac-141ba8dbdaa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070337265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1070337265
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2235014978
Short name T998
Test name
Test status
Simulation time 188214641 ps
CPU time 1.95 seconds
Started Aug 10 05:58:37 PM PDT 24
Finished Aug 10 05:58:39 PM PDT 24
Peak memory 215056 kb
Host smart-4e3e4047-2df1-4757-8d77-53017dc37b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235014978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2235014978
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.216687288
Short name T310
Test name
Test status
Simulation time 85435357 ps
CPU time 2.42 seconds
Started Aug 10 05:58:37 PM PDT 24
Finished Aug 10 05:58:40 PM PDT 24
Peak memory 207048 kb
Host smart-cd73a306-b350-4b08-b372-99ca0848c8a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216687288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.216687288
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.546117310
Short name T1020
Test name
Test status
Simulation time 107317725 ps
CPU time 1.08 seconds
Started Aug 10 05:58:37 PM PDT 24
Finished Aug 10 05:58:38 PM PDT 24
Peak memory 206860 kb
Host smart-9a7bad2b-3a93-4086-ae21-296c5f4a1f80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546117310 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.546117310
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2721926257
Short name T288
Test name
Test status
Simulation time 27607254 ps
CPU time 0.82 seconds
Started Aug 10 05:58:38 PM PDT 24
Finished Aug 10 05:58:39 PM PDT 24
Peak memory 206644 kb
Host smart-1b96a744-4fdc-4700-bd54-71773ab23cf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721926257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2721926257
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3582645487
Short name T1112
Test name
Test status
Simulation time 51820574 ps
CPU time 0.89 seconds
Started Aug 10 05:58:40 PM PDT 24
Finished Aug 10 05:58:41 PM PDT 24
Peak memory 206692 kb
Host smart-1158b605-a4e0-46b4-9aae-22dbfe887190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582645487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3582645487
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3032549017
Short name T1063
Test name
Test status
Simulation time 69694550 ps
CPU time 1.52 seconds
Started Aug 10 05:58:38 PM PDT 24
Finished Aug 10 05:58:39 PM PDT 24
Peak memory 206800 kb
Host smart-2ee7a610-7800-4f06-84e9-a744e5a8c7e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032549017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3032549017
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1277511910
Short name T1049
Test name
Test status
Simulation time 71461798 ps
CPU time 2.51 seconds
Started Aug 10 05:58:36 PM PDT 24
Finished Aug 10 05:58:39 PM PDT 24
Peak memory 215248 kb
Host smart-f9b14423-7a31-48f8-8ea5-ac739100b45f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277511910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1277511910
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2984995801
Short name T1036
Test name
Test status
Simulation time 246567220 ps
CPU time 1.63 seconds
Started Aug 10 05:58:41 PM PDT 24
Finished Aug 10 05:58:43 PM PDT 24
Peak memory 215220 kb
Host smart-7cedbf3f-8411-45a3-a712-2e8a816e39ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984995801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2984995801
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.691213559
Short name T1065
Test name
Test status
Simulation time 135126403 ps
CPU time 1.31 seconds
Started Aug 10 05:58:55 PM PDT 24
Finished Aug 10 05:58:57 PM PDT 24
Peak memory 215132 kb
Host smart-3079e10b-508c-4ff8-b5e6-cba5f26f2da5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691213559 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.691213559
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2842775651
Short name T287
Test name
Test status
Simulation time 128192702 ps
CPU time 0.9 seconds
Started Aug 10 05:58:53 PM PDT 24
Finished Aug 10 05:58:54 PM PDT 24
Peak memory 206764 kb
Host smart-d6452c44-f818-4699-9aca-c81c97056ca6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842775651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2842775651
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.761225385
Short name T1030
Test name
Test status
Simulation time 22912789 ps
CPU time 0.83 seconds
Started Aug 10 05:58:49 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 206688 kb
Host smart-50604a43-9ad4-4972-8480-474d48482dcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761225385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.761225385
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.715032627
Short name T289
Test name
Test status
Simulation time 52518194 ps
CPU time 1.1 seconds
Started Aug 10 05:58:57 PM PDT 24
Finished Aug 10 05:58:59 PM PDT 24
Peak memory 206968 kb
Host smart-4eb37448-4670-462f-86a2-e26ac0b5889c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715032627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.715032627
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.459121196
Short name T1103
Test name
Test status
Simulation time 38510708 ps
CPU time 2.55 seconds
Started Aug 10 05:58:36 PM PDT 24
Finished Aug 10 05:58:39 PM PDT 24
Peak memory 215160 kb
Host smart-2bcd644b-334c-44fa-9797-5a1159e57ac1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459121196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.459121196
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2345208398
Short name T1098
Test name
Test status
Simulation time 477697896 ps
CPU time 8.17 seconds
Started Aug 10 05:58:49 PM PDT 24
Finished Aug 10 05:58:57 PM PDT 24
Peak memory 215088 kb
Host smart-84c18dd5-7d92-4c78-8a66-fa099716ea4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345208398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2345208398
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2788523222
Short name T1007
Test name
Test status
Simulation time 56634593 ps
CPU time 1.34 seconds
Started Aug 10 05:58:55 PM PDT 24
Finished Aug 10 05:58:56 PM PDT 24
Peak memory 215164 kb
Host smart-9c0b2111-34e5-47b3-b111-98c4081fc07d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788523222 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2788523222
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.754621668
Short name T274
Test name
Test status
Simulation time 41977746 ps
CPU time 0.83 seconds
Started Aug 10 05:58:55 PM PDT 24
Finished Aug 10 05:59:01 PM PDT 24
Peak memory 206704 kb
Host smart-a9abae67-6f0d-4a5b-ad88-01e068427b95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754621668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.754621668
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.4251052687
Short name T1078
Test name
Test status
Simulation time 10826985 ps
CPU time 0.84 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:48 PM PDT 24
Peak memory 206780 kb
Host smart-9ab7e63d-2c73-46fd-a336-67a433226a75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251052687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.4251052687
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1661547069
Short name T290
Test name
Test status
Simulation time 25207363 ps
CPU time 1.01 seconds
Started Aug 10 05:59:03 PM PDT 24
Finished Aug 10 05:59:04 PM PDT 24
Peak memory 206916 kb
Host smart-5876e7e3-3899-4eac-853b-e496a20353b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661547069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1661547069
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.4252277941
Short name T1000
Test name
Test status
Simulation time 63824636 ps
CPU time 2.71 seconds
Started Aug 10 05:58:45 PM PDT 24
Finished Aug 10 05:58:48 PM PDT 24
Peak memory 215088 kb
Host smart-722e4b04-83e8-4a64-aa9f-e8ee18770680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252277941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.4252277941
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.468929277
Short name T301
Test name
Test status
Simulation time 274104438 ps
CPU time 2.04 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:50 PM PDT 24
Peak memory 206948 kb
Host smart-a20a1c44-2b8e-40ef-998a-20ac02799d42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468929277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.468929277
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1139579369
Short name T1016
Test name
Test status
Simulation time 53922694 ps
CPU time 1.55 seconds
Started Aug 10 05:58:55 PM PDT 24
Finished Aug 10 05:58:56 PM PDT 24
Peak memory 219708 kb
Host smart-5db3dd79-3368-4ffc-9383-ff5496482783
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139579369 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1139579369
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1641854176
Short name T271
Test name
Test status
Simulation time 13315899 ps
CPU time 0.9 seconds
Started Aug 10 05:58:53 PM PDT 24
Finished Aug 10 05:58:54 PM PDT 24
Peak memory 206812 kb
Host smart-958eea44-aaf9-4f37-a9bc-651df02d474b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641854176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1641854176
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.241433331
Short name T1110
Test name
Test status
Simulation time 14214358 ps
CPU time 0.9 seconds
Started Aug 10 05:58:45 PM PDT 24
Finished Aug 10 05:58:46 PM PDT 24
Peak memory 206700 kb
Host smart-9c6d7a63-afe9-4c97-866a-6ca623c15957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241433331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.241433331
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.25686454
Short name T1079
Test name
Test status
Simulation time 65584730 ps
CPU time 1.16 seconds
Started Aug 10 05:58:51 PM PDT 24
Finished Aug 10 05:58:53 PM PDT 24
Peak memory 206888 kb
Host smart-263dad6f-506d-4721-b909-a7c734cc7036
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25686454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_out
standing.25686454
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3598580915
Short name T1047
Test name
Test status
Simulation time 417964689 ps
CPU time 3.81 seconds
Started Aug 10 05:59:12 PM PDT 24
Finished Aug 10 05:59:15 PM PDT 24
Peak memory 215176 kb
Host smart-d003cb91-c842-4333-b6af-796e135683e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598580915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3598580915
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1274897920
Short name T308
Test name
Test status
Simulation time 450954854 ps
CPU time 7.57 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 05:59:10 PM PDT 24
Peak memory 206896 kb
Host smart-7fc77e75-4697-4c86-914c-3e9a5abe8afa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274897920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1274897920
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2684761057
Short name T1031
Test name
Test status
Simulation time 60591767 ps
CPU time 0.97 seconds
Started Aug 10 05:58:56 PM PDT 24
Finished Aug 10 05:58:57 PM PDT 24
Peak memory 206848 kb
Host smart-5fc4908e-5214-44c4-a54b-7d30df4b5d33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684761057 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2684761057
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1838916808
Short name T1121
Test name
Test status
Simulation time 63566571 ps
CPU time 0.92 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 206672 kb
Host smart-861c7c08-dbce-4c0d-b56a-74db85350ea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838916808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1838916808
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.228750825
Short name T1053
Test name
Test status
Simulation time 21827381 ps
CPU time 0.83 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:48 PM PDT 24
Peak memory 206628 kb
Host smart-ac91dc5b-6b8e-4a76-af0c-c26e5d05b035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228750825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.228750825
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2193882900
Short name T1077
Test name
Test status
Simulation time 39745035 ps
CPU time 1.07 seconds
Started Aug 10 05:58:58 PM PDT 24
Finished Aug 10 05:58:59 PM PDT 24
Peak memory 206940 kb
Host smart-830b485a-fcb2-4dc8-adf5-aa2a908d1a60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193882900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2193882900
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.4046833633
Short name T1061
Test name
Test status
Simulation time 242562820 ps
CPU time 3.99 seconds
Started Aug 10 05:58:45 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 218968 kb
Host smart-79d65162-2c8f-4e0a-a68b-9fd357899e2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046833633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.4046833633
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.837472326
Short name T300
Test name
Test status
Simulation time 177355190 ps
CPU time 1.68 seconds
Started Aug 10 05:58:46 PM PDT 24
Finished Aug 10 05:58:48 PM PDT 24
Peak memory 207032 kb
Host smart-6eab552d-658b-4605-b9da-a3548a6adadf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837472326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.837472326
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1982100357
Short name T1117
Test name
Test status
Simulation time 78827840 ps
CPU time 1.1 seconds
Started Aug 10 05:58:29 PM PDT 24
Finished Aug 10 05:58:31 PM PDT 24
Peak memory 206884 kb
Host smart-b18d04d4-829e-4bf3-a650-1fec13269e0f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982100357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1982100357
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4112599047
Short name T1033
Test name
Test status
Simulation time 1777962755 ps
CPU time 6.51 seconds
Started Aug 10 05:58:43 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 206880 kb
Host smart-08e1cee9-5a94-4c75-8262-5d8cfc0611de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112599047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.4112599047
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1388466293
Short name T1129
Test name
Test status
Simulation time 13557296 ps
CPU time 0.9 seconds
Started Aug 10 05:58:29 PM PDT 24
Finished Aug 10 05:58:30 PM PDT 24
Peak memory 206880 kb
Host smart-c840814c-031c-4862-bda4-00abd45e71b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388466293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1388466293
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3257523494
Short name T1009
Test name
Test status
Simulation time 101356161 ps
CPU time 1.68 seconds
Started Aug 10 05:58:29 PM PDT 24
Finished Aug 10 05:58:31 PM PDT 24
Peak memory 215280 kb
Host smart-1984988e-2696-4510-89ef-fe2ba95613d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257523494 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3257523494
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3628359768
Short name T1067
Test name
Test status
Simulation time 15297411 ps
CPU time 0.87 seconds
Started Aug 10 05:58:52 PM PDT 24
Finished Aug 10 05:58:53 PM PDT 24
Peak memory 206648 kb
Host smart-7ca13750-eb80-4702-ad99-eeb3abfbc37e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628359768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3628359768
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.697543128
Short name T1093
Test name
Test status
Simulation time 20804273 ps
CPU time 0.81 seconds
Started Aug 10 05:58:41 PM PDT 24
Finished Aug 10 05:58:42 PM PDT 24
Peak memory 205352 kb
Host smart-4c9d537a-4a4d-4c97-a201-49538e068f50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697543128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.697543128
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1781214971
Short name T1043
Test name
Test status
Simulation time 27900205 ps
CPU time 1.27 seconds
Started Aug 10 05:58:29 PM PDT 24
Finished Aug 10 05:58:30 PM PDT 24
Peak memory 206928 kb
Host smart-7186e735-22b3-45b1-8f9d-59dc676c3ade
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781214971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1781214971
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3823592583
Short name T1069
Test name
Test status
Simulation time 30651724 ps
CPU time 1.97 seconds
Started Aug 10 05:58:44 PM PDT 24
Finished Aug 10 05:58:46 PM PDT 24
Peak memory 215100 kb
Host smart-8e5b2a26-71fd-44c9-84ec-76db9cdf8c52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823592583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3823592583
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1912004360
Short name T1105
Test name
Test status
Simulation time 76148388 ps
CPU time 1.79 seconds
Started Aug 10 05:58:41 PM PDT 24
Finished Aug 10 05:58:43 PM PDT 24
Peak memory 207028 kb
Host smart-ff40b96c-247c-4a83-9e44-9718c60ff4a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912004360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1912004360
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3254762481
Short name T1087
Test name
Test status
Simulation time 31192855 ps
CPU time 0.84 seconds
Started Aug 10 05:59:02 PM PDT 24
Finished Aug 10 05:59:03 PM PDT 24
Peak memory 206580 kb
Host smart-a8b476dd-ef72-421a-b8eb-f747af475196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254762481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3254762481
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1657450494
Short name T1122
Test name
Test status
Simulation time 13935633 ps
CPU time 0.88 seconds
Started Aug 10 05:58:57 PM PDT 24
Finished Aug 10 05:58:58 PM PDT 24
Peak memory 206684 kb
Host smart-5ddfb795-f822-4f8f-8493-ac962db7271d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657450494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1657450494
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1585419432
Short name T1006
Test name
Test status
Simulation time 56815986 ps
CPU time 0.94 seconds
Started Aug 10 05:58:57 PM PDT 24
Finished Aug 10 05:58:58 PM PDT 24
Peak memory 206268 kb
Host smart-34e3632a-07e7-4caa-8b1e-99bf9735869f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585419432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1585419432
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3252294823
Short name T1083
Test name
Test status
Simulation time 17094311 ps
CPU time 0.95 seconds
Started Aug 10 05:58:45 PM PDT 24
Finished Aug 10 05:58:46 PM PDT 24
Peak memory 206652 kb
Host smart-72975f05-711a-45bf-bb95-e292150a7ece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252294823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3252294823
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1464736547
Short name T1092
Test name
Test status
Simulation time 36796892 ps
CPU time 0.78 seconds
Started Aug 10 05:58:49 PM PDT 24
Finished Aug 10 05:58:50 PM PDT 24
Peak memory 206580 kb
Host smart-005607a2-8e54-45bc-a464-88f6b9ec1575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464736547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1464736547
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2408733685
Short name T1085
Test name
Test status
Simulation time 17834662 ps
CPU time 0.93 seconds
Started Aug 10 05:59:06 PM PDT 24
Finished Aug 10 05:59:07 PM PDT 24
Peak memory 206732 kb
Host smart-77802871-0603-43d7-bec0-dc75b579caa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408733685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2408733685
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.254530328
Short name T1054
Test name
Test status
Simulation time 27579422 ps
CPU time 0.87 seconds
Started Aug 10 05:58:55 PM PDT 24
Finished Aug 10 05:58:56 PM PDT 24
Peak memory 206700 kb
Host smart-74b7778e-ba7d-42fa-ab43-2f8b02fe7d86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254530328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.254530328
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.300953647
Short name T1091
Test name
Test status
Simulation time 12963556 ps
CPU time 0.89 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 206660 kb
Host smart-975977e2-1734-4aa0-804e-5a81c27b0445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300953647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.300953647
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1507202872
Short name T1064
Test name
Test status
Simulation time 23218407 ps
CPU time 0.9 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 206668 kb
Host smart-7902cf6e-4362-4794-860b-bd1799271b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507202872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1507202872
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.715217446
Short name T1081
Test name
Test status
Simulation time 33672500 ps
CPU time 0.82 seconds
Started Aug 10 05:58:52 PM PDT 24
Finished Aug 10 05:58:53 PM PDT 24
Peak memory 206484 kb
Host smart-96f1ccc9-d134-4676-8cdf-f86ce9f933c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715217446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.715217446
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.804775407
Short name T1102
Test name
Test status
Simulation time 29352982 ps
CPU time 1.12 seconds
Started Aug 10 05:58:54 PM PDT 24
Finished Aug 10 05:58:56 PM PDT 24
Peak memory 206716 kb
Host smart-67cad9a7-33e8-4da0-887b-c89a638192c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804775407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.804775407
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.614515458
Short name T1109
Test name
Test status
Simulation time 36431635 ps
CPU time 1.9 seconds
Started Aug 10 05:58:43 PM PDT 24
Finished Aug 10 05:58:45 PM PDT 24
Peak memory 206724 kb
Host smart-814b4484-ec6e-411a-afb0-5ed8c769a5fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614515458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.614515458
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1222834983
Short name T279
Test name
Test status
Simulation time 22507021 ps
CPU time 0.87 seconds
Started Aug 10 05:58:29 PM PDT 24
Finished Aug 10 05:58:30 PM PDT 24
Peak memory 206744 kb
Host smart-7e6b5377-dece-474a-9629-fa671673bf4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222834983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1222834983
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.635825386
Short name T1090
Test name
Test status
Simulation time 27506550 ps
CPU time 1.6 seconds
Started Aug 10 05:58:52 PM PDT 24
Finished Aug 10 05:58:54 PM PDT 24
Peak memory 214992 kb
Host smart-68581417-8a15-4d52-9fb0-3bf3e64c62db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635825386 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.635825386
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.13930593
Short name T277
Test name
Test status
Simulation time 16508766 ps
CPU time 1.01 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:30 PM PDT 24
Peak memory 206744 kb
Host smart-ab18ffc2-3ec6-4cb7-8ded-6bc955c625e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13930593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.13930593
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1999925985
Short name T1021
Test name
Test status
Simulation time 15639590 ps
CPU time 0.89 seconds
Started Aug 10 05:58:46 PM PDT 24
Finished Aug 10 05:58:47 PM PDT 24
Peak memory 206588 kb
Host smart-85e84ee3-e125-4249-94eb-193a4a8152f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999925985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1999925985
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1911943422
Short name T1119
Test name
Test status
Simulation time 31651053 ps
CPU time 0.94 seconds
Started Aug 10 05:58:57 PM PDT 24
Finished Aug 10 05:58:58 PM PDT 24
Peak memory 206728 kb
Host smart-e8c59741-f2a9-4eb2-b234-e45cc814c3ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911943422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1911943422
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3222197451
Short name T1051
Test name
Test status
Simulation time 468987217 ps
CPU time 3.79 seconds
Started Aug 10 05:58:28 PM PDT 24
Finished Aug 10 05:58:32 PM PDT 24
Peak memory 215176 kb
Host smart-18059599-9991-4198-9190-10cd8a4c37ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222197451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3222197451
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.255436015
Short name T1014
Test name
Test status
Simulation time 12879287 ps
CPU time 0.87 seconds
Started Aug 10 05:59:03 PM PDT 24
Finished Aug 10 05:59:04 PM PDT 24
Peak memory 206748 kb
Host smart-b4d19707-0b13-4639-859f-fdc66f9c436f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255436015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.255436015
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3831145691
Short name T1086
Test name
Test status
Simulation time 56299506 ps
CPU time 0.8 seconds
Started Aug 10 05:58:53 PM PDT 24
Finished Aug 10 05:58:54 PM PDT 24
Peak memory 206524 kb
Host smart-276d10ba-44ad-43d9-9b1d-4e9cc2cab407
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831145691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3831145691
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3579880920
Short name T1005
Test name
Test status
Simulation time 16114024 ps
CPU time 0.92 seconds
Started Aug 10 05:58:56 PM PDT 24
Finished Aug 10 05:58:57 PM PDT 24
Peak memory 206680 kb
Host smart-95f4ea3a-d2af-4222-b5e3-57f9b2e9b572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579880920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3579880920
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.319596229
Short name T1096
Test name
Test status
Simulation time 31744871 ps
CPU time 0.81 seconds
Started Aug 10 05:58:54 PM PDT 24
Finished Aug 10 05:58:55 PM PDT 24
Peak memory 206548 kb
Host smart-bbe99b09-cef2-4c66-9681-418293e9577f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319596229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.319596229
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3880725507
Short name T1056
Test name
Test status
Simulation time 18984271 ps
CPU time 0.87 seconds
Started Aug 10 05:58:50 PM PDT 24
Finished Aug 10 05:58:51 PM PDT 24
Peak memory 206740 kb
Host smart-f41c6dbe-574b-4f77-8118-a25ba5e29ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880725507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3880725507
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1562971494
Short name T1044
Test name
Test status
Simulation time 40949786 ps
CPU time 0.83 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 206704 kb
Host smart-fa6aeea1-289a-41ee-b9fd-7554f02b7e79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562971494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1562971494
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1758226037
Short name T1046
Test name
Test status
Simulation time 14259127 ps
CPU time 0.91 seconds
Started Aug 10 05:59:08 PM PDT 24
Finished Aug 10 05:59:09 PM PDT 24
Peak memory 206672 kb
Host smart-6731488a-1379-4949-ac92-4ef00c81130b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758226037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1758226037
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2308352447
Short name T1008
Test name
Test status
Simulation time 35593978 ps
CPU time 0.87 seconds
Started Aug 10 05:58:53 PM PDT 24
Finished Aug 10 05:58:54 PM PDT 24
Peak memory 206704 kb
Host smart-2b46b3ae-82bf-4d54-bde4-ccbbd58f9b28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308352447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2308352447
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.4189747816
Short name T1012
Test name
Test status
Simulation time 31131855 ps
CPU time 0.84 seconds
Started Aug 10 05:58:51 PM PDT 24
Finished Aug 10 05:58:52 PM PDT 24
Peak memory 206684 kb
Host smart-29953e11-4b4f-4dea-8bbf-b5af59cfaa07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189747816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.4189747816
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3440754009
Short name T1115
Test name
Test status
Simulation time 48342208 ps
CPU time 0.85 seconds
Started Aug 10 05:58:46 PM PDT 24
Finished Aug 10 05:58:47 PM PDT 24
Peak memory 206740 kb
Host smart-3d0a5b25-abd4-409e-95ec-29356506b960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440754009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3440754009
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3927710544
Short name T284
Test name
Test status
Simulation time 21273258 ps
CPU time 1.22 seconds
Started Aug 10 05:59:03 PM PDT 24
Finished Aug 10 05:59:04 PM PDT 24
Peak memory 206688 kb
Host smart-05e7cc75-6911-44fc-814f-4ab26e595ee7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927710544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3927710544
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3660564782
Short name T1017
Test name
Test status
Simulation time 706713598 ps
CPU time 5.01 seconds
Started Aug 10 05:59:08 PM PDT 24
Finished Aug 10 05:59:13 PM PDT 24
Peak memory 206708 kb
Host smart-8ad0cd9b-77a8-40a8-ba6d-53557ddb7529
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660564782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3660564782
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3763705797
Short name T1035
Test name
Test status
Simulation time 46167127 ps
CPU time 0.81 seconds
Started Aug 10 05:58:56 PM PDT 24
Finished Aug 10 05:58:57 PM PDT 24
Peak memory 206648 kb
Host smart-72081a43-aaed-4eff-87c4-65c80bc26083
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763705797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3763705797
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.311937015
Short name T999
Test name
Test status
Simulation time 24811394 ps
CPU time 1.2 seconds
Started Aug 10 05:58:37 PM PDT 24
Finished Aug 10 05:58:39 PM PDT 24
Peak memory 215224 kb
Host smart-de78c5dd-e218-4d81-80d5-775ed99765ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311937015 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.311937015
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3683909767
Short name T273
Test name
Test status
Simulation time 14759508 ps
CPU time 0.88 seconds
Started Aug 10 05:58:37 PM PDT 24
Finished Aug 10 05:58:38 PM PDT 24
Peak memory 206776 kb
Host smart-d1b418da-31e4-47bc-be55-acf7164b8399
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683909767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3683909767
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2067305473
Short name T1018
Test name
Test status
Simulation time 14722826 ps
CPU time 0.9 seconds
Started Aug 10 05:58:53 PM PDT 24
Finished Aug 10 05:58:54 PM PDT 24
Peak memory 206576 kb
Host smart-12a04aed-84b9-4354-b81f-aff6f08477f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067305473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2067305473
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.164183946
Short name T291
Test name
Test status
Simulation time 34669549 ps
CPU time 1.1 seconds
Started Aug 10 05:58:49 PM PDT 24
Finished Aug 10 05:58:50 PM PDT 24
Peak memory 206928 kb
Host smart-7157813e-ba2f-4e2b-956a-11e4c5d95415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164183946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.164183946
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2157009948
Short name T1100
Test name
Test status
Simulation time 281584069 ps
CPU time 3.69 seconds
Started Aug 10 05:58:57 PM PDT 24
Finished Aug 10 05:59:00 PM PDT 24
Peak memory 214964 kb
Host smart-84e8075c-8db5-4ab5-9223-83ca0c1a5049
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157009948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2157009948
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3865725899
Short name T309
Test name
Test status
Simulation time 270667542 ps
CPU time 2.16 seconds
Started Aug 10 05:58:43 PM PDT 24
Finished Aug 10 05:58:45 PM PDT 24
Peak memory 206948 kb
Host smart-53f4f274-380e-482f-89f7-907323a7a91c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865725899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3865725899
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.4200171872
Short name T1071
Test name
Test status
Simulation time 14430165 ps
CPU time 0.91 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 206676 kb
Host smart-e95a652d-704e-40a9-9a5f-5e773f6e3b2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200171872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.4200171872
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1649946841
Short name T1060
Test name
Test status
Simulation time 79491885 ps
CPU time 0.8 seconds
Started Aug 10 05:58:52 PM PDT 24
Finished Aug 10 05:58:53 PM PDT 24
Peak memory 206524 kb
Host smart-d24fb27c-b4a4-4fc8-8049-76fa9e8f1d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649946841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1649946841
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1077217627
Short name T1073
Test name
Test status
Simulation time 70755634 ps
CPU time 0.78 seconds
Started Aug 10 05:58:45 PM PDT 24
Finished Aug 10 05:58:46 PM PDT 24
Peak memory 206496 kb
Host smart-32b6befd-4afe-432b-bb86-355abb6c5bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077217627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1077217627
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2688001817
Short name T1072
Test name
Test status
Simulation time 21395863 ps
CPU time 0.87 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 206676 kb
Host smart-aa83ba40-689e-4c4a-885f-6bd009e51ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688001817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2688001817
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.200908378
Short name T1026
Test name
Test status
Simulation time 16707688 ps
CPU time 0.86 seconds
Started Aug 10 05:59:16 PM PDT 24
Finished Aug 10 05:59:17 PM PDT 24
Peak memory 206704 kb
Host smart-84541193-10eb-4b20-b16f-0dd7b2c94eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200908378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.200908378
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2887931357
Short name T1126
Test name
Test status
Simulation time 32959025 ps
CPU time 0.83 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:47 PM PDT 24
Peak memory 206580 kb
Host smart-0a3f36d3-46e5-442f-b204-464f6b905283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887931357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2887931357
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2107979565
Short name T1050
Test name
Test status
Simulation time 35422770 ps
CPU time 0.94 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 206668 kb
Host smart-7d521ce7-dd6b-40f5-b7e7-ec4df7cd6491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107979565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2107979565
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.4124932961
Short name T1123
Test name
Test status
Simulation time 11448775 ps
CPU time 0.84 seconds
Started Aug 10 05:58:53 PM PDT 24
Finished Aug 10 05:58:54 PM PDT 24
Peak memory 206704 kb
Host smart-265f2a12-18ba-4d47-abba-92f48a60cbf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124932961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.4124932961
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3737750697
Short name T1040
Test name
Test status
Simulation time 75629789 ps
CPU time 0.8 seconds
Started Aug 10 05:58:57 PM PDT 24
Finished Aug 10 05:58:58 PM PDT 24
Peak memory 206444 kb
Host smart-eb8ff02c-a4a0-4584-b397-2b2aa99ff0c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737750697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3737750697
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1895964599
Short name T1128
Test name
Test status
Simulation time 44311635 ps
CPU time 0.86 seconds
Started Aug 10 05:58:53 PM PDT 24
Finished Aug 10 05:58:54 PM PDT 24
Peak memory 206740 kb
Host smart-a6f21fdf-7cf3-46c9-a4f5-40f3fab8301a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895964599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1895964599
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4150330489
Short name T1057
Test name
Test status
Simulation time 37765742 ps
CPU time 1.3 seconds
Started Aug 10 05:58:50 PM PDT 24
Finished Aug 10 05:58:52 PM PDT 24
Peak memory 215008 kb
Host smart-5446862c-1304-446f-8eef-600eccc17564
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150330489 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.4150330489
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.67438292
Short name T283
Test name
Test status
Simulation time 24893911 ps
CPU time 0.86 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:49 PM PDT 24
Peak memory 206824 kb
Host smart-2cefb635-73ae-4876-8a77-b76da1dbe444
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67438292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.67438292
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3029942784
Short name T1066
Test name
Test status
Simulation time 13426319 ps
CPU time 0.88 seconds
Started Aug 10 05:58:38 PM PDT 24
Finished Aug 10 05:58:39 PM PDT 24
Peak memory 206740 kb
Host smart-5962d8e0-4faa-45d1-86c2-cfc4d714c011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029942784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3029942784
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3873563337
Short name T1095
Test name
Test status
Simulation time 25405352 ps
CPU time 1 seconds
Started Aug 10 05:59:03 PM PDT 24
Finished Aug 10 05:59:04 PM PDT 24
Peak memory 206904 kb
Host smart-93af8fa2-dae3-45e3-b985-de5876a019ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873563337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3873563337
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.110997378
Short name T1019
Test name
Test status
Simulation time 40551772 ps
CPU time 2.75 seconds
Started Aug 10 05:58:41 PM PDT 24
Finished Aug 10 05:58:44 PM PDT 24
Peak memory 215252 kb
Host smart-11c34d40-ef19-4dff-b0ef-2836e340bdae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110997378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.110997378
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1073738979
Short name T1048
Test name
Test status
Simulation time 158891786 ps
CPU time 1.51 seconds
Started Aug 10 05:58:59 PM PDT 24
Finished Aug 10 05:59:01 PM PDT 24
Peak memory 214936 kb
Host smart-cae47ce2-cce8-4994-b81c-5beea9b2f9bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073738979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1073738979
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1111329030
Short name T1010
Test name
Test status
Simulation time 24043194 ps
CPU time 1.21 seconds
Started Aug 10 05:58:36 PM PDT 24
Finished Aug 10 05:58:38 PM PDT 24
Peak memory 215140 kb
Host smart-82cf211b-ac30-41f9-8619-3fca5887fa06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111329030 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1111329030
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.73825291
Short name T281
Test name
Test status
Simulation time 57126112 ps
CPU time 0.79 seconds
Started Aug 10 05:58:51 PM PDT 24
Finished Aug 10 05:58:52 PM PDT 24
Peak memory 206720 kb
Host smart-d4fd66d8-62e6-4586-8e78-15a0c3319c6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73825291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.73825291
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.467247989
Short name T1084
Test name
Test status
Simulation time 14400083 ps
CPU time 0.84 seconds
Started Aug 10 05:58:49 PM PDT 24
Finished Aug 10 05:58:50 PM PDT 24
Peak memory 206536 kb
Host smart-9a913018-57a3-4c39-8613-d3a5974a8308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467247989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.467247989
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3719512655
Short name T1094
Test name
Test status
Simulation time 64193510 ps
CPU time 1.02 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:48 PM PDT 24
Peak memory 206964 kb
Host smart-ed7e8fe6-a67c-42e3-a7b5-8b34c5ccac61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719512655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3719512655
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1347747716
Short name T1024
Test name
Test status
Simulation time 49842966 ps
CPU time 1.7 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:50 PM PDT 24
Peak memory 215132 kb
Host smart-d1fda246-e299-459c-acc4-5d40c3b82929
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347747716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1347747716
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.399706751
Short name T1074
Test name
Test status
Simulation time 92475022 ps
CPU time 1.6 seconds
Started Aug 10 05:58:35 PM PDT 24
Finished Aug 10 05:58:37 PM PDT 24
Peak memory 206916 kb
Host smart-0bad9335-b1e6-4cd8-8246-a62115526926
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399706751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.399706751
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.848944849
Short name T1104
Test name
Test status
Simulation time 20382846 ps
CPU time 1.25 seconds
Started Aug 10 05:58:38 PM PDT 24
Finished Aug 10 05:58:39 PM PDT 24
Peak memory 215156 kb
Host smart-29f20a61-b512-4e33-b211-a7872ae599e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848944849 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.848944849
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3462146795
Short name T272
Test name
Test status
Simulation time 55200498 ps
CPU time 0.81 seconds
Started Aug 10 05:58:55 PM PDT 24
Finished Aug 10 05:58:56 PM PDT 24
Peak memory 206660 kb
Host smart-2670fe79-d873-4c73-aad3-5940d0d29d4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462146795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3462146795
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2452250822
Short name T1101
Test name
Test status
Simulation time 12958796 ps
CPU time 0.85 seconds
Started Aug 10 05:58:50 PM PDT 24
Finished Aug 10 05:58:52 PM PDT 24
Peak memory 206540 kb
Host smart-b9f20fd0-0b87-46fb-9ca8-37f2696fc249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452250822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2452250822
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2426193328
Short name T1045
Test name
Test status
Simulation time 182736263 ps
CPU time 1.19 seconds
Started Aug 10 05:58:47 PM PDT 24
Finished Aug 10 05:58:48 PM PDT 24
Peak memory 206984 kb
Host smart-454e4f90-63e5-4f69-a1f6-6f1e7e011fa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426193328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2426193328
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3820495412
Short name T1124
Test name
Test status
Simulation time 23320469 ps
CPU time 1.55 seconds
Started Aug 10 05:58:36 PM PDT 24
Finished Aug 10 05:58:38 PM PDT 24
Peak memory 215128 kb
Host smart-39c3cddc-1a21-4fa7-9e05-31538dbd5450
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820495412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3820495412
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4199699917
Short name T307
Test name
Test status
Simulation time 120498904 ps
CPU time 2.89 seconds
Started Aug 10 05:58:37 PM PDT 24
Finished Aug 10 05:58:40 PM PDT 24
Peak memory 207300 kb
Host smart-46d3c60b-5d7d-4d97-a7fd-c5fbbb79601d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199699917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.4199699917
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.353110629
Short name T1127
Test name
Test status
Simulation time 150044894 ps
CPU time 1.59 seconds
Started Aug 10 05:58:45 PM PDT 24
Finished Aug 10 05:58:47 PM PDT 24
Peak memory 215204 kb
Host smart-951a8404-8993-47bf-87a8-085246392661
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353110629 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.353110629
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2690632200
Short name T1023
Test name
Test status
Simulation time 154786371 ps
CPU time 0.86 seconds
Started Aug 10 05:58:54 PM PDT 24
Finished Aug 10 05:58:55 PM PDT 24
Peak memory 206728 kb
Host smart-ec8a6a43-22f0-4812-85ac-03b0f68852fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690632200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2690632200
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1763103266
Short name T1001
Test name
Test status
Simulation time 22964066 ps
CPU time 0.84 seconds
Started Aug 10 05:58:39 PM PDT 24
Finished Aug 10 05:58:41 PM PDT 24
Peak memory 206660 kb
Host smart-76741777-4f4b-4e92-bc96-243145801889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763103266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1763103266
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.398954740
Short name T1107
Test name
Test status
Simulation time 31937783 ps
CPU time 1.15 seconds
Started Aug 10 05:58:40 PM PDT 24
Finished Aug 10 05:58:41 PM PDT 24
Peak memory 206944 kb
Host smart-28c5d17c-e010-4b16-9517-318d88ab7a9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398954740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.398954740
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1807409613
Short name T1059
Test name
Test status
Simulation time 216382380 ps
CPU time 3.64 seconds
Started Aug 10 05:58:51 PM PDT 24
Finished Aug 10 05:58:55 PM PDT 24
Peak memory 215032 kb
Host smart-1eaa3fda-48cc-4cd9-927e-1bd5240c50f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807409613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1807409613
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3804750186
Short name T312
Test name
Test status
Simulation time 160177056 ps
CPU time 2.05 seconds
Started Aug 10 05:58:48 PM PDT 24
Finished Aug 10 05:58:50 PM PDT 24
Peak memory 207264 kb
Host smart-a6fbc4e2-8f44-44dd-8d0c-76ec405e9c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804750186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3804750186
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.220154561
Short name T1002
Test name
Test status
Simulation time 20778250 ps
CPU time 1.18 seconds
Started Aug 10 05:58:41 PM PDT 24
Finished Aug 10 05:58:43 PM PDT 24
Peak memory 215260 kb
Host smart-11875256-c932-467b-a07d-eb46ebfba69f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220154561 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.220154561
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2667548844
Short name T276
Test name
Test status
Simulation time 37602994 ps
CPU time 0.88 seconds
Started Aug 10 05:58:52 PM PDT 24
Finished Aug 10 05:58:53 PM PDT 24
Peak memory 206808 kb
Host smart-ec246679-dd72-43df-a7d9-246e02686e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667548844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2667548844
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2063444102
Short name T1089
Test name
Test status
Simulation time 86677623 ps
CPU time 0.82 seconds
Started Aug 10 05:59:00 PM PDT 24
Finished Aug 10 05:59:01 PM PDT 24
Peak memory 206620 kb
Host smart-9a792dcf-97ed-4f6d-80de-638ed6c507de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063444102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2063444102
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1518432380
Short name T292
Test name
Test status
Simulation time 133866087 ps
CPU time 1.29 seconds
Started Aug 10 05:58:50 PM PDT 24
Finished Aug 10 05:58:51 PM PDT 24
Peak memory 206740 kb
Host smart-e79e2d0c-097b-4061-ad6f-bf3c2b4ba81f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518432380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1518432380
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3905896587
Short name T1125
Test name
Test status
Simulation time 78199442 ps
CPU time 2.81 seconds
Started Aug 10 05:58:36 PM PDT 24
Finished Aug 10 05:58:39 PM PDT 24
Peak memory 215128 kb
Host smart-47b70a4e-9df7-437b-aafd-d32f717f716b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905896587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3905896587
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2796216178
Short name T1118
Test name
Test status
Simulation time 101988239 ps
CPU time 2.55 seconds
Started Aug 10 05:58:43 PM PDT 24
Finished Aug 10 05:58:46 PM PDT 24
Peak memory 206904 kb
Host smart-f575edff-a751-489c-bb8f-5316983fb4e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796216178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2796216178
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1023487477
Short name T81
Test name
Test status
Simulation time 24220431 ps
CPU time 1.16 seconds
Started Aug 10 07:21:23 PM PDT 24
Finished Aug 10 07:21:25 PM PDT 24
Peak memory 219756 kb
Host smart-c05e2025-bcf1-45b5-b7be-a12285f284bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023487477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1023487477
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1803005896
Short name T997
Test name
Test status
Simulation time 17509049 ps
CPU time 0.8 seconds
Started Aug 10 07:21:28 PM PDT 24
Finished Aug 10 07:21:29 PM PDT 24
Peak memory 206632 kb
Host smart-f37066a5-46a3-4f11-9674-964c752dbfea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803005896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1803005896
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.472766679
Short name T452
Test name
Test status
Simulation time 104451837 ps
CPU time 1.14 seconds
Started Aug 10 07:21:27 PM PDT 24
Finished Aug 10 07:21:28 PM PDT 24
Peak memory 219488 kb
Host smart-6765275e-981a-4a76-994a-c6eba707d596
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472766679 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.472766679
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_genbits.2090194351
Short name T474
Test name
Test status
Simulation time 29943874 ps
CPU time 1.36 seconds
Started Aug 10 07:21:25 PM PDT 24
Finished Aug 10 07:21:27 PM PDT 24
Peak memory 218648 kb
Host smart-608e6e8b-c10f-4169-9d74-1c6de561d38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090194351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2090194351
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.4201075349
Short name T31
Test name
Test status
Simulation time 19804893 ps
CPU time 1.07 seconds
Started Aug 10 07:21:24 PM PDT 24
Finished Aug 10 07:21:26 PM PDT 24
Peak memory 215976 kb
Host smart-0d62233f-f44d-4d6a-a355-d9795ffaa850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201075349 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.4201075349
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_smoke.435640065
Short name T973
Test name
Test status
Simulation time 46998140 ps
CPU time 0.92 seconds
Started Aug 10 07:21:30 PM PDT 24
Finished Aug 10 07:21:31 PM PDT 24
Peak memory 215320 kb
Host smart-bc1371a1-3a93-48e1-9c81-aefa518bf89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435640065 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.435640065
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2314266585
Short name T747
Test name
Test status
Simulation time 22707138 ps
CPU time 0.98 seconds
Started Aug 10 07:21:27 PM PDT 24
Finished Aug 10 07:21:28 PM PDT 24
Peak memory 206656 kb
Host smart-e8d076b3-991d-4676-81d3-1bd663ae6b15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314266585 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2314266585
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2488793736
Short name T971
Test name
Test status
Simulation time 146626932280 ps
CPU time 988.92 seconds
Started Aug 10 07:21:29 PM PDT 24
Finished Aug 10 07:37:58 PM PDT 24
Peak memory 222864 kb
Host smart-eec72961-b7c6-4be0-b20d-1350bcd96fcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488793736 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2488793736
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.3297653975
Short name T969
Test name
Test status
Simulation time 31778747 ps
CPU time 0.79 seconds
Started Aug 10 07:21:44 PM PDT 24
Finished Aug 10 07:21:45 PM PDT 24
Peak memory 206460 kb
Host smart-45c29430-df8c-4348-b280-31d8bf922c22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297653975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3297653975
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.801085798
Short name T823
Test name
Test status
Simulation time 64343074 ps
CPU time 0.84 seconds
Started Aug 10 07:21:36 PM PDT 24
Finished Aug 10 07:21:37 PM PDT 24
Peak memory 216264 kb
Host smart-27c2e0a1-8543-4ba8-ad47-acf108538726
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801085798 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.801085798
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.3663290018
Short name T551
Test name
Test status
Simulation time 19397063 ps
CPU time 1.11 seconds
Started Aug 10 07:21:38 PM PDT 24
Finished Aug 10 07:21:39 PM PDT 24
Peak memory 224116 kb
Host smart-d0508bfc-cf9f-495f-869f-24bc5a88c27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663290018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3663290018
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1207861058
Short name T422
Test name
Test status
Simulation time 48919723 ps
CPU time 1.5 seconds
Started Aug 10 07:21:30 PM PDT 24
Finished Aug 10 07:21:31 PM PDT 24
Peak memory 217468 kb
Host smart-65654f2b-f375-4b63-adc7-64bc5f260baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207861058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1207861058
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2175073057
Short name T376
Test name
Test status
Simulation time 23627363 ps
CPU time 1.19 seconds
Started Aug 10 07:21:30 PM PDT 24
Finished Aug 10 07:21:31 PM PDT 24
Peak memory 215232 kb
Host smart-e1e2e501-1eb0-4c26-a7db-16f3a657a453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175073057 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2175073057
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3555296000
Short name T346
Test name
Test status
Simulation time 22697092 ps
CPU time 0.99 seconds
Started Aug 10 07:21:30 PM PDT 24
Finished Aug 10 07:21:31 PM PDT 24
Peak memory 206956 kb
Host smart-49919d61-1d4b-425d-8ddb-c120de10bf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555296000 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3555296000
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1454213512
Short name T19
Test name
Test status
Simulation time 826876544 ps
CPU time 6.74 seconds
Started Aug 10 07:21:38 PM PDT 24
Finished Aug 10 07:21:45 PM PDT 24
Peak memory 239104 kb
Host smart-85520ccf-0526-4cf9-bb0f-6fe3f854823f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454213512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1454213512
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_stress_all.936253798
Short name T863
Test name
Test status
Simulation time 701450288 ps
CPU time 3.99 seconds
Started Aug 10 07:21:25 PM PDT 24
Finished Aug 10 07:21:29 PM PDT 24
Peak memory 215384 kb
Host smart-22c98b42-dee3-4578-901e-d04956a48aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936253798 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.936253798
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1646179483
Short name T767
Test name
Test status
Simulation time 281390313885 ps
CPU time 3340.56 seconds
Started Aug 10 07:21:28 PM PDT 24
Finished Aug 10 08:17:09 PM PDT 24
Peak memory 231680 kb
Host smart-41aeb89d-bd63-4091-a64a-b50e494adce1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646179483 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1646179483
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.723065954
Short name T377
Test name
Test status
Simulation time 75818035 ps
CPU time 1.18 seconds
Started Aug 10 07:22:00 PM PDT 24
Finished Aug 10 07:22:01 PM PDT 24
Peak memory 219740 kb
Host smart-5f44aac1-c83c-4474-9ab4-d9a077c33cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723065954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.723065954
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.255301053
Short name T896
Test name
Test status
Simulation time 144081631 ps
CPU time 0.92 seconds
Started Aug 10 07:22:00 PM PDT 24
Finished Aug 10 07:22:01 PM PDT 24
Peak memory 215008 kb
Host smart-7985a6f6-6c24-4005-8b88-9f4c1d79c2b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255301053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.255301053
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.960658970
Short name T909
Test name
Test status
Simulation time 17191617 ps
CPU time 1.02 seconds
Started Aug 10 07:21:59 PM PDT 24
Finished Aug 10 07:22:01 PM PDT 24
Peak memory 216484 kb
Host smart-08cbb26a-635f-4d07-8760-277c8528e9e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960658970 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.960658970
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.3009178701
Short name T180
Test name
Test status
Simulation time 21583021 ps
CPU time 1.05 seconds
Started Aug 10 07:22:00 PM PDT 24
Finished Aug 10 07:22:01 PM PDT 24
Peak memory 224188 kb
Host smart-8992036d-801d-4581-b7b5-6be0d671c29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009178701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3009178701
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.4090389849
Short name T484
Test name
Test status
Simulation time 38089673 ps
CPU time 1.61 seconds
Started Aug 10 07:22:02 PM PDT 24
Finished Aug 10 07:22:04 PM PDT 24
Peak memory 217476 kb
Host smart-05d2c6c7-8853-4c00-ad93-681cfd0adf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090389849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4090389849
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.320151614
Short name T788
Test name
Test status
Simulation time 32334577 ps
CPU time 0.95 seconds
Started Aug 10 07:21:59 PM PDT 24
Finished Aug 10 07:22:00 PM PDT 24
Peak memory 215320 kb
Host smart-be7b52cb-c12a-40ab-a614-ab8e73b392cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320151614 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.320151614
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2369356109
Short name T701
Test name
Test status
Simulation time 31879775 ps
CPU time 0.97 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:21:59 PM PDT 24
Peak memory 215360 kb
Host smart-c5d8f1d1-4248-48f4-9fb3-9509cc0b5556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369356109 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2369356109
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1584835753
Short name T425
Test name
Test status
Simulation time 404622845 ps
CPU time 4.11 seconds
Started Aug 10 07:21:59 PM PDT 24
Finished Aug 10 07:22:03 PM PDT 24
Peak memory 217116 kb
Host smart-a8eec50c-4969-4994-af2c-49d6d4aec699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584835753 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1584835753
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.321588252
Short name T239
Test name
Test status
Simulation time 92629142861 ps
CPU time 2110.38 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:57:08 PM PDT 24
Peak memory 227016 kb
Host smart-e4d7d632-1c4f-4f60-b86f-8c5ccf08af62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321588252 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.321588252
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.936690966
Short name T403
Test name
Test status
Simulation time 68477572 ps
CPU time 1.1 seconds
Started Aug 10 07:23:43 PM PDT 24
Finished Aug 10 07:23:44 PM PDT 24
Peak memory 217392 kb
Host smart-a65d2ac8-799c-48b9-87b4-2d8f728ddf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936690966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.936690966
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.3424513688
Short name T481
Test name
Test status
Simulation time 22907601 ps
CPU time 1.12 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 218364 kb
Host smart-387b380e-a434-499c-84c0-dc42d9e4525c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424513688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3424513688
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/102.edn_alert.2294252449
Short name T598
Test name
Test status
Simulation time 97619143 ps
CPU time 1.34 seconds
Started Aug 10 07:23:50 PM PDT 24
Finished Aug 10 07:23:51 PM PDT 24
Peak memory 215572 kb
Host smart-f4ad37f5-e3b3-4ea5-8e18-7ece4008ced8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294252449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.2294252449
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.3110481589
Short name T437
Test name
Test status
Simulation time 34366397 ps
CPU time 1.09 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 217380 kb
Host smart-85192f5b-1fc3-4eb2-a6ba-a91b8c55389b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110481589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3110481589
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.825453333
Short name T795
Test name
Test status
Simulation time 98941619 ps
CPU time 1.31 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 215596 kb
Host smart-72091b09-8f7e-4ef1-8383-6d6a2731b48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825453333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.825453333
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.2876162521
Short name T876
Test name
Test status
Simulation time 74508957 ps
CPU time 1.2 seconds
Started Aug 10 07:23:44 PM PDT 24
Finished Aug 10 07:23:45 PM PDT 24
Peak memory 218728 kb
Host smart-88898195-f745-4959-87cb-ab465342cc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876162521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2876162521
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.1333708828
Short name T299
Test name
Test status
Simulation time 31945567 ps
CPU time 1.36 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:48 PM PDT 24
Peak memory 215588 kb
Host smart-ed69e009-af54-4631-9591-d6bfad65914d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333708828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1333708828
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.145328513
Short name T479
Test name
Test status
Simulation time 147136499 ps
CPU time 1.75 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 217468 kb
Host smart-0c66c4e7-7544-4d5e-81cd-e050745db239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145328513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.145328513
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.765797938
Short name T355
Test name
Test status
Simulation time 42405735 ps
CPU time 1.16 seconds
Started Aug 10 07:23:48 PM PDT 24
Finished Aug 10 07:23:50 PM PDT 24
Peak memory 219680 kb
Host smart-9766c51a-33cd-4d4b-800a-2189ddee9f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765797938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.765797938
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.2273145387
Short name T881
Test name
Test status
Simulation time 54523045 ps
CPU time 1.23 seconds
Started Aug 10 07:23:43 PM PDT 24
Finished Aug 10 07:23:44 PM PDT 24
Peak memory 215316 kb
Host smart-9cbcc599-abcc-475e-a737-07650954d302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273145387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2273145387
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.2914022288
Short name T343
Test name
Test status
Simulation time 53521045 ps
CPU time 1.59 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:48 PM PDT 24
Peak memory 218576 kb
Host smart-ada3216c-709a-458c-8e9f-aaf507e25c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914022288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2914022288
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.1398442586
Short name T689
Test name
Test status
Simulation time 22255696 ps
CPU time 1.15 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 218748 kb
Host smart-fc3fd8e6-fb66-4ab7-8512-ffe3a7a48761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398442586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1398442586
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.1944512101
Short name T915
Test name
Test status
Simulation time 43602730 ps
CPU time 1.67 seconds
Started Aug 10 07:23:47 PM PDT 24
Finished Aug 10 07:23:49 PM PDT 24
Peak memory 220180 kb
Host smart-1149f109-f753-4cd8-87db-8f00b74b6f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944512101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1944512101
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2491161557
Short name T731
Test name
Test status
Simulation time 152164374 ps
CPU time 1.74 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:48 PM PDT 24
Peak memory 219008 kb
Host smart-5f4b1ea6-92db-4c28-8fc2-ed3b2782cc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491161557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2491161557
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3320145802
Short name T100
Test name
Test status
Simulation time 35683409 ps
CPU time 1.05 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 219892 kb
Host smart-dd1cab6b-701f-4234-9138-8e54853eb891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320145802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3320145802
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3658217809
Short name T615
Test name
Test status
Simulation time 65173299 ps
CPU time 1.66 seconds
Started Aug 10 07:23:48 PM PDT 24
Finished Aug 10 07:23:50 PM PDT 24
Peak memory 218948 kb
Host smart-21479a6b-e359-45fc-b572-0bd7fb4b5a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658217809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3658217809
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2792112675
Short name T270
Test name
Test status
Simulation time 29022784 ps
CPU time 1.4 seconds
Started Aug 10 07:21:59 PM PDT 24
Finished Aug 10 07:22:01 PM PDT 24
Peak memory 220380 kb
Host smart-c1f2d5f1-f0cd-4977-a1ff-a5ae792edaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792112675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2792112675
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3393491289
Short name T516
Test name
Test status
Simulation time 48466439 ps
CPU time 0.94 seconds
Started Aug 10 07:21:59 PM PDT 24
Finished Aug 10 07:22:00 PM PDT 24
Peak memory 215184 kb
Host smart-942e6567-eb33-4dad-b58c-99476e2885df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393491289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3393491289
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.72629365
Short name T596
Test name
Test status
Simulation time 26142796 ps
CPU time 1.05 seconds
Started Aug 10 07:22:00 PM PDT 24
Finished Aug 10 07:22:01 PM PDT 24
Peak memory 218548 kb
Host smart-ab9ea92a-1c0b-45c3-97e7-ef71c7ec7c3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72629365 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_dis
able_auto_req_mode.72629365
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2918680562
Short name T939
Test name
Test status
Simulation time 20152881 ps
CPU time 1.02 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:21:59 PM PDT 24
Peak memory 219800 kb
Host smart-e780cd7b-bea8-4ae8-88e0-bc787ecbf10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918680562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2918680562
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3222883229
Short name T918
Test name
Test status
Simulation time 87217359 ps
CPU time 1.44 seconds
Started Aug 10 07:21:59 PM PDT 24
Finished Aug 10 07:22:01 PM PDT 24
Peak memory 219252 kb
Host smart-060769d0-6119-4d6c-b1c3-9d452ec3ea5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222883229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3222883229
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.3437588283
Short name T850
Test name
Test status
Simulation time 19224112 ps
CPU time 0.98 seconds
Started Aug 10 07:21:59 PM PDT 24
Finished Aug 10 07:22:00 PM PDT 24
Peak memory 215284 kb
Host smart-0420cd99-22bb-4313-ace1-e5abb8dd3d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437588283 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3437588283
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3520237649
Short name T894
Test name
Test status
Simulation time 182758840 ps
CPU time 2.28 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:22:01 PM PDT 24
Peak memory 219624 kb
Host smart-a3380abe-bf07-431f-8fe8-c7c646e7b7d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520237649 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3520237649
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2588006927
Short name T622
Test name
Test status
Simulation time 31727344219 ps
CPU time 383.09 seconds
Started Aug 10 07:21:57 PM PDT 24
Finished Aug 10 07:28:21 PM PDT 24
Peak memory 218364 kb
Host smart-09b4109a-d028-4f66-9ab1-a5f4e76333ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588006927 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2588006927
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.654570416
Short name T726
Test name
Test status
Simulation time 40475393 ps
CPU time 1.22 seconds
Started Aug 10 07:23:48 PM PDT 24
Finished Aug 10 07:23:49 PM PDT 24
Peak memory 219676 kb
Host smart-a08ab727-2879-4a0f-8312-fc959bb6f6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654570416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.654570416
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2300152073
Short name T749
Test name
Test status
Simulation time 46049162 ps
CPU time 1.55 seconds
Started Aug 10 07:23:48 PM PDT 24
Finished Aug 10 07:23:50 PM PDT 24
Peak memory 219940 kb
Host smart-db46d910-4d81-4eba-b21f-ed7f2b9f87fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300152073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2300152073
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.2807044684
Short name T794
Test name
Test status
Simulation time 70481281 ps
CPU time 1.16 seconds
Started Aug 10 07:23:48 PM PDT 24
Finished Aug 10 07:23:50 PM PDT 24
Peak memory 218660 kb
Host smart-55ea6e12-a2e8-4bed-9efa-81954a3ff17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807044684 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2807044684
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/112.edn_alert.3354202340
Short name T825
Test name
Test status
Simulation time 81462211 ps
CPU time 1.23 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 220684 kb
Host smart-b19200ff-d061-45e5-9119-3fa5d7265ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354202340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3354202340
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/113.edn_alert.1185122938
Short name T353
Test name
Test status
Simulation time 29832186 ps
CPU time 1.28 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:48 PM PDT 24
Peak memory 218576 kb
Host smart-a672ba09-6824-45de-bae3-c3f9d5fa7c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185122938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1185122938
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.2030641035
Short name T655
Test name
Test status
Simulation time 32345689 ps
CPU time 1.29 seconds
Started Aug 10 07:23:48 PM PDT 24
Finished Aug 10 07:23:49 PM PDT 24
Peak memory 219960 kb
Host smart-32cf3f46-5e5e-444c-97aa-4d224b1f673b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030641035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2030641035
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.3431481709
Short name T184
Test name
Test status
Simulation time 24871547 ps
CPU time 1.15 seconds
Started Aug 10 07:23:48 PM PDT 24
Finished Aug 10 07:23:50 PM PDT 24
Peak memory 218748 kb
Host smart-017383f5-0f9a-42cc-8f9a-693d70370fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431481709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3431481709
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.2804487383
Short name T628
Test name
Test status
Simulation time 108479077 ps
CPU time 1.33 seconds
Started Aug 10 07:23:50 PM PDT 24
Finished Aug 10 07:23:51 PM PDT 24
Peak memory 217532 kb
Host smart-f9c9a152-afb5-4c35-a62c-89acca6daa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804487383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2804487383
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.2262853901
Short name T518
Test name
Test status
Simulation time 46171975 ps
CPU time 1.2 seconds
Started Aug 10 07:23:47 PM PDT 24
Finished Aug 10 07:23:49 PM PDT 24
Peak memory 219284 kb
Host smart-682faec3-22b2-4baa-9dce-018ea0f8c0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262853901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.2262853901
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.4275652264
Short name T469
Test name
Test status
Simulation time 52059030 ps
CPU time 1.68 seconds
Started Aug 10 07:23:48 PM PDT 24
Finished Aug 10 07:23:50 PM PDT 24
Peak memory 218508 kb
Host smart-ed0f9af4-e189-4251-9de1-914d5bb00f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275652264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.4275652264
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.2922001411
Short name T314
Test name
Test status
Simulation time 24404803 ps
CPU time 1.15 seconds
Started Aug 10 07:23:49 PM PDT 24
Finished Aug 10 07:23:51 PM PDT 24
Peak memory 218440 kb
Host smart-52937304-7243-4b63-94b4-74e3a6bf6d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922001411 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.2922001411
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.951987489
Short name T793
Test name
Test status
Simulation time 39102678 ps
CPU time 1.42 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 219484 kb
Host smart-4db65007-e371-4acd-97a8-3da294f0e13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951987489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.951987489
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.4090815554
Short name T913
Test name
Test status
Simulation time 22213099 ps
CPU time 1.1 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 220620 kb
Host smart-5342bb05-70f7-459a-a706-36920b0f46e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090815554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.4090815554
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3985448528
Short name T505
Test name
Test status
Simulation time 44111559 ps
CPU time 1.5 seconds
Started Aug 10 07:23:42 PM PDT 24
Finished Aug 10 07:23:44 PM PDT 24
Peak memory 218620 kb
Host smart-c5f71855-a801-4540-8ede-a262be34df49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985448528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3985448528
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3397221816
Short name T917
Test name
Test status
Simulation time 82679705 ps
CPU time 1.21 seconds
Started Aug 10 07:23:50 PM PDT 24
Finished Aug 10 07:23:51 PM PDT 24
Peak memory 217260 kb
Host smart-c0d177d0-8253-494b-940d-39c401e07a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397221816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3397221816
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1216915328
Short name T383
Test name
Test status
Simulation time 26705830 ps
CPU time 1.2 seconds
Started Aug 10 07:23:48 PM PDT 24
Finished Aug 10 07:23:49 PM PDT 24
Peak memory 219480 kb
Host smart-ad6c8661-cdfd-4a4f-bb77-11d7e7472dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216915328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1216915328
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.1870358411
Short name T983
Test name
Test status
Simulation time 49232534 ps
CPU time 1.07 seconds
Started Aug 10 07:23:49 PM PDT 24
Finished Aug 10 07:23:50 PM PDT 24
Peak memory 217248 kb
Host smart-e9789178-1b88-4894-ae0f-741a4395e913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870358411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1870358411
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2198292673
Short name T843
Test name
Test status
Simulation time 50923385 ps
CPU time 1.28 seconds
Started Aug 10 07:22:13 PM PDT 24
Finished Aug 10 07:22:14 PM PDT 24
Peak memory 219520 kb
Host smart-ba56c2b3-fde3-44ac-bcdc-8d83d26f4409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198292673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2198292673
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2752007028
Short name T626
Test name
Test status
Simulation time 18582535 ps
CPU time 0.94 seconds
Started Aug 10 07:22:09 PM PDT 24
Finished Aug 10 07:22:10 PM PDT 24
Peak memory 215164 kb
Host smart-500e6793-370c-4ead-a451-d00143f1075d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752007028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2752007028
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1678464369
Short name T672
Test name
Test status
Simulation time 16311950 ps
CPU time 0.86 seconds
Started Aug 10 07:22:11 PM PDT 24
Finished Aug 10 07:22:12 PM PDT 24
Peak memory 216244 kb
Host smart-6f805140-d474-433c-a2cd-bd9213d5c01e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678464369 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1678464369
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3275919474
Short name T933
Test name
Test status
Simulation time 53513383 ps
CPU time 1.14 seconds
Started Aug 10 07:22:13 PM PDT 24
Finished Aug 10 07:22:14 PM PDT 24
Peak memory 217192 kb
Host smart-a8518b9e-c217-4d64-b7ee-6183541482c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275919474 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3275919474
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3092320545
Short name T8
Test name
Test status
Simulation time 21329401 ps
CPU time 1.13 seconds
Started Aug 10 07:22:13 PM PDT 24
Finished Aug 10 07:22:14 PM PDT 24
Peak memory 219868 kb
Host smart-9eece630-d6bb-4cec-8c0e-0c4d2cc1909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092320545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3092320545
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3746913941
Short name T910
Test name
Test status
Simulation time 40446530 ps
CPU time 1.41 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:22:00 PM PDT 24
Peak memory 219900 kb
Host smart-617c7f4c-bd8e-493d-910f-70c60b28824c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746913941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3746913941
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.318260246
Short name T372
Test name
Test status
Simulation time 90838896 ps
CPU time 0.85 seconds
Started Aug 10 07:22:14 PM PDT 24
Finished Aug 10 07:22:15 PM PDT 24
Peak memory 215316 kb
Host smart-6c1f428e-58de-4cee-9ee5-e97fb6c006b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318260246 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.318260246
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2615982598
Short name T590
Test name
Test status
Simulation time 131774943 ps
CPU time 0.94 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:21:59 PM PDT 24
Peak memory 215360 kb
Host smart-c89a22e4-a68b-4311-9528-3682bc56c8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615982598 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2615982598
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1422222225
Short name T892
Test name
Test status
Simulation time 223558659 ps
CPU time 4.82 seconds
Started Aug 10 07:22:02 PM PDT 24
Finished Aug 10 07:22:07 PM PDT 24
Peak memory 218516 kb
Host smart-6a0b11cc-74ac-4aaa-85c9-77e0431d0205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422222225 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1422222225
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.240606786
Short name T412
Test name
Test status
Simulation time 60849030855 ps
CPU time 697.59 seconds
Started Aug 10 07:21:57 PM PDT 24
Finished Aug 10 07:33:35 PM PDT 24
Peak memory 221716 kb
Host smart-979d9cf1-6acc-4dfd-801f-9af0403b7f3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240606786 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.240606786
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.696707761
Short name T267
Test name
Test status
Simulation time 87642685 ps
CPU time 1.22 seconds
Started Aug 10 07:23:50 PM PDT 24
Finished Aug 10 07:23:51 PM PDT 24
Peak memory 218632 kb
Host smart-bf7b9c8e-6eb9-4d51-9cc5-acbe4e21a7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696707761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.696707761
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3595271808
Short name T24
Test name
Test status
Simulation time 77692309 ps
CPU time 1.05 seconds
Started Aug 10 07:23:50 PM PDT 24
Finished Aug 10 07:23:51 PM PDT 24
Peak memory 215376 kb
Host smart-3ad2cb8f-82bf-4a41-ae51-f398d55145ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595271808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3595271808
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.4272273762
Short name T855
Test name
Test status
Simulation time 163098461 ps
CPU time 1.37 seconds
Started Aug 10 07:23:44 PM PDT 24
Finished Aug 10 07:23:45 PM PDT 24
Peak memory 219632 kb
Host smart-7837adaa-f0e0-4355-972b-163df73da9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272273762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.4272273762
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.808026495
Short name T334
Test name
Test status
Simulation time 70916984 ps
CPU time 1.62 seconds
Started Aug 10 07:23:44 PM PDT 24
Finished Aug 10 07:23:45 PM PDT 24
Peak memory 218432 kb
Host smart-3e395e1b-6503-4ea4-a23b-94d4c844560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808026495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.808026495
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.47856074
Short name T91
Test name
Test status
Simulation time 27582042 ps
CPU time 1.26 seconds
Started Aug 10 07:23:52 PM PDT 24
Finished Aug 10 07:23:54 PM PDT 24
Peak memory 215544 kb
Host smart-ecd04a7a-4729-456e-9b8d-8697de8fb570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47856074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.47856074
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.1112888941
Short name T462
Test name
Test status
Simulation time 79788736 ps
CPU time 2.74 seconds
Started Aug 10 07:23:49 PM PDT 24
Finished Aug 10 07:23:52 PM PDT 24
Peak memory 217472 kb
Host smart-b95a8048-9e8c-4fbd-9a73-240ae6a98311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112888941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1112888941
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.3612718741
Short name T139
Test name
Test status
Simulation time 24015315 ps
CPU time 1.16 seconds
Started Aug 10 07:23:51 PM PDT 24
Finished Aug 10 07:23:52 PM PDT 24
Peak memory 218260 kb
Host smart-8543e6c7-546d-453b-89b4-f5ddfd62bc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612718741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.3612718741
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/125.edn_alert.1858339012
Short name T195
Test name
Test status
Simulation time 25537442 ps
CPU time 1.18 seconds
Started Aug 10 07:23:56 PM PDT 24
Finished Aug 10 07:23:57 PM PDT 24
Peak memory 215468 kb
Host smart-1b241a49-66d3-4602-8f0d-1f7961b7561a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858339012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1858339012
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.3284663917
Short name T708
Test name
Test status
Simulation time 70026875 ps
CPU time 2.32 seconds
Started Aug 10 07:23:53 PM PDT 24
Finished Aug 10 07:23:55 PM PDT 24
Peak memory 220092 kb
Host smart-18e4ac5f-0ffa-4361-97e8-49452385f5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284663917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3284663917
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.944441427
Short name T861
Test name
Test status
Simulation time 71174386 ps
CPU time 1.52 seconds
Started Aug 10 07:23:54 PM PDT 24
Finished Aug 10 07:23:56 PM PDT 24
Peak memory 218864 kb
Host smart-75e1f665-94dc-43e3-bfdc-ad3a5f226fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944441427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.944441427
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.2557584994
Short name T145
Test name
Test status
Simulation time 90964777 ps
CPU time 1.14 seconds
Started Aug 10 07:23:50 PM PDT 24
Finished Aug 10 07:23:52 PM PDT 24
Peak memory 219424 kb
Host smart-0156adc6-0a95-4c81-8ca8-431391a808a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557584994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2557584994
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1078749923
Short name T359
Test name
Test status
Simulation time 37313597 ps
CPU time 1.55 seconds
Started Aug 10 07:23:53 PM PDT 24
Finished Aug 10 07:23:55 PM PDT 24
Peak memory 219980 kb
Host smart-a94ce890-9617-4feb-a052-45750737c9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078749923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1078749923
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1794802947
Short name T874
Test name
Test status
Simulation time 87855519 ps
CPU time 3.07 seconds
Started Aug 10 07:23:56 PM PDT 24
Finished Aug 10 07:23:59 PM PDT 24
Peak memory 220104 kb
Host smart-e9b6ecfa-0dcc-4b3d-955e-a9fc1a15c174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794802947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1794802947
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3011359900
Short name T644
Test name
Test status
Simulation time 51903138 ps
CPU time 1.29 seconds
Started Aug 10 07:23:52 PM PDT 24
Finished Aug 10 07:23:53 PM PDT 24
Peak memory 220456 kb
Host smart-32872ccd-cf81-4275-b7a6-e1db178d2f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011359900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3011359900
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.3778932621
Short name T594
Test name
Test status
Simulation time 57157485 ps
CPU time 1.46 seconds
Started Aug 10 07:23:58 PM PDT 24
Finished Aug 10 07:24:00 PM PDT 24
Peak memory 218428 kb
Host smart-628cf808-1d93-4a4f-ac7b-11f26a09fade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778932621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3778932621
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.69655169
Short name T150
Test name
Test status
Simulation time 67061625 ps
CPU time 1.32 seconds
Started Aug 10 07:22:13 PM PDT 24
Finished Aug 10 07:22:14 PM PDT 24
Peak memory 218836 kb
Host smart-d2a89804-8bcc-4f27-9248-c41c81a07ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69655169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.69655169
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.4021653900
Short name T606
Test name
Test status
Simulation time 22329047 ps
CPU time 0.9 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:16 PM PDT 24
Peak memory 216332 kb
Host smart-afce0214-ccfc-4d2a-90e2-1c89772223ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021653900 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.4021653900
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1080481242
Short name T122
Test name
Test status
Simulation time 43357382 ps
CPU time 1.35 seconds
Started Aug 10 07:22:13 PM PDT 24
Finished Aug 10 07:22:15 PM PDT 24
Peak memory 219536 kb
Host smart-f850ed64-5d41-49ac-8aee-a516400a5b98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080481242 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1080481242
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.737647455
Short name T570
Test name
Test status
Simulation time 20060189 ps
CPU time 1.08 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:17 PM PDT 24
Peak memory 224096 kb
Host smart-6aa885cf-6754-4420-8777-e29057b99a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737647455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.737647455
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2545304100
Short name T533
Test name
Test status
Simulation time 43177326 ps
CPU time 1.18 seconds
Started Aug 10 07:22:10 PM PDT 24
Finished Aug 10 07:22:12 PM PDT 24
Peak memory 219944 kb
Host smart-dfd6302b-781c-4232-9d14-e3e866b403c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545304100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2545304100
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1839029537
Short name T524
Test name
Test status
Simulation time 21835774 ps
CPU time 1.16 seconds
Started Aug 10 07:22:12 PM PDT 24
Finished Aug 10 07:22:13 PM PDT 24
Peak memory 224128 kb
Host smart-d4c66db2-9334-4822-af94-5f15ea194210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839029537 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1839029537
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.420413942
Short name T538
Test name
Test status
Simulation time 20366967 ps
CPU time 1.01 seconds
Started Aug 10 07:22:12 PM PDT 24
Finished Aug 10 07:22:13 PM PDT 24
Peak memory 215284 kb
Host smart-6d9b2fc7-e153-41ea-940c-4274322bf47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420413942 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.420413942
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1242942215
Short name T530
Test name
Test status
Simulation time 625313953 ps
CPU time 4.01 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:19 PM PDT 24
Peak memory 215324 kb
Host smart-84fef682-af92-4406-884c-435b335a2097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242942215 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1242942215
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1887186393
Short name T709
Test name
Test status
Simulation time 34139332344 ps
CPU time 424.71 seconds
Started Aug 10 07:22:10 PM PDT 24
Finished Aug 10 07:29:15 PM PDT 24
Peak memory 218144 kb
Host smart-f04cc461-0efc-4e5a-95bf-75fdcc281cf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887186393 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1887186393
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1908481135
Short name T478
Test name
Test status
Simulation time 33635630 ps
CPU time 1.38 seconds
Started Aug 10 07:23:59 PM PDT 24
Finished Aug 10 07:24:01 PM PDT 24
Peak memory 219632 kb
Host smart-ea38b14f-36bf-4232-9f13-e8aed8ea383d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908481135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1908481135
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.823891129
Short name T52
Test name
Test status
Simulation time 49051012 ps
CPU time 1.16 seconds
Started Aug 10 07:23:53 PM PDT 24
Finished Aug 10 07:23:55 PM PDT 24
Peak memory 218616 kb
Host smart-3a3307e0-4eda-4bc9-a69a-cc4ae4c18c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823891129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.823891129
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.3299299365
Short name T859
Test name
Test status
Simulation time 113769852 ps
CPU time 1.26 seconds
Started Aug 10 07:23:56 PM PDT 24
Finished Aug 10 07:23:57 PM PDT 24
Peak memory 218716 kb
Host smart-1a457c01-6839-48cc-9338-9f77f08bdf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299299365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3299299365
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3167812532
Short name T956
Test name
Test status
Simulation time 25326328 ps
CPU time 1.23 seconds
Started Aug 10 07:23:53 PM PDT 24
Finished Aug 10 07:23:54 PM PDT 24
Peak memory 219464 kb
Host smart-ae1268c4-25d4-4244-a712-dd47eceb340d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167812532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3167812532
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.709105766
Short name T780
Test name
Test status
Simulation time 62971992 ps
CPU time 2.17 seconds
Started Aug 10 07:23:52 PM PDT 24
Finished Aug 10 07:23:55 PM PDT 24
Peak memory 218536 kb
Host smart-eddd40a8-a077-4faf-90e3-7a054007d9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709105766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.709105766
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.1006476760
Short name T586
Test name
Test status
Simulation time 27682056 ps
CPU time 1.24 seconds
Started Aug 10 07:23:51 PM PDT 24
Finished Aug 10 07:23:52 PM PDT 24
Peak memory 218600 kb
Host smart-eba46028-8ccf-4785-b43f-e4bbb5838144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006476760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.1006476760
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3591939693
Short name T39
Test name
Test status
Simulation time 100044718 ps
CPU time 1.33 seconds
Started Aug 10 07:23:52 PM PDT 24
Finished Aug 10 07:23:53 PM PDT 24
Peak memory 219120 kb
Host smart-68d55e01-ebff-4129-8809-cc6139aa94a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591939693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3591939693
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.3474788629
Short name T228
Test name
Test status
Simulation time 81572027 ps
CPU time 1.19 seconds
Started Aug 10 07:23:53 PM PDT 24
Finished Aug 10 07:23:55 PM PDT 24
Peak memory 218464 kb
Host smart-84426be5-11f2-4eae-b7fc-fb0ad74f1dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474788629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3474788629
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/135.edn_alert.1704978616
Short name T621
Test name
Test status
Simulation time 82472716 ps
CPU time 1.09 seconds
Started Aug 10 07:23:52 PM PDT 24
Finished Aug 10 07:23:54 PM PDT 24
Peak memory 218404 kb
Host smart-b9e1c728-4c7e-406b-87fc-567fb6620d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704978616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1704978616
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.824031142
Short name T617
Test name
Test status
Simulation time 104857213 ps
CPU time 1.1 seconds
Started Aug 10 07:23:53 PM PDT 24
Finished Aug 10 07:23:54 PM PDT 24
Peak memory 219460 kb
Host smart-cc2184bb-271b-44fa-bd10-b6a3da5b53c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824031142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.824031142
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2591534872
Short name T972
Test name
Test status
Simulation time 31642592 ps
CPU time 1.24 seconds
Started Aug 10 07:23:52 PM PDT 24
Finished Aug 10 07:23:54 PM PDT 24
Peak memory 221000 kb
Host smart-642a9d88-6371-41a7-807d-ceb968f97429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591534872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2591534872
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.1888318470
Short name T22
Test name
Test status
Simulation time 59816963 ps
CPU time 1.59 seconds
Started Aug 10 07:23:54 PM PDT 24
Finished Aug 10 07:23:55 PM PDT 24
Peak memory 219372 kb
Host smart-97af8a5b-a3b4-4210-a0d9-6911f82403ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888318470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1888318470
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3877315128
Short name T351
Test name
Test status
Simulation time 42649867 ps
CPU time 1.23 seconds
Started Aug 10 07:23:52 PM PDT 24
Finished Aug 10 07:23:54 PM PDT 24
Peak memory 218712 kb
Host smart-30fc79d7-9eb0-44d5-a6cb-0f1969749bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877315128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3877315128
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3622115845
Short name T463
Test name
Test status
Simulation time 28418683 ps
CPU time 1.04 seconds
Started Aug 10 07:23:57 PM PDT 24
Finished Aug 10 07:23:58 PM PDT 24
Peak memory 215256 kb
Host smart-252b6a9c-e390-4745-9264-2407874ce5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622115845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3622115845
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1493559469
Short name T739
Test name
Test status
Simulation time 95377973 ps
CPU time 1.16 seconds
Started Aug 10 07:23:56 PM PDT 24
Finished Aug 10 07:23:57 PM PDT 24
Peak memory 219680 kb
Host smart-699c18c3-674a-43a0-9619-7e09c64a946b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493559469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1493559469
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.1409738509
Short name T656
Test name
Test status
Simulation time 54960305 ps
CPU time 1.29 seconds
Started Aug 10 07:23:56 PM PDT 24
Finished Aug 10 07:23:57 PM PDT 24
Peak memory 218460 kb
Host smart-bd855453-bf76-42f8-928a-a6a20bba0ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409738509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1409738509
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2561441301
Short name T104
Test name
Test status
Simulation time 27938302 ps
CPU time 1.17 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:16 PM PDT 24
Peak memory 219712 kb
Host smart-ee6483e2-9b62-44c8-97dc-02ae9c599170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561441301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2561441301
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3873823484
Short name T400
Test name
Test status
Simulation time 25334565 ps
CPU time 0.9 seconds
Started Aug 10 07:22:10 PM PDT 24
Finished Aug 10 07:22:11 PM PDT 24
Peak memory 206828 kb
Host smart-f53791ba-043a-4b75-8943-0d87d0356648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873823484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3873823484
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1418654149
Short name T224
Test name
Test status
Simulation time 67565792 ps
CPU time 1.18 seconds
Started Aug 10 07:22:12 PM PDT 24
Finished Aug 10 07:22:14 PM PDT 24
Peak memory 217084 kb
Host smart-8e16c6ea-f660-4f5b-a767-a35608445c2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418654149 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1418654149
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3166419578
Short name T459
Test name
Test status
Simulation time 33189576 ps
CPU time 1.08 seconds
Started Aug 10 07:22:13 PM PDT 24
Finished Aug 10 07:22:14 PM PDT 24
Peak memory 220900 kb
Host smart-aeba74b3-4c7a-4877-bbf5-406a7b331f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166419578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3166419578
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2105122178
Short name T470
Test name
Test status
Simulation time 31131448 ps
CPU time 1.47 seconds
Started Aug 10 07:22:12 PM PDT 24
Finished Aug 10 07:22:13 PM PDT 24
Peak memory 217456 kb
Host smart-b00b9c27-2e8b-4eaf-835c-c9749856a911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105122178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2105122178
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3122662678
Short name T759
Test name
Test status
Simulation time 38768057 ps
CPU time 0.87 seconds
Started Aug 10 07:22:16 PM PDT 24
Finished Aug 10 07:22:17 PM PDT 24
Peak memory 215280 kb
Host smart-a6148790-cd94-4236-abe3-90465823011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122662678 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3122662678
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3121800484
Short name T627
Test name
Test status
Simulation time 50995216 ps
CPU time 0.93 seconds
Started Aug 10 07:22:11 PM PDT 24
Finished Aug 10 07:22:12 PM PDT 24
Peak memory 215316 kb
Host smart-82c3409e-97db-4ddd-8580-8baab66cbdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121800484 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3121800484
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3910301296
Short name T205
Test name
Test status
Simulation time 724538385 ps
CPU time 4.69 seconds
Started Aug 10 07:22:11 PM PDT 24
Finished Aug 10 07:22:15 PM PDT 24
Peak memory 219628 kb
Host smart-9f0f9811-8917-4222-be96-6f7ae639d87a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910301296 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3910301296
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2756161255
Short name T37
Test name
Test status
Simulation time 438231811467 ps
CPU time 2476.88 seconds
Started Aug 10 07:22:09 PM PDT 24
Finished Aug 10 08:03:26 PM PDT 24
Peak memory 228964 kb
Host smart-32a35c10-af84-4ac1-939c-c3913c77da8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756161255 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2756161255
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.3066917888
Short name T958
Test name
Test status
Simulation time 26135594 ps
CPU time 1.22 seconds
Started Aug 10 07:23:54 PM PDT 24
Finished Aug 10 07:23:55 PM PDT 24
Peak memory 219668 kb
Host smart-1a03ea2e-c1d8-4a5b-a043-d53707575a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066917888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3066917888
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.4242274567
Short name T921
Test name
Test status
Simulation time 44326424 ps
CPU time 1.5 seconds
Started Aug 10 07:23:54 PM PDT 24
Finished Aug 10 07:23:56 PM PDT 24
Peak memory 217500 kb
Host smart-3a626b19-ea0d-4640-a3b6-4c618f975fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242274567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.4242274567
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.3232290314
Short name T268
Test name
Test status
Simulation time 29995858 ps
CPU time 1.28 seconds
Started Aug 10 07:23:54 PM PDT 24
Finished Aug 10 07:23:56 PM PDT 24
Peak memory 218504 kb
Host smart-d1e8a6b7-7f18-48b2-b841-709b82bbd714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232290314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3232290314
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3109563268
Short name T835
Test name
Test status
Simulation time 83179614 ps
CPU time 1.35 seconds
Started Aug 10 07:23:54 PM PDT 24
Finished Aug 10 07:23:55 PM PDT 24
Peak memory 218500 kb
Host smart-fc69f9f3-b3e0-49db-bcd2-be9dfa1a0364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109563268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3109563268
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.724317887
Short name T827
Test name
Test status
Simulation time 109370508 ps
CPU time 1.17 seconds
Started Aug 10 07:23:51 PM PDT 24
Finished Aug 10 07:23:52 PM PDT 24
Peak memory 220488 kb
Host smart-4a9364b4-7b94-481f-a9b6-bac1c79ca4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724317887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.724317887
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.820778236
Short name T854
Test name
Test status
Simulation time 109489492 ps
CPU time 1.16 seconds
Started Aug 10 07:23:50 PM PDT 24
Finished Aug 10 07:23:51 PM PDT 24
Peak memory 217212 kb
Host smart-e9c60467-f034-4b93-bd6e-ba6b3303b3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820778236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.820778236
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1588104180
Short name T782
Test name
Test status
Simulation time 44723953 ps
CPU time 1.28 seconds
Started Aug 10 07:23:54 PM PDT 24
Finished Aug 10 07:23:55 PM PDT 24
Peak memory 219768 kb
Host smart-f65109af-f95c-4164-b1a5-2fe0a7a21c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588104180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1588104180
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.3813126080
Short name T608
Test name
Test status
Simulation time 222701719 ps
CPU time 3.06 seconds
Started Aug 10 07:23:51 PM PDT 24
Finished Aug 10 07:23:54 PM PDT 24
Peak memory 215340 kb
Host smart-c67fcc04-c807-45f1-81dc-8fa0539df540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813126080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3813126080
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.546919876
Short name T852
Test name
Test status
Simulation time 44100136 ps
CPU time 1.34 seconds
Started Aug 10 07:24:00 PM PDT 24
Finished Aug 10 07:24:02 PM PDT 24
Peak memory 220328 kb
Host smart-4578d05e-479c-4128-a4e7-5e687d170823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546919876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.546919876
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.382642315
Short name T501
Test name
Test status
Simulation time 45995430 ps
CPU time 0.99 seconds
Started Aug 10 07:23:54 PM PDT 24
Finished Aug 10 07:23:55 PM PDT 24
Peak memory 217424 kb
Host smart-7d27b7c5-6b56-4567-810c-b41259647e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382642315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.382642315
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2882180703
Short name T354
Test name
Test status
Simulation time 32266591 ps
CPU time 1.45 seconds
Started Aug 10 07:24:03 PM PDT 24
Finished Aug 10 07:24:04 PM PDT 24
Peak memory 220380 kb
Host smart-337b1cc5-b71f-4956-8f41-5ac4be3c9560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882180703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2882180703
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.3378195681
Short name T952
Test name
Test status
Simulation time 62740866 ps
CPU time 1.66 seconds
Started Aug 10 07:24:03 PM PDT 24
Finished Aug 10 07:24:05 PM PDT 24
Peak memory 218816 kb
Host smart-a0de943b-0962-4852-9aa5-384bd5672c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378195681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3378195681
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2301418546
Short name T352
Test name
Test status
Simulation time 29899738 ps
CPU time 1.25 seconds
Started Aug 10 07:24:03 PM PDT 24
Finished Aug 10 07:24:05 PM PDT 24
Peak memory 220548 kb
Host smart-075b5194-ac9d-436a-a75d-08acf6c2c450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301418546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2301418546
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.614641660
Short name T260
Test name
Test status
Simulation time 46392942 ps
CPU time 1.08 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 218936 kb
Host smart-5b4f3f56-651b-413e-aea1-5ad395141ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614641660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.614641660
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.3244291461
Short name T702
Test name
Test status
Simulation time 82581674 ps
CPU time 1.2 seconds
Started Aug 10 07:24:07 PM PDT 24
Finished Aug 10 07:24:08 PM PDT 24
Peak memory 219668 kb
Host smart-f8db59fe-d96d-455d-b886-786724abf027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244291461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3244291461
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.2077880026
Short name T836
Test name
Test status
Simulation time 101030602 ps
CPU time 1.04 seconds
Started Aug 10 07:24:01 PM PDT 24
Finished Aug 10 07:24:02 PM PDT 24
Peak memory 217300 kb
Host smart-761f3ea0-7a42-44af-b5b1-fc9a2c54e37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077880026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2077880026
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.3775961090
Short name T867
Test name
Test status
Simulation time 24084054 ps
CPU time 1.18 seconds
Started Aug 10 07:24:05 PM PDT 24
Finished Aug 10 07:24:06 PM PDT 24
Peak memory 220764 kb
Host smart-ae5670f9-be15-4420-add7-af2aff95f73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775961090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3775961090
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2130971272
Short name T493
Test name
Test status
Simulation time 86445478 ps
CPU time 1.2 seconds
Started Aug 10 07:24:05 PM PDT 24
Finished Aug 10 07:24:06 PM PDT 24
Peak memory 217264 kb
Host smart-081cabe0-6f39-4d5c-9ea6-79506bf86ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130971272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2130971272
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3996920793
Short name T129
Test name
Test status
Simulation time 78936400 ps
CPU time 1.27 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:04 PM PDT 24
Peak memory 219760 kb
Host smart-27773d0a-f573-4dfb-8f31-96b4dc037ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996920793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3996920793
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2741039238
Short name T802
Test name
Test status
Simulation time 45414093 ps
CPU time 1.82 seconds
Started Aug 10 07:24:00 PM PDT 24
Finished Aug 10 07:24:02 PM PDT 24
Peak memory 217412 kb
Host smart-d4313d06-f63c-4b52-9c07-f85048b18672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741039238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2741039238
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1176896218
Short name T562
Test name
Test status
Simulation time 57386463 ps
CPU time 1.26 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:16 PM PDT 24
Peak memory 215432 kb
Host smart-c63bab72-80c0-4e96-8278-dc5775e138ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176896218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1176896218
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.4053947862
Short name T477
Test name
Test status
Simulation time 55225446 ps
CPU time 0.95 seconds
Started Aug 10 07:22:12 PM PDT 24
Finished Aug 10 07:22:13 PM PDT 24
Peak memory 215220 kb
Host smart-5c96130f-a862-40a3-bfcf-b12b5da30222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053947862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.4053947862
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3876720538
Short name T175
Test name
Test status
Simulation time 14787816 ps
CPU time 0.95 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:16 PM PDT 24
Peak memory 216776 kb
Host smart-13ce461c-3c38-469d-8b64-8415ca9e9e17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876720538 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3876720538
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.2195129774
Short name T450
Test name
Test status
Simulation time 39303717 ps
CPU time 0.92 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:16 PM PDT 24
Peak memory 218816 kb
Host smart-966fe565-a392-4f6c-b3a8-9467dce92d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195129774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2195129774
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2484490847
Short name T405
Test name
Test status
Simulation time 148023989 ps
CPU time 1.17 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:16 PM PDT 24
Peak memory 217392 kb
Host smart-3382de92-325d-4ddc-9f78-8703f96761ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484490847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2484490847
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3702701329
Short name T856
Test name
Test status
Simulation time 29798605 ps
CPU time 0.98 seconds
Started Aug 10 07:22:12 PM PDT 24
Finished Aug 10 07:22:13 PM PDT 24
Peak memory 215512 kb
Host smart-845cd67d-1dca-4d2f-8e9a-175b290c4077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702701329 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3702701329
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.140228630
Short name T559
Test name
Test status
Simulation time 19449399 ps
CPU time 1.02 seconds
Started Aug 10 07:22:12 PM PDT 24
Finished Aug 10 07:22:14 PM PDT 24
Peak memory 207108 kb
Host smart-c035e8d4-9add-4072-a3a1-67259afa4856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140228630 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.140228630
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2748605641
Short name T699
Test name
Test status
Simulation time 325188148 ps
CPU time 2.23 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:18 PM PDT 24
Peak memory 215356 kb
Host smart-47ca4641-25bb-4f48-91c7-8e960db31910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748605641 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2748605641
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_alert.1417214354
Short name T821
Test name
Test status
Simulation time 110335211 ps
CPU time 1.17 seconds
Started Aug 10 07:24:00 PM PDT 24
Finished Aug 10 07:24:02 PM PDT 24
Peak memory 218532 kb
Host smart-b637b179-30d3-4bd9-b7c9-91c15dae7b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417214354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.1417214354
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.1887534743
Short name T379
Test name
Test status
Simulation time 46726448 ps
CPU time 1.22 seconds
Started Aug 10 07:24:03 PM PDT 24
Finished Aug 10 07:24:04 PM PDT 24
Peak memory 218704 kb
Host smart-3660be3c-3a4b-4951-ac43-dabc2da7ab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887534743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1887534743
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1156057229
Short name T349
Test name
Test status
Simulation time 54227712 ps
CPU time 1.18 seconds
Started Aug 10 07:24:06 PM PDT 24
Finished Aug 10 07:24:07 PM PDT 24
Peak memory 218548 kb
Host smart-d672d0d7-7e7a-4135-bcef-4f07d1c11b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156057229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1156057229
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.1592397690
Short name T476
Test name
Test status
Simulation time 37295500 ps
CPU time 1.35 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 218684 kb
Host smart-2e336b39-37f2-4625-88b4-d3017b36c654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592397690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1592397690
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.952762144
Short name T662
Test name
Test status
Simulation time 91869872 ps
CPU time 1.23 seconds
Started Aug 10 07:24:06 PM PDT 24
Finished Aug 10 07:24:08 PM PDT 24
Peak memory 219488 kb
Host smart-6332eacc-e9ad-4a04-a958-04edd29b35ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952762144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.952762144
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3861659811
Short name T631
Test name
Test status
Simulation time 68718123 ps
CPU time 1.14 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 217368 kb
Host smart-1fe5d47f-8fe5-4e3b-bca2-b908fd091c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861659811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3861659811
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.3739439254
Short name T266
Test name
Test status
Simulation time 52284359 ps
CPU time 1.27 seconds
Started Aug 10 07:24:06 PM PDT 24
Finished Aug 10 07:24:07 PM PDT 24
Peak memory 219160 kb
Host smart-9f3e0e89-f796-42a2-9ac5-42a5b820811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739439254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3739439254
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1760265842
Short name T563
Test name
Test status
Simulation time 145008352 ps
CPU time 1.19 seconds
Started Aug 10 07:24:05 PM PDT 24
Finished Aug 10 07:24:06 PM PDT 24
Peak memory 217288 kb
Host smart-5a5a5c21-4dfb-417e-a2eb-ebe98143964e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760265842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1760265842
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.430145810
Short name T985
Test name
Test status
Simulation time 51410229 ps
CPU time 1.26 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 219328 kb
Host smart-5c967b0b-1dbb-481a-bfb6-f9ab69f54cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430145810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.430145810
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1311923892
Short name T490
Test name
Test status
Simulation time 68109290 ps
CPU time 2.8 seconds
Started Aug 10 07:24:06 PM PDT 24
Finished Aug 10 07:24:09 PM PDT 24
Peak memory 220264 kb
Host smart-d94d081a-9499-4c78-8a2a-7a49ddb08402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311923892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1311923892
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1239298059
Short name T720
Test name
Test status
Simulation time 27538895 ps
CPU time 1.15 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 218428 kb
Host smart-f6e11392-0369-4b00-85a3-6b271206c563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239298059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1239298059
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2970197957
Short name T294
Test name
Test status
Simulation time 85093416 ps
CPU time 1.33 seconds
Started Aug 10 07:24:04 PM PDT 24
Finished Aug 10 07:24:06 PM PDT 24
Peak memory 218724 kb
Host smart-bc70a9e2-c926-4389-8592-1ac933324d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970197957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2970197957
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.217906408
Short name T611
Test name
Test status
Simulation time 68488386 ps
CPU time 1.13 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 220500 kb
Host smart-26ec8b94-1633-4ccb-8820-33a2ddcce5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217906408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.217906408
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.696915524
Short name T990
Test name
Test status
Simulation time 71277481 ps
CPU time 1.06 seconds
Started Aug 10 07:24:05 PM PDT 24
Finished Aug 10 07:24:06 PM PDT 24
Peak memory 217340 kb
Host smart-cae94b6f-548d-45ff-bf5f-b3bf689dc629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696915524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.696915524
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3219687292
Short name T87
Test name
Test status
Simulation time 82680105 ps
CPU time 1.2 seconds
Started Aug 10 07:24:03 PM PDT 24
Finished Aug 10 07:24:04 PM PDT 24
Peak memory 218780 kb
Host smart-9c4e14a7-c8ab-46a5-94d4-ad78ddcb43b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219687292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3219687292
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1035680175
Short name T391
Test name
Test status
Simulation time 140773861 ps
CPU time 1.64 seconds
Started Aug 10 07:24:06 PM PDT 24
Finished Aug 10 07:24:08 PM PDT 24
Peak memory 219048 kb
Host smart-4cb2117c-8475-49b4-a7bf-9767fc7e580f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035680175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1035680175
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1234647186
Short name T813
Test name
Test status
Simulation time 67341631 ps
CPU time 1.1 seconds
Started Aug 10 07:24:03 PM PDT 24
Finished Aug 10 07:24:04 PM PDT 24
Peak memory 217312 kb
Host smart-25b57ae1-e10d-48cc-8976-cfeeab424e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234647186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1234647186
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3776689161
Short name T298
Test name
Test status
Simulation time 46509100 ps
CPU time 1.23 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:16 PM PDT 24
Peak memory 218312 kb
Host smart-83d69ae9-d28d-4282-8654-b53f7d05678e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776689161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3776689161
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3224825312
Short name T572
Test name
Test status
Simulation time 36265010 ps
CPU time 0.96 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:16 PM PDT 24
Peak memory 215224 kb
Host smart-e0e47755-c7f1-4769-ad67-5bd612c9abec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224825312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3224825312
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1703581615
Short name T681
Test name
Test status
Simulation time 92233831 ps
CPU time 1.1 seconds
Started Aug 10 07:22:16 PM PDT 24
Finished Aug 10 07:22:17 PM PDT 24
Peak memory 218592 kb
Host smart-f872bd5a-0cfa-4c4c-b8e0-9de8634a1a78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703581615 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1703581615
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.600253125
Short name T157
Test name
Test status
Simulation time 30280217 ps
CPU time 0.96 seconds
Started Aug 10 07:22:13 PM PDT 24
Finished Aug 10 07:22:14 PM PDT 24
Peak memory 218596 kb
Host smart-12487f56-f103-486a-9fcc-bb9cd0f6e523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600253125 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.600253125
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2046573143
Short name T396
Test name
Test status
Simulation time 69503337 ps
CPU time 1.31 seconds
Started Aug 10 07:22:11 PM PDT 24
Finished Aug 10 07:22:13 PM PDT 24
Peak memory 219000 kb
Host smart-96d6864a-dd63-4df8-890e-ebadab131e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046573143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2046573143
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3022147179
Short name T664
Test name
Test status
Simulation time 21383916 ps
CPU time 1.03 seconds
Started Aug 10 07:22:12 PM PDT 24
Finished Aug 10 07:22:13 PM PDT 24
Peak memory 215964 kb
Host smart-4011f40d-1e17-4f1f-b97c-78b050079f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022147179 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3022147179
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.379805970
Short name T25
Test name
Test status
Simulation time 27309338 ps
CPU time 1 seconds
Started Aug 10 07:22:12 PM PDT 24
Finished Aug 10 07:22:14 PM PDT 24
Peak memory 215312 kb
Host smart-6fea6f53-f18c-4499-afea-1eae16cd4e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379805970 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.379805970
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.4140282490
Short name T480
Test name
Test status
Simulation time 19752925 ps
CPU time 1 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:16 PM PDT 24
Peak memory 206560 kb
Host smart-863329d9-d57e-4a26-bd3a-db17e17e642d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140282490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.4140282490
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_alert.4260061478
Short name T671
Test name
Test status
Simulation time 28643441 ps
CPU time 1.23 seconds
Started Aug 10 07:24:04 PM PDT 24
Finished Aug 10 07:24:06 PM PDT 24
Peak memory 219664 kb
Host smart-3d143004-8854-4fa6-9b1b-bafee512000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260061478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.4260061478
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.4245025511
Short name T645
Test name
Test status
Simulation time 75191212 ps
CPU time 1.73 seconds
Started Aug 10 07:24:06 PM PDT 24
Finished Aug 10 07:24:07 PM PDT 24
Peak memory 218796 kb
Host smart-b2abc005-8fb3-462f-8d6a-da3a627e5c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245025511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.4245025511
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.4177971380
Short name T707
Test name
Test status
Simulation time 86852090 ps
CPU time 1.34 seconds
Started Aug 10 07:24:06 PM PDT 24
Finished Aug 10 07:24:08 PM PDT 24
Peak memory 219572 kb
Host smart-c6ea5f0d-8426-441a-a864-49a35ced5f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177971380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.4177971380
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.3862051391
Short name T83
Test name
Test status
Simulation time 47830447 ps
CPU time 1.16 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:04 PM PDT 24
Peak memory 217360 kb
Host smart-af97674f-1361-4eba-8aab-2b374c40167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862051391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3862051391
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.3631299420
Short name T429
Test name
Test status
Simulation time 69375033 ps
CPU time 1.14 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 220096 kb
Host smart-ed71a862-ab6a-4175-b262-341d9c2abcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631299420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.3631299420
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3625330103
Short name T717
Test name
Test status
Simulation time 127242323 ps
CPU time 2.89 seconds
Started Aug 10 07:24:04 PM PDT 24
Finished Aug 10 07:24:07 PM PDT 24
Peak memory 220204 kb
Host smart-ff1bc140-e683-4a00-a1be-e33ee05ecffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625330103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3625330103
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.2366217977
Short name T55
Test name
Test status
Simulation time 22698487 ps
CPU time 1.17 seconds
Started Aug 10 07:24:03 PM PDT 24
Finished Aug 10 07:24:04 PM PDT 24
Peak memory 220024 kb
Host smart-d9c8a944-cab2-468a-bba8-a63d21f51162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366217977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.2366217977
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.758344335
Short name T401
Test name
Test status
Simulation time 133578009 ps
CPU time 1.39 seconds
Started Aug 10 07:24:01 PM PDT 24
Finished Aug 10 07:24:02 PM PDT 24
Peak memory 219800 kb
Host smart-63939ac6-c720-41a1-9870-babf2676059f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758344335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.758344335
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2049736251
Short name T907
Test name
Test status
Simulation time 23358553 ps
CPU time 1.12 seconds
Started Aug 10 07:24:00 PM PDT 24
Finished Aug 10 07:24:01 PM PDT 24
Peak memory 218596 kb
Host smart-06259ae5-9b29-4b3c-9a28-deaa36224c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049736251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2049736251
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.118172528
Short name T803
Test name
Test status
Simulation time 183546865 ps
CPU time 1.43 seconds
Started Aug 10 07:24:03 PM PDT 24
Finished Aug 10 07:24:04 PM PDT 24
Peak memory 218736 kb
Host smart-12f3acf8-7a1c-46b8-9325-43c3eaf78ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118172528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.118172528
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.4059054382
Short name T826
Test name
Test status
Simulation time 61798156 ps
CPU time 1.29 seconds
Started Aug 10 07:24:04 PM PDT 24
Finished Aug 10 07:24:06 PM PDT 24
Peak memory 218512 kb
Host smart-3ddae79c-144a-404a-88ee-b5d485d175f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059054382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.4059054382
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1437328790
Short name T322
Test name
Test status
Simulation time 39274460 ps
CPU time 1.44 seconds
Started Aug 10 07:24:01 PM PDT 24
Finished Aug 10 07:24:02 PM PDT 24
Peak memory 218772 kb
Host smart-0991dd73-1cdd-4749-994f-2b927d9f8ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437328790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1437328790
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.1567088501
Short name T107
Test name
Test status
Simulation time 27158278 ps
CPU time 1.25 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 220320 kb
Host smart-5bdaafbc-d8fd-46db-ad7f-f382fa8677a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567088501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1567088501
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.2217148548
Short name T960
Test name
Test status
Simulation time 60659905 ps
CPU time 1.73 seconds
Started Aug 10 07:24:01 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 218344 kb
Host smart-6e2d3972-a787-4718-a674-3a294222b904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217148548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2217148548
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2067050092
Short name T119
Test name
Test status
Simulation time 30462967 ps
CPU time 1.31 seconds
Started Aug 10 07:24:04 PM PDT 24
Finished Aug 10 07:24:06 PM PDT 24
Peak memory 219644 kb
Host smart-6938aa71-d11a-4e76-948b-5a28126a4abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067050092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2067050092
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.780431252
Short name T68
Test name
Test status
Simulation time 58305920 ps
CPU time 1.19 seconds
Started Aug 10 07:24:06 PM PDT 24
Finished Aug 10 07:24:08 PM PDT 24
Peak memory 218836 kb
Host smart-9a68ea56-f618-44e6-bfaf-774c034f87ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780431252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.780431252
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.4129931865
Short name T165
Test name
Test status
Simulation time 306326998 ps
CPU time 1.09 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 218420 kb
Host smart-ea0a19ab-a027-4afd-8156-0c3eecf21a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129931865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.4129931865
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.4204310998
Short name T578
Test name
Test status
Simulation time 88669171 ps
CPU time 1.24 seconds
Started Aug 10 07:24:02 PM PDT 24
Finished Aug 10 07:24:03 PM PDT 24
Peak memory 218660 kb
Host smart-30e0805d-0bdf-434c-bc71-ea137978fcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204310998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.4204310998
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1723855988
Short name T837
Test name
Test status
Simulation time 129929740 ps
CPU time 1.16 seconds
Started Aug 10 07:24:09 PM PDT 24
Finished Aug 10 07:24:11 PM PDT 24
Peak memory 220176 kb
Host smart-002b78fa-0227-4bc8-bbc1-8648c323b821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723855988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1723855988
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.667623713
Short name T369
Test name
Test status
Simulation time 61529807 ps
CPU time 1.48 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 218588 kb
Host smart-32a7742f-d72d-4463-b2ec-e963199c9339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667623713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.667623713
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1356474455
Short name T531
Test name
Test status
Simulation time 27546921 ps
CPU time 1.23 seconds
Started Aug 10 07:22:13 PM PDT 24
Finished Aug 10 07:22:15 PM PDT 24
Peak memory 219500 kb
Host smart-f9d570a6-15c5-43da-ae57-c13577554299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356474455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1356474455
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3825674222
Short name T695
Test name
Test status
Simulation time 13982943 ps
CPU time 0.86 seconds
Started Aug 10 07:22:22 PM PDT 24
Finished Aug 10 07:22:23 PM PDT 24
Peak memory 206812 kb
Host smart-3f24cd99-588f-4a7e-8521-f3747da982e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825674222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3825674222
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.373095644
Short name T936
Test name
Test status
Simulation time 13458976 ps
CPU time 0.9 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:27 PM PDT 24
Peak memory 219240 kb
Host smart-ab86a970-ed77-4960-85fc-58419ff75fed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373095644 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.373095644
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3521985782
Short name T149
Test name
Test status
Simulation time 167035894 ps
CPU time 1.06 seconds
Started Aug 10 07:22:21 PM PDT 24
Finished Aug 10 07:22:22 PM PDT 24
Peak memory 219628 kb
Host smart-d61b8f3f-465d-4501-a1b2-0ccc84b41481
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521985782 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3521985782
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1289372289
Short name T138
Test name
Test status
Simulation time 30472246 ps
CPU time 1.05 seconds
Started Aug 10 07:22:14 PM PDT 24
Finished Aug 10 07:22:15 PM PDT 24
Peak memory 224148 kb
Host smart-72fd7634-d5db-462d-bccb-dba8df6fcd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289372289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1289372289
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.627079028
Short name T632
Test name
Test status
Simulation time 123284953 ps
CPU time 1.18 seconds
Started Aug 10 07:22:12 PM PDT 24
Finished Aug 10 07:22:13 PM PDT 24
Peak memory 217600 kb
Host smart-d6e28f93-b76e-4d11-af50-12b76ad5ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627079028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.627079028
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.4285986740
Short name T667
Test name
Test status
Simulation time 21110601 ps
CPU time 1.02 seconds
Started Aug 10 07:22:15 PM PDT 24
Finished Aug 10 07:22:16 PM PDT 24
Peak memory 215416 kb
Host smart-4ba514ab-cc04-4b0b-b0e3-9e21540adeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285986740 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.4285986740
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2426054831
Short name T489
Test name
Test status
Simulation time 17278898 ps
CPU time 1 seconds
Started Aug 10 07:22:14 PM PDT 24
Finished Aug 10 07:22:15 PM PDT 24
Peak memory 215328 kb
Host smart-ef81e36e-a78b-4636-865c-2ff9a2be2bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426054831 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2426054831
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2966520740
Short name T498
Test name
Test status
Simulation time 395226939 ps
CPU time 2.54 seconds
Started Aug 10 07:22:16 PM PDT 24
Finished Aug 10 07:22:18 PM PDT 24
Peak memory 215260 kb
Host smart-1b1bc96b-a9d9-4abb-80b5-ed40766d4276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966520740 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2966520740
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1002867468
Short name T240
Test name
Test status
Simulation time 20568369092 ps
CPU time 443.86 seconds
Started Aug 10 07:22:11 PM PDT 24
Finished Aug 10 07:29:35 PM PDT 24
Peak memory 217972 kb
Host smart-4427e7e4-5f36-4038-911b-62234a250555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002867468 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1002867468
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.348667352
Short name T752
Test name
Test status
Simulation time 40676635 ps
CPU time 1.03 seconds
Started Aug 10 07:24:10 PM PDT 24
Finished Aug 10 07:24:11 PM PDT 24
Peak memory 217272 kb
Host smart-3440fd64-6275-4b37-aff2-2c4e29770385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348667352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.348667352
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.2700829441
Short name T877
Test name
Test status
Simulation time 49004878 ps
CPU time 1.3 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 218592 kb
Host smart-cf1e83cc-b560-45a6-bd4f-f5c0bd2a787d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700829441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2700829441
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1274265959
Short name T897
Test name
Test status
Simulation time 39536480 ps
CPU time 1.79 seconds
Started Aug 10 07:24:11 PM PDT 24
Finished Aug 10 07:24:13 PM PDT 24
Peak memory 219420 kb
Host smart-718ffbdc-f3d1-4a41-bc30-7d85ad86afd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274265959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1274265959
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.137016550
Short name T903
Test name
Test status
Simulation time 24743549 ps
CPU time 1.28 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 220484 kb
Host smart-17e49436-63e5-43d7-ba8f-f61eebe89873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137016550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.137016550
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3071623457
Short name T46
Test name
Test status
Simulation time 82830425 ps
CPU time 1.06 seconds
Started Aug 10 07:24:10 PM PDT 24
Finished Aug 10 07:24:11 PM PDT 24
Peak memory 217328 kb
Host smart-13c1dd8e-45bf-4051-a678-6889eca683ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071623457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3071623457
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.692568588
Short name T73
Test name
Test status
Simulation time 39505584 ps
CPU time 1.14 seconds
Started Aug 10 07:24:10 PM PDT 24
Finished Aug 10 07:24:11 PM PDT 24
Peak memory 217208 kb
Host smart-a3b56a33-b1be-4b78-a2a4-e15bf81b8f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692568588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.692568588
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.4160758710
Short name T584
Test name
Test status
Simulation time 78113154 ps
CPU time 1.21 seconds
Started Aug 10 07:24:17 PM PDT 24
Finished Aug 10 07:24:19 PM PDT 24
Peak memory 218596 kb
Host smart-5bad3479-db03-406b-83e3-c2bd6fa19501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160758710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.4160758710
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2863206355
Short name T842
Test name
Test status
Simulation time 63091876 ps
CPU time 1 seconds
Started Aug 10 07:24:09 PM PDT 24
Finished Aug 10 07:24:10 PM PDT 24
Peak memory 217428 kb
Host smart-ce41884e-c752-4ced-b465-ddb9670b9eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863206355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2863206355
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3689435658
Short name T347
Test name
Test status
Simulation time 86622425 ps
CPU time 1.19 seconds
Started Aug 10 07:24:09 PM PDT 24
Finished Aug 10 07:24:10 PM PDT 24
Peak memory 219120 kb
Host smart-3f0d8520-eda3-45fd-96f8-8e68e36994b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689435658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3689435658
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.3382738649
Short name T940
Test name
Test status
Simulation time 141293659 ps
CPU time 2.93 seconds
Started Aug 10 07:24:10 PM PDT 24
Finished Aug 10 07:24:13 PM PDT 24
Peak memory 220360 kb
Host smart-f7dd81b4-4bce-44d2-ac52-77bcd84612ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382738649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3382738649
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1516093123
Short name T124
Test name
Test status
Simulation time 44015558 ps
CPU time 1.28 seconds
Started Aug 10 07:24:11 PM PDT 24
Finished Aug 10 07:24:13 PM PDT 24
Peak memory 218524 kb
Host smart-fd3c8772-54bc-4fff-b570-5c47fc83957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516093123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1516093123
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/178.edn_alert.1958595218
Short name T703
Test name
Test status
Simulation time 66897511 ps
CPU time 1.07 seconds
Started Aug 10 07:24:11 PM PDT 24
Finished Aug 10 07:24:12 PM PDT 24
Peak memory 219532 kb
Host smart-6009bb7b-44e4-4ac4-b8d6-53051620e625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958595218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1958595218
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.1795524834
Short name T544
Test name
Test status
Simulation time 134323294 ps
CPU time 1.81 seconds
Started Aug 10 07:24:17 PM PDT 24
Finished Aug 10 07:24:19 PM PDT 24
Peak memory 219036 kb
Host smart-de384cf2-a321-4c40-8602-1905ee4c7d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795524834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1795524834
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.1123024448
Short name T839
Test name
Test status
Simulation time 25524313 ps
CPU time 1.25 seconds
Started Aug 10 07:24:18 PM PDT 24
Finished Aug 10 07:24:20 PM PDT 24
Peak memory 219452 kb
Host smart-d0fe1b43-2f92-40f2-88ef-e8457d79a4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123024448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.1123024448
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.323449923
Short name T962
Test name
Test status
Simulation time 69349622 ps
CPU time 1.56 seconds
Started Aug 10 07:24:11 PM PDT 24
Finished Aug 10 07:24:13 PM PDT 24
Peak memory 217516 kb
Host smart-4e9a0c68-2507-4bc4-98fa-579e6483fdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323449923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.323449923
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.4076758271
Short name T231
Test name
Test status
Simulation time 23846762 ps
CPU time 1.22 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:24 PM PDT 24
Peak memory 218720 kb
Host smart-434bc75a-1fc8-4842-a5c3-5eefbb06ec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076758271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.4076758271
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.4042756516
Short name T380
Test name
Test status
Simulation time 18052135 ps
CPU time 0.98 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:24 PM PDT 24
Peak memory 206856 kb
Host smart-884283ed-5825-4b98-951e-e094e46c9e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042756516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.4042756516
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1142913443
Short name T772
Test name
Test status
Simulation time 10510134 ps
CPU time 0.87 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:27 PM PDT 24
Peak memory 216448 kb
Host smart-03f18633-d9e7-40f2-a2b8-f9b869f3b7fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142913443 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1142913443
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1351096666
Short name T132
Test name
Test status
Simulation time 93331530 ps
CPU time 1.11 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:24 PM PDT 24
Peak memory 215580 kb
Host smart-29fc0a89-788f-4939-bbb8-5e99c1be77be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351096666 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1351096666
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.4078762153
Short name T7
Test name
Test status
Simulation time 32845212 ps
CPU time 0.93 seconds
Started Aug 10 07:22:24 PM PDT 24
Finished Aug 10 07:22:25 PM PDT 24
Peak memory 218776 kb
Host smart-a2ce36c4-4f1d-4348-9dc8-004b7f86d2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078762153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.4078762153
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.3069541616
Short name T869
Test name
Test status
Simulation time 37684727 ps
CPU time 0.9 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:27 PM PDT 24
Peak memory 215464 kb
Host smart-d79f5e48-5828-4d05-8734-a5f6311829fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069541616 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3069541616
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1280481119
Short name T723
Test name
Test status
Simulation time 17538502 ps
CPU time 1.03 seconds
Started Aug 10 07:22:22 PM PDT 24
Finished Aug 10 07:22:23 PM PDT 24
Peak memory 215328 kb
Host smart-2f25bdae-89c3-4bc4-84c0-9268b3c49f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280481119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1280481119
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1448463024
Short name T428
Test name
Test status
Simulation time 184611981 ps
CPU time 2.44 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:29 PM PDT 24
Peak memory 220156 kb
Host smart-9a51bd31-2cba-43bf-ac5c-8cbf5d2f0bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448463024 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1448463024
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1358596102
Short name T262
Test name
Test status
Simulation time 226922086396 ps
CPU time 1378.32 seconds
Started Aug 10 07:22:27 PM PDT 24
Finished Aug 10 07:45:25 PM PDT 24
Peak memory 222584 kb
Host smart-f6ee2d6d-5240-469b-92cb-42dec85e13ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358596102 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1358596102
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.4149227121
Short name T456
Test name
Test status
Simulation time 86972039 ps
CPU time 1.12 seconds
Started Aug 10 07:24:08 PM PDT 24
Finished Aug 10 07:24:09 PM PDT 24
Peak memory 218340 kb
Host smart-ae0f2f6f-a884-431e-a853-970dd2386fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149227121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.4149227121
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/181.edn_alert.3469609065
Short name T430
Test name
Test status
Simulation time 263956027 ps
CPU time 1.4 seconds
Started Aug 10 07:24:09 PM PDT 24
Finished Aug 10 07:24:10 PM PDT 24
Peak memory 220836 kb
Host smart-d9ede932-b888-441b-9fc6-49b94af90894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469609065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3469609065
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.153567153
Short name T319
Test name
Test status
Simulation time 34726221 ps
CPU time 1.33 seconds
Started Aug 10 07:24:17 PM PDT 24
Finished Aug 10 07:24:19 PM PDT 24
Peak memory 220108 kb
Host smart-2358ae29-50a9-4a80-9f70-8da31ca01b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153567153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.153567153
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.88607405
Short name T718
Test name
Test status
Simulation time 73708922 ps
CPU time 1.42 seconds
Started Aug 10 07:24:15 PM PDT 24
Finished Aug 10 07:24:17 PM PDT 24
Peak memory 218736 kb
Host smart-6f6814a4-dd3e-4d45-b8f7-e7d9a1e9a161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88607405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.88607405
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1006914712
Short name T919
Test name
Test status
Simulation time 42474568 ps
CPU time 1.54 seconds
Started Aug 10 07:24:09 PM PDT 24
Finished Aug 10 07:24:11 PM PDT 24
Peak memory 218408 kb
Host smart-cef6af42-fb9a-408c-81cd-7fa003030094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006914712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1006914712
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3398021615
Short name T522
Test name
Test status
Simulation time 22780193 ps
CPU time 1.21 seconds
Started Aug 10 07:24:14 PM PDT 24
Finished Aug 10 07:24:15 PM PDT 24
Peak memory 218428 kb
Host smart-d786862d-4095-47e7-a20d-517df74e530d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398021615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3398021615
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.4017548012
Short name T419
Test name
Test status
Simulation time 144136599 ps
CPU time 1.87 seconds
Started Aug 10 07:24:15 PM PDT 24
Finished Aug 10 07:24:17 PM PDT 24
Peak memory 219736 kb
Host smart-47378d35-19fa-4c6c-b683-8dbefdfb68c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017548012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.4017548012
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.4043858004
Short name T265
Test name
Test status
Simulation time 50183199 ps
CPU time 1.3 seconds
Started Aug 10 07:24:07 PM PDT 24
Finished Aug 10 07:24:08 PM PDT 24
Peak memory 218608 kb
Host smart-8aeee40e-bc88-4fd0-95cd-e1f2555a924e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043858004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.4043858004
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2183677005
Short name T576
Test name
Test status
Simulation time 68628958 ps
CPU time 1.1 seconds
Started Aug 10 07:24:15 PM PDT 24
Finished Aug 10 07:24:16 PM PDT 24
Peak memory 217492 kb
Host smart-d41b8a0a-1b06-45b6-a4c8-914143619c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183677005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2183677005
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.1972043248
Short name T409
Test name
Test status
Simulation time 29575820 ps
CPU time 1.33 seconds
Started Aug 10 07:24:14 PM PDT 24
Finished Aug 10 07:24:15 PM PDT 24
Peak memory 219396 kb
Host smart-155c39ca-44bf-434d-916e-c86b60ead169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972043248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.1972043248
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.4217648350
Short name T926
Test name
Test status
Simulation time 49843221 ps
CPU time 1.48 seconds
Started Aug 10 07:24:08 PM PDT 24
Finished Aug 10 07:24:10 PM PDT 24
Peak memory 218408 kb
Host smart-c575e733-e99b-44e9-9a50-4ac62eafa42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217648350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4217648350
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.2239859757
Short name T183
Test name
Test status
Simulation time 65730706 ps
CPU time 1.01 seconds
Started Aug 10 07:24:18 PM PDT 24
Finished Aug 10 07:24:19 PM PDT 24
Peak memory 218744 kb
Host smart-39465087-b18d-4e8b-98b8-c30a808d5b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239859757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2239859757
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.1826117126
Short name T995
Test name
Test status
Simulation time 67467303 ps
CPU time 1.02 seconds
Started Aug 10 07:24:18 PM PDT 24
Finished Aug 10 07:24:19 PM PDT 24
Peak memory 217436 kb
Host smart-0a7bea6c-2f05-42d7-8019-e959a6892c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826117126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1826117126
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.5283545
Short name T126
Test name
Test status
Simulation time 112210474 ps
CPU time 1.28 seconds
Started Aug 10 07:24:23 PM PDT 24
Finished Aug 10 07:24:25 PM PDT 24
Peak memory 218292 kb
Host smart-fd7c3e76-e5e2-4deb-ac3c-a2dea0580b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5283545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.5283545
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.1551924589
Short name T14
Test name
Test status
Simulation time 40757822 ps
CPU time 1.48 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:20 PM PDT 24
Peak memory 219824 kb
Host smart-8de55ad6-5797-4606-9d9d-c5a65d7f99d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551924589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1551924589
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.1292908931
Short name T108
Test name
Test status
Simulation time 29507092 ps
CPU time 1.32 seconds
Started Aug 10 07:24:17 PM PDT 24
Finished Aug 10 07:24:18 PM PDT 24
Peak memory 218556 kb
Host smart-c3f1fd5c-b571-4033-8e8d-d80dc18a71b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292908931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1292908931
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2962521226
Short name T550
Test name
Test status
Simulation time 77412307 ps
CPU time 1.1 seconds
Started Aug 10 07:24:21 PM PDT 24
Finished Aug 10 07:24:22 PM PDT 24
Peak memory 217356 kb
Host smart-cf64ac4e-652a-4b1a-8919-733a073550d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962521226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2962521226
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.4139839290
Short name T920
Test name
Test status
Simulation time 27615706 ps
CPU time 1.27 seconds
Started Aug 10 07:22:24 PM PDT 24
Finished Aug 10 07:22:25 PM PDT 24
Peak memory 219472 kb
Host smart-7f32403c-297c-4947-9140-a1512a3f9d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139839290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.4139839290
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3989012622
Short name T362
Test name
Test status
Simulation time 48572242 ps
CPU time 0.86 seconds
Started Aug 10 07:22:22 PM PDT 24
Finished Aug 10 07:22:23 PM PDT 24
Peak memory 206872 kb
Host smart-88afd3d1-0d3f-48d2-a946-7393a865c1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989012622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3989012622
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.4293123980
Short name T345
Test name
Test status
Simulation time 110200590 ps
CPU time 0.89 seconds
Started Aug 10 07:22:24 PM PDT 24
Finished Aug 10 07:22:25 PM PDT 24
Peak memory 216344 kb
Host smart-ac763c45-88eb-434d-a8da-b3e8c03c983b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293123980 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.4293123980
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2048383224
Short name T69
Test name
Test status
Simulation time 111069874 ps
CPU time 1.44 seconds
Started Aug 10 07:22:22 PM PDT 24
Finished Aug 10 07:22:24 PM PDT 24
Peak memory 217144 kb
Host smart-74ba1044-7eed-4009-b802-845f9b83e9d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048383224 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2048383224
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3807122984
Short name T791
Test name
Test status
Simulation time 70354367 ps
CPU time 1.16 seconds
Started Aug 10 07:22:24 PM PDT 24
Finished Aug 10 07:22:25 PM PDT 24
Peak memory 225880 kb
Host smart-b544d48d-5551-4544-b17d-f7abccbf71d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807122984 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3807122984
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1624330722
Short name T387
Test name
Test status
Simulation time 239699937 ps
CPU time 1.17 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:25 PM PDT 24
Peak memory 217208 kb
Host smart-db6795fc-c1ac-4145-a06a-278caf360411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624330722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1624330722
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.4114134083
Short name T60
Test name
Test status
Simulation time 29579240 ps
CPU time 1.12 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:24 PM PDT 24
Peak memory 224284 kb
Host smart-6383a7a9-f984-47bd-a025-8a009748c72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114134083 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.4114134083
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3856184967
Short name T465
Test name
Test status
Simulation time 51643548 ps
CPU time 0.93 seconds
Started Aug 10 07:22:22 PM PDT 24
Finished Aug 10 07:22:23 PM PDT 24
Peak memory 215292 kb
Host smart-5f6cabda-13de-44e2-acef-ba24eab8f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856184967 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3856184967
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3134875578
Short name T491
Test name
Test status
Simulation time 1027183263 ps
CPU time 6.07 seconds
Started Aug 10 07:22:21 PM PDT 24
Finished Aug 10 07:22:27 PM PDT 24
Peak memory 217348 kb
Host smart-70910a13-02b9-4009-a04e-9282c45e06ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134875578 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3134875578
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3632433626
Short name T525
Test name
Test status
Simulation time 235737213878 ps
CPU time 1280.95 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:43:44 PM PDT 24
Peak memory 223116 kb
Host smart-f8da09d0-0437-413a-9258-bbe0fe3b9944
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632433626 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3632433626
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2687253439
Short name T756
Test name
Test status
Simulation time 23846806 ps
CPU time 1.19 seconds
Started Aug 10 07:24:23 PM PDT 24
Finished Aug 10 07:24:25 PM PDT 24
Peak memory 219256 kb
Host smart-b3cfca44-2a8e-46c5-bb1f-87b4bf257abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687253439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2687253439
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3550380098
Short name T472
Test name
Test status
Simulation time 525157409 ps
CPU time 2.48 seconds
Started Aug 10 07:24:18 PM PDT 24
Finished Aug 10 07:24:20 PM PDT 24
Peak memory 220024 kb
Host smart-f5a66c15-9053-4d47-b1f5-16729941df40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550380098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3550380098
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.1497289267
Short name T719
Test name
Test status
Simulation time 43683165 ps
CPU time 1.1 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:20 PM PDT 24
Peak memory 219524 kb
Host smart-55c91551-232b-4e0a-9844-91a73e2f3948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497289267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1497289267
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.3831800199
Short name T659
Test name
Test status
Simulation time 105930530 ps
CPU time 1.3 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 218716 kb
Host smart-a6a998c3-b030-4149-bf9c-562df496375a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831800199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3831800199
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2822309824
Short name T51
Test name
Test status
Simulation time 61774105 ps
CPU time 1.21 seconds
Started Aug 10 07:24:21 PM PDT 24
Finished Aug 10 07:24:23 PM PDT 24
Peak memory 218860 kb
Host smart-a5c98fe7-eec1-40ac-920e-d6403ad2600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822309824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2822309824
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.322267200
Short name T327
Test name
Test status
Simulation time 140115262 ps
CPU time 1.3 seconds
Started Aug 10 07:24:20 PM PDT 24
Finished Aug 10 07:24:22 PM PDT 24
Peak memory 220020 kb
Host smart-c96e4b10-dea5-4e82-95e4-552a23ac5e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322267200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.322267200
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2412571625
Short name T814
Test name
Test status
Simulation time 41589978 ps
CPU time 1.18 seconds
Started Aug 10 07:24:24 PM PDT 24
Finished Aug 10 07:24:25 PM PDT 24
Peak memory 218528 kb
Host smart-89ece6c4-9fd2-456d-831d-822eee3f97d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412571625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2412571625
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2427524114
Short name T511
Test name
Test status
Simulation time 88982970 ps
CPU time 1.32 seconds
Started Aug 10 07:24:18 PM PDT 24
Finished Aug 10 07:24:19 PM PDT 24
Peak memory 219648 kb
Host smart-93d7d1f0-b9ef-4043-9362-a9986c0863b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427524114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2427524114
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2864946081
Short name T514
Test name
Test status
Simulation time 24716108 ps
CPU time 1.24 seconds
Started Aug 10 07:24:20 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 219528 kb
Host smart-7d85704a-2bdb-46c7-9f45-a4847ea23fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864946081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2864946081
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.2359044491
Short name T513
Test name
Test status
Simulation time 49535761 ps
CPU time 1.65 seconds
Started Aug 10 07:24:18 PM PDT 24
Finished Aug 10 07:24:20 PM PDT 24
Peak memory 220020 kb
Host smart-4f7ee337-a6ad-4815-bb36-13cfa0e9e107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359044491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2359044491
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.523379688
Short name T179
Test name
Test status
Simulation time 49152255 ps
CPU time 1.05 seconds
Started Aug 10 07:24:22 PM PDT 24
Finished Aug 10 07:24:23 PM PDT 24
Peak memory 219424 kb
Host smart-523c1af2-f650-4f8d-b97c-33801770df37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523379688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.523379688
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.333975235
Short name T853
Test name
Test status
Simulation time 134619927 ps
CPU time 1.51 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 218992 kb
Host smart-5bf952ea-21aa-4fc4-af06-aaee23a5ae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333975235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.333975235
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.813161959
Short name T879
Test name
Test status
Simulation time 67488937 ps
CPU time 1.14 seconds
Started Aug 10 07:24:18 PM PDT 24
Finished Aug 10 07:24:19 PM PDT 24
Peak memory 219408 kb
Host smart-555c1e0d-aedc-4573-8097-c6162f434d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813161959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.813161959
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.1205898774
Short name T979
Test name
Test status
Simulation time 59013582 ps
CPU time 1.24 seconds
Started Aug 10 07:24:21 PM PDT 24
Finished Aug 10 07:24:23 PM PDT 24
Peak memory 218856 kb
Host smart-1da8d183-df24-470e-81a5-00c2c1697697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205898774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1205898774
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.4107968933
Short name T86
Test name
Test status
Simulation time 23068943 ps
CPU time 1.19 seconds
Started Aug 10 07:24:22 PM PDT 24
Finished Aug 10 07:24:23 PM PDT 24
Peak memory 219804 kb
Host smart-76925440-48d5-4432-a447-d77ca27342a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107968933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.4107968933
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.1358681608
Short name T775
Test name
Test status
Simulation time 42474178 ps
CPU time 1.2 seconds
Started Aug 10 07:24:20 PM PDT 24
Finished Aug 10 07:24:22 PM PDT 24
Peak memory 217500 kb
Host smart-f45fbbf6-5e57-46ce-8a41-2254de4cb3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358681608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1358681608
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.3400841458
Short name T650
Test name
Test status
Simulation time 173859817 ps
CPU time 1.23 seconds
Started Aug 10 07:24:23 PM PDT 24
Finished Aug 10 07:24:25 PM PDT 24
Peak memory 220588 kb
Host smart-c1459ec8-d6ea-49ad-bd0a-43ab25d6d773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400841458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3400841458
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2516333556
Short name T431
Test name
Test status
Simulation time 56918234 ps
CPU time 1.81 seconds
Started Aug 10 07:24:17 PM PDT 24
Finished Aug 10 07:24:19 PM PDT 24
Peak memory 218400 kb
Host smart-4ac6b06f-c412-4c9b-a579-c107127c84dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516333556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2516333556
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3703611386
Short name T696
Test name
Test status
Simulation time 37875416 ps
CPU time 1.14 seconds
Started Aug 10 07:21:37 PM PDT 24
Finished Aug 10 07:21:38 PM PDT 24
Peak memory 219728 kb
Host smart-2489a576-a51f-4dc3-aa38-495c4ec677cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703611386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3703611386
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2580049456
Short name T738
Test name
Test status
Simulation time 17488545 ps
CPU time 0.96 seconds
Started Aug 10 07:21:38 PM PDT 24
Finished Aug 10 07:21:39 PM PDT 24
Peak memory 206820 kb
Host smart-530f05bc-8fa2-4d87-b873-042f5c7617ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580049456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2580049456
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2971816307
Short name T609
Test name
Test status
Simulation time 193237995 ps
CPU time 1.14 seconds
Started Aug 10 07:21:35 PM PDT 24
Finished Aug 10 07:21:36 PM PDT 24
Peak memory 219584 kb
Host smart-dd79eee3-98f8-455c-81df-9109cb03f653
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971816307 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2971816307
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.401396479
Short name T62
Test name
Test status
Simulation time 19314008 ps
CPU time 1.14 seconds
Started Aug 10 07:21:38 PM PDT 24
Finished Aug 10 07:21:39 PM PDT 24
Peak memory 224172 kb
Host smart-d92192b7-2bb4-47ba-87ab-2ab3b442579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401396479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.401396479
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.4217395913
Short name T82
Test name
Test status
Simulation time 33301978 ps
CPU time 1.72 seconds
Started Aug 10 07:21:36 PM PDT 24
Finished Aug 10 07:21:38 PM PDT 24
Peak memory 217588 kb
Host smart-85c00d07-cdcf-4dd7-b07c-af5148cf5033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217395913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.4217395913
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3918468271
Short name T34
Test name
Test status
Simulation time 31442554 ps
CPU time 0.86 seconds
Started Aug 10 07:21:35 PM PDT 24
Finished Aug 10 07:21:36 PM PDT 24
Peak memory 215848 kb
Host smart-5faa342c-7ea3-4813-ac85-4a09b0ea359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918468271 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3918468271
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1525771078
Short name T959
Test name
Test status
Simulation time 25217982 ps
CPU time 0.89 seconds
Started Aug 10 07:21:38 PM PDT 24
Finished Aug 10 07:21:38 PM PDT 24
Peak memory 207108 kb
Host smart-a5ead7db-00b9-47c2-9ec2-dbf776c2547b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525771078 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1525771078
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2242558188
Short name T66
Test name
Test status
Simulation time 2431193287 ps
CPU time 7.03 seconds
Started Aug 10 07:21:38 PM PDT 24
Finished Aug 10 07:21:45 PM PDT 24
Peak memory 240208 kb
Host smart-7d700262-0747-47e1-917f-2b156be412b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242558188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2242558188
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.18545371
Short name T849
Test name
Test status
Simulation time 17360856 ps
CPU time 1.03 seconds
Started Aug 10 07:21:36 PM PDT 24
Finished Aug 10 07:21:37 PM PDT 24
Peak memory 215300 kb
Host smart-b0c70568-3683-4829-a01d-26b6d003da52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18545371 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.18545371
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3870766580
Short name T248
Test name
Test status
Simulation time 772590985 ps
CPU time 2.6 seconds
Started Aug 10 07:21:36 PM PDT 24
Finished Aug 10 07:21:39 PM PDT 24
Peak memory 217400 kb
Host smart-2a0c9775-028e-4413-b544-1dc3c7bcccf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870766580 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3870766580
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.172451560
Short name T851
Test name
Test status
Simulation time 39820138302 ps
CPU time 1005.92 seconds
Started Aug 10 07:21:38 PM PDT 24
Finished Aug 10 07:38:25 PM PDT 24
Peak memory 223568 kb
Host smart-79bda762-74d2-4545-b298-75bd097eae73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172451560 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.172451560
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.171618232
Short name T133
Test name
Test status
Simulation time 68133133 ps
CPU time 1.08 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:25 PM PDT 24
Peak memory 219684 kb
Host smart-8d331516-cd92-4e95-9f41-3577659f4426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171618232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.171618232
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2063415062
Short name T438
Test name
Test status
Simulation time 35535436 ps
CPU time 1.1 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:25 PM PDT 24
Peak memory 215164 kb
Host smart-849f4c49-d41f-40dc-bff3-e41573f94ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063415062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2063415062
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1210575459
Short name T411
Test name
Test status
Simulation time 10105051 ps
CPU time 0.87 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:24 PM PDT 24
Peak memory 216232 kb
Host smart-4f88f82e-4891-4154-931e-f457145080f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210575459 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1210575459
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1866187995
Short name T210
Test name
Test status
Simulation time 33281181 ps
CPU time 1.15 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:28 PM PDT 24
Peak memory 219664 kb
Host smart-a1ce0c66-d2bb-4d38-bd26-55c82d6497be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866187995 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1866187995
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2430457093
Short name T548
Test name
Test status
Simulation time 43844761 ps
CPU time 0.85 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:27 PM PDT 24
Peak memory 218804 kb
Host smart-911e4c1d-6e6e-4c9c-97cf-643ab5ee1ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430457093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2430457093
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3704492609
Short name T47
Test name
Test status
Simulation time 62823065 ps
CPU time 1.45 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:25 PM PDT 24
Peak memory 218744 kb
Host smart-fbbf6023-974c-472e-af9a-928834cd4a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704492609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3704492609
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.557411875
Short name T444
Test name
Test status
Simulation time 25368073 ps
CPU time 0.96 seconds
Started Aug 10 07:22:22 PM PDT 24
Finished Aug 10 07:22:23 PM PDT 24
Peak memory 216000 kb
Host smart-cb717552-9711-4810-8ce7-77827e0ca0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557411875 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.557411875
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3417850686
Short name T103
Test name
Test status
Simulation time 18946997 ps
CPU time 0.98 seconds
Started Aug 10 07:22:24 PM PDT 24
Finished Aug 10 07:22:25 PM PDT 24
Peak memory 207076 kb
Host smart-8d937816-aace-4177-94e6-aae57b434caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417850686 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3417850686
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1139873449
Short name T603
Test name
Test status
Simulation time 352316178 ps
CPU time 2.36 seconds
Started Aug 10 07:22:22 PM PDT 24
Finished Aug 10 07:22:24 PM PDT 24
Peak memory 217312 kb
Host smart-6a113c6f-7a2d-4dd2-9926-33a2061ccb66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139873449 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1139873449
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2677156195
Short name T848
Test name
Test status
Simulation time 353509271428 ps
CPU time 2333.09 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 08:01:19 PM PDT 24
Peak memory 230544 kb
Host smart-cb2f0fcc-a9b9-4733-b6e6-2c6fc1f710d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677156195 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2677156195
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2910536812
Short name T482
Test name
Test status
Simulation time 36438607 ps
CPU time 1.07 seconds
Started Aug 10 07:24:18 PM PDT 24
Finished Aug 10 07:24:19 PM PDT 24
Peak memory 218684 kb
Host smart-db2edba3-d3a1-45fe-b551-0c926f127283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910536812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2910536812
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3962015297
Short name T13
Test name
Test status
Simulation time 124779175 ps
CPU time 1.25 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:20 PM PDT 24
Peak memory 219992 kb
Host smart-16a640b5-6943-4509-85df-a1e8e78f1ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962015297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3962015297
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.4230719200
Short name T50
Test name
Test status
Simulation time 60380932 ps
CPU time 1.69 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 218348 kb
Host smart-611b9d20-8d7f-42ab-a02d-27301a9e30e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230719200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.4230719200
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1537166413
Short name T361
Test name
Test status
Simulation time 34576741 ps
CPU time 1.26 seconds
Started Aug 10 07:24:17 PM PDT 24
Finished Aug 10 07:24:18 PM PDT 24
Peak memory 217396 kb
Host smart-4a7fed0a-1b84-4633-a68f-2f3fad5fe42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537166413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1537166413
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3041409210
Short name T862
Test name
Test status
Simulation time 92534515 ps
CPU time 1.27 seconds
Started Aug 10 07:24:20 PM PDT 24
Finished Aug 10 07:24:22 PM PDT 24
Peak memory 217384 kb
Host smart-2db9a697-79d6-4154-8e68-d9a577906cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041409210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3041409210
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1912018628
Short name T771
Test name
Test status
Simulation time 157156553 ps
CPU time 2.38 seconds
Started Aug 10 07:24:24 PM PDT 24
Finished Aug 10 07:24:27 PM PDT 24
Peak memory 219868 kb
Host smart-8c55b7db-5e27-4911-b1bd-25b1e2d07d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912018628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1912018628
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.482337735
Short name T323
Test name
Test status
Simulation time 60988961 ps
CPU time 1.15 seconds
Started Aug 10 07:24:21 PM PDT 24
Finished Aug 10 07:24:23 PM PDT 24
Peak memory 219160 kb
Host smart-5e89f315-d476-4b4f-89f0-14ad72e51544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482337735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.482337735
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.407181337
Short name T728
Test name
Test status
Simulation time 43216692 ps
CPU time 1.09 seconds
Started Aug 10 07:24:23 PM PDT 24
Finished Aug 10 07:24:25 PM PDT 24
Peak memory 217292 kb
Host smart-2f2de7a8-30b3-4daf-ada4-533d21d0a8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407181337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.407181337
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1815398748
Short name T339
Test name
Test status
Simulation time 80884801 ps
CPU time 1.28 seconds
Started Aug 10 07:24:20 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 218840 kb
Host smart-e1bd3735-2ab9-4fc9-bba0-0962b4a0e222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815398748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1815398748
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.4095862522
Short name T992
Test name
Test status
Simulation time 44836437 ps
CPU time 1.11 seconds
Started Aug 10 07:24:22 PM PDT 24
Finished Aug 10 07:24:23 PM PDT 24
Peak memory 217292 kb
Host smart-95b0c564-2472-4691-a9ba-daed92b1cfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095862522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.4095862522
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2874831636
Short name T716
Test name
Test status
Simulation time 107046149 ps
CPU time 1.33 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:28 PM PDT 24
Peak memory 221156 kb
Host smart-e9486082-6c55-4676-a553-0cee1912dd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874831636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2874831636
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.528672091
Short name T72
Test name
Test status
Simulation time 13110258 ps
CPU time 0.87 seconds
Started Aug 10 07:22:25 PM PDT 24
Finished Aug 10 07:22:26 PM PDT 24
Peak memory 206836 kb
Host smart-13256d9a-0a05-4856-aa5b-3dec5c6bd889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528672091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.528672091
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.4074119120
Short name T209
Test name
Test status
Simulation time 46531640 ps
CPU time 1.11 seconds
Started Aug 10 07:22:27 PM PDT 24
Finished Aug 10 07:22:28 PM PDT 24
Peak memory 219648 kb
Host smart-cc2a1d9b-f685-4c30-8421-05d99ae00833
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074119120 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.4074119120
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.21269481
Short name T682
Test name
Test status
Simulation time 25227853 ps
CPU time 0.92 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:27 PM PDT 24
Peak memory 218356 kb
Host smart-3b2a7dc7-d06d-43eb-9e88-77debcb34e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21269481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.21269481
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.206782487
Short name T332
Test name
Test status
Simulation time 85117230 ps
CPU time 1.15 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:25 PM PDT 24
Peak memory 217488 kb
Host smart-41d99fdb-7d2e-4619-8465-b14982e4ff30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206782487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.206782487
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1973880676
Short name T593
Test name
Test status
Simulation time 32325345 ps
CPU time 1.28 seconds
Started Aug 10 07:22:25 PM PDT 24
Finished Aug 10 07:22:27 PM PDT 24
Peak memory 215400 kb
Host smart-0e8615d1-4ae9-458f-b88f-8c38adf926bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973880676 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1973880676
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1482262384
Short name T552
Test name
Test status
Simulation time 18365428 ps
CPU time 1.1 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:24 PM PDT 24
Peak memory 215272 kb
Host smart-1ae040b2-82f8-4789-b98d-87c3a469856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482262384 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1482262384
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3223377824
Short name T579
Test name
Test status
Simulation time 131432545 ps
CPU time 3.03 seconds
Started Aug 10 07:22:22 PM PDT 24
Finished Aug 10 07:22:26 PM PDT 24
Peak memory 217140 kb
Host smart-e02fb081-0d2f-44eb-809e-95817fea601d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223377824 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3223377824
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.461311300
Short name T824
Test name
Test status
Simulation time 36662835606 ps
CPU time 460.25 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:30:03 PM PDT 24
Peak memory 223668 kb
Host smart-be68659d-f58a-4aae-b181-cfabe86339db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461311300 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.461311300
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.142543399
Short name T660
Test name
Test status
Simulation time 53751510 ps
CPU time 1.88 seconds
Started Aug 10 07:24:22 PM PDT 24
Finished Aug 10 07:24:24 PM PDT 24
Peak memory 218740 kb
Host smart-a6a3eb22-737e-46aa-b472-4e1a8fdeec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142543399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.142543399
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3852361478
Short name T574
Test name
Test status
Simulation time 51859266 ps
CPU time 1.35 seconds
Started Aug 10 07:24:22 PM PDT 24
Finished Aug 10 07:24:23 PM PDT 24
Peak memory 219004 kb
Host smart-5f5d0ba1-e02c-4a06-89b4-99b222faa2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852361478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3852361478
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2814677177
Short name T840
Test name
Test status
Simulation time 56014875 ps
CPU time 1.23 seconds
Started Aug 10 07:24:18 PM PDT 24
Finished Aug 10 07:24:20 PM PDT 24
Peak memory 219912 kb
Host smart-b07dec90-35bb-4c27-8ec8-39b40070124f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814677177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2814677177
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3779747229
Short name T338
Test name
Test status
Simulation time 80406953 ps
CPU time 2.92 seconds
Started Aug 10 07:24:22 PM PDT 24
Finished Aug 10 07:24:25 PM PDT 24
Peak memory 220496 kb
Host smart-aa077884-43d3-48b8-8830-4603b0395824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779747229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3779747229
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2398408100
Short name T657
Test name
Test status
Simulation time 88153495 ps
CPU time 1.18 seconds
Started Aug 10 07:24:18 PM PDT 24
Finished Aug 10 07:24:19 PM PDT 24
Peak memory 217444 kb
Host smart-c70b644c-2c30-45f0-95e0-af29697ee9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398408100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2398408100
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.172518948
Short name T78
Test name
Test status
Simulation time 39112134 ps
CPU time 1.23 seconds
Started Aug 10 07:24:24 PM PDT 24
Finished Aug 10 07:24:25 PM PDT 24
Peak memory 218660 kb
Host smart-241dc673-d32d-4005-9e77-3bc6679ccb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172518948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.172518948
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.118053164
Short name T461
Test name
Test status
Simulation time 42449629 ps
CPU time 1.14 seconds
Started Aug 10 07:24:20 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 217736 kb
Host smart-b153dfe5-7386-4083-973c-4db306bb2d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118053164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.118053164
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3178646236
Short name T944
Test name
Test status
Simulation time 122324144 ps
CPU time 1.39 seconds
Started Aug 10 07:24:20 PM PDT 24
Finished Aug 10 07:24:22 PM PDT 24
Peak memory 219768 kb
Host smart-0c8524e4-6d08-4402-b508-7953ecc43171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178646236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3178646236
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3857045423
Short name T328
Test name
Test status
Simulation time 108944354 ps
CPU time 1.22 seconds
Started Aug 10 07:24:21 PM PDT 24
Finished Aug 10 07:24:23 PM PDT 24
Peak memory 220052 kb
Host smart-27bd701a-23e3-4ee1-8ae3-aab78a8c6ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857045423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3857045423
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2251787377
Short name T512
Test name
Test status
Simulation time 46077603 ps
CPU time 1.55 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 218532 kb
Host smart-1aec0cf7-f40a-457c-a270-df1337995ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251787377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2251787377
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.182706318
Short name T226
Test name
Test status
Simulation time 29023453 ps
CPU time 1.29 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:25 PM PDT 24
Peak memory 218800 kb
Host smart-9cd1d1e7-d1f8-4102-8726-b0dfcec16d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182706318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.182706318
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.876890218
Short name T679
Test name
Test status
Simulation time 17600899 ps
CPU time 0.97 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:24 PM PDT 24
Peak memory 206768 kb
Host smart-d630ee95-4d73-47ea-85e5-ac8cdcea7380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876890218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.876890218
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3089165639
Short name T189
Test name
Test status
Simulation time 19597771 ps
CPU time 0.89 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:27 PM PDT 24
Peak memory 216740 kb
Host smart-c2a6431d-9e57-4d8f-9b5a-bdcf34a7b463
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089165639 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3089165639
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3722685324
Short name T454
Test name
Test status
Simulation time 39768805 ps
CPU time 1.1 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:28 PM PDT 24
Peak memory 218760 kb
Host smart-da4f6a39-ac4d-4b46-86fc-f244d9578b76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722685324 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3722685324
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3299854988
Short name T225
Test name
Test status
Simulation time 33309860 ps
CPU time 0.87 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:27 PM PDT 24
Peak memory 218700 kb
Host smart-9994e19b-386b-4f89-aab9-7523a9b6c60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299854988 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3299854988
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2527059641
Short name T757
Test name
Test status
Simulation time 52307730 ps
CPU time 1.24 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:28 PM PDT 24
Peak memory 217000 kb
Host smart-d92f95c0-4916-4453-b809-d7cc2be80326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527059641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2527059641
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1487169848
Short name T684
Test name
Test status
Simulation time 23116473 ps
CPU time 1.18 seconds
Started Aug 10 07:22:27 PM PDT 24
Finished Aug 10 07:22:28 PM PDT 24
Peak memory 224160 kb
Host smart-eec71c8e-7e9f-45de-8a71-9364f195134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487169848 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1487169848
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.699473139
Short name T616
Test name
Test status
Simulation time 27111732 ps
CPU time 0.96 seconds
Started Aug 10 07:22:22 PM PDT 24
Finished Aug 10 07:22:23 PM PDT 24
Peak memory 207080 kb
Host smart-06db932a-392f-41c4-aae2-0adda8bcf3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699473139 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.699473139
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.90101839
Short name T758
Test name
Test status
Simulation time 469066423 ps
CPU time 5.13 seconds
Started Aug 10 07:22:23 PM PDT 24
Finished Aug 10 07:22:28 PM PDT 24
Peak memory 215332 kb
Host smart-34b38027-2187-49bf-9fb8-26304dd64a0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90101839 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.90101839
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.391729485
Short name T471
Test name
Test status
Simulation time 456361713692 ps
CPU time 2214 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:59:20 PM PDT 24
Peak memory 231096 kb
Host smart-17c432ff-c0ac-44e5-90ae-bc50ae8d34c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391729485 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.391729485
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1716568325
Short name T870
Test name
Test status
Simulation time 114221553 ps
CPU time 1.5 seconds
Started Aug 10 07:24:24 PM PDT 24
Finished Aug 10 07:24:25 PM PDT 24
Peak memory 218876 kb
Host smart-05e33929-e505-4441-bf57-2a9e01ec1535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716568325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1716568325
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.562230121
Short name T508
Test name
Test status
Simulation time 64660337 ps
CPU time 1.72 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 218820 kb
Host smart-4aa86716-78de-4345-a4da-db15d3fea602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562230121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.562230121
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.725884431
Short name T846
Test name
Test status
Simulation time 57313670 ps
CPU time 1.5 seconds
Started Aug 10 07:24:20 PM PDT 24
Finished Aug 10 07:24:21 PM PDT 24
Peak memory 217456 kb
Host smart-37e8715a-88c0-48e7-b639-1ce22a0169f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725884431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.725884431
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.803279600
Short name T623
Test name
Test status
Simulation time 61150000 ps
CPU time 2.24 seconds
Started Aug 10 07:24:19 PM PDT 24
Finished Aug 10 07:24:22 PM PDT 24
Peak memory 219652 kb
Host smart-e6444d20-8a56-4772-9585-169c0b294ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803279600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.803279600
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1755903331
Short name T388
Test name
Test status
Simulation time 143767490 ps
CPU time 1.18 seconds
Started Aug 10 07:24:24 PM PDT 24
Finished Aug 10 07:24:25 PM PDT 24
Peak memory 218508 kb
Host smart-da5a006f-6b3e-4c85-976c-5145ea469eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755903331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1755903331
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1827722636
Short name T889
Test name
Test status
Simulation time 69480974 ps
CPU time 1.32 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 219884 kb
Host smart-c26f4382-b397-4455-a8ac-038cadd18c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827722636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1827722636
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2420979537
Short name T957
Test name
Test status
Simulation time 35618184 ps
CPU time 1.32 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 217220 kb
Host smart-9adf1b8d-3ab4-4a4d-a5eb-1667ada6a802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420979537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2420979537
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.307354933
Short name T435
Test name
Test status
Simulation time 39885774 ps
CPU time 1.66 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 218960 kb
Host smart-08eded4d-9157-4d1d-a11c-6af03e70c54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307354933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.307354933
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2025834899
Short name T392
Test name
Test status
Simulation time 68831924 ps
CPU time 1.27 seconds
Started Aug 10 07:24:30 PM PDT 24
Finished Aug 10 07:24:31 PM PDT 24
Peak memory 217252 kb
Host smart-72d779f7-c980-490c-8bfa-062e70ba8211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025834899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2025834899
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2374572259
Short name T341
Test name
Test status
Simulation time 91032185 ps
CPU time 1.56 seconds
Started Aug 10 07:24:30 PM PDT 24
Finished Aug 10 07:24:32 PM PDT 24
Peak memory 218972 kb
Host smart-dd093abb-3ca2-49b6-af46-e3ff0b58fca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374572259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2374572259
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.3976154087
Short name T449
Test name
Test status
Simulation time 44160235 ps
CPU time 0.94 seconds
Started Aug 10 07:22:35 PM PDT 24
Finished Aug 10 07:22:36 PM PDT 24
Peak memory 215180 kb
Host smart-6fb2fe31-fb69-4869-a8ea-d2c3f5b5c53a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976154087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3976154087
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3579487357
Short name T170
Test name
Test status
Simulation time 29480608 ps
CPU time 0.89 seconds
Started Aug 10 07:22:32 PM PDT 24
Finished Aug 10 07:22:33 PM PDT 24
Peak memory 216444 kb
Host smart-f8944f74-2a9a-4233-a623-629f33e36675
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579487357 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3579487357
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2366687213
Short name T15
Test name
Test status
Simulation time 112233927 ps
CPU time 1.13 seconds
Started Aug 10 07:22:36 PM PDT 24
Finished Aug 10 07:22:37 PM PDT 24
Peak memory 217100 kb
Host smart-6cc54799-7090-44cc-89ee-9474c8b24759
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366687213 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2366687213
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.683697282
Short name T164
Test name
Test status
Simulation time 20012419 ps
CPU time 1.25 seconds
Started Aug 10 07:22:22 PM PDT 24
Finished Aug 10 07:22:23 PM PDT 24
Peak memory 224156 kb
Host smart-51986871-6a6f-4d7e-8edb-facb10e4f2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683697282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.683697282
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3608850293
Short name T416
Test name
Test status
Simulation time 60461520 ps
CPU time 1.04 seconds
Started Aug 10 07:22:27 PM PDT 24
Finished Aug 10 07:22:28 PM PDT 24
Peak memory 217432 kb
Host smart-2b9844eb-e2e0-43cb-9cc4-e3c9ffb3eff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608850293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3608850293
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2806159151
Short name T59
Test name
Test status
Simulation time 22552905 ps
CPU time 1.2 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:27 PM PDT 24
Peak memory 224172 kb
Host smart-76ee7f0b-2225-442f-86d3-5e42d841578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806159151 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2806159151
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1488662139
Short name T761
Test name
Test status
Simulation time 51026134 ps
CPU time 0.88 seconds
Started Aug 10 07:22:26 PM PDT 24
Finished Aug 10 07:22:27 PM PDT 24
Peak memory 215296 kb
Host smart-395dc0af-aeeb-4797-a83c-4d2a3db24d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488662139 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1488662139
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1688018481
Short name T890
Test name
Test status
Simulation time 370283267 ps
CPU time 4.15 seconds
Started Aug 10 07:22:24 PM PDT 24
Finished Aug 10 07:22:28 PM PDT 24
Peak memory 215380 kb
Host smart-e5e4ce7e-a495-4562-80c0-fcda5a66388f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688018481 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1688018481
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3781320199
Short name T976
Test name
Test status
Simulation time 36159014302 ps
CPU time 438.22 seconds
Started Aug 10 07:22:25 PM PDT 24
Finished Aug 10 07:29:43 PM PDT 24
Peak memory 221412 kb
Host smart-7775fec3-b9c1-495c-b395-df31e57703ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781320199 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3781320199
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2174025199
Short name T485
Test name
Test status
Simulation time 48367283 ps
CPU time 1.79 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 218708 kb
Host smart-88f5b080-d27a-4d00-8ac2-5a034dc13632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174025199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2174025199
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2025833353
Short name T938
Test name
Test status
Simulation time 55503845 ps
CPU time 1.25 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 219852 kb
Host smart-ada9ddfe-79ae-4d8f-8b6f-8b12f9f09d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025833353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2025833353
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1557151467
Short name T102
Test name
Test status
Simulation time 46245646 ps
CPU time 1.32 seconds
Started Aug 10 07:24:28 PM PDT 24
Finished Aug 10 07:24:29 PM PDT 24
Peak memory 217332 kb
Host smart-ce5f1760-606e-43d7-8b27-85ffb09063c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557151467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1557151467
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.122727610
Short name T669
Test name
Test status
Simulation time 38560663 ps
CPU time 1.36 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:32 PM PDT 24
Peak memory 217336 kb
Host smart-76804c15-d5af-43ca-b744-d3da4776dea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122727610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.122727610
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.4261958005
Short name T790
Test name
Test status
Simulation time 28723220 ps
CPU time 1.24 seconds
Started Aug 10 07:24:29 PM PDT 24
Finished Aug 10 07:24:30 PM PDT 24
Peak memory 218520 kb
Host smart-bf3923f5-44a3-4410-87ca-49df793a7edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261958005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.4261958005
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2918833966
Short name T560
Test name
Test status
Simulation time 69563629 ps
CPU time 1.11 seconds
Started Aug 10 07:24:27 PM PDT 24
Finished Aug 10 07:24:28 PM PDT 24
Peak memory 217276 kb
Host smart-47627221-dcdc-4490-8a75-9407296763f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918833966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2918833966
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1189159774
Short name T712
Test name
Test status
Simulation time 71052842 ps
CPU time 1.43 seconds
Started Aug 10 07:24:30 PM PDT 24
Finished Aug 10 07:24:32 PM PDT 24
Peak memory 217396 kb
Host smart-bfa14972-dbd4-4e76-aea1-695f4a9fc3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189159774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1189159774
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2038734586
Short name T426
Test name
Test status
Simulation time 59216390 ps
CPU time 1.33 seconds
Started Aug 10 07:24:29 PM PDT 24
Finished Aug 10 07:24:30 PM PDT 24
Peak memory 218600 kb
Host smart-1dd9927e-4666-4708-ab21-9b7a0fecdf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038734586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2038734586
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.149846590
Short name T48
Test name
Test status
Simulation time 48432074 ps
CPU time 1.13 seconds
Started Aug 10 07:24:30 PM PDT 24
Finished Aug 10 07:24:31 PM PDT 24
Peak memory 217344 kb
Host smart-ecc952bf-21c2-4bca-a8fa-c647fdd460e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149846590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.149846590
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2100143915
Short name T336
Test name
Test status
Simulation time 127263731 ps
CPU time 1.48 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:32 PM PDT 24
Peak memory 218560 kb
Host smart-3880c921-c5be-42c0-8c6d-b2767aeba4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100143915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2100143915
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3392479271
Short name T571
Test name
Test status
Simulation time 157474178 ps
CPU time 1.14 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 07:22:35 PM PDT 24
Peak memory 215576 kb
Host smart-4731f883-8411-4771-8a40-1de5cb1fe217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392479271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3392479271
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1703886261
Short name T534
Test name
Test status
Simulation time 17928334 ps
CPU time 0.9 seconds
Started Aug 10 07:22:43 PM PDT 24
Finished Aug 10 07:22:44 PM PDT 24
Peak memory 206844 kb
Host smart-5ee0e681-76d0-472b-bfb7-a1a2b0edb43d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703886261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1703886261
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3477897175
Short name T155
Test name
Test status
Simulation time 13905174 ps
CPU time 0.93 seconds
Started Aug 10 07:22:33 PM PDT 24
Finished Aug 10 07:22:34 PM PDT 24
Peak memory 215524 kb
Host smart-7df9bbe0-b96f-4896-aa47-f53ba9c2144d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477897175 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3477897175
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2651504600
Short name T407
Test name
Test status
Simulation time 56201291 ps
CPU time 1.07 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 07:22:36 PM PDT 24
Peak memory 219556 kb
Host smart-24e7c625-c308-4643-9fb4-c2ec477313a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651504600 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2651504600
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.883983417
Short name T817
Test name
Test status
Simulation time 32515034 ps
CPU time 0.99 seconds
Started Aug 10 07:22:35 PM PDT 24
Finished Aug 10 07:22:36 PM PDT 24
Peak memory 224036 kb
Host smart-485390be-166a-4a85-9219-54f77a613af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883983417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.883983417
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.42797408
Short name T885
Test name
Test status
Simulation time 166496029 ps
CPU time 1.11 seconds
Started Aug 10 07:22:35 PM PDT 24
Finished Aug 10 07:22:37 PM PDT 24
Peak memory 217412 kb
Host smart-65c756cf-105b-461c-b33a-3ed437591adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42797408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.42797408
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3701519700
Short name T385
Test name
Test status
Simulation time 27884049 ps
CPU time 1.04 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 07:22:35 PM PDT 24
Peak memory 215468 kb
Host smart-db6b82b7-400b-4dd1-8e6b-d4df5abc9aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701519700 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3701519700
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3337244433
Short name T569
Test name
Test status
Simulation time 33900056 ps
CPU time 1 seconds
Started Aug 10 07:22:33 PM PDT 24
Finished Aug 10 07:22:34 PM PDT 24
Peak memory 215300 kb
Host smart-b515a81d-f4a1-4b76-b7bc-cf7c165986aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337244433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3337244433
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3310250968
Short name T252
Test name
Test status
Simulation time 267604559 ps
CPU time 5.19 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 07:22:39 PM PDT 24
Peak memory 217252 kb
Host smart-86456bef-8812-4561-b25f-b83edeb480dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310250968 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3310250968
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2696274133
Short name T981
Test name
Test status
Simulation time 297232998872 ps
CPU time 436.64 seconds
Started Aug 10 07:22:44 PM PDT 24
Finished Aug 10 07:30:01 PM PDT 24
Peak memory 218816 kb
Host smart-8dff1722-56e3-4842-89eb-5ee78351a2e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696274133 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2696274133
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.4193134282
Short name T797
Test name
Test status
Simulation time 79532062 ps
CPU time 1.28 seconds
Started Aug 10 07:24:34 PM PDT 24
Finished Aug 10 07:24:36 PM PDT 24
Peak memory 218832 kb
Host smart-05abe46b-4809-4d2a-850a-9732ba61c4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193134282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.4193134282
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.659345845
Short name T810
Test name
Test status
Simulation time 311028748 ps
CPU time 1.65 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 218988 kb
Host smart-5a5e3222-a1c1-431a-9bfb-b3d24cee905b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659345845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.659345845
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2305184937
Short name T763
Test name
Test status
Simulation time 36999973 ps
CPU time 1.36 seconds
Started Aug 10 07:24:30 PM PDT 24
Finished Aug 10 07:24:31 PM PDT 24
Peak memory 219576 kb
Host smart-052bba58-80d8-4883-9824-26a60b929a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305184937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2305184937
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.244208147
Short name T955
Test name
Test status
Simulation time 174208606 ps
CPU time 1.31 seconds
Started Aug 10 07:24:29 PM PDT 24
Finished Aug 10 07:24:30 PM PDT 24
Peak memory 219928 kb
Host smart-78bad9f9-ee3a-426e-91de-2d4fb8c1c08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244208147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.244208147
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1205483642
Short name T725
Test name
Test status
Simulation time 46848946 ps
CPU time 1.33 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 217428 kb
Host smart-17f3de86-47c9-46d8-ab58-5baf2a39dc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205483642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1205483642
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.133708964
Short name T40
Test name
Test status
Simulation time 83678992 ps
CPU time 1.35 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 218792 kb
Host smart-3084808a-7ab9-4175-85c1-f691338193c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133708964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.133708964
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.428074590
Short name T591
Test name
Test status
Simulation time 74525166 ps
CPU time 1.51 seconds
Started Aug 10 07:24:30 PM PDT 24
Finished Aug 10 07:24:31 PM PDT 24
Peak memory 219644 kb
Host smart-44ecdd0f-b8ef-48b0-8b31-3da97097d10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428074590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.428074590
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3829860357
Short name T509
Test name
Test status
Simulation time 38756240 ps
CPU time 1.47 seconds
Started Aug 10 07:24:34 PM PDT 24
Finished Aug 10 07:24:36 PM PDT 24
Peak memory 217556 kb
Host smart-433b0738-7918-42a0-bea5-2a4865e6c69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829860357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3829860357
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2492860269
Short name T451
Test name
Test status
Simulation time 58450164 ps
CPU time 1.18 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 217396 kb
Host smart-30a90a1e-4c75-4f24-8d45-60584c902dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492860269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2492860269
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2564066956
Short name T815
Test name
Test status
Simulation time 61324955 ps
CPU time 1.3 seconds
Started Aug 10 07:24:28 PM PDT 24
Finished Aug 10 07:24:30 PM PDT 24
Peak memory 219812 kb
Host smart-34e50c1d-6614-4d25-9fc1-a299c0fb0a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564066956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2564066956
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.4117679222
Short name T76
Test name
Test status
Simulation time 124899645 ps
CPU time 1.08 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 07:22:35 PM PDT 24
Peak memory 218476 kb
Host smart-8008722f-0781-40f8-a006-91544ba80003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117679222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.4117679222
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.301584171
Short name T256
Test name
Test status
Simulation time 61104285 ps
CPU time 0.92 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 07:22:35 PM PDT 24
Peak memory 215184 kb
Host smart-964ef71f-52db-465b-a010-4d697ac4ed49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301584171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.301584171
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.780006208
Short name T796
Test name
Test status
Simulation time 82039623 ps
CPU time 0.84 seconds
Started Aug 10 07:22:36 PM PDT 24
Finished Aug 10 07:22:37 PM PDT 24
Peak memory 216508 kb
Host smart-02d3cf13-f4ad-4de1-8939-e665ebdbfc7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780006208 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.780006208
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2739372005
Short name T930
Test name
Test status
Simulation time 49636730 ps
CPU time 1.54 seconds
Started Aug 10 07:22:33 PM PDT 24
Finished Aug 10 07:22:35 PM PDT 24
Peak memory 217184 kb
Host smart-1ebd04b4-8bc5-48fa-a6cc-af3384907a97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739372005 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2739372005
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1986380006
Short name T911
Test name
Test status
Simulation time 20061052 ps
CPU time 1.19 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 07:22:35 PM PDT 24
Peak memory 218824 kb
Host smart-a13dd8a1-b875-4ffe-8029-c2628e5d04e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986380006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1986380006
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2479180886
Short name T325
Test name
Test status
Simulation time 51575891 ps
CPU time 1.78 seconds
Started Aug 10 07:22:36 PM PDT 24
Finished Aug 10 07:22:38 PM PDT 24
Peak memory 220356 kb
Host smart-dec9dcfb-8c30-44b4-9a80-8d44fe7ef4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479180886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2479180886
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1419523841
Short name T589
Test name
Test status
Simulation time 42594301 ps
CPU time 0.96 seconds
Started Aug 10 07:22:35 PM PDT 24
Finished Aug 10 07:22:36 PM PDT 24
Peak memory 215496 kb
Host smart-521f50b7-8e60-4b24-8afc-72793bb30e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419523841 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1419523841
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.848968504
Short name T360
Test name
Test status
Simulation time 27804587 ps
CPU time 0.9 seconds
Started Aug 10 07:22:33 PM PDT 24
Finished Aug 10 07:22:34 PM PDT 24
Peak memory 215324 kb
Host smart-8f1aaa01-0634-4487-ba1f-e82180f96451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848968504 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.848968504
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2733106354
Short name T808
Test name
Test status
Simulation time 283127974 ps
CPU time 3.27 seconds
Started Aug 10 07:22:41 PM PDT 24
Finished Aug 10 07:22:44 PM PDT 24
Peak memory 215396 kb
Host smart-eadc4557-af16-42c2-ab65-7aa2a729ef17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733106354 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2733106354
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.754799762
Short name T769
Test name
Test status
Simulation time 31099837110 ps
CPU time 700.64 seconds
Started Aug 10 07:22:44 PM PDT 24
Finished Aug 10 07:34:25 PM PDT 24
Peak memory 223624 kb
Host smart-3584f780-2388-46fb-ad2c-30778aa5517e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754799762 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.754799762
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.523297551
Short name T597
Test name
Test status
Simulation time 26463044 ps
CPU time 1.26 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:32 PM PDT 24
Peak memory 218480 kb
Host smart-9dea1814-0f84-4b22-a579-74452eb04476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523297551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.523297551
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.758758154
Short name T507
Test name
Test status
Simulation time 75068041 ps
CPU time 1.14 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:32 PM PDT 24
Peak memory 217460 kb
Host smart-306688ce-4530-4571-842a-08258d3d2642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758758154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.758758154
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2977048436
Short name T750
Test name
Test status
Simulation time 86236436 ps
CPU time 1.04 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:32 PM PDT 24
Peak memory 219372 kb
Host smart-66de9c10-e8d8-4764-9f3e-b91c8d1e1190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977048436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2977048436
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2262816710
Short name T583
Test name
Test status
Simulation time 92675206 ps
CPU time 1.16 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 218808 kb
Host smart-27fd0f60-d3a8-4ceb-9d8f-9dbbd7be32df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262816710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2262816710
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2856966422
Short name T828
Test name
Test status
Simulation time 50979590 ps
CPU time 1.24 seconds
Started Aug 10 07:24:28 PM PDT 24
Finished Aug 10 07:24:29 PM PDT 24
Peak memory 215316 kb
Host smart-49c5f0dc-d70a-4b98-bcd9-69ea86688a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856966422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2856966422
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3373330184
Short name T779
Test name
Test status
Simulation time 60350270 ps
CPU time 1.45 seconds
Started Aug 10 07:24:35 PM PDT 24
Finished Aug 10 07:24:36 PM PDT 24
Peak memory 218876 kb
Host smart-807364bf-e8f1-4ea3-a840-4ec4046eeea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373330184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3373330184
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.536871735
Short name T641
Test name
Test status
Simulation time 33838544 ps
CPU time 1.45 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 218584 kb
Host smart-c658cf87-1d5b-4241-ac4d-5eef8698909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536871735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.536871735
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1077501466
Short name T844
Test name
Test status
Simulation time 50942545 ps
CPU time 1.22 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 217580 kb
Host smart-37a1b342-603c-462d-9952-f1711898ecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077501466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1077501466
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2990024238
Short name T421
Test name
Test status
Simulation time 174477544 ps
CPU time 1.19 seconds
Started Aug 10 07:24:30 PM PDT 24
Finished Aug 10 07:24:32 PM PDT 24
Peak memory 217376 kb
Host smart-e6301924-f82f-470d-8c41-66744dc836f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990024238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2990024238
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2602233974
Short name T663
Test name
Test status
Simulation time 37693037 ps
CPU time 1.3 seconds
Started Aug 10 07:22:33 PM PDT 24
Finished Aug 10 07:22:34 PM PDT 24
Peak memory 219668 kb
Host smart-0c372b76-b23b-4f0e-9b0a-08ec3500ee71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602233974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2602233974
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2095386420
Short name T382
Test name
Test status
Simulation time 22416758 ps
CPU time 0.91 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 07:22:35 PM PDT 24
Peak memory 215132 kb
Host smart-da1f35d7-4e99-40d7-b6d8-0ba66db0934e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095386420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2095386420
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3566971840
Short name T986
Test name
Test status
Simulation time 22908266 ps
CPU time 0.91 seconds
Started Aug 10 07:22:43 PM PDT 24
Finished Aug 10 07:22:44 PM PDT 24
Peak memory 216796 kb
Host smart-3173d070-efa2-467b-95e7-262179b7dc7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566971840 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3566971840
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.2913509628
Short name T908
Test name
Test status
Simulation time 24011114 ps
CPU time 1.2 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 07:22:36 PM PDT 24
Peak memory 224196 kb
Host smart-0da1ef0a-423f-4e47-ba60-5f22e1f91ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913509628 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2913509628
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3825492217
Short name T330
Test name
Test status
Simulation time 43375887 ps
CPU time 1.47 seconds
Started Aug 10 07:22:40 PM PDT 24
Finished Aug 10 07:22:42 PM PDT 24
Peak memory 218380 kb
Host smart-444c2726-f7a8-4412-a369-d48926ae841a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825492217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3825492217
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3257070870
Short name T395
Test name
Test status
Simulation time 26731469 ps
CPU time 0.97 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 07:22:35 PM PDT 24
Peak memory 215496 kb
Host smart-5564a39c-fcc5-43f1-a174-e251db6485e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257070870 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3257070870
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.340998905
Short name T764
Test name
Test status
Simulation time 26610933 ps
CPU time 1.02 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 07:22:35 PM PDT 24
Peak memory 215216 kb
Host smart-c6f7753c-92c6-46e6-b636-a9b0ae0f405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340998905 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.340998905
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3305312259
Short name T588
Test name
Test status
Simulation time 192514012 ps
CPU time 1.53 seconds
Started Aug 10 07:22:36 PM PDT 24
Finished Aug 10 07:22:38 PM PDT 24
Peak memory 217416 kb
Host smart-b9599a75-60b8-48ac-95be-29ad9c02f007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305312259 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3305312259
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3583450188
Short name T243
Test name
Test status
Simulation time 271528314914 ps
CPU time 1456.94 seconds
Started Aug 10 07:22:33 PM PDT 24
Finished Aug 10 07:46:50 PM PDT 24
Peak memory 223068 kb
Host smart-3955772e-7ceb-48f0-8741-6ad847fd50c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583450188 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3583450188
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.22690735
Short name T580
Test name
Test status
Simulation time 63504559 ps
CPU time 1.4 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 217240 kb
Host smart-2ddaebc2-e330-4414-82f6-6310d0538acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22690735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.22690735
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3328986477
Short name T433
Test name
Test status
Simulation time 33383882 ps
CPU time 1.47 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 217532 kb
Host smart-7c30d3c8-1ee2-4f39-9bed-635603580e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328986477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3328986477
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.791466282
Short name T698
Test name
Test status
Simulation time 90432672 ps
CPU time 3.18 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 219008 kb
Host smart-673cc7c5-5b69-42cd-b24e-0a30e5980eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791466282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.791466282
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2367529230
Short name T674
Test name
Test status
Simulation time 62557475 ps
CPU time 1.37 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 219920 kb
Host smart-87beb78a-d860-46ec-a046-36c3e11006c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367529230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2367529230
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3772297261
Short name T43
Test name
Test status
Simulation time 104199567 ps
CPU time 1.27 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 218496 kb
Host smart-cd86152d-0516-4ed1-8ec3-f846620f4831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772297261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3772297261
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3869271864
Short name T888
Test name
Test status
Simulation time 64856426 ps
CPU time 1.45 seconds
Started Aug 10 07:24:34 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 220116 kb
Host smart-800dc23a-4886-4592-b3d1-7adf5e615cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869271864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3869271864
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2177034383
Short name T568
Test name
Test status
Simulation time 39954662 ps
CPU time 1.47 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 217456 kb
Host smart-412155aa-7ce8-4a85-9add-c91335351257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177034383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2177034383
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.983874380
Short name T441
Test name
Test status
Simulation time 73363158 ps
CPU time 1.1 seconds
Started Aug 10 07:24:35 PM PDT 24
Finished Aug 10 07:24:36 PM PDT 24
Peak memory 219520 kb
Host smart-602b57fe-2e25-4a72-b4da-3776ee76aeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983874380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.983874380
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.792379811
Short name T467
Test name
Test status
Simulation time 40853375 ps
CPU time 1.39 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 218436 kb
Host smart-d46423f6-1cb5-4264-b421-08c6b345ec1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792379811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.792379811
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3866983525
Short name T668
Test name
Test status
Simulation time 78548502 ps
CPU time 1.11 seconds
Started Aug 10 07:22:43 PM PDT 24
Finished Aug 10 07:22:45 PM PDT 24
Peak memory 218288 kb
Host smart-19fb105a-f7c4-4d4e-a186-5ac17b8ceb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866983525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3866983525
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3903093069
Short name T834
Test name
Test status
Simulation time 51021409 ps
CPU time 0.96 seconds
Started Aug 10 07:22:35 PM PDT 24
Finished Aug 10 07:22:36 PM PDT 24
Peak memory 215168 kb
Host smart-7e8c3a55-0f4e-44ff-b503-940de3f95a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903093069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3903093069
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.262024412
Short name T154
Test name
Test status
Simulation time 10379210 ps
CPU time 0.88 seconds
Started Aug 10 07:22:43 PM PDT 24
Finished Aug 10 07:22:44 PM PDT 24
Peak memory 215352 kb
Host smart-8d7e5282-2cbb-41bd-b709-4cc417323af1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262024412 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.262024412
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.447633900
Short name T247
Test name
Test status
Simulation time 23487342 ps
CPU time 0.96 seconds
Started Aug 10 07:22:34 PM PDT 24
Finished Aug 10 07:22:35 PM PDT 24
Peak memory 218656 kb
Host smart-aa75e210-b828-49f2-9372-d48171970834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447633900 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.447633900
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3268028319
Short name T637
Test name
Test status
Simulation time 66966758 ps
CPU time 2.01 seconds
Started Aug 10 07:22:36 PM PDT 24
Finished Aug 10 07:22:38 PM PDT 24
Peak memory 219980 kb
Host smart-52213ea6-19a6-4972-bc0f-74372de26144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268028319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3268028319
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1270703989
Short name T748
Test name
Test status
Simulation time 42782465 ps
CPU time 0.9 seconds
Started Aug 10 07:22:33 PM PDT 24
Finished Aug 10 07:22:34 PM PDT 24
Peak memory 215384 kb
Host smart-4001f39c-1947-4c2e-a575-e7d6eb0596ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270703989 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1270703989
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.4011482667
Short name T406
Test name
Test status
Simulation time 26946601 ps
CPU time 0.95 seconds
Started Aug 10 07:22:35 PM PDT 24
Finished Aug 10 07:22:36 PM PDT 24
Peak memory 215308 kb
Host smart-2e361d8e-ad2a-4483-a83a-109928d5aadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011482667 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.4011482667
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1182189882
Short name T807
Test name
Test status
Simulation time 91266886 ps
CPU time 2.29 seconds
Started Aug 10 07:22:35 PM PDT 24
Finished Aug 10 07:22:38 PM PDT 24
Peak memory 219944 kb
Host smart-0cecd5ec-7b67-48ab-9313-c0f0607b5373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182189882 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1182189882
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.4038518384
Short name T457
Test name
Test status
Simulation time 50115201890 ps
CPU time 305.3 seconds
Started Aug 10 07:22:35 PM PDT 24
Finished Aug 10 07:27:41 PM PDT 24
Peak memory 218344 kb
Host smart-d48aadef-25e6-45bb-8864-1dc11ce056d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038518384 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.4038518384
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2807931799
Short name T99
Test name
Test status
Simulation time 45200580 ps
CPU time 1.18 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 218744 kb
Host smart-c78f909c-17d7-49e3-a729-6209e0d3cf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807931799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2807931799
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2012920200
Short name T683
Test name
Test status
Simulation time 28454458 ps
CPU time 1.22 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 218804 kb
Host smart-71c014d9-cb04-4225-a0a3-b2c11b69f817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012920200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2012920200
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.922819499
Short name T532
Test name
Test status
Simulation time 41715486 ps
CPU time 1.37 seconds
Started Aug 10 07:24:29 PM PDT 24
Finished Aug 10 07:24:30 PM PDT 24
Peak memory 217452 kb
Host smart-7e70e4a2-4d8e-4ab8-a403-3fda71f369e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922819499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.922819499
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3507491430
Short name T922
Test name
Test status
Simulation time 81827960 ps
CPU time 1.41 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 218832 kb
Host smart-98855436-a99c-4feb-992f-677c80fbacca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507491430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3507491430
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3124779033
Short name T592
Test name
Test status
Simulation time 118059089 ps
CPU time 1.44 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 218988 kb
Host smart-04408351-60a4-47a9-9b1b-47887898cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124779033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3124779033
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1406494733
Short name T713
Test name
Test status
Simulation time 75093668 ps
CPU time 2.62 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:36 PM PDT 24
Peak memory 219884 kb
Host smart-0ed25d8a-5701-4524-8b7e-f1154eb910c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406494733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1406494733
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3545449359
Short name T473
Test name
Test status
Simulation time 129798990 ps
CPU time 2.76 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 220324 kb
Host smart-1c208fb1-9319-4038-a157-5e3e6de38669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545449359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3545449359
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3903203587
Short name T436
Test name
Test status
Simulation time 64087614 ps
CPU time 1.33 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 218600 kb
Host smart-afccf560-6891-47be-b2e6-4a6407e67568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903203587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3903203587
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1082430067
Short name T49
Test name
Test status
Simulation time 59609464 ps
CPU time 1.68 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 218868 kb
Host smart-0ccf27f0-4e75-45c6-9793-f73d64b4ebda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082430067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1082430067
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3876359597
Short name T528
Test name
Test status
Simulation time 50660500 ps
CPU time 1.2 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 217316 kb
Host smart-c4d35b2b-7121-4cc0-af01-df0342eed230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876359597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3876359597
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3928849222
Short name T675
Test name
Test status
Simulation time 48431817 ps
CPU time 1.1 seconds
Started Aug 10 07:22:37 PM PDT 24
Finished Aug 10 07:22:38 PM PDT 24
Peak memory 218340 kb
Host smart-5fd82f6a-dd6d-40f7-9c93-db520e541177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928849222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3928849222
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2756323354
Short name T487
Test name
Test status
Simulation time 15058793 ps
CPU time 0.93 seconds
Started Aug 10 07:22:43 PM PDT 24
Finished Aug 10 07:22:44 PM PDT 24
Peak memory 215224 kb
Host smart-c6af7321-0885-4b63-b5d7-f2bf184cc05d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756323354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2756323354
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.290719603
Short name T841
Test name
Test status
Simulation time 18696823 ps
CPU time 0.84 seconds
Started Aug 10 07:22:32 PM PDT 24
Finished Aug 10 07:22:33 PM PDT 24
Peak memory 218040 kb
Host smart-783fe3e0-3662-4415-b1aa-ebae70d94bad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290719603 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.290719603
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3776649000
Short name T743
Test name
Test status
Simulation time 44771841 ps
CPU time 1.44 seconds
Started Aug 10 07:22:36 PM PDT 24
Finished Aug 10 07:22:38 PM PDT 24
Peak memory 217064 kb
Host smart-a8089139-dba0-4d7f-abed-1e765c60969b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776649000 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3776649000
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1120778524
Short name T653
Test name
Test status
Simulation time 40729951 ps
CPU time 0.95 seconds
Started Aug 10 07:22:37 PM PDT 24
Finished Aug 10 07:22:38 PM PDT 24
Peak memory 218704 kb
Host smart-e654114a-46d1-4092-b891-11ff7c26ab35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120778524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1120778524
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3572809506
Short name T455
Test name
Test status
Simulation time 36525481 ps
CPU time 1.69 seconds
Started Aug 10 07:22:44 PM PDT 24
Finished Aug 10 07:22:46 PM PDT 24
Peak memory 218532 kb
Host smart-80994672-0776-4961-b1bc-eaea66bfe6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572809506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3572809506
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1526772411
Short name T553
Test name
Test status
Simulation time 23267368 ps
CPU time 1.2 seconds
Started Aug 10 07:22:35 PM PDT 24
Finished Aug 10 07:22:36 PM PDT 24
Peak memory 224120 kb
Host smart-464005d0-0cac-4fb5-933d-9b331d086b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526772411 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1526772411
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.382250480
Short name T70
Test name
Test status
Simulation time 27637616 ps
CPU time 0.95 seconds
Started Aug 10 07:22:35 PM PDT 24
Finished Aug 10 07:22:36 PM PDT 24
Peak memory 215296 kb
Host smart-33505395-d8e4-4ff7-95cc-d209eb3c6510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382250480 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.382250480
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.4066736720
Short name T365
Test name
Test status
Simulation time 79356958 ps
CPU time 1.94 seconds
Started Aug 10 07:22:45 PM PDT 24
Finished Aug 10 07:22:47 PM PDT 24
Peak memory 217204 kb
Host smart-ce65a4ec-1ca8-483a-abab-8467f8860d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066736720 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.4066736720
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/280.edn_genbits.2915001202
Short name T320
Test name
Test status
Simulation time 35962462 ps
CPU time 1.3 seconds
Started Aug 10 07:24:34 PM PDT 24
Finished Aug 10 07:24:36 PM PDT 24
Peak memory 218604 kb
Host smart-05b5f4d0-6b21-4587-91d0-281235985659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915001202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2915001202
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1102240708
Short name T445
Test name
Test status
Simulation time 100967083 ps
CPU time 1.44 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 218920 kb
Host smart-435a22fc-63e4-4c0e-a8eb-d93e7e4320d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102240708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1102240708
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.697767843
Short name T460
Test name
Test status
Simulation time 139456187 ps
CPU time 2.89 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 220112 kb
Host smart-6107b63c-3ced-4e27-9386-d67bfd5a1fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697767843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.697767843
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1825352497
Short name T661
Test name
Test status
Simulation time 48417316 ps
CPU time 1.27 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 218452 kb
Host smart-1e1a8871-3a63-4da7-b968-87460616f161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825352497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1825352497
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1069395692
Short name T829
Test name
Test status
Simulation time 42344698 ps
CPU time 1.29 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 218944 kb
Host smart-1b0f9da8-8305-4272-9acf-3e12d10c7111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069395692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1069395692
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1100103137
Short name T953
Test name
Test status
Simulation time 174160428 ps
CPU time 1.48 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 218960 kb
Host smart-ec95c28c-d8a6-4dd9-9a8e-c1694ff68265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100103137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1100103137
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1619352025
Short name T390
Test name
Test status
Simulation time 50007995 ps
CPU time 1.84 seconds
Started Aug 10 07:24:31 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 218616 kb
Host smart-9175ba31-fef8-4fc6-aecb-014c3e9e0254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619352025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1619352025
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2543300265
Short name T585
Test name
Test status
Simulation time 175711189 ps
CPU time 1.29 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 219008 kb
Host smart-84749c6a-fbfc-429b-a5f0-6e61c0d84360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543300265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2543300265
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2964372936
Short name T23
Test name
Test status
Simulation time 60252342 ps
CPU time 1.77 seconds
Started Aug 10 07:24:34 PM PDT 24
Finished Aug 10 07:24:36 PM PDT 24
Peak memory 219980 kb
Host smart-cbc2acf2-0bcd-41d2-8398-cd9d853067d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964372936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2964372936
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2578011713
Short name T496
Test name
Test status
Simulation time 64717437 ps
CPU time 1.25 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:47 PM PDT 24
Peak memory 219588 kb
Host smart-de2e9c40-cace-447e-955b-3e1439c59b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578011713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2578011713
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.990870044
Short name T410
Test name
Test status
Simulation time 16504878 ps
CPU time 0.88 seconds
Started Aug 10 07:22:45 PM PDT 24
Finished Aug 10 07:22:46 PM PDT 24
Peak memory 206772 kb
Host smart-a085a78f-6143-4daf-9a56-5f9625ecbbe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990870044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.990870044
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3371868561
Short name T566
Test name
Test status
Simulation time 41807969 ps
CPU time 0.88 seconds
Started Aug 10 07:22:48 PM PDT 24
Finished Aug 10 07:22:49 PM PDT 24
Peak memory 215392 kb
Host smart-9aa39271-4cac-421d-abd3-e7f005e3ee88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371868561 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3371868561
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.4074409876
Short name T567
Test name
Test status
Simulation time 117371784 ps
CPU time 1.12 seconds
Started Aug 10 07:22:56 PM PDT 24
Finished Aug 10 07:22:58 PM PDT 24
Peak memory 218324 kb
Host smart-6e99f86c-b3ab-40cb-b09a-c6b00393ed43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074409876 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.4074409876
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1631299620
Short name T665
Test name
Test status
Simulation time 23473759 ps
CPU time 1.2 seconds
Started Aug 10 07:22:44 PM PDT 24
Finished Aug 10 07:22:45 PM PDT 24
Peak memory 224148 kb
Host smart-e0b6cef8-16ed-4969-b6c8-adf0eb8afd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631299620 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1631299620
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3327014444
Short name T558
Test name
Test status
Simulation time 77357984 ps
CPU time 1.49 seconds
Started Aug 10 07:22:41 PM PDT 24
Finished Aug 10 07:22:43 PM PDT 24
Peak memory 218684 kb
Host smart-8098e366-3040-45e8-b94d-9d8c5691d555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327014444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3327014444
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2343488677
Short name T443
Test name
Test status
Simulation time 28392515 ps
CPU time 0.97 seconds
Started Aug 10 07:22:48 PM PDT 24
Finished Aug 10 07:22:49 PM PDT 24
Peak memory 215468 kb
Host smart-2ff9128c-31e2-4245-838a-ecaa221b30cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343488677 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2343488677
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3991033385
Short name T966
Test name
Test status
Simulation time 73776261 ps
CPU time 0.93 seconds
Started Aug 10 07:22:36 PM PDT 24
Finished Aug 10 07:22:37 PM PDT 24
Peak memory 215316 kb
Host smart-27794ff3-b983-4c4a-8da7-4889442563f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991033385 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3991033385
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.73573264
Short name T760
Test name
Test status
Simulation time 1404066665 ps
CPU time 3.06 seconds
Started Aug 10 07:22:36 PM PDT 24
Finished Aug 10 07:22:39 PM PDT 24
Peak memory 217428 kb
Host smart-95c74990-4419-4fb9-925e-91cdaade9f79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73573264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.73573264
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.536189335
Short name T912
Test name
Test status
Simulation time 101391034382 ps
CPU time 393.81 seconds
Started Aug 10 07:22:35 PM PDT 24
Finished Aug 10 07:29:09 PM PDT 24
Peak memory 218936 kb
Host smart-0c1f456d-f824-4188-aa30-9fa1ec2d5d73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536189335 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.536189335
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.925418063
Short name T931
Test name
Test status
Simulation time 65243683 ps
CPU time 1.27 seconds
Started Aug 10 07:24:32 PM PDT 24
Finished Aug 10 07:24:33 PM PDT 24
Peak memory 218852 kb
Host smart-d05beb77-e933-44ad-8f35-8e4c984bf2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925418063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.925418063
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.4122251953
Short name T92
Test name
Test status
Simulation time 136358305 ps
CPU time 1.44 seconds
Started Aug 10 07:24:34 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 219680 kb
Host smart-7c51e97a-d00a-42a4-acd6-310064fa1fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122251953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.4122251953
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3004357508
Short name T10
Test name
Test status
Simulation time 27016518 ps
CPU time 1.18 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 219952 kb
Host smart-4b84b5c4-fd30-4487-8c5f-9875fa965ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004357508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3004357508
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2765592001
Short name T741
Test name
Test status
Simulation time 76005612 ps
CPU time 1.15 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 217608 kb
Host smart-d8156e32-e615-4b99-a4b3-040f29a23ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765592001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2765592001
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.4182393026
Short name T577
Test name
Test status
Simulation time 40208646 ps
CPU time 1.55 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 218536 kb
Host smart-90b0e482-9f89-44bb-a987-85529a0539b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182393026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.4182393026
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2941434817
Short name T770
Test name
Test status
Simulation time 52672018 ps
CPU time 1.4 seconds
Started Aug 10 07:24:34 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 217556 kb
Host smart-c6d7434d-a1a3-4084-a8c1-5b7dea39d1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941434817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2941434817
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.4053180640
Short name T735
Test name
Test status
Simulation time 27972775 ps
CPU time 1.37 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 218544 kb
Host smart-4dcdd2a3-0fb0-4365-8468-4c0a5221e5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053180640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.4053180640
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.732688385
Short name T105
Test name
Test status
Simulation time 102987088 ps
CPU time 1.6 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 219116 kb
Host smart-142a4a40-38d7-4079-8a2e-96f3de213904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732688385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.732688385
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3361857884
Short name T625
Test name
Test status
Simulation time 131266292 ps
CPU time 1.53 seconds
Started Aug 10 07:24:34 PM PDT 24
Finished Aug 10 07:24:35 PM PDT 24
Peak memory 218440 kb
Host smart-411f1c91-cd4e-483c-8f4c-83a137ce2ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361857884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3361857884
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.157121122
Short name T177
Test name
Test status
Simulation time 22065397 ps
CPU time 1.18 seconds
Started Aug 10 07:21:45 PM PDT 24
Finished Aug 10 07:21:47 PM PDT 24
Peak memory 218656 kb
Host smart-4bbbc6bd-61cc-4d0c-a378-0970d17d70e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157121122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.157121122
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3100658376
Short name T899
Test name
Test status
Simulation time 35114345 ps
CPU time 0.97 seconds
Started Aug 10 07:21:44 PM PDT 24
Finished Aug 10 07:21:45 PM PDT 24
Peak memory 206868 kb
Host smart-abb68517-996b-4e34-ac51-8675b456dc64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100658376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3100658376
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1771330343
Short name T601
Test name
Test status
Simulation time 21114866 ps
CPU time 0.87 seconds
Started Aug 10 07:21:35 PM PDT 24
Finished Aug 10 07:21:36 PM PDT 24
Peak memory 216612 kb
Host smart-722287d1-6fcd-4778-9ef6-823cb6185df9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771330343 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1771330343
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3224378833
Short name T499
Test name
Test status
Simulation time 46386151 ps
CPU time 1.16 seconds
Started Aug 10 07:21:39 PM PDT 24
Finished Aug 10 07:21:41 PM PDT 24
Peak memory 218668 kb
Host smart-2411b679-695c-4e44-bf99-460b2bd74e51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224378833 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3224378833
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2755940087
Short name T368
Test name
Test status
Simulation time 23385056 ps
CPU time 0.96 seconds
Started Aug 10 07:21:45 PM PDT 24
Finished Aug 10 07:21:46 PM PDT 24
Peak memory 218796 kb
Host smart-583404ab-4688-4d37-be69-bb7ec317c8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755940087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2755940087
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3337183576
Short name T417
Test name
Test status
Simulation time 52276921 ps
CPU time 2.01 seconds
Started Aug 10 07:21:37 PM PDT 24
Finished Aug 10 07:21:39 PM PDT 24
Peak memory 217504 kb
Host smart-fce4d2b1-fa05-48ca-952d-d5e870e7db69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337183576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3337183576
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1850628699
Short name T510
Test name
Test status
Simulation time 96264595 ps
CPU time 0.95 seconds
Started Aug 10 07:21:37 PM PDT 24
Finished Aug 10 07:21:38 PM PDT 24
Peak memory 223908 kb
Host smart-3371f40e-da45-4886-a454-94db21db0e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850628699 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1850628699
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.312456343
Short name T961
Test name
Test status
Simulation time 26854396 ps
CPU time 0.92 seconds
Started Aug 10 07:21:38 PM PDT 24
Finished Aug 10 07:21:39 PM PDT 24
Peak memory 207072 kb
Host smart-013fd096-8426-4250-bd95-25cd10c8a8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312456343 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.312456343
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.297543218
Short name T18
Test name
Test status
Simulation time 895837313 ps
CPU time 7.69 seconds
Started Aug 10 07:21:36 PM PDT 24
Finished Aug 10 07:21:44 PM PDT 24
Peak memory 239756 kb
Host smart-b074384a-7f40-475c-9057-146a68505648
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297543218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.297543218
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.962140436
Short name T737
Test name
Test status
Simulation time 16290340 ps
CPU time 1.02 seconds
Started Aug 10 07:21:36 PM PDT 24
Finished Aug 10 07:21:37 PM PDT 24
Peak memory 215436 kb
Host smart-f53707c9-ab0f-4f20-a36f-1954f83a5590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962140436 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.962140436
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2698827076
Short name T344
Test name
Test status
Simulation time 54899268 ps
CPU time 1.11 seconds
Started Aug 10 07:21:36 PM PDT 24
Finished Aug 10 07:21:38 PM PDT 24
Peak memory 215320 kb
Host smart-575c88df-405e-4551-95c7-8219a9764d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698827076 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2698827076
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2405312297
Short name T951
Test name
Test status
Simulation time 132541956234 ps
CPU time 1489.23 seconds
Started Aug 10 07:21:37 PM PDT 24
Finished Aug 10 07:46:26 PM PDT 24
Peak memory 223772 kb
Host smart-50ee77bd-f123-45a9-8030-e534f06363ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405312297 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2405312297
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1429583172
Short name T348
Test name
Test status
Simulation time 29341454 ps
CPU time 1.31 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 220244 kb
Host smart-88ee57a2-d307-46e4-89ec-e2a9d76c09ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429583172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1429583172
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2799694775
Short name T64
Test name
Test status
Simulation time 19619639 ps
CPU time 1.02 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:47 PM PDT 24
Peak memory 206864 kb
Host smart-3582b1ba-65c3-4c7d-99a6-75809bf5376a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799694775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2799694775
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2497617619
Short name T216
Test name
Test status
Simulation time 10954497 ps
CPU time 0.91 seconds
Started Aug 10 07:22:56 PM PDT 24
Finished Aug 10 07:22:57 PM PDT 24
Peak memory 216484 kb
Host smart-b325f5b0-1384-402e-85b2-ecb7bdbd2f2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497617619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2497617619
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3539163257
Short name T949
Test name
Test status
Simulation time 25666949 ps
CPU time 1.13 seconds
Started Aug 10 07:22:44 PM PDT 24
Finished Aug 10 07:22:45 PM PDT 24
Peak memory 219808 kb
Host smart-351a0c7d-3f96-4a1f-acf8-f6fe508abe11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539163257 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3539163257
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.127834825
Short name T727
Test name
Test status
Simulation time 29690825 ps
CPU time 1.32 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:47 PM PDT 24
Peak memory 220088 kb
Host smart-f6d2490f-e48b-4c0a-95aa-b243b51d5aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127834825 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.127834825
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1390181067
Short name T519
Test name
Test status
Simulation time 53097071 ps
CPU time 1.32 seconds
Started Aug 10 07:22:48 PM PDT 24
Finished Aug 10 07:22:49 PM PDT 24
Peak memory 218764 kb
Host smart-6553eabd-06d3-416d-992e-0d876763e0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390181067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1390181067
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_smoke.3019663119
Short name T648
Test name
Test status
Simulation time 50101686 ps
CPU time 0.91 seconds
Started Aug 10 07:22:45 PM PDT 24
Finished Aug 10 07:22:46 PM PDT 24
Peak memory 215292 kb
Host smart-ed410387-8d33-4456-bdd8-8a5e14b9c871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019663119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3019663119
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2568663020
Short name T715
Test name
Test status
Simulation time 292026283 ps
CPU time 3.38 seconds
Started Aug 10 07:22:51 PM PDT 24
Finished Aug 10 07:22:54 PM PDT 24
Peak memory 219536 kb
Host smart-bb8e644b-1970-47b3-b4eb-409e2fb74826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568663020 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2568663020
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3477743342
Short name T399
Test name
Test status
Simulation time 178348031634 ps
CPU time 1983.72 seconds
Started Aug 10 07:22:55 PM PDT 24
Finished Aug 10 07:56:00 PM PDT 24
Peak memory 226292 kb
Host smart-5d1eed2e-9ba8-41a5-9817-e6fcd4b067a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477743342 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3477743342
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1812116879
Short name T117
Test name
Test status
Simulation time 27900933 ps
CPU time 1.48 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:49 PM PDT 24
Peak memory 220328 kb
Host smart-f63524e9-cbc0-493d-80d2-ef93dbd8f502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812116879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1812116879
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2209317718
Short name T408
Test name
Test status
Simulation time 57186394 ps
CPU time 0.89 seconds
Started Aug 10 07:22:50 PM PDT 24
Finished Aug 10 07:22:51 PM PDT 24
Peak memory 206848 kb
Host smart-1743b40a-d804-4c1a-89df-4d08a520bf0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209317718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2209317718
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.138200797
Short name T555
Test name
Test status
Simulation time 37838669 ps
CPU time 0.83 seconds
Started Aug 10 07:22:44 PM PDT 24
Finished Aug 10 07:22:45 PM PDT 24
Peak memory 216484 kb
Host smart-8260426a-1e4a-4bf9-8656-4edf96adc184
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138200797 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.138200797
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3869289360
Short name T402
Test name
Test status
Simulation time 141099994 ps
CPU time 1.21 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 219700 kb
Host smart-a6e17b86-6ed6-4374-b955-0a93d53c032d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869289360 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3869289360
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.339287956
Short name T898
Test name
Test status
Simulation time 29557580 ps
CPU time 1.33 seconds
Started Aug 10 07:22:50 PM PDT 24
Finished Aug 10 07:22:51 PM PDT 24
Peak memory 219884 kb
Host smart-f6b9ccdd-9bf5-40be-b531-11f7827f8407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339287956 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.339287956
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.676720583
Short name T857
Test name
Test status
Simulation time 64158117 ps
CPU time 1.45 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 218440 kb
Host smart-cd0b6279-081c-465e-8151-33a67c92f25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676720583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.676720583
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_smoke.2728263465
Short name T618
Test name
Test status
Simulation time 17427901 ps
CPU time 1.01 seconds
Started Aug 10 07:22:45 PM PDT 24
Finished Aug 10 07:22:46 PM PDT 24
Peak memory 215316 kb
Host smart-21d123ba-038f-4fdc-8715-c10b46543f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728263465 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2728263465
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2383971875
Short name T258
Test name
Test status
Simulation time 304015116 ps
CPU time 5.75 seconds
Started Aug 10 07:22:48 PM PDT 24
Finished Aug 10 07:22:54 PM PDT 24
Peak memory 215320 kb
Host smart-d7aa6caa-a127-4899-99e4-231e84f763b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383971875 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2383971875
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3334607680
Short name T642
Test name
Test status
Simulation time 16531182007 ps
CPU time 422.9 seconds
Started Aug 10 07:22:51 PM PDT 24
Finished Aug 10 07:29:54 PM PDT 24
Peak memory 218516 kb
Host smart-3ab9ccc3-8d58-4fd7-ac2f-0ec5e6932ffc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334607680 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3334607680
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.833825961
Short name T950
Test name
Test status
Simulation time 85626605 ps
CPU time 1.18 seconds
Started Aug 10 07:22:56 PM PDT 24
Finished Aug 10 07:22:58 PM PDT 24
Peak memory 220584 kb
Host smart-290e9d7d-9321-40d1-b9c8-28f3e2c9fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833825961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.833825961
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2275508627
Short name T965
Test name
Test status
Simulation time 25060125 ps
CPU time 1.08 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:47 PM PDT 24
Peak memory 207064 kb
Host smart-4329c8df-1ad9-4786-9701-85bdbe747a03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275508627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2275508627
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3232923561
Short name T535
Test name
Test status
Simulation time 16586030 ps
CPU time 0.86 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 216260 kb
Host smart-a5ba14a6-73f1-42b0-8780-bfde15055026
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232923561 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3232923561
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2724919874
Short name T393
Test name
Test status
Simulation time 78874640 ps
CPU time 1.08 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:49 PM PDT 24
Peak memory 219580 kb
Host smart-76682cb2-2105-4860-97be-13c2611f4b9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724919874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2724919874
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2623479302
Short name T991
Test name
Test status
Simulation time 24345508 ps
CPU time 0.93 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 218948 kb
Host smart-8ff4b486-357f-43f9-9120-17ad418d4038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623479302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2623479302
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.65730428
Short name T44
Test name
Test status
Simulation time 134295349 ps
CPU time 1.85 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 218896 kb
Host smart-8fd9a131-5419-4b0e-b967-790dfc5ad595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65730428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.65730428
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3796738656
Short name T895
Test name
Test status
Simulation time 26698239 ps
CPU time 1.05 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 215292 kb
Host smart-b1eda430-850f-4251-8b52-984209f263f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796738656 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3796738656
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2401762576
Short name T541
Test name
Test status
Simulation time 43427657 ps
CPU time 0.86 seconds
Started Aug 10 07:22:48 PM PDT 24
Finished Aug 10 07:22:49 PM PDT 24
Peak memory 215096 kb
Host smart-7f5a2ca0-f55a-4121-91ee-b2eb0c27b589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401762576 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2401762576
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.4174133723
Short name T515
Test name
Test status
Simulation time 315160287 ps
CPU time 4.08 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:50 PM PDT 24
Peak memory 215296 kb
Host smart-3bf94e78-72c2-4048-b131-1013c14bc159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174133723 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.4174133723
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.887288455
Short name T619
Test name
Test status
Simulation time 115368042721 ps
CPU time 754.36 seconds
Started Aug 10 07:22:50 PM PDT 24
Finished Aug 10 07:35:25 PM PDT 24
Peak memory 223584 kb
Host smart-ed4c64fa-7951-45df-8ca7-903dcec603ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887288455 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.887288455
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2569722283
Short name T3
Test name
Test status
Simulation time 51160747 ps
CPU time 1.13 seconds
Started Aug 10 07:22:48 PM PDT 24
Finished Aug 10 07:22:49 PM PDT 24
Peak memory 218840 kb
Host smart-ada5fe74-7826-4877-9765-5eb7ab54dead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569722283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2569722283
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1489573388
Short name T367
Test name
Test status
Simulation time 38782987 ps
CPU time 0.81 seconds
Started Aug 10 07:22:48 PM PDT 24
Finished Aug 10 07:22:49 PM PDT 24
Peak memory 206600 kb
Host smart-d433772d-6203-4646-8a71-aae3639e6a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489573388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1489573388
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2999366181
Short name T162
Test name
Test status
Simulation time 16906041 ps
CPU time 0.84 seconds
Started Aug 10 07:22:56 PM PDT 24
Finished Aug 10 07:22:57 PM PDT 24
Peak memory 216484 kb
Host smart-07649f8e-5273-4d97-a75e-994a6591546b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999366181 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2999366181
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.4002386621
Short name T600
Test name
Test status
Simulation time 91871353 ps
CPU time 1.1 seconds
Started Aug 10 07:22:48 PM PDT 24
Finished Aug 10 07:22:49 PM PDT 24
Peak memory 218364 kb
Host smart-b0ed566b-7cfc-4e63-89a9-3ec67d4c14e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002386621 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.4002386621
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2294545171
Short name T214
Test name
Test status
Simulation time 75793466 ps
CPU time 1.05 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 224164 kb
Host smart-07e09b3e-bef3-4320-a08c-27dc56718feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294545171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2294545171
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3680959504
Short name T928
Test name
Test status
Simulation time 54257037 ps
CPU time 1.3 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 217308 kb
Host smart-083ba408-cc23-4036-8b8b-c6141f429b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680959504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3680959504
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_smoke.1911931839
Short name T948
Test name
Test status
Simulation time 15007546 ps
CPU time 1.04 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:47 PM PDT 24
Peak memory 215276 kb
Host smart-d16f0b6c-cf53-4858-86aa-d02ff537494b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911931839 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1911931839
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1070765869
Short name T947
Test name
Test status
Simulation time 2652006559 ps
CPU time 4.47 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:52 PM PDT 24
Peak memory 217168 kb
Host smart-a78077a7-6d0c-4a65-92ef-6579fb267747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070765869 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1070765869
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4067799574
Short name T36
Test name
Test status
Simulation time 533767559134 ps
CPU time 2242.49 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 08:00:08 PM PDT 24
Peak memory 236980 kb
Host smart-509a0a36-5250-4fee-8cbb-2750019e6012
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067799574 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4067799574
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.4196650556
Short name T639
Test name
Test status
Simulation time 424503002 ps
CPU time 1.42 seconds
Started Aug 10 07:22:48 PM PDT 24
Finished Aug 10 07:22:50 PM PDT 24
Peak memory 219720 kb
Host smart-ab441ae0-dc48-41e2-8e87-b15e75c5efcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196650556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.4196650556
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.842823036
Short name T415
Test name
Test status
Simulation time 13409303 ps
CPU time 0.9 seconds
Started Aug 10 07:22:51 PM PDT 24
Finished Aug 10 07:22:52 PM PDT 24
Peak memory 206828 kb
Host smart-ce60a31b-3e05-4e2d-9652-3b277dc82c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842823036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.842823036
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1522319255
Short name T212
Test name
Test status
Simulation time 32110888 ps
CPU time 0.86 seconds
Started Aug 10 07:22:43 PM PDT 24
Finished Aug 10 07:22:44 PM PDT 24
Peak memory 216552 kb
Host smart-b16e2dd0-9aa9-4efe-ac97-375de64aaf12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522319255 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1522319255
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1792474042
Short name T121
Test name
Test status
Simulation time 51862500 ps
CPU time 1.14 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 217136 kb
Host smart-9605c193-5f79-4b41-8387-869c961a2023
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792474042 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1792474042
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.500601614
Short name T120
Test name
Test status
Simulation time 27188507 ps
CPU time 1 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:49 PM PDT 24
Peak memory 220120 kb
Host smart-527ab58f-419b-4147-a94b-1e179bbc773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500601614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.500601614
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.649303166
Short name T905
Test name
Test status
Simulation time 47801997 ps
CPU time 1.16 seconds
Started Aug 10 07:22:56 PM PDT 24
Finished Aug 10 07:22:58 PM PDT 24
Peak memory 218880 kb
Host smart-b856df27-a004-45e0-8ebf-3edf89f15b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649303166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.649303166
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.241214621
Short name T109
Test name
Test status
Simulation time 90428034 ps
CPU time 0.89 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:47 PM PDT 24
Peak memory 215448 kb
Host smart-d121ba90-7a66-4d07-9665-bf0be8967817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241214621 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.241214621
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.717774992
Short name T446
Test name
Test status
Simulation time 14857073 ps
CPU time 1.01 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 215320 kb
Host smart-5d2a6c2c-a292-4064-bf68-f7fd0b63ee0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717774992 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.717774992
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.69355006
Short name T670
Test name
Test status
Simulation time 25279911 ps
CPU time 1.16 seconds
Started Aug 10 07:22:47 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 215208 kb
Host smart-387ed6cf-a8d8-46f8-8748-969bd8c9665e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69355006 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.69355006
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.882937622
Short name T261
Test name
Test status
Simulation time 129037228868 ps
CPU time 261.85 seconds
Started Aug 10 07:22:56 PM PDT 24
Finished Aug 10 07:27:18 PM PDT 24
Peak memory 218016 kb
Host smart-9d2df1c4-7451-4bbb-96cc-e1167bc5b606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882937622 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.882937622
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1126757866
Short name T134
Test name
Test status
Simulation time 31047535 ps
CPU time 1.29 seconds
Started Aug 10 07:22:48 PM PDT 24
Finished Aug 10 07:22:50 PM PDT 24
Peak memory 220524 kb
Host smart-027faad5-596c-4e74-8ea9-0b6e1e843038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126757866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1126757866
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3941407498
Short name T373
Test name
Test status
Simulation time 77495522 ps
CPU time 0.99 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 206864 kb
Host smart-54611efa-7f3c-4b76-8269-b2835e63a18a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941407498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3941407498
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.68653779
Short name T220
Test name
Test status
Simulation time 13762923 ps
CPU time 0.92 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:00 PM PDT 24
Peak memory 216692 kb
Host smart-cb05b7dc-2a9e-466f-8377-6482cc205c81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68653779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.68653779
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.4041934434
Short name T9
Test name
Test status
Simulation time 34888013 ps
CPU time 0.91 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:00 PM PDT 24
Peak memory 220028 kb
Host smart-9f5a2c67-ee94-475d-a523-321687962fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041934434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4041934434
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3956360970
Short name T906
Test name
Test status
Simulation time 79562059 ps
CPU time 1.34 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 217448 kb
Host smart-973e2caa-1c2c-4e78-a2d3-90383ea0560e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956360970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3956360970
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1119703898
Short name T914
Test name
Test status
Simulation time 20348675 ps
CPU time 1.11 seconds
Started Aug 10 07:22:46 PM PDT 24
Finished Aug 10 07:22:48 PM PDT 24
Peak memory 216156 kb
Host smart-57f39a91-465d-4d97-8d89-3056ec4d0963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119703898 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1119703898
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2427763115
Short name T630
Test name
Test status
Simulation time 30622907 ps
CPU time 0.88 seconds
Started Aug 10 07:22:48 PM PDT 24
Finished Aug 10 07:22:49 PM PDT 24
Peak memory 215312 kb
Host smart-5614f1d1-66e1-4b1b-b2e9-79f5d9276d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427763115 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2427763115
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1126297823
Short name T414
Test name
Test status
Simulation time 574125756 ps
CPU time 3.26 seconds
Started Aug 10 07:22:51 PM PDT 24
Finished Aug 10 07:22:54 PM PDT 24
Peak memory 219608 kb
Host smart-826bb094-c939-4f6e-8b24-c8a8615a0c72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126297823 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1126297823
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_alert.4091194168
Short name T263
Test name
Test status
Simulation time 37807219 ps
CPU time 1.1 seconds
Started Aug 10 07:23:02 PM PDT 24
Finished Aug 10 07:23:03 PM PDT 24
Peak memory 218644 kb
Host smart-d6f35b4b-089c-4614-a193-08e225edda0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091194168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.4091194168
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1499131630
Short name T730
Test name
Test status
Simulation time 20344787 ps
CPU time 1.02 seconds
Started Aug 10 07:23:03 PM PDT 24
Finished Aug 10 07:23:05 PM PDT 24
Peak memory 206748 kb
Host smart-7667d487-9bc9-4db8-ac76-01fcee651a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499131630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1499131630
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.407348073
Short name T176
Test name
Test status
Simulation time 11940817 ps
CPU time 1 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 216624 kb
Host smart-317525fe-428e-43be-976f-e515a590d816
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407348073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.407348073
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.383916506
Short name T711
Test name
Test status
Simulation time 26567911 ps
CPU time 1.01 seconds
Started Aug 10 07:22:58 PM PDT 24
Finished Aug 10 07:22:59 PM PDT 24
Peak memory 219624 kb
Host smart-c8e77821-4289-4f48-a0fd-f95e38b03cb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383916506 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.383916506
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.4108961410
Short name T526
Test name
Test status
Simulation time 29584400 ps
CPU time 1.3 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 219908 kb
Host smart-6fc7bc2d-4267-428a-89d3-ddb0bd714e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108961410 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.4108961410
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.81376053
Short name T398
Test name
Test status
Simulation time 40713432 ps
CPU time 1.52 seconds
Started Aug 10 07:22:58 PM PDT 24
Finished Aug 10 07:22:59 PM PDT 24
Peak memory 217388 kb
Host smart-8793ecd5-877f-4d43-862d-8085f8d7b97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81376053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.81376053
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.4138401999
Short name T95
Test name
Test status
Simulation time 25771162 ps
CPU time 0.96 seconds
Started Aug 10 07:22:57 PM PDT 24
Finished Aug 10 07:22:58 PM PDT 24
Peak memory 216036 kb
Host smart-5eb1a6ec-6cf3-4dfa-bb5c-29d75b9d20eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138401999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4138401999
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2195573471
Short name T537
Test name
Test status
Simulation time 44125632 ps
CPU time 0.92 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:00 PM PDT 24
Peak memory 215256 kb
Host smart-c9c10936-1379-4f36-b4d4-25d2be7214d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195573471 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2195573471
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.569501949
Short name T929
Test name
Test status
Simulation time 108139143 ps
CPU time 2.14 seconds
Started Aug 10 07:23:02 PM PDT 24
Finished Aug 10 07:23:04 PM PDT 24
Peak memory 217256 kb
Host smart-c7f95de8-b1f8-41a7-8162-3a31b76d81c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569501949 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.569501949
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3943865153
Short name T246
Test name
Test status
Simulation time 34649044302 ps
CPU time 404.27 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:29:45 PM PDT 24
Peak memory 217576 kb
Host smart-78c24ec1-237f-4a8f-865a-1c21a8eb000c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943865153 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3943865153
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3100885382
Short name T293
Test name
Test status
Simulation time 99589798 ps
CPU time 1.35 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 215712 kb
Host smart-444aa721-868e-466f-b799-3b7ddf78f6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100885382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3100885382
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.707213942
Short name T447
Test name
Test status
Simulation time 217641287 ps
CPU time 0.88 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 206856 kb
Host smart-52d5446d-74b5-418f-bf2f-86b6568d5644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707213942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.707213942
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1479957964
Short name T168
Test name
Test status
Simulation time 33354536 ps
CPU time 0.86 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 216440 kb
Host smart-9b9c9024-169f-4932-9c0b-a572154b2dd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479957964 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1479957964
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1900745573
Short name T148
Test name
Test status
Simulation time 99127219 ps
CPU time 1.1 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:23:03 PM PDT 24
Peak memory 219368 kb
Host smart-c95bba99-cbdf-4c46-8a0a-d1896cfbb70b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900745573 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1900745573
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1920429391
Short name T61
Test name
Test status
Simulation time 39139138 ps
CPU time 1.21 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 229844 kb
Host smart-e78d7484-bc02-47fa-869f-979d0703e011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920429391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1920429391
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.994827691
Short name T93
Test name
Test status
Simulation time 90076984 ps
CPU time 2.67 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 220488 kb
Host smart-4085bdae-6caa-448b-b45c-e8e21852b233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994827691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.994827691
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.519413166
Short name T111
Test name
Test status
Simulation time 20750636 ps
CPU time 1.06 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 216676 kb
Host smart-12596d0e-45c9-4764-ac19-ed76fbd5eb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519413166 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.519413166
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3898375584
Short name T886
Test name
Test status
Simulation time 18423357 ps
CPU time 1.02 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:00 PM PDT 24
Peak memory 215312 kb
Host smart-1954c32e-3fb4-47a4-a395-67580ffc8dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898375584 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3898375584
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2730350462
Short name T833
Test name
Test status
Simulation time 413865954 ps
CPU time 2.76 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:03 PM PDT 24
Peak memory 215416 kb
Host smart-31aab895-547c-4c23-817d-5f91e220b2c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730350462 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2730350462
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1629245275
Short name T517
Test name
Test status
Simulation time 51876020556 ps
CPU time 1177.65 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:42:39 PM PDT 24
Peak memory 220240 kb
Host smart-307096f2-848e-4acf-8339-f6b19eb9733f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629245275 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1629245275
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.4100243765
Short name T151
Test name
Test status
Simulation time 70385462 ps
CPU time 1.23 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 218756 kb
Host smart-39fb4f23-54e0-416e-99d1-10b86675c633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100243765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.4100243765
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2746385771
Short name T453
Test name
Test status
Simulation time 33335421 ps
CPU time 1.18 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 215300 kb
Host smart-6ce14d10-7fb7-43ea-8108-ad85ddedc975
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746385771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2746385771
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.607805429
Short name T547
Test name
Test status
Simulation time 10608526 ps
CPU time 0.84 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:00 PM PDT 24
Peak memory 215360 kb
Host smart-c77a55ba-b7ba-41a1-9a87-705119127080
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607805429 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.607805429
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.3670789833
Short name T4
Test name
Test status
Simulation time 21307616 ps
CPU time 1.11 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:00 PM PDT 24
Peak memory 224320 kb
Host smart-63fe7246-03a8-46e0-8d0e-715d275b8794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670789833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3670789833
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1571937947
Short name T561
Test name
Test status
Simulation time 139725721 ps
CPU time 1.51 seconds
Started Aug 10 07:22:58 PM PDT 24
Finished Aug 10 07:23:00 PM PDT 24
Peak memory 218684 kb
Host smart-871200f4-6193-42f1-a478-925ed541428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571937947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1571937947
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.4126930769
Short name T26
Test name
Test status
Simulation time 19797273 ps
CPU time 1.15 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 216088 kb
Host smart-0be7a1ab-e020-480e-80fa-e51c9c2d74ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126930769 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.4126930769
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.791711836
Short name T296
Test name
Test status
Simulation time 80620907 ps
CPU time 0.92 seconds
Started Aug 10 07:22:57 PM PDT 24
Finished Aug 10 07:22:58 PM PDT 24
Peak memory 215304 kb
Host smart-13e679f9-e6c7-494f-8b45-8902bcb723a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791711836 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.791711836
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3382646401
Short name T557
Test name
Test status
Simulation time 1145575188 ps
CPU time 3.86 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:03 PM PDT 24
Peak memory 215448 kb
Host smart-2d53f47f-7b37-4be5-9691-b8d762d9e0ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382646401 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3382646401
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1263408548
Short name T418
Test name
Test status
Simulation time 53914279353 ps
CPU time 1270.31 seconds
Started Aug 10 07:23:02 PM PDT 24
Finished Aug 10 07:44:13 PM PDT 24
Peak memory 221260 kb
Host smart-ed1c42d2-afe6-4c23-a2f7-ebdb28acea62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263408548 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1263408548
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.319095715
Short name T787
Test name
Test status
Simulation time 39893176 ps
CPU time 1.12 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 218756 kb
Host smart-37c69ec2-404d-420c-b46e-d79af38bb785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319095715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.319095715
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.456620174
Short name T658
Test name
Test status
Simulation time 44432497 ps
CPU time 1.04 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 206852 kb
Host smart-80dca8c7-b63b-45f7-8abc-ae6c948ec530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456620174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.456620174
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.690364836
Short name T937
Test name
Test status
Simulation time 19423052 ps
CPU time 0.89 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 216576 kb
Host smart-48e84f9f-8617-48b7-b924-0b91e63e602d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690364836 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.690364836
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.4225283191
Short name T539
Test name
Test status
Simulation time 37361977 ps
CPU time 1.31 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 217064 kb
Host smart-840a9077-ef84-4a2a-80da-ef507a5da567
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225283191 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.4225283191
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1337930040
Short name T218
Test name
Test status
Simulation time 33277569 ps
CPU time 0.99 seconds
Started Aug 10 07:22:58 PM PDT 24
Finished Aug 10 07:22:59 PM PDT 24
Peak memory 223968 kb
Host smart-da5412db-9728-403c-92c4-ca429c6b01e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337930040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1337930040
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.542540065
Short name T427
Test name
Test status
Simulation time 260726524 ps
CPU time 3.63 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:03 PM PDT 24
Peak memory 219252 kb
Host smart-1ffe0110-609d-4746-a826-c1bb9cf65730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542540065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.542540065
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2204948488
Short name T33
Test name
Test status
Simulation time 27407597 ps
CPU time 0.95 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:00 PM PDT 24
Peak memory 216112 kb
Host smart-04593d47-39e7-4acf-bae5-87e006b81c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204948488 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2204948488
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.882182829
Short name T384
Test name
Test status
Simulation time 17009927 ps
CPU time 1.03 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 215260 kb
Host smart-3e5a98b6-630b-4d4b-9275-2efcb0afa240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882182829 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.882182829
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.4122693404
Short name T994
Test name
Test status
Simulation time 172559957 ps
CPU time 3.81 seconds
Started Aug 10 07:22:58 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 220228 kb
Host smart-cc5c3fbb-0c9f-4571-be21-900cda39c64c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122693404 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.4122693404
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.4045842146
Short name T636
Test name
Test status
Simulation time 449065330961 ps
CPU time 750.88 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:35:32 PM PDT 24
Peak memory 221116 kb
Host smart-415c1e9b-fdbd-41cf-9193-e31d7006ed1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045842146 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.4045842146
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3206455045
Short name T977
Test name
Test status
Simulation time 90981883 ps
CPU time 1.2 seconds
Started Aug 10 07:21:38 PM PDT 24
Finished Aug 10 07:21:40 PM PDT 24
Peak memory 220556 kb
Host smart-bd980d45-e699-4e9e-a806-6c7274ec644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206455045 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3206455045
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1925064300
Short name T806
Test name
Test status
Simulation time 44653949 ps
CPU time 0.94 seconds
Started Aug 10 07:21:45 PM PDT 24
Finished Aug 10 07:21:46 PM PDT 24
Peak memory 206828 kb
Host smart-c2c2497a-22f2-49d7-90b6-097bf1a5bc87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925064300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1925064300
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3522182348
Short name T203
Test name
Test status
Simulation time 31619372 ps
CPU time 0.86 seconds
Started Aug 10 07:21:46 PM PDT 24
Finished Aug 10 07:21:47 PM PDT 24
Peak memory 216448 kb
Host smart-8892fb04-1c33-4dbc-914a-55dd6d2d148a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522182348 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3522182348
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2448222427
Short name T620
Test name
Test status
Simulation time 59303250 ps
CPU time 1.16 seconds
Started Aug 10 07:21:47 PM PDT 24
Finished Aug 10 07:21:48 PM PDT 24
Peak memory 219476 kb
Host smart-1f476cff-1a10-4475-b5e6-6a692f1ebb84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448222427 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2448222427
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1592064010
Short name T845
Test name
Test status
Simulation time 94649177 ps
CPU time 1.22 seconds
Started Aug 10 07:21:39 PM PDT 24
Finished Aug 10 07:21:41 PM PDT 24
Peak memory 220004 kb
Host smart-b344b234-78b3-4e56-9b6c-0391a76b857b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592064010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1592064010
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2287656440
Short name T635
Test name
Test status
Simulation time 67748399 ps
CPU time 1.22 seconds
Started Aug 10 07:21:39 PM PDT 24
Finished Aug 10 07:21:40 PM PDT 24
Peak memory 220100 kb
Host smart-778b74ce-84a9-481e-9666-2f38440f91cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287656440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2287656440
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.264698071
Short name T989
Test name
Test status
Simulation time 25369681 ps
CPU time 1.02 seconds
Started Aug 10 07:21:36 PM PDT 24
Finished Aug 10 07:21:37 PM PDT 24
Peak memory 224128 kb
Host smart-9fb11266-1574-4728-8aac-c78e1a6bf8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264698071 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.264698071
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2746889422
Short name T629
Test name
Test status
Simulation time 26073896 ps
CPU time 0.95 seconds
Started Aug 10 07:21:36 PM PDT 24
Finished Aug 10 07:21:37 PM PDT 24
Peak memory 207068 kb
Host smart-a2086f11-59c0-44a2-8212-a51c582e5ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746889422 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2746889422
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.4030061680
Short name T67
Test name
Test status
Simulation time 1093442058 ps
CPU time 5.18 seconds
Started Aug 10 07:21:49 PM PDT 24
Finished Aug 10 07:21:55 PM PDT 24
Peak memory 242912 kb
Host smart-49cdc540-dd7d-41c6-a044-5c06e0fe4463
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030061680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.4030061680
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.842942866
Short name T804
Test name
Test status
Simulation time 42377160 ps
CPU time 0.87 seconds
Started Aug 10 07:21:37 PM PDT 24
Finished Aug 10 07:21:38 PM PDT 24
Peak memory 215316 kb
Host smart-5ba490c7-ee9b-4ca2-8806-5547f4ffe86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842942866 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.842942866
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.735569848
Short name T652
Test name
Test status
Simulation time 146278248 ps
CPU time 2.02 seconds
Started Aug 10 07:21:39 PM PDT 24
Finished Aug 10 07:21:42 PM PDT 24
Peak memory 218624 kb
Host smart-910cde2b-139b-463c-bb02-3cf6a28e1055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735569848 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.735569848
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3124826165
Short name T542
Test name
Test status
Simulation time 47511398853 ps
CPU time 1231.29 seconds
Started Aug 10 07:21:38 PM PDT 24
Finished Aug 10 07:42:09 PM PDT 24
Peak memory 223588 kb
Host smart-3383431d-e495-406c-92ab-2f8dce3b4d9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124826165 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3124826165
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.882095737
Short name T878
Test name
Test status
Simulation time 33124812 ps
CPU time 1.24 seconds
Started Aug 10 07:23:03 PM PDT 24
Finished Aug 10 07:23:04 PM PDT 24
Peak memory 219740 kb
Host smart-960f82ea-7940-4e65-a96e-2ccdc225cfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882095737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.882095737
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.899230260
Short name T685
Test name
Test status
Simulation time 269068028 ps
CPU time 1.74 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:23:03 PM PDT 24
Peak memory 206984 kb
Host smart-11f745d1-0d69-4231-bc68-a8c24f93625e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899230260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.899230260
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1693833133
Short name T187
Test name
Test status
Simulation time 16887948 ps
CPU time 0.83 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 216492 kb
Host smart-dc4beed4-ca11-4bdf-96d8-adb11103d6db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693833133 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1693833133
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.3688089313
Short name T17
Test name
Test status
Simulation time 21967626 ps
CPU time 1.05 seconds
Started Aug 10 07:23:03 PM PDT 24
Finished Aug 10 07:23:05 PM PDT 24
Peak memory 224036 kb
Host smart-5146ff5e-3492-48aa-aff9-7c62b3116daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688089313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3688089313
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1715384954
Short name T423
Test name
Test status
Simulation time 30410985 ps
CPU time 1.27 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 217324 kb
Host smart-2cc492f5-453f-4bb0-9272-fad7222df280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715384954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1715384954
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.4073731299
Short name T980
Test name
Test status
Simulation time 21986448 ps
CPU time 1.21 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:00 PM PDT 24
Peak memory 224208 kb
Host smart-4de7d37b-daf8-44bf-a312-a243ac5e26a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073731299 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.4073731299
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2929707523
Short name T75
Test name
Test status
Simulation time 23697895 ps
CPU time 0.98 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:00 PM PDT 24
Peak memory 215304 kb
Host smart-670dea4c-f0e0-4ffc-a8bd-dc30d3935f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929707523 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2929707523
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.415556461
Short name T564
Test name
Test status
Simulation time 262263223 ps
CPU time 5.19 seconds
Started Aug 10 07:23:02 PM PDT 24
Finished Aug 10 07:23:07 PM PDT 24
Peak memory 218520 kb
Host smart-8da4d54a-9bbc-470c-bfa6-0b7f6e640077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415556461 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.415556461
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3944975987
Short name T238
Test name
Test status
Simulation time 17640209801 ps
CPU time 315.89 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:28:18 PM PDT 24
Peak memory 218160 kb
Host smart-88fd3335-295d-43a3-a91a-1fbf13cad16a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944975987 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3944975987
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.587054496
Short name T945
Test name
Test status
Simulation time 29038139 ps
CPU time 1.29 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 219704 kb
Host smart-1dd56bdb-c189-49cb-a83a-b89f58da8263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587054496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.587054496
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3930910087
Short name T891
Test name
Test status
Simulation time 18979797 ps
CPU time 0.95 seconds
Started Aug 10 07:22:58 PM PDT 24
Finished Aug 10 07:22:59 PM PDT 24
Peak memory 206856 kb
Host smart-741eea79-e6e5-457c-b93f-b35bf0394a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930910087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3930910087
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2435055447
Short name T202
Test name
Test status
Simulation time 57687176 ps
CPU time 0.82 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 218252 kb
Host smart-ea14fc24-e12d-4d0f-a0e2-489e42506427
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435055447 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2435055447
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1439021480
Short name T595
Test name
Test status
Simulation time 112932791 ps
CPU time 1.2 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 219480 kb
Host smart-548a6c52-5584-4164-a59a-fb2c50c134bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439021480 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1439021480
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3648359838
Short name T137
Test name
Test status
Simulation time 29847658 ps
CPU time 1.45 seconds
Started Aug 10 07:23:03 PM PDT 24
Finished Aug 10 07:23:05 PM PDT 24
Peak memory 225804 kb
Host smart-e3d8a77e-c67c-4cc8-a324-a5003d91cd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648359838 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3648359838
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3390152739
Short name T924
Test name
Test status
Simulation time 49831850 ps
CPU time 1.11 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 218420 kb
Host smart-c10bfd44-1362-469b-9019-12f1a3728718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390152739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3390152739
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2585129496
Short name T778
Test name
Test status
Simulation time 20922407 ps
CPU time 1.08 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 215448 kb
Host smart-a2e3faad-b748-44bf-9811-3083b87680b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585129496 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2585129496
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.615803634
Short name T818
Test name
Test status
Simulation time 18418354 ps
CPU time 1.03 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:23:03 PM PDT 24
Peak memory 215320 kb
Host smart-20ef8bf4-c3d6-4cb6-9594-48c3690844cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615803634 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.615803634
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.4039093876
Short name T370
Test name
Test status
Simulation time 833990374 ps
CPU time 3.3 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:23:05 PM PDT 24
Peak memory 217520 kb
Host smart-a8142a70-53ec-418a-bab1-00104f5568e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039093876 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.4039093876
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1090704658
Short name T440
Test name
Test status
Simulation time 107091506495 ps
CPU time 1204.96 seconds
Started Aug 10 07:23:03 PM PDT 24
Finished Aug 10 07:43:09 PM PDT 24
Peak memory 222300 kb
Host smart-ff045ddf-579c-4a26-b7f5-3a609ba354fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090704658 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1090704658
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3150786062
Short name T941
Test name
Test status
Simulation time 46065500 ps
CPU time 1.31 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 220256 kb
Host smart-145d14b9-c0f7-4ea5-90a5-3dafeded6c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150786062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3150786062
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1118192573
Short name T729
Test name
Test status
Simulation time 117585756 ps
CPU time 0.8 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 206820 kb
Host smart-4c95de71-547d-4609-b711-1f663a7770ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118192573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1118192573
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3439698557
Short name T364
Test name
Test status
Simulation time 19715169 ps
CPU time 0.89 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 216376 kb
Host smart-98eabcdf-c872-4077-80e7-8cdd2a8e98fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439698557 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3439698557
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.188871945
Short name T143
Test name
Test status
Simulation time 80327324 ps
CPU time 1 seconds
Started Aug 10 07:22:58 PM PDT 24
Finished Aug 10 07:22:59 PM PDT 24
Peak memory 217044 kb
Host smart-81a124f2-18c2-48f2-89f9-7a2791d2a320
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188871945 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.188871945
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3413855457
Short name T624
Test name
Test status
Simulation time 19674844 ps
CPU time 1.13 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:00 PM PDT 24
Peak memory 224112 kb
Host smart-523711c3-e2fe-4b8d-95da-6ee3af158255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413855457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3413855457
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3880798303
Short name T324
Test name
Test status
Simulation time 92737657 ps
CPU time 1.9 seconds
Started Aug 10 07:23:03 PM PDT 24
Finished Aug 10 07:23:05 PM PDT 24
Peak memory 219916 kb
Host smart-db274d74-287c-4734-af98-99d2e970c534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880798303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3880798303
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.4255131275
Short name T386
Test name
Test status
Simulation time 38759401 ps
CPU time 0.91 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 215468 kb
Host smart-7c17dabf-f25b-4b6c-9ee2-c0d3937ac231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255131275 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.4255131275
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.593149009
Short name T468
Test name
Test status
Simulation time 99585854 ps
CPU time 0.85 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:22:59 PM PDT 24
Peak memory 215144 kb
Host smart-c2997f0c-099c-454a-b4ff-ccaf6e16fbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593149009 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.593149009
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3644644169
Short name T785
Test name
Test status
Simulation time 178610785 ps
CPU time 2.33 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 217408 kb
Host smart-046e1a15-2708-455f-a191-9c369fc87db1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644644169 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3644644169
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3261155360
Short name T235
Test name
Test status
Simulation time 56685403648 ps
CPU time 1435.8 seconds
Started Aug 10 07:23:02 PM PDT 24
Finished Aug 10 07:46:58 PM PDT 24
Peak memory 223168 kb
Host smart-ab993f4e-82d6-499f-8306-37df58e22a56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261155360 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3261155360
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2067027358
Short name T786
Test name
Test status
Simulation time 72439449 ps
CPU time 1.21 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:23:03 PM PDT 24
Peak memory 219852 kb
Host smart-5b9e3a92-341f-43f7-b1eb-e38b6463845b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067027358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2067027358
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.872165422
Short name T634
Test name
Test status
Simulation time 163035968 ps
CPU time 0.87 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 206660 kb
Host smart-c963cbea-af71-4249-b2d3-536211eeff0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872165422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.872165422
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1382418753
Short name T188
Test name
Test status
Simulation time 15609220 ps
CPU time 0.89 seconds
Started Aug 10 07:23:03 PM PDT 24
Finished Aug 10 07:23:05 PM PDT 24
Peak memory 219040 kb
Host smart-724b6b4a-eb7a-412a-9e15-90494b9cc30f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382418753 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1382418753
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1222896099
Short name T363
Test name
Test status
Simulation time 102168264 ps
CPU time 1.18 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 217080 kb
Host smart-0ef490f2-0ed9-48f0-83a8-3351cc810be6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222896099 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1222896099
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3391735627
Short name T819
Test name
Test status
Simulation time 22480958 ps
CPU time 0.99 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 218800 kb
Host smart-f569cc6e-84a9-4fd3-815d-ad70896b673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391735627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3391735627
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3037974488
Short name T371
Test name
Test status
Simulation time 68221705 ps
CPU time 1.23 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:23:02 PM PDT 24
Peak memory 219272 kb
Host smart-891134fc-c11b-446b-8232-d22c628c7a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037974488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3037974488
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.4141304796
Short name T466
Test name
Test status
Simulation time 27712474 ps
CPU time 0.95 seconds
Started Aug 10 07:22:59 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 215508 kb
Host smart-f6675299-0031-40f3-b54d-ba4ce8940eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141304796 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.4141304796
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2259278535
Short name T540
Test name
Test status
Simulation time 48243462 ps
CPU time 1 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 215312 kb
Host smart-eacb49e6-ebf7-406a-ab8e-1dcbe3fca348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259278535 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2259278535
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3582306138
Short name T257
Test name
Test status
Simulation time 558846366 ps
CPU time 3.44 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:23:05 PM PDT 24
Peak memory 217376 kb
Host smart-d91ed710-c707-4531-aaeb-4b3ba9686d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582306138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3582306138
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2424054222
Short name T242
Test name
Test status
Simulation time 701474456953 ps
CPU time 2207.53 seconds
Started Aug 10 07:23:01 PM PDT 24
Finished Aug 10 07:59:49 PM PDT 24
Peak memory 225908 kb
Host smart-c004529e-cd36-4c14-822c-119c2b86489c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424054222 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2424054222
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.4255341845
Short name T765
Test name
Test status
Simulation time 33545156 ps
CPU time 1.17 seconds
Started Aug 10 07:23:20 PM PDT 24
Finished Aug 10 07:23:21 PM PDT 24
Peak memory 219564 kb
Host smart-19dfa56f-c6b5-4a97-aa75-05b3d2ae7f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255341845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4255341845
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.811772036
Short name T434
Test name
Test status
Simulation time 20747268 ps
CPU time 1 seconds
Started Aug 10 07:23:09 PM PDT 24
Finished Aug 10 07:23:10 PM PDT 24
Peak memory 215208 kb
Host smart-4c661cfd-f1fd-490f-8064-4693781ee857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811772036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.811772036
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1708772423
Short name T79
Test name
Test status
Simulation time 37561236 ps
CPU time 0.88 seconds
Started Aug 10 07:23:13 PM PDT 24
Finished Aug 10 07:23:14 PM PDT 24
Peak memory 216456 kb
Host smart-84cb2f6a-3e6d-43a6-b278-35e44dc94df4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708772423 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1708772423
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.712509980
Short name T865
Test name
Test status
Simulation time 27805487 ps
CPU time 1.08 seconds
Started Aug 10 07:23:08 PM PDT 24
Finished Aug 10 07:23:10 PM PDT 24
Peak memory 218568 kb
Host smart-279da5d9-2b6c-428a-9320-5c3ec4249f25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712509980 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.712509980
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2290992430
Short name T710
Test name
Test status
Simulation time 42380662 ps
CPU time 1.03 seconds
Started Aug 10 07:23:07 PM PDT 24
Finished Aug 10 07:23:08 PM PDT 24
Peak memory 218860 kb
Host smart-29e8b10a-3e60-4fe2-92c3-44c4ff8c3ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290992430 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2290992430
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2492165144
Short name T753
Test name
Test status
Simulation time 85678817 ps
CPU time 1.22 seconds
Started Aug 10 07:23:02 PM PDT 24
Finished Aug 10 07:23:03 PM PDT 24
Peak memory 220332 kb
Host smart-a1f6b764-06a7-4b2c-a313-0a3fd2174b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492165144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2492165144
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1402517989
Short name T613
Test name
Test status
Simulation time 34959059 ps
CPU time 0.98 seconds
Started Aug 10 07:23:02 PM PDT 24
Finished Aug 10 07:23:03 PM PDT 24
Peak memory 215508 kb
Host smart-046cef36-8a47-4259-b495-b72e945a4cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402517989 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1402517989
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1806399952
Short name T809
Test name
Test status
Simulation time 32203009 ps
CPU time 1.08 seconds
Started Aug 10 07:23:02 PM PDT 24
Finished Aug 10 07:23:03 PM PDT 24
Peak memory 215336 kb
Host smart-f8af75e5-b22a-41b6-8df9-903350c412c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806399952 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1806399952
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3373902980
Short name T251
Test name
Test status
Simulation time 252526357 ps
CPU time 1.22 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:23:01 PM PDT 24
Peak memory 217428 kb
Host smart-0efd8b0e-3c07-4472-be01-7ebf7fe362bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373902980 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3373902980
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3228054790
Short name T964
Test name
Test status
Simulation time 805530022110 ps
CPU time 1056.24 seconds
Started Aug 10 07:23:00 PM PDT 24
Finished Aug 10 07:40:37 PM PDT 24
Peak memory 221148 kb
Host smart-9835a5c2-9a3c-48e6-8797-a0d19a23cfee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228054790 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3228054790
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3627674876
Short name T127
Test name
Test status
Simulation time 40679678 ps
CPU time 1.16 seconds
Started Aug 10 07:23:17 PM PDT 24
Finished Aug 10 07:23:18 PM PDT 24
Peak memory 218628 kb
Host smart-ef01fb94-a9a0-4db0-ac9e-fefae675207c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627674876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3627674876
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.655569901
Short name T744
Test name
Test status
Simulation time 27597858 ps
CPU time 1.18 seconds
Started Aug 10 07:23:09 PM PDT 24
Finished Aug 10 07:23:10 PM PDT 24
Peak memory 206912 kb
Host smart-50eda371-ae0b-4267-adc2-2be2675a358b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655569901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.655569901
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1427904238
Short name T690
Test name
Test status
Simulation time 11154039 ps
CPU time 0.86 seconds
Started Aug 10 07:23:13 PM PDT 24
Finished Aug 10 07:23:14 PM PDT 24
Peak memory 215384 kb
Host smart-498d304c-26a9-45a0-b4dc-a57f4d566c88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427904238 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1427904238
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2606500201
Short name T987
Test name
Test status
Simulation time 32470055 ps
CPU time 1.22 seconds
Started Aug 10 07:23:09 PM PDT 24
Finished Aug 10 07:23:10 PM PDT 24
Peak memory 217184 kb
Host smart-33754a39-5e1a-43a7-b07d-20836c53c333
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606500201 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2606500201
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.853775077
Short name T784
Test name
Test status
Simulation time 30899819 ps
CPU time 0.93 seconds
Started Aug 10 07:23:24 PM PDT 24
Finished Aug 10 07:23:25 PM PDT 24
Peak memory 218524 kb
Host smart-d2a94982-dc7c-4f2a-afb1-feb5f4812054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853775077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.853775077
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.830592952
Short name T546
Test name
Test status
Simulation time 60016003 ps
CPU time 1.33 seconds
Started Aug 10 07:23:11 PM PDT 24
Finished Aug 10 07:23:12 PM PDT 24
Peak memory 217300 kb
Host smart-b10056c8-6e11-449f-845a-1b0fbf8a4325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830592952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.830592952
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1956227925
Short name T89
Test name
Test status
Simulation time 25971154 ps
CPU time 0.95 seconds
Started Aug 10 07:23:15 PM PDT 24
Finished Aug 10 07:23:16 PM PDT 24
Peak memory 215944 kb
Host smart-31fe162c-0203-40c3-b6ef-06da47a5aaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956227925 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1956227925
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2088531705
Short name T860
Test name
Test status
Simulation time 20501688 ps
CPU time 1 seconds
Started Aug 10 07:23:09 PM PDT 24
Finished Aug 10 07:23:10 PM PDT 24
Peak memory 215264 kb
Host smart-58b52e39-7b95-44e0-b7c7-51346bd3f3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088531705 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2088531705
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3022571586
Short name T96
Test name
Test status
Simulation time 801020019 ps
CPU time 4.2 seconds
Started Aug 10 07:23:09 PM PDT 24
Finished Aug 10 07:23:14 PM PDT 24
Peak memory 217248 kb
Host smart-c8a13674-146a-47bb-82da-505f5584c2c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022571586 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3022571586
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2415933819
Short name T858
Test name
Test status
Simulation time 168444059230 ps
CPU time 1956.22 seconds
Started Aug 10 07:23:13 PM PDT 24
Finished Aug 10 07:55:50 PM PDT 24
Peak memory 227240 kb
Host smart-e5f155d8-5a03-4763-907d-ade7ec81a937
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415933819 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2415933819
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2176192992
Short name T315
Test name
Test status
Simulation time 77535972 ps
CPU time 1.17 seconds
Started Aug 10 07:23:17 PM PDT 24
Finished Aug 10 07:23:19 PM PDT 24
Peak memory 220044 kb
Host smart-84d90125-b9f1-426d-9b04-6c40cb3cecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176192992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2176192992
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.624982002
Short name T249
Test name
Test status
Simulation time 70886356 ps
CPU time 1.75 seconds
Started Aug 10 07:23:09 PM PDT 24
Finished Aug 10 07:23:11 PM PDT 24
Peak memory 207004 kb
Host smart-2edf5f0a-c5b6-4ae9-a136-930dfe019be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624982002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.624982002
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3768290121
Short name T229
Test name
Test status
Simulation time 40786660 ps
CPU time 0.89 seconds
Started Aug 10 07:23:12 PM PDT 24
Finished Aug 10 07:23:13 PM PDT 24
Peak memory 215388 kb
Host smart-2eb11e3f-7ffb-4305-a685-fd3231150321
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768290121 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3768290121
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.967535623
Short name T831
Test name
Test status
Simulation time 38776896 ps
CPU time 1.23 seconds
Started Aug 10 07:23:12 PM PDT 24
Finished Aug 10 07:23:14 PM PDT 24
Peak memory 217156 kb
Host smart-0c31bb6c-a3a5-43ae-aeaf-2fb566ad61ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967535623 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.967535623
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1618379298
Short name T211
Test name
Test status
Simulation time 34861604 ps
CPU time 1.08 seconds
Started Aug 10 07:23:10 PM PDT 24
Finished Aug 10 07:23:11 PM PDT 24
Peak memory 219980 kb
Host smart-76e60471-d6bb-4e84-bcb2-c7b1077be6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618379298 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1618379298
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.812235640
Short name T317
Test name
Test status
Simulation time 44783869 ps
CPU time 1.29 seconds
Started Aug 10 07:23:11 PM PDT 24
Finished Aug 10 07:23:13 PM PDT 24
Peak memory 217400 kb
Host smart-2d9646a4-f405-4d07-87b4-7776c1e722c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812235640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.812235640
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3791289696
Short name T110
Test name
Test status
Simulation time 41559042 ps
CPU time 0.83 seconds
Started Aug 10 07:23:09 PM PDT 24
Finished Aug 10 07:23:10 PM PDT 24
Peak memory 215804 kb
Host smart-087660ae-a9b0-4d56-8339-33cc671325ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791289696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3791289696
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3322673421
Short name T85
Test name
Test status
Simulation time 47478413 ps
CPU time 0.97 seconds
Started Aug 10 07:23:12 PM PDT 24
Finished Aug 10 07:23:13 PM PDT 24
Peak memory 215300 kb
Host smart-324ed008-c051-4e90-aee8-c0a735919407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322673421 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3322673421
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.623832694
Short name T397
Test name
Test status
Simulation time 285052655 ps
CPU time 2.04 seconds
Started Aug 10 07:23:12 PM PDT 24
Finished Aug 10 07:23:14 PM PDT 24
Peak memory 215364 kb
Host smart-0288ac82-69a9-4f38-978b-78274208ce86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623832694 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.623832694
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2460865349
Short name T236
Test name
Test status
Simulation time 215244694951 ps
CPU time 1317.85 seconds
Started Aug 10 07:23:12 PM PDT 24
Finished Aug 10 07:45:10 PM PDT 24
Peak memory 223876 kb
Host smart-04f5a656-4e0d-415f-ac7e-b3d4366be072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460865349 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2460865349
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1838457192
Short name T643
Test name
Test status
Simulation time 216331497 ps
CPU time 1.27 seconds
Started Aug 10 07:23:11 PM PDT 24
Finished Aug 10 07:23:12 PM PDT 24
Peak memory 215592 kb
Host smart-d9a99886-bfc6-4e02-b71e-49ef396f0b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838457192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1838457192
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3105733747
Short name T612
Test name
Test status
Simulation time 16689404 ps
CPU time 0.96 seconds
Started Aug 10 07:23:11 PM PDT 24
Finished Aug 10 07:23:12 PM PDT 24
Peak memory 215188 kb
Host smart-a6d29908-23b0-43d4-b853-3fe8205a3a35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105733747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3105733747
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3300644260
Short name T169
Test name
Test status
Simulation time 68970533 ps
CPU time 0.89 seconds
Started Aug 10 07:23:10 PM PDT 24
Finished Aug 10 07:23:11 PM PDT 24
Peak memory 216480 kb
Host smart-fea6e555-ca4c-4d70-be97-52323d26266a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300644260 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3300644260
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.208521838
Short name T206
Test name
Test status
Simulation time 37641425 ps
CPU time 1.28 seconds
Started Aug 10 07:23:15 PM PDT 24
Finished Aug 10 07:23:16 PM PDT 24
Peak memory 218408 kb
Host smart-c9aedfb7-dcf4-4175-86fd-387f88517344
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208521838 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.208521838
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3697186149
Short name T193
Test name
Test status
Simulation time 30356723 ps
CPU time 0.85 seconds
Started Aug 10 07:23:08 PM PDT 24
Finished Aug 10 07:23:09 PM PDT 24
Peak memory 218520 kb
Host smart-72682b1d-fc13-4657-ac32-0be1f3f4d7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697186149 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3697186149
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1095414855
Short name T721
Test name
Test status
Simulation time 82011050 ps
CPU time 1.3 seconds
Started Aug 10 07:23:13 PM PDT 24
Finished Aug 10 07:23:15 PM PDT 24
Peak memory 218680 kb
Host smart-6067bcc3-3c7b-4bc9-aaa7-ca8a8ef22bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095414855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1095414855
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3810230968
Short name T94
Test name
Test status
Simulation time 41527627 ps
CPU time 0.88 seconds
Started Aug 10 07:23:12 PM PDT 24
Finished Aug 10 07:23:13 PM PDT 24
Peak memory 215784 kb
Host smart-dbfb5a15-d77d-4f8c-8f05-b06563e5a591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810230968 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3810230968
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1965053163
Short name T101
Test name
Test status
Simulation time 16723864 ps
CPU time 1 seconds
Started Aug 10 07:23:16 PM PDT 24
Finished Aug 10 07:23:17 PM PDT 24
Peak memory 215264 kb
Host smart-3523a3d1-25e7-4e80-a70d-01a045bc80e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965053163 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1965053163
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2173888108
Short name T830
Test name
Test status
Simulation time 614680647 ps
CPU time 4.48 seconds
Started Aug 10 07:23:24 PM PDT 24
Finished Aug 10 07:23:29 PM PDT 24
Peak memory 217224 kb
Host smart-14a93fb0-722f-4dce-b3d8-7413096af5ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173888108 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2173888108
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3689114109
Short name T497
Test name
Test status
Simulation time 395461309327 ps
CPU time 1098.84 seconds
Started Aug 10 07:23:09 PM PDT 24
Finished Aug 10 07:41:28 PM PDT 24
Peak memory 231296 kb
Host smart-46bf3796-fe83-43ab-9639-b843cc092fcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689114109 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3689114109
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3295641619
Short name T704
Test name
Test status
Simulation time 28758670 ps
CPU time 1.3 seconds
Started Aug 10 07:23:14 PM PDT 24
Finished Aug 10 07:23:15 PM PDT 24
Peak memory 219556 kb
Host smart-6bd2e5d4-3ec0-4941-b651-2cf4379fe74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295641619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3295641619
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1933226927
Short name T605
Test name
Test status
Simulation time 27939755 ps
CPU time 0.98 seconds
Started Aug 10 07:23:23 PM PDT 24
Finished Aug 10 07:23:24 PM PDT 24
Peak memory 206808 kb
Host smart-2a92357a-b97c-4953-b805-f30691913769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933226927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1933226927
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2078278838
Short name T156
Test name
Test status
Simulation time 10227020 ps
CPU time 0.84 seconds
Started Aug 10 07:23:14 PM PDT 24
Finished Aug 10 07:23:15 PM PDT 24
Peak memory 215424 kb
Host smart-b4c563d8-fbe9-49d2-b22b-bdfe45839d36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078278838 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2078278838
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.187583789
Short name T131
Test name
Test status
Simulation time 35067367 ps
CPU time 1.1 seconds
Started Aug 10 07:23:10 PM PDT 24
Finished Aug 10 07:23:11 PM PDT 24
Peak memory 218576 kb
Host smart-c417c65c-f1f7-4042-81db-f629c5b026e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187583789 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.187583789
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3087611482
Short name T192
Test name
Test status
Simulation time 23980234 ps
CPU time 0.92 seconds
Started Aug 10 07:23:23 PM PDT 24
Finished Aug 10 07:23:24 PM PDT 24
Peak memory 218812 kb
Host smart-3fcf2626-ec0e-4c7f-b193-978908eb17ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087611482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3087611482
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3269714725
Short name T366
Test name
Test status
Simulation time 103980349 ps
CPU time 1.37 seconds
Started Aug 10 07:23:17 PM PDT 24
Finished Aug 10 07:23:19 PM PDT 24
Peak memory 217512 kb
Host smart-ba3cccae-de49-49fb-93f1-d76343dcd697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269714725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3269714725
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3159704083
Short name T677
Test name
Test status
Simulation time 21613348 ps
CPU time 1.1 seconds
Started Aug 10 07:23:13 PM PDT 24
Finished Aug 10 07:23:14 PM PDT 24
Peak memory 216012 kb
Host smart-6298624d-b6a2-4703-95aa-54b7eaa3db02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159704083 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3159704083
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3427769333
Short name T811
Test name
Test status
Simulation time 15591733 ps
CPU time 0.97 seconds
Started Aug 10 07:23:09 PM PDT 24
Finished Aug 10 07:23:10 PM PDT 24
Peak memory 215304 kb
Host smart-8b8c8f6c-1321-4bdc-8243-0f200f9d1b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427769333 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3427769333
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1594667732
Short name T762
Test name
Test status
Simulation time 44632538 ps
CPU time 1.12 seconds
Started Aug 10 07:23:17 PM PDT 24
Finished Aug 10 07:23:18 PM PDT 24
Peak memory 215280 kb
Host smart-6d00e65e-fb6c-49cd-ae34-0b038e51cb78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594667732 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1594667732
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3810326279
Short name T901
Test name
Test status
Simulation time 213899035839 ps
CPU time 1356.15 seconds
Started Aug 10 07:23:17 PM PDT 24
Finished Aug 10 07:45:53 PM PDT 24
Peak memory 224752 kb
Host smart-baf48455-ef70-498a-8da5-1881c866dc68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810326279 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3810326279
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.456581150
Short name T358
Test name
Test status
Simulation time 79176692 ps
CPU time 1.16 seconds
Started Aug 10 07:23:15 PM PDT 24
Finished Aug 10 07:23:16 PM PDT 24
Peak memory 220620 kb
Host smart-22b5671f-5da8-4878-948a-3ed9488ab389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456581150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.456581150
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1165057356
Short name T549
Test name
Test status
Simulation time 77544639 ps
CPU time 0.99 seconds
Started Aug 10 07:23:24 PM PDT 24
Finished Aug 10 07:23:25 PM PDT 24
Peak memory 206812 kb
Host smart-a81175ea-4039-49a4-b4b0-2d9b7cfc2dde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165057356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1165057356
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.4208058256
Short name T599
Test name
Test status
Simulation time 72775277 ps
CPU time 1.25 seconds
Started Aug 10 07:23:09 PM PDT 24
Finished Aug 10 07:23:10 PM PDT 24
Peak memory 219656 kb
Host smart-d52610f3-43e4-40d0-8eb1-934ef41fbd8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208058256 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.4208058256
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.14808941
Short name T458
Test name
Test status
Simulation time 26373076 ps
CPU time 0.98 seconds
Started Aug 10 07:23:15 PM PDT 24
Finished Aug 10 07:23:16 PM PDT 24
Peak memory 220072 kb
Host smart-93970401-57a4-4c4c-a15f-0f09a4121d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14808941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.14808941
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.566997898
Short name T389
Test name
Test status
Simulation time 43072534 ps
CPU time 1.06 seconds
Started Aug 10 07:23:17 PM PDT 24
Finished Aug 10 07:23:19 PM PDT 24
Peak memory 217324 kb
Host smart-ebe62e66-b678-4777-9cc4-34153c9ab68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566997898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.566997898
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.815664350
Short name T604
Test name
Test status
Simulation time 21897608 ps
CPU time 1.1 seconds
Started Aug 10 07:23:17 PM PDT 24
Finished Aug 10 07:23:18 PM PDT 24
Peak memory 215352 kb
Host smart-4dd44bd5-e242-4aa3-9d41-061f024965c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815664350 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.815664350
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3958982451
Short name T768
Test name
Test status
Simulation time 18600986 ps
CPU time 1.03 seconds
Started Aug 10 07:23:15 PM PDT 24
Finished Aug 10 07:23:17 PM PDT 24
Peak memory 215268 kb
Host smart-acba273e-a009-4798-823c-541db852e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958982451 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3958982451
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3382626483
Short name T57
Test name
Test status
Simulation time 1041148458 ps
CPU time 3.22 seconds
Started Aug 10 07:23:13 PM PDT 24
Finished Aug 10 07:23:16 PM PDT 24
Peak memory 217276 kb
Host smart-d483dedc-388d-453a-b29c-cffffc531cda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382626483 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3382626483
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3411272883
Short name T232
Test name
Test status
Simulation time 86888508279 ps
CPU time 910.95 seconds
Started Aug 10 07:23:13 PM PDT 24
Finished Aug 10 07:38:25 PM PDT 24
Peak memory 223532 kb
Host smart-cf7e343a-045f-4954-8b44-202d9c24e446
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411272883 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3411272883
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1039802178
Short name T185
Test name
Test status
Simulation time 78962270 ps
CPU time 1.17 seconds
Started Aug 10 07:21:45 PM PDT 24
Finished Aug 10 07:21:46 PM PDT 24
Peak memory 219304 kb
Host smart-07582d20-a468-47fa-8bc4-e909580e9046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039802178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1039802178
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3450522661
Short name T575
Test name
Test status
Simulation time 29704213 ps
CPU time 0.96 seconds
Started Aug 10 07:21:46 PM PDT 24
Finished Aug 10 07:21:47 PM PDT 24
Peak memory 206964 kb
Host smart-77914c75-f871-48d5-a167-eee7f441f754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450522661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3450522661
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.500999874
Short name T651
Test name
Test status
Simulation time 90846228 ps
CPU time 1.24 seconds
Started Aug 10 07:21:49 PM PDT 24
Finished Aug 10 07:21:51 PM PDT 24
Peak memory 219684 kb
Host smart-691759a6-44c4-4d7c-bd98-503fde1da7e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500999874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.500999874
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2592842524
Short name T602
Test name
Test status
Simulation time 28172789 ps
CPU time 0.86 seconds
Started Aug 10 07:21:50 PM PDT 24
Finished Aug 10 07:21:51 PM PDT 24
Peak memory 218492 kb
Host smart-8c056331-5487-4d28-ba3e-cfe71efcb0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592842524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2592842524
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.936787921
Short name T875
Test name
Test status
Simulation time 68933673 ps
CPU time 1.42 seconds
Started Aug 10 07:21:50 PM PDT 24
Finished Aug 10 07:21:51 PM PDT 24
Peak memory 217492 kb
Host smart-2977a73b-146b-4753-b01e-cee81d0206aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936787921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.936787921
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.530571769
Short name T946
Test name
Test status
Simulation time 36421613 ps
CPU time 0.88 seconds
Started Aug 10 07:21:47 PM PDT 24
Finished Aug 10 07:21:48 PM PDT 24
Peak memory 215324 kb
Host smart-3c615147-da76-421e-8c13-b60065dadcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530571769 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.530571769
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2213868763
Short name T732
Test name
Test status
Simulation time 34710515 ps
CPU time 0.93 seconds
Started Aug 10 07:21:50 PM PDT 24
Finished Aug 10 07:21:52 PM PDT 24
Peak memory 207112 kb
Host smart-a39bad9d-43bd-4500-a3af-0e671bd0f5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213868763 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2213868763
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3630896128
Short name T798
Test name
Test status
Simulation time 17218347 ps
CPU time 0.99 seconds
Started Aug 10 07:21:47 PM PDT 24
Finished Aug 10 07:21:48 PM PDT 24
Peak memory 215328 kb
Host smart-42f88cb1-97ae-4f6b-9719-f906170f1101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630896128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3630896128
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.687223468
Short name T98
Test name
Test status
Simulation time 424491774 ps
CPU time 8.23 seconds
Started Aug 10 07:21:47 PM PDT 24
Finished Aug 10 07:21:56 PM PDT 24
Peak memory 218528 kb
Host smart-a02376eb-0c42-4b89-b7b5-982147bd8a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687223468 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.687223468
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.969666021
Short name T245
Test name
Test status
Simulation time 175129504187 ps
CPU time 749.79 seconds
Started Aug 10 07:21:49 PM PDT 24
Finished Aug 10 07:34:19 PM PDT 24
Peak memory 223704 kb
Host smart-783dc8e4-54de-4348-af60-36210f78feb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969666021 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.969666021
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2367765116
Short name T692
Test name
Test status
Simulation time 38190986 ps
CPU time 1.24 seconds
Started Aug 10 07:23:15 PM PDT 24
Finished Aug 10 07:23:16 PM PDT 24
Peak memory 219588 kb
Host smart-e892fbe6-361e-4a36-8e77-7e9c2a091ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367765116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2367765116
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.3772802532
Short name T394
Test name
Test status
Simulation time 47879333 ps
CPU time 1.02 seconds
Started Aug 10 07:23:17 PM PDT 24
Finished Aug 10 07:23:18 PM PDT 24
Peak memory 218972 kb
Host smart-21cad777-c2d2-4295-a87e-7643e20ff0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772802532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3772802532
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2767189199
Short name T464
Test name
Test status
Simulation time 94009073 ps
CPU time 1.64 seconds
Started Aug 10 07:23:17 PM PDT 24
Finished Aug 10 07:23:19 PM PDT 24
Peak memory 218916 kb
Host smart-2e3ad834-bba7-4e3c-bd50-03253316faf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767189199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2767189199
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.4147602851
Short name T502
Test name
Test status
Simulation time 27008495 ps
CPU time 1.41 seconds
Started Aug 10 07:23:23 PM PDT 24
Finished Aug 10 07:23:25 PM PDT 24
Peak memory 219756 kb
Host smart-f0d55f84-9eae-4185-b110-aa85340df219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147602851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.4147602851
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.214471712
Short name T136
Test name
Test status
Simulation time 139067574 ps
CPU time 1.01 seconds
Started Aug 10 07:23:24 PM PDT 24
Finished Aug 10 07:23:25 PM PDT 24
Peak memory 219056 kb
Host smart-6da9e580-1665-4af9-84ee-f7f9405e35ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214471712 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.214471712
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1749690774
Short name T678
Test name
Test status
Simulation time 225140720 ps
CPU time 3.18 seconds
Started Aug 10 07:23:16 PM PDT 24
Finished Aug 10 07:23:19 PM PDT 24
Peak memory 219892 kb
Host smart-f3df2101-faaf-4908-9bf0-88cd01a0efc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749690774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1749690774
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1110017229
Short name T820
Test name
Test status
Simulation time 27174631 ps
CPU time 1.15 seconds
Started Aug 10 07:23:15 PM PDT 24
Finished Aug 10 07:23:16 PM PDT 24
Peak memory 220776 kb
Host smart-fe096e46-f189-4037-b41e-60690ede2d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110017229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1110017229
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.1804532283
Short name T880
Test name
Test status
Simulation time 50040975 ps
CPU time 1.13 seconds
Started Aug 10 07:23:18 PM PDT 24
Finished Aug 10 07:23:19 PM PDT 24
Peak memory 229884 kb
Host smart-054b6aab-ea2a-447c-a1d2-e0c52b6b373c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804532283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1804532283
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3626817022
Short name T527
Test name
Test status
Simulation time 117803069 ps
CPU time 1.1 seconds
Started Aug 10 07:23:24 PM PDT 24
Finished Aug 10 07:23:25 PM PDT 24
Peak memory 217324 kb
Host smart-9038f2ab-0b04-4e08-9d47-9a41a9ac93e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626817022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3626817022
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.511990136
Short name T227
Test name
Test status
Simulation time 48253299 ps
CPU time 1.31 seconds
Started Aug 10 07:23:24 PM PDT 24
Finished Aug 10 07:23:26 PM PDT 24
Peak memory 218464 kb
Host smart-564f698b-1e13-45ad-96ff-f484e2e0f10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511990136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.511990136
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.3621395331
Short name T217
Test name
Test status
Simulation time 21659019 ps
CPU time 1.1 seconds
Started Aug 10 07:23:23 PM PDT 24
Finished Aug 10 07:23:24 PM PDT 24
Peak memory 220216 kb
Host smart-1fe7f3b1-d810-46b6-bbe9-dd60cc49068b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621395331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3621395331
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2852150802
Short name T254
Test name
Test status
Simulation time 31148658 ps
CPU time 1.27 seconds
Started Aug 10 07:23:17 PM PDT 24
Finished Aug 10 07:23:19 PM PDT 24
Peak memory 218388 kb
Host smart-b69f8eb5-5547-44d9-87c8-57c2a1c4fd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852150802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2852150802
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.307769465
Short name T158
Test name
Test status
Simulation time 19098350 ps
CPU time 1.18 seconds
Started Aug 10 07:23:20 PM PDT 24
Finished Aug 10 07:23:21 PM PDT 24
Peak memory 224176 kb
Host smart-9d45bb29-ca3e-4193-8cf5-bbcdf36f6164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307769465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.307769465
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3680029079
Short name T781
Test name
Test status
Simulation time 109662983 ps
CPU time 1.52 seconds
Started Aug 10 07:23:26 PM PDT 24
Finished Aug 10 07:23:28 PM PDT 24
Peak memory 217352 kb
Host smart-4eae314f-c704-4443-97f8-48e489aa73a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680029079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3680029079
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2757288816
Short name T80
Test name
Test status
Simulation time 42439671 ps
CPU time 1.21 seconds
Started Aug 10 07:23:25 PM PDT 24
Finished Aug 10 07:23:26 PM PDT 24
Peak memory 218400 kb
Host smart-a3c2010a-81d4-4552-9488-bbcf927aba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757288816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2757288816
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.1800400425
Short name T963
Test name
Test status
Simulation time 23997969 ps
CPU time 0.93 seconds
Started Aug 10 07:23:20 PM PDT 24
Finished Aug 10 07:23:21 PM PDT 24
Peak memory 218800 kb
Host smart-9fa62f68-b33b-46b0-9635-72a37ee9aed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800400425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1800400425
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1928454603
Short name T12
Test name
Test status
Simulation time 40165594 ps
CPU time 1.42 seconds
Started Aug 10 07:23:20 PM PDT 24
Finished Aug 10 07:23:22 PM PDT 24
Peak memory 218700 kb
Host smart-7fbe4600-df02-4320-b4de-6fc2c5774e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928454603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1928454603
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.401503642
Short name T982
Test name
Test status
Simulation time 86675720 ps
CPU time 1.16 seconds
Started Aug 10 07:23:23 PM PDT 24
Finished Aug 10 07:23:24 PM PDT 24
Peak memory 220624 kb
Host smart-11e8ae77-8376-4325-9435-4290ac60bf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401503642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.401503642
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.753909154
Short name T221
Test name
Test status
Simulation time 24716084 ps
CPU time 0.96 seconds
Started Aug 10 07:23:23 PM PDT 24
Finished Aug 10 07:23:24 PM PDT 24
Peak memory 218788 kb
Host smart-ef666242-936b-4504-bd2a-9c292fd884a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753909154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.753909154
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2446179394
Short name T654
Test name
Test status
Simulation time 44748263 ps
CPU time 1.18 seconds
Started Aug 10 07:23:22 PM PDT 24
Finished Aug 10 07:23:23 PM PDT 24
Peak memory 218800 kb
Host smart-0ba8110c-f173-4878-81c1-d65a74068957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446179394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2446179394
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3157253470
Short name T191
Test name
Test status
Simulation time 74851466 ps
CPU time 1.15 seconds
Started Aug 10 07:23:24 PM PDT 24
Finished Aug 10 07:23:25 PM PDT 24
Peak memory 220536 kb
Host smart-43f23dc8-2020-4cfa-a534-572b2fa9d47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157253470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3157253470
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.2379249434
Short name T927
Test name
Test status
Simulation time 54943380 ps
CPU time 1.32 seconds
Started Aug 10 07:23:22 PM PDT 24
Finished Aug 10 07:23:24 PM PDT 24
Peak memory 225896 kb
Host smart-93754e29-2150-4ad8-ba41-30da62afd6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379249434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2379249434
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1809363286
Short name T331
Test name
Test status
Simulation time 90143118 ps
CPU time 1.25 seconds
Started Aug 10 07:23:25 PM PDT 24
Finished Aug 10 07:23:26 PM PDT 24
Peak memory 217244 kb
Host smart-b4e9adde-1521-45c0-b5b9-8aafa05201f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809363286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1809363286
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3088483219
Short name T84
Test name
Test status
Simulation time 23974282 ps
CPU time 1.17 seconds
Started Aug 10 07:23:24 PM PDT 24
Finished Aug 10 07:23:25 PM PDT 24
Peak memory 219800 kb
Host smart-b326dddb-e73e-43c5-ae99-f92bcc338c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088483219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3088483219
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.591496376
Short name T141
Test name
Test status
Simulation time 31137243 ps
CPU time 1.04 seconds
Started Aug 10 07:23:22 PM PDT 24
Finished Aug 10 07:23:23 PM PDT 24
Peak memory 220008 kb
Host smart-0a0a67a2-3b56-4524-ac45-b62a93686347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591496376 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.591496376
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.379918834
Short name T520
Test name
Test status
Simulation time 50335581 ps
CPU time 1.44 seconds
Started Aug 10 07:23:23 PM PDT 24
Finished Aug 10 07:23:25 PM PDT 24
Peak memory 219100 kb
Host smart-f034c6aa-51a7-4db0-bda8-782fadaa3978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379918834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.379918834
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2787366545
Short name T676
Test name
Test status
Simulation time 31295032 ps
CPU time 1.35 seconds
Started Aug 10 07:23:23 PM PDT 24
Finished Aug 10 07:23:24 PM PDT 24
Peak memory 215592 kb
Host smart-16caf546-721d-419f-8d40-b8dce2c86047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787366545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2787366545
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1217044545
Short name T774
Test name
Test status
Simulation time 21463810 ps
CPU time 0.98 seconds
Started Aug 10 07:23:26 PM PDT 24
Finished Aug 10 07:23:27 PM PDT 24
Peak memory 218648 kb
Host smart-2eda098a-bbf3-436d-a6e4-2355303b1135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217044545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1217044545
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3067343518
Short name T633
Test name
Test status
Simulation time 35486987 ps
CPU time 1.45 seconds
Started Aug 10 07:23:21 PM PDT 24
Finished Aug 10 07:23:23 PM PDT 24
Peak memory 217488 kb
Host smart-4ab4f912-7123-4599-bad1-5f27e3b9b7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067343518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3067343518
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2735890918
Short name T135
Test name
Test status
Simulation time 129010752 ps
CPU time 1.33 seconds
Started Aug 10 07:21:50 PM PDT 24
Finished Aug 10 07:21:51 PM PDT 24
Peak memory 218948 kb
Host smart-de9c203b-35a7-4729-bc19-812ee9ba44f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735890918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2735890918
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.204001771
Short name T832
Test name
Test status
Simulation time 63561416 ps
CPU time 0.9 seconds
Started Aug 10 07:21:47 PM PDT 24
Finished Aug 10 07:21:48 PM PDT 24
Peak memory 206804 kb
Host smart-d1e279ea-137f-4557-be90-68ea91af6f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204001771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.204001771
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1470023670
Short name T742
Test name
Test status
Simulation time 26402780 ps
CPU time 0.84 seconds
Started Aug 10 07:21:49 PM PDT 24
Finished Aug 10 07:21:50 PM PDT 24
Peak memory 215392 kb
Host smart-140f1970-eabc-4c84-875b-9040cc364b16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470023670 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1470023670
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1587086630
Short name T506
Test name
Test status
Simulation time 19237623 ps
CPU time 1 seconds
Started Aug 10 07:21:48 PM PDT 24
Finished Aug 10 07:21:49 PM PDT 24
Peak memory 219848 kb
Host smart-643a024b-7f57-4b93-88b9-df96e36abd63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587086630 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1587086630
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_genbits.961777359
Short name T988
Test name
Test status
Simulation time 66282504 ps
CPU time 1.34 seconds
Started Aug 10 07:21:50 PM PDT 24
Finished Aug 10 07:21:51 PM PDT 24
Peak memory 218824 kb
Host smart-b54c0cfa-16b6-4b57-bd15-9c094b58c257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961777359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.961777359
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.863269428
Short name T375
Test name
Test status
Simulation time 36644220 ps
CPU time 0.89 seconds
Started Aug 10 07:21:47 PM PDT 24
Finished Aug 10 07:21:48 PM PDT 24
Peak memory 215340 kb
Host smart-dc7ec87a-594f-4f3e-ae5f-270fc28946f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863269428 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.863269428
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1630927928
Short name T27
Test name
Test status
Simulation time 15081754 ps
CPU time 1 seconds
Started Aug 10 07:21:49 PM PDT 24
Finished Aug 10 07:21:50 PM PDT 24
Peak memory 207172 kb
Host smart-661d4358-918d-4518-abb2-b5c8bd8a151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630927928 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1630927928
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.372754015
Short name T97
Test name
Test status
Simulation time 38308200 ps
CPU time 0.95 seconds
Started Aug 10 07:21:46 PM PDT 24
Finished Aug 10 07:21:47 PM PDT 24
Peak memory 215320 kb
Host smart-a815d263-801b-415b-9df6-a71100ab6cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372754015 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.372754015
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2306221049
Short name T378
Test name
Test status
Simulation time 169832799 ps
CPU time 3.85 seconds
Started Aug 10 07:21:49 PM PDT 24
Finished Aug 10 07:21:53 PM PDT 24
Peak memory 217128 kb
Host smart-435f4400-a3c1-4348-8efc-53b0689102f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306221049 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2306221049
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.4070434889
Short name T241
Test name
Test status
Simulation time 625141676329 ps
CPU time 915.47 seconds
Started Aug 10 07:21:50 PM PDT 24
Finished Aug 10 07:37:05 PM PDT 24
Peak memory 228780 kb
Host smart-e4058bee-49f5-4927-a6cf-2491860b7184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070434889 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.4070434889
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.3459296765
Short name T357
Test name
Test status
Simulation time 27379144 ps
CPU time 1.29 seconds
Started Aug 10 07:23:21 PM PDT 24
Finished Aug 10 07:23:23 PM PDT 24
Peak memory 219356 kb
Host smart-9f7b5bb3-982f-4652-9831-182a6da2bd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459296765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.3459296765
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1537108884
Short name T159
Test name
Test status
Simulation time 34398760 ps
CPU time 0.95 seconds
Started Aug 10 07:23:22 PM PDT 24
Finished Aug 10 07:23:23 PM PDT 24
Peak memory 218652 kb
Host smart-a8a7be61-f868-4f9b-9cc8-8c6c9a232424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537108884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1537108884
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.252009531
Short name T607
Test name
Test status
Simulation time 123608934 ps
CPU time 1.26 seconds
Started Aug 10 07:23:21 PM PDT 24
Finished Aug 10 07:23:22 PM PDT 24
Peak memory 219968 kb
Host smart-67b9ecd1-a4a6-4d6c-aa2b-9c333771c057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252009531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.252009531
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.3654996795
Short name T789
Test name
Test status
Simulation time 26005832 ps
CPU time 1.23 seconds
Started Aug 10 07:23:24 PM PDT 24
Finished Aug 10 07:23:26 PM PDT 24
Peak memory 220784 kb
Host smart-d59c312c-f336-4433-b01f-88cda71d964a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654996795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.3654996795
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2380748770
Short name T186
Test name
Test status
Simulation time 20350711 ps
CPU time 1.04 seconds
Started Aug 10 07:23:20 PM PDT 24
Finished Aug 10 07:23:21 PM PDT 24
Peak memory 218676 kb
Host smart-db7cf7f5-d71c-4050-8c66-01973d6e51ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380748770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2380748770
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2257257509
Short name T439
Test name
Test status
Simulation time 200687394 ps
CPU time 1.12 seconds
Started Aug 10 07:23:26 PM PDT 24
Finished Aug 10 07:23:27 PM PDT 24
Peak memory 217340 kb
Host smart-01818e27-f0f9-4608-868a-1470def4f9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257257509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2257257509
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1193885636
Short name T1
Test name
Test status
Simulation time 91054352 ps
CPU time 1.16 seconds
Started Aug 10 07:23:26 PM PDT 24
Finished Aug 10 07:23:27 PM PDT 24
Peak memory 218888 kb
Host smart-7c42ece3-52f7-4fb4-a008-07b7a8f76d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193885636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1193885636
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1113759322
Short name T381
Test name
Test status
Simulation time 23249519 ps
CPU time 0.94 seconds
Started Aug 10 07:23:23 PM PDT 24
Finished Aug 10 07:23:24 PM PDT 24
Peak memory 218936 kb
Host smart-970158ec-21e6-4e1c-853d-8b089a3c8d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113759322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1113759322
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3567439153
Short name T545
Test name
Test status
Simulation time 80829224 ps
CPU time 1.07 seconds
Started Aug 10 07:23:22 PM PDT 24
Finished Aug 10 07:23:24 PM PDT 24
Peak memory 217204 kb
Host smart-a0694be7-79da-4449-add3-822a30bd2975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567439153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3567439153
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.717719647
Short name T932
Test name
Test status
Simulation time 42885978 ps
CPU time 1.18 seconds
Started Aug 10 07:23:19 PM PDT 24
Finished Aug 10 07:23:21 PM PDT 24
Peak memory 219512 kb
Host smart-64b9a96d-c67b-4aa0-a3de-85170c012adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717719647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.717719647
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.4266942673
Short name T161
Test name
Test status
Simulation time 23673818 ps
CPU time 1.05 seconds
Started Aug 10 07:23:22 PM PDT 24
Finished Aug 10 07:23:24 PM PDT 24
Peak memory 224168 kb
Host smart-0ed5dd25-66aa-4df4-b3d6-3026a0ab42e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266942673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.4266942673
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1666489218
Short name T543
Test name
Test status
Simulation time 75110314 ps
CPU time 2.79 seconds
Started Aug 10 07:23:20 PM PDT 24
Finished Aug 10 07:23:23 PM PDT 24
Peak memory 217424 kb
Host smart-4158f5d7-0171-41d2-a08f-cf15cd6c60fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666489218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1666489218
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.717744880
Short name T432
Test name
Test status
Simulation time 42751958 ps
CPU time 1.17 seconds
Started Aug 10 07:23:26 PM PDT 24
Finished Aug 10 07:23:27 PM PDT 24
Peak memory 219648 kb
Host smart-81de4c4d-a1a5-4822-91b4-c72e3e188ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717744880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.717744880
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3387276303
Short name T130
Test name
Test status
Simulation time 55865161 ps
CPU time 1.13 seconds
Started Aug 10 07:23:22 PM PDT 24
Finished Aug 10 07:23:23 PM PDT 24
Peak memory 229876 kb
Host smart-bd434f92-7ab5-46ca-8020-4166b3c646dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387276303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3387276303
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1484143787
Short name T838
Test name
Test status
Simulation time 47896416 ps
CPU time 1.41 seconds
Started Aug 10 07:23:22 PM PDT 24
Finished Aug 10 07:23:23 PM PDT 24
Peak memory 218836 kb
Host smart-951368d7-8ac9-424d-bdcf-d5daebb79fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484143787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1484143787
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.2248535710
Short name T816
Test name
Test status
Simulation time 24478555 ps
CPU time 1.22 seconds
Started Aug 10 07:23:21 PM PDT 24
Finished Aug 10 07:23:23 PM PDT 24
Peak memory 218460 kb
Host smart-df476a05-c4b0-4d4a-b5f6-ff4fdbeb7e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248535710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2248535710
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_genbits.2891692991
Short name T448
Test name
Test status
Simulation time 187687191 ps
CPU time 1.19 seconds
Started Aug 10 07:23:21 PM PDT 24
Finished Aug 10 07:23:22 PM PDT 24
Peak memory 217244 kb
Host smart-6343463e-317f-4e4d-916c-bc582f402f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891692991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2891692991
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1504047392
Short name T714
Test name
Test status
Simulation time 53594934 ps
CPU time 1.26 seconds
Started Aug 10 07:23:26 PM PDT 24
Finished Aug 10 07:23:27 PM PDT 24
Peak memory 220160 kb
Host smart-f16df5ff-43a3-4304-a8d9-23e7079188cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504047392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1504047392
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.3877681866
Short name T152
Test name
Test status
Simulation time 45622677 ps
CPU time 1.24 seconds
Started Aug 10 07:23:22 PM PDT 24
Finished Aug 10 07:23:24 PM PDT 24
Peak memory 225988 kb
Host smart-4b6b87f1-98a7-4ce6-b898-4354ca1a98f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877681866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3877681866
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1097933548
Short name T916
Test name
Test status
Simulation time 40721646 ps
CPU time 1.15 seconds
Started Aug 10 07:23:25 PM PDT 24
Finished Aug 10 07:23:26 PM PDT 24
Peak memory 218564 kb
Host smart-b57606f3-d4ec-4c88-bbb4-de59d8563ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097933548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1097933548
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2889934976
Short name T125
Test name
Test status
Simulation time 55053441 ps
CPU time 1.34 seconds
Started Aug 10 07:23:26 PM PDT 24
Finished Aug 10 07:23:28 PM PDT 24
Peak memory 215508 kb
Host smart-2f228ed9-9f13-4918-bb65-418d0f0a93a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889934976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2889934976
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.2134018589
Short name T554
Test name
Test status
Simulation time 22088673 ps
CPU time 0.95 seconds
Started Aug 10 07:23:31 PM PDT 24
Finished Aug 10 07:23:32 PM PDT 24
Peak memory 218744 kb
Host smart-0e3e512e-8bb5-4998-b666-4472ea849107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134018589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2134018589
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3922051373
Short name T88
Test name
Test status
Simulation time 61371004 ps
CPU time 1.77 seconds
Started Aug 10 07:23:25 PM PDT 24
Finished Aug 10 07:23:27 PM PDT 24
Peak memory 218448 kb
Host smart-fdd1ac7d-a294-42a6-bdd7-859671efcaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922051373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3922051373
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.846313207
Short name T882
Test name
Test status
Simulation time 65962962 ps
CPU time 1.11 seconds
Started Aug 10 07:23:34 PM PDT 24
Finished Aug 10 07:23:35 PM PDT 24
Peak memory 218712 kb
Host smart-e48fc449-f1c8-4d03-8f86-f4d375b1dc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846313207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.846313207
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.2341634395
Short name T587
Test name
Test status
Simulation time 25088076 ps
CPU time 1.19 seconds
Started Aug 10 07:23:38 PM PDT 24
Finished Aug 10 07:23:39 PM PDT 24
Peak memory 220852 kb
Host smart-f3688fbb-b4f4-4a1b-aea6-5dd86aad167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341634395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2341634395
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3440547644
Short name T253
Test name
Test status
Simulation time 39699186 ps
CPU time 1.32 seconds
Started Aug 10 07:23:33 PM PDT 24
Finished Aug 10 07:23:34 PM PDT 24
Peak memory 218676 kb
Host smart-3cc66e90-9c13-4009-b6f3-99c348314f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440547644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3440547644
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1504267416
Short name T172
Test name
Test status
Simulation time 25455550 ps
CPU time 1.17 seconds
Started Aug 10 07:23:31 PM PDT 24
Finished Aug 10 07:23:32 PM PDT 24
Peak memory 219592 kb
Host smart-b2005297-2584-4074-b7c9-f449703eb650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504267416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1504267416
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2395790976
Short name T146
Test name
Test status
Simulation time 29266115 ps
CPU time 1.29 seconds
Started Aug 10 07:23:34 PM PDT 24
Finished Aug 10 07:23:36 PM PDT 24
Peak memory 220876 kb
Host smart-90dd0ba7-e354-4e3b-a61a-5982603cb6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395790976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2395790976
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1029991643
Short name T887
Test name
Test status
Simulation time 750860931 ps
CPU time 4.64 seconds
Started Aug 10 07:23:38 PM PDT 24
Finished Aug 10 07:23:43 PM PDT 24
Peak memory 218652 kb
Host smart-bce9e071-d8c6-42b8-8493-ebca620374a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029991643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1029991643
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2852763848
Short name T943
Test name
Test status
Simulation time 47026078 ps
CPU time 1.16 seconds
Started Aug 10 07:21:48 PM PDT 24
Finished Aug 10 07:21:49 PM PDT 24
Peak memory 218832 kb
Host smart-337f1649-67dd-4108-80e7-4fdca3956504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852763848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2852763848
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1936778790
Short name T404
Test name
Test status
Simulation time 68906451 ps
CPU time 0.89 seconds
Started Aug 10 07:21:47 PM PDT 24
Finished Aug 10 07:21:48 PM PDT 24
Peak memory 206624 kb
Host smart-ea876d94-63cd-4d18-8f77-126abba45e5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936778790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1936778790
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.4192419454
Short name T792
Test name
Test status
Simulation time 13752448 ps
CPU time 0.92 seconds
Started Aug 10 07:21:50 PM PDT 24
Finished Aug 10 07:21:51 PM PDT 24
Peak memory 216392 kb
Host smart-c6274504-eba3-49bc-a506-af6307d13cd6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192419454 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4192419454
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.646448884
Short name T297
Test name
Test status
Simulation time 93098051 ps
CPU time 1.03 seconds
Started Aug 10 07:21:48 PM PDT 24
Finished Aug 10 07:21:49 PM PDT 24
Peak memory 218640 kb
Host smart-a62cf271-38a0-47fa-b7f0-3cb625ce6791
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646448884 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.646448884
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3493520967
Short name T754
Test name
Test status
Simulation time 35658577 ps
CPU time 1.06 seconds
Started Aug 10 07:21:48 PM PDT 24
Finished Aug 10 07:21:49 PM PDT 24
Peak memory 217780 kb
Host smart-eb141ae6-920d-4283-9380-73a8a3b234ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493520967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3493520967
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2837300391
Short name T800
Test name
Test status
Simulation time 24331761 ps
CPU time 1.13 seconds
Started Aug 10 07:21:48 PM PDT 24
Finished Aug 10 07:21:49 PM PDT 24
Peak memory 217364 kb
Host smart-5abe5980-147c-4da6-8cde-5841cd825265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837300391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2837300391
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3235009140
Short name T32
Test name
Test status
Simulation time 21522080 ps
CPU time 1.1 seconds
Started Aug 10 07:21:46 PM PDT 24
Finished Aug 10 07:21:47 PM PDT 24
Peak memory 215452 kb
Host smart-6c24ad6a-bb0d-4bd0-b9a7-cab2e10e6cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235009140 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3235009140
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3726112851
Short name T28
Test name
Test status
Simulation time 49386402 ps
CPU time 0.92 seconds
Started Aug 10 07:21:50 PM PDT 24
Finished Aug 10 07:21:51 PM PDT 24
Peak memory 207004 kb
Host smart-f5e20fc1-622b-4c8a-b14e-69a894e35fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726112851 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3726112851
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3583663277
Short name T801
Test name
Test status
Simulation time 42041479 ps
CPU time 0.89 seconds
Started Aug 10 07:21:47 PM PDT 24
Finished Aug 10 07:21:48 PM PDT 24
Peak memory 215264 kb
Host smart-e896a7df-c9eb-4755-8093-775ce0ef1a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583663277 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3583663277
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1618592077
Short name T812
Test name
Test status
Simulation time 333542403 ps
CPU time 3.16 seconds
Started Aug 10 07:21:50 PM PDT 24
Finished Aug 10 07:21:53 PM PDT 24
Peak memory 217176 kb
Host smart-a264a7c2-6ea1-4662-9c41-6c96d097d52a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618592077 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1618592077
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.776061690
Short name T504
Test name
Test status
Simulation time 292107267106 ps
CPU time 1215.89 seconds
Started Aug 10 07:21:50 PM PDT 24
Finished Aug 10 07:42:06 PM PDT 24
Peak memory 223472 kb
Host smart-7153f894-9956-4bd5-89de-5665973ab9a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776061690 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.776061690
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.1449719114
Short name T118
Test name
Test status
Simulation time 109334411 ps
CPU time 1.26 seconds
Started Aug 10 07:23:31 PM PDT 24
Finished Aug 10 07:23:33 PM PDT 24
Peak memory 218644 kb
Host smart-6e789eb3-0546-4772-9396-776ce60901ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449719114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1449719114
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.16459992
Short name T970
Test name
Test status
Simulation time 80686613 ps
CPU time 1.15 seconds
Started Aug 10 07:23:36 PM PDT 24
Finished Aug 10 07:23:38 PM PDT 24
Peak memory 225652 kb
Host smart-1bf09331-782d-4c8f-8a25-874d1bbc9c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16459992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.16459992
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2838721696
Short name T777
Test name
Test status
Simulation time 42148364 ps
CPU time 1.51 seconds
Started Aug 10 07:23:31 PM PDT 24
Finished Aug 10 07:23:33 PM PDT 24
Peak memory 217364 kb
Host smart-ee4d05b8-d4a2-46d1-9375-aa62fa951141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838721696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2838721696
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.701445242
Short name T902
Test name
Test status
Simulation time 74988361 ps
CPU time 1.18 seconds
Started Aug 10 07:23:33 PM PDT 24
Finished Aug 10 07:23:35 PM PDT 24
Peak memory 220716 kb
Host smart-3b70781c-3083-4c73-a1a9-034d363c0e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701445242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.701445242
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.1196711504
Short name T993
Test name
Test status
Simulation time 25071065 ps
CPU time 0.92 seconds
Started Aug 10 07:23:38 PM PDT 24
Finished Aug 10 07:23:39 PM PDT 24
Peak memory 218824 kb
Host smart-325f4afa-6b34-447b-8ad0-9b4b42f5e075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196711504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1196711504
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.4140082346
Short name T934
Test name
Test status
Simulation time 163113941 ps
CPU time 2.54 seconds
Started Aug 10 07:23:30 PM PDT 24
Finished Aug 10 07:23:33 PM PDT 24
Peak memory 215356 kb
Host smart-9e2cfe0b-787a-4977-9fc4-b4077f12e62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140082346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.4140082346
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.475146969
Short name T649
Test name
Test status
Simulation time 39811001 ps
CPU time 1.14 seconds
Started Aug 10 07:23:34 PM PDT 24
Finished Aug 10 07:23:36 PM PDT 24
Peak memory 219628 kb
Host smart-8f192c77-3eee-4022-ba27-778d69b34fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475146969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.475146969
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.4139630479
Short name T181
Test name
Test status
Simulation time 31538693 ps
CPU time 0.9 seconds
Started Aug 10 07:23:31 PM PDT 24
Finished Aug 10 07:23:32 PM PDT 24
Peak memory 218552 kb
Host smart-50e510ea-a7be-4c07-8748-8b277f6cf567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139630479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.4139630479
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.966460031
Short name T745
Test name
Test status
Simulation time 36385638 ps
CPU time 1.56 seconds
Started Aug 10 07:23:36 PM PDT 24
Finished Aug 10 07:23:38 PM PDT 24
Peak memory 218736 kb
Host smart-c0bdd7e5-baf1-476d-90c3-32f5e7174de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966460031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.966460031
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.771586260
Short name T171
Test name
Test status
Simulation time 41700632 ps
CPU time 1.22 seconds
Started Aug 10 07:23:39 PM PDT 24
Finished Aug 10 07:23:40 PM PDT 24
Peak memory 215596 kb
Host smart-e3c9fedd-5eaa-49a0-8442-8cba713c603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771586260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.771586260
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3211525040
Short name T923
Test name
Test status
Simulation time 23019025 ps
CPU time 0.87 seconds
Started Aug 10 07:23:38 PM PDT 24
Finished Aug 10 07:23:38 PM PDT 24
Peak memory 218764 kb
Host smart-53f3bac1-6f5a-4792-a038-c5fc532aba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211525040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3211525040
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1703795500
Short name T954
Test name
Test status
Simulation time 53494254 ps
CPU time 1.65 seconds
Started Aug 10 07:23:40 PM PDT 24
Finished Aug 10 07:23:42 PM PDT 24
Peak memory 218376 kb
Host smart-f1df57e9-821d-4232-a06e-02eb16a95d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703795500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1703795500
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2008625199
Short name T264
Test name
Test status
Simulation time 105684486 ps
CPU time 1.2 seconds
Started Aug 10 07:23:38 PM PDT 24
Finished Aug 10 07:23:39 PM PDT 24
Peak memory 219684 kb
Host smart-c1eb3a64-56da-48ea-98a0-f98565ea51f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008625199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2008625199
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.783062510
Short name T197
Test name
Test status
Simulation time 62161016 ps
CPU time 0.97 seconds
Started Aug 10 07:23:32 PM PDT 24
Finished Aug 10 07:23:33 PM PDT 24
Peak memory 229484 kb
Host smart-de6b10bd-1ea2-4c8a-a6cb-1f1bf7154d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783062510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.783062510
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1012830424
Short name T495
Test name
Test status
Simulation time 40916094 ps
CPU time 1.4 seconds
Started Aug 10 07:23:34 PM PDT 24
Finished Aug 10 07:23:35 PM PDT 24
Peak memory 218684 kb
Host smart-f15645f3-88a2-4ae8-bba6-aaa6191950c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012830424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1012830424
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.291088554
Short name T106
Test name
Test status
Simulation time 25614373 ps
CPU time 1.29 seconds
Started Aug 10 07:23:34 PM PDT 24
Finished Aug 10 07:23:36 PM PDT 24
Peak memory 220400 kb
Host smart-54787ad6-44ae-451a-986f-9146bd59f94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291088554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.291088554
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.4090168935
Short name T199
Test name
Test status
Simulation time 56175643 ps
CPU time 0.98 seconds
Started Aug 10 07:23:37 PM PDT 24
Finished Aug 10 07:23:38 PM PDT 24
Peak memory 218556 kb
Host smart-627f7627-d8e2-4e1d-aacf-68829aa7a09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090168935 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.4090168935
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.815547844
Short name T974
Test name
Test status
Simulation time 97499850 ps
CPU time 1.47 seconds
Started Aug 10 07:23:34 PM PDT 24
Finished Aug 10 07:23:36 PM PDT 24
Peak memory 218688 kb
Host smart-82862055-6652-4619-a9c1-017694b95290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815547844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.815547844
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1980045998
Short name T521
Test name
Test status
Simulation time 45416774 ps
CPU time 1.16 seconds
Started Aug 10 07:23:32 PM PDT 24
Finished Aug 10 07:23:33 PM PDT 24
Peak memory 219584 kb
Host smart-964d5845-90e6-4f8e-9ff0-6a4c0cdc3053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980045998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1980045998
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.2919264456
Short name T213
Test name
Test status
Simulation time 23211057 ps
CPU time 1.01 seconds
Started Aug 10 07:23:36 PM PDT 24
Finished Aug 10 07:23:37 PM PDT 24
Peak memory 219136 kb
Host smart-7e56763d-f542-4fa6-bfd3-5c4bb4fc6b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919264456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2919264456
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2885880831
Short name T640
Test name
Test status
Simulation time 35193824 ps
CPU time 1.4 seconds
Started Aug 10 07:23:37 PM PDT 24
Finished Aug 10 07:23:38 PM PDT 24
Peak memory 218596 kb
Host smart-1c4be188-f30a-4241-b222-2964fc9505a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885880831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2885880831
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.65446586
Short name T805
Test name
Test status
Simulation time 25918016 ps
CPU time 1.21 seconds
Started Aug 10 07:23:37 PM PDT 24
Finished Aug 10 07:23:38 PM PDT 24
Peak memory 215536 kb
Host smart-ac0b4ea1-fe33-4639-9b4d-3de50d2ceda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65446586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.65446586
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.1464907635
Short name T975
Test name
Test status
Simulation time 33313683 ps
CPU time 1.32 seconds
Started Aug 10 07:23:39 PM PDT 24
Finished Aug 10 07:23:40 PM PDT 24
Peak memory 219776 kb
Host smart-16ba9681-6065-4d6c-9791-42e9616f5fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464907635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1464907635
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2592907397
Short name T872
Test name
Test status
Simulation time 29303003 ps
CPU time 1.28 seconds
Started Aug 10 07:23:41 PM PDT 24
Finished Aug 10 07:23:42 PM PDT 24
Peak memory 217292 kb
Host smart-deb4903b-7eef-42c9-8e4a-067f99b85828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592907397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2592907397
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.242879524
Short name T688
Test name
Test status
Simulation time 33849151 ps
CPU time 1.11 seconds
Started Aug 10 07:23:39 PM PDT 24
Finished Aug 10 07:23:40 PM PDT 24
Peak memory 218692 kb
Host smart-e44c6731-3061-4fbc-bb41-fd85db898bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242879524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.242879524
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2842267455
Short name T153
Test name
Test status
Simulation time 21842544 ps
CPU time 1.05 seconds
Started Aug 10 07:23:33 PM PDT 24
Finished Aug 10 07:23:34 PM PDT 24
Peak memory 224144 kb
Host smart-51908932-0ecc-4811-8e41-652241232bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842267455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2842267455
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1250215735
Short name T666
Test name
Test status
Simulation time 40868575 ps
CPU time 1.39 seconds
Started Aug 10 07:23:35 PM PDT 24
Finished Aug 10 07:23:36 PM PDT 24
Peak memory 219928 kb
Host smart-7f907378-1cb0-4ff8-b402-f185c0fecd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250215735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1250215735
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1258664529
Short name T968
Test name
Test status
Simulation time 128110767 ps
CPU time 1.19 seconds
Started Aug 10 07:23:40 PM PDT 24
Finished Aug 10 07:23:41 PM PDT 24
Peak memory 219644 kb
Host smart-31ddadc7-1d18-47a4-872d-b7ddf26dd260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258664529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1258664529
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2778988089
Short name T63
Test name
Test status
Simulation time 36757846 ps
CPU time 1.2 seconds
Started Aug 10 07:23:44 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 229780 kb
Host smart-b51814a3-e12c-46a5-b38e-ee23d73b5342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778988089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2778988089
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1198448211
Short name T776
Test name
Test status
Simulation time 159474814 ps
CPU time 1.24 seconds
Started Aug 10 07:23:40 PM PDT 24
Finished Aug 10 07:23:41 PM PDT 24
Peak memory 218468 kb
Host smart-75d7e50b-060a-47f6-b3d8-1cb41202c99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198448211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1198448211
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1689175450
Short name T680
Test name
Test status
Simulation time 172403871 ps
CPU time 1.29 seconds
Started Aug 10 07:22:00 PM PDT 24
Finished Aug 10 07:22:02 PM PDT 24
Peak memory 218256 kb
Host smart-0a9cd829-928d-4efa-8ef1-51e8e358f41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689175450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1689175450
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3139749327
Short name T734
Test name
Test status
Simulation time 30006041 ps
CPU time 0.98 seconds
Started Aug 10 07:21:57 PM PDT 24
Finished Aug 10 07:21:58 PM PDT 24
Peak memory 215244 kb
Host smart-81cbb203-2055-4f00-a0c9-2c5f3a705eff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139749327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3139749327
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4049837583
Short name T697
Test name
Test status
Simulation time 36494158 ps
CPU time 0.82 seconds
Started Aug 10 07:21:59 PM PDT 24
Finished Aug 10 07:21:59 PM PDT 24
Peak memory 215372 kb
Host smart-07bed467-a00e-42b6-ad80-b91515a65e95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049837583 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4049837583
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1299434352
Short name T565
Test name
Test status
Simulation time 78740965 ps
CPU time 1.03 seconds
Started Aug 10 07:21:57 PM PDT 24
Finished Aug 10 07:21:58 PM PDT 24
Peak memory 218364 kb
Host smart-295ac4c3-2e9c-4800-bea9-24049e7f79ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299434352 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1299434352
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.54148189
Short name T58
Test name
Test status
Simulation time 29649617 ps
CPU time 1.04 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:21:59 PM PDT 24
Peak memory 223996 kb
Host smart-38713d52-bebd-4a05-ad25-3b9daa640d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54148189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.54148189
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3265856420
Short name T581
Test name
Test status
Simulation time 121203957 ps
CPU time 2.43 seconds
Started Aug 10 07:21:47 PM PDT 24
Finished Aug 10 07:21:50 PM PDT 24
Peak memory 220048 kb
Host smart-5a375c09-cec4-492e-8cbb-12b97d55691a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265856420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3265856420
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3397032979
Short name T494
Test name
Test status
Simulation time 22187655 ps
CPU time 1.1 seconds
Started Aug 10 07:22:01 PM PDT 24
Finished Aug 10 07:22:02 PM PDT 24
Peak memory 215456 kb
Host smart-657f103d-f1a1-4392-9cfc-ff1e11cf66d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397032979 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3397032979
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3804471093
Short name T694
Test name
Test status
Simulation time 17436236 ps
CPU time 0.95 seconds
Started Aug 10 07:21:47 PM PDT 24
Finished Aug 10 07:21:48 PM PDT 24
Peak memory 207084 kb
Host smart-9c0965fa-0092-4ffc-b7fe-2f4b3093df9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804471093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3804471093
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3315294319
Short name T873
Test name
Test status
Simulation time 16731431 ps
CPU time 1 seconds
Started Aug 10 07:21:45 PM PDT 24
Finished Aug 10 07:21:47 PM PDT 24
Peak memory 215304 kb
Host smart-c3eae8cd-119e-49cf-a8e4-8baa53ddaa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315294319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3315294319
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2963447775
Short name T686
Test name
Test status
Simulation time 821112020 ps
CPU time 5 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:22:03 PM PDT 24
Peak memory 217620 kb
Host smart-57c0c682-b66b-4b77-9aa2-ef670a789c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963447775 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2963447775
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.43277674
Short name T234
Test name
Test status
Simulation time 44243395398 ps
CPU time 713.73 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:33:52 PM PDT 24
Peak memory 218448 kb
Host smart-adff68f6-88a3-46a0-8ec1-82429e9b5b6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43277674 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.43277674
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.251588736
Short name T755
Test name
Test status
Simulation time 50911962 ps
CPU time 1.24 seconds
Started Aug 10 07:23:32 PM PDT 24
Finished Aug 10 07:23:33 PM PDT 24
Peak memory 219008 kb
Host smart-a1aaec7f-58ff-4c58-a9da-bb0f917e5a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251588736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.251588736
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1518292460
Short name T140
Test name
Test status
Simulation time 34059890 ps
CPU time 0.95 seconds
Started Aug 10 07:23:35 PM PDT 24
Finished Aug 10 07:23:36 PM PDT 24
Peak memory 219964 kb
Host smart-2633f721-01ed-44c3-9e23-dc3e69af948e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518292460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1518292460
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1026546348
Short name T693
Test name
Test status
Simulation time 52421153 ps
CPU time 1.91 seconds
Started Aug 10 07:23:39 PM PDT 24
Finished Aug 10 07:23:41 PM PDT 24
Peak memory 218696 kb
Host smart-780287e9-10bc-4e37-8407-471da78a3422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026546348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1026546348
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1153433283
Short name T868
Test name
Test status
Simulation time 49573600 ps
CPU time 1.08 seconds
Started Aug 10 07:23:35 PM PDT 24
Finished Aug 10 07:23:36 PM PDT 24
Peak memory 218668 kb
Host smart-88a61ed3-9c91-403b-9159-2b675f9d2a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153433283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1153433283
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1098862387
Short name T610
Test name
Test status
Simulation time 20956067 ps
CPU time 1.06 seconds
Started Aug 10 07:23:39 PM PDT 24
Finished Aug 10 07:23:40 PM PDT 24
Peak memory 224140 kb
Host smart-89f65210-a5c6-40d9-96cd-712eee1a01ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098862387 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1098862387
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.372124398
Short name T413
Test name
Test status
Simulation time 33640126 ps
CPU time 1.45 seconds
Started Aug 10 07:23:34 PM PDT 24
Finished Aug 10 07:23:35 PM PDT 24
Peak memory 217364 kb
Host smart-857d2f3a-2743-4333-8301-584fe9225c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372124398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.372124398
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3152352192
Short name T700
Test name
Test status
Simulation time 41480090 ps
CPU time 1.1 seconds
Started Aug 10 07:23:34 PM PDT 24
Finished Aug 10 07:23:35 PM PDT 24
Peak memory 218708 kb
Host smart-df82805d-d339-4a57-ae51-302a6a080fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152352192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3152352192
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.716317088
Short name T147
Test name
Test status
Simulation time 37637107 ps
CPU time 0.96 seconds
Started Aug 10 07:23:32 PM PDT 24
Finished Aug 10 07:23:33 PM PDT 24
Peak memory 219876 kb
Host smart-3e864bbe-e3c4-4fd0-8bf0-264d565e1dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716317088 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.716317088
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3444595972
Short name T475
Test name
Test status
Simulation time 54547470 ps
CPU time 1.39 seconds
Started Aug 10 07:23:36 PM PDT 24
Finished Aug 10 07:23:38 PM PDT 24
Peak memory 218796 kb
Host smart-cb497f32-9d78-4e4e-b969-4af4bb9f68c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444595972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3444595972
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1242638308
Short name T884
Test name
Test status
Simulation time 72683257 ps
CPU time 1.19 seconds
Started Aug 10 07:23:34 PM PDT 24
Finished Aug 10 07:23:36 PM PDT 24
Peak memory 218440 kb
Host smart-0d3ea3ea-7505-4f9d-a4ac-53ba25b73a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242638308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1242638308
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.3245084284
Short name T500
Test name
Test status
Simulation time 22128253 ps
CPU time 0.9 seconds
Started Aug 10 07:23:34 PM PDT 24
Finished Aug 10 07:23:35 PM PDT 24
Peak memory 218728 kb
Host smart-6647ee75-f77d-4546-a819-e049b1765d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245084284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3245084284
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.4128069620
Short name T904
Test name
Test status
Simulation time 41498787 ps
CPU time 1.08 seconds
Started Aug 10 07:23:39 PM PDT 24
Finished Aug 10 07:23:40 PM PDT 24
Peak memory 217316 kb
Host smart-fc22df1a-5cc1-439f-b78d-9b076f960ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128069620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.4128069620
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.935755621
Short name T230
Test name
Test status
Simulation time 49587803 ps
CPU time 1.15 seconds
Started Aug 10 07:23:40 PM PDT 24
Finished Aug 10 07:23:42 PM PDT 24
Peak memory 218748 kb
Host smart-2620e082-7730-45b0-9618-cc01d44308ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935755621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.935755621
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2495413941
Short name T847
Test name
Test status
Simulation time 20263021 ps
CPU time 1.09 seconds
Started Aug 10 07:23:39 PM PDT 24
Finished Aug 10 07:23:40 PM PDT 24
Peak memory 218656 kb
Host smart-c1832deb-9843-46e5-b4b0-c01039320f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495413941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2495413941
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1833229995
Short name T259
Test name
Test status
Simulation time 68780871 ps
CPU time 1.59 seconds
Started Aug 10 07:23:37 PM PDT 24
Finished Aug 10 07:23:38 PM PDT 24
Peak memory 218848 kb
Host smart-bdee9837-e487-461d-a5b1-f259409a08ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833229995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1833229995
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2180835710
Short name T724
Test name
Test status
Simulation time 54837067 ps
CPU time 1.23 seconds
Started Aug 10 07:23:41 PM PDT 24
Finished Aug 10 07:23:42 PM PDT 24
Peak memory 219832 kb
Host smart-000484a3-f21e-4015-9369-1d3d6c11dbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180835710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2180835710
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3399006416
Short name T204
Test name
Test status
Simulation time 44843240 ps
CPU time 1.12 seconds
Started Aug 10 07:23:40 PM PDT 24
Finished Aug 10 07:23:42 PM PDT 24
Peak memory 219896 kb
Host smart-58cb6aa9-a3d1-43e0-bae6-a136471d775c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399006416 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3399006416
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3655786850
Short name T342
Test name
Test status
Simulation time 1039362515 ps
CPU time 7.87 seconds
Started Aug 10 07:23:34 PM PDT 24
Finished Aug 10 07:23:42 PM PDT 24
Peak memory 218724 kb
Host smart-c366cf05-72e4-4a4b-9872-57a762ce8db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655786850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3655786850
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1485231089
Short name T614
Test name
Test status
Simulation time 44355049 ps
CPU time 1.21 seconds
Started Aug 10 07:23:40 PM PDT 24
Finished Aug 10 07:23:42 PM PDT 24
Peak memory 218672 kb
Host smart-76a35432-5d8a-4694-9f73-d7c240233bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485231089 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1485231089
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.4199007217
Short name T706
Test name
Test status
Simulation time 20578158 ps
CPU time 0.94 seconds
Started Aug 10 07:23:39 PM PDT 24
Finished Aug 10 07:23:40 PM PDT 24
Peak memory 218680 kb
Host smart-e2c6d91f-87a6-4693-b4f3-7007e9e8c532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199007217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.4199007217
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2585294769
Short name T305
Test name
Test status
Simulation time 262122234 ps
CPU time 1.64 seconds
Started Aug 10 07:23:41 PM PDT 24
Finished Aug 10 07:23:42 PM PDT 24
Peak memory 218852 kb
Host smart-07309031-4bfe-41db-bb49-51c2bae4a68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585294769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2585294769
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.4229426842
Short name T942
Test name
Test status
Simulation time 22997973 ps
CPU time 1.16 seconds
Started Aug 10 07:23:41 PM PDT 24
Finished Aug 10 07:23:42 PM PDT 24
Peak memory 219976 kb
Host smart-9604f6d4-0920-4e1f-8fb8-8a08a0e2b1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229426842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.4229426842
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_genbits.3890949261
Short name T733
Test name
Test status
Simulation time 61038559 ps
CPU time 1.34 seconds
Started Aug 10 07:23:40 PM PDT 24
Finished Aug 10 07:23:42 PM PDT 24
Peak memory 219556 kb
Host smart-fda8eaf5-1066-4c72-b9b8-bb8f4eae4439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890949261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3890949261
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1681863519
Short name T673
Test name
Test status
Simulation time 35137554 ps
CPU time 1.22 seconds
Started Aug 10 07:23:42 PM PDT 24
Finished Aug 10 07:23:43 PM PDT 24
Peak memory 220744 kb
Host smart-e9cb73df-94f4-4c38-b283-96a3c38894d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681863519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1681863519
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2942749242
Short name T167
Test name
Test status
Simulation time 30071206 ps
CPU time 0.93 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 218884 kb
Host smart-3cd0d5e6-874e-49f6-8e81-365c22f43b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942749242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2942749242
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3594816480
Short name T42
Test name
Test status
Simulation time 85974622 ps
CPU time 1.25 seconds
Started Aug 10 07:23:40 PM PDT 24
Finished Aug 10 07:23:41 PM PDT 24
Peak memory 217432 kb
Host smart-1dd0e5dc-fe28-4a8e-a944-65c1350ce0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594816480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3594816480
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2809436382
Short name T925
Test name
Test status
Simulation time 40329244 ps
CPU time 1.13 seconds
Started Aug 10 07:23:41 PM PDT 24
Finished Aug 10 07:23:42 PM PDT 24
Peak memory 218988 kb
Host smart-fc5f464a-e0e8-4fd9-925b-12ae5134e609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809436382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2809436382
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2880321269
Short name T736
Test name
Test status
Simulation time 41908006 ps
CPU time 0.95 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 219112 kb
Host smart-5d96bc18-04b9-4733-a722-3be4d3557368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880321269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2880321269
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3429716400
Short name T503
Test name
Test status
Simulation time 46058451 ps
CPU time 1.33 seconds
Started Aug 10 07:23:44 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 218664 kb
Host smart-22691186-9763-41bd-b742-01b7e35f937a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429716400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3429716400
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1864147532
Short name T871
Test name
Test status
Simulation time 28326659 ps
CPU time 1.29 seconds
Started Aug 10 07:22:00 PM PDT 24
Finished Aug 10 07:22:01 PM PDT 24
Peak memory 219528 kb
Host smart-1c956d15-c697-4975-b674-3a6f68791ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864147532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1864147532
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1120902679
Short name T374
Test name
Test status
Simulation time 78938169 ps
CPU time 1 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:21:59 PM PDT 24
Peak memory 215212 kb
Host smart-2d509263-2f30-4d9c-b8b4-b89210a0029f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120902679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1120902679
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2709205809
Short name T647
Test name
Test status
Simulation time 13446611 ps
CPU time 0.95 seconds
Started Aug 10 07:21:59 PM PDT 24
Finished Aug 10 07:22:00 PM PDT 24
Peak memory 219108 kb
Host smart-ff6ddfe6-55ef-4783-83ee-d21eef49f80c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709205809 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2709205809
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.27774076
Short name T984
Test name
Test status
Simulation time 31998437 ps
CPU time 1.04 seconds
Started Aug 10 07:21:55 PM PDT 24
Finished Aug 10 07:21:56 PM PDT 24
Peak memory 217032 kb
Host smart-fb133223-19a4-4e4e-9a1d-95424bf6e175
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27774076 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disa
ble_auto_req_mode.27774076
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2891738817
Short name T196
Test name
Test status
Simulation time 65743958 ps
CPU time 0.84 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:21:59 PM PDT 24
Peak memory 219456 kb
Host smart-eaf3307d-8751-4298-8cdb-b76ddacafe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891738817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2891738817
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2134533790
Short name T483
Test name
Test status
Simulation time 31744357 ps
CPU time 1.36 seconds
Started Aug 10 07:21:59 PM PDT 24
Finished Aug 10 07:22:01 PM PDT 24
Peak memory 218528 kb
Host smart-5f216a00-d0d2-41ca-b22c-888f8ff86b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134533790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2134533790
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3172195212
Short name T740
Test name
Test status
Simulation time 21593281 ps
CPU time 1.09 seconds
Started Aug 10 07:21:57 PM PDT 24
Finished Aug 10 07:21:59 PM PDT 24
Peak memory 215932 kb
Host smart-6c329d76-02fc-48d0-850d-8c50c7fcc90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172195212 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3172195212
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2403291273
Short name T536
Test name
Test status
Simulation time 25111826 ps
CPU time 1.01 seconds
Started Aug 10 07:22:02 PM PDT 24
Finished Aug 10 07:22:03 PM PDT 24
Peak memory 207092 kb
Host smart-bf043d48-80d3-4afa-b5d7-04d02d6c9e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403291273 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2403291273
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.984147150
Short name T424
Test name
Test status
Simulation time 110498495 ps
CPU time 0.97 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:21:59 PM PDT 24
Peak memory 215156 kb
Host smart-7e32ace2-f059-414c-9e87-864f07c17806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984147150 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.984147150
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2160890411
Short name T751
Test name
Test status
Simulation time 1004067360 ps
CPU time 5.44 seconds
Started Aug 10 07:22:00 PM PDT 24
Finished Aug 10 07:22:05 PM PDT 24
Peak memory 215292 kb
Host smart-42c6fa66-a5a4-4d88-82f1-2a8298c8bc4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160890411 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2160890411
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2883357613
Short name T244
Test name
Test status
Simulation time 14666637639 ps
CPU time 234.68 seconds
Started Aug 10 07:21:58 PM PDT 24
Finished Aug 10 07:25:53 PM PDT 24
Peak memory 218132 kb
Host smart-7ceccafa-e106-427f-84b2-6ece2583d756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883357613 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2883357613
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.2250013591
Short name T691
Test name
Test status
Simulation time 43783665 ps
CPU time 1.23 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 218580 kb
Host smart-2f92a67e-3390-42a1-b583-4eb20dd9af01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250013591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.2250013591
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.4220235275
Short name T687
Test name
Test status
Simulation time 21529992 ps
CPU time 1.03 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 224176 kb
Host smart-917ee48b-8ee0-4c46-bcfb-1f04945d9408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220235275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.4220235275
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1860039462
Short name T529
Test name
Test status
Simulation time 55944915 ps
CPU time 1.42 seconds
Started Aug 10 07:23:44 PM PDT 24
Finished Aug 10 07:23:45 PM PDT 24
Peak memory 218904 kb
Host smart-2c16d6dd-bb84-438c-8cd7-c94d4494dea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860039462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1860039462
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.2341853038
Short name T705
Test name
Test status
Simulation time 27857007 ps
CPU time 1.19 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 215624 kb
Host smart-3340f148-74cc-46c6-a2ae-fd2d1deb79a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341853038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.2341853038
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2992991388
Short name T222
Test name
Test status
Simulation time 29803515 ps
CPU time 1.14 seconds
Started Aug 10 07:23:43 PM PDT 24
Finished Aug 10 07:23:44 PM PDT 24
Peak memory 219924 kb
Host smart-50c0f481-8cb6-4230-9be1-5eb842427221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992991388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2992991388
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.132969663
Short name T318
Test name
Test status
Simulation time 44170116 ps
CPU time 1.33 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 218520 kb
Host smart-c7c08e0f-681e-4a15-a6ff-862683d6a490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132969663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.132969663
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.890144167
Short name T492
Test name
Test status
Simulation time 78131966 ps
CPU time 1.21 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 219264 kb
Host smart-d60881f9-c571-43e8-9b5c-7f72187b6360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890144167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.890144167
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.364960904
Short name T174
Test name
Test status
Simulation time 21820459 ps
CPU time 0.94 seconds
Started Aug 10 07:23:43 PM PDT 24
Finished Aug 10 07:23:44 PM PDT 24
Peak memory 218616 kb
Host smart-b48c8931-9a3a-4145-aa30-321ac1ad7fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364960904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.364960904
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3078780387
Short name T420
Test name
Test status
Simulation time 45446441 ps
CPU time 1.65 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 219968 kb
Host smart-1905ebcf-a2f7-4458-9418-997403b91582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078780387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3078780387
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.527879430
Short name T783
Test name
Test status
Simulation time 74576659 ps
CPU time 1.29 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:48 PM PDT 24
Peak memory 215600 kb
Host smart-df30c597-7220-4ef9-a146-a1a902e50b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527879430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.527879430
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.1107131846
Short name T163
Test name
Test status
Simulation time 20154199 ps
CPU time 1.17 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 224160 kb
Host smart-b4e9c293-93e7-46f8-8bc2-c35bd0e882ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107131846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1107131846
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.953202868
Short name T20
Test name
Test status
Simulation time 31393643 ps
CPU time 1.37 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 220016 kb
Host smart-a7c1acfb-0f46-4f26-9215-b9a6aebbe93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953202868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.953202868
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1817542691
Short name T799
Test name
Test status
Simulation time 23932487 ps
CPU time 1.19 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 218448 kb
Host smart-36e8d455-327f-414b-a7bd-14ccada31d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817542691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1817542691
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1603441231
Short name T900
Test name
Test status
Simulation time 22780478 ps
CPU time 0.96 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 218836 kb
Host smart-c9d62e56-9ca8-479a-9a9b-d0aa8ea8c31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603441231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1603441231
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1212658260
Short name T638
Test name
Test status
Simulation time 54957778 ps
CPU time 1.76 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 218632 kb
Host smart-a254f5c3-c642-470f-a48d-6e8c925c3f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212658260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1212658260
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.1391061386
Short name T166
Test name
Test status
Simulation time 45550496 ps
CPU time 1.18 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 220732 kb
Host smart-5b887ced-8088-4544-86a7-d655838b1e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391061386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.1391061386
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1179542152
Short name T114
Test name
Test status
Simulation time 35784851 ps
CPU time 1.1 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 220784 kb
Host smart-3c129d62-a70f-4403-aeff-ed18fee0153b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179542152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1179542152
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1332282455
Short name T996
Test name
Test status
Simulation time 31499646 ps
CPU time 1.18 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 217288 kb
Host smart-e05b7644-d47c-41c7-875b-79b21965258f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332282455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1332282455
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.2199977883
Short name T822
Test name
Test status
Simulation time 43789068 ps
CPU time 1.17 seconds
Started Aug 10 07:23:44 PM PDT 24
Finished Aug 10 07:23:45 PM PDT 24
Peak memory 219000 kb
Host smart-0ab1bd0d-2c2a-48f1-8ab5-5c7e0169aeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199977883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.2199977883
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.2162232788
Short name T864
Test name
Test status
Simulation time 67900673 ps
CPU time 1.1 seconds
Started Aug 10 07:23:44 PM PDT 24
Finished Aug 10 07:23:45 PM PDT 24
Peak memory 224132 kb
Host smart-c1ed20d8-1a45-4068-9f79-10d6a83ece12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162232788 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2162232788
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1935917936
Short name T978
Test name
Test status
Simulation time 91158312 ps
CPU time 1.52 seconds
Started Aug 10 07:23:47 PM PDT 24
Finished Aug 10 07:23:49 PM PDT 24
Peak memory 220224 kb
Host smart-70f9d7b6-4094-43ac-97e6-bedf8c3bd19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935917936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1935917936
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.577191290
Short name T582
Test name
Test status
Simulation time 27347302 ps
CPU time 1.21 seconds
Started Aug 10 07:23:47 PM PDT 24
Finished Aug 10 07:23:48 PM PDT 24
Peak memory 220700 kb
Host smart-76d6299f-c9a8-4bc3-8d00-3e63f70ceb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577191290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.577191290
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.3030524863
Short name T113
Test name
Test status
Simulation time 34383163 ps
CPU time 0.99 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 219764 kb
Host smart-e9f241de-f049-4ff9-ba03-7e2071181f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030524863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3030524863
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2687382694
Short name T573
Test name
Test status
Simulation time 52730823 ps
CPU time 1.23 seconds
Started Aug 10 07:23:44 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 219076 kb
Host smart-2ee41203-3bd2-45f3-96fa-f43d6b9781f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687382694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2687382694
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2357823525
Short name T893
Test name
Test status
Simulation time 87510933 ps
CPU time 1.28 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 220092 kb
Host smart-fb6c962a-df03-40e2-a82e-5baa92e32845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357823525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2357823525
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.920384916
Short name T115
Test name
Test status
Simulation time 21951141 ps
CPU time 1.05 seconds
Started Aug 10 07:23:47 PM PDT 24
Finished Aug 10 07:23:48 PM PDT 24
Peak memory 219832 kb
Host smart-018dedef-3938-46c8-81bf-d2d555de1a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920384916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.920384916
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2591356969
Short name T766
Test name
Test status
Simulation time 121475608 ps
CPU time 2.5 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:48 PM PDT 24
Peak memory 220332 kb
Host smart-eb1a683a-4fd1-4aa9-b54c-df9845da5516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591356969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2591356969
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2931533247
Short name T356
Test name
Test status
Simulation time 27802490 ps
CPU time 1.24 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:46 PM PDT 24
Peak memory 218640 kb
Host smart-29b017ef-6a97-4844-a1c5-58ff9c14870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931533247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2931533247
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.1524470007
Short name T773
Test name
Test status
Simulation time 20355432 ps
CPU time 1.01 seconds
Started Aug 10 07:23:46 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 218568 kb
Host smart-739f97fb-23ca-4dcd-8670-e2833dc949fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524470007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1524470007
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1102794583
Short name T523
Test name
Test status
Simulation time 51590279 ps
CPU time 1.48 seconds
Started Aug 10 07:23:45 PM PDT 24
Finished Aug 10 07:23:47 PM PDT 24
Peak memory 218340 kb
Host smart-cb21b827-3ab5-49b3-89c0-423f34f7a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102794583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1102794583
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%