Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 8 0 8 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] 7668 1 T4 28 T6 19 T50 19
all_values[1] 7668 1 T4 28 T6 19 T50 19



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 7875 1 T4 31 T6 27 T50 17
auto[1] 7461 1 T4 25 T6 11 T50 21



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 5987 1 T4 25 T6 15 T50 14
auto[1] 9349 1 T4 31 T6 23 T50 24



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 9100 1 T4 36 T6 25 T50 23
auto[1] 6236 1 T4 20 T6 13 T50 15



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intr   cp_intr_test   cp_intr_en   cp_intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] auto[0] auto[0] auto[0] 1462 1 T4 5 T6 7 T50 8
all_values[0] auto[0] auto[0] auto[1] 781 1 T4 1 T6 4 T50 1
all_values[0] auto[0] auto[1] auto[0] 1498 1 T4 8 T6 1 T50 3
all_values[0] auto[0] auto[1] auto[1] 777 1 T4 4 T50 3 T97 1
all_values[0] auto[1] auto[0] auto[1] 1625 1 T4 4 T6 6 T50 2
all_values[0] auto[1] auto[1] auto[1] 1525 1 T4 6 T6 1 T50 2
all_values[1] auto[0] auto[0] auto[0] 1568 1 T4 9 T6 5 T50 1
all_values[1] auto[0] auto[0] auto[1] 791 1 T4 6 T6 2 T50 2
all_values[1] auto[0] auto[1] auto[0] 1459 1 T4 3 T6 2 T50 2
all_values[1] auto[0] auto[1] auto[1] 764 1 T6 4 T50 3 T96 1
all_values[1] auto[1] auto[0] auto[1] 1648 1 T4 6 T6 3 T50 3
all_values[1] auto[1] auto[1] auto[1] 1438 1 T4 4 T6 3 T50 8


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal