Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr
Bins
| | | | | | | | | | | | |
all_values[0] |
7668 |
1 |
|
|
T4 |
28 |
|
T6 |
19 |
|
T50 |
19 |
all_values[1] |
7668 |
1 |
|
|
T4 |
28 |
|
T6 |
19 |
|
T50 |
19 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
| | | | | | | | | | | | |
auto[0] |
7875 |
1 |
|
|
T4 |
31 |
|
T6 |
27 |
|
T50 |
17 |
auto[1] |
7461 |
1 |
|
|
T4 |
25 |
|
T6 |
11 |
|
T50 |
21 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
| | | | | | | | | | | | |
auto[0] |
5987 |
1 |
|
|
T4 |
25 |
|
T6 |
15 |
|
T50 |
14 |
auto[1] |
9349 |
1 |
|
|
T4 |
31 |
|
T6 |
23 |
|
T50 |
24 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
| | | | | | | | | | | | |
auto[0] |
9100 |
1 |
|
|
T4 |
36 |
|
T6 |
25 |
|
T50 |
23 |
auto[1] |
6236 |
1 |
|
|
T4 |
20 |
|
T6 |
13 |
|
T50 |
15 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
| | | | | |
TOTAL |
12 |
0 |
12 |
100.00 |
|
Automatically Generated Cross Bins |
12 |
0 |
12 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
| | | | | | | | | | | | | | | |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
1462 |
1 |
|
|
T4 |
5 |
|
T6 |
7 |
|
T50 |
8 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
781 |
1 |
|
|
T4 |
1 |
|
T6 |
4 |
|
T50 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
1498 |
1 |
|
|
T4 |
8 |
|
T6 |
1 |
|
T50 |
3 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
777 |
1 |
|
|
T4 |
4 |
|
T50 |
3 |
|
T97 |
1 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
1625 |
1 |
|
|
T4 |
4 |
|
T6 |
6 |
|
T50 |
2 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
1525 |
1 |
|
|
T4 |
6 |
|
T6 |
1 |
|
T50 |
2 |
all_values[1] |
auto[0] |
auto[0] |
auto[0] |
1568 |
1 |
|
|
T4 |
9 |
|
T6 |
5 |
|
T50 |
1 |
all_values[1] |
auto[0] |
auto[0] |
auto[1] |
791 |
1 |
|
|
T4 |
6 |
|
T6 |
2 |
|
T50 |
2 |
all_values[1] |
auto[0] |
auto[1] |
auto[0] |
1459 |
1 |
|
|
T4 |
3 |
|
T6 |
2 |
|
T50 |
2 |
all_values[1] |
auto[0] |
auto[1] |
auto[1] |
764 |
1 |
|
|
T6 |
4 |
|
T50 |
3 |
|
T96 |
1 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
1648 |
1 |
|
|
T4 |
6 |
|
T6 |
3 |
|
T50 |
3 |
all_values[1] |
auto[1] |
auto[1] |
auto[1] |
1438 |
1 |
|
|
T4 |
4 |
|
T6 |
3 |
|
T50 |
8 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |