Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.70 98.25 93.97 97.02 92.44 96.37 99.77 92.06


Total test records in report: 1129
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T1028 /workspace/coverage/cover_reg_top/17.edn_intr_test.1120000235 Aug 11 07:05:01 PM PDT 24 Aug 11 07:05:02 PM PDT 24 45681930 ps
T1029 /workspace/coverage/cover_reg_top/7.edn_intr_test.792252381 Aug 11 07:04:41 PM PDT 24 Aug 11 07:04:42 PM PDT 24 11769216 ps
T249 /workspace/coverage/cover_reg_top/2.edn_csr_rw.4212126974 Aug 11 07:04:28 PM PDT 24 Aug 11 07:04:30 PM PDT 24 15998958 ps
T1030 /workspace/coverage/cover_reg_top/27.edn_intr_test.4228533913 Aug 11 07:05:08 PM PDT 24 Aug 11 07:05:09 PM PDT 24 25565378 ps
T1031 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2859782748 Aug 11 07:04:47 PM PDT 24 Aug 11 07:04:48 PM PDT 24 23779545 ps
T1032 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2078826690 Aug 11 07:05:05 PM PDT 24 Aug 11 07:05:07 PM PDT 24 193262066 ps
T1033 /workspace/coverage/cover_reg_top/33.edn_intr_test.1068594853 Aug 11 07:05:10 PM PDT 24 Aug 11 07:05:11 PM PDT 24 41823110 ps
T1034 /workspace/coverage/cover_reg_top/0.edn_tl_errors.4082740333 Aug 11 07:04:17 PM PDT 24 Aug 11 07:04:20 PM PDT 24 49243089 ps
T1035 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3531775857 Aug 11 07:04:47 PM PDT 24 Aug 11 07:04:48 PM PDT 24 22029002 ps
T1036 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4019432487 Aug 11 07:04:59 PM PDT 24 Aug 11 07:05:00 PM PDT 24 43077751 ps
T250 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1955726976 Aug 11 07:04:28 PM PDT 24 Aug 11 07:04:29 PM PDT 24 28598761 ps
T251 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1370111131 Aug 11 07:04:57 PM PDT 24 Aug 11 07:04:58 PM PDT 24 21712506 ps
T290 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.229264207 Aug 11 07:04:58 PM PDT 24 Aug 11 07:05:00 PM PDT 24 72103665 ps
T268 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3343285274 Aug 11 07:04:52 PM PDT 24 Aug 11 07:04:54 PM PDT 24 78469245 ps
T269 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3604701250 Aug 11 07:05:02 PM PDT 24 Aug 11 07:05:03 PM PDT 24 13975460 ps
T1037 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3182638121 Aug 11 07:04:41 PM PDT 24 Aug 11 07:04:42 PM PDT 24 15054603 ps
T1038 /workspace/coverage/cover_reg_top/26.edn_intr_test.1865026682 Aug 11 07:05:06 PM PDT 24 Aug 11 07:05:09 PM PDT 24 11337656 ps
T1039 /workspace/coverage/cover_reg_top/19.edn_intr_test.3042956225 Aug 11 07:05:00 PM PDT 24 Aug 11 07:05:01 PM PDT 24 14531139 ps
T1040 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2072359946 Aug 11 07:04:47 PM PDT 24 Aug 11 07:04:49 PM PDT 24 145110105 ps
T1041 /workspace/coverage/cover_reg_top/38.edn_intr_test.1940033715 Aug 11 07:05:06 PM PDT 24 Aug 11 07:05:07 PM PDT 24 44992751 ps
T1042 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1100143355 Aug 11 07:04:25 PM PDT 24 Aug 11 07:04:27 PM PDT 24 18335592 ps
T252 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3804866701 Aug 11 07:05:00 PM PDT 24 Aug 11 07:05:01 PM PDT 24 199454624 ps
T1043 /workspace/coverage/cover_reg_top/28.edn_intr_test.3153315687 Aug 11 07:05:06 PM PDT 24 Aug 11 07:05:07 PM PDT 24 48004057 ps
T1044 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1366628066 Aug 11 07:04:46 PM PDT 24 Aug 11 07:04:48 PM PDT 24 55656646 ps
T253 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2945174074 Aug 11 07:04:34 PM PDT 24 Aug 11 07:04:35 PM PDT 24 25880749 ps
T1045 /workspace/coverage/cover_reg_top/43.edn_intr_test.3710510962 Aug 11 07:05:10 PM PDT 24 Aug 11 07:05:11 PM PDT 24 22648651 ps
T1046 /workspace/coverage/cover_reg_top/32.edn_intr_test.1169601661 Aug 11 07:05:06 PM PDT 24 Aug 11 07:05:07 PM PDT 24 27493706 ps
T1047 /workspace/coverage/cover_reg_top/9.edn_intr_test.3423342228 Aug 11 07:04:46 PM PDT 24 Aug 11 07:04:47 PM PDT 24 12329900 ps
T285 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1695661759 Aug 11 07:04:23 PM PDT 24 Aug 11 07:04:25 PM PDT 24 159401829 ps
T1048 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2825632238 Aug 11 07:04:42 PM PDT 24 Aug 11 07:04:46 PM PDT 24 52416518 ps
T1049 /workspace/coverage/cover_reg_top/2.edn_intr_test.2151651456 Aug 11 07:04:27 PM PDT 24 Aug 11 07:04:28 PM PDT 24 21379220 ps
T286 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.831211218 Aug 11 07:04:19 PM PDT 24 Aug 11 07:04:21 PM PDT 24 97020623 ps
T270 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3765736948 Aug 11 07:04:42 PM PDT 24 Aug 11 07:04:43 PM PDT 24 25761483 ps
T1050 /workspace/coverage/cover_reg_top/44.edn_intr_test.4226757277 Aug 11 07:05:08 PM PDT 24 Aug 11 07:05:09 PM PDT 24 44072636 ps
T254 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1066205259 Aug 11 07:04:24 PM PDT 24 Aug 11 07:04:25 PM PDT 24 45666509 ps
T255 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1615820344 Aug 11 07:04:27 PM PDT 24 Aug 11 07:04:28 PM PDT 24 18837534 ps
T256 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.502080820 Aug 11 07:04:48 PM PDT 24 Aug 11 07:04:49 PM PDT 24 54607160 ps
T1051 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1855096354 Aug 11 07:04:22 PM PDT 24 Aug 11 07:04:23 PM PDT 24 22306589 ps
T1052 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1553430485 Aug 11 07:04:23 PM PDT 24 Aug 11 07:04:24 PM PDT 24 15172167 ps
T271 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1344486964 Aug 11 07:04:42 PM PDT 24 Aug 11 07:04:44 PM PDT 24 56395336 ps
T287 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3898642719 Aug 11 07:04:40 PM PDT 24 Aug 11 07:04:43 PM PDT 24 663602244 ps
T1053 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1946332839 Aug 11 07:04:30 PM PDT 24 Aug 11 07:04:31 PM PDT 24 131047557 ps
T257 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2352839737 Aug 11 07:04:43 PM PDT 24 Aug 11 07:04:44 PM PDT 24 14281479 ps
T1054 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2512744181 Aug 11 07:04:30 PM PDT 24 Aug 11 07:04:31 PM PDT 24 48604995 ps
T1055 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3550198800 Aug 11 07:04:37 PM PDT 24 Aug 11 07:04:39 PM PDT 24 37415059 ps
T1056 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1095326850 Aug 11 07:04:41 PM PDT 24 Aug 11 07:04:45 PM PDT 24 83050795 ps
T1057 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2794481743 Aug 11 07:04:29 PM PDT 24 Aug 11 07:04:33 PM PDT 24 266034783 ps
T1058 /workspace/coverage/cover_reg_top/19.edn_tl_errors.530886150 Aug 11 07:05:01 PM PDT 24 Aug 11 07:05:03 PM PDT 24 24198409 ps
T1059 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.692579371 Aug 11 07:04:34 PM PDT 24 Aug 11 07:04:35 PM PDT 24 75364532 ps
T1060 /workspace/coverage/cover_reg_top/23.edn_intr_test.2606608588 Aug 11 07:04:59 PM PDT 24 Aug 11 07:05:00 PM PDT 24 16549173 ps
T1061 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2735350390 Aug 11 07:04:53 PM PDT 24 Aug 11 07:04:55 PM PDT 24 76120929 ps
T1062 /workspace/coverage/cover_reg_top/47.edn_intr_test.2460186020 Aug 11 07:05:09 PM PDT 24 Aug 11 07:05:10 PM PDT 24 63225944 ps
T1063 /workspace/coverage/cover_reg_top/15.edn_tl_errors.118624913 Aug 11 07:04:52 PM PDT 24 Aug 11 07:04:57 PM PDT 24 285744848 ps
T1064 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2021447812 Aug 11 07:04:55 PM PDT 24 Aug 11 07:04:56 PM PDT 24 485453859 ps
T1065 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1451183339 Aug 11 07:05:01 PM PDT 24 Aug 11 07:05:02 PM PDT 24 31717622 ps
T258 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.883979641 Aug 11 07:04:28 PM PDT 24 Aug 11 07:04:29 PM PDT 24 91390328 ps
T1066 /workspace/coverage/cover_reg_top/4.edn_intr_test.1026538815 Aug 11 07:04:41 PM PDT 24 Aug 11 07:04:42 PM PDT 24 29456521 ps
T1067 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3922927619 Aug 11 07:04:47 PM PDT 24 Aug 11 07:04:48 PM PDT 24 58669521 ps
T1068 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4164115985 Aug 11 07:05:00 PM PDT 24 Aug 11 07:05:02 PM PDT 24 60665006 ps
T1069 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1957162527 Aug 11 07:04:47 PM PDT 24 Aug 11 07:04:48 PM PDT 24 16115484 ps
T1070 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3373650072 Aug 11 07:05:01 PM PDT 24 Aug 11 07:05:02 PM PDT 24 54736012 ps
T1071 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1176073189 Aug 11 07:04:53 PM PDT 24 Aug 11 07:04:54 PM PDT 24 80896288 ps
T1072 /workspace/coverage/cover_reg_top/49.edn_intr_test.713475509 Aug 11 07:05:05 PM PDT 24 Aug 11 07:05:06 PM PDT 24 13065696 ps
T1073 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1580499764 Aug 11 07:04:41 PM PDT 24 Aug 11 07:04:43 PM PDT 24 55326791 ps
T1074 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3542973371 Aug 11 07:04:41 PM PDT 24 Aug 11 07:04:44 PM PDT 24 102558140 ps
T259 /workspace/coverage/cover_reg_top/15.edn_csr_rw.4059952154 Aug 11 07:04:54 PM PDT 24 Aug 11 07:04:55 PM PDT 24 18604486 ps
T1075 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.314890281 Aug 11 07:04:29 PM PDT 24 Aug 11 07:04:30 PM PDT 24 19724552 ps
T1076 /workspace/coverage/cover_reg_top/18.edn_intr_test.4177120892 Aug 11 07:05:02 PM PDT 24 Aug 11 07:05:03 PM PDT 24 43280790 ps
T1077 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1035399805 Aug 11 07:04:28 PM PDT 24 Aug 11 07:04:32 PM PDT 24 155233154 ps
T1078 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1474142408 Aug 11 07:04:22 PM PDT 24 Aug 11 07:04:23 PM PDT 24 63040618 ps
T1079 /workspace/coverage/cover_reg_top/8.edn_intr_test.1520763566 Aug 11 07:04:42 PM PDT 24 Aug 11 07:04:43 PM PDT 24 15046322 ps
T260 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1074930040 Aug 11 07:04:41 PM PDT 24 Aug 11 07:04:43 PM PDT 24 238236696 ps
T1080 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3952449582 Aug 11 07:04:42 PM PDT 24 Aug 11 07:04:43 PM PDT 24 58470572 ps
T1081 /workspace/coverage/cover_reg_top/16.edn_intr_test.3299093225 Aug 11 07:05:00 PM PDT 24 Aug 11 07:05:01 PM PDT 24 63331170 ps
T1082 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3966181795 Aug 11 07:04:37 PM PDT 24 Aug 11 07:04:43 PM PDT 24 195736478 ps
T1083 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3479218236 Aug 11 07:04:25 PM PDT 24 Aug 11 07:04:28 PM PDT 24 57520652 ps
T1084 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3658068903 Aug 11 07:05:02 PM PDT 24 Aug 11 07:05:04 PM PDT 24 18913005 ps
T1085 /workspace/coverage/cover_reg_top/30.edn_intr_test.1460648912 Aug 11 07:05:06 PM PDT 24 Aug 11 07:05:07 PM PDT 24 47303671 ps
T1086 /workspace/coverage/cover_reg_top/15.edn_intr_test.1153820598 Aug 11 07:04:53 PM PDT 24 Aug 11 07:04:54 PM PDT 24 21709985 ps
T291 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2182030192 Aug 11 07:05:05 PM PDT 24 Aug 11 07:05:08 PM PDT 24 117604846 ps
T1087 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1787984301 Aug 11 07:05:00 PM PDT 24 Aug 11 07:05:03 PM PDT 24 132552406 ps
T1088 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3969547462 Aug 11 07:04:51 PM PDT 24 Aug 11 07:04:53 PM PDT 24 21283877 ps
T1089 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4229162180 Aug 11 07:04:47 PM PDT 24 Aug 11 07:04:48 PM PDT 24 51219848 ps
T261 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2964356102 Aug 11 07:04:25 PM PDT 24 Aug 11 07:04:26 PM PDT 24 18508092 ps
T1090 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2834396304 Aug 11 07:04:53 PM PDT 24 Aug 11 07:04:57 PM PDT 24 438738328 ps
T1091 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2018959473 Aug 11 07:04:53 PM PDT 24 Aug 11 07:04:54 PM PDT 24 35966970 ps
T1092 /workspace/coverage/cover_reg_top/21.edn_intr_test.4205042050 Aug 11 07:05:00 PM PDT 24 Aug 11 07:05:02 PM PDT 24 13952227 ps
T292 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.349875446 Aug 11 07:04:48 PM PDT 24 Aug 11 07:04:50 PM PDT 24 206014189 ps
T262 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1801458854 Aug 11 07:04:52 PM PDT 24 Aug 11 07:04:53 PM PDT 24 25748982 ps
T1093 /workspace/coverage/cover_reg_top/24.edn_intr_test.1945795031 Aug 11 07:04:58 PM PDT 24 Aug 11 07:04:59 PM PDT 24 11224683 ps
T1094 /workspace/coverage/cover_reg_top/36.edn_intr_test.612686232 Aug 11 07:05:06 PM PDT 24 Aug 11 07:05:07 PM PDT 24 11959270 ps
T1095 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.125669610 Aug 11 07:04:48 PM PDT 24 Aug 11 07:04:49 PM PDT 24 92884175 ps
T288 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3284165448 Aug 11 07:05:01 PM PDT 24 Aug 11 07:05:03 PM PDT 24 48433578 ps
T1096 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2249268544 Aug 11 07:04:35 PM PDT 24 Aug 11 07:04:37 PM PDT 24 56102187 ps
T1097 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3967578549 Aug 11 07:04:59 PM PDT 24 Aug 11 07:05:02 PM PDT 24 81379854 ps
T1098 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.548030358 Aug 11 07:04:34 PM PDT 24 Aug 11 07:04:35 PM PDT 24 47164605 ps
T1099 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1319266839 Aug 11 07:04:53 PM PDT 24 Aug 11 07:04:55 PM PDT 24 385468721 ps
T1100 /workspace/coverage/cover_reg_top/34.edn_intr_test.4230734191 Aug 11 07:05:05 PM PDT 24 Aug 11 07:05:06 PM PDT 24 34064462 ps
T1101 /workspace/coverage/cover_reg_top/20.edn_intr_test.2725258984 Aug 11 07:05:00 PM PDT 24 Aug 11 07:05:01 PM PDT 24 63541452 ps
T1102 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2506439041 Aug 11 07:04:22 PM PDT 24 Aug 11 07:04:24 PM PDT 24 40278266 ps
T1103 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1951180373 Aug 11 07:04:55 PM PDT 24 Aug 11 07:04:57 PM PDT 24 84626379 ps
T264 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3511798152 Aug 11 07:04:37 PM PDT 24 Aug 11 07:04:38 PM PDT 24 109083217 ps
T1104 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2837926786 Aug 11 07:04:28 PM PDT 24 Aug 11 07:04:30 PM PDT 24 55404346 ps
T1105 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3828304981 Aug 11 07:04:30 PM PDT 24 Aug 11 07:04:33 PM PDT 24 110292209 ps
T1106 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1516741163 Aug 11 07:04:46 PM PDT 24 Aug 11 07:04:49 PM PDT 24 32191285 ps
T1107 /workspace/coverage/cover_reg_top/41.edn_intr_test.4165871921 Aug 11 07:05:07 PM PDT 24 Aug 11 07:05:08 PM PDT 24 58919638 ps
T1108 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1286744398 Aug 11 07:04:54 PM PDT 24 Aug 11 07:04:55 PM PDT 24 16725965 ps
T1109 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1630016705 Aug 11 07:04:55 PM PDT 24 Aug 11 07:04:57 PM PDT 24 180906501 ps
T1110 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3500994459 Aug 11 07:04:35 PM PDT 24 Aug 11 07:04:36 PM PDT 24 176010536 ps
T263 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1758030920 Aug 11 07:04:48 PM PDT 24 Aug 11 07:04:49 PM PDT 24 44182179 ps
T1111 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1152138810 Aug 11 07:04:48 PM PDT 24 Aug 11 07:04:50 PM PDT 24 32019062 ps
T1112 /workspace/coverage/cover_reg_top/39.edn_intr_test.1195483594 Aug 11 07:05:06 PM PDT 24 Aug 11 07:05:07 PM PDT 24 32577352 ps
T1113 /workspace/coverage/cover_reg_top/11.edn_intr_test.1865986639 Aug 11 07:04:48 PM PDT 24 Aug 11 07:04:49 PM PDT 24 14031150 ps
T1114 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2483584526 Aug 11 07:04:30 PM PDT 24 Aug 11 07:04:34 PM PDT 24 326202324 ps
T1115 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3501524926 Aug 11 07:05:02 PM PDT 24 Aug 11 07:05:04 PM PDT 24 158210046 ps
T1116 /workspace/coverage/cover_reg_top/22.edn_intr_test.2672809113 Aug 11 07:05:00 PM PDT 24 Aug 11 07:05:00 PM PDT 24 10596281 ps
T1117 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4113450701 Aug 11 07:05:00 PM PDT 24 Aug 11 07:05:02 PM PDT 24 41315268 ps
T1118 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1242338696 Aug 11 07:04:53 PM PDT 24 Aug 11 07:04:54 PM PDT 24 185073341 ps
T1119 /workspace/coverage/cover_reg_top/42.edn_intr_test.3784682336 Aug 11 07:05:07 PM PDT 24 Aug 11 07:05:08 PM PDT 24 20941987 ps
T1120 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.315170161 Aug 11 07:04:45 PM PDT 24 Aug 11 07:04:46 PM PDT 24 50191898 ps
T1121 /workspace/coverage/cover_reg_top/18.edn_csr_rw.102559194 Aug 11 07:04:58 PM PDT 24 Aug 11 07:04:59 PM PDT 24 54753102 ps
T1122 /workspace/coverage/cover_reg_top/10.edn_intr_test.3382020731 Aug 11 07:04:49 PM PDT 24 Aug 11 07:04:50 PM PDT 24 21965260 ps
T1123 /workspace/coverage/cover_reg_top/31.edn_intr_test.2563719049 Aug 11 07:05:05 PM PDT 24 Aug 11 07:05:06 PM PDT 24 11889782 ps
T1124 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1652229604 Aug 11 07:04:59 PM PDT 24 Aug 11 07:05:00 PM PDT 24 14335890 ps
T1125 /workspace/coverage/cover_reg_top/5.edn_intr_test.1386826096 Aug 11 07:04:43 PM PDT 24 Aug 11 07:04:44 PM PDT 24 13944960 ps
T1126 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.148714896 Aug 11 07:04:54 PM PDT 24 Aug 11 07:04:55 PM PDT 24 144404025 ps
T1127 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1538075104 Aug 11 07:04:22 PM PDT 24 Aug 11 07:04:24 PM PDT 24 63611070 ps
T1128 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2546964124 Aug 11 07:04:23 PM PDT 24 Aug 11 07:04:24 PM PDT 24 45637785 ps
T1129 /workspace/coverage/cover_reg_top/40.edn_intr_test.906495868 Aug 11 07:05:06 PM PDT 24 Aug 11 07:05:07 PM PDT 24 16322706 ps

Test location /workspace/coverage/default/70.edn_genbits.2220036825
Short name T24
Test name
Test status
Simulation time 40821238 ps
CPU time 1.48 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 217272 kb
Host smart-6cd2410a-2b75-455a-8cc6-0a21609e4128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220036825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2220036825
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2125606294
Short name T16
Test name
Test status
Simulation time 958196512 ps
CPU time 5.11 seconds
Started Aug 11 06:25:16 PM PDT 24
Finished Aug 11 06:25:21 PM PDT 24
Peak memory 241936 kb
Host smart-51f5a7fc-9c29-4411-9270-b7052764615c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125606294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2125606294
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.4225954191
Short name T15
Test name
Test status
Simulation time 112157143 ps
CPU time 1.17 seconds
Started Aug 11 06:25:47 PM PDT 24
Finished Aug 11 06:25:48 PM PDT 24
Peak memory 219632 kb
Host smart-2f1a8ef4-158e-4440-b35a-a2dc305b2e50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225954191 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.4225954191
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3390757296
Short name T37
Test name
Test status
Simulation time 60301647488 ps
CPU time 1551.91 seconds
Started Aug 11 06:25:16 PM PDT 24
Finished Aug 11 06:51:08 PM PDT 24
Peak memory 225128 kb
Host smart-beffb7d6-d7ca-4894-bc11-ad0c3c173640
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390757296 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3390757296
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.edn_alert.230404198
Short name T26
Test name
Test status
Simulation time 74309157 ps
CPU time 1.11 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 218328 kb
Host smart-7280ea17-767d-4657-bcf7-8f15c5629d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230404198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.230404198
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/244.edn_genbits.3238062981
Short name T40
Test name
Test status
Simulation time 40196716 ps
CPU time 1.61 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:27:36 PM PDT 24
Peak memory 217400 kb
Host smart-a8d0d246-29fc-4883-b2b6-1e0076e1262c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238062981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3238062981
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_disable.348212773
Short name T86
Test name
Test status
Simulation time 32480370 ps
CPU time 0.85 seconds
Started Aug 11 06:26:31 PM PDT 24
Finished Aug 11 06:26:32 PM PDT 24
Peak memory 216472 kb
Host smart-4dd5d7ce-327f-4be3-9d49-270777e6a605
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348212773 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.348212773
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/185.edn_alert.4126818290
Short name T48
Test name
Test status
Simulation time 41262313 ps
CPU time 1.23 seconds
Started Aug 11 06:27:05 PM PDT 24
Finished Aug 11 06:27:06 PM PDT 24
Peak memory 218664 kb
Host smart-a657942c-5932-45f8-8934-feb4e3dff808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126818290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.4126818290
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.1404471883
Short name T12
Test name
Test status
Simulation time 88747675 ps
CPU time 1.23 seconds
Started Aug 11 06:26:50 PM PDT 24
Finished Aug 11 06:26:51 PM PDT 24
Peak memory 219976 kb
Host smart-f5524b5d-771c-4219-ae41-d77f247ccfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404471883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1404471883
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.1141445125
Short name T107
Test name
Test status
Simulation time 90795878 ps
CPU time 1.27 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 220020 kb
Host smart-1f09a220-79b1-4442-bf96-c4822b581b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141445125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1141445125
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/8.edn_regwen.3604708663
Short name T23
Test name
Test status
Simulation time 17631650 ps
CPU time 1.01 seconds
Started Aug 11 06:25:22 PM PDT 24
Finished Aug 11 06:25:23 PM PDT 24
Peak memory 207088 kb
Host smart-9f4f6e7d-6050-44e7-bc15-c22076d49efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604708663 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3604708663
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/36.edn_alert.573295549
Short name T199
Test name
Test status
Simulation time 81032570 ps
CPU time 1.11 seconds
Started Aug 11 06:25:58 PM PDT 24
Finished Aug 11 06:26:00 PM PDT 24
Peak memory 220732 kb
Host smart-e6b2876f-c9cb-483e-8ccf-735bd9cf951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573295549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.573295549
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.813810067
Short name T120
Test name
Test status
Simulation time 47063159 ps
CPU time 1.17 seconds
Started Aug 11 06:25:25 PM PDT 24
Finished Aug 11 06:25:26 PM PDT 24
Peak memory 218388 kb
Host smart-6910057b-5175-4b63-8fe0-c51c8167e378
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813810067 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.813810067
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.4276222787
Short name T230
Test name
Test status
Simulation time 62339393601 ps
CPU time 242.98 seconds
Started Aug 11 06:25:29 PM PDT 24
Finished Aug 11 06:29:32 PM PDT 24
Peak memory 223644 kb
Host smart-e561c00a-c49d-40e0-9ffb-4007d701d65b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276222787 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.4276222787
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3898642719
Short name T287
Test name
Test status
Simulation time 663602244 ps
CPU time 2.82 seconds
Started Aug 11 07:04:40 PM PDT 24
Finished Aug 11 07:04:43 PM PDT 24
Peak memory 215056 kb
Host smart-3e63ffb9-90a4-4668-80c7-2c8deb860e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898642719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3898642719
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/default/13.edn_genbits.570789176
Short name T2
Test name
Test status
Simulation time 47768470 ps
CPU time 1.41 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:41 PM PDT 24
Peak memory 218780 kb
Host smart-9d2cd332-df28-4a45-a77b-2088e04cc1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570789176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.570789176
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_disable.3138391481
Short name T194
Test name
Test status
Simulation time 32820366 ps
CPU time 0.87 seconds
Started Aug 11 06:25:37 PM PDT 24
Finished Aug 11 06:25:38 PM PDT 24
Peak memory 216428 kb
Host smart-566c98be-2b6a-46ec-bd8b-187b26861ad5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138391481 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3138391481
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/127.edn_alert.2952810772
Short name T89
Test name
Test status
Simulation time 23672620 ps
CPU time 1.14 seconds
Started Aug 11 06:26:48 PM PDT 24
Finished Aug 11 06:26:49 PM PDT 24
Peak memory 219612 kb
Host smart-4b1f9773-c951-4888-a478-1d0f30d6e391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952810772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2952810772
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.440518723
Short name T150
Test name
Test status
Simulation time 62168866 ps
CPU time 0.98 seconds
Started Aug 11 06:25:28 PM PDT 24
Finished Aug 11 06:25:29 PM PDT 24
Peak memory 219460 kb
Host smart-e76b2110-8326-42bb-9cb9-b9f0ccb9e3d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440518723 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.440518723
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_disable.4292992454
Short name T223
Test name
Test status
Simulation time 20221839 ps
CPU time 0.89 seconds
Started Aug 11 06:26:03 PM PDT 24
Finished Aug 11 06:26:04 PM PDT 24
Peak memory 216424 kb
Host smart-9f6a7f03-430b-4ab7-961f-da0b30d3128d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292992454 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.4292992454
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable.1943255126
Short name T221
Test name
Test status
Simulation time 23510353 ps
CPU time 0.9 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:42 PM PDT 24
Peak memory 219120 kb
Host smart-767d1d11-e921-49e9-85b7-7f8ce1d64bf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943255126 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1943255126
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1066205259
Short name T254
Test name
Test status
Simulation time 45666509 ps
CPU time 1.03 seconds
Started Aug 11 07:04:24 PM PDT 24
Finished Aug 11 07:04:25 PM PDT 24
Peak memory 206836 kb
Host smart-250143f9-5efa-4cf2-b949-afa634898718
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066205259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1066205259
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/default/116.edn_alert.1434974686
Short name T78
Test name
Test status
Simulation time 146841981 ps
CPU time 1.12 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:49 PM PDT 24
Peak memory 220592 kb
Host smart-1ffa02ea-80d7-487e-b22a-473f20298563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434974686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1434974686
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/113.edn_alert.2645516212
Short name T333
Test name
Test status
Simulation time 47630168 ps
CPU time 1.17 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 219620 kb
Host smart-1bc0812b-5556-4443-b423-d0690d1dc64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645516212 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2645516212
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/169.edn_alert.824135132
Short name T330
Test name
Test status
Simulation time 65457108 ps
CPU time 1.27 seconds
Started Aug 11 06:27:08 PM PDT 24
Finished Aug 11 06:27:09 PM PDT 24
Peak memory 218236 kb
Host smart-c7aa9869-6266-40ac-9e03-6c6e9989498e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824135132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.824135132
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/175.edn_alert.3993964576
Short name T106
Test name
Test status
Simulation time 55198492 ps
CPU time 1.2 seconds
Started Aug 11 06:26:55 PM PDT 24
Finished Aug 11 06:26:56 PM PDT 24
Peak memory 220012 kb
Host smart-4aafcf18-bd2e-44f9-b1c0-7ebfd0cd12e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993964576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3993964576
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/166.edn_alert.1267827536
Short name T11
Test name
Test status
Simulation time 102329009 ps
CPU time 1.24 seconds
Started Aug 11 06:26:55 PM PDT 24
Finished Aug 11 06:26:56 PM PDT 24
Peak memory 218276 kb
Host smart-3ea98744-c1b3-4042-ada9-a6e9186bd4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267827536 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1267827536
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/118.edn_alert.2345347625
Short name T130
Test name
Test status
Simulation time 47048861 ps
CPU time 1.3 seconds
Started Aug 11 06:26:40 PM PDT 24
Finished Aug 11 06:26:42 PM PDT 24
Peak memory 219796 kb
Host smart-b5477f24-4a56-471b-bc21-f8676f49b4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345347625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2345347625
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert.1786911482
Short name T484
Test name
Test status
Simulation time 69427706 ps
CPU time 1.12 seconds
Started Aug 11 06:25:38 PM PDT 24
Finished Aug 11 06:25:39 PM PDT 24
Peak memory 220704 kb
Host smart-8e9d2fbf-01fd-4a02-8c57-8e02d0c8bbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786911482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1786911482
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2697424121
Short name T88
Test name
Test status
Simulation time 76232665 ps
CPU time 1.03 seconds
Started Aug 11 06:25:42 PM PDT 24
Finished Aug 11 06:25:43 PM PDT 24
Peak memory 218568 kb
Host smart-81e3b5bc-b643-4f4f-971d-3643f242d31e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697424121 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2697424121
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_disable.3877049105
Short name T165
Test name
Test status
Simulation time 12848723 ps
CPU time 0.89 seconds
Started Aug 11 06:26:23 PM PDT 24
Finished Aug 11 06:26:24 PM PDT 24
Peak memory 207312 kb
Host smart-5df9636c-403e-4292-8b8b-232816f52548
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877049105 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3877049105
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/28.edn_intr.7139419
Short name T34
Test name
Test status
Simulation time 63076752 ps
CPU time 0.85 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 215496 kb
Host smart-f0cc56f8-f98a-4fa7-a76e-f2a54a500285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7139419 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.7139419
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_disable.3311630965
Short name T212
Test name
Test status
Simulation time 16561019 ps
CPU time 0.82 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:56 PM PDT 24
Peak memory 216492 kb
Host smart-c4a9ff1c-dab6-485a-8f81-da1c0b1e8b6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311630965 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3311630965
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/185.edn_genbits.231621228
Short name T85
Test name
Test status
Simulation time 46144463 ps
CPU time 1.36 seconds
Started Aug 11 06:27:03 PM PDT 24
Finished Aug 11 06:27:05 PM PDT 24
Peak memory 218728 kb
Host smart-e99fb842-b02a-4cd7-9274-e7db01233f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231621228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.231621228
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.447496894
Short name T883
Test name
Test status
Simulation time 92854404 ps
CPU time 1.26 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 215624 kb
Host smart-c3e6c006-0460-449f-b448-5e6da48c88fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447496894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.447496894
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/12.edn_intr.2246303520
Short name T31
Test name
Test status
Simulation time 22482980 ps
CPU time 1.01 seconds
Started Aug 11 06:25:26 PM PDT 24
Finished Aug 11 06:25:27 PM PDT 24
Peak memory 216172 kb
Host smart-3d2729ea-7097-4ce7-92dd-c74a7183bea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246303520 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2246303520
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/0.edn_err.1847633108
Short name T200
Test name
Test status
Simulation time 35354591 ps
CPU time 1 seconds
Started Aug 11 06:25:18 PM PDT 24
Finished Aug 11 06:25:19 PM PDT 24
Peak memory 229536 kb
Host smart-d4af99c6-5aa7-4633-907f-8e1a925e49f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847633108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1847633108
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2195214185
Short name T155
Test name
Test status
Simulation time 55723623 ps
CPU time 1.22 seconds
Started Aug 11 06:25:15 PM PDT 24
Finished Aug 11 06:25:16 PM PDT 24
Peak memory 219524 kb
Host smart-b098b579-9701-448a-8ab8-dbd3fe7c9837
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195214185 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2195214185
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_alert.1879308179
Short name T98
Test name
Test status
Simulation time 31636857 ps
CPU time 1.33 seconds
Started Aug 11 06:25:23 PM PDT 24
Finished Aug 11 06:25:24 PM PDT 24
Peak memory 219912 kb
Host smart-7d2e0f34-e535-409a-b31d-bd4d8e8c71d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879308179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1879308179
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/100.edn_alert.2762021408
Short name T136
Test name
Test status
Simulation time 33000700 ps
CPU time 1.28 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:38 PM PDT 24
Peak memory 219520 kb
Host smart-5d2f9ce5-0e3f-43da-a33c-d2bda0ba6652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762021408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2762021408
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.4274752810
Short name T203
Test name
Test status
Simulation time 87785014 ps
CPU time 1.12 seconds
Started Aug 11 06:25:31 PM PDT 24
Finished Aug 11 06:25:32 PM PDT 24
Peak memory 215560 kb
Host smart-b1ec9e07-602c-41e7-a294-e50743948e2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274752810 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.4274752810
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3843303966
Short name T805
Test name
Test status
Simulation time 49758783 ps
CPU time 1.54 seconds
Started Aug 11 06:25:30 PM PDT 24
Finished Aug 11 06:25:32 PM PDT 24
Peak memory 217148 kb
Host smart-d6eb24df-a4c8-4049-a2e1-1175b505d4e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843303966 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3843303966
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/131.edn_alert.411367627
Short name T479
Test name
Test status
Simulation time 296606667 ps
CPU time 1.44 seconds
Started Aug 11 06:26:51 PM PDT 24
Finished Aug 11 06:26:53 PM PDT 24
Peak memory 220464 kb
Host smart-ef67aff7-3e07-4af1-b6ce-93ae39f503fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411367627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.411367627
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/143.edn_alert.48075469
Short name T80
Test name
Test status
Simulation time 32162864 ps
CPU time 1.18 seconds
Started Aug 11 06:26:49 PM PDT 24
Finished Aug 11 06:26:50 PM PDT 24
Peak memory 218264 kb
Host smart-972b72a6-0cb6-443c-b543-2080fbbe0b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48075469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.48075469
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/26.edn_disable.4097898183
Short name T217
Test name
Test status
Simulation time 11616000 ps
CPU time 0.92 seconds
Started Aug 11 06:25:47 PM PDT 24
Finished Aug 11 06:25:48 PM PDT 24
Peak memory 215516 kb
Host smart-20e59c62-69d8-45cb-8123-5da5dad9e2e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097898183 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4097898183
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable.541406040
Short name T193
Test name
Test status
Simulation time 15986385 ps
CPU time 0.91 seconds
Started Aug 11 06:25:13 PM PDT 24
Finished Aug 11 06:25:14 PM PDT 24
Peak memory 219260 kb
Host smart-4e0ab061-7fd9-46f8-b3ce-5102296e6e36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541406040 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.541406040
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable.3070402245
Short name T202
Test name
Test status
Simulation time 12654459 ps
CPU time 0.88 seconds
Started Aug 11 06:26:21 PM PDT 24
Finished Aug 11 06:26:22 PM PDT 24
Peak memory 216656 kb
Host smart-492e295d-7efe-4a1a-ab2b-6541cdfdbdf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070402245 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3070402245
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/61.edn_err.3545926506
Short name T188
Test name
Test status
Simulation time 19239032 ps
CPU time 1.06 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:38 PM PDT 24
Peak memory 218672 kb
Host smart-a4a6a661-bd5b-4fa8-bc6f-7dce8d454332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545926506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3545926506
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/178.edn_genbits.3711975827
Short name T295
Test name
Test status
Simulation time 161276612 ps
CPU time 2.28 seconds
Started Aug 11 06:27:11 PM PDT 24
Finished Aug 11 06:27:13 PM PDT 24
Peak memory 219216 kb
Host smart-a5235615-2a6c-439d-a943-bd7d1597148d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711975827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3711975827
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_genbits.2590170317
Short name T293
Test name
Test status
Simulation time 39947851 ps
CPU time 1.68 seconds
Started Aug 11 06:25:38 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 220212 kb
Host smart-1c0e9c5c-3a26-496f-aaf6-789406c56186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590170317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2590170317
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.3315889891
Short name T66
Test name
Test status
Simulation time 44938734 ps
CPU time 0.87 seconds
Started Aug 11 06:25:30 PM PDT 24
Finished Aug 11 06:25:31 PM PDT 24
Peak memory 215204 kb
Host smart-c3b9772a-61b5-4bb5-8ec1-d7f5038981d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315889891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3315889891
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_genbits.2000019861
Short name T687
Test name
Test status
Simulation time 77090452 ps
CPU time 1.27 seconds
Started Aug 11 06:25:46 PM PDT 24
Finished Aug 11 06:25:47 PM PDT 24
Peak memory 217672 kb
Host smart-14be4833-3d97-4052-854d-7a47c999b2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000019861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2000019861
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3228566243
Short name T35
Test name
Test status
Simulation time 24529480 ps
CPU time 0.96 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:56 PM PDT 24
Peak memory 216304 kb
Host smart-5912f39c-4c88-4e72-938f-f335f431dfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228566243 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3228566243
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/67.edn_alert.1501141725
Short name T334
Test name
Test status
Simulation time 35727252 ps
CPU time 1.23 seconds
Started Aug 11 06:26:25 PM PDT 24
Finished Aug 11 06:26:27 PM PDT 24
Peak memory 215552 kb
Host smart-71ac2837-f187-4d17-834e-afed212d5ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501141725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1501141725
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/10.edn_genbits.1155977124
Short name T348
Test name
Test status
Simulation time 63455942 ps
CPU time 1.84 seconds
Started Aug 11 06:25:24 PM PDT 24
Finished Aug 11 06:25:26 PM PDT 24
Peak memory 218856 kb
Host smart-ef28b9d3-bcd9-4464-a45c-08860a5241e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155977124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1155977124
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2774537785
Short name T357
Test name
Test status
Simulation time 143812522 ps
CPU time 1.46 seconds
Started Aug 11 06:26:48 PM PDT 24
Finished Aug 11 06:26:49 PM PDT 24
Peak memory 217664 kb
Host smart-68f18980-c16a-4dad-8d26-5548a6b2910e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774537785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2774537785
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1758030920
Short name T263
Test name
Test status
Simulation time 44182179 ps
CPU time 0.95 seconds
Started Aug 11 07:04:48 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 206840 kb
Host smart-a0e3e76c-b4fe-4b53-8c61-c7af55ea8223
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758030920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1758030920
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3343285274
Short name T268
Test name
Test status
Simulation time 78469245 ps
CPU time 1.21 seconds
Started Aug 11 07:04:52 PM PDT 24
Finished Aug 11 07:04:54 PM PDT 24
Peak memory 206936 kb
Host smart-b90be48f-ba16-4e1c-8910-8b05974f5606
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343285274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3343285274
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.349875446
Short name T292
Test name
Test status
Simulation time 206014189 ps
CPU time 1.66 seconds
Started Aug 11 07:04:48 PM PDT 24
Finished Aug 11 07:04:50 PM PDT 24
Peak memory 206908 kb
Host smart-0bd68fa7-6a25-4579-92b6-59734380d9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349875446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.349875446
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.873060297
Short name T572
Test name
Test status
Simulation time 108893222849 ps
CPU time 622.54 seconds
Started Aug 11 06:25:12 PM PDT 24
Finished Aug 11 06:35:35 PM PDT 24
Peak memory 219792 kb
Host smart-38247e64-e4fa-4acf-83a7-fde9832429ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873060297 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.873060297
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_stress_all.3425669173
Short name T938
Test name
Test status
Simulation time 31102678 ps
CPU time 1.03 seconds
Started Aug 11 06:25:15 PM PDT 24
Finished Aug 11 06:25:16 PM PDT 24
Peak memory 207108 kb
Host smart-67d9be2d-f422-4ead-9817-5be88e5f2678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425669173 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3425669173
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/102.edn_genbits.1316118230
Short name T324
Test name
Test status
Simulation time 109575938 ps
CPU time 2.11 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 219848 kb
Host smart-0d95c35e-8dfb-4333-b1ed-be2487ca9d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316118230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1316118230
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/110.edn_genbits.3662016764
Short name T367
Test name
Test status
Simulation time 50434234 ps
CPU time 1.51 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 219140 kb
Host smart-cf34cf28-815a-49e0-9757-43379cb537bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662016764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3662016764
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_genbits.2608153244
Short name T244
Test name
Test status
Simulation time 82522846 ps
CPU time 1.17 seconds
Started Aug 11 06:25:25 PM PDT 24
Finished Aug 11 06:25:26 PM PDT 24
Peak memory 215284 kb
Host smart-876068f0-24d9-4b1a-b0a8-1de183dc43d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608153244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2608153244
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3676361178
Short name T306
Test name
Test status
Simulation time 61233048 ps
CPU time 1.44 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 218744 kb
Host smart-f68891eb-c2ed-4339-a324-782f10badac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676361178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3676361178
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1762448207
Short name T312
Test name
Test status
Simulation time 50073598 ps
CPU time 1.79 seconds
Started Aug 11 06:26:50 PM PDT 24
Finished Aug 11 06:26:51 PM PDT 24
Peak memory 218812 kb
Host smart-7ff19617-b2e2-4d0b-b4da-12ce74e139c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762448207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1762448207
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.129530758
Short name T302
Test name
Test status
Simulation time 50503308 ps
CPU time 1.24 seconds
Started Aug 11 06:26:51 PM PDT 24
Finished Aug 11 06:26:52 PM PDT 24
Peak memory 218712 kb
Host smart-38cd9370-3c36-4230-9099-a6b96afcfcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129530758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.129530758
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2480500212
Short name T323
Test name
Test status
Simulation time 47583516 ps
CPU time 1.67 seconds
Started Aug 11 06:26:55 PM PDT 24
Finished Aug 11 06:26:57 PM PDT 24
Peak memory 218576 kb
Host smart-52823a5d-cc60-4bc9-86a4-913a8356f7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480500212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2480500212
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/190.edn_genbits.1335580080
Short name T58
Test name
Test status
Simulation time 46216445 ps
CPU time 1.16 seconds
Started Aug 11 06:27:23 PM PDT 24
Finished Aug 11 06:27:24 PM PDT 24
Peak memory 217396 kb
Host smart-a3ca2c09-0ae1-4a15-a3e9-ec950f2bb8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335580080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1335580080
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1360024574
Short name T30
Test name
Test status
Simulation time 30824265 ps
CPU time 0.85 seconds
Started Aug 11 06:25:38 PM PDT 24
Finished Aug 11 06:25:39 PM PDT 24
Peak memory 215880 kb
Host smart-dd18e85d-9606-4847-bddb-79bbe73267c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360024574 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1360024574
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/47.edn_err.1047015941
Short name T111
Test name
Test status
Simulation time 26942206 ps
CPU time 1.36 seconds
Started Aug 11 06:26:29 PM PDT 24
Finished Aug 11 06:26:30 PM PDT 24
Peak memory 229644 kb
Host smart-30934951-210b-42b5-9b1d-048d51e4d2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047015941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1047015941
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/13.edn_alert.2269099785
Short name T115
Test name
Test status
Simulation time 30237503 ps
CPU time 1.35 seconds
Started Aug 11 06:25:32 PM PDT 24
Finished Aug 11 06:25:34 PM PDT 24
Peak memory 220472 kb
Host smart-62bf7173-b586-4b11-9055-2abdb5191be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269099785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2269099785
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1100143355
Short name T1042
Test name
Test status
Simulation time 18335592 ps
CPU time 1.31 seconds
Started Aug 11 07:04:25 PM PDT 24
Finished Aug 11 07:04:27 PM PDT 24
Peak memory 206888 kb
Host smart-46f455f0-08fa-4a42-9b22-d8cee5a53505
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100143355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1100143355
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1538075104
Short name T1127
Test name
Test status
Simulation time 63611070 ps
CPU time 2.01 seconds
Started Aug 11 07:04:22 PM PDT 24
Finished Aug 11 07:04:24 PM PDT 24
Peak memory 206884 kb
Host smart-edaccca9-0bfa-4519-b649-b79625330fdf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538075104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1538075104
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1553430485
Short name T1052
Test name
Test status
Simulation time 15172167 ps
CPU time 0.99 seconds
Started Aug 11 07:04:23 PM PDT 24
Finished Aug 11 07:04:24 PM PDT 24
Peak memory 206820 kb
Host smart-20bf102e-7d14-4ccd-8781-ab894b386fdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553430485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1553430485
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2506439041
Short name T1102
Test name
Test status
Simulation time 40278266 ps
CPU time 1.34 seconds
Started Aug 11 07:04:22 PM PDT 24
Finished Aug 11 07:04:24 PM PDT 24
Peak memory 215232 kb
Host smart-71eefaf0-3f05-4890-840d-8f82cde41561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506439041 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2506439041
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2964356102
Short name T261
Test name
Test status
Simulation time 18508092 ps
CPU time 0.84 seconds
Started Aug 11 07:04:25 PM PDT 24
Finished Aug 11 07:04:26 PM PDT 24
Peak memory 206616 kb
Host smart-3041e117-f41e-4cf3-aaf4-75575d401b3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964356102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2964356102
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2720127342
Short name T1010
Test name
Test status
Simulation time 55545421 ps
CPU time 0.8 seconds
Started Aug 11 07:04:23 PM PDT 24
Finished Aug 11 07:04:24 PM PDT 24
Peak memory 206580 kb
Host smart-f480adca-8c38-4dd8-bcf0-a86978020509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720127342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2720127342
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1474142408
Short name T1078
Test name
Test status
Simulation time 63040618 ps
CPU time 1.38 seconds
Started Aug 11 07:04:22 PM PDT 24
Finished Aug 11 07:04:23 PM PDT 24
Peak memory 206892 kb
Host smart-33bb4041-afd0-44b2-a4a4-e735b15ab7b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474142408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1474142408
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.4082740333
Short name T1034
Test name
Test status
Simulation time 49243089 ps
CPU time 3.22 seconds
Started Aug 11 07:04:17 PM PDT 24
Finished Aug 11 07:04:20 PM PDT 24
Peak memory 215120 kb
Host smart-fb805034-63c8-4726-aa40-4e516c7350f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082740333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.4082740333
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.831211218
Short name T286
Test name
Test status
Simulation time 97020623 ps
CPU time 2.62 seconds
Started Aug 11 07:04:19 PM PDT 24
Finished Aug 11 07:04:21 PM PDT 24
Peak memory 206980 kb
Host smart-1454f5f0-1aa1-46a3-941d-22ef0dd0146f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831211218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.831211218
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3479218236
Short name T1083
Test name
Test status
Simulation time 57520652 ps
CPU time 3.37 seconds
Started Aug 11 07:04:25 PM PDT 24
Finished Aug 11 07:04:28 PM PDT 24
Peak memory 206920 kb
Host smart-5217e8c3-9994-430b-9054-3509d74c815e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479218236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3479218236
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1855096354
Short name T1051
Test name
Test status
Simulation time 22306589 ps
CPU time 0.81 seconds
Started Aug 11 07:04:22 PM PDT 24
Finished Aug 11 07:04:23 PM PDT 24
Peak memory 206776 kb
Host smart-1f646086-4581-4f99-87a6-c84aaf709e58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855096354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1855096354
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1764463415
Short name T1015
Test name
Test status
Simulation time 56996411 ps
CPU time 1.12 seconds
Started Aug 11 07:04:28 PM PDT 24
Finished Aug 11 07:04:29 PM PDT 24
Peak memory 215200 kb
Host smart-585b91a5-aa20-42ce-aa92-efe0928562c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764463415 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1764463415
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2546964124
Short name T1128
Test name
Test status
Simulation time 45637785 ps
CPU time 0.93 seconds
Started Aug 11 07:04:23 PM PDT 24
Finished Aug 11 07:04:24 PM PDT 24
Peak memory 206848 kb
Host smart-9827096a-de73-4d44-aa89-e496aea455c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546964124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2546964124
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3259780130
Short name T1018
Test name
Test status
Simulation time 38855588 ps
CPU time 0.83 seconds
Started Aug 11 07:04:23 PM PDT 24
Finished Aug 11 07:04:24 PM PDT 24
Peak memory 206696 kb
Host smart-d084c9b3-c941-4314-b95a-4200a6be972d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259780130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3259780130
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1946332839
Short name T1053
Test name
Test status
Simulation time 131047557 ps
CPU time 0.95 seconds
Started Aug 11 07:04:30 PM PDT 24
Finished Aug 11 07:04:31 PM PDT 24
Peak memory 206888 kb
Host smart-4f0e5f16-6132-4c68-80bc-1218a428c14a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946332839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1946332839
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2727494299
Short name T1027
Test name
Test status
Simulation time 143655252 ps
CPU time 2.64 seconds
Started Aug 11 07:04:22 PM PDT 24
Finished Aug 11 07:04:25 PM PDT 24
Peak memory 215072 kb
Host smart-8a7e4171-551d-47ad-8527-914a8dfa5c34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727494299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2727494299
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1695661759
Short name T285
Test name
Test status
Simulation time 159401829 ps
CPU time 1.53 seconds
Started Aug 11 07:04:23 PM PDT 24
Finished Aug 11 07:04:25 PM PDT 24
Peak memory 207092 kb
Host smart-d0e9a721-7cc8-45e8-9cc8-c84d5c2b2f1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695661759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1695661759
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2859782748
Short name T1031
Test name
Test status
Simulation time 23779545 ps
CPU time 1.18 seconds
Started Aug 11 07:04:47 PM PDT 24
Finished Aug 11 07:04:48 PM PDT 24
Peak memory 216916 kb
Host smart-186ab92b-c6bb-46da-a5f4-1bb176290a01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859782748 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2859782748
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.459708505
Short name T1021
Test name
Test status
Simulation time 22932174 ps
CPU time 0.95 seconds
Started Aug 11 07:04:48 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 206876 kb
Host smart-d5ef43b9-2cc1-460a-bec4-34afb727ecdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459708505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.459708505
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3382020731
Short name T1122
Test name
Test status
Simulation time 21965260 ps
CPU time 0.89 seconds
Started Aug 11 07:04:49 PM PDT 24
Finished Aug 11 07:04:50 PM PDT 24
Peak memory 206704 kb
Host smart-403f9347-1f45-4536-849c-3106aaceab17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382020731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3382020731
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4229162180
Short name T1089
Test name
Test status
Simulation time 51219848 ps
CPU time 1.03 seconds
Started Aug 11 07:04:47 PM PDT 24
Finished Aug 11 07:04:48 PM PDT 24
Peak memory 206940 kb
Host smart-5cfc3e65-695c-4d0c-a484-46eef1668d0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229162180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.4229162180
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1152138810
Short name T1111
Test name
Test status
Simulation time 32019062 ps
CPU time 1.72 seconds
Started Aug 11 07:04:48 PM PDT 24
Finished Aug 11 07:04:50 PM PDT 24
Peak memory 215124 kb
Host smart-062c404b-3e9a-44c3-b6c2-1d1c536e60bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152138810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1152138810
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1701000945
Short name T278
Test name
Test status
Simulation time 174567716 ps
CPU time 1.64 seconds
Started Aug 11 07:04:47 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 206916 kb
Host smart-f8cf6f2b-5f49-4076-b11f-c1debb7aa00d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701000945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1701000945
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1366628066
Short name T1044
Test name
Test status
Simulation time 55656646 ps
CPU time 1.45 seconds
Started Aug 11 07:04:46 PM PDT 24
Finished Aug 11 07:04:48 PM PDT 24
Peak memory 215232 kb
Host smart-71c5478b-8b7d-4fab-83c2-5ff55aa07fd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366628066 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1366628066
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1865986639
Short name T1113
Test name
Test status
Simulation time 14031150 ps
CPU time 0.86 seconds
Started Aug 11 07:04:48 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 206668 kb
Host smart-8a846bed-87f7-435f-9965-0940125436f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865986639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1865986639
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1957162527
Short name T1069
Test name
Test status
Simulation time 16115484 ps
CPU time 1.05 seconds
Started Aug 11 07:04:47 PM PDT 24
Finished Aug 11 07:04:48 PM PDT 24
Peak memory 206956 kb
Host smart-d04051ad-83fc-404e-8a77-8e1bdebbda18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957162527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1957162527
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.343044447
Short name T1023
Test name
Test status
Simulation time 251609827 ps
CPU time 2.49 seconds
Started Aug 11 07:04:46 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 215096 kb
Host smart-6e66d7ef-41b8-45af-bf5b-e5c289d4ed59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343044447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.343044447
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1176073189
Short name T1071
Test name
Test status
Simulation time 80896288 ps
CPU time 1.09 seconds
Started Aug 11 07:04:53 PM PDT 24
Finished Aug 11 07:04:54 PM PDT 24
Peak memory 216728 kb
Host smart-6d49004e-61e7-4892-ae97-9536fa2b8a3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176073189 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1176073189
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1801458854
Short name T262
Test name
Test status
Simulation time 25748982 ps
CPU time 0.91 seconds
Started Aug 11 07:04:52 PM PDT 24
Finished Aug 11 07:04:53 PM PDT 24
Peak memory 206828 kb
Host smart-9334a6d1-56a6-485a-a2e2-b7d5a91a85a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801458854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1801458854
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1278975213
Short name T1009
Test name
Test status
Simulation time 20703175 ps
CPU time 0.81 seconds
Started Aug 11 07:04:52 PM PDT 24
Finished Aug 11 07:04:53 PM PDT 24
Peak memory 206500 kb
Host smart-c53a6ff9-afbb-4abe-9f55-93a7aaf3235f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278975213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1278975213
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1516741163
Short name T1106
Test name
Test status
Simulation time 32191285 ps
CPU time 2.04 seconds
Started Aug 11 07:04:46 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 215200 kb
Host smart-8082428d-b646-46fb-b434-f0d2e24e0c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516741163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1516741163
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1630016705
Short name T1109
Test name
Test status
Simulation time 180906501 ps
CPU time 2.49 seconds
Started Aug 11 07:04:55 PM PDT 24
Finished Aug 11 07:04:57 PM PDT 24
Peak memory 215184 kb
Host smart-81564f5a-0999-4e79-97e5-c9b843a35199
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630016705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1630016705
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1951180373
Short name T1103
Test name
Test status
Simulation time 84626379 ps
CPU time 1.91 seconds
Started Aug 11 07:04:55 PM PDT 24
Finished Aug 11 07:04:57 PM PDT 24
Peak memory 215184 kb
Host smart-41de1180-bc53-4935-8b04-4f1e1b509231
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951180373 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1951180373
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1370111131
Short name T251
Test name
Test status
Simulation time 21712506 ps
CPU time 0.89 seconds
Started Aug 11 07:04:57 PM PDT 24
Finished Aug 11 07:04:58 PM PDT 24
Peak memory 206840 kb
Host smart-3374d873-dab1-4f6c-b04e-c382cee87d23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370111131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1370111131
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3258877971
Short name T1020
Test name
Test status
Simulation time 19737337 ps
CPU time 0.84 seconds
Started Aug 11 07:04:53 PM PDT 24
Finished Aug 11 07:04:54 PM PDT 24
Peak memory 206492 kb
Host smart-7ffbdc90-c585-4083-af61-f152fa5369b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258877971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3258877971
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3969547462
Short name T1088
Test name
Test status
Simulation time 21283877 ps
CPU time 1.1 seconds
Started Aug 11 07:04:51 PM PDT 24
Finished Aug 11 07:04:53 PM PDT 24
Peak memory 206932 kb
Host smart-674f8671-125b-4de8-aecd-c13a5484d3ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969547462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3969547462
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2834396304
Short name T1090
Test name
Test status
Simulation time 438738328 ps
CPU time 4.07 seconds
Started Aug 11 07:04:53 PM PDT 24
Finished Aug 11 07:04:57 PM PDT 24
Peak memory 215488 kb
Host smart-6ead97d3-b124-4d50-9198-e464482de4de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834396304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2834396304
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1242338696
Short name T1118
Test name
Test status
Simulation time 185073341 ps
CPU time 1.63 seconds
Started Aug 11 07:04:53 PM PDT 24
Finished Aug 11 07:04:54 PM PDT 24
Peak memory 207040 kb
Host smart-a7737452-a29d-4a96-b94d-8982e076d023
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242338696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1242338696
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1286744398
Short name T1108
Test name
Test status
Simulation time 16725965 ps
CPU time 0.98 seconds
Started Aug 11 07:04:54 PM PDT 24
Finished Aug 11 07:04:55 PM PDT 24
Peak memory 206916 kb
Host smart-1d49a0e1-41e6-43d5-a7f9-7dedb0f728ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286744398 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1286744398
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2018959473
Short name T1091
Test name
Test status
Simulation time 35966970 ps
CPU time 0.81 seconds
Started Aug 11 07:04:53 PM PDT 24
Finished Aug 11 07:04:54 PM PDT 24
Peak memory 206644 kb
Host smart-0995dec5-fde6-4e4d-a9aa-24aac5be9f79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018959473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2018959473
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1614502748
Short name T999
Test name
Test status
Simulation time 29397079 ps
CPU time 0.81 seconds
Started Aug 11 07:04:53 PM PDT 24
Finished Aug 11 07:04:54 PM PDT 24
Peak memory 206548 kb
Host smart-9ee8829f-ad79-4af4-9b06-cfc5e63c913d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614502748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1614502748
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2021447812
Short name T1064
Test name
Test status
Simulation time 485453859 ps
CPU time 1.51 seconds
Started Aug 11 07:04:55 PM PDT 24
Finished Aug 11 07:04:56 PM PDT 24
Peak memory 206940 kb
Host smart-f7a8206a-c60b-4c0f-bfb3-4d2ca0b30433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021447812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2021447812
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2316918012
Short name T1004
Test name
Test status
Simulation time 144105493 ps
CPU time 4.61 seconds
Started Aug 11 07:04:53 PM PDT 24
Finished Aug 11 07:04:57 PM PDT 24
Peak memory 215104 kb
Host smart-0315e986-4e87-46b8-ba6e-6bb5f351ff4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316918012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2316918012
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.148714896
Short name T1126
Test name
Test status
Simulation time 144404025 ps
CPU time 1.5 seconds
Started Aug 11 07:04:54 PM PDT 24
Finished Aug 11 07:04:55 PM PDT 24
Peak memory 206968 kb
Host smart-cc1c3cc1-adf1-4565-ae60-4b4e7938fae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148714896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.148714896
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1652229604
Short name T1124
Test name
Test status
Simulation time 14335890 ps
CPU time 0.98 seconds
Started Aug 11 07:04:59 PM PDT 24
Finished Aug 11 07:05:00 PM PDT 24
Peak memory 206984 kb
Host smart-3c4f5cbe-552b-4a1c-925e-ca41936ed47d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652229604 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1652229604
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.4059952154
Short name T259
Test name
Test status
Simulation time 18604486 ps
CPU time 0.92 seconds
Started Aug 11 07:04:54 PM PDT 24
Finished Aug 11 07:04:55 PM PDT 24
Peak memory 206800 kb
Host smart-19cdb803-8c1d-4ad4-839b-fd894a3f19a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059952154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.4059952154
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1153820598
Short name T1086
Test name
Test status
Simulation time 21709985 ps
CPU time 0.86 seconds
Started Aug 11 07:04:53 PM PDT 24
Finished Aug 11 07:04:54 PM PDT 24
Peak memory 206696 kb
Host smart-6907ff48-b060-4f53-b5c1-cfefe488066c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153820598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1153820598
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2735350390
Short name T1061
Test name
Test status
Simulation time 76120929 ps
CPU time 1.49 seconds
Started Aug 11 07:04:53 PM PDT 24
Finished Aug 11 07:04:55 PM PDT 24
Peak memory 206876 kb
Host smart-201d11d8-6153-4ed8-9b5c-bc730b721fff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735350390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2735350390
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.118624913
Short name T1063
Test name
Test status
Simulation time 285744848 ps
CPU time 4.6 seconds
Started Aug 11 07:04:52 PM PDT 24
Finished Aug 11 07:04:57 PM PDT 24
Peak memory 215024 kb
Host smart-5503229b-256e-41cf-aaff-a35e1014478e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118624913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.118624913
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1319266839
Short name T1099
Test name
Test status
Simulation time 385468721 ps
CPU time 2.51 seconds
Started Aug 11 07:04:53 PM PDT 24
Finished Aug 11 07:04:55 PM PDT 24
Peak memory 215140 kb
Host smart-99b19bb2-5368-47e2-a9c4-11ec1019cbb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319266839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1319266839
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4113450701
Short name T1117
Test name
Test status
Simulation time 41315268 ps
CPU time 1.58 seconds
Started Aug 11 07:05:00 PM PDT 24
Finished Aug 11 07:05:02 PM PDT 24
Peak memory 215196 kb
Host smart-5fc068d8-658e-4abc-b865-797ecba67db3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113450701 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.4113450701
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1124880503
Short name T267
Test name
Test status
Simulation time 15759021 ps
CPU time 0.88 seconds
Started Aug 11 07:05:01 PM PDT 24
Finished Aug 11 07:05:02 PM PDT 24
Peak memory 206756 kb
Host smart-c4969433-e5bc-436e-bb0e-cef1e7bbc7de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124880503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1124880503
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3299093225
Short name T1081
Test name
Test status
Simulation time 63331170 ps
CPU time 0.8 seconds
Started Aug 11 07:05:00 PM PDT 24
Finished Aug 11 07:05:01 PM PDT 24
Peak memory 206708 kb
Host smart-db601b81-2044-40ea-97e9-20e545dce3a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299093225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3299093225
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3501524926
Short name T1115
Test name
Test status
Simulation time 158210046 ps
CPU time 1.5 seconds
Started Aug 11 07:05:02 PM PDT 24
Finished Aug 11 07:05:04 PM PDT 24
Peak memory 206944 kb
Host smart-186d847d-128e-426d-b760-63779b600ec7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501524926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3501524926
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1787984301
Short name T1087
Test name
Test status
Simulation time 132552406 ps
CPU time 2.65 seconds
Started Aug 11 07:05:00 PM PDT 24
Finished Aug 11 07:05:03 PM PDT 24
Peak memory 215148 kb
Host smart-ae986232-5368-48cd-83b7-f05426cf8195
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787984301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1787984301
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4164115985
Short name T1068
Test name
Test status
Simulation time 60665006 ps
CPU time 1.83 seconds
Started Aug 11 07:05:00 PM PDT 24
Finished Aug 11 07:05:02 PM PDT 24
Peak memory 206884 kb
Host smart-5cd61f72-2783-4794-bb57-3649fa68b072
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164115985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4164115985
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3373650072
Short name T1070
Test name
Test status
Simulation time 54736012 ps
CPU time 1.24 seconds
Started Aug 11 07:05:01 PM PDT 24
Finished Aug 11 07:05:02 PM PDT 24
Peak memory 215244 kb
Host smart-8a06201c-01ba-4e36-ab4b-42a789bcd414
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373650072 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3373650072
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2819504347
Short name T1005
Test name
Test status
Simulation time 18801521 ps
CPU time 0.99 seconds
Started Aug 11 07:05:04 PM PDT 24
Finished Aug 11 07:05:05 PM PDT 24
Peak memory 206840 kb
Host smart-92e0fa66-cdb4-4cd1-9c47-fab5a1f0744f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819504347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2819504347
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1120000235
Short name T1028
Test name
Test status
Simulation time 45681930 ps
CPU time 0.89 seconds
Started Aug 11 07:05:01 PM PDT 24
Finished Aug 11 07:05:02 PM PDT 24
Peak memory 206856 kb
Host smart-9045ecfd-58d8-4611-8fc1-0f098f61d498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120000235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1120000235
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3804866701
Short name T252
Test name
Test status
Simulation time 199454624 ps
CPU time 1.34 seconds
Started Aug 11 07:05:00 PM PDT 24
Finished Aug 11 07:05:01 PM PDT 24
Peak memory 206976 kb
Host smart-5498b342-8595-4a65-b4ff-b44148ff781c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804866701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3804866701
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.482703237
Short name T1013
Test name
Test status
Simulation time 192989627 ps
CPU time 2.3 seconds
Started Aug 11 07:04:59 PM PDT 24
Finished Aug 11 07:05:01 PM PDT 24
Peak memory 215116 kb
Host smart-bb8e634d-5466-47ac-b811-38a7a52b566d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482703237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.482703237
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2182030192
Short name T291
Test name
Test status
Simulation time 117604846 ps
CPU time 2.89 seconds
Started Aug 11 07:05:05 PM PDT 24
Finished Aug 11 07:05:08 PM PDT 24
Peak memory 206904 kb
Host smart-1d10edff-7f94-4bae-871a-f4e3c4c8a9b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182030192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2182030192
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2078826690
Short name T1032
Test name
Test status
Simulation time 193262066 ps
CPU time 1.53 seconds
Started Aug 11 07:05:05 PM PDT 24
Finished Aug 11 07:05:07 PM PDT 24
Peak memory 215176 kb
Host smart-e891d0a4-189f-4d99-a5ac-301809bb5945
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078826690 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2078826690
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.102559194
Short name T1121
Test name
Test status
Simulation time 54753102 ps
CPU time 0.79 seconds
Started Aug 11 07:04:58 PM PDT 24
Finished Aug 11 07:04:59 PM PDT 24
Peak memory 206600 kb
Host smart-842ad072-0f64-4017-98f2-58abd65ebacd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102559194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.102559194
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4177120892
Short name T1076
Test name
Test status
Simulation time 43280790 ps
CPU time 0.85 seconds
Started Aug 11 07:05:02 PM PDT 24
Finished Aug 11 07:05:03 PM PDT 24
Peak memory 206716 kb
Host smart-8f348782-c3b8-4b77-a28e-f245ea449428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177120892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4177120892
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3658068903
Short name T1084
Test name
Test status
Simulation time 18913005 ps
CPU time 1.14 seconds
Started Aug 11 07:05:02 PM PDT 24
Finished Aug 11 07:05:04 PM PDT 24
Peak memory 206948 kb
Host smart-23da8bfe-a005-434e-9c56-d86ac1a3305c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658068903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3658068903
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3967578549
Short name T1097
Test name
Test status
Simulation time 81379854 ps
CPU time 3.16 seconds
Started Aug 11 07:04:59 PM PDT 24
Finished Aug 11 07:05:02 PM PDT 24
Peak memory 215120 kb
Host smart-0959123b-eb7b-4325-976f-fe4c78b3f340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967578549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3967578549
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3284165448
Short name T288
Test name
Test status
Simulation time 48433578 ps
CPU time 1.67 seconds
Started Aug 11 07:05:01 PM PDT 24
Finished Aug 11 07:05:03 PM PDT 24
Peak memory 207136 kb
Host smart-66c7e7b1-b117-43f6-bff2-ef8ce8942844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284165448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3284165448
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4019432487
Short name T1036
Test name
Test status
Simulation time 43077751 ps
CPU time 1.18 seconds
Started Aug 11 07:04:59 PM PDT 24
Finished Aug 11 07:05:00 PM PDT 24
Peak memory 215232 kb
Host smart-ec2cbf6b-e1c7-43a5-ad14-d6e91fbacf28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019432487 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.4019432487
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1451183339
Short name T1065
Test name
Test status
Simulation time 31717622 ps
CPU time 0.85 seconds
Started Aug 11 07:05:01 PM PDT 24
Finished Aug 11 07:05:02 PM PDT 24
Peak memory 206784 kb
Host smart-b7432f3f-6ac8-4922-8344-8d9ef21f8c0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451183339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1451183339
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3042956225
Short name T1039
Test name
Test status
Simulation time 14531139 ps
CPU time 0.84 seconds
Started Aug 11 07:05:00 PM PDT 24
Finished Aug 11 07:05:01 PM PDT 24
Peak memory 206744 kb
Host smart-775721cf-421b-4620-b7d2-6ecfeb8cb3fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042956225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3042956225
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3604701250
Short name T269
Test name
Test status
Simulation time 13975460 ps
CPU time 0.95 seconds
Started Aug 11 07:05:02 PM PDT 24
Finished Aug 11 07:05:03 PM PDT 24
Peak memory 206916 kb
Host smart-3fb5e4fe-0a9c-4305-b62a-415b92ad6b0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604701250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3604701250
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.530886150
Short name T1058
Test name
Test status
Simulation time 24198409 ps
CPU time 1.66 seconds
Started Aug 11 07:05:01 PM PDT 24
Finished Aug 11 07:05:03 PM PDT 24
Peak memory 215184 kb
Host smart-62704345-3be1-497d-a4a4-5ce2b69eca17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530886150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.530886150
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.229264207
Short name T290
Test name
Test status
Simulation time 72103665 ps
CPU time 2.01 seconds
Started Aug 11 07:04:58 PM PDT 24
Finished Aug 11 07:05:00 PM PDT 24
Peak memory 206904 kb
Host smart-519bc5c8-80f9-4e53-90a5-116c5ed8a34e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229264207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.229264207
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.883979641
Short name T258
Test name
Test status
Simulation time 91390328 ps
CPU time 0.96 seconds
Started Aug 11 07:04:28 PM PDT 24
Finished Aug 11 07:04:29 PM PDT 24
Peak memory 206848 kb
Host smart-a5a723ec-a9be-4338-8658-a8daa1ec1354
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883979641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.883979641
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3828304981
Short name T1105
Test name
Test status
Simulation time 110292209 ps
CPU time 3.27 seconds
Started Aug 11 07:04:30 PM PDT 24
Finished Aug 11 07:04:33 PM PDT 24
Peak memory 206908 kb
Host smart-67d1f779-a96e-4e09-83cc-fd73d894893f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828304981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3828304981
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1955726976
Short name T250
Test name
Test status
Simulation time 28598761 ps
CPU time 0.99 seconds
Started Aug 11 07:04:28 PM PDT 24
Finished Aug 11 07:04:29 PM PDT 24
Peak memory 206832 kb
Host smart-b2b7b603-e43f-477a-aa0d-f7e1fa1a5cdf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955726976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1955726976
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2837926786
Short name T1104
Test name
Test status
Simulation time 55404346 ps
CPU time 1.34 seconds
Started Aug 11 07:04:28 PM PDT 24
Finished Aug 11 07:04:30 PM PDT 24
Peak memory 215188 kb
Host smart-2c9c6765-786b-44f8-8d57-e71f6a4480a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837926786 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2837926786
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.4212126974
Short name T249
Test name
Test status
Simulation time 15998958 ps
CPU time 0.98 seconds
Started Aug 11 07:04:28 PM PDT 24
Finished Aug 11 07:04:30 PM PDT 24
Peak memory 206860 kb
Host smart-60203f3b-fe3b-4459-a1ff-2de8a3b92c18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212126974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.4212126974
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2151651456
Short name T1049
Test name
Test status
Simulation time 21379220 ps
CPU time 0.87 seconds
Started Aug 11 07:04:27 PM PDT 24
Finished Aug 11 07:04:28 PM PDT 24
Peak memory 206576 kb
Host smart-c4bffc48-21f6-424a-8df3-e7595277f50e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151651456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2151651456
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.314890281
Short name T1075
Test name
Test status
Simulation time 19724552 ps
CPU time 0.96 seconds
Started Aug 11 07:04:29 PM PDT 24
Finished Aug 11 07:04:30 PM PDT 24
Peak memory 206968 kb
Host smart-2fefc94a-e0a1-47c4-8a91-00e5227c723e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314890281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.314890281
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1035399805
Short name T1077
Test name
Test status
Simulation time 155233154 ps
CPU time 3.9 seconds
Started Aug 11 07:04:28 PM PDT 24
Finished Aug 11 07:04:32 PM PDT 24
Peak memory 215176 kb
Host smart-4adc3475-3923-40ab-b45c-40e2e2c167bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035399805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1035399805
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1812766901
Short name T289
Test name
Test status
Simulation time 172737400 ps
CPU time 1.59 seconds
Started Aug 11 07:04:30 PM PDT 24
Finished Aug 11 07:04:31 PM PDT 24
Peak memory 207004 kb
Host smart-1382e3d3-cb92-4beb-ace5-e94d4a5692ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812766901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1812766901
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2725258984
Short name T1101
Test name
Test status
Simulation time 63541452 ps
CPU time 0.89 seconds
Started Aug 11 07:05:00 PM PDT 24
Finished Aug 11 07:05:01 PM PDT 24
Peak memory 206720 kb
Host smart-3c978ebb-bfca-43e3-a972-7eb6fe2af458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725258984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2725258984
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4205042050
Short name T1092
Test name
Test status
Simulation time 13952227 ps
CPU time 0.88 seconds
Started Aug 11 07:05:00 PM PDT 24
Finished Aug 11 07:05:02 PM PDT 24
Peak memory 206680 kb
Host smart-21257559-62e2-4658-bd03-fd9ba9566123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205042050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4205042050
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2672809113
Short name T1116
Test name
Test status
Simulation time 10596281 ps
CPU time 0.87 seconds
Started Aug 11 07:05:00 PM PDT 24
Finished Aug 11 07:05:00 PM PDT 24
Peak memory 206716 kb
Host smart-45f81582-e7a3-47a4-8fd9-f784d6f43d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672809113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2672809113
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2606608588
Short name T1060
Test name
Test status
Simulation time 16549173 ps
CPU time 0.94 seconds
Started Aug 11 07:04:59 PM PDT 24
Finished Aug 11 07:05:00 PM PDT 24
Peak memory 206680 kb
Host smart-fe29ecf6-fcb7-48cb-83ec-4f726e7e0d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606608588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2606608588
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1945795031
Short name T1093
Test name
Test status
Simulation time 11224683 ps
CPU time 0.88 seconds
Started Aug 11 07:04:58 PM PDT 24
Finished Aug 11 07:04:59 PM PDT 24
Peak memory 206704 kb
Host smart-b9f32b01-a86c-451f-b1a7-67f12a107e74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945795031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1945795031
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2738057622
Short name T1007
Test name
Test status
Simulation time 13297426 ps
CPU time 0.88 seconds
Started Aug 11 07:04:59 PM PDT 24
Finished Aug 11 07:05:00 PM PDT 24
Peak memory 206708 kb
Host smart-cc67141d-85e2-4df3-bb45-a101d130b999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738057622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2738057622
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1865026682
Short name T1038
Test name
Test status
Simulation time 11337656 ps
CPU time 0.91 seconds
Started Aug 11 07:05:06 PM PDT 24
Finished Aug 11 07:05:09 PM PDT 24
Peak memory 206652 kb
Host smart-ac4534b4-1048-4930-a904-38d7c618f828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865026682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1865026682
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.4228533913
Short name T1030
Test name
Test status
Simulation time 25565378 ps
CPU time 0.9 seconds
Started Aug 11 07:05:08 PM PDT 24
Finished Aug 11 07:05:09 PM PDT 24
Peak memory 206704 kb
Host smart-1c94b491-8911-468e-80f0-50109f3280b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228533913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.4228533913
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3153315687
Short name T1043
Test name
Test status
Simulation time 48004057 ps
CPU time 0.83 seconds
Started Aug 11 07:05:06 PM PDT 24
Finished Aug 11 07:05:07 PM PDT 24
Peak memory 206668 kb
Host smart-abcd8b54-01bf-470e-8d8f-c7b6f7050987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153315687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3153315687
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3861657644
Short name T1025
Test name
Test status
Simulation time 16604613 ps
CPU time 0.99 seconds
Started Aug 11 07:05:06 PM PDT 24
Finished Aug 11 07:05:07 PM PDT 24
Peak memory 206736 kb
Host smart-4c5d7a35-edf9-466f-b196-db1f29df1be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861657644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3861657644
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1074930040
Short name T260
Test name
Test status
Simulation time 238236696 ps
CPU time 1.34 seconds
Started Aug 11 07:04:41 PM PDT 24
Finished Aug 11 07:04:43 PM PDT 24
Peak memory 206936 kb
Host smart-59d52e0c-f8bb-4fa4-ab36-8706f311a2c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074930040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1074930040
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2794481743
Short name T1057
Test name
Test status
Simulation time 266034783 ps
CPU time 3.52 seconds
Started Aug 11 07:04:29 PM PDT 24
Finished Aug 11 07:04:33 PM PDT 24
Peak memory 206820 kb
Host smart-4a57ec7d-0335-4ce1-9a33-0df6b36f8b91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794481743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2794481743
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2512744181
Short name T1054
Test name
Test status
Simulation time 48604995 ps
CPU time 0.89 seconds
Started Aug 11 07:04:30 PM PDT 24
Finished Aug 11 07:04:31 PM PDT 24
Peak memory 206920 kb
Host smart-3199e310-fef6-4ee2-a096-193ccfa47df9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512744181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2512744181
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1172223300
Short name T1026
Test name
Test status
Simulation time 19599065 ps
CPU time 1.14 seconds
Started Aug 11 07:04:35 PM PDT 24
Finished Aug 11 07:04:37 PM PDT 24
Peak memory 215228 kb
Host smart-bcc4dd0e-edd3-4aad-a732-8b389a36e109
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172223300 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1172223300
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1615820344
Short name T255
Test name
Test status
Simulation time 18837534 ps
CPU time 0.85 seconds
Started Aug 11 07:04:27 PM PDT 24
Finished Aug 11 07:04:28 PM PDT 24
Peak memory 206656 kb
Host smart-bd76d6c0-5f63-47fe-a59c-aed03c847262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615820344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1615820344
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.704039456
Short name T1012
Test name
Test status
Simulation time 12246526 ps
CPU time 0.86 seconds
Started Aug 11 07:04:28 PM PDT 24
Finished Aug 11 07:04:29 PM PDT 24
Peak memory 206680 kb
Host smart-118e9e81-4d3f-4d76-9174-e9931b5905df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704039456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.704039456
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4280172936
Short name T265
Test name
Test status
Simulation time 46689712 ps
CPU time 0.93 seconds
Started Aug 11 07:04:34 PM PDT 24
Finished Aug 11 07:04:35 PM PDT 24
Peak memory 206936 kb
Host smart-5252896c-ea26-41b0-9914-700086862214
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280172936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.4280172936
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2483584526
Short name T1114
Test name
Test status
Simulation time 326202324 ps
CPU time 3.15 seconds
Started Aug 11 07:04:30 PM PDT 24
Finished Aug 11 07:04:34 PM PDT 24
Peak memory 215200 kb
Host smart-34a28d48-5bda-49a9-9854-a0fb23aa77fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483584526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2483584526
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3796663483
Short name T280
Test name
Test status
Simulation time 87683403 ps
CPU time 1.56 seconds
Started Aug 11 07:04:29 PM PDT 24
Finished Aug 11 07:04:30 PM PDT 24
Peak memory 206960 kb
Host smart-92db6427-0da5-4382-b030-d65c6f5f6402
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796663483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3796663483
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1460648912
Short name T1085
Test name
Test status
Simulation time 47303671 ps
CPU time 0.82 seconds
Started Aug 11 07:05:06 PM PDT 24
Finished Aug 11 07:05:07 PM PDT 24
Peak memory 206796 kb
Host smart-a98c3296-b760-4c1b-ae7c-12836411fe3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460648912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1460648912
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2563719049
Short name T1123
Test name
Test status
Simulation time 11889782 ps
CPU time 0.87 seconds
Started Aug 11 07:05:05 PM PDT 24
Finished Aug 11 07:05:06 PM PDT 24
Peak memory 206672 kb
Host smart-7d8e448c-0704-43fe-a0d8-407f25457918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563719049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2563719049
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1169601661
Short name T1046
Test name
Test status
Simulation time 27493706 ps
CPU time 0.87 seconds
Started Aug 11 07:05:06 PM PDT 24
Finished Aug 11 07:05:07 PM PDT 24
Peak memory 206680 kb
Host smart-ef935235-b95e-480f-9580-2e43603b0922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169601661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1169601661
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1068594853
Short name T1033
Test name
Test status
Simulation time 41823110 ps
CPU time 0.84 seconds
Started Aug 11 07:05:10 PM PDT 24
Finished Aug 11 07:05:11 PM PDT 24
Peak memory 206660 kb
Host smart-39e3b442-b25d-4cde-a5e2-bdee307ed588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068594853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1068594853
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.4230734191
Short name T1100
Test name
Test status
Simulation time 34064462 ps
CPU time 0.87 seconds
Started Aug 11 07:05:05 PM PDT 24
Finished Aug 11 07:05:06 PM PDT 24
Peak memory 206680 kb
Host smart-fa300fc4-14e4-4ae9-81a7-413aab66681e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230734191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.4230734191
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1613447412
Short name T1006
Test name
Test status
Simulation time 17427449 ps
CPU time 0.95 seconds
Started Aug 11 07:05:06 PM PDT 24
Finished Aug 11 07:05:07 PM PDT 24
Peak memory 206700 kb
Host smart-9c3b2e20-2aad-40dc-a3b0-07cd4804b393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613447412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1613447412
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.612686232
Short name T1094
Test name
Test status
Simulation time 11959270 ps
CPU time 0.89 seconds
Started Aug 11 07:05:06 PM PDT 24
Finished Aug 11 07:05:07 PM PDT 24
Peak memory 206716 kb
Host smart-1df11875-06e2-4419-850d-b64494a9cdf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612686232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.612686232
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.228203176
Short name T1017
Test name
Test status
Simulation time 45515799 ps
CPU time 0.85 seconds
Started Aug 11 07:05:04 PM PDT 24
Finished Aug 11 07:05:05 PM PDT 24
Peak memory 206664 kb
Host smart-8a2f533a-390a-4dd0-ac10-eb233e3e1d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228203176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.228203176
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1940033715
Short name T1041
Test name
Test status
Simulation time 44992751 ps
CPU time 0.85 seconds
Started Aug 11 07:05:06 PM PDT 24
Finished Aug 11 07:05:07 PM PDT 24
Peak memory 206692 kb
Host smart-193b07f6-f546-4589-b3c5-ec1b8a7d8160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940033715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1940033715
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1195483594
Short name T1112
Test name
Test status
Simulation time 32577352 ps
CPU time 0.82 seconds
Started Aug 11 07:05:06 PM PDT 24
Finished Aug 11 07:05:07 PM PDT 24
Peak memory 206564 kb
Host smart-774302d8-71f5-4cfb-8c15-1b687814e7c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195483594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1195483594
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3550198800
Short name T1055
Test name
Test status
Simulation time 37415059 ps
CPU time 1.58 seconds
Started Aug 11 07:04:37 PM PDT 24
Finished Aug 11 07:04:39 PM PDT 24
Peak memory 206924 kb
Host smart-d5d91403-778a-4650-983c-54df3eb3ed03
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550198800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3550198800
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3966181795
Short name T1082
Test name
Test status
Simulation time 195736478 ps
CPU time 5.1 seconds
Started Aug 11 07:04:37 PM PDT 24
Finished Aug 11 07:04:43 PM PDT 24
Peak memory 206840 kb
Host smart-75633b6b-d052-427b-9d27-339dbcb5b533
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966181795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3966181795
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2945174074
Short name T253
Test name
Test status
Simulation time 25880749 ps
CPU time 0.91 seconds
Started Aug 11 07:04:34 PM PDT 24
Finished Aug 11 07:04:35 PM PDT 24
Peak memory 206852 kb
Host smart-9b4267e7-f7f8-4e4d-9f34-3ab2705b7647
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945174074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2945174074
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3500994459
Short name T1110
Test name
Test status
Simulation time 176010536 ps
CPU time 1.28 seconds
Started Aug 11 07:04:35 PM PDT 24
Finished Aug 11 07:04:36 PM PDT 24
Peak memory 215268 kb
Host smart-ce4bf31b-501f-47a3-bcea-a6c7971301c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500994459 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3500994459
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3511798152
Short name T264
Test name
Test status
Simulation time 109083217 ps
CPU time 0.93 seconds
Started Aug 11 07:04:37 PM PDT 24
Finished Aug 11 07:04:38 PM PDT 24
Peak memory 206840 kb
Host smart-82d008c1-263e-480e-8de7-564ed98a5b47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511798152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3511798152
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1026538815
Short name T1066
Test name
Test status
Simulation time 29456521 ps
CPU time 0.9 seconds
Started Aug 11 07:04:41 PM PDT 24
Finished Aug 11 07:04:42 PM PDT 24
Peak memory 206716 kb
Host smart-0cfdb70b-1a1c-4a54-b957-f61519bf1855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026538815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1026538815
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.692579371
Short name T1059
Test name
Test status
Simulation time 75364532 ps
CPU time 1.06 seconds
Started Aug 11 07:04:34 PM PDT 24
Finished Aug 11 07:04:35 PM PDT 24
Peak memory 206884 kb
Host smart-331a5da0-a493-4604-9135-06d86e3aa117
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692579371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.692579371
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3936936362
Short name T1003
Test name
Test status
Simulation time 112736729 ps
CPU time 4.02 seconds
Started Aug 11 07:04:35 PM PDT 24
Finished Aug 11 07:04:40 PM PDT 24
Peak memory 215072 kb
Host smart-3b3a8a7d-93c5-46a0-adc6-073412c411ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936936362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3936936362
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.548030358
Short name T1098
Test name
Test status
Simulation time 47164605 ps
CPU time 1.71 seconds
Started Aug 11 07:04:34 PM PDT 24
Finished Aug 11 07:04:35 PM PDT 24
Peak memory 207204 kb
Host smart-8239b988-6328-4c77-9ec6-8bd8834cf7d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548030358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.548030358
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.906495868
Short name T1129
Test name
Test status
Simulation time 16322706 ps
CPU time 0.84 seconds
Started Aug 11 07:05:06 PM PDT 24
Finished Aug 11 07:05:07 PM PDT 24
Peak memory 206700 kb
Host smart-2167c207-c6e8-46ba-a195-3bf5fccf72b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906495868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.906495868
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.4165871921
Short name T1107
Test name
Test status
Simulation time 58919638 ps
CPU time 0.83 seconds
Started Aug 11 07:05:07 PM PDT 24
Finished Aug 11 07:05:08 PM PDT 24
Peak memory 206868 kb
Host smart-bdcbc4c5-a0b3-43d1-a7c0-37e06e1d6722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165871921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.4165871921
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3784682336
Short name T1119
Test name
Test status
Simulation time 20941987 ps
CPU time 0.9 seconds
Started Aug 11 07:05:07 PM PDT 24
Finished Aug 11 07:05:08 PM PDT 24
Peak memory 206732 kb
Host smart-d123b24f-0815-4326-badb-c66ea48f16ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784682336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3784682336
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3710510962
Short name T1045
Test name
Test status
Simulation time 22648651 ps
CPU time 0.85 seconds
Started Aug 11 07:05:10 PM PDT 24
Finished Aug 11 07:05:11 PM PDT 24
Peak memory 206660 kb
Host smart-077a83eb-5d6c-4b52-a8a5-020408816f11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710510962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3710510962
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.4226757277
Short name T1050
Test name
Test status
Simulation time 44072636 ps
CPU time 0.8 seconds
Started Aug 11 07:05:08 PM PDT 24
Finished Aug 11 07:05:09 PM PDT 24
Peak memory 206572 kb
Host smart-e13379b5-de46-408d-afeb-5c1d825f8c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226757277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.4226757277
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1566077241
Short name T1011
Test name
Test status
Simulation time 18169016 ps
CPU time 0.9 seconds
Started Aug 11 07:05:08 PM PDT 24
Finished Aug 11 07:05:09 PM PDT 24
Peak memory 206732 kb
Host smart-dc9604d5-684d-45be-898d-6b6e01fd1cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566077241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1566077241
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2704689455
Short name T1002
Test name
Test status
Simulation time 11071746 ps
CPU time 0.89 seconds
Started Aug 11 07:05:06 PM PDT 24
Finished Aug 11 07:05:07 PM PDT 24
Peak memory 206676 kb
Host smart-3f07a968-2fa0-462d-b217-d7e99bd945f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704689455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2704689455
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2460186020
Short name T1062
Test name
Test status
Simulation time 63225944 ps
CPU time 0.93 seconds
Started Aug 11 07:05:09 PM PDT 24
Finished Aug 11 07:05:10 PM PDT 24
Peak memory 206728 kb
Host smart-2e27cc9b-e425-4fc2-a83b-9573d6de6fde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460186020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2460186020
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.293854581
Short name T1001
Test name
Test status
Simulation time 14841715 ps
CPU time 0.79 seconds
Started Aug 11 07:05:10 PM PDT 24
Finished Aug 11 07:05:11 PM PDT 24
Peak memory 206548 kb
Host smart-c4c78aaf-8417-46f3-bd68-71704fa94c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293854581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.293854581
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.713475509
Short name T1072
Test name
Test status
Simulation time 13065696 ps
CPU time 0.91 seconds
Started Aug 11 07:05:05 PM PDT 24
Finished Aug 11 07:05:06 PM PDT 24
Peak memory 206708 kb
Host smart-35cc57c6-7be2-4e42-aac9-2e6eafd71ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713475509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.713475509
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3952449582
Short name T1080
Test name
Test status
Simulation time 58470572 ps
CPU time 1.4 seconds
Started Aug 11 07:04:42 PM PDT 24
Finished Aug 11 07:04:43 PM PDT 24
Peak memory 215256 kb
Host smart-115f06e5-4a52-40eb-90ba-ff2083003b91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952449582 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3952449582
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2352839737
Short name T257
Test name
Test status
Simulation time 14281479 ps
CPU time 0.91 seconds
Started Aug 11 07:04:43 PM PDT 24
Finished Aug 11 07:04:44 PM PDT 24
Peak memory 206856 kb
Host smart-941ed73c-d032-45cf-9547-79da30932f45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352839737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2352839737
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1386826096
Short name T1125
Test name
Test status
Simulation time 13944960 ps
CPU time 0.87 seconds
Started Aug 11 07:04:43 PM PDT 24
Finished Aug 11 07:04:44 PM PDT 24
Peak memory 206672 kb
Host smart-a4512efa-b541-4747-b6a7-362a70b600ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386826096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1386826096
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.266961074
Short name T266
Test name
Test status
Simulation time 30420908 ps
CPU time 1.11 seconds
Started Aug 11 07:04:40 PM PDT 24
Finished Aug 11 07:04:41 PM PDT 24
Peak memory 206888 kb
Host smart-d451e9ba-fe0e-49c4-81e4-c812a2004b17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266961074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.266961074
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1793469010
Short name T1016
Test name
Test status
Simulation time 357970908 ps
CPU time 2.73 seconds
Started Aug 11 07:04:35 PM PDT 24
Finished Aug 11 07:04:38 PM PDT 24
Peak memory 215168 kb
Host smart-496888d1-eeec-402f-bd18-1278acd4c840
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793469010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1793469010
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2249268544
Short name T1096
Test name
Test status
Simulation time 56102187 ps
CPU time 1.72 seconds
Started Aug 11 07:04:35 PM PDT 24
Finished Aug 11 07:04:37 PM PDT 24
Peak memory 206984 kb
Host smart-3ca28fa9-e00e-4a06-ad4e-6bc7a42ab7e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249268544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2249268544
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1096677467
Short name T1019
Test name
Test status
Simulation time 22805685 ps
CPU time 1.21 seconds
Started Aug 11 07:04:43 PM PDT 24
Finished Aug 11 07:04:45 PM PDT 24
Peak memory 215244 kb
Host smart-f1aa9f66-b567-483e-a14c-f482ee932dd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096677467 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1096677467
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3765736948
Short name T270
Test name
Test status
Simulation time 25761483 ps
CPU time 0.82 seconds
Started Aug 11 07:04:42 PM PDT 24
Finished Aug 11 07:04:43 PM PDT 24
Peak memory 206824 kb
Host smart-ea1b728c-3481-4396-907c-ac2625b59112
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765736948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3765736948
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.718646501
Short name T1022
Test name
Test status
Simulation time 29635470 ps
CPU time 0.94 seconds
Started Aug 11 07:04:41 PM PDT 24
Finished Aug 11 07:04:42 PM PDT 24
Peak memory 206668 kb
Host smart-bd1ce18e-f522-4d3a-bbc2-571932e3ae28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718646501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.718646501
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1580499764
Short name T1073
Test name
Test status
Simulation time 55326791 ps
CPU time 1.34 seconds
Started Aug 11 07:04:41 PM PDT 24
Finished Aug 11 07:04:43 PM PDT 24
Peak memory 206912 kb
Host smart-4ed6504b-c33e-4c61-943c-a4c125b54914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580499764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1580499764
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2825632238
Short name T1048
Test name
Test status
Simulation time 52416518 ps
CPU time 3.82 seconds
Started Aug 11 07:04:42 PM PDT 24
Finished Aug 11 07:04:46 PM PDT 24
Peak memory 215192 kb
Host smart-6a0bc628-e502-4357-b013-0dab50a151c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825632238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2825632238
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2270512787
Short name T1008
Test name
Test status
Simulation time 40119436 ps
CPU time 1.09 seconds
Started Aug 11 07:04:42 PM PDT 24
Finished Aug 11 07:04:44 PM PDT 24
Peak memory 214912 kb
Host smart-360413bd-99a0-4986-a83f-0128e063c5a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270512787 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2270512787
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3182638121
Short name T1037
Test name
Test status
Simulation time 15054603 ps
CPU time 0.97 seconds
Started Aug 11 07:04:41 PM PDT 24
Finished Aug 11 07:04:42 PM PDT 24
Peak memory 206836 kb
Host smart-3d6b731d-c925-4dfc-a627-5c392189424d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182638121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3182638121
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.792252381
Short name T1029
Test name
Test status
Simulation time 11769216 ps
CPU time 0.87 seconds
Started Aug 11 07:04:41 PM PDT 24
Finished Aug 11 07:04:42 PM PDT 24
Peak memory 206700 kb
Host smart-f87d8a5b-efd5-4018-9a5f-466ae890e0ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792252381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.792252381
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.502080820
Short name T256
Test name
Test status
Simulation time 54607160 ps
CPU time 1.02 seconds
Started Aug 11 07:04:48 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 206968 kb
Host smart-81ff55ab-93a0-4595-a752-81453be4ad75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502080820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.502080820
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3542973371
Short name T1074
Test name
Test status
Simulation time 102558140 ps
CPU time 2.17 seconds
Started Aug 11 07:04:41 PM PDT 24
Finished Aug 11 07:04:44 PM PDT 24
Peak memory 215408 kb
Host smart-5f81dddb-536a-4bcf-b213-e747ea27d584
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542973371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3542973371
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.315170161
Short name T1120
Test name
Test status
Simulation time 50191898 ps
CPU time 1.71 seconds
Started Aug 11 07:04:45 PM PDT 24
Finished Aug 11 07:04:46 PM PDT 24
Peak memory 207284 kb
Host smart-f108668b-18af-4788-880b-7e6ef46d0c3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315170161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.315170161
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2099954289
Short name T1024
Test name
Test status
Simulation time 33605551 ps
CPU time 1.1 seconds
Started Aug 11 07:04:41 PM PDT 24
Finished Aug 11 07:04:43 PM PDT 24
Peak memory 215228 kb
Host smart-94af8a1d-cef7-4bff-bf70-b4c4c56d473f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099954289 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2099954289
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1850198282
Short name T1000
Test name
Test status
Simulation time 14895631 ps
CPU time 0.94 seconds
Started Aug 11 07:04:43 PM PDT 24
Finished Aug 11 07:04:44 PM PDT 24
Peak memory 206800 kb
Host smart-4b43769a-df15-4729-a324-98e061cb3bd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850198282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1850198282
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1520763566
Short name T1079
Test name
Test status
Simulation time 15046322 ps
CPU time 0.91 seconds
Started Aug 11 07:04:42 PM PDT 24
Finished Aug 11 07:04:43 PM PDT 24
Peak memory 206716 kb
Host smart-79e21777-b666-4178-8f77-0941247f8fa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520763566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1520763566
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1344486964
Short name T271
Test name
Test status
Simulation time 56395336 ps
CPU time 1.1 seconds
Started Aug 11 07:04:42 PM PDT 24
Finished Aug 11 07:04:44 PM PDT 24
Peak memory 206936 kb
Host smart-0e1f19af-7abe-441f-8548-d53a493401c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344486964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1344486964
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1095326850
Short name T1056
Test name
Test status
Simulation time 83050795 ps
CPU time 3.39 seconds
Started Aug 11 07:04:41 PM PDT 24
Finished Aug 11 07:04:45 PM PDT 24
Peak memory 215152 kb
Host smart-c8ef9bf6-1d87-4ce4-ba8a-1b4ab04bb879
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095326850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1095326850
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.307986372
Short name T279
Test name
Test status
Simulation time 138900979 ps
CPU time 1.64 seconds
Started Aug 11 07:04:42 PM PDT 24
Finished Aug 11 07:04:44 PM PDT 24
Peak memory 206916 kb
Host smart-f894aff5-e8ea-4e16-88d2-28c529e1fd1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307986372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.307986372
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.125669610
Short name T1095
Test name
Test status
Simulation time 92884175 ps
CPU time 1.3 seconds
Started Aug 11 07:04:48 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 215132 kb
Host smart-0b112047-87ef-4cea-8c52-340119967bb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125669610 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.125669610
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3531775857
Short name T1035
Test name
Test status
Simulation time 22029002 ps
CPU time 0.86 seconds
Started Aug 11 07:04:47 PM PDT 24
Finished Aug 11 07:04:48 PM PDT 24
Peak memory 206812 kb
Host smart-425b7bfe-80ff-4556-8fb8-c3384090c840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531775857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3531775857
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3423342228
Short name T1047
Test name
Test status
Simulation time 12329900 ps
CPU time 0.9 seconds
Started Aug 11 07:04:46 PM PDT 24
Finished Aug 11 07:04:47 PM PDT 24
Peak memory 206688 kb
Host smart-d62df6c9-e58e-4072-92b9-6a1d79ad3369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423342228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3423342228
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3922927619
Short name T1067
Test name
Test status
Simulation time 58669521 ps
CPU time 1.1 seconds
Started Aug 11 07:04:47 PM PDT 24
Finished Aug 11 07:04:48 PM PDT 24
Peak memory 206972 kb
Host smart-e1add2a4-0c27-4db4-a7c8-cef39d3f62b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922927619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3922927619
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3537317538
Short name T1014
Test name
Test status
Simulation time 500181102 ps
CPU time 4.37 seconds
Started Aug 11 07:04:48 PM PDT 24
Finished Aug 11 07:04:52 PM PDT 24
Peak memory 215176 kb
Host smart-e2c7e896-2fe0-413d-883f-3544c9f07161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537317538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3537317538
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2072359946
Short name T1040
Test name
Test status
Simulation time 145110105 ps
CPU time 1.47 seconds
Started Aug 11 07:04:47 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 206888 kb
Host smart-bdd0c84e-ba5a-4d1a-92a8-23652b8eee35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072359946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2072359946
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1135280274
Short name T556
Test name
Test status
Simulation time 39410633 ps
CPU time 1.23 seconds
Started Aug 11 06:25:07 PM PDT 24
Finished Aug 11 06:25:08 PM PDT 24
Peak memory 219628 kb
Host smart-b52f85e3-b012-486b-bea8-207ee88ae8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135280274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1135280274
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2062948169
Short name T863
Test name
Test status
Simulation time 68491120 ps
CPU time 0.87 seconds
Started Aug 11 06:25:13 PM PDT 24
Finished Aug 11 06:25:14 PM PDT 24
Peak memory 215124 kb
Host smart-23dcc91a-4e72-4eda-bc9a-510818e5d7d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062948169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2062948169
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3411566253
Short name T459
Test name
Test status
Simulation time 62839973 ps
CPU time 0.89 seconds
Started Aug 11 06:25:07 PM PDT 24
Finished Aug 11 06:25:08 PM PDT 24
Peak memory 216264 kb
Host smart-7fdbd784-ea63-492d-b8e5-220a3f703bc4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411566253 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3411566253
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3381738094
Short name T791
Test name
Test status
Simulation time 55666009 ps
CPU time 1.08 seconds
Started Aug 11 06:25:14 PM PDT 24
Finished Aug 11 06:25:15 PM PDT 24
Peak memory 218492 kb
Host smart-6c95982e-a2c3-4616-9223-4c65af816437
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381738094 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3381738094
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_genbits.3389495578
Short name T370
Test name
Test status
Simulation time 251845876 ps
CPU time 1.01 seconds
Started Aug 11 06:25:05 PM PDT 24
Finished Aug 11 06:25:06 PM PDT 24
Peak memory 217280 kb
Host smart-27e2924e-c1ff-4552-b066-0d7da0723e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389495578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3389495578
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2386945168
Short name T425
Test name
Test status
Simulation time 23213640 ps
CPU time 1.29 seconds
Started Aug 11 06:25:13 PM PDT 24
Finished Aug 11 06:25:14 PM PDT 24
Peak memory 224160 kb
Host smart-11de8b00-66db-4ab7-9dc9-0206f12d31f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386945168 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2386945168
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3874453232
Short name T27
Test name
Test status
Simulation time 27490531 ps
CPU time 0.97 seconds
Started Aug 11 06:25:05 PM PDT 24
Finished Aug 11 06:25:06 PM PDT 24
Peak memory 207116 kb
Host smart-5afd75a8-4080-4405-8b8c-d84ef196d857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874453232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3874453232
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.4129102975
Short name T65
Test name
Test status
Simulation time 2026709249 ps
CPU time 9.13 seconds
Started Aug 11 06:25:05 PM PDT 24
Finished Aug 11 06:25:14 PM PDT 24
Peak memory 243920 kb
Host smart-0a65bf50-b7d7-4fe1-a592-bbfde1ffee34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129102975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.4129102975
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3433679138
Short name T614
Test name
Test status
Simulation time 155721129 ps
CPU time 0.9 seconds
Started Aug 11 06:25:07 PM PDT 24
Finished Aug 11 06:25:08 PM PDT 24
Peak memory 215312 kb
Host smart-1f0b60ff-3d04-4f9b-b060-caa1cc6f7ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433679138 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3433679138
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3899034902
Short name T543
Test name
Test status
Simulation time 1448722534 ps
CPU time 4.17 seconds
Started Aug 11 06:25:13 PM PDT 24
Finished Aug 11 06:25:18 PM PDT 24
Peak memory 215316 kb
Host smart-ea9c1f3f-9a05-4260-83e6-db4180bfa880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899034902 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3899034902
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.1503573746
Short name T609
Test name
Test status
Simulation time 26115933 ps
CPU time 1.18 seconds
Started Aug 11 06:25:17 PM PDT 24
Finished Aug 11 06:25:19 PM PDT 24
Peak memory 219188 kb
Host smart-2fb7d461-cd57-4e47-bbb6-c928632efe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503573746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1503573746
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.655609245
Short name T512
Test name
Test status
Simulation time 65029350 ps
CPU time 0.83 seconds
Started Aug 11 06:25:14 PM PDT 24
Finished Aug 11 06:25:15 PM PDT 24
Peak memory 206848 kb
Host smart-1977b1f5-9895-42da-9eba-bd006ef7743a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655609245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.655609245
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.4024366641
Short name T472
Test name
Test status
Simulation time 38761910 ps
CPU time 0.87 seconds
Started Aug 11 06:25:14 PM PDT 24
Finished Aug 11 06:25:15 PM PDT 24
Peak memory 216244 kb
Host smart-9588cc10-76b2-445d-8960-44852bc1dfaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024366641 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.4024366641
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.2766962017
Short name T153
Test name
Test status
Simulation time 36343943 ps
CPU time 1.01 seconds
Started Aug 11 06:25:13 PM PDT 24
Finished Aug 11 06:25:14 PM PDT 24
Peak memory 229768 kb
Host smart-581bfd2a-3158-4c67-b1ee-139395dd3cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766962017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2766962017
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3546421551
Short name T398
Test name
Test status
Simulation time 64146640 ps
CPU time 1.36 seconds
Started Aug 11 06:25:15 PM PDT 24
Finished Aug 11 06:25:17 PM PDT 24
Peak memory 218924 kb
Host smart-fe262ddd-cb9f-4c56-b9e9-2f3426fabb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546421551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3546421551
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1869360860
Short name T53
Test name
Test status
Simulation time 117414292 ps
CPU time 0.93 seconds
Started Aug 11 06:25:15 PM PDT 24
Finished Aug 11 06:25:16 PM PDT 24
Peak memory 223884 kb
Host smart-c842dd81-9271-46ff-a17b-d0f4e770a9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869360860 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1869360860
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3667029873
Short name T832
Test name
Test status
Simulation time 34835450 ps
CPU time 1.05 seconds
Started Aug 11 06:25:13 PM PDT 24
Finished Aug 11 06:25:15 PM PDT 24
Peak memory 207104 kb
Host smart-9d907f11-bc1d-46bc-8fb5-4fe3ac437782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667029873 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3667029873
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.4254673528
Short name T899
Test name
Test status
Simulation time 32419817 ps
CPU time 1.03 seconds
Started Aug 11 06:25:19 PM PDT 24
Finished Aug 11 06:25:20 PM PDT 24
Peak memory 215272 kb
Host smart-9778c562-16cd-4956-a079-bd768244ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254673528 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.4254673528
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.4280948297
Short name T679
Test name
Test status
Simulation time 60904884625 ps
CPU time 1151.47 seconds
Started Aug 11 06:25:14 PM PDT 24
Finished Aug 11 06:44:26 PM PDT 24
Peak memory 221668 kb
Host smart-2af27e0b-c803-4417-ade0-1849fd2eeb63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280948297 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.4280948297
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.2583071594
Short name T738
Test name
Test status
Simulation time 63492491 ps
CPU time 0.82 seconds
Started Aug 11 06:25:28 PM PDT 24
Finished Aug 11 06:25:29 PM PDT 24
Peak memory 206620 kb
Host smart-139e5bb9-a692-4d08-9fba-fe34f54d1a92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583071594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2583071594
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3033516
Short name T77
Test name
Test status
Simulation time 11912372 ps
CPU time 0.9 seconds
Started Aug 11 06:25:23 PM PDT 24
Finished Aug 11 06:25:25 PM PDT 24
Peak memory 216668 kb
Host smart-b215c95c-b696-4042-a95a-c67bfccc856d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033516 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3033516
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.4097679593
Short name T224
Test name
Test status
Simulation time 19313715 ps
CPU time 1.01 seconds
Started Aug 11 06:25:27 PM PDT 24
Finished Aug 11 06:25:28 PM PDT 24
Peak memory 215512 kb
Host smart-d470915e-e12f-48a1-8133-90119caf3286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097679593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.4097679593
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.1041960416
Short name T870
Test name
Test status
Simulation time 36129863 ps
CPU time 0.91 seconds
Started Aug 11 06:25:24 PM PDT 24
Finished Aug 11 06:25:25 PM PDT 24
Peak memory 215352 kb
Host smart-ba445188-20bc-471c-95f0-ceff86825c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041960416 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1041960416
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3338268603
Short name T501
Test name
Test status
Simulation time 72952126 ps
CPU time 0.95 seconds
Started Aug 11 06:25:22 PM PDT 24
Finished Aug 11 06:25:24 PM PDT 24
Peak memory 215304 kb
Host smart-06a1b9b0-fd6e-400c-b9b7-fef7d25994d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338268603 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3338268603
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3684563689
Short name T747
Test name
Test status
Simulation time 224143064 ps
CPU time 4.84 seconds
Started Aug 11 06:25:22 PM PDT 24
Finished Aug 11 06:25:27 PM PDT 24
Peak memory 215268 kb
Host smart-1066030c-785b-46e7-b44c-8ee18babb785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684563689 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3684563689
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2760237397
Short name T412
Test name
Test status
Simulation time 432853477973 ps
CPU time 1059.1 seconds
Started Aug 11 06:25:24 PM PDT 24
Finished Aug 11 06:43:03 PM PDT 24
Peak memory 222812 kb
Host smart-b2ba6f2e-e0fd-4705-b9fe-cc7f7600e93b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760237397 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2760237397
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.4260797082
Short name T422
Test name
Test status
Simulation time 122414593 ps
CPU time 1.2 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 217424 kb
Host smart-91486443-cdb9-4c7e-b89b-6b1e3e758b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260797082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4260797082
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.252045239
Short name T674
Test name
Test status
Simulation time 28305953 ps
CPU time 1.26 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 219564 kb
Host smart-10ffec7d-942f-4636-93ec-de675748c5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252045239 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.252045239
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.1912098168
Short name T436
Test name
Test status
Simulation time 39909996 ps
CPU time 1.11 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 220000 kb
Host smart-50b4317c-2b9a-4d74-9a6a-f6f2681c5df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912098168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1912098168
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.2861590992
Short name T616
Test name
Test status
Simulation time 27446171 ps
CPU time 1.13 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 219632 kb
Host smart-0c21c140-0ebe-4bbb-9868-26952e99ee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861590992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.2861590992
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.919155672
Short name T76
Test name
Test status
Simulation time 41354778 ps
CPU time 1.36 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 218468 kb
Host smart-194f13b1-3b8e-4ba3-b826-87efa159fdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919155672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.919155672
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.4059109505
Short name T141
Test name
Test status
Simulation time 22840504 ps
CPU time 1.12 seconds
Started Aug 11 06:26:39 PM PDT 24
Finished Aug 11 06:26:40 PM PDT 24
Peak memory 219748 kb
Host smart-006356e0-50f9-4680-9eae-67ad802c8c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059109505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.4059109505
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2031668701
Short name T414
Test name
Test status
Simulation time 135600616 ps
CPU time 1.43 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 215304 kb
Host smart-2db1a2ba-6531-4a61-b0bb-836d2e67d901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031668701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2031668701
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3545727493
Short name T675
Test name
Test status
Simulation time 47193854 ps
CPU time 1.48 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 218400 kb
Host smart-4a106d5f-f1c8-4026-8771-d4781f0ec52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545727493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3545727493
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2699853549
Short name T916
Test name
Test status
Simulation time 97103322 ps
CPU time 1.19 seconds
Started Aug 11 06:26:55 PM PDT 24
Finished Aug 11 06:26:57 PM PDT 24
Peak memory 218396 kb
Host smart-79c3ec20-2173-4089-9143-49f9c4c27a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699853549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2699853549
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.3014890274
Short name T539
Test name
Test status
Simulation time 68491289 ps
CPU time 1.23 seconds
Started Aug 11 06:26:48 PM PDT 24
Finished Aug 11 06:26:49 PM PDT 24
Peak memory 217184 kb
Host smart-8e133689-fe9a-4f56-8b04-6c6d77259133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014890274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3014890274
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.3750310115
Short name T908
Test name
Test status
Simulation time 80233053 ps
CPU time 1.13 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 219724 kb
Host smart-95186001-217c-4898-935a-3a539a8af6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750310115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3750310115
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.3167849755
Short name T340
Test name
Test status
Simulation time 84180958 ps
CPU time 1.8 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 219172 kb
Host smart-72feac6c-c12b-4a2c-b5d0-2749212e4e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167849755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3167849755
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.2193328819
Short name T493
Test name
Test status
Simulation time 76443756 ps
CPU time 1.18 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 218916 kb
Host smart-2949735c-a74e-4618-abd5-a2175cf9213d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193328819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2193328819
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/109.edn_alert.2189710865
Short name T277
Test name
Test status
Simulation time 93801949 ps
CPU time 1.18 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 215660 kb
Host smart-e75c501e-216c-4d84-ba77-97e25e3260cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189710865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.2189710865
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.156984832
Short name T690
Test name
Test status
Simulation time 231914209 ps
CPU time 3.33 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:50 PM PDT 24
Peak memory 219168 kb
Host smart-777adcfc-dd25-468d-b8a2-d9dd37953e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156984832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.156984832
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.824411910
Short name T664
Test name
Test status
Simulation time 26616953 ps
CPU time 1.26 seconds
Started Aug 11 06:25:28 PM PDT 24
Finished Aug 11 06:25:29 PM PDT 24
Peak memory 219616 kb
Host smart-fe944421-1c01-4592-a1e6-f7834c0e0ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824411910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.824411910
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.4230524882
Short name T560
Test name
Test status
Simulation time 26029702 ps
CPU time 0.91 seconds
Started Aug 11 06:25:24 PM PDT 24
Finished Aug 11 06:25:25 PM PDT 24
Peak memory 215144 kb
Host smart-4a386872-c5b2-4fc1-baa5-57c8fff7cb4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230524882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4230524882
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.4292253543
Short name T205
Test name
Test status
Simulation time 14070650 ps
CPU time 0.96 seconds
Started Aug 11 06:25:25 PM PDT 24
Finished Aug 11 06:25:26 PM PDT 24
Peak memory 216708 kb
Host smart-f6f6d5d1-cf6b-4731-94ae-4c5578b00731
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292253543 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.4292253543
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.3713390598
Short name T886
Test name
Test status
Simulation time 31659356 ps
CPU time 1.31 seconds
Started Aug 11 06:25:24 PM PDT 24
Finished Aug 11 06:25:26 PM PDT 24
Peak memory 219876 kb
Host smart-948c054c-67b5-4c83-9170-697919a046d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713390598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3713390598
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3389911138
Short name T75
Test name
Test status
Simulation time 86961618 ps
CPU time 2.75 seconds
Started Aug 11 06:25:26 PM PDT 24
Finished Aug 11 06:25:28 PM PDT 24
Peak memory 220088 kb
Host smart-408c5bc3-9580-4dbf-b8e6-b2d5159b7895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389911138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3389911138
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1190169695
Short name T973
Test name
Test status
Simulation time 20760121 ps
CPU time 1.06 seconds
Started Aug 11 06:25:27 PM PDT 24
Finished Aug 11 06:25:28 PM PDT 24
Peak memory 216180 kb
Host smart-0e97d99c-762b-4fc3-bbee-ed59f262cfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190169695 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1190169695
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1888410746
Short name T950
Test name
Test status
Simulation time 17625422 ps
CPU time 1.03 seconds
Started Aug 11 06:25:23 PM PDT 24
Finished Aug 11 06:25:25 PM PDT 24
Peak memory 215292 kb
Host smart-80c57410-7d19-470a-8aad-77d0835b7529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888410746 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1888410746
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3724121331
Short name T878
Test name
Test status
Simulation time 304923688 ps
CPU time 5.77 seconds
Started Aug 11 06:25:24 PM PDT 24
Finished Aug 11 06:25:30 PM PDT 24
Peak memory 217176 kb
Host smart-d11de195-f33a-451f-b7df-5be796fb45fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724121331 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3724121331
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.4200413781
Short name T826
Test name
Test status
Simulation time 52328255748 ps
CPU time 276.52 seconds
Started Aug 11 06:25:28 PM PDT 24
Finished Aug 11 06:30:05 PM PDT 24
Peak memory 218108 kb
Host smart-2d9d26a4-1ec7-4612-9d91-3f5c50782fc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200413781 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.4200413781
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1654621351
Short name T672
Test name
Test status
Simulation time 25074186 ps
CPU time 1.24 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 220224 kb
Host smart-66effe1c-7051-4102-bef6-de96aa387a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654621351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1654621351
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/111.edn_alert.2416633844
Short name T782
Test name
Test status
Simulation time 25062767 ps
CPU time 1.26 seconds
Started Aug 11 06:26:48 PM PDT 24
Finished Aug 11 06:26:50 PM PDT 24
Peak memory 219544 kb
Host smart-9f1e95bd-0ffb-4cbb-8d81-6b55c9d327ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416633844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2416633844
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.2442554264
Short name T839
Test name
Test status
Simulation time 145588714 ps
CPU time 1.51 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 218804 kb
Host smart-26d98a2a-a237-4818-bdad-6bea11fbce7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442554264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2442554264
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3327583563
Short name T851
Test name
Test status
Simulation time 38038320 ps
CPU time 1.07 seconds
Started Aug 11 06:26:49 PM PDT 24
Finished Aug 11 06:26:50 PM PDT 24
Peak memory 218340 kb
Host smart-117bcf61-3399-44c4-b04b-187030d26c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327583563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3327583563
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3132273837
Short name T830
Test name
Test status
Simulation time 41370170 ps
CPU time 1.42 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 219988 kb
Host smart-0bc4d35a-0c23-488f-9b08-e7f630d06204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132273837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3132273837
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.431733628
Short name T304
Test name
Test status
Simulation time 80029669 ps
CPU time 1.09 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 220136 kb
Host smart-50ecceb5-db38-4048-b771-d4cff1398f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431733628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.431733628
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.4287481456
Short name T552
Test name
Test status
Simulation time 29110081 ps
CPU time 1.2 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 218260 kb
Host smart-8882f22d-3bb3-4ff8-96b9-47f0e244a678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287481456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.4287481456
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.2837692688
Short name T694
Test name
Test status
Simulation time 37974556 ps
CPU time 1.35 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 218324 kb
Host smart-cddc0a75-8fa9-4859-9622-fd4dc920345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837692688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2837692688
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.1323066733
Short name T454
Test name
Test status
Simulation time 354242643 ps
CPU time 1.21 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 218532 kb
Host smart-d11e9971-6c7d-4f6b-8748-702f4de62dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323066733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1323066733
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1911023158
Short name T355
Test name
Test status
Simulation time 157289874 ps
CPU time 1.37 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 218688 kb
Host smart-12940f93-a2a4-4427-857e-e77609d7dd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911023158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1911023158
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.4118153516
Short name T467
Test name
Test status
Simulation time 64385693 ps
CPU time 1.02 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:53 PM PDT 24
Peak memory 217320 kb
Host smart-8b9c23c9-fa2e-4975-815e-90dc184f327b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118153516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4118153516
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.2557486761
Short name T662
Test name
Test status
Simulation time 41862088 ps
CPU time 1.17 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 219356 kb
Host smart-c9bb9dc3-b81a-4b9c-8f90-28d41e8223db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557486761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.2557486761
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.4071837794
Short name T538
Test name
Test status
Simulation time 39905124 ps
CPU time 1.49 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 217460 kb
Host smart-fcf21e90-4dfc-4492-9841-ac377e9d885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071837794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.4071837794
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2444689314
Short name T402
Test name
Test status
Simulation time 74064483 ps
CPU time 2.38 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:49 PM PDT 24
Peak memory 220252 kb
Host smart-aab41bda-45a9-4887-aa11-96dafc841066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444689314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2444689314
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3773764155
Short name T921
Test name
Test status
Simulation time 22389626 ps
CPU time 1.1 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 219412 kb
Host smart-857ad3d3-e3c9-44a8-9412-09ad32cebb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773764155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3773764155
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.824039141
Short name T385
Test name
Test status
Simulation time 55801377 ps
CPU time 1.21 seconds
Started Aug 11 06:26:39 PM PDT 24
Finished Aug 11 06:26:40 PM PDT 24
Peak memory 217448 kb
Host smart-1ed2c4d5-f505-4f9e-b722-482962319945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824039141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.824039141
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.964065920
Short name T620
Test name
Test status
Simulation time 25249964 ps
CPU time 1.22 seconds
Started Aug 11 06:25:33 PM PDT 24
Finished Aug 11 06:25:38 PM PDT 24
Peak memory 219692 kb
Host smart-7a3f0891-5106-477a-98d0-8939dd096473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964065920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.964065920
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1207296360
Short name T683
Test name
Test status
Simulation time 12810107 ps
CPU time 0.89 seconds
Started Aug 11 06:25:30 PM PDT 24
Finished Aug 11 06:25:31 PM PDT 24
Peak memory 207012 kb
Host smart-85e756a8-31eb-4150-bf8c-f864f8990ee3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207296360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1207296360
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2827312992
Short name T770
Test name
Test status
Simulation time 15003823 ps
CPU time 0.86 seconds
Started Aug 11 06:25:32 PM PDT 24
Finished Aug 11 06:25:33 PM PDT 24
Peak memory 218876 kb
Host smart-08b3d210-2bb9-46b3-8a9b-c66c00bdd538
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827312992 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2827312992
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.1435074402
Short name T69
Test name
Test status
Simulation time 20056167 ps
CPU time 1.04 seconds
Started Aug 11 06:25:30 PM PDT 24
Finished Aug 11 06:25:32 PM PDT 24
Peak memory 218692 kb
Host smart-87d26a08-6bde-41df-88dd-c1e4b27a998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435074402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1435074402
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_smoke.3344318465
Short name T395
Test name
Test status
Simulation time 15815614 ps
CPU time 0.98 seconds
Started Aug 11 06:25:22 PM PDT 24
Finished Aug 11 06:25:24 PM PDT 24
Peak memory 215248 kb
Host smart-ad89f330-cdf1-4595-b78a-f20a1ced731a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344318465 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3344318465
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1910268102
Short name T6
Test name
Test status
Simulation time 251621847 ps
CPU time 1.97 seconds
Started Aug 11 06:25:23 PM PDT 24
Finished Aug 11 06:25:26 PM PDT 24
Peak memory 215316 kb
Host smart-b4ca225d-a815-4d8d-aecc-00d9cebe0565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910268102 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1910268102
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.976919506
Short name T942
Test name
Test status
Simulation time 149291590888 ps
CPU time 940.47 seconds
Started Aug 11 06:25:25 PM PDT 24
Finished Aug 11 06:41:05 PM PDT 24
Peak memory 221864 kb
Host smart-a547b0f4-2d5b-40b8-a544-966b7ac2c7b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976919506 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.976919506
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.2070870008
Short name T610
Test name
Test status
Simulation time 98791215 ps
CPU time 1.17 seconds
Started Aug 11 06:26:53 PM PDT 24
Finished Aug 11 06:26:54 PM PDT 24
Peak memory 220244 kb
Host smart-51f8f52c-b250-418a-8da8-4f0e3446c809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070870008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2070870008
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3971481197
Short name T746
Test name
Test status
Simulation time 68561150 ps
CPU time 1.5 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:42 PM PDT 24
Peak memory 217508 kb
Host smart-18373443-0ee7-4f1b-afbe-183da9206056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971481197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3971481197
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3789259635
Short name T657
Test name
Test status
Simulation time 82180571 ps
CPU time 1.11 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 219572 kb
Host smart-71f4a72d-ff63-4faf-842e-00895ac00015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789259635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3789259635
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.659501202
Short name T736
Test name
Test status
Simulation time 97067049 ps
CPU time 0.98 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 217280 kb
Host smart-b5f9cb1c-1e2b-4034-ba51-47f7fae262cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659501202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.659501202
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.1376021265
Short name T541
Test name
Test status
Simulation time 153799605 ps
CPU time 1.18 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:40 PM PDT 24
Peak memory 218928 kb
Host smart-338bdbb6-5670-43b2-98e7-e6ff5bec2ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376021265 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1376021265
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.4218561107
Short name T800
Test name
Test status
Simulation time 100667615 ps
CPU time 1.51 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 218716 kb
Host smart-9bf5430b-d01e-40c3-ad70-047308877764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218561107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.4218561107
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2292502361
Short name T225
Test name
Test status
Simulation time 25636089 ps
CPU time 1.21 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 219636 kb
Host smart-c16fada5-7f1f-4ffc-b370-4808e830d8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292502361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2292502361
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.265552549
Short name T737
Test name
Test status
Simulation time 68323821 ps
CPU time 1.49 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 218964 kb
Host smart-9bfce06d-fe93-488f-8564-841727034594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265552549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.265552549
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.140400968
Short name T373
Test name
Test status
Simulation time 47572865 ps
CPU time 1.18 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 215612 kb
Host smart-5cdb076e-1fa7-4496-a0aa-dfef84289107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140400968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.140400968
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.648924054
Short name T423
Test name
Test status
Simulation time 37764305 ps
CPU time 1.45 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:49 PM PDT 24
Peak memory 218816 kb
Host smart-cdadcef9-8026-424b-8912-cdba7506a436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648924054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.648924054
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.3247506695
Short name T700
Test name
Test status
Simulation time 59271910 ps
CPU time 1.35 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 215544 kb
Host smart-4e683ee7-3803-4e87-82ca-9e00e7ab5bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247506695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3247506695
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.915424298
Short name T449
Test name
Test status
Simulation time 112622021 ps
CPU time 1.3 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 217356 kb
Host smart-6f7b7708-cbf4-4437-a2e5-67cb9c435a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915424298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.915424298
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.578219381
Short name T248
Test name
Test status
Simulation time 34983924 ps
CPU time 1.36 seconds
Started Aug 11 06:26:48 PM PDT 24
Finished Aug 11 06:26:49 PM PDT 24
Peak memory 215552 kb
Host smart-e8ab67ef-a693-4aed-b6f3-9a0bb6886b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578219381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.578219381
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.589778059
Short name T362
Test name
Test status
Simulation time 29183972 ps
CPU time 1.24 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 217480 kb
Host smart-671c785b-1e0c-464c-98f2-d0c60cf0660e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589778059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.589778059
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2049158952
Short name T880
Test name
Test status
Simulation time 67311179 ps
CPU time 1.08 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 217456 kb
Host smart-facfdbbf-2aca-4276-a3f6-bd686bd6df26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049158952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2049158952
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.927372422
Short name T777
Test name
Test status
Simulation time 40663365 ps
CPU time 1.29 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 219652 kb
Host smart-66515d93-59f0-46a1-aeca-8d795608f13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927372422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.927372422
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.2975988967
Short name T756
Test name
Test status
Simulation time 35277344 ps
CPU time 1.04 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 217244 kb
Host smart-55c13c9a-e130-48cb-8551-6213c1017c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975988967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2975988967
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3625685929
Short name T332
Test name
Test status
Simulation time 42350863 ps
CPU time 1.15 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 218288 kb
Host smart-6d73858f-44e2-4e76-a0f8-a0441d08438c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625685929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3625685929
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.3733479222
Short name T622
Test name
Test status
Simulation time 2194651274 ps
CPU time 63.32 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:27:50 PM PDT 24
Peak memory 219740 kb
Host smart-54d7e8dc-81b6-43e2-bd99-c777878d69cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733479222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3733479222
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_disable.1627892799
Short name T363
Test name
Test status
Simulation time 58802612 ps
CPU time 0.93 seconds
Started Aug 11 06:25:33 PM PDT 24
Finished Aug 11 06:25:34 PM PDT 24
Peak memory 216468 kb
Host smart-e2f118f1-5d3a-4a4c-aba3-b95cb0e03c25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627892799 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1627892799
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.3461407234
Short name T837
Test name
Test status
Simulation time 28445252 ps
CPU time 1.16 seconds
Started Aug 11 06:25:32 PM PDT 24
Finished Aug 11 06:25:34 PM PDT 24
Peak memory 218652 kb
Host smart-64495980-f4e9-423e-bc6e-a44d6ed9b2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461407234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3461407234
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_intr.226768463
Short name T380
Test name
Test status
Simulation time 27441846 ps
CPU time 0.95 seconds
Started Aug 11 06:25:30 PM PDT 24
Finished Aug 11 06:25:31 PM PDT 24
Peak memory 215436 kb
Host smart-19433bfb-c5f5-42cc-8ee6-b6dbf1f24d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226768463 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.226768463
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2935253045
Short name T925
Test name
Test status
Simulation time 18518932 ps
CPU time 1.03 seconds
Started Aug 11 06:25:31 PM PDT 24
Finished Aug 11 06:25:32 PM PDT 24
Peak memory 215288 kb
Host smart-29172b78-3e1d-4ab6-838f-2d740147cf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935253045 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2935253045
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2574814239
Short name T317
Test name
Test status
Simulation time 128237766 ps
CPU time 2.93 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:42 PM PDT 24
Peak memory 217164 kb
Host smart-72a4bc6d-c0ec-473c-b194-573261b4aa9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574814239 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2574814239
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1553954037
Short name T900
Test name
Test status
Simulation time 152001041162 ps
CPU time 1657.63 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:53:17 PM PDT 24
Peak memory 224784 kb
Host smart-d59f44da-e13e-4701-b9ce-e8e0db98674f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553954037 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1553954037
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.1805763198
Short name T793
Test name
Test status
Simulation time 169965140 ps
CPU time 1.11 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:53 PM PDT 24
Peak memory 219380 kb
Host smart-c8e06094-1b71-4dca-a7a1-c8228c891e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805763198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.1805763198
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1228037437
Short name T933
Test name
Test status
Simulation time 33209230 ps
CPU time 1.66 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:54 PM PDT 24
Peak memory 217568 kb
Host smart-e533a383-8bb7-4406-90d5-4e5c0bb795c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228037437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1228037437
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1792087202
Short name T426
Test name
Test status
Simulation time 206097733 ps
CPU time 1.13 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 217360 kb
Host smart-91013a65-64f1-446d-bf18-7c9e2efc741c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792087202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1792087202
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3044861147
Short name T677
Test name
Test status
Simulation time 23011067 ps
CPU time 1.16 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 218620 kb
Host smart-055dac77-4843-4bf1-a4d2-344a86bd734b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044861147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3044861147
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2769357827
Short name T319
Test name
Test status
Simulation time 260043290 ps
CPU time 3.75 seconds
Started Aug 11 06:26:50 PM PDT 24
Finished Aug 11 06:26:54 PM PDT 24
Peak memory 217764 kb
Host smart-e90f2d42-8813-4f18-be3c-94c169bd6e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769357827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2769357827
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.499182824
Short name T568
Test name
Test status
Simulation time 28113560 ps
CPU time 1.22 seconds
Started Aug 11 06:26:55 PM PDT 24
Finished Aug 11 06:26:57 PM PDT 24
Peak memory 218488 kb
Host smart-b52b1202-d89c-4fb5-aabf-5b5f6ee0db72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499182824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.499182824
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3109563332
Short name T46
Test name
Test status
Simulation time 139508731 ps
CPU time 3.09 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:49 PM PDT 24
Peak memory 219808 kb
Host smart-7f3a5f87-992f-454b-8ece-97786d5702fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109563332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3109563332
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1581735134
Short name T728
Test name
Test status
Simulation time 31070230 ps
CPU time 1.4 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 219912 kb
Host smart-33a2aa80-c224-4dd9-8d1a-8d40de504bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581735134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1581735134
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1739643925
Short name T428
Test name
Test status
Simulation time 5006296889 ps
CPU time 92.51 seconds
Started Aug 11 06:26:49 PM PDT 24
Finished Aug 11 06:28:22 PM PDT 24
Peak memory 218544 kb
Host smart-ed5f9284-9210-47e6-9c8a-5a19d8fd99f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739643925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1739643925
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.2498413995
Short name T152
Test name
Test status
Simulation time 38658409 ps
CPU time 1.14 seconds
Started Aug 11 06:26:50 PM PDT 24
Finished Aug 11 06:26:52 PM PDT 24
Peak memory 219560 kb
Host smart-3994329d-9875-4e3a-9ee0-94c2b18a4903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498413995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2498413995
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.673304025
Short name T536
Test name
Test status
Simulation time 84783826 ps
CPU time 1.26 seconds
Started Aug 11 06:26:51 PM PDT 24
Finished Aug 11 06:26:53 PM PDT 24
Peak memory 217296 kb
Host smart-d7cd9dab-8131-45d4-92f7-07f9f0389bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673304025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.673304025
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3634047770
Short name T831
Test name
Test status
Simulation time 77027792 ps
CPU time 1.12 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 218552 kb
Host smart-8b934f66-e318-4e42-a638-a449d07944f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634047770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3634047770
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.2168441645
Short name T769
Test name
Test status
Simulation time 80488192 ps
CPU time 1.15 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 218364 kb
Host smart-79095a11-61c9-4e8c-9172-0ec632e20d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168441645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2168441645
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.1064945056
Short name T959
Test name
Test status
Simulation time 34123860 ps
CPU time 1.43 seconds
Started Aug 11 06:26:55 PM PDT 24
Finished Aug 11 06:26:56 PM PDT 24
Peak memory 217476 kb
Host smart-5d26a510-7c6d-4325-ac1d-7086819fb5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064945056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1064945056
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.1616582988
Short name T276
Test name
Test status
Simulation time 25792421 ps
CPU time 1.18 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 220640 kb
Host smart-17218b08-3dbe-43e7-9d5e-493fb73b89b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616582988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1616582988
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1148651293
Short name T368
Test name
Test status
Simulation time 49196622 ps
CPU time 1.15 seconds
Started Aug 11 06:26:55 PM PDT 24
Finished Aug 11 06:26:56 PM PDT 24
Peak memory 217404 kb
Host smart-53ac6c7f-38a3-48c8-99b2-526275b9d8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148651293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1148651293
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1004399771
Short name T190
Test name
Test status
Simulation time 39983733 ps
CPU time 1.11 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 220156 kb
Host smart-e4000a8d-727b-455b-af7c-fdf46f36a6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004399771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1004399771
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert.2151844020
Short name T456
Test name
Test status
Simulation time 109613432 ps
CPU time 1.17 seconds
Started Aug 11 06:25:32 PM PDT 24
Finished Aug 11 06:25:33 PM PDT 24
Peak memory 218624 kb
Host smart-8ef2b7d5-380a-4fa4-903c-77058a91129c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151844020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2151844020
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2884678842
Short name T841
Test name
Test status
Simulation time 45725352 ps
CPU time 0.89 seconds
Started Aug 11 06:25:29 PM PDT 24
Finished Aug 11 06:25:30 PM PDT 24
Peak memory 215220 kb
Host smart-df31fe4f-fd19-48e7-99b1-9ae7af1ff9af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884678842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2884678842
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.577098538
Short name T327
Test name
Test status
Simulation time 26563583 ps
CPU time 0.97 seconds
Started Aug 11 06:25:30 PM PDT 24
Finished Aug 11 06:25:31 PM PDT 24
Peak memory 216228 kb
Host smart-9f85136b-6b9b-419e-be62-704c9cd60ee9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577098538 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.577098538
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3933363549
Short name T901
Test name
Test status
Simulation time 38316820 ps
CPU time 1.2 seconds
Started Aug 11 06:25:32 PM PDT 24
Finished Aug 11 06:25:33 PM PDT 24
Peak memory 217208 kb
Host smart-d5bca662-2763-4eea-8fe3-48f9ebf637a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933363549 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3933363549
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1502825032
Short name T192
Test name
Test status
Simulation time 23112720 ps
CPU time 0.95 seconds
Started Aug 11 06:25:38 PM PDT 24
Finished Aug 11 06:25:39 PM PDT 24
Peak memory 218696 kb
Host smart-8f802e1f-4742-4adf-b9a1-5cb6eed2f82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502825032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1502825032
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1349760950
Short name T845
Test name
Test status
Simulation time 81464208 ps
CPU time 1.1 seconds
Started Aug 11 06:25:32 PM PDT 24
Finished Aug 11 06:25:33 PM PDT 24
Peak memory 218520 kb
Host smart-ac8f054d-d361-40fd-b453-e4d5c275e65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349760950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1349760950
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1816663673
Short name T988
Test name
Test status
Simulation time 28100642 ps
CPU time 0.96 seconds
Started Aug 11 06:25:29 PM PDT 24
Finished Aug 11 06:25:30 PM PDT 24
Peak memory 215460 kb
Host smart-3c87fdc1-65cc-4a1f-8fb3-6db81a2df352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816663673 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1816663673
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.891516558
Short name T907
Test name
Test status
Simulation time 17596139 ps
CPU time 1.04 seconds
Started Aug 11 06:25:35 PM PDT 24
Finished Aug 11 06:25:38 PM PDT 24
Peak memory 215288 kb
Host smart-386d2601-e8f3-485e-8b82-2b4fbf098dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891516558 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.891516558
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3727430605
Short name T245
Test name
Test status
Simulation time 30693708 ps
CPU time 1.16 seconds
Started Aug 11 06:25:33 PM PDT 24
Finished Aug 11 06:25:34 PM PDT 24
Peak memory 206840 kb
Host smart-9817f4f1-f1bc-4cdc-aa15-60a253ed76d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727430605 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3727430605
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1623512137
Short name T822
Test name
Test status
Simulation time 50823716208 ps
CPU time 1271.46 seconds
Started Aug 11 06:25:45 PM PDT 24
Finished Aug 11 06:46:56 PM PDT 24
Peak memory 222480 kb
Host smart-83016ec2-8031-4294-8476-12d3f63792ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623512137 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1623512137
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1465666364
Short name T996
Test name
Test status
Simulation time 56720800 ps
CPU time 1.18 seconds
Started Aug 11 06:26:51 PM PDT 24
Finished Aug 11 06:26:52 PM PDT 24
Peak memory 221416 kb
Host smart-70cc70ea-67b7-4c33-98c8-adcdbb4d0e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465666364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1465666364
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.1471908580
Short name T755
Test name
Test status
Simulation time 37537233 ps
CPU time 1.43 seconds
Started Aug 11 06:26:50 PM PDT 24
Finished Aug 11 06:26:52 PM PDT 24
Peak memory 218504 kb
Host smart-aec734e8-f860-4a7b-ae8f-0e2eb0edd51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471908580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1471908580
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.1680598036
Short name T842
Test name
Test status
Simulation time 23248145 ps
CPU time 1.12 seconds
Started Aug 11 06:26:53 PM PDT 24
Finished Aug 11 06:26:54 PM PDT 24
Peak memory 218504 kb
Host smart-101fcc5f-30d9-4650-9dd6-2e764e86a73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680598036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1680598036
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.4144406833
Short name T761
Test name
Test status
Simulation time 72195829 ps
CPU time 1.41 seconds
Started Aug 11 06:26:48 PM PDT 24
Finished Aug 11 06:26:50 PM PDT 24
Peak memory 219980 kb
Host smart-9a448198-3e9c-46db-8977-81d7fc7d258e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144406833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.4144406833
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3554015287
Short name T335
Test name
Test status
Simulation time 305809910 ps
CPU time 1.45 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:58 PM PDT 24
Peak memory 219512 kb
Host smart-570011bd-1139-40f3-8d35-1c8481f3f1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554015287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3554015287
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1497751972
Short name T966
Test name
Test status
Simulation time 123315822 ps
CPU time 1.81 seconds
Started Aug 11 06:26:48 PM PDT 24
Finished Aug 11 06:26:50 PM PDT 24
Peak memory 217492 kb
Host smart-321682d4-a734-4d65-80ff-983176ea93ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497751972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1497751972
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3654226118
Short name T523
Test name
Test status
Simulation time 49319519 ps
CPU time 0.94 seconds
Started Aug 11 06:26:50 PM PDT 24
Finished Aug 11 06:26:51 PM PDT 24
Peak memory 217264 kb
Host smart-052f706f-6206-407a-a0a8-f00381e01215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654226118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3654226118
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.25099955
Short name T915
Test name
Test status
Simulation time 34993451 ps
CPU time 1 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 219464 kb
Host smart-c198b34b-1db1-4076-8751-652301781342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25099955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.25099955
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/145.edn_alert.3172063947
Short name T954
Test name
Test status
Simulation time 27114845 ps
CPU time 1.36 seconds
Started Aug 11 06:26:53 PM PDT 24
Finished Aug 11 06:26:54 PM PDT 24
Peak memory 215540 kb
Host smart-c3752954-4800-44ba-867f-3868c198fc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172063947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3172063947
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2979534216
Short name T896
Test name
Test status
Simulation time 82588783 ps
CPU time 2.8 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:55 PM PDT 24
Peak memory 220188 kb
Host smart-de402ca2-764f-4021-a31e-a075c0693a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979534216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2979534216
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.3825160216
Short name T117
Test name
Test status
Simulation time 40391475 ps
CPU time 1.15 seconds
Started Aug 11 06:27:09 PM PDT 24
Finished Aug 11 06:27:11 PM PDT 24
Peak memory 219336 kb
Host smart-fbbdaf80-d705-4d13-9609-29bb75cf34f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825160216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.3825160216
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1599624768
Short name T654
Test name
Test status
Simulation time 70371897 ps
CPU time 1.41 seconds
Started Aug 11 06:26:49 PM PDT 24
Finished Aug 11 06:26:51 PM PDT 24
Peak memory 217636 kb
Host smart-9c0afab1-94f8-4078-b5bb-831381f5b511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599624768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1599624768
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.165476391
Short name T695
Test name
Test status
Simulation time 30038844 ps
CPU time 1.18 seconds
Started Aug 11 06:27:11 PM PDT 24
Finished Aug 11 06:27:12 PM PDT 24
Peak memory 218648 kb
Host smart-5d4c1726-7ef5-4b74-a501-b01c884ea535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165476391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.165476391
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.2697671477
Short name T314
Test name
Test status
Simulation time 74537381 ps
CPU time 1.17 seconds
Started Aug 11 06:26:55 PM PDT 24
Finished Aug 11 06:26:56 PM PDT 24
Peak memory 218748 kb
Host smart-b3496b29-fb4b-43bb-9051-a4ef5bef4b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697671477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2697671477
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.746218101
Short name T945
Test name
Test status
Simulation time 41625383 ps
CPU time 1.24 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:53 PM PDT 24
Peak memory 218632 kb
Host smart-0c508308-6760-4bee-a228-340dcf69308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746218101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.746218101
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/149.edn_alert.3980724049
Short name T197
Test name
Test status
Simulation time 34338464 ps
CPU time 1.21 seconds
Started Aug 11 06:26:59 PM PDT 24
Finished Aug 11 06:27:00 PM PDT 24
Peak memory 219956 kb
Host smart-ba584c50-28f5-440d-9312-28b6d407efff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980724049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3980724049
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3556864408
Short name T803
Test name
Test status
Simulation time 31766624 ps
CPU time 1.34 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:54 PM PDT 24
Peak memory 215300 kb
Host smart-8040fdc4-467d-46e9-85d3-c8fd66c31b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556864408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3556864408
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1363133410
Short name T923
Test name
Test status
Simulation time 25438951 ps
CPU time 1.23 seconds
Started Aug 11 06:25:29 PM PDT 24
Finished Aug 11 06:25:31 PM PDT 24
Peak memory 218484 kb
Host smart-a493fa9f-f1b2-4872-b4a1-73275a8a446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363133410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1363133410
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3625683386
Short name T342
Test name
Test status
Simulation time 21066876 ps
CPU time 1.01 seconds
Started Aug 11 06:25:30 PM PDT 24
Finished Aug 11 06:25:32 PM PDT 24
Peak memory 206836 kb
Host smart-b857aae9-e921-4c54-993d-dd4df4b2f033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625683386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3625683386
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.573790638
Short name T184
Test name
Test status
Simulation time 20817377 ps
CPU time 0.89 seconds
Started Aug 11 06:25:30 PM PDT 24
Finished Aug 11 06:25:31 PM PDT 24
Peak memory 219192 kb
Host smart-c7b07502-9b17-424d-9588-a28a8977c935
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573790638 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.573790638
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1642780493
Short name T550
Test name
Test status
Simulation time 37702988 ps
CPU time 1.24 seconds
Started Aug 11 06:25:31 PM PDT 24
Finished Aug 11 06:25:33 PM PDT 24
Peak memory 219752 kb
Host smart-73981801-3331-4f21-ba94-bf21043d5cb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642780493 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1642780493
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3831567324
Short name T930
Test name
Test status
Simulation time 163288442 ps
CPU time 1.22 seconds
Started Aug 11 06:25:32 PM PDT 24
Finished Aug 11 06:25:34 PM PDT 24
Peak memory 225932 kb
Host smart-43367132-fa45-4f63-ab73-a67a82ead1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831567324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3831567324
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2911884244
Short name T531
Test name
Test status
Simulation time 46079892 ps
CPU time 1.29 seconds
Started Aug 11 06:25:29 PM PDT 24
Finished Aug 11 06:25:30 PM PDT 24
Peak memory 219888 kb
Host smart-247e53f8-8a54-4378-a2e2-2d1636b0fc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911884244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2911884244
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2397835956
Short name T386
Test name
Test status
Simulation time 44649709 ps
CPU time 0.84 seconds
Started Aug 11 06:25:34 PM PDT 24
Finished Aug 11 06:25:35 PM PDT 24
Peak memory 215160 kb
Host smart-e3007c2f-adee-4a29-80b9-867472f513f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397835956 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2397835956
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3950181540
Short name T344
Test name
Test status
Simulation time 16032324 ps
CPU time 1 seconds
Started Aug 11 06:25:34 PM PDT 24
Finished Aug 11 06:25:35 PM PDT 24
Peak memory 215292 kb
Host smart-a7cd75ef-f68b-4111-b933-8d1796d17222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950181540 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3950181540
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1232752724
Short name T847
Test name
Test status
Simulation time 72573341 ps
CPU time 1.99 seconds
Started Aug 11 06:25:30 PM PDT 24
Finished Aug 11 06:25:33 PM PDT 24
Peak memory 218744 kb
Host smart-6dd657c1-4ba1-4da8-91d2-0879395af6f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232752724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1232752724
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.479147642
Short name T490
Test name
Test status
Simulation time 17106431405 ps
CPU time 195.3 seconds
Started Aug 11 06:25:35 PM PDT 24
Finished Aug 11 06:28:52 PM PDT 24
Peak memory 222928 kb
Host smart-c6a9e115-f06b-46c3-a6db-1b7a09033357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479147642 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.479147642
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2324102022
Short name T936
Test name
Test status
Simulation time 47199812 ps
CPU time 1.15 seconds
Started Aug 11 06:26:51 PM PDT 24
Finished Aug 11 06:26:52 PM PDT 24
Peak memory 219564 kb
Host smart-27ac3e30-5066-427e-b476-5d842d89dd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324102022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2324102022
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.494507017
Short name T858
Test name
Test status
Simulation time 80838352 ps
CPU time 1.48 seconds
Started Aug 11 06:26:56 PM PDT 24
Finished Aug 11 06:26:57 PM PDT 24
Peak memory 218992 kb
Host smart-b1d0aa7f-060f-4811-9fdf-a1787c5a01bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494507017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.494507017
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1761930505
Short name T625
Test name
Test status
Simulation time 31075945 ps
CPU time 1.1 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:53 PM PDT 24
Peak memory 219668 kb
Host smart-b576260a-3510-4e20-be29-2cf9254b6241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761930505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1761930505
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3701049159
Short name T652
Test name
Test status
Simulation time 35071141 ps
CPU time 1.04 seconds
Started Aug 11 06:27:00 PM PDT 24
Finished Aug 11 06:27:01 PM PDT 24
Peak memory 215444 kb
Host smart-0c80f664-a21e-4b88-b67a-7f008a0bbfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701049159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3701049159
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.150667463
Short name T663
Test name
Test status
Simulation time 30565710 ps
CPU time 1.32 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:54 PM PDT 24
Peak memory 215544 kb
Host smart-3300e637-db4a-478e-ae09-d1acd7b86721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150667463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.150667463
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.850986828
Short name T583
Test name
Test status
Simulation time 59157816 ps
CPU time 1.56 seconds
Started Aug 11 06:26:54 PM PDT 24
Finished Aug 11 06:26:56 PM PDT 24
Peak memory 218680 kb
Host smart-94fdf62c-6b8b-4e49-b663-c50c0ebe7908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850986828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.850986828
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.509622381
Short name T855
Test name
Test status
Simulation time 103298539 ps
CPU time 1.04 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:53 PM PDT 24
Peak memory 219508 kb
Host smart-11326e99-bb4b-4d46-8a85-2bc0d31b595b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509622381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.509622381
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3932922727
Short name T974
Test name
Test status
Simulation time 53370571 ps
CPU time 1.59 seconds
Started Aug 11 06:26:57 PM PDT 24
Finished Aug 11 06:26:59 PM PDT 24
Peak memory 218764 kb
Host smart-4cf9e7a9-49f8-479f-a6c6-525d9f74e19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932922727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3932922727
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.2505171065
Short name T553
Test name
Test status
Simulation time 40519693 ps
CPU time 1.12 seconds
Started Aug 11 06:27:00 PM PDT 24
Finished Aug 11 06:27:01 PM PDT 24
Peak memory 218420 kb
Host smart-62a0ae46-f812-49cb-ad12-0c6d99c8605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505171065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.2505171065
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.4090443581
Short name T1
Test name
Test status
Simulation time 136222375 ps
CPU time 1.68 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:54 PM PDT 24
Peak memory 218760 kb
Host smart-3ecb7f9d-0008-4109-8708-79ec8a2ac32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090443581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.4090443581
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3427410578
Short name T228
Test name
Test status
Simulation time 101283219 ps
CPU time 1.32 seconds
Started Aug 11 06:26:57 PM PDT 24
Finished Aug 11 06:26:59 PM PDT 24
Peak memory 215704 kb
Host smart-540b0491-2dc0-4e10-90d6-02e3c217cad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427410578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3427410578
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/156.edn_alert.3895588919
Short name T986
Test name
Test status
Simulation time 39536067 ps
CPU time 1.12 seconds
Started Aug 11 06:26:57 PM PDT 24
Finished Aug 11 06:26:58 PM PDT 24
Peak memory 218412 kb
Host smart-c6009c21-6d2f-4191-81ef-e806aee4fd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895588919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3895588919
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2687056843
Short name T759
Test name
Test status
Simulation time 38448412 ps
CPU time 1.27 seconds
Started Aug 11 06:26:51 PM PDT 24
Finished Aug 11 06:26:52 PM PDT 24
Peak memory 218592 kb
Host smart-bf0deb7c-8a62-4605-af3a-e7613469abf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687056843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2687056843
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.575948794
Short name T909
Test name
Test status
Simulation time 39617948 ps
CPU time 1.09 seconds
Started Aug 11 06:26:51 PM PDT 24
Finished Aug 11 06:26:52 PM PDT 24
Peak memory 219420 kb
Host smart-1faa3c47-1fae-4d76-85b7-5f4308e6e97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575948794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.575948794
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.2425293072
Short name T313
Test name
Test status
Simulation time 33983173 ps
CPU time 1.51 seconds
Started Aug 11 06:26:50 PM PDT 24
Finished Aug 11 06:26:52 PM PDT 24
Peak memory 217464 kb
Host smart-dcd23c70-50a5-44a4-868a-bacc1467e8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425293072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2425293072
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.30559672
Short name T795
Test name
Test status
Simulation time 28550532 ps
CPU time 1.33 seconds
Started Aug 11 06:27:13 PM PDT 24
Finished Aug 11 06:27:14 PM PDT 24
Peak memory 220552 kb
Host smart-a1bff819-1cd8-4a5c-9376-16242642060e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30559672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.30559672
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1608695672
Short name T311
Test name
Test status
Simulation time 52239065 ps
CPU time 1.28 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:53 PM PDT 24
Peak memory 217240 kb
Host smart-932d798d-9c37-41ac-9d97-4cae22143951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608695672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1608695672
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.1978811231
Short name T920
Test name
Test status
Simulation time 36008846 ps
CPU time 1.17 seconds
Started Aug 11 06:26:50 PM PDT 24
Finished Aug 11 06:26:52 PM PDT 24
Peak memory 219444 kb
Host smart-934e972a-8f46-40c6-8689-28ee59959a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978811231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.1978811231
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1387490209
Short name T698
Test name
Test status
Simulation time 92938580 ps
CPU time 1.53 seconds
Started Aug 11 06:26:50 PM PDT 24
Finished Aug 11 06:26:51 PM PDT 24
Peak memory 218448 kb
Host smart-69f4831b-e557-411a-a95d-36d9a9785e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387490209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1387490209
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3265003522
Short name T492
Test name
Test status
Simulation time 39322040 ps
CPU time 1.24 seconds
Started Aug 11 06:25:33 PM PDT 24
Finished Aug 11 06:25:34 PM PDT 24
Peak memory 219724 kb
Host smart-f81c5714-3708-477e-846a-2a11c58a6c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265003522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3265003522
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.4243774945
Short name T345
Test name
Test status
Simulation time 14875768 ps
CPU time 0.86 seconds
Started Aug 11 06:25:36 PM PDT 24
Finished Aug 11 06:25:37 PM PDT 24
Peak memory 206768 kb
Host smart-02497529-eaa2-46da-a6ab-096226662cd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243774945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.4243774945
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3725675856
Short name T226
Test name
Test status
Simulation time 41399326 ps
CPU time 0.88 seconds
Started Aug 11 06:25:32 PM PDT 24
Finished Aug 11 06:25:34 PM PDT 24
Peak memory 215340 kb
Host smart-89593b50-0d21-4a00-9b56-f3b2abe0d63b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725675856 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3725675856
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1522545413
Short name T602
Test name
Test status
Simulation time 29808663 ps
CPU time 1.16 seconds
Started Aug 11 06:25:37 PM PDT 24
Finished Aug 11 06:25:38 PM PDT 24
Peak memory 218688 kb
Host smart-e6a7c16e-86fc-46a6-980e-ac68dbdd2e7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522545413 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1522545413
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3798636371
Short name T781
Test name
Test status
Simulation time 57261897 ps
CPU time 1.12 seconds
Started Aug 11 06:25:32 PM PDT 24
Finished Aug 11 06:25:33 PM PDT 24
Peak memory 220124 kb
Host smart-653b2be1-9fb8-41f3-baee-793501b3101a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798636371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3798636371
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.242332249
Short name T838
Test name
Test status
Simulation time 72803472 ps
CPU time 1.17 seconds
Started Aug 11 06:25:30 PM PDT 24
Finished Aug 11 06:25:31 PM PDT 24
Peak memory 219988 kb
Host smart-f5a88e9b-dd54-4de8-ada9-fc8476d430ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242332249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.242332249
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3852378930
Short name T699
Test name
Test status
Simulation time 28646318 ps
CPU time 1.02 seconds
Started Aug 11 06:25:31 PM PDT 24
Finished Aug 11 06:25:37 PM PDT 24
Peak memory 215376 kb
Host smart-a99b014e-41c1-409b-89da-638f46b8ef48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852378930 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3852378930
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1046269188
Short name T447
Test name
Test status
Simulation time 41336531 ps
CPU time 0.93 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 215236 kb
Host smart-068c613f-e427-4dae-803d-7be5ff9fec37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046269188 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1046269188
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3613633185
Short name T758
Test name
Test status
Simulation time 211855436 ps
CPU time 1.39 seconds
Started Aug 11 06:25:29 PM PDT 24
Finished Aug 11 06:25:31 PM PDT 24
Peak memory 217228 kb
Host smart-4fdf8907-8ddf-4c9e-ac2e-b049fa24a5a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613633185 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3613633185
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2034973793
Short name T853
Test name
Test status
Simulation time 15367072385 ps
CPU time 377.53 seconds
Started Aug 11 06:25:37 PM PDT 24
Finished Aug 11 06:31:54 PM PDT 24
Peak memory 223392 kb
Host smart-e723de1b-46eb-4e03-9bab-1aa66a02d2a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034973793 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2034973793
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.1552834905
Short name T440
Test name
Test status
Simulation time 53197828 ps
CPU time 1.22 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:53 PM PDT 24
Peak memory 218508 kb
Host smart-b0088c38-86fa-4d21-98f6-a4680fb2d0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552834905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.1552834905
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.746174559
Short name T594
Test name
Test status
Simulation time 61071533 ps
CPU time 1.33 seconds
Started Aug 11 06:26:55 PM PDT 24
Finished Aug 11 06:26:57 PM PDT 24
Peak memory 219684 kb
Host smart-a403ee89-b45b-4c27-8178-5e3c2ad4dd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746174559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.746174559
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.86082818
Short name T960
Test name
Test status
Simulation time 50375577 ps
CPU time 1.26 seconds
Started Aug 11 06:27:11 PM PDT 24
Finished Aug 11 06:27:12 PM PDT 24
Peak memory 218304 kb
Host smart-eaf9f044-0286-4cf6-ad93-9b9ff6b2761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86082818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.86082818
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2635203605
Short name T240
Test name
Test status
Simulation time 70319057 ps
CPU time 1.6 seconds
Started Aug 11 06:26:54 PM PDT 24
Finished Aug 11 06:26:56 PM PDT 24
Peak memory 218768 kb
Host smart-c6a0439a-f163-4a22-bda3-4301f06f5bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635203605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2635203605
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.740549322
Short name T882
Test name
Test status
Simulation time 76397211 ps
CPU time 1.15 seconds
Started Aug 11 06:27:09 PM PDT 24
Finished Aug 11 06:27:10 PM PDT 24
Peak memory 220328 kb
Host smart-383e0f9f-e058-4a8c-b284-7a62c0dbf1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740549322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.740549322
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.2865686344
Short name T381
Test name
Test status
Simulation time 140748454 ps
CPU time 3.03 seconds
Started Aug 11 06:26:52 PM PDT 24
Finished Aug 11 06:26:55 PM PDT 24
Peak memory 219964 kb
Host smart-38e63d4a-8386-41f2-a3a2-cea5d8056c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865686344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2865686344
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.381488662
Short name T599
Test name
Test status
Simulation time 44192044 ps
CPU time 1.22 seconds
Started Aug 11 06:26:51 PM PDT 24
Finished Aug 11 06:26:52 PM PDT 24
Peak memory 219604 kb
Host smart-d3d93e62-709b-42a4-9a6f-390ace440401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381488662 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.381488662
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1339900747
Short name T629
Test name
Test status
Simulation time 75630391 ps
CPU time 1.63 seconds
Started Aug 11 06:26:55 PM PDT 24
Finished Aug 11 06:26:56 PM PDT 24
Peak memory 218756 kb
Host smart-f96146ce-733e-4140-bfef-f3331fbc9eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339900747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1339900747
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.3325803174
Short name T181
Test name
Test status
Simulation time 67710450 ps
CPU time 1.07 seconds
Started Aug 11 06:26:53 PM PDT 24
Finished Aug 11 06:26:54 PM PDT 24
Peak memory 215492 kb
Host smart-d0159598-bf49-4f03-aba1-831db3f22d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325803174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3325803174
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.4254449380
Short name T932
Test name
Test status
Simulation time 81732576 ps
CPU time 1.13 seconds
Started Aug 11 06:26:50 PM PDT 24
Finished Aug 11 06:26:51 PM PDT 24
Peak memory 217348 kb
Host smart-bcd96baa-93b1-4f42-95e5-becd93c4b2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254449380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4254449380
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.1572898695
Short name T905
Test name
Test status
Simulation time 58285733 ps
CPU time 1.25 seconds
Started Aug 11 06:26:50 PM PDT 24
Finished Aug 11 06:26:52 PM PDT 24
Peak memory 220776 kb
Host smart-b4b6b8f3-450c-44bf-b19a-4220d716650c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572898695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.1572898695
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3662853292
Short name T350
Test name
Test status
Simulation time 55506535 ps
CPU time 1.08 seconds
Started Aug 11 06:26:59 PM PDT 24
Finished Aug 11 06:27:00 PM PDT 24
Peak memory 217428 kb
Host smart-722d152e-0430-4617-9919-754eb7a5d062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662853292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3662853292
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.3262026919
Short name T322
Test name
Test status
Simulation time 48957442 ps
CPU time 1.65 seconds
Started Aug 11 06:26:57 PM PDT 24
Finished Aug 11 06:26:59 PM PDT 24
Peak memory 218860 kb
Host smart-723a3f80-ddc3-4116-ad38-bf4e05c4fbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262026919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3262026919
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.4011472430
Short name T854
Test name
Test status
Simulation time 28868520 ps
CPU time 1.27 seconds
Started Aug 11 06:26:59 PM PDT 24
Finished Aug 11 06:27:01 PM PDT 24
Peak memory 219472 kb
Host smart-c4505f83-8bbc-481a-9d61-f86b9d0b1a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011472430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.4011472430
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.257981415
Short name T421
Test name
Test status
Simulation time 49656596 ps
CPU time 1.59 seconds
Started Aug 11 06:27:17 PM PDT 24
Finished Aug 11 06:27:18 PM PDT 24
Peak memory 218372 kb
Host smart-3e29e576-07b7-4272-92f5-9226bcd120ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257981415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.257981415
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.961638306
Short name T396
Test name
Test status
Simulation time 124284893 ps
CPU time 1.35 seconds
Started Aug 11 06:27:10 PM PDT 24
Finished Aug 11 06:27:11 PM PDT 24
Peak memory 219464 kb
Host smart-705249dd-4d04-4fb4-a5ee-36e5b96f75dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961638306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.961638306
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1332420874
Short name T731
Test name
Test status
Simulation time 50089200 ps
CPU time 1.34 seconds
Started Aug 11 06:26:58 PM PDT 24
Finished Aug 11 06:26:59 PM PDT 24
Peak memory 218476 kb
Host smart-2b56f2ab-4c31-4cfe-8230-f279f41f5e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332420874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1332420874
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.383417846
Short name T394
Test name
Test status
Simulation time 39361453 ps
CPU time 1.36 seconds
Started Aug 11 06:27:08 PM PDT 24
Finished Aug 11 06:27:10 PM PDT 24
Peak memory 215296 kb
Host smart-cbe23156-144a-4cfe-bf75-dab7f5218404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383417846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.383417846
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.3151137669
Short name T445
Test name
Test status
Simulation time 32185170 ps
CPU time 0.95 seconds
Started Aug 11 06:25:36 PM PDT 24
Finished Aug 11 06:25:37 PM PDT 24
Peak memory 206816 kb
Host smart-2072637d-d741-4baf-9b04-36b151f156ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151137669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3151137669
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3301137655
Short name T81
Test name
Test status
Simulation time 15565523 ps
CPU time 0.89 seconds
Started Aug 11 06:25:37 PM PDT 24
Finished Aug 11 06:25:38 PM PDT 24
Peak memory 216768 kb
Host smart-80d62d6b-8fde-41c3-96b7-9422e49fcbcc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301137655 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3301137655
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1057066990
Short name T119
Test name
Test status
Simulation time 49758846 ps
CPU time 1.11 seconds
Started Aug 11 06:25:45 PM PDT 24
Finished Aug 11 06:25:46 PM PDT 24
Peak memory 217232 kb
Host smart-e1c7383d-6328-441f-bed7-1c3a873435a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057066990 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1057066990
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1691618023
Short name T632
Test name
Test status
Simulation time 50171204 ps
CPU time 0.97 seconds
Started Aug 11 06:25:40 PM PDT 24
Finished Aug 11 06:25:42 PM PDT 24
Peak memory 220092 kb
Host smart-1b1540f0-341a-4d91-a886-5ce56a6e9592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691618023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1691618023
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2782747401
Short name T298
Test name
Test status
Simulation time 33808498 ps
CPU time 1.1 seconds
Started Aug 11 06:25:36 PM PDT 24
Finished Aug 11 06:25:37 PM PDT 24
Peak memory 217276 kb
Host smart-85f5aaa2-1552-4d93-83c8-8f62ea3783c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782747401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2782747401
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3038528617
Short name T754
Test name
Test status
Simulation time 41588992 ps
CPU time 0.89 seconds
Started Aug 11 06:25:44 PM PDT 24
Finished Aug 11 06:25:45 PM PDT 24
Peak memory 215448 kb
Host smart-cd8ca30c-c837-483c-adab-3308f4f6ff4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038528617 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3038528617
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.563298895
Short name T435
Test name
Test status
Simulation time 72530519 ps
CPU time 0.94 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 215292 kb
Host smart-aa45d552-8992-4d88-9579-2cbba7c3f1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563298895 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.563298895
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3606770128
Short name T820
Test name
Test status
Simulation time 502867169 ps
CPU time 3.26 seconds
Started Aug 11 06:25:42 PM PDT 24
Finished Aug 11 06:25:46 PM PDT 24
Peak memory 215220 kb
Host smart-96440e8e-1427-4820-ad41-7ec68a9a58a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606770128 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3606770128
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2683772278
Short name T39
Test name
Test status
Simulation time 67198499050 ps
CPU time 1449.7 seconds
Started Aug 11 06:25:38 PM PDT 24
Finished Aug 11 06:49:48 PM PDT 24
Peak memory 221648 kb
Host smart-dbccf90c-0e4e-4c46-a701-2b16b0fa1085
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683772278 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2683772278
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.4221287195
Short name T169
Test name
Test status
Simulation time 28608377 ps
CPU time 1.31 seconds
Started Aug 11 06:27:11 PM PDT 24
Finished Aug 11 06:27:12 PM PDT 24
Peak memory 219936 kb
Host smart-8217c8bd-8131-42b5-944a-e924575b7b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221287195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.4221287195
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.722570762
Short name T778
Test name
Test status
Simulation time 46664287 ps
CPU time 1.02 seconds
Started Aug 11 06:27:03 PM PDT 24
Finished Aug 11 06:27:04 PM PDT 24
Peak memory 217404 kb
Host smart-ca93b512-6530-4e4f-9afc-bae9dc98db86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722570762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.722570762
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.2792080621
Short name T948
Test name
Test status
Simulation time 40213235 ps
CPU time 1.13 seconds
Started Aug 11 06:26:54 PM PDT 24
Finished Aug 11 06:26:56 PM PDT 24
Peak memory 218492 kb
Host smart-f06a758d-44a6-492c-aca1-bfd33b78d9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792080621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2792080621
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.889290522
Short name T518
Test name
Test status
Simulation time 39878322 ps
CPU time 1.54 seconds
Started Aug 11 06:26:59 PM PDT 24
Finished Aug 11 06:27:01 PM PDT 24
Peak memory 219056 kb
Host smart-9d888103-ae03-41ca-9c9a-cf3236c9cbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889290522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.889290522
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.104664364
Short name T547
Test name
Test status
Simulation time 25671610 ps
CPU time 1.2 seconds
Started Aug 11 06:27:11 PM PDT 24
Finished Aug 11 06:27:12 PM PDT 24
Peak memory 220624 kb
Host smart-64f83db0-c2a0-436a-800e-2f2d4ef4ddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104664364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.104664364
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.21221885
Short name T316
Test name
Test status
Simulation time 92730074 ps
CPU time 1.14 seconds
Started Aug 11 06:27:08 PM PDT 24
Finished Aug 11 06:27:10 PM PDT 24
Peak memory 217400 kb
Host smart-e97b6b70-58ee-4413-913e-e04a4919d8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21221885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.21221885
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3050009014
Short name T634
Test name
Test status
Simulation time 36369182 ps
CPU time 1.15 seconds
Started Aug 11 06:27:00 PM PDT 24
Finished Aug 11 06:27:01 PM PDT 24
Peak memory 220112 kb
Host smart-2cb137a9-4f83-418e-9fba-79fccbfccaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050009014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3050009014
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1498027550
Short name T641
Test name
Test status
Simulation time 171518453 ps
CPU time 1.29 seconds
Started Aug 11 06:26:59 PM PDT 24
Finished Aug 11 06:27:01 PM PDT 24
Peak memory 219208 kb
Host smart-90345f43-e8bc-4905-bd2a-3b94e4a1cf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498027550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1498027550
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.390995157
Short name T114
Test name
Test status
Simulation time 89078104 ps
CPU time 1.17 seconds
Started Aug 11 06:27:14 PM PDT 24
Finished Aug 11 06:27:16 PM PDT 24
Peak memory 220116 kb
Host smart-8ec79376-be60-4af5-b098-ede6254d8a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390995157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.390995157
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2853592664
Short name T994
Test name
Test status
Simulation time 68164469 ps
CPU time 1.25 seconds
Started Aug 11 06:26:56 PM PDT 24
Finished Aug 11 06:26:57 PM PDT 24
Peak memory 218908 kb
Host smart-84064755-4f26-47e6-8013-83159bcabc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853592664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2853592664
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.4222657302
Short name T582
Test name
Test status
Simulation time 48638437 ps
CPU time 1.3 seconds
Started Aug 11 06:27:00 PM PDT 24
Finished Aug 11 06:27:01 PM PDT 24
Peak memory 218928 kb
Host smart-f95474ee-07b8-4685-93b4-0eaa5ade15e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222657302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.4222657302
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2052823126
Short name T100
Test name
Test status
Simulation time 25869443 ps
CPU time 1.29 seconds
Started Aug 11 06:26:59 PM PDT 24
Finished Aug 11 06:27:00 PM PDT 24
Peak memory 220480 kb
Host smart-aca338f2-3a88-452d-bff2-0ff9f8589a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052823126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2052823126
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.1536801381
Short name T998
Test name
Test status
Simulation time 69456450 ps
CPU time 1.07 seconds
Started Aug 11 06:26:58 PM PDT 24
Finished Aug 11 06:26:59 PM PDT 24
Peak memory 217224 kb
Host smart-29e9823e-72cd-44c3-a748-39a17c6629a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536801381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1536801381
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.266004576
Short name T745
Test name
Test status
Simulation time 49985753 ps
CPU time 1.35 seconds
Started Aug 11 06:27:02 PM PDT 24
Finished Aug 11 06:27:03 PM PDT 24
Peak memory 215568 kb
Host smart-752ad215-2aab-4c8e-a89d-11602ac1609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266004576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.266004576
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.3222321349
Short name T645
Test name
Test status
Simulation time 40385575 ps
CPU time 1.6 seconds
Started Aug 11 06:27:07 PM PDT 24
Finished Aug 11 06:27:08 PM PDT 24
Peak memory 218732 kb
Host smart-b50f5831-7d91-4a66-8fea-9f8f7d2c875a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222321349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3222321349
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2410662823
Short name T688
Test name
Test status
Simulation time 25700516 ps
CPU time 1.22 seconds
Started Aug 11 06:26:57 PM PDT 24
Finished Aug 11 06:26:58 PM PDT 24
Peak memory 220472 kb
Host smart-5bd926ab-056c-409a-840c-4c61bc48aa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410662823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2410662823
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/179.edn_alert.2888043732
Short name T103
Test name
Test status
Simulation time 374116219 ps
CPU time 1.17 seconds
Started Aug 11 06:27:13 PM PDT 24
Finished Aug 11 06:27:14 PM PDT 24
Peak memory 219552 kb
Host smart-282ff558-344d-4e95-bcc9-f2ebeac38dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888043732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2888043732
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2441232385
Short name T815
Test name
Test status
Simulation time 70153706 ps
CPU time 2.5 seconds
Started Aug 11 06:26:57 PM PDT 24
Finished Aug 11 06:26:59 PM PDT 24
Peak memory 219992 kb
Host smart-80f7da15-ad67-4104-bcdc-7498b68f347f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441232385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2441232385
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.893517730
Short name T850
Test name
Test status
Simulation time 36227464 ps
CPU time 1.27 seconds
Started Aug 11 06:25:42 PM PDT 24
Finished Aug 11 06:25:43 PM PDT 24
Peak memory 219724 kb
Host smart-dba0dbe6-1a77-4e6d-8c15-3ec46137e3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893517730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.893517730
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.4175718495
Short name T494
Test name
Test status
Simulation time 24388265 ps
CPU time 1.16 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:41 PM PDT 24
Peak memory 206892 kb
Host smart-48df2ae3-d9d6-4768-be96-feaba2855253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175718495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.4175718495
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3801984616
Short name T128
Test name
Test status
Simulation time 34476489 ps
CPU time 1.22 seconds
Started Aug 11 06:25:37 PM PDT 24
Finished Aug 11 06:25:39 PM PDT 24
Peak memory 217224 kb
Host smart-cab1463d-ea25-48f4-b576-0f02ed1555fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801984616 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3801984616
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1986680055
Short name T869
Test name
Test status
Simulation time 24377440 ps
CPU time 0.98 seconds
Started Aug 11 06:25:42 PM PDT 24
Finished Aug 11 06:25:43 PM PDT 24
Peak memory 218664 kb
Host smart-ce19fc79-1a06-4899-8415-e2e68a9cbc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986680055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1986680055
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_smoke.2766647559
Short name T772
Test name
Test status
Simulation time 28358357 ps
CPU time 1 seconds
Started Aug 11 06:25:48 PM PDT 24
Finished Aug 11 06:25:50 PM PDT 24
Peak memory 215332 kb
Host smart-ca54aed3-190a-47d9-92cc-3f501ff8d44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766647559 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2766647559
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.393200146
Short name T856
Test name
Test status
Simulation time 1097956597 ps
CPU time 4.14 seconds
Started Aug 11 06:25:40 PM PDT 24
Finished Aug 11 06:25:44 PM PDT 24
Peak memory 215276 kb
Host smart-a0f722a9-39ae-4f8a-9cd1-417d8e34ca2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393200146 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.393200146
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2519529082
Short name T656
Test name
Test status
Simulation time 57297054439 ps
CPU time 1219.42 seconds
Started Aug 11 06:25:44 PM PDT 24
Finished Aug 11 06:46:04 PM PDT 24
Peak memory 223612 kb
Host smart-c8503804-e124-4444-b487-00324b4d182d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519529082 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2519529082
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1489663716
Short name T411
Test name
Test status
Simulation time 22573104 ps
CPU time 1.19 seconds
Started Aug 11 06:27:03 PM PDT 24
Finished Aug 11 06:27:04 PM PDT 24
Peak memory 219532 kb
Host smart-d536ad45-224d-4ec7-b11f-6ca6e1fa506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489663716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1489663716
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.940241902
Short name T374
Test name
Test status
Simulation time 44945413 ps
CPU time 1.8 seconds
Started Aug 11 06:27:18 PM PDT 24
Finished Aug 11 06:27:20 PM PDT 24
Peak memory 218460 kb
Host smart-4ae62759-14b3-493a-8327-56e9a161ca3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940241902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.940241902
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.190874013
Short name T535
Test name
Test status
Simulation time 118023800 ps
CPU time 1.24 seconds
Started Aug 11 06:27:04 PM PDT 24
Finished Aug 11 06:27:06 PM PDT 24
Peak memory 220036 kb
Host smart-8d66b5fb-a55d-4c7d-9da8-95a54ade3fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190874013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.190874013
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3582025011
Short name T692
Test name
Test status
Simulation time 97184037 ps
CPU time 1.25 seconds
Started Aug 11 06:27:03 PM PDT 24
Finished Aug 11 06:27:05 PM PDT 24
Peak memory 217408 kb
Host smart-9ff20f99-3137-4249-ad50-e15bf1345d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582025011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3582025011
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3388296854
Short name T180
Test name
Test status
Simulation time 40107029 ps
CPU time 1.1 seconds
Started Aug 11 06:27:17 PM PDT 24
Finished Aug 11 06:27:19 PM PDT 24
Peak memory 218480 kb
Host smart-5922aea6-d778-42e9-97b2-31eaa954e542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388296854 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3388296854
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.3952685333
Short name T384
Test name
Test status
Simulation time 46678982 ps
CPU time 1.28 seconds
Started Aug 11 06:27:09 PM PDT 24
Finished Aug 11 06:27:10 PM PDT 24
Peak memory 217376 kb
Host smart-15154a8e-e68a-45ef-93ab-8fe9ed2b04cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952685333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3952685333
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1310868291
Short name T658
Test name
Test status
Simulation time 88241806 ps
CPU time 1.21 seconds
Started Aug 11 06:27:15 PM PDT 24
Finished Aug 11 06:27:16 PM PDT 24
Peak memory 218460 kb
Host smart-4edacdad-07a9-4756-941a-19c8245e9c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310868291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1310868291
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.4055104059
Short name T498
Test name
Test status
Simulation time 859597464 ps
CPU time 6.33 seconds
Started Aug 11 06:27:03 PM PDT 24
Finished Aug 11 06:27:10 PM PDT 24
Peak memory 220456 kb
Host smart-9fc0c46c-09cd-4d81-9dee-c3b3e2a7a8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055104059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.4055104059
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.1041017504
Short name T438
Test name
Test status
Simulation time 160372382 ps
CPU time 1.14 seconds
Started Aug 11 06:27:18 PM PDT 24
Finished Aug 11 06:27:19 PM PDT 24
Peak memory 218536 kb
Host smart-b6acc56b-ff6e-4a79-a463-9d2b0ac5b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041017504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.1041017504
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.3850126773
Short name T356
Test name
Test status
Simulation time 45305619 ps
CPU time 1.3 seconds
Started Aug 11 06:27:04 PM PDT 24
Finished Aug 11 06:27:05 PM PDT 24
Peak memory 218656 kb
Host smart-ceb7bab7-c8f8-4f6f-b50e-51434eedbd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850126773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3850126773
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.4206429979
Short name T774
Test name
Test status
Simulation time 34900177 ps
CPU time 1.07 seconds
Started Aug 11 06:27:03 PM PDT 24
Finished Aug 11 06:27:04 PM PDT 24
Peak memory 219612 kb
Host smart-5e1b1326-b8bb-48bb-ad1a-2614205df28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206429979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.4206429979
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.2134268627
Short name T239
Test name
Test status
Simulation time 235334728 ps
CPU time 2.73 seconds
Started Aug 11 06:27:04 PM PDT 24
Finished Aug 11 06:27:07 PM PDT 24
Peak memory 219828 kb
Host smart-3a466d23-cff7-4113-9243-1667e2fbc370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134268627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2134268627
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1963432532
Short name T710
Test name
Test status
Simulation time 24361505 ps
CPU time 1.25 seconds
Started Aug 11 06:27:25 PM PDT 24
Finished Aug 11 06:27:27 PM PDT 24
Peak memory 220172 kb
Host smart-0b371b27-86f1-4c8e-9cb7-1f2490ed0d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963432532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1963432532
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.532206914
Short name T524
Test name
Test status
Simulation time 76544164 ps
CPU time 1.29 seconds
Started Aug 11 06:27:08 PM PDT 24
Finished Aug 11 06:27:09 PM PDT 24
Peak memory 217428 kb
Host smart-65f9985f-a479-423e-b284-f6e08b746e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532206914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.532206914
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2529920362
Short name T533
Test name
Test status
Simulation time 23994900 ps
CPU time 1.15 seconds
Started Aug 11 06:27:03 PM PDT 24
Finished Aug 11 06:27:05 PM PDT 24
Peak memory 218512 kb
Host smart-339eb1ab-a478-4d5c-9eb6-5edb289fec2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529920362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2529920362
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3935331605
Short name T468
Test name
Test status
Simulation time 96186145 ps
CPU time 0.97 seconds
Started Aug 11 06:27:15 PM PDT 24
Finished Aug 11 06:27:16 PM PDT 24
Peak memory 217348 kb
Host smart-cc55446b-60dc-47d6-a0c4-9acf24a63d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935331605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3935331605
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.1620368799
Short name T706
Test name
Test status
Simulation time 161813304 ps
CPU time 1.18 seconds
Started Aug 11 06:27:17 PM PDT 24
Finished Aug 11 06:27:18 PM PDT 24
Peak memory 219864 kb
Host smart-5f3a689a-8fe0-4830-9ff1-5aef0431a660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620368799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1620368799
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.3387286830
Short name T439
Test name
Test status
Simulation time 51774134 ps
CPU time 1.28 seconds
Started Aug 11 06:27:15 PM PDT 24
Finished Aug 11 06:27:16 PM PDT 24
Peak memory 217492 kb
Host smart-43bc2ca6-c77a-4767-bf1d-a038e2c29430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387286830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3387286830
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3232416938
Short name T707
Test name
Test status
Simulation time 43624668 ps
CPU time 1.13 seconds
Started Aug 11 06:25:36 PM PDT 24
Finished Aug 11 06:25:37 PM PDT 24
Peak memory 221028 kb
Host smart-994608e1-dfe7-4105-bba1-33f93a7f7e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232416938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3232416938
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2696046156
Short name T566
Test name
Test status
Simulation time 35451151 ps
CPU time 1.05 seconds
Started Aug 11 06:25:46 PM PDT 24
Finished Aug 11 06:25:47 PM PDT 24
Peak memory 215196 kb
Host smart-d0edd131-1d83-461d-ac84-0b91e8bb387a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696046156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2696046156
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1114932258
Short name T961
Test name
Test status
Simulation time 10820828 ps
CPU time 0.9 seconds
Started Aug 11 06:25:47 PM PDT 24
Finished Aug 11 06:25:48 PM PDT 24
Peak memory 216388 kb
Host smart-df8f045d-86c6-44b9-b230-5a877229d26d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114932258 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1114932258
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.1049107882
Short name T977
Test name
Test status
Simulation time 65850354 ps
CPU time 1.33 seconds
Started Aug 11 06:25:49 PM PDT 24
Finished Aug 11 06:25:50 PM PDT 24
Peak memory 226156 kb
Host smart-63e56aba-c906-4481-9b2f-6d0edbc3ad5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049107882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1049107882
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_intr.3870896018
Short name T29
Test name
Test status
Simulation time 21780345 ps
CPU time 1.16 seconds
Started Aug 11 06:25:40 PM PDT 24
Finished Aug 11 06:25:42 PM PDT 24
Peak memory 216004 kb
Host smart-a70be524-dce4-4d2c-b78d-77a402637b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870896018 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3870896018
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3378114715
Short name T351
Test name
Test status
Simulation time 56440019 ps
CPU time 0.96 seconds
Started Aug 11 06:25:47 PM PDT 24
Finished Aug 11 06:25:48 PM PDT 24
Peak memory 215228 kb
Host smart-b0e3a17c-226c-4a75-8d98-9a55f09fe89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378114715 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3378114715
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3561849115
Short name T773
Test name
Test status
Simulation time 317800349 ps
CPU time 2 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:41 PM PDT 24
Peak memory 217404 kb
Host smart-45c29358-3bd5-43fd-8b3b-5013100c59c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561849115 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3561849115
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.148064218
Short name T567
Test name
Test status
Simulation time 9991541405 ps
CPU time 197.22 seconds
Started Aug 11 06:25:37 PM PDT 24
Finished Aug 11 06:28:54 PM PDT 24
Peak memory 222300 kb
Host smart-92a74630-ebcd-43f0-b1ed-bfde39a8379b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148064218 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.148064218
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.4274092686
Short name T491
Test name
Test status
Simulation time 98354986 ps
CPU time 1.24 seconds
Started Aug 11 06:27:24 PM PDT 24
Finished Aug 11 06:27:25 PM PDT 24
Peak memory 218480 kb
Host smart-ce757c22-cc95-4e28-8933-88cfc3e611de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274092686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.4274092686
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/191.edn_alert.1128517968
Short name T569
Test name
Test status
Simulation time 42245826 ps
CPU time 1.14 seconds
Started Aug 11 06:27:13 PM PDT 24
Finished Aug 11 06:27:14 PM PDT 24
Peak memory 218296 kb
Host smart-18c57771-dcc9-4479-b05d-15a5ec5516d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128517968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1128517968
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.569181366
Short name T824
Test name
Test status
Simulation time 137487045 ps
CPU time 2.3 seconds
Started Aug 11 06:27:12 PM PDT 24
Finished Aug 11 06:27:14 PM PDT 24
Peak memory 219588 kb
Host smart-ed371dce-53ed-4a19-962f-d60145043b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569181366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.569181366
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.4113178153
Short name T104
Test name
Test status
Simulation time 49387525 ps
CPU time 1.19 seconds
Started Aug 11 06:27:18 PM PDT 24
Finished Aug 11 06:27:20 PM PDT 24
Peak memory 220684 kb
Host smart-33f17b6a-438f-45f0-b231-8cc583dea5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113178153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.4113178153
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.4070866175
Short name T338
Test name
Test status
Simulation time 18080086 ps
CPU time 1.1 seconds
Started Aug 11 06:27:11 PM PDT 24
Finished Aug 11 06:27:12 PM PDT 24
Peak memory 217208 kb
Host smart-ecce1dbf-07f8-45e5-8133-8678427eca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070866175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4070866175
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2819998517
Short name T407
Test name
Test status
Simulation time 77192910 ps
CPU time 1 seconds
Started Aug 11 06:27:22 PM PDT 24
Finished Aug 11 06:27:23 PM PDT 24
Peak memory 219472 kb
Host smart-02b3830f-cacf-4a74-b9ff-98183d2196ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819998517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2819998517
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.1610584683
Short name T360
Test name
Test status
Simulation time 75291820 ps
CPU time 1.19 seconds
Started Aug 11 06:27:24 PM PDT 24
Finished Aug 11 06:27:26 PM PDT 24
Peak memory 217292 kb
Host smart-dac35cbe-813a-4804-9e85-0b508ab389d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610584683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1610584683
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.1282326632
Short name T859
Test name
Test status
Simulation time 24742889 ps
CPU time 1.23 seconds
Started Aug 11 06:27:17 PM PDT 24
Finished Aug 11 06:27:18 PM PDT 24
Peak memory 219208 kb
Host smart-c7d2f7b6-647e-4994-8b9a-291af2528c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282326632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1282326632
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.378238735
Short name T861
Test name
Test status
Simulation time 33543127 ps
CPU time 1.3 seconds
Started Aug 11 06:27:16 PM PDT 24
Finished Aug 11 06:27:18 PM PDT 24
Peak memory 218544 kb
Host smart-820703c0-3a46-4466-b4b6-3d69d3dd3604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378238735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.378238735
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.3111460645
Short name T196
Test name
Test status
Simulation time 29679462 ps
CPU time 1.21 seconds
Started Aug 11 06:27:18 PM PDT 24
Finished Aug 11 06:27:19 PM PDT 24
Peak memory 219676 kb
Host smart-424a8423-f905-4eaf-9500-87a90351e225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111460645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3111460645
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.4172358566
Short name T887
Test name
Test status
Simulation time 64709019 ps
CPU time 1.52 seconds
Started Aug 11 06:27:09 PM PDT 24
Finished Aug 11 06:27:11 PM PDT 24
Peak memory 218628 kb
Host smart-c22eb3c4-ac70-4fac-a841-85eb522ea5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172358566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.4172358566
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.4283965437
Short name T175
Test name
Test status
Simulation time 40545717 ps
CPU time 1.09 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:27:40 PM PDT 24
Peak memory 218240 kb
Host smart-3f265861-8577-4d7e-8f2e-9bca4bf36b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283965437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.4283965437
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.1399869936
Short name T294
Test name
Test status
Simulation time 45086547 ps
CPU time 1.29 seconds
Started Aug 11 06:27:19 PM PDT 24
Finished Aug 11 06:27:21 PM PDT 24
Peak memory 217476 kb
Host smart-d3d05848-5902-42f3-bac9-e87a3df3a5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399869936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1399869936
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3332727332
Short name T198
Test name
Test status
Simulation time 31169873 ps
CPU time 1.15 seconds
Started Aug 11 06:27:33 PM PDT 24
Finished Aug 11 06:27:34 PM PDT 24
Peak memory 219792 kb
Host smart-10eb3919-1103-4b8e-b150-336f41614244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332727332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3332727332
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.679961484
Short name T613
Test name
Test status
Simulation time 27078884 ps
CPU time 1.22 seconds
Started Aug 11 06:27:27 PM PDT 24
Finished Aug 11 06:27:28 PM PDT 24
Peak memory 218964 kb
Host smart-07ebb0da-f09e-4ad7-b3e8-94e10a817a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679961484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.679961484
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2019658206
Short name T142
Test name
Test status
Simulation time 78307728 ps
CPU time 1.12 seconds
Started Aug 11 06:27:12 PM PDT 24
Finished Aug 11 06:27:13 PM PDT 24
Peak memory 219644 kb
Host smart-2eb09f40-eeaf-4073-b190-d6f4442ada38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019658206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2019658206
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3976522206
Short name T648
Test name
Test status
Simulation time 56204817 ps
CPU time 0.99 seconds
Started Aug 11 06:27:22 PM PDT 24
Finished Aug 11 06:27:24 PM PDT 24
Peak memory 217300 kb
Host smart-fcc94205-267c-4ee1-ac4c-0e5fcd867104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976522206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3976522206
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2459267286
Short name T101
Test name
Test status
Simulation time 154707851 ps
CPU time 1.45 seconds
Started Aug 11 06:27:14 PM PDT 24
Finished Aug 11 06:27:16 PM PDT 24
Peak memory 215524 kb
Host smart-3daf0285-e386-4315-84c6-f5b091470695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459267286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2459267286
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.577050834
Short name T482
Test name
Test status
Simulation time 52322121 ps
CPU time 1.2 seconds
Started Aug 11 06:27:27 PM PDT 24
Finished Aug 11 06:27:28 PM PDT 24
Peak memory 217592 kb
Host smart-15ab6328-5080-4d46-ac3b-24a58587b7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577050834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.577050834
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2795318264
Short name T486
Test name
Test status
Simulation time 22882303 ps
CPU time 1.2 seconds
Started Aug 11 06:25:17 PM PDT 24
Finished Aug 11 06:25:19 PM PDT 24
Peak memory 219876 kb
Host smart-af1df0a9-c149-4664-8ca3-a7f88667ef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795318264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2795318264
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.862379086
Short name T526
Test name
Test status
Simulation time 15694542 ps
CPU time 0.93 seconds
Started Aug 11 06:25:15 PM PDT 24
Finished Aug 11 06:25:16 PM PDT 24
Peak memory 215180 kb
Host smart-35f5d42e-3923-4d35-8900-0c6bac3497fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862379086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.862379086
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.293048331
Short name T478
Test name
Test status
Simulation time 15890177 ps
CPU time 0.81 seconds
Started Aug 11 06:25:14 PM PDT 24
Finished Aug 11 06:25:15 PM PDT 24
Peak memory 218280 kb
Host smart-4b5cb082-c369-46c1-b8c9-668e3326cdb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293048331 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.293048331
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3019906576
Short name T208
Test name
Test status
Simulation time 98306726 ps
CPU time 1.07 seconds
Started Aug 11 06:25:16 PM PDT 24
Finished Aug 11 06:25:17 PM PDT 24
Peak memory 219476 kb
Host smart-62311d47-abab-4d2b-aa1e-32468385389b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019906576 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3019906576
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1563211020
Short name T9
Test name
Test status
Simulation time 54904887 ps
CPU time 0.9 seconds
Started Aug 11 06:25:13 PM PDT 24
Finished Aug 11 06:25:14 PM PDT 24
Peak memory 219992 kb
Host smart-8f2aabc5-a53b-4551-81a4-bd9fcfe036e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563211020 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1563211020
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3678819808
Short name T812
Test name
Test status
Simulation time 52859536 ps
CPU time 1.58 seconds
Started Aug 11 06:25:16 PM PDT 24
Finished Aug 11 06:25:17 PM PDT 24
Peak memory 217700 kb
Host smart-f4d7d87b-3028-4d18-92e6-7032d8547eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678819808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3678819808
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.764277519
Short name T670
Test name
Test status
Simulation time 37843049 ps
CPU time 0.93 seconds
Started Aug 11 06:25:16 PM PDT 24
Finished Aug 11 06:25:17 PM PDT 24
Peak memory 215324 kb
Host smart-78d09f30-eacb-4d39-815c-44e235db7101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764277519 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.764277519
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1293014037
Short name T764
Test name
Test status
Simulation time 49433968 ps
CPU time 1.03 seconds
Started Aug 11 06:25:16 PM PDT 24
Finished Aug 11 06:25:17 PM PDT 24
Peak memory 207104 kb
Host smart-77c46b70-7cb3-4157-a4eb-8d43baf8615d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293014037 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1293014037
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3916794246
Short name T19
Test name
Test status
Simulation time 503570544 ps
CPU time 8.88 seconds
Started Aug 11 06:25:19 PM PDT 24
Finished Aug 11 06:25:28 PM PDT 24
Peak memory 242308 kb
Host smart-30b4cf98-d2bb-464f-bac4-8b129d799619
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916794246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3916794246
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3866320265
Short name T983
Test name
Test status
Simulation time 19050341 ps
CPU time 0.98 seconds
Started Aug 11 06:25:14 PM PDT 24
Finished Aug 11 06:25:15 PM PDT 24
Peak memory 215320 kb
Host smart-67281b3b-35a4-4e65-8a64-6d63a6ecd453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866320265 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3866320265
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2649917524
Short name T808
Test name
Test status
Simulation time 301041031 ps
CPU time 3.21 seconds
Started Aug 11 06:25:12 PM PDT 24
Finished Aug 11 06:25:15 PM PDT 24
Peak memory 215324 kb
Host smart-f7ef3c89-9ea7-4457-a923-938a83bd546c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649917524 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2649917524
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_alert.2593393334
Short name T94
Test name
Test status
Simulation time 102733456 ps
CPU time 1.04 seconds
Started Aug 11 06:25:45 PM PDT 24
Finished Aug 11 06:25:46 PM PDT 24
Peak memory 218760 kb
Host smart-09e8c7d0-5523-43dd-ab54-dc6019af02ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593393334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2593393334
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2785812763
Short name T349
Test name
Test status
Simulation time 136656288 ps
CPU time 1.01 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 206936 kb
Host smart-720ef5fd-1b73-4e59-b52b-0c9b9a8aa264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785812763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2785812763
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.590035753
Short name T84
Test name
Test status
Simulation time 18846076 ps
CPU time 0.91 seconds
Started Aug 11 06:25:38 PM PDT 24
Finished Aug 11 06:25:39 PM PDT 24
Peak memory 215536 kb
Host smart-fb7c6652-8d8e-4959-89db-b0c0704104ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590035753 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.590035753
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.2196644967
Short name T161
Test name
Test status
Simulation time 69499056 ps
CPU time 1.13 seconds
Started Aug 11 06:25:38 PM PDT 24
Finished Aug 11 06:25:39 PM PDT 24
Peak memory 225852 kb
Host smart-57394cf5-0892-4cba-856a-cd0c40a42e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196644967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2196644967
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1925308090
Short name T383
Test name
Test status
Simulation time 107140834 ps
CPU time 1.27 seconds
Started Aug 11 06:25:36 PM PDT 24
Finished Aug 11 06:25:37 PM PDT 24
Peak memory 219432 kb
Host smart-eec62fac-cecb-4896-910b-61cae1c45eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925308090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1925308090
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.4144777920
Short name T717
Test name
Test status
Simulation time 41175253 ps
CPU time 0.95 seconds
Started Aug 11 06:25:49 PM PDT 24
Finished Aug 11 06:25:50 PM PDT 24
Peak memory 215284 kb
Host smart-ba2dd447-de18-4b99-be91-156c759f20bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144777920 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.4144777920
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.4217784448
Short name T369
Test name
Test status
Simulation time 28093553 ps
CPU time 0.97 seconds
Started Aug 11 06:25:49 PM PDT 24
Finished Aug 11 06:25:50 PM PDT 24
Peak memory 215272 kb
Host smart-d288b594-a138-476c-a2fe-21cfd8d16f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217784448 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.4217784448
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.662108527
Short name T965
Test name
Test status
Simulation time 853444665 ps
CPU time 3.06 seconds
Started Aug 11 06:25:37 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 217484 kb
Host smart-b0b0bcab-5b2a-4bef-a850-cd14fd2c83c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662108527 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.662108527
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1819817311
Short name T461
Test name
Test status
Simulation time 43977826690 ps
CPU time 525.46 seconds
Started Aug 11 06:25:38 PM PDT 24
Finished Aug 11 06:34:23 PM PDT 24
Peak memory 217768 kb
Host smart-0f0cfd77-7b38-4ef9-a544-3aa0219541df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819817311 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1819817311
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2452384756
Short name T676
Test name
Test status
Simulation time 56181020 ps
CPU time 1.26 seconds
Started Aug 11 06:27:14 PM PDT 24
Finished Aug 11 06:27:15 PM PDT 24
Peak memory 217292 kb
Host smart-1b0bac86-ef6e-46c5-85a4-4e5d1fb84fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452384756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2452384756
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3749635455
Short name T956
Test name
Test status
Simulation time 33813964 ps
CPU time 1.29 seconds
Started Aug 11 06:27:20 PM PDT 24
Finished Aug 11 06:27:22 PM PDT 24
Peak memory 218944 kb
Host smart-8874ab0f-23ae-403d-a043-e22dda0881f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749635455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3749635455
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2473107459
Short name T463
Test name
Test status
Simulation time 39209554 ps
CPU time 1.16 seconds
Started Aug 11 06:27:26 PM PDT 24
Finished Aug 11 06:27:27 PM PDT 24
Peak memory 218752 kb
Host smart-93f42651-0da7-4a41-a10c-d7e14c154434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473107459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2473107459
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1924593822
Short name T628
Test name
Test status
Simulation time 27872831 ps
CPU time 1.45 seconds
Started Aug 11 06:27:14 PM PDT 24
Finished Aug 11 06:27:15 PM PDT 24
Peak memory 217644 kb
Host smart-7f4119b6-667f-427e-87ab-ad4ceadaf83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924593822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1924593822
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.205077509
Short name T515
Test name
Test status
Simulation time 102865003 ps
CPU time 1.03 seconds
Started Aug 11 06:27:28 PM PDT 24
Finished Aug 11 06:27:29 PM PDT 24
Peak memory 217368 kb
Host smart-e8093140-518e-4e41-a27a-d3397bf8fa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205077509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.205077509
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3998039826
Short name T862
Test name
Test status
Simulation time 275965916 ps
CPU time 3.61 seconds
Started Aug 11 06:27:17 PM PDT 24
Finished Aug 11 06:27:21 PM PDT 24
Peak memory 220152 kb
Host smart-ef000db3-4f9f-4d67-9c59-a2076e66fbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998039826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3998039826
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2644100274
Short name T881
Test name
Test status
Simulation time 70513011 ps
CPU time 2.58 seconds
Started Aug 11 06:27:29 PM PDT 24
Finished Aug 11 06:27:31 PM PDT 24
Peak memory 218744 kb
Host smart-95be8111-ef2d-43e7-849a-0d02679e0220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644100274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2644100274
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3755212320
Short name T307
Test name
Test status
Simulation time 39770015 ps
CPU time 1.44 seconds
Started Aug 11 06:27:20 PM PDT 24
Finished Aug 11 06:27:21 PM PDT 24
Peak memory 217520 kb
Host smart-26f25669-a18c-4998-93d7-c8acab0e7155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755212320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3755212320
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4122091770
Short name T282
Test name
Test status
Simulation time 85832238 ps
CPU time 1.07 seconds
Started Aug 11 06:27:17 PM PDT 24
Finished Aug 11 06:27:19 PM PDT 24
Peak memory 217184 kb
Host smart-5e9cb32f-d79a-4c5a-ba8a-acdf4be7596b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122091770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4122091770
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1175116802
Short name T326
Test name
Test status
Simulation time 48926386 ps
CPU time 1.67 seconds
Started Aug 11 06:27:08 PM PDT 24
Finished Aug 11 06:27:10 PM PDT 24
Peak memory 219812 kb
Host smart-58ee4d13-1895-4c9f-983e-ef3016884775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175116802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1175116802
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2442069409
Short name T848
Test name
Test status
Simulation time 84410008 ps
CPU time 1.06 seconds
Started Aug 11 06:25:46 PM PDT 24
Finished Aug 11 06:25:47 PM PDT 24
Peak memory 218644 kb
Host smart-cdc58850-b07f-40aa-9b5f-4106144f167e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442069409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2442069409
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.113753862
Short name T873
Test name
Test status
Simulation time 20196030 ps
CPU time 0.87 seconds
Started Aug 11 06:25:46 PM PDT 24
Finished Aug 11 06:25:47 PM PDT 24
Peak memory 206752 kb
Host smart-07d8ad0e-6198-495b-ac4f-fa61c63cf1b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113753862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.113753862
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.968478616
Short name T975
Test name
Test status
Simulation time 35950276 ps
CPU time 0.84 seconds
Started Aug 11 06:25:37 PM PDT 24
Finished Aug 11 06:25:38 PM PDT 24
Peak memory 215336 kb
Host smart-1a3be28d-b863-46a9-89ac-76ec6092f9ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968478616 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.968478616
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1368126042
Short name T997
Test name
Test status
Simulation time 26108738 ps
CPU time 1.19 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:41 PM PDT 24
Peak memory 219692 kb
Host smart-a9f5dd62-8c9e-42ee-8caf-0f711b989923
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368126042 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1368126042
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3401104124
Short name T178
Test name
Test status
Simulation time 24390978 ps
CPU time 1.07 seconds
Started Aug 11 06:25:37 PM PDT 24
Finished Aug 11 06:25:38 PM PDT 24
Peak memory 224176 kb
Host smart-0af8c19b-f353-4599-b89d-c07b5a682a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401104124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3401104124
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1434902642
Short name T734
Test name
Test status
Simulation time 95178303 ps
CPU time 3.09 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:42 PM PDT 24
Peak memory 215448 kb
Host smart-10312777-9d79-4fb3-8022-ac02ca126e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434902642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1434902642
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3697713325
Short name T5
Test name
Test status
Simulation time 20779506 ps
CPU time 1.11 seconds
Started Aug 11 06:25:38 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 216076 kb
Host smart-19111abe-e651-4ed2-bac0-f96e90b690bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697713325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3697713325
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2319265922
Short name T636
Test name
Test status
Simulation time 46490336 ps
CPU time 0.97 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 215264 kb
Host smart-3684d66d-7a38-4d9d-a488-fca229cb00df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319265922 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2319265922
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1156079047
Short name T964
Test name
Test status
Simulation time 123606016 ps
CPU time 2.65 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:42 PM PDT 24
Peak memory 215304 kb
Host smart-8d0077dd-bb8b-42d9-ab9d-6ed61fb4f6be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156079047 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1156079047
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3416999887
Short name T752
Test name
Test status
Simulation time 45100050376 ps
CPU time 599.34 seconds
Started Aug 11 06:25:38 PM PDT 24
Finished Aug 11 06:35:37 PM PDT 24
Peak memory 218296 kb
Host smart-bdf463cc-ff1d-4c4d-8178-1048c5d0a269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416999887 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3416999887
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1381197942
Short name T432
Test name
Test status
Simulation time 70135709 ps
CPU time 1.08 seconds
Started Aug 11 06:27:18 PM PDT 24
Finished Aug 11 06:27:20 PM PDT 24
Peak memory 215352 kb
Host smart-6d623e16-dc59-49d1-974c-115ca9b6251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381197942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1381197942
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1496516283
Short name T281
Test name
Test status
Simulation time 101621001 ps
CPU time 1.04 seconds
Started Aug 11 06:27:25 PM PDT 24
Finished Aug 11 06:27:26 PM PDT 24
Peak memory 217380 kb
Host smart-d429a6a9-ccea-4452-b700-1f2ad934a827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496516283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1496516283
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.962621001
Short name T955
Test name
Test status
Simulation time 92694655 ps
CPU time 1.43 seconds
Started Aug 11 06:27:31 PM PDT 24
Finished Aug 11 06:27:33 PM PDT 24
Peak memory 218972 kb
Host smart-2bc2c265-973d-4bec-b785-c1b2156b48b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962621001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.962621001
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3020722501
Short name T967
Test name
Test status
Simulation time 44358428 ps
CPU time 1.33 seconds
Started Aug 11 06:27:21 PM PDT 24
Finished Aug 11 06:27:22 PM PDT 24
Peak memory 219820 kb
Host smart-a555a96b-f917-42c0-9ed7-ce19a67431c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020722501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3020722501
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2032505678
Short name T301
Test name
Test status
Simulation time 65982956 ps
CPU time 1.73 seconds
Started Aug 11 06:27:18 PM PDT 24
Finished Aug 11 06:27:20 PM PDT 24
Peak memory 218740 kb
Host smart-64f4963e-6458-4078-8521-43e7c4264b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032505678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2032505678
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.227299908
Short name T537
Test name
Test status
Simulation time 266461074 ps
CPU time 1.64 seconds
Started Aug 11 06:27:24 PM PDT 24
Finished Aug 11 06:27:26 PM PDT 24
Peak memory 218824 kb
Host smart-ec753c5d-cdb0-4f0e-9b71-cc4bedd28b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227299908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.227299908
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.4170315632
Short name T642
Test name
Test status
Simulation time 54799110 ps
CPU time 1.19 seconds
Started Aug 11 06:27:09 PM PDT 24
Finished Aug 11 06:27:11 PM PDT 24
Peak memory 217388 kb
Host smart-6d10936a-8597-4bcd-9915-e902f2a2fd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170315632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.4170315632
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2819254893
Short name T521
Test name
Test status
Simulation time 38986106 ps
CPU time 1.26 seconds
Started Aug 11 06:27:31 PM PDT 24
Finished Aug 11 06:27:33 PM PDT 24
Peak memory 218548 kb
Host smart-fb081f98-1b48-488f-ba88-6def5101ae43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819254893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2819254893
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.909622886
Short name T508
Test name
Test status
Simulation time 167838349 ps
CPU time 1.17 seconds
Started Aug 11 06:27:26 PM PDT 24
Finished Aug 11 06:27:27 PM PDT 24
Peak memory 217244 kb
Host smart-58ce70fb-e7f7-4fa5-915e-a61029627225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909622886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.909622886
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1114409120
Short name T437
Test name
Test status
Simulation time 186155834 ps
CPU time 1.56 seconds
Started Aug 11 06:27:23 PM PDT 24
Finished Aug 11 06:27:25 PM PDT 24
Peak memory 218768 kb
Host smart-41fa0ba6-20be-49b6-9a4c-ef6cb816ca3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114409120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1114409120
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1992718898
Short name T570
Test name
Test status
Simulation time 25664943 ps
CPU time 1.22 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 219112 kb
Host smart-cdf1b8d0-adc0-4ecd-89cf-a44f4e5f0ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992718898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1992718898
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2346586652
Short name T846
Test name
Test status
Simulation time 13349673 ps
CPU time 0.89 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 207016 kb
Host smart-75274161-ea09-45d4-981f-ee7eedfd01b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346586652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2346586652
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.208125391
Short name T860
Test name
Test status
Simulation time 16568333 ps
CPU time 0.81 seconds
Started Aug 11 06:25:44 PM PDT 24
Finished Aug 11 06:25:45 PM PDT 24
Peak memory 219108 kb
Host smart-aa0ee106-e40e-40b5-a9cb-ddb0e9448ca5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208125391 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.208125391
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2461101748
Short name T608
Test name
Test status
Simulation time 33153689 ps
CPU time 1.24 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 217200 kb
Host smart-a6f810cf-00b6-4338-9597-aaf7a20b4b09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461101748 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2461101748
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.4245085433
Short name T144
Test name
Test status
Simulation time 32330130 ps
CPU time 1.03 seconds
Started Aug 11 06:25:42 PM PDT 24
Finished Aug 11 06:25:43 PM PDT 24
Peak memory 218612 kb
Host smart-f3ee1f26-f988-4957-b2b5-bd9dc8aeedce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245085433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.4245085433
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.303642173
Short name T867
Test name
Test status
Simulation time 38042314 ps
CPU time 1.51 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 215320 kb
Host smart-ae4fb38a-3cfa-4cc2-83f7-5396cbf580fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303642173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.303642173
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.993342103
Short name T585
Test name
Test status
Simulation time 41040536 ps
CPU time 1.03 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 224176 kb
Host smart-b66a65f0-3a57-434a-b848-7afc60eb7ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993342103 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.993342103
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1555266040
Short name T389
Test name
Test status
Simulation time 14460906 ps
CPU time 0.98 seconds
Started Aug 11 06:25:49 PM PDT 24
Finished Aug 11 06:25:50 PM PDT 24
Peak memory 215196 kb
Host smart-d1d27d3a-0b54-43c5-b98f-7b9fe87187a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555266040 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1555266040
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.268363596
Short name T968
Test name
Test status
Simulation time 48665604 ps
CPU time 1.52 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 207164 kb
Host smart-160fc382-a5fb-44ca-818f-f443099f8a97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268363596 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.268363596
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2457951728
Short name T607
Test name
Test status
Simulation time 83171010041 ps
CPU time 1889.09 seconds
Started Aug 11 06:25:38 PM PDT 24
Finished Aug 11 06:57:08 PM PDT 24
Peak memory 226420 kb
Host smart-410a97f3-e449-43a3-bc5d-ab7d558f82ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457951728 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2457951728
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2877478765
Short name T558
Test name
Test status
Simulation time 67571688 ps
CPU time 2.71 seconds
Started Aug 11 06:27:20 PM PDT 24
Finished Aug 11 06:27:23 PM PDT 24
Peak memory 220264 kb
Host smart-d2a731ad-f10b-498e-bbf4-28fbc7dd3837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877478765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2877478765
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1664516462
Short name T732
Test name
Test status
Simulation time 110711571 ps
CPU time 1.68 seconds
Started Aug 11 06:27:12 PM PDT 24
Finished Aug 11 06:27:19 PM PDT 24
Peak memory 218940 kb
Host smart-9aae4e74-32d9-49c7-8e21-0abae0587967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664516462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1664516462
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3770603058
Short name T297
Test name
Test status
Simulation time 64704716 ps
CPU time 2.4 seconds
Started Aug 11 06:27:30 PM PDT 24
Finished Aug 11 06:27:32 PM PDT 24
Peak memory 220144 kb
Host smart-1fe1fe2a-21ae-4bd1-b187-733cc74812c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770603058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3770603058
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1156432921
Short name T912
Test name
Test status
Simulation time 156084780 ps
CPU time 2.27 seconds
Started Aug 11 06:27:20 PM PDT 24
Finished Aug 11 06:27:23 PM PDT 24
Peak memory 219980 kb
Host smart-416e3b5c-b686-45cf-9fa1-1f5f63cbd7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156432921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1156432921
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4026098693
Short name T843
Test name
Test status
Simulation time 38836804 ps
CPU time 1.2 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 217340 kb
Host smart-dfc31e50-ce19-4f56-a797-3fd8228c02eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026098693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4026098693
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.938994
Short name T392
Test name
Test status
Simulation time 48928218 ps
CPU time 1.58 seconds
Started Aug 11 06:27:21 PM PDT 24
Finished Aug 11 06:27:23 PM PDT 24
Peak memory 218776 kb
Host smart-df8caf1d-5351-41a2-9835-5e0f5cfdd914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.938994
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2995858573
Short name T660
Test name
Test status
Simulation time 292349467 ps
CPU time 1.04 seconds
Started Aug 11 06:27:13 PM PDT 24
Finished Aug 11 06:27:14 PM PDT 24
Peak memory 217436 kb
Host smart-ad0e7c66-e52f-4eda-ac58-7426018f12a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995858573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2995858573
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2633319570
Short name T242
Test name
Test status
Simulation time 53901305 ps
CPU time 1.67 seconds
Started Aug 11 06:27:28 PM PDT 24
Finished Aug 11 06:27:29 PM PDT 24
Peak memory 218804 kb
Host smart-c198c0e4-789e-479e-8bac-ed78f3c156f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633319570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2633319570
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3192296005
Short name T865
Test name
Test status
Simulation time 88451784 ps
CPU time 1.24 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 218544 kb
Host smart-162842e9-8b5e-461f-821e-fe1e6f2724e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192296005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3192296005
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.4073679753
Short name T611
Test name
Test status
Simulation time 41066862 ps
CPU time 1.58 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 218636 kb
Host smart-253e4573-b062-4116-9450-1be7e067e94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073679753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.4073679753
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3875376057
Short name T146
Test name
Test status
Simulation time 27398014 ps
CPU time 1.25 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 220728 kb
Host smart-518de132-1312-4f39-965d-faf5eb472cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875376057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3875376057
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1887914417
Short name T742
Test name
Test status
Simulation time 115359975 ps
CPU time 0.91 seconds
Started Aug 11 06:25:42 PM PDT 24
Finished Aug 11 06:25:43 PM PDT 24
Peak memory 215144 kb
Host smart-9cd13534-4860-4fdb-b821-20a3c322e50b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887914417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1887914417
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2907739725
Short name T166
Test name
Test status
Simulation time 14790584 ps
CPU time 0.96 seconds
Started Aug 11 06:25:42 PM PDT 24
Finished Aug 11 06:25:43 PM PDT 24
Peak memory 215696 kb
Host smart-e7435818-d52d-41d4-88c6-4ec211b13d93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907739725 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2907739725
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1188732704
Short name T516
Test name
Test status
Simulation time 34454330 ps
CPU time 1.16 seconds
Started Aug 11 06:25:39 PM PDT 24
Finished Aug 11 06:25:40 PM PDT 24
Peak memory 219676 kb
Host smart-8ad982c5-f04f-449d-8393-33091d0c8179
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188732704 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1188732704
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1133689888
Short name T143
Test name
Test status
Simulation time 165801923 ps
CPU time 1.06 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 232500 kb
Host smart-2990fe4e-ce56-43d7-8192-27180b785dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133689888 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1133689888
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1735156433
Short name T693
Test name
Test status
Simulation time 43093500 ps
CPU time 1.29 seconds
Started Aug 11 06:25:47 PM PDT 24
Finished Aug 11 06:25:49 PM PDT 24
Peak memory 217268 kb
Host smart-07ffe4f2-fd9f-4184-8f31-3700318c28d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735156433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1735156433
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2487673873
Short name T686
Test name
Test status
Simulation time 26780582 ps
CPU time 0.96 seconds
Started Aug 11 06:25:53 PM PDT 24
Finished Aug 11 06:25:54 PM PDT 24
Peak memory 215096 kb
Host smart-6fe3ccbb-4092-4e31-81d2-57760f4fe232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487673873 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2487673873
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.4039390539
Short name T485
Test name
Test status
Simulation time 47941461 ps
CPU time 0.92 seconds
Started Aug 11 06:25:53 PM PDT 24
Finished Aug 11 06:25:54 PM PDT 24
Peak memory 215108 kb
Host smart-4c09c265-2dc8-4d2b-b5d4-3d135350bc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039390539 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.4039390539
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1447955818
Short name T829
Test name
Test status
Simulation time 1482723895 ps
CPU time 4.58 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:55 PM PDT 24
Peak memory 215304 kb
Host smart-7a13e2db-d588-470f-a249-7893d07450c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447955818 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1447955818
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1538574289
Short name T102
Test name
Test status
Simulation time 33123573159 ps
CPU time 822.75 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:39:34 PM PDT 24
Peak memory 223612 kb
Host smart-d204709c-54ea-43bd-8812-dd69a2f74a36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538574289 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1538574289
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3925668346
Short name T455
Test name
Test status
Simulation time 21382436 ps
CPU time 1.19 seconds
Started Aug 11 06:27:33 PM PDT 24
Finished Aug 11 06:27:40 PM PDT 24
Peak memory 220012 kb
Host smart-5a87a844-9c3b-4777-b5ee-0a9a6c257c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925668346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3925668346
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.4266871806
Short name T413
Test name
Test status
Simulation time 230781711 ps
CPU time 1.17 seconds
Started Aug 11 06:27:24 PM PDT 24
Finished Aug 11 06:27:26 PM PDT 24
Peak memory 217432 kb
Host smart-07624250-673f-4b2b-9b69-e0eb1ec5789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266871806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.4266871806
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3538629560
Short name T419
Test name
Test status
Simulation time 46773992 ps
CPU time 1.11 seconds
Started Aug 11 06:27:33 PM PDT 24
Finished Aug 11 06:27:34 PM PDT 24
Peak memory 218740 kb
Host smart-f241dd23-e452-49b5-8fb3-ca44c53c21d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538629560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3538629560
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1808815128
Short name T548
Test name
Test status
Simulation time 160124455 ps
CPU time 1.18 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:27:36 PM PDT 24
Peak memory 217272 kb
Host smart-593914c8-0811-4bd9-8001-4938567ba6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808815128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1808815128
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1448216055
Short name T871
Test name
Test status
Simulation time 47036030 ps
CPU time 1.76 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:27:36 PM PDT 24
Peak memory 218624 kb
Host smart-4983632b-a270-4524-bca4-9b9a9f24bba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448216055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1448216055
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2127938026
Short name T946
Test name
Test status
Simulation time 35641662 ps
CPU time 1.46 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:27:38 PM PDT 24
Peak memory 220024 kb
Host smart-581e7c86-62f6-4ee0-84b6-1123512cada9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127938026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2127938026
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2758861785
Short name T14
Test name
Test status
Simulation time 118760377 ps
CPU time 1.22 seconds
Started Aug 11 06:27:32 PM PDT 24
Finished Aug 11 06:27:34 PM PDT 24
Peak memory 220304 kb
Host smart-621b2c28-21a3-492b-8ac4-3bbc9630199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758861785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2758861785
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2039700958
Short name T544
Test name
Test status
Simulation time 50654328 ps
CPU time 1.25 seconds
Started Aug 11 06:27:27 PM PDT 24
Finished Aug 11 06:27:29 PM PDT 24
Peak memory 217152 kb
Host smart-513484a9-4901-42b1-887e-6c7dadf266a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039700958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2039700958
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2983335435
Short name T780
Test name
Test status
Simulation time 61259470 ps
CPU time 1.04 seconds
Started Aug 11 06:27:28 PM PDT 24
Finished Aug 11 06:27:29 PM PDT 24
Peak memory 218796 kb
Host smart-5e7d1173-9e1c-4d54-aefa-817ec8db6e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983335435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2983335435
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3936788063
Short name T79
Test name
Test status
Simulation time 80263424 ps
CPU time 1.56 seconds
Started Aug 11 06:27:29 PM PDT 24
Finished Aug 11 06:27:31 PM PDT 24
Peak memory 219776 kb
Host smart-8764e396-745f-4e8d-82c5-9cfd6a21e2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936788063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3936788063
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2016666771
Short name T768
Test name
Test status
Simulation time 27196708 ps
CPU time 1.35 seconds
Started Aug 11 06:25:52 PM PDT 24
Finished Aug 11 06:25:54 PM PDT 24
Peak memory 219544 kb
Host smart-bb861749-2d95-4cc1-9d97-d169f1c6cd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016666771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2016666771
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.4040472999
Short name T519
Test name
Test status
Simulation time 26020887 ps
CPU time 1.05 seconds
Started Aug 11 06:25:48 PM PDT 24
Finished Aug 11 06:25:50 PM PDT 24
Peak memory 206804 kb
Host smart-0d6ad2e8-80bf-483c-a369-dbadc69443c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040472999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4040472999
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1582368724
Short name T828
Test name
Test status
Simulation time 20087284 ps
CPU time 0.9 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 216508 kb
Host smart-8bbef0fe-e2ca-43a3-88d6-27b4c01f449b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582368724 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1582368724
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.498964389
Short name T924
Test name
Test status
Simulation time 183930758 ps
CPU time 1.06 seconds
Started Aug 11 06:25:44 PM PDT 24
Finished Aug 11 06:25:45 PM PDT 24
Peak memory 217112 kb
Host smart-d167b8f8-cce8-4a98-b581-748737f6bdb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498964389 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.498964389
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2391749698
Short name T638
Test name
Test status
Simulation time 19842691 ps
CPU time 1.13 seconds
Started Aug 11 06:25:48 PM PDT 24
Finished Aug 11 06:25:49 PM PDT 24
Peak memory 224284 kb
Host smart-eebd6960-4f46-4efe-91d4-a76f412f7cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391749698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2391749698
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.4153677700
Short name T733
Test name
Test status
Simulation time 38247461 ps
CPU time 1.28 seconds
Started Aug 11 06:25:47 PM PDT 24
Finished Aug 11 06:25:49 PM PDT 24
Peak memory 218384 kb
Host smart-af5a1eab-1774-4f9f-9945-f3f615ba3228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153677700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.4153677700
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.544718202
Short name T92
Test name
Test status
Simulation time 26420008 ps
CPU time 0.97 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 215872 kb
Host smart-ade9c937-2cc4-4b9a-bde3-a5ed878a1553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544718202 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.544718202
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1502876506
Short name T794
Test name
Test status
Simulation time 46906881 ps
CPU time 0.91 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 215272 kb
Host smart-64f6463e-2a37-43f9-9f41-71c13194aa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502876506 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1502876506
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2403504526
Short name T604
Test name
Test status
Simulation time 60496033 ps
CPU time 1.25 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 206732 kb
Host smart-53a7e423-a474-4cbf-b384-1caf77644087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403504526 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2403504526
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1064941742
Short name T753
Test name
Test status
Simulation time 71111621541 ps
CPU time 813.87 seconds
Started Aug 11 06:25:52 PM PDT 24
Finished Aug 11 06:39:26 PM PDT 24
Peak memory 223572 kb
Host smart-4266fe91-ada5-42d9-ad10-9a9c25968ee5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064941742 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1064941742
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1132788789
Short name T643
Test name
Test status
Simulation time 126860926 ps
CPU time 1.41 seconds
Started Aug 11 06:27:27 PM PDT 24
Finished Aug 11 06:27:28 PM PDT 24
Peak memory 218780 kb
Host smart-2320eb66-ea55-4c37-bb7f-4e0ffafea2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132788789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1132788789
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1746552865
Short name T464
Test name
Test status
Simulation time 34120931 ps
CPU time 1.41 seconds
Started Aug 11 06:27:28 PM PDT 24
Finished Aug 11 06:27:30 PM PDT 24
Peak memory 217444 kb
Host smart-d34dc9d6-d9b1-4d43-b560-66df42d8cb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746552865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1746552865
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1926388842
Short name T358
Test name
Test status
Simulation time 71276888 ps
CPU time 1.37 seconds
Started Aug 11 06:27:24 PM PDT 24
Finished Aug 11 06:27:25 PM PDT 24
Peak memory 217272 kb
Host smart-82434ac1-9a8d-4e8b-ba8e-381c120b7466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926388842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1926388842
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2745818574
Short name T460
Test name
Test status
Simulation time 67501301 ps
CPU time 1.12 seconds
Started Aug 11 06:27:31 PM PDT 24
Finished Aug 11 06:27:32 PM PDT 24
Peak memory 217412 kb
Host smart-28f5e339-1eee-40e4-bf21-34a7223add7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745818574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2745818574
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2306152555
Short name T73
Test name
Test status
Simulation time 39146305 ps
CPU time 1.53 seconds
Started Aug 11 06:27:30 PM PDT 24
Finished Aug 11 06:27:32 PM PDT 24
Peak memory 218580 kb
Host smart-a89b42df-7e28-4c07-bcfe-6af243e10e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306152555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2306152555
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2658530247
Short name T532
Test name
Test status
Simulation time 221362644 ps
CPU time 2.8 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:27:40 PM PDT 24
Peak memory 219936 kb
Host smart-9191d88c-6e24-4bdf-859a-14ff58f32521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658530247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2658530247
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1965551814
Short name T922
Test name
Test status
Simulation time 60107973 ps
CPU time 1.94 seconds
Started Aug 11 06:27:32 PM PDT 24
Finished Aug 11 06:27:35 PM PDT 24
Peak memory 218940 kb
Host smart-fdba9732-32b6-4421-91cd-2b85bbb6c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965551814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1965551814
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1955803088
Short name T243
Test name
Test status
Simulation time 121089417 ps
CPU time 1.27 seconds
Started Aug 11 06:27:26 PM PDT 24
Finished Aug 11 06:27:27 PM PDT 24
Peak memory 215364 kb
Host smart-f5c22a3e-b127-4626-9832-c1ed6d1b46e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955803088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1955803088
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.19144296
Short name T935
Test name
Test status
Simulation time 92745359 ps
CPU time 1.28 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 217744 kb
Host smart-efd7d9f7-32e4-4428-9e30-9c1f0724f08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19144296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.19144296
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.630584966
Short name T864
Test name
Test status
Simulation time 61829574 ps
CPU time 1.07 seconds
Started Aug 11 06:25:45 PM PDT 24
Finished Aug 11 06:25:46 PM PDT 24
Peak memory 218576 kb
Host smart-b25b7c02-81cc-4c5e-afd5-91fda43df198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630584966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.630584966
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.114134392
Short name T504
Test name
Test status
Simulation time 44497109 ps
CPU time 0.85 seconds
Started Aug 11 06:25:49 PM PDT 24
Finished Aug 11 06:25:50 PM PDT 24
Peak memory 215008 kb
Host smart-da0af96a-ac9e-443f-b534-cbd42c44a042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114134392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.114134392
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2347874098
Short name T220
Test name
Test status
Simulation time 28106633 ps
CPU time 0.83 seconds
Started Aug 11 06:25:44 PM PDT 24
Finished Aug 11 06:25:44 PM PDT 24
Peak memory 216492 kb
Host smart-261a56c6-e1fe-4ad9-8b8d-0ceeddf03cf0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347874098 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2347874098
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3368788545
Short name T149
Test name
Test status
Simulation time 29453884 ps
CPU time 1.1 seconds
Started Aug 11 06:25:44 PM PDT 24
Finished Aug 11 06:25:45 PM PDT 24
Peak memory 217064 kb
Host smart-c0d46456-fcb6-4e02-82a7-d9e61a722843
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368788545 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3368788545
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1359566092
Short name T213
Test name
Test status
Simulation time 25549776 ps
CPU time 1.02 seconds
Started Aug 11 06:25:53 PM PDT 24
Finished Aug 11 06:25:54 PM PDT 24
Peak memory 220036 kb
Host smart-3af44968-7e7e-4816-b653-c895ccc2e3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359566092 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1359566092
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.865357660
Short name T889
Test name
Test status
Simulation time 86585166 ps
CPU time 1.64 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 219180 kb
Host smart-6f2bf505-1d12-4649-b85b-974c37569054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865357660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.865357660
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3576815723
Short name T462
Test name
Test status
Simulation time 30744281 ps
CPU time 0.9 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 215272 kb
Host smart-c20718fc-542a-4492-b56e-1cad972b3cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576815723 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3576815723
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.574358749
Short name T372
Test name
Test status
Simulation time 45392948 ps
CPU time 0.98 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 207120 kb
Host smart-c8e82d69-bd1c-424b-9eeb-0bf780ae4148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574358749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.574358749
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.86556921
Short name T665
Test name
Test status
Simulation time 914260997 ps
CPU time 5.04 seconds
Started Aug 11 06:25:56 PM PDT 24
Finished Aug 11 06:26:01 PM PDT 24
Peak memory 215308 kb
Host smart-428ef860-6426-48f8-9ff5-e17a83d5f6e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86556921 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.86556921
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.998702453
Short name T229
Test name
Test status
Simulation time 26320308215 ps
CPU time 595.63 seconds
Started Aug 11 06:25:48 PM PDT 24
Finished Aug 11 06:35:44 PM PDT 24
Peak memory 218664 kb
Host smart-59f18521-e0b1-40eb-8bfa-0ef6c7612b67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998702453 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.998702453
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2024549937
Short name T72
Test name
Test status
Simulation time 60385559 ps
CPU time 1.1 seconds
Started Aug 11 06:27:24 PM PDT 24
Finished Aug 11 06:27:25 PM PDT 24
Peak memory 217376 kb
Host smart-24c3e5ed-7f9d-452a-b9d8-371e28859459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024549937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2024549937
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2474650394
Short name T790
Test name
Test status
Simulation time 120430188 ps
CPU time 1.42 seconds
Started Aug 11 06:27:25 PM PDT 24
Finished Aug 11 06:27:27 PM PDT 24
Peak memory 218780 kb
Host smart-83e62f3c-511d-48b5-a8a7-bbbceb2eb8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474650394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2474650394
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2741686624
Short name T483
Test name
Test status
Simulation time 46990387 ps
CPU time 1.61 seconds
Started Aug 11 06:27:28 PM PDT 24
Finished Aug 11 06:27:30 PM PDT 24
Peak memory 217328 kb
Host smart-79fe323d-5a56-45f9-8ee7-d1eb0abfb744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741686624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2741686624
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3406706027
Short name T339
Test name
Test status
Simulation time 58545736 ps
CPU time 1.09 seconds
Started Aug 11 06:27:32 PM PDT 24
Finished Aug 11 06:27:34 PM PDT 24
Peak memory 219868 kb
Host smart-7442aaf6-4163-4594-80de-9c4c93959415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406706027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3406706027
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1159357469
Short name T25
Test name
Test status
Simulation time 70926717 ps
CPU time 1.14 seconds
Started Aug 11 06:27:28 PM PDT 24
Finished Aug 11 06:27:29 PM PDT 24
Peak memory 218576 kb
Host smart-85319a02-cd96-4ea7-bc1c-6761a6b2b117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159357469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1159357469
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.96964817
Short name T377
Test name
Test status
Simulation time 147136038 ps
CPU time 1.26 seconds
Started Aug 11 06:27:23 PM PDT 24
Finished Aug 11 06:27:25 PM PDT 24
Peak memory 220052 kb
Host smart-ee91ea7b-f9bb-473d-bf78-699b7e3e45f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96964817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.96964817
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.4274752749
Short name T45
Test name
Test status
Simulation time 136620493 ps
CPU time 1.61 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:27:40 PM PDT 24
Peak memory 218868 kb
Host smart-1bf33453-2408-43ac-9e9c-2fe62bf83c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274752749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.4274752749
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3103976352
Short name T378
Test name
Test status
Simulation time 84266909 ps
CPU time 1.24 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:27:39 PM PDT 24
Peak memory 218968 kb
Host smart-f3865a88-631e-4c0f-8ebc-4ee7f74893c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103976352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3103976352
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1164863333
Short name T429
Test name
Test status
Simulation time 30988988 ps
CPU time 1.34 seconds
Started Aug 11 06:27:28 PM PDT 24
Finished Aug 11 06:27:29 PM PDT 24
Peak memory 219308 kb
Host smart-7e4f2819-2215-4dab-a6f0-9142d8fb3068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164863333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1164863333
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3592911136
Short name T721
Test name
Test status
Simulation time 206324142 ps
CPU time 1.42 seconds
Started Aug 11 06:27:26 PM PDT 24
Finished Aug 11 06:27:28 PM PDT 24
Peak memory 218876 kb
Host smart-435b3029-26b7-4733-b164-7d0ff4098f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592911136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3592911136
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2712616039
Short name T981
Test name
Test status
Simulation time 29390956 ps
CPU time 1.28 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:51 PM PDT 24
Peak memory 219620 kb
Host smart-2a188879-b5de-4419-a6bb-cc2984ace356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712616039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2712616039
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.870681839
Short name T947
Test name
Test status
Simulation time 92047335 ps
CPU time 0.85 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 214960 kb
Host smart-41552e9b-4c35-48e5-9873-de4364d73859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870681839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.870681839
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.643344068
Short name T577
Test name
Test status
Simulation time 29459264 ps
CPU time 1.08 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 219660 kb
Host smart-e2572101-1c47-49f0-8d3e-da6564b97e1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643344068 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.643344068
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2393497239
Short name T7
Test name
Test status
Simulation time 23681615 ps
CPU time 1.15 seconds
Started Aug 11 06:25:53 PM PDT 24
Finished Aug 11 06:25:54 PM PDT 24
Peak memory 219008 kb
Host smart-05a9779b-6eec-4cf1-aef4-a2d5d9dca2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393497239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2393497239
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.260943766
Short name T300
Test name
Test status
Simulation time 97529431 ps
CPU time 1.44 seconds
Started Aug 11 06:25:56 PM PDT 24
Finished Aug 11 06:25:58 PM PDT 24
Peak memory 218776 kb
Host smart-d554271d-9144-41d8-ae32-e861aedda076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260943766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.260943766
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1461709598
Short name T113
Test name
Test status
Simulation time 22057320 ps
CPU time 1.11 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 215980 kb
Host smart-aa13a94d-bf03-411a-9c5c-fa372409fc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461709598 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1461709598
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2630990665
Short name T586
Test name
Test status
Simulation time 14664599 ps
CPU time 0.99 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 215320 kb
Host smart-64754f48-7b0b-480d-9125-13de189aa973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630990665 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2630990665
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1840365948
Short name T96
Test name
Test status
Simulation time 465962529 ps
CPU time 5.16 seconds
Started Aug 11 06:25:57 PM PDT 24
Finished Aug 11 06:26:02 PM PDT 24
Peak memory 217384 kb
Host smart-7dd519df-0be4-4534-904c-9b1c08b23d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840365948 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1840365948
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.553116890
Short name T644
Test name
Test status
Simulation time 51076910050 ps
CPU time 285.98 seconds
Started Aug 11 06:25:48 PM PDT 24
Finished Aug 11 06:30:34 PM PDT 24
Peak memory 217980 kb
Host smart-7f1cd43a-3d50-4832-8295-0de60dda920b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553116890 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.553116890
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1852842348
Short name T685
Test name
Test status
Simulation time 78238335 ps
CPU time 1.86 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:27:39 PM PDT 24
Peak memory 220188 kb
Host smart-3c9aac36-581b-4124-9f22-fe0215cb0df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852842348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1852842348
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3773125704
Short name T818
Test name
Test status
Simulation time 82868035 ps
CPU time 2.82 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:27:40 PM PDT 24
Peak memory 218916 kb
Host smart-376ddeb6-9a21-47fc-a389-fd9a452dc1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773125704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3773125704
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1575888027
Short name T82
Test name
Test status
Simulation time 74875208 ps
CPU time 1.16 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:27:36 PM PDT 24
Peak memory 218424 kb
Host smart-c21b8008-0f6e-4004-b6a7-c2639dc5e807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575888027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1575888027
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1603994763
Short name T681
Test name
Test status
Simulation time 146439215 ps
CPU time 1.66 seconds
Started Aug 11 06:27:29 PM PDT 24
Finished Aug 11 06:27:31 PM PDT 24
Peak memory 218672 kb
Host smart-ec1f797d-f70c-4a77-b70e-a585400f9d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603994763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1603994763
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2470803765
Short name T433
Test name
Test status
Simulation time 52713493 ps
CPU time 1.24 seconds
Started Aug 11 06:27:27 PM PDT 24
Finished Aug 11 06:27:29 PM PDT 24
Peak memory 215440 kb
Host smart-e3895647-33d7-461c-94ed-4d9362bf2f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470803765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2470803765
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3322848704
Short name T448
Test name
Test status
Simulation time 122303548 ps
CPU time 1.14 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:27:35 PM PDT 24
Peak memory 217456 kb
Host smart-760f65a9-1e33-4458-95f9-4818eb032a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322848704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3322848704
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.521897249
Short name T630
Test name
Test status
Simulation time 71399095 ps
CPU time 1.77 seconds
Started Aug 11 06:27:33 PM PDT 24
Finished Aug 11 06:27:35 PM PDT 24
Peak memory 220012 kb
Host smart-8efd7018-21cb-40d6-a777-fffc27431874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521897249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.521897249
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3781237398
Short name T941
Test name
Test status
Simulation time 27076039 ps
CPU time 1.37 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:27:39 PM PDT 24
Peak memory 218692 kb
Host smart-bf94d1a0-4d75-40fe-af5b-3245ab6ecd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781237398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3781237398
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.806402571
Short name T366
Test name
Test status
Simulation time 43817841 ps
CPU time 1.63 seconds
Started Aug 11 06:27:32 PM PDT 24
Finished Aug 11 06:27:34 PM PDT 24
Peak memory 218728 kb
Host smart-729613b6-6297-4458-a389-7e2bb1ef5584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806402571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.806402571
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3227736116
Short name T444
Test name
Test status
Simulation time 137550561 ps
CPU time 1.13 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:27:40 PM PDT 24
Peak memory 217256 kb
Host smart-6a8254db-fe01-41c6-943d-f989ee9efb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227736116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3227736116
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3502150468
Short name T606
Test name
Test status
Simulation time 27797002 ps
CPU time 1.22 seconds
Started Aug 11 06:25:53 PM PDT 24
Finished Aug 11 06:25:54 PM PDT 24
Peak memory 220308 kb
Host smart-16c2c508-d05c-444d-b8e4-a131b853ef0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502150468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3502150468
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1752824820
Short name T673
Test name
Test status
Simulation time 46083429 ps
CPU time 0.87 seconds
Started Aug 11 06:25:53 PM PDT 24
Finished Aug 11 06:25:59 PM PDT 24
Peak memory 206800 kb
Host smart-8931053b-dc6a-491d-95e5-6c278604e1e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752824820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1752824820
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.235245953
Short name T185
Test name
Test status
Simulation time 33259593 ps
CPU time 0.87 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:53 PM PDT 24
Peak memory 216584 kb
Host smart-05309eac-dba8-4efc-9576-a7acc544ee7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235245953 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.235245953
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2887125045
Short name T371
Test name
Test status
Simulation time 36924694 ps
CPU time 1.25 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 217100 kb
Host smart-c49f3a3e-b95a-4fe1-99b2-d79af2514687
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887125045 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2887125045
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.4054562463
Short name T729
Test name
Test status
Simulation time 72782022 ps
CPU time 0.8 seconds
Started Aug 11 06:25:47 PM PDT 24
Finished Aug 11 06:25:48 PM PDT 24
Peak memory 218392 kb
Host smart-05409317-2e64-44e4-8cd2-7559299e93bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054562463 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.4054562463
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1175970533
Short name T347
Test name
Test status
Simulation time 25312765 ps
CPU time 1.35 seconds
Started Aug 11 06:25:48 PM PDT 24
Finished Aug 11 06:25:50 PM PDT 24
Peak memory 217716 kb
Host smart-c2f3ee64-7125-4671-926f-4f6356c92794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175970533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1175970533
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3828520738
Short name T579
Test name
Test status
Simulation time 21421882 ps
CPU time 1.17 seconds
Started Aug 11 06:25:45 PM PDT 24
Finished Aug 11 06:25:46 PM PDT 24
Peak memory 215564 kb
Host smart-42fb710c-acda-4a42-94b9-539ca5a5afa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828520738 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3828520738
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.876176602
Short name T807
Test name
Test status
Simulation time 133444824 ps
CPU time 0.94 seconds
Started Aug 11 06:25:49 PM PDT 24
Finished Aug 11 06:25:50 PM PDT 24
Peak memory 215292 kb
Host smart-4ae7e715-85ef-47e1-a40d-cc72ce8b897e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876176602 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.876176602
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1858199232
Short name T730
Test name
Test status
Simulation time 1182227292 ps
CPU time 4.73 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:56 PM PDT 24
Peak memory 219948 kb
Host smart-bdddac3b-89b7-4f3b-a360-b16b398adac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858199232 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1858199232
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1941717866
Short name T953
Test name
Test status
Simulation time 36990063126 ps
CPU time 784.21 seconds
Started Aug 11 06:25:44 PM PDT 24
Finished Aug 11 06:38:48 PM PDT 24
Peak memory 223524 kb
Host smart-eb8575c2-a894-4502-9a6d-c32eda7194af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941717866 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1941717866
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2296977133
Short name T554
Test name
Test status
Simulation time 42858177 ps
CPU time 1.41 seconds
Started Aug 11 06:27:28 PM PDT 24
Finished Aug 11 06:27:29 PM PDT 24
Peak memory 218628 kb
Host smart-479f8325-495e-4427-8f0b-698eed751f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296977133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2296977133
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.4211338719
Short name T814
Test name
Test status
Simulation time 85112868 ps
CPU time 1.28 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:27:38 PM PDT 24
Peak memory 219916 kb
Host smart-3f1509a4-a057-4add-8883-0db69b8ae762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211338719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4211338719
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3077214292
Short name T489
Test name
Test status
Simulation time 40284798 ps
CPU time 1.43 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:27:36 PM PDT 24
Peak memory 218404 kb
Host smart-40518bae-f708-4aef-9ece-cfa60706a389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077214292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3077214292
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.745316153
Short name T507
Test name
Test status
Simulation time 37299093 ps
CPU time 1.43 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 218612 kb
Host smart-884dbe3c-4a92-4fd9-ad4c-0459116764a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745316153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.745316153
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3562161031
Short name T786
Test name
Test status
Simulation time 158540686 ps
CPU time 1.31 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:27:35 PM PDT 24
Peak memory 218724 kb
Host smart-4489eab6-a8d3-4637-a65f-5719fc0913ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562161031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3562161031
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.25529775
Short name T982
Test name
Test status
Simulation time 99530132 ps
CPU time 2.19 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:27:42 PM PDT 24
Peak memory 220284 kb
Host smart-5252f5ab-30df-4668-9aca-16a40ed5aa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25529775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.25529775
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.872695124
Short name T399
Test name
Test status
Simulation time 55106057 ps
CPU time 1.32 seconds
Started Aug 11 06:27:30 PM PDT 24
Finished Aug 11 06:27:31 PM PDT 24
Peak memory 217484 kb
Host smart-75092942-d756-44a1-815e-555796f3e6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872695124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.872695124
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1437260201
Short name T801
Test name
Test status
Simulation time 199927896 ps
CPU time 1.34 seconds
Started Aug 11 06:27:30 PM PDT 24
Finished Aug 11 06:27:31 PM PDT 24
Peak memory 218768 kb
Host smart-f69ff244-6152-4c91-9bc3-cbe39713afc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437260201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1437260201
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1856148431
Short name T387
Test name
Test status
Simulation time 98064305 ps
CPU time 1.33 seconds
Started Aug 11 06:27:27 PM PDT 24
Finished Aug 11 06:27:29 PM PDT 24
Peak memory 218700 kb
Host smart-e045b5ca-c40b-4cbc-8970-3c56dbc11dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856148431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1856148431
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.456492834
Short name T825
Test name
Test status
Simulation time 49951962 ps
CPU time 1.29 seconds
Started Aug 11 06:27:31 PM PDT 24
Finished Aug 11 06:27:33 PM PDT 24
Peak memory 218584 kb
Host smart-e5c68d32-b348-4971-bc67-28db382f9efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456492834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.456492834
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3344346183
Short name T83
Test name
Test status
Simulation time 27740115 ps
CPU time 1.32 seconds
Started Aug 11 06:25:48 PM PDT 24
Finished Aug 11 06:25:49 PM PDT 24
Peak memory 219520 kb
Host smart-a772046d-51b8-431b-b534-f85c2be026f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344346183 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3344346183
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.914090017
Short name T635
Test name
Test status
Simulation time 27189436 ps
CPU time 0.9 seconds
Started Aug 11 06:25:53 PM PDT 24
Finished Aug 11 06:25:54 PM PDT 24
Peak memory 206820 kb
Host smart-7c0538f7-a46c-4197-ae76-e903f7f02627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914090017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.914090017
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1389755769
Short name T415
Test name
Test status
Simulation time 168799076 ps
CPU time 0.99 seconds
Started Aug 11 06:26:00 PM PDT 24
Finished Aug 11 06:26:01 PM PDT 24
Peak memory 218452 kb
Host smart-cafcf7d6-e7bc-4c63-829e-9495659afd97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389755769 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1389755769
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2466476967
Short name T211
Test name
Test status
Simulation time 19891248 ps
CPU time 1.05 seconds
Started Aug 11 06:25:54 PM PDT 24
Finished Aug 11 06:26:00 PM PDT 24
Peak memory 218908 kb
Host smart-07057c2a-7900-4452-84ac-891b6c856a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466476967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2466476967
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2674736812
Short name T576
Test name
Test status
Simulation time 82440366 ps
CPU time 1.17 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:53 PM PDT 24
Peak memory 218600 kb
Host smart-2976fc3f-c6a8-42d6-8887-0d51b597f304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674736812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2674736812
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_smoke.246870780
Short name T875
Test name
Test status
Simulation time 43324130 ps
CPU time 1 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:53 PM PDT 24
Peak memory 215300 kb
Host smart-267ccfc1-7d51-4cb8-8b14-b9fb16b51a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246870780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.246870780
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1590466571
Short name T564
Test name
Test status
Simulation time 508252172 ps
CPU time 3.18 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:54 PM PDT 24
Peak memory 220324 kb
Host smart-f2fdd413-125d-4995-963b-5f0ab1e06d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590466571 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1590466571
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2976216357
Short name T684
Test name
Test status
Simulation time 98721086577 ps
CPU time 2397.49 seconds
Started Aug 11 06:25:54 PM PDT 24
Finished Aug 11 07:05:51 PM PDT 24
Peak memory 230544 kb
Host smart-5fd01787-02a2-42dc-ac75-a8d65630ec86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976216357 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2976216357
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2441114655
Short name T792
Test name
Test status
Simulation time 83790603 ps
CPU time 1.49 seconds
Started Aug 11 06:27:30 PM PDT 24
Finished Aug 11 06:27:32 PM PDT 24
Peak memory 219116 kb
Host smart-67503db9-2473-4f7b-9a02-875b956fb71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441114655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2441114655
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1928115917
Short name T631
Test name
Test status
Simulation time 62351302 ps
CPU time 1.35 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:27:38 PM PDT 24
Peak memory 217320 kb
Host smart-11d69fbc-403f-40ab-89c3-0775ee77cb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928115917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1928115917
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.87593897
Short name T897
Test name
Test status
Simulation time 92027255 ps
CPU time 2.16 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:27:40 PM PDT 24
Peak memory 218916 kb
Host smart-445befbc-078d-4d42-a7f5-e9961f69c61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87593897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.87593897
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.4047874988
Short name T420
Test name
Test status
Simulation time 60943352 ps
CPU time 1.47 seconds
Started Aug 11 06:27:30 PM PDT 24
Finished Aug 11 06:27:31 PM PDT 24
Peak memory 218680 kb
Host smart-89c96d29-3d9c-4b8c-a0af-e9b870cf8e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047874988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.4047874988
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3284257324
Short name T844
Test name
Test status
Simulation time 36107943 ps
CPU time 0.99 seconds
Started Aug 11 06:27:33 PM PDT 24
Finished Aug 11 06:27:35 PM PDT 24
Peak memory 217372 kb
Host smart-f1a4a70d-c739-456a-ad76-a40895f71da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284257324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3284257324
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1463640299
Short name T593
Test name
Test status
Simulation time 37391915 ps
CPU time 1.39 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:27:38 PM PDT 24
Peak memory 215280 kb
Host smart-0722bcc3-068d-4f65-b5c7-dd5425b905a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463640299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1463640299
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2862777763
Short name T888
Test name
Test status
Simulation time 81272620 ps
CPU time 1.19 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 218956 kb
Host smart-4daf3419-4264-419e-a2dd-350ea362684b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862777763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2862777763
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3967683702
Short name T59
Test name
Test status
Simulation time 72818970 ps
CPU time 1.37 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 218620 kb
Host smart-26eafe48-5eb5-400e-8433-002412d26424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967683702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3967683702
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3782538808
Short name T603
Test name
Test status
Simulation time 43533510 ps
CPU time 1.2 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:27:41 PM PDT 24
Peak memory 218748 kb
Host smart-e8e87a7c-ed14-48d0-ac32-0e0e269b498a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782538808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3782538808
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1111082358
Short name T434
Test name
Test status
Simulation time 45565352 ps
CPU time 1.85 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 220180 kb
Host smart-2bc34eda-1973-4036-b40e-42906f117598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111082358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1111082358
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.669352770
Short name T836
Test name
Test status
Simulation time 76215539 ps
CPU time 1.14 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 218676 kb
Host smart-4463a191-0b8c-4294-9dbb-a3bc64dc595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669352770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.669352770
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.676972667
Short name T470
Test name
Test status
Simulation time 18829722 ps
CPU time 0.83 seconds
Started Aug 11 06:25:58 PM PDT 24
Finished Aug 11 06:25:59 PM PDT 24
Peak memory 206728 kb
Host smart-24f6e358-f3b2-40cf-b9e5-eefd4a949867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676972667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.676972667
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.183234694
Short name T893
Test name
Test status
Simulation time 16016882 ps
CPU time 0.86 seconds
Started Aug 11 06:26:00 PM PDT 24
Finished Aug 11 06:26:01 PM PDT 24
Peak memory 216520 kb
Host smart-2a8ff430-7451-4743-9b52-88e831a190ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183234694 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.183234694
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.483597253
Short name T655
Test name
Test status
Simulation time 54059699 ps
CPU time 1.11 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:57 PM PDT 24
Peak memory 219412 kb
Host smart-40cb4311-f7e6-41a8-9fc4-8b8805f46f6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483597253 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.483597253
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.938870998
Short name T54
Test name
Test status
Simulation time 70830567 ps
CPU time 1.25 seconds
Started Aug 11 06:25:53 PM PDT 24
Finished Aug 11 06:25:54 PM PDT 24
Peak memory 224856 kb
Host smart-054d078b-20d6-479e-a55b-d9f02ce64f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938870998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.938870998
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3322454520
Short name T653
Test name
Test status
Simulation time 72961173 ps
CPU time 1.13 seconds
Started Aug 11 06:25:52 PM PDT 24
Finished Aug 11 06:25:54 PM PDT 24
Peak memory 219084 kb
Host smart-ac76871a-6b4e-454c-be6a-36d66b131f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322454520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3322454520
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.981973014
Short name T783
Test name
Test status
Simulation time 46315668 ps
CPU time 0.95 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:56 PM PDT 24
Peak memory 215320 kb
Host smart-3e79c4fb-b9b9-4d83-ab9e-c21c54ba5551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981973014 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.981973014
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3222566778
Short name T581
Test name
Test status
Simulation time 813632904 ps
CPU time 5.58 seconds
Started Aug 11 06:25:58 PM PDT 24
Finished Aug 11 06:26:04 PM PDT 24
Peak memory 217424 kb
Host smart-0753723f-845d-41d1-9d89-d93b843e848f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222566778 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3222566778
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.562264922
Short name T978
Test name
Test status
Simulation time 432326091475 ps
CPU time 1903.07 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:57:33 PM PDT 24
Peak memory 228564 kb
Host smart-f3881139-7cbf-4995-b58a-3f18953bb1de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562264922 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.562264922
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.4248829475
Short name T626
Test name
Test status
Simulation time 52859298 ps
CPU time 1.36 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:27:41 PM PDT 24
Peak memory 220056 kb
Host smart-877eeec5-70ba-4a7b-a2b5-294fb6fa3482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248829475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.4248829475
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2034792455
Short name T510
Test name
Test status
Simulation time 75877757 ps
CPU time 1.28 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:27:41 PM PDT 24
Peak memory 218860 kb
Host smart-c4b7c869-9e70-4fd1-9c59-8129ce47f3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034792455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2034792455
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.247873723
Short name T513
Test name
Test status
Simulation time 30126764 ps
CPU time 1.34 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:27:42 PM PDT 24
Peak memory 217528 kb
Host smart-357e7185-6edb-4017-91f5-e51b45d35405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247873723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.247873723
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3064079514
Short name T584
Test name
Test status
Simulation time 49968092 ps
CPU time 1.24 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 218488 kb
Host smart-a7f34088-fd23-4e30-8afa-07e88610734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064079514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3064079514
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2496519619
Short name T375
Test name
Test status
Simulation time 102343631 ps
CPU time 1.86 seconds
Started Aug 11 06:27:29 PM PDT 24
Finished Aug 11 06:27:31 PM PDT 24
Peak memory 219032 kb
Host smart-99d0917b-d346-482d-b449-2f1a3955b49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496519619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2496519619
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1676480622
Short name T951
Test name
Test status
Simulation time 176053460 ps
CPU time 1.49 seconds
Started Aug 11 06:27:30 PM PDT 24
Finished Aug 11 06:27:32 PM PDT 24
Peak memory 218948 kb
Host smart-d7072bbb-8262-4c13-90ee-e75b5517a78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676480622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1676480622
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1257819187
Short name T914
Test name
Test status
Simulation time 165838540 ps
CPU time 2.91 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 219100 kb
Host smart-6b9604f6-afad-42d5-a0c3-3ba4928d43cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257819187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1257819187
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2539838719
Short name T509
Test name
Test status
Simulation time 86907513 ps
CPU time 1.69 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:27:40 PM PDT 24
Peak memory 220184 kb
Host smart-535b0f06-f60d-4760-a6db-ba1a79522833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539838719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2539838719
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1736614373
Short name T310
Test name
Test status
Simulation time 38832354 ps
CPU time 1.66 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 219348 kb
Host smart-ae9ad9f8-d9aa-4269-9da8-f1efe7c82f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736614373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1736614373
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1289248239
Short name T934
Test name
Test status
Simulation time 37097053 ps
CPU time 1.3 seconds
Started Aug 11 06:27:29 PM PDT 24
Finished Aug 11 06:27:30 PM PDT 24
Peak memory 218532 kb
Host smart-59903202-1d39-4981-9fcd-fdb02b7b3a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289248239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1289248239
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.931254316
Short name T274
Test name
Test status
Simulation time 82660428 ps
CPU time 1.18 seconds
Started Aug 11 06:25:14 PM PDT 24
Finished Aug 11 06:25:16 PM PDT 24
Peak memory 218472 kb
Host smart-57dd7af7-e344-4208-b01c-8306bc5cdec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931254316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.931254316
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2321729421
Short name T704
Test name
Test status
Simulation time 29683928 ps
CPU time 0.86 seconds
Started Aug 11 06:25:13 PM PDT 24
Finished Aug 11 06:25:14 PM PDT 24
Peak memory 215080 kb
Host smart-6d770d50-c1a8-462e-b9a9-3db7ed13107d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321729421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2321729421
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1694755479
Short name T157
Test name
Test status
Simulation time 29056010 ps
CPU time 1.23 seconds
Started Aug 11 06:25:13 PM PDT 24
Finished Aug 11 06:25:15 PM PDT 24
Peak memory 217064 kb
Host smart-dff194e5-df87-467f-94c1-6ec6ef59c869
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694755479 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1694755479
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3496137224
Short name T481
Test name
Test status
Simulation time 28117040 ps
CPU time 0.84 seconds
Started Aug 11 06:25:17 PM PDT 24
Finished Aug 11 06:25:18 PM PDT 24
Peak memory 218592 kb
Host smart-642db7d3-bf7f-41a8-a54d-0fee8253ecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496137224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3496137224
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3234714424
Short name T823
Test name
Test status
Simulation time 38716907 ps
CPU time 1.47 seconds
Started Aug 11 06:25:12 PM PDT 24
Finished Aug 11 06:25:14 PM PDT 24
Peak memory 217256 kb
Host smart-3f8806d8-2f12-4cdb-91b7-8b0a55667514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234714424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3234714424
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2863166759
Short name T720
Test name
Test status
Simulation time 29137845 ps
CPU time 0.9 seconds
Started Aug 11 06:25:17 PM PDT 24
Finished Aug 11 06:25:18 PM PDT 24
Peak memory 216196 kb
Host smart-63628b34-8ccd-4f52-b306-0cb03c9035e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863166759 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2863166759
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1071217859
Short name T866
Test name
Test status
Simulation time 26938325 ps
CPU time 0.95 seconds
Started Aug 11 06:25:21 PM PDT 24
Finished Aug 11 06:25:22 PM PDT 24
Peak memory 207112 kb
Host smart-71e6fb13-f167-4816-85d1-f75ba729e177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071217859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1071217859
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1056179191
Short name T20
Test name
Test status
Simulation time 1019924191 ps
CPU time 8.05 seconds
Started Aug 11 06:25:14 PM PDT 24
Finished Aug 11 06:25:22 PM PDT 24
Peak memory 243280 kb
Host smart-2758fae9-e458-43ee-a0ce-9bd4015f59f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056179191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1056179191
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3286000332
Short name T359
Test name
Test status
Simulation time 34508527 ps
CPU time 0.93 seconds
Started Aug 11 06:25:14 PM PDT 24
Finished Aug 11 06:25:15 PM PDT 24
Peak memory 215272 kb
Host smart-3c146f46-c78e-4fda-8134-e4b00b4da17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286000332 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3286000332
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.101650100
Short name T972
Test name
Test status
Simulation time 105974382 ps
CPU time 2.16 seconds
Started Aug 11 06:25:17 PM PDT 24
Finished Aug 11 06:25:19 PM PDT 24
Peak memory 215388 kb
Host smart-d4e1aaa5-a948-4c0c-99c4-f12a1aafead3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101650100 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.101650100
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2914977186
Short name T99
Test name
Test status
Simulation time 19973627379 ps
CPU time 438.91 seconds
Started Aug 11 06:25:18 PM PDT 24
Finished Aug 11 06:32:37 PM PDT 24
Peak memory 223600 kb
Host smart-515f3bf4-1932-46c9-b753-c2c018897782
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914977186 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2914977186
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.713326670
Short name T766
Test name
Test status
Simulation time 162334795 ps
CPU time 1.29 seconds
Started Aug 11 06:25:54 PM PDT 24
Finished Aug 11 06:25:55 PM PDT 24
Peak memory 219460 kb
Host smart-9d8efe75-4eae-4aa6-838a-3d6eda9a3909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713326670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.713326670
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1482426184
Short name T400
Test name
Test status
Simulation time 25791628 ps
CPU time 0.87 seconds
Started Aug 11 06:25:52 PM PDT 24
Finished Aug 11 06:25:53 PM PDT 24
Peak memory 206776 kb
Host smart-106de760-a0b8-4d76-9448-0a80279b2d2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482426184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1482426184
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1042584471
Short name T624
Test name
Test status
Simulation time 36802382 ps
CPU time 0.84 seconds
Started Aug 11 06:25:54 PM PDT 24
Finished Aug 11 06:25:55 PM PDT 24
Peak memory 216468 kb
Host smart-9f820a06-0af6-4252-8848-fc73b8d1d3d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042584471 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1042584471
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.732006380
Short name T671
Test name
Test status
Simulation time 29870425 ps
CPU time 1.2 seconds
Started Aug 11 06:25:54 PM PDT 24
Finished Aug 11 06:25:55 PM PDT 24
Peak memory 217028 kb
Host smart-c671d46c-4d5d-4afc-9066-3930251dbbd2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732006380 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.732006380
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.875754551
Short name T210
Test name
Test status
Simulation time 30444397 ps
CPU time 1.37 seconds
Started Aug 11 06:25:52 PM PDT 24
Finished Aug 11 06:25:53 PM PDT 24
Peak memory 225908 kb
Host smart-86429185-9325-444d-8dab-05ac5c68417f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875754551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.875754551
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2359808980
Short name T465
Test name
Test status
Simulation time 182958460 ps
CPU time 1.08 seconds
Started Aug 11 06:25:57 PM PDT 24
Finished Aug 11 06:25:58 PM PDT 24
Peak memory 217692 kb
Host smart-5d05c9fc-7e5b-423f-8530-c04291e90ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359808980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2359808980
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2115867907
Short name T93
Test name
Test status
Simulation time 20922525 ps
CPU time 1.06 seconds
Started Aug 11 06:26:01 PM PDT 24
Finished Aug 11 06:26:03 PM PDT 24
Peak memory 215996 kb
Host smart-d1034561-93de-4e7c-8f51-0bc17f08234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115867907 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2115867907
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.707675747
Short name T872
Test name
Test status
Simulation time 45939122 ps
CPU time 0.91 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:56 PM PDT 24
Peak memory 215308 kb
Host smart-ef0c30e4-2537-4727-9a45-62f9666500b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707675747 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.707675747
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2989826516
Short name T562
Test name
Test status
Simulation time 535438726 ps
CPU time 5.22 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:26:01 PM PDT 24
Peak memory 217364 kb
Host smart-eb40eea0-d2fa-42f0-8c5a-8895de32723b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989826516 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2989826516
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3523482970
Short name T451
Test name
Test status
Simulation time 44505933758 ps
CPU time 960.42 seconds
Started Aug 11 06:25:56 PM PDT 24
Finished Aug 11 06:41:57 PM PDT 24
Peak memory 218616 kb
Host smart-acb8bfc1-f5d8-476b-a0bc-f04ccd6f9de8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523482970 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3523482970
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2399105665
Short name T275
Test name
Test status
Simulation time 33744143 ps
CPU time 1.33 seconds
Started Aug 11 06:25:57 PM PDT 24
Finished Aug 11 06:25:59 PM PDT 24
Peak memory 215556 kb
Host smart-40a93bbb-3250-4af9-b5c0-8fc8ba3ed578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399105665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2399105665
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.472180521
Short name T762
Test name
Test status
Simulation time 19125411 ps
CPU time 0.82 seconds
Started Aug 11 06:25:57 PM PDT 24
Finished Aug 11 06:25:58 PM PDT 24
Peak memory 206776 kb
Host smart-005f8192-f647-467f-bca7-33d22a3fb4a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472180521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.472180521
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1907818807
Short name T574
Test name
Test status
Simulation time 28028439 ps
CPU time 0.86 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:56 PM PDT 24
Peak memory 216324 kb
Host smart-cd8431c4-7e7b-46dc-bb30-9f446b89b80c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907818807 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1907818807
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1898744157
Short name T551
Test name
Test status
Simulation time 41645424 ps
CPU time 1.41 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:57 PM PDT 24
Peak memory 217156 kb
Host smart-70ec5ac4-8e4a-4929-85a2-87d5e81a8f58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898744157 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1898744157
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3405644407
Short name T500
Test name
Test status
Simulation time 20164158 ps
CPU time 1.05 seconds
Started Aug 11 06:25:53 PM PDT 24
Finished Aug 11 06:25:54 PM PDT 24
Peak memory 218872 kb
Host smart-5803f0b7-14ba-493d-a71a-8099be80eb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405644407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3405644407
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1889068076
Short name T305
Test name
Test status
Simulation time 45828161 ps
CPU time 1.53 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:57 PM PDT 24
Peak memory 218616 kb
Host smart-082c16b4-a471-4a76-9e8c-ab8be9b1cbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889068076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1889068076
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1795298751
Short name T987
Test name
Test status
Simulation time 46974709 ps
CPU time 0.88 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:56 PM PDT 24
Peak memory 215180 kb
Host smart-169d468c-10c7-4cfd-91ef-d0654575334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795298751 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1795298751
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1936932650
Short name T852
Test name
Test status
Simulation time 50647222 ps
CPU time 0.92 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:57 PM PDT 24
Peak memory 215300 kb
Host smart-aa381889-801a-4057-b9df-fa8055c03d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936932650 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1936932650
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.258231629
Short name T617
Test name
Test status
Simulation time 644423841 ps
CPU time 3.84 seconds
Started Aug 11 06:25:52 PM PDT 24
Finished Aug 11 06:25:56 PM PDT 24
Peak memory 217220 kb
Host smart-7e9224a4-f166-4845-9b0f-1aad45df12b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258231629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.258231629
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1508113379
Short name T235
Test name
Test status
Simulation time 83530573330 ps
CPU time 412.04 seconds
Started Aug 11 06:26:04 PM PDT 24
Finished Aug 11 06:32:56 PM PDT 24
Peak memory 223428 kb
Host smart-3eef8324-fc15-4ce0-8d5a-3cc1a5d8add1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508113379 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1508113379
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2499281122
Short name T884
Test name
Test status
Simulation time 134425444 ps
CPU time 1.29 seconds
Started Aug 11 06:25:52 PM PDT 24
Finished Aug 11 06:25:53 PM PDT 24
Peak memory 219672 kb
Host smart-fd254add-4941-418e-b313-f9a3b450b597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499281122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2499281122
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.830420195
Short name T993
Test name
Test status
Simulation time 32730016 ps
CPU time 0.94 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 206784 kb
Host smart-a147b976-1990-42df-a594-7b6c62516073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830420195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.830420195
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2247240049
Short name T891
Test name
Test status
Simulation time 28873292 ps
CPU time 0.84 seconds
Started Aug 11 06:25:50 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 215372 kb
Host smart-3f021519-24cc-4e1d-b211-8609dcd000b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247240049 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2247240049
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.27993489
Short name T980
Test name
Test status
Simulation time 134790187 ps
CPU time 1.16 seconds
Started Aug 11 06:25:57 PM PDT 24
Finished Aug 11 06:25:59 PM PDT 24
Peak memory 218440 kb
Host smart-4a39767c-49e1-4bbc-9681-a0aebe7b46f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27993489 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_dis
able_auto_req_mode.27993489
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.818459574
Short name T133
Test name
Test status
Simulation time 23667637 ps
CPU time 1.32 seconds
Started Aug 11 06:25:57 PM PDT 24
Finished Aug 11 06:25:58 PM PDT 24
Peak memory 229736 kb
Host smart-30e1ca6c-de6d-443b-89bc-5d464aa4035d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818459574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.818459574
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2492673561
Short name T320
Test name
Test status
Simulation time 112583168 ps
CPU time 1.37 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:56 PM PDT 24
Peak memory 217344 kb
Host smart-5319a92f-92ab-42a6-9885-6cad60478a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492673561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2492673561
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1376496549
Short name T36
Test name
Test status
Simulation time 22865717 ps
CPU time 0.91 seconds
Started Aug 11 06:25:59 PM PDT 24
Finished Aug 11 06:26:00 PM PDT 24
Peak memory 216172 kb
Host smart-7e20daee-efbb-42d8-9f7e-48e54537483a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376496549 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1376496549
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3501264130
Short name T810
Test name
Test status
Simulation time 72912927 ps
CPU time 0.92 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:57 PM PDT 24
Peak memory 215312 kb
Host smart-794ea426-f91d-422a-bf0c-893ee040e489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501264130 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3501264130
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.4000561100
Short name T497
Test name
Test status
Simulation time 302765511 ps
CPU time 5.25 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:26:00 PM PDT 24
Peak memory 217160 kb
Host smart-7e6ab216-9e00-4e55-b26c-72138776fb4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000561100 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.4000561100
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3321050911
Short name T234
Test name
Test status
Simulation time 126275227813 ps
CPU time 1530.64 seconds
Started Aug 11 06:26:02 PM PDT 24
Finished Aug 11 06:51:33 PM PDT 24
Peak memory 224576 kb
Host smart-1a8e5908-8a4e-44f6-a25d-f7fa92345470
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321050911 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3321050911
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2644482046
Short name T105
Test name
Test status
Simulation time 26160422 ps
CPU time 1.3 seconds
Started Aug 11 06:25:57 PM PDT 24
Finished Aug 11 06:25:58 PM PDT 24
Peak memory 219304 kb
Host smart-cc53651a-7c4a-470d-951d-a66dcb4f4d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644482046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2644482046
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.833875361
Short name T49
Test name
Test status
Simulation time 21996377 ps
CPU time 0.83 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:52 PM PDT 24
Peak memory 206732 kb
Host smart-cb846019-bd62-4b2a-aa99-83443f85f2a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833875361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.833875361
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2518909989
Short name T195
Test name
Test status
Simulation time 53980718 ps
CPU time 0.85 seconds
Started Aug 11 06:25:52 PM PDT 24
Finished Aug 11 06:25:53 PM PDT 24
Peak memory 216572 kb
Host smart-d7d9e687-cc39-43c5-8d21-b227fe4ae910
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518909989 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2518909989
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1912628536
Short name T840
Test name
Test status
Simulation time 107483332 ps
CPU time 1.13 seconds
Started Aug 11 06:25:58 PM PDT 24
Finished Aug 11 06:25:59 PM PDT 24
Peak memory 216868 kb
Host smart-f0399880-1569-4bc3-b9fa-ace9fc220181
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912628536 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1912628536
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3764908657
Short name T963
Test name
Test status
Simulation time 37712226 ps
CPU time 1.26 seconds
Started Aug 11 06:25:53 PM PDT 24
Finished Aug 11 06:25:55 PM PDT 24
Peak memory 220180 kb
Host smart-1b877482-da37-491b-ac06-f4a3eb50d84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764908657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3764908657
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.448183897
Short name T283
Test name
Test status
Simulation time 61864856 ps
CPU time 1.19 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:53 PM PDT 24
Peak memory 217308 kb
Host smart-8d01bc16-4fa2-4428-bdb1-0b83b5f60b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448183897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.448183897
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3787564782
Short name T989
Test name
Test status
Simulation time 32759629 ps
CPU time 1.01 seconds
Started Aug 11 06:25:58 PM PDT 24
Finished Aug 11 06:25:59 PM PDT 24
Peak memory 223728 kb
Host smart-9c5931d9-0be8-4df6-b186-49baea838dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787564782 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3787564782
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.212053742
Short name T406
Test name
Test status
Simulation time 26626292 ps
CPU time 0.94 seconds
Started Aug 11 06:25:54 PM PDT 24
Finished Aug 11 06:25:55 PM PDT 24
Peak memory 215316 kb
Host smart-897998d9-2627-4b8a-8965-3e19529907a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212053742 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.212053742
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3227806388
Short name T4
Test name
Test status
Simulation time 217323787 ps
CPU time 4.34 seconds
Started Aug 11 06:25:56 PM PDT 24
Finished Aug 11 06:26:01 PM PDT 24
Peak memory 217436 kb
Host smart-16dd1c32-1a97-4e2d-bed7-cfca4d139c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227806388 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3227806388
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2509310546
Short name T789
Test name
Test status
Simulation time 36764994301 ps
CPU time 952.86 seconds
Started Aug 11 06:25:54 PM PDT 24
Finished Aug 11 06:41:47 PM PDT 24
Peak memory 223660 kb
Host smart-9e81eeef-7f04-4387-ba13-dcc5fd5c2994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509310546 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2509310546
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3329501618
Short name T703
Test name
Test status
Simulation time 72153245 ps
CPU time 1.14 seconds
Started Aug 11 06:26:03 PM PDT 24
Finished Aug 11 06:26:04 PM PDT 24
Peak memory 218496 kb
Host smart-d3c43bbb-227b-4124-89f0-415de776d86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329501618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3329501618
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3559434783
Short name T985
Test name
Test status
Simulation time 42019031 ps
CPU time 1.02 seconds
Started Aug 11 06:26:00 PM PDT 24
Finished Aug 11 06:26:01 PM PDT 24
Peak memory 215200 kb
Host smart-67c6062a-fe4b-4e13-b350-d3f085a5b677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559434783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3559434783
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.573297412
Short name T627
Test name
Test status
Simulation time 26995790 ps
CPU time 0.86 seconds
Started Aug 11 06:25:59 PM PDT 24
Finished Aug 11 06:26:00 PM PDT 24
Peak memory 207312 kb
Host smart-96675d55-7f49-411d-8bb2-f0c628ecb794
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573297412 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.573297412
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3621464939
Short name T121
Test name
Test status
Simulation time 37387467 ps
CPU time 1.27 seconds
Started Aug 11 06:26:04 PM PDT 24
Finished Aug 11 06:26:06 PM PDT 24
Peak memory 217160 kb
Host smart-c07b1d1c-f8f2-4eda-a8aa-08eb60082ae9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621464939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3621464939
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.951444326
Short name T666
Test name
Test status
Simulation time 56584520 ps
CPU time 1.28 seconds
Started Aug 11 06:26:14 PM PDT 24
Finished Aug 11 06:26:15 PM PDT 24
Peak memory 219984 kb
Host smart-b5b0cd5e-f7da-4606-afd5-296743c11170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951444326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.951444326
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.905771950
Short name T379
Test name
Test status
Simulation time 230386650 ps
CPU time 1.06 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:25:57 PM PDT 24
Peak memory 217300 kb
Host smart-987cbc68-eee2-4818-8c3d-b15ded4add43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905771950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.905771950
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.541395803
Short name T796
Test name
Test status
Simulation time 43934573 ps
CPU time 0.87 seconds
Started Aug 11 06:26:19 PM PDT 24
Finished Aug 11 06:26:20 PM PDT 24
Peak memory 215204 kb
Host smart-dd88650a-be0e-4da7-92fe-2162f8cb585e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541395803 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.541395803
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1211463837
Short name T534
Test name
Test status
Simulation time 31555593 ps
CPU time 0.98 seconds
Started Aug 11 06:25:55 PM PDT 24
Finished Aug 11 06:26:01 PM PDT 24
Peak memory 215312 kb
Host smart-c54e8ae2-3eeb-4cf0-b328-8bdb7187fefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211463837 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1211463837
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.143368798
Short name T247
Test name
Test status
Simulation time 1392446464 ps
CPU time 2.29 seconds
Started Aug 11 06:25:51 PM PDT 24
Finished Aug 11 06:25:53 PM PDT 24
Peak memory 217112 kb
Host smart-00e1367a-1195-417b-9167-81ad09407c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143368798 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.143368798
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3912893068
Short name T236
Test name
Test status
Simulation time 47192510112 ps
CPU time 522.3 seconds
Started Aug 11 06:25:59 PM PDT 24
Finished Aug 11 06:34:42 PM PDT 24
Peak memory 221580 kb
Host smart-fb423236-78b0-4cb1-aa88-327322998915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912893068 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3912893068
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.277273910
Short name T336
Test name
Test status
Simulation time 30753173 ps
CPU time 1.3 seconds
Started Aug 11 06:26:13 PM PDT 24
Finished Aug 11 06:26:15 PM PDT 24
Peak memory 219860 kb
Host smart-fb09955b-6bce-448f-836f-6e76391cf0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277273910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.277273910
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.555424088
Short name T590
Test name
Test status
Simulation time 44246273 ps
CPU time 0.89 seconds
Started Aug 11 06:26:11 PM PDT 24
Finished Aug 11 06:26:12 PM PDT 24
Peak memory 215188 kb
Host smart-9f9b8ebf-0c03-4637-ab6c-f2d15b03db03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555424088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.555424088
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.53753140
Short name T41
Test name
Test status
Simulation time 20903413 ps
CPU time 0.9 seconds
Started Aug 11 06:26:01 PM PDT 24
Finished Aug 11 06:26:02 PM PDT 24
Peak memory 216636 kb
Host smart-b0178239-76cb-4796-b4ec-594fe4c8564e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53753140 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.53753140
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.55489579
Short name T669
Test name
Test status
Simulation time 39107224 ps
CPU time 1.05 seconds
Started Aug 11 06:26:03 PM PDT 24
Finished Aug 11 06:26:05 PM PDT 24
Peak memory 218556 kb
Host smart-5a7aa7e1-f376-4c10-96ae-1615b66a8187
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55489579 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_dis
able_auto_req_mode.55489579
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1888278772
Short name T575
Test name
Test status
Simulation time 21453810 ps
CPU time 0.91 seconds
Started Aug 11 06:26:01 PM PDT 24
Finished Aug 11 06:26:02 PM PDT 24
Peak memory 218476 kb
Host smart-41ab399b-bc5d-4c5c-8c9c-00b3b7ddaded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888278772 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1888278772
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3765767754
Short name T895
Test name
Test status
Simulation time 79522231 ps
CPU time 1.33 seconds
Started Aug 11 06:26:02 PM PDT 24
Finished Aug 11 06:26:04 PM PDT 24
Peak memory 218852 kb
Host smart-6e8d2f0b-a5f8-45bd-8e4b-d2206aa308a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765767754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3765767754
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1604467209
Short name T723
Test name
Test status
Simulation time 68926001 ps
CPU time 1.02 seconds
Started Aug 11 06:26:01 PM PDT 24
Finished Aug 11 06:26:02 PM PDT 24
Peak memory 223972 kb
Host smart-8b73f8f7-8129-417e-8d25-17c21f7da06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604467209 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1604467209
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1914658461
Short name T971
Test name
Test status
Simulation time 16540970 ps
CPU time 0.97 seconds
Started Aug 11 06:26:02 PM PDT 24
Finished Aug 11 06:26:03 PM PDT 24
Peak memory 215264 kb
Host smart-eab7dfde-b35e-49f6-8a68-de47b372d174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914658461 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1914658461
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2175628026
Short name T776
Test name
Test status
Simulation time 488328823 ps
CPU time 3.2 seconds
Started Aug 11 06:26:09 PM PDT 24
Finished Aug 11 06:26:12 PM PDT 24
Peak memory 215388 kb
Host smart-d6f0791e-9a73-4ae0-af4d-064f3c39c7f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175628026 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2175628026
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2036369115
Short name T937
Test name
Test status
Simulation time 17348240700 ps
CPU time 390.86 seconds
Started Aug 11 06:26:15 PM PDT 24
Finished Aug 11 06:32:45 PM PDT 24
Peak memory 216452 kb
Host smart-e76d896a-1382-4d53-8584-a5d132ec7252
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036369115 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2036369115
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert_test.1617919206
Short name T442
Test name
Test status
Simulation time 13074697 ps
CPU time 0.85 seconds
Started Aug 11 06:25:59 PM PDT 24
Finished Aug 11 06:26:00 PM PDT 24
Peak memory 207048 kb
Host smart-bfe9ea45-d084-48da-978d-d62d3b4e847a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617919206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1617919206
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1398584644
Short name T751
Test name
Test status
Simulation time 50449783 ps
CPU time 1.18 seconds
Started Aug 11 06:26:14 PM PDT 24
Finished Aug 11 06:26:15 PM PDT 24
Peak memory 217320 kb
Host smart-c9ef2c57-840c-4a27-aa69-508509618a51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398584644 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1398584644
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.687705870
Short name T473
Test name
Test status
Simulation time 21983661 ps
CPU time 0.91 seconds
Started Aug 11 06:26:04 PM PDT 24
Finished Aug 11 06:26:05 PM PDT 24
Peak memory 218932 kb
Host smart-d00d3b4a-ce3b-49dc-a6d8-974dda7f102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687705870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.687705870
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.935492348
Short name T991
Test name
Test status
Simulation time 296535859 ps
CPU time 3.56 seconds
Started Aug 11 06:25:59 PM PDT 24
Finished Aug 11 06:26:03 PM PDT 24
Peak memory 219876 kb
Host smart-4d7aae13-0ad5-424a-964a-a1b49389fd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935492348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.935492348
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.4133443674
Short name T765
Test name
Test status
Simulation time 24038045 ps
CPU time 1.1 seconds
Started Aug 11 06:26:03 PM PDT 24
Finished Aug 11 06:26:04 PM PDT 24
Peak memory 215376 kb
Host smart-5788c7c8-a605-480a-b584-d291c6960799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133443674 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4133443674
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1124507169
Short name T992
Test name
Test status
Simulation time 17618966 ps
CPU time 1.03 seconds
Started Aug 11 06:26:10 PM PDT 24
Finished Aug 11 06:26:12 PM PDT 24
Peak memory 215344 kb
Host smart-8f4c7551-982e-482e-b1bb-5d071458fe91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124507169 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1124507169
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1363522532
Short name T605
Test name
Test status
Simulation time 326236164 ps
CPU time 2.45 seconds
Started Aug 11 06:25:58 PM PDT 24
Finished Aug 11 06:26:00 PM PDT 24
Peak memory 217320 kb
Host smart-b7343a14-c483-4a2b-ae3c-48985426dcc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363522532 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1363522532
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1126488110
Short name T237
Test name
Test status
Simulation time 24882455613 ps
CPU time 547.57 seconds
Started Aug 11 06:26:03 PM PDT 24
Finished Aug 11 06:35:10 PM PDT 24
Peak memory 217452 kb
Host smart-f97b796b-f90e-4fa1-9714-073aade74fb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126488110 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1126488110
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3435755282
Short name T944
Test name
Test status
Simulation time 65511144 ps
CPU time 1.09 seconds
Started Aug 11 06:26:21 PM PDT 24
Finished Aug 11 06:26:22 PM PDT 24
Peak memory 215576 kb
Host smart-dd77ecdd-b9b2-42db-9d70-c8f06a862db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435755282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3435755282
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1726024351
Short name T364
Test name
Test status
Simulation time 28337810 ps
CPU time 0.91 seconds
Started Aug 11 06:25:58 PM PDT 24
Finished Aug 11 06:25:59 PM PDT 24
Peak memory 215176 kb
Host smart-c13859de-e307-4a01-8b9a-77d9aa2fb45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726024351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1726024351
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1909232091
Short name T639
Test name
Test status
Simulation time 40193386 ps
CPU time 0.86 seconds
Started Aug 11 06:26:10 PM PDT 24
Finished Aug 11 06:26:11 PM PDT 24
Peak memory 215516 kb
Host smart-ed3d28e4-dfdb-47ad-a5e8-7b4e2b4db95b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909232091 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1909232091
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2844724420
Short name T976
Test name
Test status
Simulation time 102570125 ps
CPU time 1.06 seconds
Started Aug 11 06:26:10 PM PDT 24
Finished Aug 11 06:26:11 PM PDT 24
Peak memory 219276 kb
Host smart-1f243695-7904-4a1f-b0f4-f69ebe9e4845
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844724420 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2844724420
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2615933179
Short name T715
Test name
Test status
Simulation time 21638534 ps
CPU time 0.98 seconds
Started Aug 11 06:26:17 PM PDT 24
Finished Aug 11 06:26:18 PM PDT 24
Peak memory 218768 kb
Host smart-ef5fe6e3-ddad-4eac-afd8-c5160879af76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615933179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2615933179
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3771959877
Short name T376
Test name
Test status
Simulation time 27748565 ps
CPU time 1.26 seconds
Started Aug 11 06:26:01 PM PDT 24
Finished Aug 11 06:26:02 PM PDT 24
Peak memory 217392 kb
Host smart-60afe02a-1ba0-4821-a8d8-b85f61447fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771959877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3771959877
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1991148691
Short name T949
Test name
Test status
Simulation time 26731680 ps
CPU time 1.07 seconds
Started Aug 11 06:26:04 PM PDT 24
Finished Aug 11 06:26:05 PM PDT 24
Peak memory 224128 kb
Host smart-82710e10-eed3-4c85-b784-00414413ef2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991148691 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1991148691
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3670437272
Short name T95
Test name
Test status
Simulation time 15289880 ps
CPU time 0.97 seconds
Started Aug 11 06:26:09 PM PDT 24
Finished Aug 11 06:26:11 PM PDT 24
Peak memory 215276 kb
Host smart-a3ddba8f-447c-488c-88f6-05ab3b34799a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670437272 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3670437272
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.229288184
Short name T739
Test name
Test status
Simulation time 213548474 ps
CPU time 4.46 seconds
Started Aug 11 06:26:09 PM PDT 24
Finished Aug 11 06:26:14 PM PDT 24
Peak memory 216868 kb
Host smart-4110d728-f535-4468-be6e-bff426c2c748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229288184 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.229288184
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3548296142
Short name T651
Test name
Test status
Simulation time 26891166155 ps
CPU time 554.56 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:35:20 PM PDT 24
Peak memory 218300 kb
Host smart-a23573ea-4f3b-48b7-9fee-05dff57ae1e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548296142 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3548296142
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.665289517
Short name T122
Test name
Test status
Simulation time 28191606 ps
CPU time 1.26 seconds
Started Aug 11 06:25:59 PM PDT 24
Finished Aug 11 06:26:01 PM PDT 24
Peak memory 220544 kb
Host smart-6465dd13-a1d2-4b67-8239-145867eb9910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665289517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.665289517
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3335262568
Short name T748
Test name
Test status
Simulation time 21736896 ps
CPU time 0.86 seconds
Started Aug 11 06:26:16 PM PDT 24
Finished Aug 11 06:26:17 PM PDT 24
Peak memory 206764 kb
Host smart-29bcaf1d-14db-4af6-a479-000b500b18cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335262568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3335262568
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.233318286
Short name T667
Test name
Test status
Simulation time 11598854 ps
CPU time 0.87 seconds
Started Aug 11 06:25:59 PM PDT 24
Finished Aug 11 06:26:00 PM PDT 24
Peak memory 216400 kb
Host smart-49c2db96-2d6f-480f-9cf0-530d0fc89d9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233318286 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.233318286
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1480200103
Short name T227
Test name
Test status
Simulation time 126194209 ps
CPU time 1.13 seconds
Started Aug 11 06:26:08 PM PDT 24
Finished Aug 11 06:26:09 PM PDT 24
Peak memory 219580 kb
Host smart-c647c577-02d4-4606-85ba-15f5080c393e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480200103 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1480200103
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3577560865
Short name T162
Test name
Test status
Simulation time 25031387 ps
CPU time 0.9 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:26:06 PM PDT 24
Peak memory 218524 kb
Host smart-003fb9c9-9d48-42f1-bdf0-927bdeb0e276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577560865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3577560865
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2484572827
Short name T913
Test name
Test status
Simulation time 38893852 ps
CPU time 1.15 seconds
Started Aug 11 06:26:14 PM PDT 24
Finished Aug 11 06:26:15 PM PDT 24
Peak memory 217468 kb
Host smart-69516bb8-049d-4bb7-8336-f50f140a8138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484572827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2484572827
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3644983232
Short name T811
Test name
Test status
Simulation time 21162735 ps
CPU time 1.09 seconds
Started Aug 11 06:26:01 PM PDT 24
Finished Aug 11 06:26:03 PM PDT 24
Peak memory 215344 kb
Host smart-8cc66330-0d99-475e-a05d-0143bcac1072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644983232 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3644983232
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1375074979
Short name T621
Test name
Test status
Simulation time 104143652 ps
CPU time 0.86 seconds
Started Aug 11 06:26:04 PM PDT 24
Finished Aug 11 06:26:05 PM PDT 24
Peak memory 215128 kb
Host smart-864ef6d1-70c9-4436-bae6-f4ff0e0d5a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375074979 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1375074979
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2162814754
Short name T241
Test name
Test status
Simulation time 104419277 ps
CPU time 1.11 seconds
Started Aug 11 06:26:12 PM PDT 24
Finished Aug 11 06:26:13 PM PDT 24
Peak memory 207292 kb
Host smart-e52cf911-fcd5-4682-9e80-4902cd196959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162814754 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2162814754
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.147581207
Short name T238
Test name
Test status
Simulation time 58643642347 ps
CPU time 1271.93 seconds
Started Aug 11 06:26:06 PM PDT 24
Finished Aug 11 06:47:18 PM PDT 24
Peak memory 221632 kb
Host smart-44079fef-8d86-44b8-b35d-c614e4e8d2db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147581207 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.147581207
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2146021364
Short name T416
Test name
Test status
Simulation time 31381496 ps
CPU time 1.36 seconds
Started Aug 11 06:26:07 PM PDT 24
Finished Aug 11 06:26:09 PM PDT 24
Peak memory 219348 kb
Host smart-79f100e5-f396-4f9c-bedc-3691e405837d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146021364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2146021364
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3510887974
Short name T517
Test name
Test status
Simulation time 26546987 ps
CPU time 0.9 seconds
Started Aug 11 06:26:21 PM PDT 24
Finished Aug 11 06:26:22 PM PDT 24
Peak memory 206808 kb
Host smart-964778f2-ef91-47c9-92cd-2cc111dc913d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510887974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3510887974
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1268894874
Short name T214
Test name
Test status
Simulation time 11974419 ps
CPU time 0.9 seconds
Started Aug 11 06:26:04 PM PDT 24
Finished Aug 11 06:26:05 PM PDT 24
Peak memory 219252 kb
Host smart-644479ac-1302-4281-a778-2ea919c89822
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268894874 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1268894874
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1282951334
Short name T156
Test name
Test status
Simulation time 33470607 ps
CPU time 1.18 seconds
Started Aug 11 06:26:09 PM PDT 24
Finished Aug 11 06:26:11 PM PDT 24
Peak memory 219428 kb
Host smart-255ba5d0-2a75-4f3c-b7d4-5dce95345a58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282951334 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1282951334
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3617656138
Short name T646
Test name
Test status
Simulation time 32673353 ps
CPU time 1.01 seconds
Started Aug 11 06:26:14 PM PDT 24
Finished Aug 11 06:26:15 PM PDT 24
Peak memory 219912 kb
Host smart-c7f46148-0cb3-4ad0-a2e3-61a098f1fd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617656138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3617656138
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1450863145
Short name T352
Test name
Test status
Simulation time 84702315 ps
CPU time 1.18 seconds
Started Aug 11 06:26:13 PM PDT 24
Finished Aug 11 06:26:14 PM PDT 24
Peak memory 217536 kb
Host smart-51e93e32-f776-4805-91a3-d0c0f71b590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450863145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1450863145
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2767342010
Short name T990
Test name
Test status
Simulation time 44532020 ps
CPU time 1.01 seconds
Started Aug 11 06:26:14 PM PDT 24
Finished Aug 11 06:26:15 PM PDT 24
Peak memory 224120 kb
Host smart-189b872a-fe49-430b-a04c-17a13b19fa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767342010 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2767342010
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2050400903
Short name T57
Test name
Test status
Simulation time 41509492 ps
CPU time 1 seconds
Started Aug 11 06:26:09 PM PDT 24
Finished Aug 11 06:26:10 PM PDT 24
Peak memory 215276 kb
Host smart-b3a2fde2-121a-4a8c-bf45-54e24ba5219d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050400903 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2050400903
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3941008022
Short name T452
Test name
Test status
Simulation time 260983735 ps
CPU time 1 seconds
Started Aug 11 06:26:03 PM PDT 24
Finished Aug 11 06:26:04 PM PDT 24
Peak memory 217152 kb
Host smart-909a0ab2-5763-4b83-8b2b-c0ebd50c4417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941008022 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3941008022
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_alert.2958113778
Short name T109
Test name
Test status
Simulation time 96160801 ps
CPU time 1.31 seconds
Started Aug 11 06:25:15 PM PDT 24
Finished Aug 11 06:25:17 PM PDT 24
Peak memory 218408 kb
Host smart-686132c8-b7ad-4ed7-8fed-16ab8ffff0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958113778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2958113778
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1927102762
Short name T727
Test name
Test status
Simulation time 33695840 ps
CPU time 0.96 seconds
Started Aug 11 06:25:18 PM PDT 24
Finished Aug 11 06:25:19 PM PDT 24
Peak memory 215228 kb
Host smart-0326da12-534d-4d6a-9052-b3ba58058670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927102762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1927102762
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2690625634
Short name T578
Test name
Test status
Simulation time 29532369 ps
CPU time 0.84 seconds
Started Aug 11 06:25:16 PM PDT 24
Finished Aug 11 06:25:17 PM PDT 24
Peak memory 216208 kb
Host smart-bf970019-5fec-4527-8101-068256a00b18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690625634 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2690625634
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2112563794
Short name T61
Test name
Test status
Simulation time 46283962 ps
CPU time 1.03 seconds
Started Aug 11 06:25:17 PM PDT 24
Finished Aug 11 06:25:18 PM PDT 24
Peak memory 218568 kb
Host smart-32c30f05-4c0b-4874-9c30-d794be21e076
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112563794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2112563794
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.963551643
Short name T927
Test name
Test status
Simulation time 35483710 ps
CPU time 1.27 seconds
Started Aug 11 06:25:13 PM PDT 24
Finished Aug 11 06:25:14 PM PDT 24
Peak memory 225592 kb
Host smart-e975f8f4-cf44-4e80-a317-74d4d0423a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963551643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.963551643
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2089877402
Short name T417
Test name
Test status
Simulation time 60245942 ps
CPU time 1.77 seconds
Started Aug 11 06:25:19 PM PDT 24
Finished Aug 11 06:25:21 PM PDT 24
Peak memory 218468 kb
Host smart-8bee3cc8-1cfe-44b3-b2c0-05620477afdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089877402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2089877402
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2889193505
Short name T55
Test name
Test status
Simulation time 20931308 ps
CPU time 1.17 seconds
Started Aug 11 06:25:20 PM PDT 24
Finished Aug 11 06:25:21 PM PDT 24
Peak memory 224156 kb
Host smart-cf95a17e-84e2-43a9-9244-e84f17771e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889193505 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2889193505
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.666165797
Short name T649
Test name
Test status
Simulation time 65355205 ps
CPU time 0.95 seconds
Started Aug 11 06:25:14 PM PDT 24
Finished Aug 11 06:25:15 PM PDT 24
Peak memory 207092 kb
Host smart-1ff3ea8c-4980-418b-b3bb-d82f3e4a851a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666165797 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.666165797
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.4272212171
Short name T64
Test name
Test status
Simulation time 608729228 ps
CPU time 4.3 seconds
Started Aug 11 06:25:17 PM PDT 24
Finished Aug 11 06:25:21 PM PDT 24
Peak memory 242060 kb
Host smart-e27ebb65-927d-4d7e-9230-e86f9d309bfe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272212171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.4272212171
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2943507343
Short name T341
Test name
Test status
Simulation time 19346192 ps
CPU time 0.99 seconds
Started Aug 11 06:25:14 PM PDT 24
Finished Aug 11 06:25:15 PM PDT 24
Peak memory 215312 kb
Host smart-fdadbd2d-48bc-453c-8c52-a483c4387abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943507343 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2943507343
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2154123352
Short name T50
Test name
Test status
Simulation time 115163551 ps
CPU time 2.89 seconds
Started Aug 11 06:25:13 PM PDT 24
Finished Aug 11 06:25:16 PM PDT 24
Peak memory 215356 kb
Host smart-87dd3714-4313-431c-b53a-74515281f0c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154123352 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2154123352
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3090050659
Short name T232
Test name
Test status
Simulation time 92040872252 ps
CPU time 1235.35 seconds
Started Aug 11 06:25:14 PM PDT 24
Finished Aug 11 06:45:50 PM PDT 24
Peak memory 223160 kb
Host smart-a584023d-9881-4291-84d2-d046426fc6f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090050659 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3090050659
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1145793412
Short name T902
Test name
Test status
Simulation time 37081501 ps
CPU time 1.18 seconds
Started Aug 11 06:26:11 PM PDT 24
Finished Aug 11 06:26:13 PM PDT 24
Peak memory 218344 kb
Host smart-5b63747a-6d2a-49dd-999f-c5ae102ae85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145793412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1145793412
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1558285845
Short name T499
Test name
Test status
Simulation time 10929015 ps
CPU time 0.84 seconds
Started Aug 11 06:26:01 PM PDT 24
Finished Aug 11 06:26:02 PM PDT 24
Peak memory 206872 kb
Host smart-0fadee7f-578f-48fd-abd4-321dee8bc440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558285845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1558285845
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.882138889
Short name T164
Test name
Test status
Simulation time 13767610 ps
CPU time 0.9 seconds
Started Aug 11 06:26:16 PM PDT 24
Finished Aug 11 06:26:17 PM PDT 24
Peak memory 215512 kb
Host smart-9acb62b1-daf4-4c9c-862b-e470d4b8e381
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882138889 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.882138889
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.4181639674
Short name T151
Test name
Test status
Simulation time 29867372 ps
CPU time 1.25 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:26:07 PM PDT 24
Peak memory 217304 kb
Host smart-e13f9021-e75b-4539-b50e-462764b151d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181639674 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.4181639674
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.485699888
Short name T56
Test name
Test status
Simulation time 36451036 ps
CPU time 1.03 seconds
Started Aug 11 06:26:02 PM PDT 24
Finished Aug 11 06:26:04 PM PDT 24
Peak memory 229796 kb
Host smart-d4e61db3-b762-4b1b-8af1-6eb263e565ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485699888 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.485699888
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3497354023
Short name T918
Test name
Test status
Simulation time 65464946 ps
CPU time 1.12 seconds
Started Aug 11 06:26:04 PM PDT 24
Finished Aug 11 06:26:10 PM PDT 24
Peak memory 217320 kb
Host smart-95cd2ad8-26e4-43fd-97d9-dd3216d8fd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497354023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3497354023
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.88862225
Short name T785
Test name
Test status
Simulation time 39238502 ps
CPU time 0.96 seconds
Started Aug 11 06:26:03 PM PDT 24
Finished Aug 11 06:26:05 PM PDT 24
Peak memory 215456 kb
Host smart-6c32b961-5524-4bf0-ac96-7ea8ef350389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88862225 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.88862225
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.354282024
Short name T573
Test name
Test status
Simulation time 16500665 ps
CPU time 0.99 seconds
Started Aug 11 06:26:09 PM PDT 24
Finished Aug 11 06:26:11 PM PDT 24
Peak memory 214992 kb
Host smart-e70ae146-c3df-4312-90ae-7ecb463e4962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354282024 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.354282024
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2170777683
Short name T97
Test name
Test status
Simulation time 893587428 ps
CPU time 4.4 seconds
Started Aug 11 06:26:11 PM PDT 24
Finished Aug 11 06:26:16 PM PDT 24
Peak memory 217340 kb
Host smart-223c89ed-112b-42bb-b2bb-4face4ee67b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170777683 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2170777683
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.150692918
Short name T857
Test name
Test status
Simulation time 44843824018 ps
CPU time 576.03 seconds
Started Aug 11 06:26:20 PM PDT 24
Finished Aug 11 06:35:56 PM PDT 24
Peak memory 217592 kb
Host smart-9a37682b-c9b5-457e-b015-e107ccf8f576
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150692918 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.150692918
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.694381412
Short name T787
Test name
Test status
Simulation time 29435402 ps
CPU time 1.23 seconds
Started Aug 11 06:26:23 PM PDT 24
Finished Aug 11 06:26:25 PM PDT 24
Peak memory 220128 kb
Host smart-d71c4090-63a4-4f0a-b484-da8eaca67e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694381412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.694381412
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.897525416
Short name T343
Test name
Test status
Simulation time 92073907 ps
CPU time 0.79 seconds
Started Aug 11 06:25:59 PM PDT 24
Finished Aug 11 06:26:00 PM PDT 24
Peak memory 206448 kb
Host smart-e0da7d27-35e7-47be-97a0-b084ea2d577a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897525416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.897525416
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.651248480
Short name T22
Test name
Test status
Simulation time 223990826 ps
CPU time 1.06 seconds
Started Aug 11 06:26:13 PM PDT 24
Finished Aug 11 06:26:14 PM PDT 24
Peak memory 219472 kb
Host smart-1c93e33e-f378-488c-991e-ab2a388ad052
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651248480 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.651248480
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2511370709
Short name T147
Test name
Test status
Simulation time 61434178 ps
CPU time 1.03 seconds
Started Aug 11 06:26:16 PM PDT 24
Finished Aug 11 06:26:17 PM PDT 24
Peak memory 220928 kb
Host smart-4c855393-87a4-4640-9a5c-144737f7c979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511370709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2511370709
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.476595074
Short name T511
Test name
Test status
Simulation time 132131516 ps
CPU time 1.07 seconds
Started Aug 11 06:26:02 PM PDT 24
Finished Aug 11 06:26:03 PM PDT 24
Peak memory 217340 kb
Host smart-3a36ad71-7b63-4359-a2ee-b49b87edeee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476595074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.476595074
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.500458042
Short name T18
Test name
Test status
Simulation time 23106744 ps
CPU time 1.25 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:26:06 PM PDT 24
Peak memory 224152 kb
Host smart-eb4e9f57-c27c-4a6f-b4e1-cb2de76d0d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500458042 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.500458042
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.815070666
Short name T788
Test name
Test status
Simulation time 24382781 ps
CPU time 0.9 seconds
Started Aug 11 06:26:11 PM PDT 24
Finished Aug 11 06:26:12 PM PDT 24
Peak memory 215276 kb
Host smart-fb5e10ca-16f7-4c18-89c9-b34e8dea9329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815070666 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.815070666
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.30343527
Short name T561
Test name
Test status
Simulation time 103915040 ps
CPU time 2.62 seconds
Started Aug 11 06:26:04 PM PDT 24
Finished Aug 11 06:26:07 PM PDT 24
Peak memory 215260 kb
Host smart-9ac66378-a6af-4918-afe9-edb31052bf8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30343527 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.30343527
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3837115409
Short name T233
Test name
Test status
Simulation time 47115270303 ps
CPU time 1097.39 seconds
Started Aug 11 06:26:16 PM PDT 24
Finished Aug 11 06:44:34 PM PDT 24
Peak memory 219308 kb
Host smart-6e9142e0-a0c2-4cbd-b489-743b198fec08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837115409 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3837115409
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1914728601
Short name T775
Test name
Test status
Simulation time 92970135 ps
CPU time 1.08 seconds
Started Aug 11 06:26:12 PM PDT 24
Finished Aug 11 06:26:13 PM PDT 24
Peak memory 219780 kb
Host smart-c79945da-7573-45c3-96d7-16db930cb897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914728601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1914728601
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2309331252
Short name T405
Test name
Test status
Simulation time 22593608 ps
CPU time 0.83 seconds
Started Aug 11 06:26:36 PM PDT 24
Finished Aug 11 06:26:37 PM PDT 24
Peak memory 206664 kb
Host smart-4fde8e8c-edd6-4c17-b8cd-412c838c4145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309331252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2309331252
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2902120992
Short name T273
Test name
Test status
Simulation time 52414448 ps
CPU time 0.96 seconds
Started Aug 11 06:26:25 PM PDT 24
Finished Aug 11 06:26:26 PM PDT 24
Peak memory 218500 kb
Host smart-901bd494-408b-481e-bf79-bc576ee5f820
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902120992 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2902120992
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3268297241
Short name T592
Test name
Test status
Simulation time 28456498 ps
CPU time 0.85 seconds
Started Aug 11 06:26:04 PM PDT 24
Finished Aug 11 06:26:05 PM PDT 24
Peak memory 218412 kb
Host smart-10c10228-dc10-4f5e-aa58-38166a064c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268297241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3268297241
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2562085328
Short name T74
Test name
Test status
Simulation time 110066799 ps
CPU time 1.29 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:26:07 PM PDT 24
Peak memory 217316 kb
Host smart-2c97e5cb-26e5-4ec6-87c0-e53a81f5473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562085328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2562085328
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.301318616
Short name T894
Test name
Test status
Simulation time 24934739 ps
CPU time 0.95 seconds
Started Aug 11 06:26:06 PM PDT 24
Finished Aug 11 06:26:07 PM PDT 24
Peak memory 215472 kb
Host smart-243cf0f0-2f6d-4175-b247-12391894935b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301318616 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.301318616
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1094426890
Short name T817
Test name
Test status
Simulation time 30626326 ps
CPU time 1.01 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:26:06 PM PDT 24
Peak memory 215288 kb
Host smart-9da6fad5-5d4d-4396-9a6b-8f631a03d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094426890 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1094426890
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1447549696
Short name T299
Test name
Test status
Simulation time 127803841 ps
CPU time 1.37 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:26:06 PM PDT 24
Peak memory 217408 kb
Host smart-2eb0cbed-5f0b-4428-ac7c-ffab150d6d08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447549696 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1447549696
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.367194204
Short name T231
Test name
Test status
Simulation time 277878442037 ps
CPU time 1695.09 seconds
Started Aug 11 06:26:07 PM PDT 24
Finished Aug 11 06:54:22 PM PDT 24
Peak memory 224128 kb
Host smart-747dd99b-61f5-4200-a503-80e15eec92c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367194204 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.367194204
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1043489740
Short name T689
Test name
Test status
Simulation time 83823312 ps
CPU time 1.2 seconds
Started Aug 11 06:26:06 PM PDT 24
Finished Aug 11 06:26:08 PM PDT 24
Peak memory 219308 kb
Host smart-3351e8d7-14e8-41ee-b148-53d3d844b12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043489740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1043489740
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.694051801
Short name T589
Test name
Test status
Simulation time 22106097 ps
CPU time 0.92 seconds
Started Aug 11 06:26:21 PM PDT 24
Finished Aug 11 06:26:22 PM PDT 24
Peak memory 206852 kb
Host smart-e1cfe2b4-049a-4e35-a15e-f664618bc16a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694051801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.694051801
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3261119054
Short name T898
Test name
Test status
Simulation time 15391089 ps
CPU time 0.86 seconds
Started Aug 11 06:26:26 PM PDT 24
Finished Aug 11 06:26:27 PM PDT 24
Peak memory 216332 kb
Host smart-4d955da7-adb1-4888-9701-54eb172a138a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261119054 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3261119054
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1309398073
Short name T767
Test name
Test status
Simulation time 43869034 ps
CPU time 1 seconds
Started Aug 11 06:26:19 PM PDT 24
Finished Aug 11 06:26:20 PM PDT 24
Peak memory 218340 kb
Host smart-82d03018-6797-4b1f-9be8-254e23fa38eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309398073 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1309398073
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.4073548390
Short name T183
Test name
Test status
Simulation time 33614348 ps
CPU time 0.84 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:26:06 PM PDT 24
Peak memory 218720 kb
Host smart-86ff9402-2db0-49ee-aeaa-ad4e5981b6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073548390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.4073548390
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.274678316
Short name T321
Test name
Test status
Simulation time 80401095 ps
CPU time 1.35 seconds
Started Aug 11 06:26:15 PM PDT 24
Finished Aug 11 06:26:16 PM PDT 24
Peak memory 219080 kb
Host smart-c4e785e0-7988-4a4e-9291-334f941d0864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274678316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.274678316
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3216963948
Short name T503
Test name
Test status
Simulation time 25766967 ps
CPU time 1.06 seconds
Started Aug 11 06:26:23 PM PDT 24
Finished Aug 11 06:26:24 PM PDT 24
Peak memory 224236 kb
Host smart-bc5da708-04ee-4d1c-838b-45f8d5bc977a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216963948 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3216963948
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.752201409
Short name T424
Test name
Test status
Simulation time 65284030 ps
CPU time 0.91 seconds
Started Aug 11 06:26:29 PM PDT 24
Finished Aug 11 06:26:30 PM PDT 24
Peak memory 215312 kb
Host smart-0d5df8d7-1143-448e-9a2c-3aef6ed5afac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752201409 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.752201409
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.313792637
Short name T246
Test name
Test status
Simulation time 718519861 ps
CPU time 4.01 seconds
Started Aug 11 06:26:28 PM PDT 24
Finished Aug 11 06:26:32 PM PDT 24
Peak memory 215164 kb
Host smart-3564cee7-b595-4857-a7ad-b46683d7786c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313792637 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.313792637
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1794979344
Short name T816
Test name
Test status
Simulation time 107705846756 ps
CPU time 1661.43 seconds
Started Aug 11 06:26:28 PM PDT 24
Finished Aug 11 06:54:09 PM PDT 24
Peak memory 226564 kb
Host smart-aebdb415-27f7-4fc2-8a67-3612a9209775
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794979344 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1794979344
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3025992462
Short name T129
Test name
Test status
Simulation time 27066412 ps
CPU time 1.26 seconds
Started Aug 11 06:26:16 PM PDT 24
Finished Aug 11 06:26:18 PM PDT 24
Peak memory 218544 kb
Host smart-ab54ca0d-bd9c-46fa-a5c5-6effd2dd7a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025992462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3025992462
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3380801491
Short name T474
Test name
Test status
Simulation time 68955645 ps
CPU time 1.01 seconds
Started Aug 11 06:26:34 PM PDT 24
Finished Aug 11 06:26:35 PM PDT 24
Peak memory 215208 kb
Host smart-b1850d56-b025-4b03-b09d-23b28150ff8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380801491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3380801491
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3901143135
Short name T443
Test name
Test status
Simulation time 47716438 ps
CPU time 0.84 seconds
Started Aug 11 06:26:07 PM PDT 24
Finished Aug 11 06:26:08 PM PDT 24
Peak memory 216376 kb
Host smart-9f2b47ac-e373-4308-812d-b5e7a3f11daa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901143135 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3901143135
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1608421356
Short name T140
Test name
Test status
Simulation time 43330891 ps
CPU time 1.03 seconds
Started Aug 11 06:26:08 PM PDT 24
Finished Aug 11 06:26:09 PM PDT 24
Peak memory 218588 kb
Host smart-a4bd07b5-21ef-4978-9543-ae58b443b8ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608421356 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1608421356
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1919894935
Short name T640
Test name
Test status
Simulation time 22575407 ps
CPU time 1.11 seconds
Started Aug 11 06:26:08 PM PDT 24
Finished Aug 11 06:26:09 PM PDT 24
Peak memory 221012 kb
Host smart-e577497b-7fd1-4bfd-a1cb-99644de88a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919894935 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1919894935
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.919862839
Short name T13
Test name
Test status
Simulation time 102177727 ps
CPU time 1.28 seconds
Started Aug 11 06:26:39 PM PDT 24
Finished Aug 11 06:26:40 PM PDT 24
Peak memory 220072 kb
Host smart-abb1575c-6dcb-4878-b793-0ec12b25ee7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919862839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.919862839
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1077465719
Short name T91
Test name
Test status
Simulation time 52364065 ps
CPU time 0.86 seconds
Started Aug 11 06:26:17 PM PDT 24
Finished Aug 11 06:26:17 PM PDT 24
Peak memory 215500 kb
Host smart-40164039-dd66-43c4-b317-1493476efee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077465719 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1077465719
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.4143518080
Short name T571
Test name
Test status
Simulation time 28676997 ps
CPU time 0.94 seconds
Started Aug 11 06:26:19 PM PDT 24
Finished Aug 11 06:26:20 PM PDT 24
Peak memory 215296 kb
Host smart-678674a5-bb84-4d34-bf23-357cb27376dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143518080 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.4143518080
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3893058231
Short name T546
Test name
Test status
Simulation time 356858497 ps
CPU time 3.97 seconds
Started Aug 11 06:26:24 PM PDT 24
Finished Aug 11 06:26:28 PM PDT 24
Peak memory 217180 kb
Host smart-595063f3-dc50-46a5-8a16-0d1548e837fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893058231 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3893058231
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1289436925
Short name T834
Test name
Test status
Simulation time 496445581831 ps
CPU time 1703.27 seconds
Started Aug 11 06:26:33 PM PDT 24
Finished Aug 11 06:54:57 PM PDT 24
Peak memory 224760 kb
Host smart-485f5861-3418-4914-a980-4623d92a4687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289436925 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1289436925
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.439659309
Short name T186
Test name
Test status
Simulation time 22795804 ps
CPU time 1.12 seconds
Started Aug 11 06:26:28 PM PDT 24
Finished Aug 11 06:26:29 PM PDT 24
Peak memory 218380 kb
Host smart-6c2e1ed6-3b63-4b69-b43f-f147c8a8340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439659309 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.439659309
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1574198026
Short name T62
Test name
Test status
Simulation time 48463995 ps
CPU time 0.88 seconds
Started Aug 11 06:26:29 PM PDT 24
Finished Aug 11 06:26:30 PM PDT 24
Peak memory 215028 kb
Host smart-38cb9bd1-7718-4587-b966-b072de9d94ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574198026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1574198026
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1911452311
Short name T804
Test name
Test status
Simulation time 58179984 ps
CPU time 0.84 seconds
Started Aug 11 06:26:18 PM PDT 24
Finished Aug 11 06:26:19 PM PDT 24
Peak memory 216500 kb
Host smart-5bdf46be-9885-4ad3-820b-525d8cf802e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911452311 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1911452311
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1146445794
Short name T714
Test name
Test status
Simulation time 42232851 ps
CPU time 1.29 seconds
Started Aug 11 06:26:17 PM PDT 24
Finished Aug 11 06:26:18 PM PDT 24
Peak memory 217040 kb
Host smart-7eef117e-b3e6-4a5a-9bfc-202585d78912
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146445794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1146445794
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1733000716
Short name T67
Test name
Test status
Simulation time 18927769 ps
CPU time 1.07 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:26:06 PM PDT 24
Peak memory 218744 kb
Host smart-446e0d81-9a49-49ab-b971-b934a1c8831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733000716 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1733000716
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2501297569
Short name T390
Test name
Test status
Simulation time 51077066 ps
CPU time 1.54 seconds
Started Aug 11 06:26:12 PM PDT 24
Finished Aug 11 06:26:14 PM PDT 24
Peak memory 218516 kb
Host smart-c94fa8c5-eca7-4ddc-84ff-0a85650327c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501297569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2501297569
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2485827266
Short name T68
Test name
Test status
Simulation time 69011917 ps
CPU time 0.83 seconds
Started Aug 11 06:26:15 PM PDT 24
Finished Aug 11 06:26:16 PM PDT 24
Peak memory 215388 kb
Host smart-38cec56a-15a7-4864-8090-a498f5a3bda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485827266 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2485827266
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2651354027
Short name T354
Test name
Test status
Simulation time 22976593 ps
CPU time 0.88 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:26:06 PM PDT 24
Peak memory 215304 kb
Host smart-b3e13f00-8fb3-4de2-8663-cb411773df90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651354027 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2651354027
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.333314010
Short name T744
Test name
Test status
Simulation time 558443029 ps
CPU time 2.3 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:26:07 PM PDT 24
Peak memory 217328 kb
Host smart-87dcd244-4b3d-497d-9668-0ee4c391a1bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333314010 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.333314010
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.4030532318
Short name T555
Test name
Test status
Simulation time 112107987943 ps
CPU time 602.6 seconds
Started Aug 11 06:26:06 PM PDT 24
Finished Aug 11 06:36:09 PM PDT 24
Peak memory 223568 kb
Host smart-d3157621-8966-404f-8fc3-939ee2737212
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030532318 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.4030532318
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3964115037
Short name T403
Test name
Test status
Simulation time 46393966 ps
CPU time 1.11 seconds
Started Aug 11 06:26:18 PM PDT 24
Finished Aug 11 06:26:19 PM PDT 24
Peak memory 218584 kb
Host smart-9ae8f17c-845e-4147-afdd-e37743a4e36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964115037 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3964115037
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1441999293
Short name T779
Test name
Test status
Simulation time 49547533 ps
CPU time 0.82 seconds
Started Aug 11 06:26:16 PM PDT 24
Finished Aug 11 06:26:17 PM PDT 24
Peak memory 206764 kb
Host smart-7c9677c7-d0b2-477a-a0be-8a26e133a38f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441999293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1441999293
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.458040292
Short name T215
Test name
Test status
Simulation time 31936709 ps
CPU time 0.83 seconds
Started Aug 11 06:26:12 PM PDT 24
Finished Aug 11 06:26:13 PM PDT 24
Peak memory 216568 kb
Host smart-6b68ff16-a1b8-4a82-bb2e-d97ed570988f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458040292 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.458040292
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1286837039
Short name T126
Test name
Test status
Simulation time 109545803 ps
CPU time 1.27 seconds
Started Aug 11 06:26:26 PM PDT 24
Finished Aug 11 06:26:27 PM PDT 24
Peak memory 217308 kb
Host smart-546f08c3-3dfc-49fa-bca4-3c9c5dc0f7e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286837039 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1286837039
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.50811448
Short name T116
Test name
Test status
Simulation time 63647894 ps
CPU time 1.04 seconds
Started Aug 11 06:26:19 PM PDT 24
Finished Aug 11 06:26:20 PM PDT 24
Peak memory 219968 kb
Host smart-e8d74a58-4cbe-4007-9cf7-9390722c920e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50811448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.50811448
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1601927132
Short name T430
Test name
Test status
Simulation time 85661996 ps
CPU time 1.06 seconds
Started Aug 11 06:26:25 PM PDT 24
Finished Aug 11 06:26:26 PM PDT 24
Peak memory 217284 kb
Host smart-332d3bf0-b452-47c8-84b2-6992b158d6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601927132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1601927132
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.436997907
Short name T565
Test name
Test status
Simulation time 20971938 ps
CPU time 1.16 seconds
Started Aug 11 06:26:23 PM PDT 24
Finished Aug 11 06:26:25 PM PDT 24
Peak memory 224156 kb
Host smart-ece91608-469a-4893-9105-e8f2cf967a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436997907 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.436997907
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3943861424
Short name T505
Test name
Test status
Simulation time 20284085 ps
CPU time 1.04 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:26:06 PM PDT 24
Peak memory 215268 kb
Host smart-f983564c-2f10-4ba5-a346-27c6a58de29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943861424 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3943861424
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2563336152
Short name T757
Test name
Test status
Simulation time 210022160 ps
CPU time 4.23 seconds
Started Aug 11 06:26:26 PM PDT 24
Finished Aug 11 06:26:30 PM PDT 24
Peak memory 217356 kb
Host smart-d473e892-7f56-44e1-b116-43aaba4f53c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563336152 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2563336152
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4154981439
Short name T709
Test name
Test status
Simulation time 180903324024 ps
CPU time 1042.68 seconds
Started Aug 11 06:26:28 PM PDT 24
Finished Aug 11 06:43:51 PM PDT 24
Peak memory 223584 kb
Host smart-ce645de4-f423-4e8e-af76-1ad7e4b74e2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154981439 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.4154981439
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3568044886
Short name T722
Test name
Test status
Simulation time 25470281 ps
CPU time 1.22 seconds
Started Aug 11 06:26:25 PM PDT 24
Finished Aug 11 06:26:26 PM PDT 24
Peak memory 219620 kb
Host smart-ccab87b4-cd06-41d6-b13d-3c56a8ba56e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568044886 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3568044886
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1981547562
Short name T906
Test name
Test status
Simulation time 46907738 ps
CPU time 0.89 seconds
Started Aug 11 06:26:04 PM PDT 24
Finished Aug 11 06:26:05 PM PDT 24
Peak memory 206820 kb
Host smart-c1480c5a-3ad6-4722-8e6d-a49215558419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981547562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1981547562
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3362709212
Short name T741
Test name
Test status
Simulation time 28346238 ps
CPU time 0.9 seconds
Started Aug 11 06:26:11 PM PDT 24
Finished Aug 11 06:26:12 PM PDT 24
Peak memory 215520 kb
Host smart-1c305b43-bee2-41c1-b533-00b7afbdd5b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362709212 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3362709212
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.846907027
Short name T209
Test name
Test status
Simulation time 50792217 ps
CPU time 1.08 seconds
Started Aug 11 06:26:05 PM PDT 24
Finished Aug 11 06:26:12 PM PDT 24
Peak memory 219460 kb
Host smart-7dae9917-0d0a-4010-ae66-ab5beba92302
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846907027 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.846907027
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_genbits.4210651766
Short name T802
Test name
Test status
Simulation time 60414381 ps
CPU time 0.98 seconds
Started Aug 11 06:26:11 PM PDT 24
Finished Aug 11 06:26:12 PM PDT 24
Peak memory 217548 kb
Host smart-cee6e018-2297-496e-8d33-4ba5a38e9f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210651766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.4210651766
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2215161490
Short name T969
Test name
Test status
Simulation time 24359805 ps
CPU time 1.01 seconds
Started Aug 11 06:26:11 PM PDT 24
Finished Aug 11 06:26:12 PM PDT 24
Peak memory 215348 kb
Host smart-9b117ab3-8f37-47dd-bac3-350587c3577a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215161490 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2215161490
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.221277714
Short name T691
Test name
Test status
Simulation time 23149070 ps
CPU time 0.87 seconds
Started Aug 11 06:26:19 PM PDT 24
Finished Aug 11 06:26:20 PM PDT 24
Peak memory 215304 kb
Host smart-0433528e-ae9a-4e46-9254-c6fd41ef5615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221277714 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.221277714
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1434812450
Short name T446
Test name
Test status
Simulation time 633021417 ps
CPU time 2.99 seconds
Started Aug 11 06:26:15 PM PDT 24
Finished Aug 11 06:26:18 PM PDT 24
Peak memory 215284 kb
Host smart-61c50174-aa96-44f3-a852-1829548b00ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434812450 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1434812450
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2158961593
Short name T952
Test name
Test status
Simulation time 299720405519 ps
CPU time 1052.4 seconds
Started Aug 11 06:26:26 PM PDT 24
Finished Aug 11 06:43:59 PM PDT 24
Peak memory 222832 kb
Host smart-29d69e22-7593-413e-a9e8-a399360b413b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158961593 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2158961593
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1971712739
Short name T160
Test name
Test status
Simulation time 22804048 ps
CPU time 1.18 seconds
Started Aug 11 06:26:20 PM PDT 24
Finished Aug 11 06:26:21 PM PDT 24
Peak memory 219188 kb
Host smart-0711bae0-0240-4ea4-b257-bdeb0142ef52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971712739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1971712739
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.886116545
Short name T763
Test name
Test status
Simulation time 26026578 ps
CPU time 0.95 seconds
Started Aug 11 06:26:13 PM PDT 24
Finished Aug 11 06:26:14 PM PDT 24
Peak memory 215220 kb
Host smart-c8223394-133c-4b9b-9b66-a5ade870d5ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886116545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.886116545
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1730219892
Short name T545
Test name
Test status
Simulation time 104908696 ps
CPU time 1.18 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 215496 kb
Host smart-e7a5186a-0562-44e2-8e3e-f2178510b699
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730219892 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1730219892
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1526434785
Short name T806
Test name
Test status
Simulation time 28195239 ps
CPU time 1.06 seconds
Started Aug 11 06:26:33 PM PDT 24
Finished Aug 11 06:26:35 PM PDT 24
Peak memory 218688 kb
Host smart-7de026c7-8f22-47fa-8025-2c4980923a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526434785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1526434785
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.833836294
Short name T813
Test name
Test status
Simulation time 92104011 ps
CPU time 1.28 seconds
Started Aug 11 06:26:28 PM PDT 24
Finished Aug 11 06:26:30 PM PDT 24
Peak memory 217352 kb
Host smart-bd824ddb-91f6-4739-a688-401128176f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833836294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.833836294
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3112127878
Short name T52
Test name
Test status
Simulation time 29322415 ps
CPU time 1.08 seconds
Started Aug 11 06:26:25 PM PDT 24
Finished Aug 11 06:26:26 PM PDT 24
Peak memory 224284 kb
Host smart-83e91ebc-9d91-4fc8-8527-ede578c9332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112127878 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3112127878
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3508109076
Short name T496
Test name
Test status
Simulation time 50284977 ps
CPU time 0.97 seconds
Started Aug 11 06:26:26 PM PDT 24
Finished Aug 11 06:26:27 PM PDT 24
Peak memory 215276 kb
Host smart-99bab0e2-4259-469a-bba0-fde59e4b1995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508109076 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3508109076
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.4154290223
Short name T525
Test name
Test status
Simulation time 875245725 ps
CPU time 4.69 seconds
Started Aug 11 06:26:18 PM PDT 24
Finished Aug 11 06:26:22 PM PDT 24
Peak memory 217332 kb
Host smart-972af27e-9ce8-470c-897f-e568af082383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154290223 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4154290223
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3212617251
Short name T38
Test name
Test status
Simulation time 60539190714 ps
CPU time 287.37 seconds
Started Aug 11 06:26:23 PM PDT 24
Finished Aug 11 06:31:11 PM PDT 24
Peak memory 223684 kb
Host smart-ee013113-7b79-48b0-92e6-2ea7f5238743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212617251 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3212617251
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3842336605
Short name T3
Test name
Test status
Simulation time 25795587 ps
CPU time 1.23 seconds
Started Aug 11 06:26:26 PM PDT 24
Finished Aug 11 06:26:27 PM PDT 24
Peak memory 220920 kb
Host smart-7c59f8e2-d59a-4d8e-be7b-c1ba9a8f511a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842336605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3842336605
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.238935710
Short name T63
Test name
Test status
Simulation time 35817980 ps
CPU time 0.91 seconds
Started Aug 11 06:26:27 PM PDT 24
Finished Aug 11 06:26:28 PM PDT 24
Peak memory 206796 kb
Host smart-6210c23c-7f9b-4606-b563-7faa0ee842cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238935710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.238935710
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1640057526
Short name T127
Test name
Test status
Simulation time 70117887 ps
CPU time 1.34 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:42 PM PDT 24
Peak memory 219580 kb
Host smart-bff2457f-0597-4575-8f87-ebd6799d45f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640057526 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1640057526
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.852994498
Short name T132
Test name
Test status
Simulation time 43325035 ps
CPU time 1.13 seconds
Started Aug 11 06:26:21 PM PDT 24
Finished Aug 11 06:26:22 PM PDT 24
Peak memory 220752 kb
Host smart-06964a42-5ed1-40b5-bbda-709cb33fb561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852994498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.852994498
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.263217578
Short name T90
Test name
Test status
Simulation time 190318141 ps
CPU time 1.58 seconds
Started Aug 11 06:26:28 PM PDT 24
Finished Aug 11 06:26:30 PM PDT 24
Peak memory 219084 kb
Host smart-c89c60fc-4870-420b-86a0-dbce2c7b0f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263217578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.263217578
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.4290243709
Short name T33
Test name
Test status
Simulation time 23452190 ps
CPU time 0.93 seconds
Started Aug 11 06:26:29 PM PDT 24
Finished Aug 11 06:26:31 PM PDT 24
Peak memory 216076 kb
Host smart-17b8bcd6-c178-45fb-b633-668bd98f247c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290243709 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.4290243709
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.464670612
Short name T701
Test name
Test status
Simulation time 53195203 ps
CPU time 0.95 seconds
Started Aug 11 06:26:13 PM PDT 24
Finished Aug 11 06:26:14 PM PDT 24
Peak memory 215304 kb
Host smart-0a2943d9-b63c-4d6e-8847-eff5c1082f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464670612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.464670612
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3504013028
Short name T835
Test name
Test status
Simulation time 533714765 ps
CPU time 5.51 seconds
Started Aug 11 06:26:16 PM PDT 24
Finished Aug 11 06:26:22 PM PDT 24
Peak memory 220040 kb
Host smart-22f538cc-7f33-4646-bc4b-17e5020c3700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504013028 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3504013028
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1839190707
Short name T713
Test name
Test status
Simulation time 213402376066 ps
CPU time 1373.32 seconds
Started Aug 11 06:26:32 PM PDT 24
Finished Aug 11 06:49:25 PM PDT 24
Peak memory 225224 kb
Host smart-1e122c71-efd8-4d71-903a-bbba5ceca7f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839190707 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1839190707
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3966967111
Short name T131
Test name
Test status
Simulation time 25513983 ps
CPU time 1.21 seconds
Started Aug 11 06:25:18 PM PDT 24
Finished Aug 11 06:25:19 PM PDT 24
Peak memory 218720 kb
Host smart-b38f0fea-ec99-4a3c-8ac3-74d7799ba04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966967111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3966967111
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2827579399
Short name T361
Test name
Test status
Simulation time 35712734 ps
CPU time 0.96 seconds
Started Aug 11 06:25:21 PM PDT 24
Finished Aug 11 06:25:22 PM PDT 24
Peak memory 215212 kb
Host smart-7a16dadb-a52e-4092-9610-9be96b806ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827579399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2827579399
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3929583510
Short name T328
Test name
Test status
Simulation time 39356260 ps
CPU time 0.87 seconds
Started Aug 11 06:25:21 PM PDT 24
Finished Aug 11 06:25:22 PM PDT 24
Peak memory 216360 kb
Host smart-2300c148-98bd-4988-a8d0-6dd37e136f49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929583510 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3929583510
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2709305115
Short name T272
Test name
Test status
Simulation time 70361069 ps
CPU time 1 seconds
Started Aug 11 06:25:21 PM PDT 24
Finished Aug 11 06:25:22 PM PDT 24
Peak memory 219372 kb
Host smart-25fe76ff-dfd0-4874-9d11-a1284127ff0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709305115 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2709305115
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3129469411
Short name T219
Test name
Test status
Simulation time 21531230 ps
CPU time 0.93 seconds
Started Aug 11 06:25:18 PM PDT 24
Finished Aug 11 06:25:19 PM PDT 24
Peak memory 218940 kb
Host smart-76efdc4f-bab1-4d7f-99ef-313b4f280aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129469411 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3129469411
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3313739644
Short name T60
Test name
Test status
Simulation time 42527692 ps
CPU time 1.47 seconds
Started Aug 11 06:25:16 PM PDT 24
Finished Aug 11 06:25:18 PM PDT 24
Peak memory 218384 kb
Host smart-4f6fae9f-5526-4f7f-86f3-d52d93df74fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313739644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3313739644
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2453600269
Short name T520
Test name
Test status
Simulation time 32289715 ps
CPU time 0.96 seconds
Started Aug 11 06:25:19 PM PDT 24
Finished Aug 11 06:25:20 PM PDT 24
Peak memory 224160 kb
Host smart-e3b7e1d5-2b9f-461e-8f70-d8aec9e79a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453600269 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2453600269
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1796835966
Short name T696
Test name
Test status
Simulation time 29902668 ps
CPU time 0.95 seconds
Started Aug 11 06:25:19 PM PDT 24
Finished Aug 11 06:25:20 PM PDT 24
Peak memory 207104 kb
Host smart-ef8826f4-f4c6-42cf-9157-f4792a8f67e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796835966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1796835966
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3334522649
Short name T409
Test name
Test status
Simulation time 42497246 ps
CPU time 1 seconds
Started Aug 11 06:25:19 PM PDT 24
Finished Aug 11 06:25:20 PM PDT 24
Peak memory 215304 kb
Host smart-9821fd89-b664-4591-b33a-14d3c17224f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334522649 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3334522649
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2326207886
Short name T540
Test name
Test status
Simulation time 687844231 ps
CPU time 4.61 seconds
Started Aug 11 06:25:22 PM PDT 24
Finished Aug 11 06:25:26 PM PDT 24
Peak memory 219812 kb
Host smart-0c1a8e41-15e9-48d3-94ed-5afd3b9f9de3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326207886 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2326207886
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/50.edn_alert.1965934469
Short name T760
Test name
Test status
Simulation time 27621628 ps
CPU time 1.26 seconds
Started Aug 11 06:26:32 PM PDT 24
Finished Aug 11 06:26:33 PM PDT 24
Peak memory 220580 kb
Host smart-68e5f872-4d31-4804-85c5-038fc1a4f3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965934469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.1965934469
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1028889544
Short name T892
Test name
Test status
Simulation time 19305346 ps
CPU time 1.14 seconds
Started Aug 11 06:26:18 PM PDT 24
Finished Aug 11 06:26:19 PM PDT 24
Peak memory 224144 kb
Host smart-b75cb832-e1ce-4dd0-b72b-474f7c0bbf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028889544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1028889544
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.443918816
Short name T619
Test name
Test status
Simulation time 196778185 ps
CPU time 1.22 seconds
Started Aug 11 06:26:32 PM PDT 24
Finished Aug 11 06:26:34 PM PDT 24
Peak memory 219188 kb
Host smart-d7d294ec-f196-46cc-a7d0-3bb0f44af7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443918816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.443918816
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2332509428
Short name T601
Test name
Test status
Simulation time 28622633 ps
CPU time 1.32 seconds
Started Aug 11 06:26:25 PM PDT 24
Finished Aug 11 06:26:27 PM PDT 24
Peak memory 215540 kb
Host smart-04195799-b0b3-40ef-b5a4-35856c01c6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332509428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2332509428
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.118849360
Short name T17
Test name
Test status
Simulation time 39442549 ps
CPU time 1.18 seconds
Started Aug 11 06:26:18 PM PDT 24
Finished Aug 11 06:26:19 PM PDT 24
Peak memory 225892 kb
Host smart-41e8e721-e337-4ba3-a329-6ebed7b0c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118849360 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.118849360
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2731426522
Short name T542
Test name
Test status
Simulation time 59206931 ps
CPU time 1.34 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 217288 kb
Host smart-00b393e6-482f-49f0-80db-7f47b7b4e8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731426522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2731426522
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3328987526
Short name T725
Test name
Test status
Simulation time 40101042 ps
CPU time 1.11 seconds
Started Aug 11 06:26:12 PM PDT 24
Finished Aug 11 06:26:14 PM PDT 24
Peak memory 219360 kb
Host smart-b1b7db9b-0385-4c9d-945a-d32edd1507be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328987526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3328987526
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.1855551556
Short name T134
Test name
Test status
Simulation time 50919780 ps
CPU time 1.05 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 219748 kb
Host smart-0a0c8e52-c696-4bc8-a805-06be0c084db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855551556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1855551556
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3228252898
Short name T10
Test name
Test status
Simulation time 42213493 ps
CPU time 1.54 seconds
Started Aug 11 06:26:27 PM PDT 24
Finished Aug 11 06:26:29 PM PDT 24
Peak memory 220020 kb
Host smart-86481a1c-178a-4ea5-8729-1210924960cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228252898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3228252898
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.276125508
Short name T331
Test name
Test status
Simulation time 92258772 ps
CPU time 1.23 seconds
Started Aug 11 06:26:16 PM PDT 24
Finished Aug 11 06:26:17 PM PDT 24
Peak memory 218660 kb
Host smart-35115c21-c71a-45da-9a64-8234989b4ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276125508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.276125508
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.1298361970
Short name T798
Test name
Test status
Simulation time 21129166 ps
CPU time 1.15 seconds
Started Aug 11 06:26:26 PM PDT 24
Finished Aug 11 06:26:27 PM PDT 24
Peak memory 219968 kb
Host smart-dde3813c-4336-4217-9762-7488ff17f0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298361970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1298361970
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3315271297
Short name T506
Test name
Test status
Simulation time 94364354 ps
CPU time 1.17 seconds
Started Aug 11 06:26:30 PM PDT 24
Finished Aug 11 06:26:31 PM PDT 24
Peak memory 220324 kb
Host smart-22ea1f8a-0c24-4a35-8f2a-0d799fb5f0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315271297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3315271297
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2508164326
Short name T595
Test name
Test status
Simulation time 60061572 ps
CPU time 1.25 seconds
Started Aug 11 06:26:16 PM PDT 24
Finished Aug 11 06:26:18 PM PDT 24
Peak memory 215516 kb
Host smart-351ac0e2-8d78-4be7-a1fc-613852ac839b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508164326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2508164326
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2244354965
Short name T849
Test name
Test status
Simulation time 28332759 ps
CPU time 0.94 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 223920 kb
Host smart-801aed30-cc3b-46bd-84a8-4d9c8a33b04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244354965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2244354965
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.785636288
Short name T404
Test name
Test status
Simulation time 153211179 ps
CPU time 1.94 seconds
Started Aug 11 06:26:31 PM PDT 24
Finished Aug 11 06:26:33 PM PDT 24
Peak memory 220404 kb
Host smart-c82e639e-40e0-4a2b-a2ac-f6ba96253823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785636288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.785636288
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.3982145711
Short name T716
Test name
Test status
Simulation time 43916918 ps
CPU time 1.17 seconds
Started Aug 11 06:26:40 PM PDT 24
Finished Aug 11 06:26:41 PM PDT 24
Peak memory 218632 kb
Host smart-fbe95771-b446-45bb-a2e1-3702edecb8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982145711 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.3982145711
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2734149605
Short name T207
Test name
Test status
Simulation time 18088319 ps
CPU time 1.06 seconds
Started Aug 11 06:26:34 PM PDT 24
Finished Aug 11 06:26:35 PM PDT 24
Peak memory 218724 kb
Host smart-7df6c94e-1265-4774-9a7f-cbdb22f4a1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734149605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2734149605
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3483041096
Short name T308
Test name
Test status
Simulation time 189243279 ps
CPU time 1.41 seconds
Started Aug 11 06:26:30 PM PDT 24
Finished Aug 11 06:26:31 PM PDT 24
Peak memory 219004 kb
Host smart-4ebc5d4f-0fab-4fdc-8747-d57524dbfe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483041096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3483041096
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2481251548
Short name T809
Test name
Test status
Simulation time 44865747 ps
CPU time 1.17 seconds
Started Aug 11 06:26:31 PM PDT 24
Finished Aug 11 06:26:32 PM PDT 24
Peak memory 220028 kb
Host smart-521677ec-0a91-496f-a221-2f47b4b41ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481251548 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2481251548
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.3838973383
Short name T680
Test name
Test status
Simulation time 24795334 ps
CPU time 1.18 seconds
Started Aug 11 06:26:30 PM PDT 24
Finished Aug 11 06:26:31 PM PDT 24
Peak memory 219068 kb
Host smart-dc78a367-92a4-4688-8f9f-e0d35160fa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838973383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3838973383
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.858196996
Short name T549
Test name
Test status
Simulation time 72093320 ps
CPU time 1.12 seconds
Started Aug 11 06:26:34 PM PDT 24
Finished Aug 11 06:26:35 PM PDT 24
Peak memory 217420 kb
Host smart-e211b2c6-d9a3-464a-9139-ed9658ba29d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858196996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.858196996
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2328545497
Short name T587
Test name
Test status
Simulation time 28620569 ps
CPU time 1.2 seconds
Started Aug 11 06:26:40 PM PDT 24
Finished Aug 11 06:26:41 PM PDT 24
Peak memory 219856 kb
Host smart-33cd4a1c-d6b6-4da2-a930-bf16de4d9f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328545497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2328545497
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.410870338
Short name T487
Test name
Test status
Simulation time 21043166 ps
CPU time 0.94 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 218576 kb
Host smart-ab709daf-53ee-4e1b-bddb-fb8e22be3dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410870338 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.410870338
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2300510267
Short name T393
Test name
Test status
Simulation time 93855347 ps
CPU time 1.55 seconds
Started Aug 11 06:26:35 PM PDT 24
Finished Aug 11 06:26:37 PM PDT 24
Peak memory 219108 kb
Host smart-7f9b2414-01cf-4141-a276-93e78b99e03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300510267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2300510267
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.729066881
Short name T910
Test name
Test status
Simulation time 52974907 ps
CPU time 1.28 seconds
Started Aug 11 06:26:24 PM PDT 24
Finished Aug 11 06:26:25 PM PDT 24
Peak memory 215552 kb
Host smart-d674ce8d-2722-4a0c-a55e-32973a173eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729066881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.729066881
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3719815025
Short name T163
Test name
Test status
Simulation time 64435754 ps
CPU time 1.06 seconds
Started Aug 11 06:26:25 PM PDT 24
Finished Aug 11 06:26:27 PM PDT 24
Peak memory 215348 kb
Host smart-65e83a52-9858-412d-b5ec-c5ed8535bd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719815025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3719815025
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.458919894
Short name T346
Test name
Test status
Simulation time 28590261 ps
CPU time 1.21 seconds
Started Aug 11 06:26:30 PM PDT 24
Finished Aug 11 06:26:32 PM PDT 24
Peak memory 219952 kb
Host smart-bce0f7a1-cc43-4315-a650-4319c86fef6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458919894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.458919894
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.100394666
Short name T647
Test name
Test status
Simulation time 275443937 ps
CPU time 1.15 seconds
Started Aug 11 06:26:28 PM PDT 24
Finished Aug 11 06:26:30 PM PDT 24
Peak memory 218796 kb
Host smart-53b789b2-2806-4373-9c23-0407ff412e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100394666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.100394666
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3012894852
Short name T471
Test name
Test status
Simulation time 51337361 ps
CPU time 1.01 seconds
Started Aug 11 06:26:34 PM PDT 24
Finished Aug 11 06:26:35 PM PDT 24
Peak memory 219964 kb
Host smart-b34143fa-66c3-4037-b5a5-fc2e4b1db8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012894852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3012894852
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3772594099
Short name T958
Test name
Test status
Simulation time 67502633 ps
CPU time 1.48 seconds
Started Aug 11 06:26:24 PM PDT 24
Finished Aug 11 06:26:26 PM PDT 24
Peak memory 219852 kb
Host smart-65426581-b180-4547-babb-41909fb1b830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772594099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3772594099
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1787260469
Short name T799
Test name
Test status
Simulation time 40720160 ps
CPU time 1.26 seconds
Started Aug 11 06:25:19 PM PDT 24
Finished Aug 11 06:25:20 PM PDT 24
Peak memory 218668 kb
Host smart-cb4857f7-1488-4c31-81a8-27e5c402be87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787260469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1787260469
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3425632326
Short name T382
Test name
Test status
Simulation time 46840619 ps
CPU time 0.92 seconds
Started Aug 11 06:25:20 PM PDT 24
Finished Aug 11 06:25:21 PM PDT 24
Peak memory 215196 kb
Host smart-e21a0a4f-e2f3-43af-9762-aa322e416ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425632326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3425632326
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2611417131
Short name T179
Test name
Test status
Simulation time 60704355 ps
CPU time 0.84 seconds
Started Aug 11 06:25:22 PM PDT 24
Finished Aug 11 06:25:23 PM PDT 24
Peak memory 218268 kb
Host smart-3043d9c4-bd5c-45a6-b83d-dbd002eb806f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611417131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2611417131
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2154664291
Short name T457
Test name
Test status
Simulation time 87242552 ps
CPU time 1.16 seconds
Started Aug 11 06:25:19 PM PDT 24
Finished Aug 11 06:25:21 PM PDT 24
Peak memory 217004 kb
Host smart-b56aaf40-2972-45c6-875f-bc55d331eabc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154664291 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2154664291
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2162430638
Short name T171
Test name
Test status
Simulation time 19574453 ps
CPU time 1.2 seconds
Started Aug 11 06:25:28 PM PDT 24
Finished Aug 11 06:25:30 PM PDT 24
Peak memory 224164 kb
Host smart-bf8e3aa6-7f06-49b0-8729-a7f81b1e71ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162430638 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2162430638
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.4220396263
Short name T618
Test name
Test status
Simulation time 43148062 ps
CPU time 1.16 seconds
Started Aug 11 06:25:17 PM PDT 24
Finished Aug 11 06:25:19 PM PDT 24
Peak memory 218900 kb
Host smart-be9ad567-2566-4886-9747-3f72b4a8f05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220396263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.4220396263
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.329042188
Short name T919
Test name
Test status
Simulation time 34090991 ps
CPU time 0.86 seconds
Started Aug 11 06:25:18 PM PDT 24
Finished Aug 11 06:25:19 PM PDT 24
Peak memory 215732 kb
Host smart-5fcb2e07-f522-4c4a-b6a6-e94562795c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329042188 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.329042188
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1013926726
Short name T441
Test name
Test status
Simulation time 15771436 ps
CPU time 0.97 seconds
Started Aug 11 06:25:20 PM PDT 24
Finished Aug 11 06:25:21 PM PDT 24
Peak memory 207120 kb
Host smart-30659c66-8317-46ea-8771-45d73e3be175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013926726 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1013926726
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3375077005
Short name T410
Test name
Test status
Simulation time 16974817 ps
CPU time 1.09 seconds
Started Aug 11 06:25:18 PM PDT 24
Finished Aug 11 06:25:19 PM PDT 24
Peak memory 215284 kb
Host smart-195ff6fe-0250-4ab4-8247-543092b37669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375077005 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3375077005
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2211146052
Short name T784
Test name
Test status
Simulation time 21124463 ps
CPU time 1.06 seconds
Started Aug 11 06:25:23 PM PDT 24
Finished Aug 11 06:25:25 PM PDT 24
Peak memory 215236 kb
Host smart-488c2086-6ef0-41c5-9cdb-1aed151d6512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211146052 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2211146052
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3908162682
Short name T939
Test name
Test status
Simulation time 30133127014 ps
CPU time 415.56 seconds
Started Aug 11 06:25:18 PM PDT 24
Finished Aug 11 06:32:14 PM PDT 24
Peak memory 218056 kb
Host smart-d6f7e9be-df50-4c20-ac9b-07d746893816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908162682 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3908162682
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2337881784
Short name T563
Test name
Test status
Simulation time 52110952 ps
CPU time 1.22 seconds
Started Aug 11 06:26:29 PM PDT 24
Finished Aug 11 06:26:30 PM PDT 24
Peak memory 220700 kb
Host smart-8dfe036c-5695-42a3-bb13-436df3f2b618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337881784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2337881784
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1985660832
Short name T903
Test name
Test status
Simulation time 28419386 ps
CPU time 0.86 seconds
Started Aug 11 06:26:34 PM PDT 24
Finished Aug 11 06:26:36 PM PDT 24
Peak memory 218596 kb
Host smart-e6be8da6-d78d-47af-9f04-d96975acec23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985660832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1985660832
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1978882650
Short name T284
Test name
Test status
Simulation time 117604279 ps
CPU time 1.71 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 220080 kb
Host smart-ba00277e-7297-41b7-9869-27054e542f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978882650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1978882650
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.2791481866
Short name T559
Test name
Test status
Simulation time 28573241 ps
CPU time 1.25 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 219584 kb
Host smart-2ebda8bf-7581-4843-b664-3277ec65ef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791481866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.2791481866
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_genbits.1032821259
Short name T365
Test name
Test status
Simulation time 66758666 ps
CPU time 1.13 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 217284 kb
Host smart-daff8674-efc1-4456-a26c-a85953be505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032821259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1032821259
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1138184736
Short name T397
Test name
Test status
Simulation time 26194061 ps
CPU time 1.21 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 220976 kb
Host smart-6836c0db-61de-451e-a95d-843e5dad8d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138184736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1138184736
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2347535203
Short name T176
Test name
Test status
Simulation time 21697018 ps
CPU time 1.03 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:38 PM PDT 24
Peak memory 218764 kb
Host smart-38be2ac3-5720-4caf-ab03-b375e7387da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347535203 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2347535203
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.4248449736
Short name T957
Test name
Test status
Simulation time 368954985 ps
CPU time 1.78 seconds
Started Aug 11 06:26:39 PM PDT 24
Finished Aug 11 06:26:41 PM PDT 24
Peak memory 218836 kb
Host smart-511d93a9-4e16-499c-adad-5b049dbe697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248449736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.4248449736
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.4015957018
Short name T450
Test name
Test status
Simulation time 49726922 ps
CPU time 1.19 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 219384 kb
Host smart-a0476bea-20fb-4033-87ab-d9955d275ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015957018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.4015957018
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.764708058
Short name T206
Test name
Test status
Simulation time 24088947 ps
CPU time 1.16 seconds
Started Aug 11 06:26:28 PM PDT 24
Finished Aug 11 06:26:30 PM PDT 24
Peak memory 218788 kb
Host smart-41b1ace6-4217-4164-99b6-68170278fb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764708058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.764708058
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2240048207
Short name T44
Test name
Test status
Simulation time 89350197 ps
CPU time 1.13 seconds
Started Aug 11 06:26:35 PM PDT 24
Finished Aug 11 06:26:36 PM PDT 24
Peak memory 218600 kb
Host smart-d41f4518-b78d-46c8-ad7b-3e8331e19f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240048207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2240048207
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.575016633
Short name T112
Test name
Test status
Simulation time 24921823 ps
CPU time 1.15 seconds
Started Aug 11 06:26:34 PM PDT 24
Finished Aug 11 06:26:36 PM PDT 24
Peak memory 218520 kb
Host smart-297ad411-f3d5-40fb-b084-e16d0ead7edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575016633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.575016633
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3246237302
Short name T522
Test name
Test status
Simulation time 27909260 ps
CPU time 0.88 seconds
Started Aug 11 06:26:31 PM PDT 24
Finished Aug 11 06:26:32 PM PDT 24
Peak memory 215192 kb
Host smart-8036f09e-52cc-49f1-a15d-04b00696d094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246237302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3246237302
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2960928251
Short name T702
Test name
Test status
Simulation time 97835815 ps
CPU time 1.1 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 218976 kb
Host smart-2a32318d-5cb7-4232-a5cb-28b48061b220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960928251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2960928251
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.2477183626
Short name T740
Test name
Test status
Simulation time 29770689 ps
CPU time 1.27 seconds
Started Aug 11 06:26:35 PM PDT 24
Finished Aug 11 06:26:37 PM PDT 24
Peak memory 219336 kb
Host smart-481085bc-f422-4e71-aa0f-822f62d6b741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477183626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2477183626
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.1401689153
Short name T172
Test name
Test status
Simulation time 21581517 ps
CPU time 1 seconds
Started Aug 11 06:26:36 PM PDT 24
Finished Aug 11 06:26:37 PM PDT 24
Peak memory 224184 kb
Host smart-994f6074-7bfa-4794-b9a9-7fe8d260cf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401689153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1401689153
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.634390683
Short name T315
Test name
Test status
Simulation time 490830983 ps
CPU time 5.52 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 218628 kb
Host smart-318203e9-8d38-41ea-8467-d4ef3986b141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634390683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.634390683
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.560385066
Short name T874
Test name
Test status
Simulation time 84265707 ps
CPU time 1.3 seconds
Started Aug 11 06:26:33 PM PDT 24
Finished Aug 11 06:26:34 PM PDT 24
Peak memory 219584 kb
Host smart-4bbd0904-de6a-4eda-9c2e-7eee7e7f2cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560385066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.560385066
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2677817304
Short name T928
Test name
Test status
Simulation time 26856140 ps
CPU time 1.19 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:38 PM PDT 24
Peak memory 220900 kb
Host smart-5e374883-2efb-4e3f-bd50-671ded15b2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677817304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2677817304
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3384064827
Short name T43
Test name
Test status
Simulation time 51819837 ps
CPU time 1.63 seconds
Started Aug 11 06:26:32 PM PDT 24
Finished Aug 11 06:26:34 PM PDT 24
Peak memory 218544 kb
Host smart-3869063a-1dd1-4834-b650-6b19c755935b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384064827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3384064827
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1260153149
Short name T469
Test name
Test status
Simulation time 24417575 ps
CPU time 0.94 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:42 PM PDT 24
Peak memory 218480 kb
Host smart-f1542c68-9d79-4969-a3ea-a9cd0f39bdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260153149 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1260153149
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1487775062
Short name T970
Test name
Test status
Simulation time 160289464 ps
CPU time 2.8 seconds
Started Aug 11 06:26:35 PM PDT 24
Finished Aug 11 06:26:38 PM PDT 24
Peak memory 219824 kb
Host smart-ddc71f6a-0e32-4f78-b40b-5db952f05533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487775062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1487775062
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1814657929
Short name T388
Test name
Test status
Simulation time 29684171 ps
CPU time 1.31 seconds
Started Aug 11 06:26:36 PM PDT 24
Finished Aug 11 06:26:37 PM PDT 24
Peak memory 219540 kb
Host smart-88b8b374-24e7-407a-a8e9-d962d64a45f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814657929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1814657929
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.943482458
Short name T139
Test name
Test status
Simulation time 21919267 ps
CPU time 1.17 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:40 PM PDT 24
Peak memory 229748 kb
Host smart-47ba20b5-a19f-49d6-9621-fd1184229cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943482458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.943482458
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.632078087
Short name T488
Test name
Test status
Simulation time 45200794 ps
CPU time 1.53 seconds
Started Aug 11 06:26:25 PM PDT 24
Finished Aug 11 06:26:26 PM PDT 24
Peak memory 220024 kb
Host smart-8b5e3030-fd64-47d5-9c54-c2d6cb90fcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632078087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.632078087
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.936614167
Short name T697
Test name
Test status
Simulation time 22836845 ps
CPU time 1.17 seconds
Started Aug 11 06:26:35 PM PDT 24
Finished Aug 11 06:26:36 PM PDT 24
Peak memory 218576 kb
Host smart-1020e16d-fa95-401f-acc0-17a64bab10f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936614167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.936614167
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.1967482522
Short name T148
Test name
Test status
Simulation time 20915096 ps
CPU time 1.21 seconds
Started Aug 11 06:26:31 PM PDT 24
Finished Aug 11 06:26:33 PM PDT 24
Peak memory 220004 kb
Host smart-b6cfb3eb-1637-478d-81b3-cc497ab61854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967482522 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1967482522
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1200215363
Short name T879
Test name
Test status
Simulation time 569804007 ps
CPU time 5.36 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 217528 kb
Host smart-2e3d1aaa-d75c-4f24-a91b-58046e53a38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200215363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1200215363
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3850995463
Short name T596
Test name
Test status
Simulation time 24026905 ps
CPU time 1.23 seconds
Started Aug 11 06:25:17 PM PDT 24
Finished Aug 11 06:25:18 PM PDT 24
Peak memory 218516 kb
Host smart-52062b1b-a9c2-454e-b273-c493fadac11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850995463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3850995463
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3745659163
Short name T712
Test name
Test status
Simulation time 43255937 ps
CPU time 0.83 seconds
Started Aug 11 06:25:18 PM PDT 24
Finished Aug 11 06:25:19 PM PDT 24
Peak memory 206796 kb
Host smart-af77eca7-2531-4fe0-8d68-965e3b245b5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745659163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3745659163
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1176523466
Short name T466
Test name
Test status
Simulation time 13018920 ps
CPU time 0.92 seconds
Started Aug 11 06:25:30 PM PDT 24
Finished Aug 11 06:25:31 PM PDT 24
Peak memory 216768 kb
Host smart-4e4c3276-2ce6-4b93-a8ad-d2f8e6ebb02e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176523466 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1176523466
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.334514847
Short name T529
Test name
Test status
Simulation time 113506337 ps
CPU time 1.25 seconds
Started Aug 11 06:25:23 PM PDT 24
Finished Aug 11 06:25:25 PM PDT 24
Peak memory 217164 kb
Host smart-15ca3653-c2a5-4097-b9ba-516cf1d62be6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334514847 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.334514847
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2652100710
Short name T177
Test name
Test status
Simulation time 19245598 ps
CPU time 1.12 seconds
Started Aug 11 06:25:29 PM PDT 24
Finished Aug 11 06:25:30 PM PDT 24
Peak memory 224176 kb
Host smart-b993462b-78c7-419c-9c83-05577c561a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652100710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2652100710
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.4127747854
Short name T431
Test name
Test status
Simulation time 121785103 ps
CPU time 1.35 seconds
Started Aug 11 06:25:20 PM PDT 24
Finished Aug 11 06:25:22 PM PDT 24
Peak memory 219892 kb
Host smart-7214083e-ed0f-4796-a51f-edf5e896ba42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127747854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.4127747854
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.181471370
Short name T904
Test name
Test status
Simulation time 24873704 ps
CPU time 0.94 seconds
Started Aug 11 06:25:17 PM PDT 24
Finished Aug 11 06:25:18 PM PDT 24
Peak memory 215488 kb
Host smart-c4fa1fc4-ed6e-4d77-8ac7-b40b5dd376a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181471370 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.181471370
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.4032858560
Short name T28
Test name
Test status
Simulation time 24454152 ps
CPU time 0.93 seconds
Started Aug 11 06:25:23 PM PDT 24
Finished Aug 11 06:25:24 PM PDT 24
Peak memory 207076 kb
Host smart-572498bb-69dc-4ca8-8b2c-2bf7dcf7c631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032858560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4032858560
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1887898381
Short name T598
Test name
Test status
Simulation time 25415135 ps
CPU time 0.99 seconds
Started Aug 11 06:25:20 PM PDT 24
Finished Aug 11 06:25:21 PM PDT 24
Peak memory 215296 kb
Host smart-0496bf4a-d681-40e5-96bb-bc3696e29cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887898381 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1887898381
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2747543736
Short name T514
Test name
Test status
Simulation time 174792618 ps
CPU time 3.64 seconds
Started Aug 11 06:25:19 PM PDT 24
Finished Aug 11 06:25:23 PM PDT 24
Peak memory 215288 kb
Host smart-8cd9af07-3af0-4739-9dff-7edf62238ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747543736 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2747543736
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2062086386
Short name T615
Test name
Test status
Simulation time 119793542821 ps
CPU time 730.95 seconds
Started Aug 11 06:25:22 PM PDT 24
Finished Aug 11 06:37:33 PM PDT 24
Peak memory 223612 kb
Host smart-52fff1e4-16f5-4746-ad5b-d35192eb4cc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062086386 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2062086386
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.1604968615
Short name T637
Test name
Test status
Simulation time 244568109 ps
CPU time 1.18 seconds
Started Aug 11 06:26:34 PM PDT 24
Finished Aug 11 06:26:35 PM PDT 24
Peak memory 215588 kb
Host smart-32382479-ba92-4884-af31-4d820cd63041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604968615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1604968615
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2154294598
Short name T218
Test name
Test status
Simulation time 28721956 ps
CPU time 1.39 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 225840 kb
Host smart-670679ca-35ad-4a2a-a6f0-d48c9589df99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154294598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2154294598
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/71.edn_alert.780733818
Short name T527
Test name
Test status
Simulation time 177683173 ps
CPU time 1.27 seconds
Started Aug 11 06:26:35 PM PDT 24
Finished Aug 11 06:26:37 PM PDT 24
Peak memory 220544 kb
Host smart-ac8b73f9-9343-46de-8f5c-806b6ef63060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780733818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.780733818
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2774445944
Short name T771
Test name
Test status
Simulation time 18420415 ps
CPU time 1.05 seconds
Started Aug 11 06:26:35 PM PDT 24
Finished Aug 11 06:26:36 PM PDT 24
Peak memory 218788 kb
Host smart-49071cfd-addb-494a-81e0-77fa942d63fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774445944 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2774445944
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.155296973
Short name T797
Test name
Test status
Simulation time 47923943 ps
CPU time 1.23 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 217444 kb
Host smart-5afee74b-a7da-4724-b56b-793b282543e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155296973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.155296973
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.28097050
Short name T926
Test name
Test status
Simulation time 24659456 ps
CPU time 1.26 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 219180 kb
Host smart-80d523a4-408e-4cd2-a280-82cbb6261e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28097050 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.28097050
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.2159428644
Short name T885
Test name
Test status
Simulation time 17818034 ps
CPU time 1.09 seconds
Started Aug 11 06:26:36 PM PDT 24
Finished Aug 11 06:26:37 PM PDT 24
Peak memory 218692 kb
Host smart-526902ab-a9c9-478a-ac5a-e4ce8a182af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159428644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2159428644
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2014568183
Short name T911
Test name
Test status
Simulation time 80321616 ps
CPU time 1.22 seconds
Started Aug 11 06:26:32 PM PDT 24
Finished Aug 11 06:26:34 PM PDT 24
Peak memory 218932 kb
Host smart-ad433014-11eb-4d9a-929f-f16b3be08c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014568183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2014568183
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2632087657
Short name T187
Test name
Test status
Simulation time 26274683 ps
CPU time 1.28 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 218492 kb
Host smart-eb0a7d2d-f5b8-47c2-abcd-562a90b28cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632087657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2632087657
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2380308548
Short name T125
Test name
Test status
Simulation time 94281788 ps
CPU time 0.89 seconds
Started Aug 11 06:26:34 PM PDT 24
Finished Aug 11 06:26:35 PM PDT 24
Peak memory 219980 kb
Host smart-ffaa59ec-cb73-45c6-ba78-faf3694daea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380308548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2380308548
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1782483529
Short name T929
Test name
Test status
Simulation time 33197096 ps
CPU time 1.38 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 218312 kb
Host smart-30406f9e-c5ff-414f-9d75-e03deb406641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782483529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1782483529
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.668994869
Short name T480
Test name
Test status
Simulation time 22544881 ps
CPU time 1.14 seconds
Started Aug 11 06:26:30 PM PDT 24
Finished Aug 11 06:26:31 PM PDT 24
Peak memory 219620 kb
Host smart-a53143d8-ed20-40f2-9987-15f26f1bc1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668994869 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.668994869
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2137218753
Short name T137
Test name
Test status
Simulation time 27369151 ps
CPU time 0.95 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 220036 kb
Host smart-56dec925-c730-421b-8dd0-15b953f03e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137218753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2137218753
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2707250426
Short name T477
Test name
Test status
Simulation time 40336401 ps
CPU time 1.45 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 219372 kb
Host smart-6ad71635-fe9b-4f68-86d5-f92ca8d3958b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707250426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2707250426
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1666081351
Short name T329
Test name
Test status
Simulation time 263417122 ps
CPU time 1.22 seconds
Started Aug 11 06:26:39 PM PDT 24
Finished Aug 11 06:26:40 PM PDT 24
Peak memory 219356 kb
Host smart-01c9f662-115f-4b7b-82b0-855f6afee08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666081351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1666081351
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1753777074
Short name T353
Test name
Test status
Simulation time 23398460 ps
CPU time 0.87 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:42 PM PDT 24
Peak memory 218604 kb
Host smart-b7600d54-bd8b-4f8a-9ef7-4687f428603a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753777074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1753777074
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.450626951
Short name T708
Test name
Test status
Simulation time 112377662 ps
CPU time 1.79 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 218920 kb
Host smart-be7a5a2f-9334-4907-9841-d8a5ccd8b8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450626951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.450626951
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.2012902566
Short name T735
Test name
Test status
Simulation time 28360694 ps
CPU time 1.25 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:42 PM PDT 24
Peak memory 218516 kb
Host smart-d918fa71-e795-4a4b-b9b2-80c0d7fec875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012902566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.2012902566
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.1154949810
Short name T458
Test name
Test status
Simulation time 145839807 ps
CPU time 1.01 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 219900 kb
Host smart-eda1dce4-4429-4f78-bbcf-aa1cd240fe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154949810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1154949810
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2823979125
Short name T591
Test name
Test status
Simulation time 57120038 ps
CPU time 1.33 seconds
Started Aug 11 06:26:39 PM PDT 24
Finished Aug 11 06:26:40 PM PDT 24
Peak memory 218408 kb
Host smart-e86dc537-dfc6-40ea-8a54-c397cb292a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823979125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2823979125
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.1750456261
Short name T890
Test name
Test status
Simulation time 45710603 ps
CPU time 1.19 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 218660 kb
Host smart-1562ad6b-a682-4cbb-8460-2e19264f4c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750456261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.1750456261
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2970171396
Short name T943
Test name
Test status
Simulation time 29397098 ps
CPU time 1.35 seconds
Started Aug 11 06:26:40 PM PDT 24
Finished Aug 11 06:26:41 PM PDT 24
Peak memory 225768 kb
Host smart-12770128-2959-4d66-a5e1-49463d375cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970171396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2970171396
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.496073253
Short name T580
Test name
Test status
Simulation time 72484277 ps
CPU time 1.14 seconds
Started Aug 11 06:26:35 PM PDT 24
Finished Aug 11 06:26:36 PM PDT 24
Peak memory 218668 kb
Host smart-ed30bd40-950c-4092-8c10-37d50e36cea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496073253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.496073253
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.1839907699
Short name T962
Test name
Test status
Simulation time 71761579 ps
CPU time 1.09 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 219496 kb
Host smart-dae5aebd-dd43-4566-b1fc-514635598af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839907699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1839907699
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.1099406682
Short name T32
Test name
Test status
Simulation time 57697079 ps
CPU time 0.82 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:38 PM PDT 24
Peak memory 218704 kb
Host smart-e4ee6ed4-2303-4602-bb6e-595d2070aa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099406682 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1099406682
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2979215456
Short name T528
Test name
Test status
Simulation time 67123227 ps
CPU time 2.4 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 218872 kb
Host smart-f95955c2-0dbb-4f56-bc8e-2130b4190ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979215456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2979215456
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1970877643
Short name T749
Test name
Test status
Simulation time 81795777 ps
CPU time 1.14 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 218180 kb
Host smart-4306d77b-a723-488b-8421-8c28fca3c9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970877643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1970877643
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.689609599
Short name T145
Test name
Test status
Simulation time 145115964 ps
CPU time 1.26 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 225692 kb
Host smart-d16efa10-e16c-45ff-b72c-51a827e3149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689609599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.689609599
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2774687354
Short name T401
Test name
Test status
Simulation time 41894261 ps
CPU time 1.44 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 217316 kb
Host smart-4c904a8f-a1a7-4184-ab6e-a4bb46bbf144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774687354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2774687354
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.827865697
Short name T123
Test name
Test status
Simulation time 31957055 ps
CPU time 1.27 seconds
Started Aug 11 06:25:19 PM PDT 24
Finished Aug 11 06:25:21 PM PDT 24
Peak memory 219432 kb
Host smart-7b68025c-734c-49e7-990c-2b84c8014894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827865697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.827865697
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.329992265
Short name T833
Test name
Test status
Simulation time 57684524 ps
CPU time 0.88 seconds
Started Aug 11 06:25:28 PM PDT 24
Finished Aug 11 06:25:29 PM PDT 24
Peak memory 206744 kb
Host smart-1ad49485-8071-4275-b434-814d63142834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329992265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.329992265
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3654862231
Short name T216
Test name
Test status
Simulation time 42569061 ps
CPU time 0.9 seconds
Started Aug 11 06:25:29 PM PDT 24
Finished Aug 11 06:25:30 PM PDT 24
Peak memory 216592 kb
Host smart-4b6be66c-c988-4dfb-b043-91b42c56839e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654862231 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3654862231
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2586199068
Short name T475
Test name
Test status
Simulation time 67077641 ps
CPU time 1.26 seconds
Started Aug 11 06:25:20 PM PDT 24
Finished Aug 11 06:25:22 PM PDT 24
Peak memory 217100 kb
Host smart-330d4869-38e9-4fa3-8d7a-5a695a178035
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586199068 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2586199068
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.534707747
Short name T170
Test name
Test status
Simulation time 22402116 ps
CPU time 1.14 seconds
Started Aug 11 06:25:20 PM PDT 24
Finished Aug 11 06:25:21 PM PDT 24
Peak memory 224120 kb
Host smart-0ae49c43-91de-4ac6-a200-d80e7ac270be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534707747 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.534707747
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3771305016
Short name T659
Test name
Test status
Simulation time 34923829 ps
CPU time 1.31 seconds
Started Aug 11 06:25:29 PM PDT 24
Finished Aug 11 06:25:30 PM PDT 24
Peak memory 219968 kb
Host smart-ba2abae7-d681-4dab-9652-2c92ee95173d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771305016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3771305016
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2553309142
Short name T711
Test name
Test status
Simulation time 20550330 ps
CPU time 1.1 seconds
Started Aug 11 06:25:21 PM PDT 24
Finished Aug 11 06:25:22 PM PDT 24
Peak memory 216716 kb
Host smart-5bef6c43-c6a8-447e-a172-16ad9bfbd9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553309142 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2553309142
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.1498397362
Short name T876
Test name
Test status
Simulation time 21697323 ps
CPU time 0.96 seconds
Started Aug 11 06:25:19 PM PDT 24
Finished Aug 11 06:25:20 PM PDT 24
Peak memory 215324 kb
Host smart-2d97b9c3-b456-4947-a7f7-0438adc81e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498397362 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1498397362
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3966083133
Short name T612
Test name
Test status
Simulation time 337362803 ps
CPU time 6.29 seconds
Started Aug 11 06:25:19 PM PDT 24
Finished Aug 11 06:25:25 PM PDT 24
Peak memory 215316 kb
Host smart-08b93294-6c04-45d0-a63e-0e7999887db9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966083133 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3966083133
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.740286772
Short name T821
Test name
Test status
Simulation time 188013226508 ps
CPU time 588.81 seconds
Started Aug 11 06:25:20 PM PDT 24
Finished Aug 11 06:35:09 PM PDT 24
Peak memory 220224 kb
Host smart-388aea22-d71d-4b24-b935-b2c55f073556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740286772 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.740286772
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2171106111
Short name T418
Test name
Test status
Simulation time 161584510 ps
CPU time 1.38 seconds
Started Aug 11 06:26:39 PM PDT 24
Finished Aug 11 06:26:40 PM PDT 24
Peak memory 219568 kb
Host smart-2a8b9ccf-f975-4347-81d1-83e65e8e2f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171106111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2171106111
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.992516936
Short name T154
Test name
Test status
Simulation time 27963180 ps
CPU time 1.28 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 229600 kb
Host smart-ead2bd50-79e3-4aca-b456-072b32221844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992516936 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.992516936
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1243047991
Short name T70
Test name
Test status
Simulation time 30848147 ps
CPU time 1.31 seconds
Started Aug 11 06:26:36 PM PDT 24
Finished Aug 11 06:26:37 PM PDT 24
Peak memory 218408 kb
Host smart-63feed66-ac2c-4038-8b7a-89fc94c2d87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243047991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1243047991
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.3236678051
Short name T718
Test name
Test status
Simulation time 86251457 ps
CPU time 1.1 seconds
Started Aug 11 06:26:35 PM PDT 24
Finished Aug 11 06:26:37 PM PDT 24
Peak memory 218596 kb
Host smart-b1f74284-fa69-4f54-8e14-2fb45434eebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236678051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.3236678051
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2806001520
Short name T204
Test name
Test status
Simulation time 22110463 ps
CPU time 1.21 seconds
Started Aug 11 06:26:40 PM PDT 24
Finished Aug 11 06:26:41 PM PDT 24
Peak memory 218912 kb
Host smart-eab6c505-3645-4d8b-945e-e50a5473c919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806001520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2806001520
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2188370249
Short name T819
Test name
Test status
Simulation time 40914336 ps
CPU time 1.03 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 218536 kb
Host smart-a391e3fd-2818-479e-b1f5-225e14279b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188370249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2188370249
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1122002154
Short name T557
Test name
Test status
Simulation time 21345862 ps
CPU time 1.09 seconds
Started Aug 11 06:26:39 PM PDT 24
Finished Aug 11 06:26:40 PM PDT 24
Peak memory 218740 kb
Host smart-b1b9a530-8e81-4925-978f-43ee61f3dae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122002154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1122002154
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1066978589
Short name T71
Test name
Test status
Simulation time 34207700 ps
CPU time 1.26 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:38 PM PDT 24
Peak memory 218528 kb
Host smart-c9798000-781f-4cd6-90f1-cb16e5cbc3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066978589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1066978589
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.471317878
Short name T135
Test name
Test status
Simulation time 87324823 ps
CPU time 1.07 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 219424 kb
Host smart-325e7f4f-c318-44b5-b085-b0529eec739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471317878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.471317878
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.4173290390
Short name T979
Test name
Test status
Simulation time 30480371 ps
CPU time 1.05 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 218752 kb
Host smart-ef45a8a8-c760-4e21-bfc8-7a917b417ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173290390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4173290390
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.4145953366
Short name T750
Test name
Test status
Simulation time 42980188 ps
CPU time 1.61 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 217380 kb
Host smart-34f5bcf7-f8b8-40ae-b220-4b151e4f397f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145953366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.4145953366
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2630795853
Short name T391
Test name
Test status
Simulation time 219603630 ps
CPU time 1.18 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 219668 kb
Host smart-d918f0be-cd73-4ffc-aa8f-fe12eebaf72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630795853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2630795853
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3835484228
Short name T173
Test name
Test status
Simulation time 32209336 ps
CPU time 0.89 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 218564 kb
Host smart-a8859eef-129d-44e6-a60c-0f1b41735cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835484228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3835484228
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.15424072
Short name T623
Test name
Test status
Simulation time 50780090 ps
CPU time 1.19 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 217376 kb
Host smart-344ce8f5-345e-4c3c-ae97-54da2ab92a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15424072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.15424072
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.1072952372
Short name T495
Test name
Test status
Simulation time 54683139 ps
CPU time 1.18 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 218584 kb
Host smart-5486072d-582f-40db-9c14-2dc04ac84c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072952372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.1072952372
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1867849543
Short name T724
Test name
Test status
Simulation time 27073945 ps
CPU time 0.98 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 219968 kb
Host smart-d7f65980-0ac0-4b5a-894b-26dca5fd75e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867849543 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1867849543
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3428657380
Short name T743
Test name
Test status
Simulation time 50104200 ps
CPU time 1.26 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 218832 kb
Host smart-4907bb54-a580-4f90-af05-a5a306d1d87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428657380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3428657380
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2066273256
Short name T337
Test name
Test status
Simulation time 90870496 ps
CPU time 1.07 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:44 PM PDT 24
Peak memory 219684 kb
Host smart-06dea1b8-23dd-4f65-aa80-c564d6c94752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066273256 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2066273256
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3240346425
Short name T222
Test name
Test status
Simulation time 47688103 ps
CPU time 0.86 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 218740 kb
Host smart-ce2fa5ad-5a77-45e1-a4e8-3f1e2c63f5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240346425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3240346425
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.4195455024
Short name T21
Test name
Test status
Simulation time 39421110 ps
CPU time 1.44 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:38 PM PDT 24
Peak memory 219532 kb
Host smart-ff4d680d-8d7a-4d5f-9c43-ef1f13d8dfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195455024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.4195455024
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.1651584582
Short name T158
Test name
Test status
Simulation time 38581728 ps
CPU time 1.24 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 219720 kb
Host smart-6ab19dbc-fbbd-4ac3-9cce-c742b75bb474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651584582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1651584582
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.239004357
Short name T189
Test name
Test status
Simulation time 32128725 ps
CPU time 1 seconds
Started Aug 11 06:26:50 PM PDT 24
Finished Aug 11 06:26:51 PM PDT 24
Peak memory 224116 kb
Host smart-d316ff37-d3b3-4649-90ef-2a0a07bf66f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239004357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.239004357
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2343770981
Short name T476
Test name
Test status
Simulation time 42877901 ps
CPU time 1.36 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 217332 kb
Host smart-eec2d7ac-c2e0-4e12-83d3-169dad38a6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343770981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2343770981
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.942316895
Short name T984
Test name
Test status
Simulation time 42414411 ps
CPU time 1.18 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 220084 kb
Host smart-95d11177-54ca-4991-81aa-25eaad1c3aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942316895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.942316895
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3708129580
Short name T995
Test name
Test status
Simulation time 29793770 ps
CPU time 1.31 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 219880 kb
Host smart-cd89d56e-5672-4be2-9448-98caa4b8cf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708129580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3708129580
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1708767064
Short name T530
Test name
Test status
Simulation time 69885430 ps
CPU time 1.3 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 218404 kb
Host smart-0e215098-9cb4-4d00-876f-b975be380dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708767064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1708767064
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2563056973
Short name T453
Test name
Test status
Simulation time 26135252 ps
CPU time 1.3 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:42 PM PDT 24
Peak memory 219728 kb
Host smart-5026f1ba-5149-4e97-9da4-8157db528ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563056973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2563056973
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.3648295180
Short name T827
Test name
Test status
Simulation time 20321731 ps
CPU time 0.93 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 218656 kb
Host smart-6d6da49b-1084-49c7-a297-bc65052c1089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648295180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3648295180
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.80673084
Short name T682
Test name
Test status
Simulation time 50397486 ps
CPU time 1.05 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:46 PM PDT 24
Peak memory 217300 kb
Host smart-4a9e9a95-4caa-44a9-bc18-35e1726cc232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80673084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.80673084
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3992655230
Short name T633
Test name
Test status
Simulation time 34804817 ps
CPU time 1.3 seconds
Started Aug 11 06:25:30 PM PDT 24
Finished Aug 11 06:25:32 PM PDT 24
Peak memory 219720 kb
Host smart-8599f6fb-55c3-4e88-b2bc-8b916c4bda1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992655230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3992655230
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.683664851
Short name T719
Test name
Test status
Simulation time 26115768 ps
CPU time 1.12 seconds
Started Aug 11 06:25:23 PM PDT 24
Finished Aug 11 06:25:25 PM PDT 24
Peak memory 206848 kb
Host smart-015a10ae-315b-4891-ab31-e99aab4a50e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683664851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.683664851
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3928589216
Short name T588
Test name
Test status
Simulation time 13909612 ps
CPU time 0.89 seconds
Started Aug 11 06:25:24 PM PDT 24
Finished Aug 11 06:25:25 PM PDT 24
Peak memory 219492 kb
Host smart-3717f0b8-900d-426c-bb55-ec55b6ab1cea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928589216 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3928589216
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3358651622
Short name T661
Test name
Test status
Simulation time 51868422 ps
CPU time 1.19 seconds
Started Aug 11 06:25:23 PM PDT 24
Finished Aug 11 06:25:25 PM PDT 24
Peak memory 217172 kb
Host smart-e6de3e99-0a1a-4563-8e91-0ea6fc689332
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358651622 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3358651622
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.786018623
Short name T201
Test name
Test status
Simulation time 24097779 ps
CPU time 1.02 seconds
Started Aug 11 06:25:22 PM PDT 24
Finished Aug 11 06:25:24 PM PDT 24
Peak memory 219684 kb
Host smart-aa8a6130-8c44-42f8-a691-248b915d7ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786018623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.786018623
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.748129177
Short name T408
Test name
Test status
Simulation time 93689022 ps
CPU time 3.21 seconds
Started Aug 11 06:25:25 PM PDT 24
Finished Aug 11 06:25:28 PM PDT 24
Peak memory 218880 kb
Host smart-6c493e6b-a5b3-4e1e-b97f-33544c67754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748129177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.748129177
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.96264172
Short name T726
Test name
Test status
Simulation time 47579564 ps
CPU time 0.83 seconds
Started Aug 11 06:25:22 PM PDT 24
Finished Aug 11 06:25:23 PM PDT 24
Peak memory 215756 kb
Host smart-e079c694-dd38-4289-9be5-05d9d5038ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96264172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.96264172
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3242745673
Short name T678
Test name
Test status
Simulation time 16041537 ps
CPU time 0.97 seconds
Started Aug 11 06:25:28 PM PDT 24
Finished Aug 11 06:25:29 PM PDT 24
Peak memory 206996 kb
Host smart-eea84b16-1c9a-44a9-baca-5ff99f15a960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242745673 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3242745673
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.4274500334
Short name T668
Test name
Test status
Simulation time 86958926 ps
CPU time 1.02 seconds
Started Aug 11 06:25:23 PM PDT 24
Finished Aug 11 06:25:24 PM PDT 24
Peak memory 215320 kb
Host smart-5be9daf5-11ad-46b6-b9c4-4133b413a79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274500334 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.4274500334
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1031078959
Short name T917
Test name
Test status
Simulation time 238941488 ps
CPU time 4.92 seconds
Started Aug 11 06:25:24 PM PDT 24
Finished Aug 11 06:25:29 PM PDT 24
Peak memory 217216 kb
Host smart-8d401d7d-a8aa-4571-b07f-981e4d35a432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031078959 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1031078959
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.349345645
Short name T868
Test name
Test status
Simulation time 208116582944 ps
CPU time 1061.71 seconds
Started Aug 11 06:25:28 PM PDT 24
Finished Aug 11 06:43:10 PM PDT 24
Peak memory 223800 kb
Host smart-54091a82-e63d-4fbf-8d14-72e2b17b7c78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349345645 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.349345645
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.4091000699
Short name T47
Test name
Test status
Simulation time 36760288 ps
CPU time 1.25 seconds
Started Aug 11 06:26:41 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 220600 kb
Host smart-5d2f4b4b-9fd0-438a-8d3f-652892e17820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091000699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.4091000699
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1359470380
Short name T191
Test name
Test status
Simulation time 20326684 ps
CPU time 1.13 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 218796 kb
Host smart-0bce0aac-63af-4b63-848a-8036fdf9740e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359470380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1359470380
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.791555839
Short name T303
Test name
Test status
Simulation time 56064863 ps
CPU time 1.26 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 219928 kb
Host smart-441ab893-1b95-4e41-9c00-2f30adbe435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791555839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.791555839
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1524802748
Short name T597
Test name
Test status
Simulation time 31798411 ps
CPU time 1.2 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 218676 kb
Host smart-07042e15-d17c-4521-a456-c6fda6984f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524802748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1524802748
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.875771808
Short name T138
Test name
Test status
Simulation time 29094857 ps
CPU time 1.06 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 229724 kb
Host smart-cb10f17a-98ef-4780-a829-9a5bfe2fddfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875771808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.875771808
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2810507195
Short name T296
Test name
Test status
Simulation time 49136172 ps
CPU time 1.23 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 217372 kb
Host smart-468deaf3-e875-4093-9f87-543c0f14e11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810507195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2810507195
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.1384543329
Short name T167
Test name
Test status
Simulation time 72617009 ps
CPU time 1.15 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 219940 kb
Host smart-ef7de271-c31d-44ae-a682-558905988115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384543329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.1384543329
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3771541749
Short name T124
Test name
Test status
Simulation time 37076277 ps
CPU time 1.27 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 229656 kb
Host smart-4aae9e5f-81fa-488d-b8c1-bca67c9b7fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771541749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3771541749
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.779114033
Short name T877
Test name
Test status
Simulation time 83856956 ps
CPU time 2.67 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:40 PM PDT 24
Peak memory 219940 kb
Host smart-12f337fa-754b-4a6b-bfa9-bb07d5e3a64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779114033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.779114033
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.737441997
Short name T87
Test name
Test status
Simulation time 94844048 ps
CPU time 1.27 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 218772 kb
Host smart-762fdd38-5c51-4363-adb9-38133007dd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737441997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.737441997
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.904249858
Short name T600
Test name
Test status
Simulation time 32869854 ps
CPU time 0.83 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 218732 kb
Host smart-153f659d-3268-49dc-be46-85134c033b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904249858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.904249858
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.4214029640
Short name T931
Test name
Test status
Simulation time 71166680 ps
CPU time 1.18 seconds
Started Aug 11 06:26:49 PM PDT 24
Finished Aug 11 06:26:55 PM PDT 24
Peak memory 220144 kb
Host smart-53efe8cd-2c10-445b-b874-0967aa5c94a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214029640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4214029640
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1630732250
Short name T705
Test name
Test status
Simulation time 90170918 ps
CPU time 1.22 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 219228 kb
Host smart-c8748f0f-66a6-4d73-a25e-4b8d8c954585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630732250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1630732250
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.4023884592
Short name T940
Test name
Test status
Simulation time 30131930 ps
CPU time 1.29 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 219944 kb
Host smart-a0534240-e223-40b8-9df0-daa44720cc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023884592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.4023884592
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2440583037
Short name T42
Test name
Test status
Simulation time 103712704 ps
CPU time 1.29 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 217236 kb
Host smart-82b9ca8b-e02b-4ca5-b446-f23b2fa3c560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440583037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2440583037
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3494771255
Short name T110
Test name
Test status
Simulation time 67214689 ps
CPU time 1.18 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:38 PM PDT 24
Peak memory 218272 kb
Host smart-7193e923-a8dd-4f18-bd12-d91e7b840b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494771255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3494771255
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.394791681
Short name T118
Test name
Test status
Simulation time 44575072 ps
CPU time 1.01 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 229700 kb
Host smart-8517f8a1-9e15-4b45-a917-c405784d7f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394791681 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.394791681
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1501192291
Short name T650
Test name
Test status
Simulation time 93963121 ps
CPU time 1.12 seconds
Started Aug 11 06:26:44 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 217296 kb
Host smart-dbe2245b-69b7-439e-946e-684a7a9daddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501192291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1501192291
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.790632202
Short name T502
Test name
Test status
Simulation time 91523585 ps
CPU time 1.16 seconds
Started Aug 11 06:26:47 PM PDT 24
Finished Aug 11 06:26:49 PM PDT 24
Peak memory 218636 kb
Host smart-5ba7bf02-1d7c-4a03-97b0-a438cc0c185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790632202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.790632202
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.2173642578
Short name T174
Test name
Test status
Simulation time 25135978 ps
CPU time 1.08 seconds
Started Aug 11 06:26:42 PM PDT 24
Finished Aug 11 06:26:43 PM PDT 24
Peak memory 224172 kb
Host smart-4b1af2a7-38fc-4926-815f-975e04e6e98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173642578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2173642578
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2773742302
Short name T427
Test name
Test status
Simulation time 621918727 ps
CPU time 2.35 seconds
Started Aug 11 06:26:43 PM PDT 24
Finished Aug 11 06:26:45 PM PDT 24
Peak memory 220192 kb
Host smart-853cab66-aeb6-469c-8c8a-87d9fbfa63e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773742302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2773742302
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3577136355
Short name T168
Test name
Test status
Simulation time 81640784 ps
CPU time 1.14 seconds
Started Aug 11 06:26:48 PM PDT 24
Finished Aug 11 06:26:50 PM PDT 24
Peak memory 220456 kb
Host smart-43dad7bc-f37b-44ad-86ca-3f35549f43fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577136355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3577136355
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1889974624
Short name T8
Test name
Test status
Simulation time 48722328 ps
CPU time 1 seconds
Started Aug 11 06:26:48 PM PDT 24
Finished Aug 11 06:26:49 PM PDT 24
Peak memory 219952 kb
Host smart-312b5841-a0e6-4e97-852a-e09dc6db0f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889974624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1889974624
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2039486019
Short name T325
Test name
Test status
Simulation time 36608699 ps
CPU time 1.37 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:47 PM PDT 24
Peak memory 215296 kb
Host smart-9a438826-e14b-4c36-b83e-8ae3bdf2519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039486019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2039486019
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.939923090
Short name T108
Test name
Test status
Simulation time 27363646 ps
CPU time 1.3 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 220000 kb
Host smart-c0df6e96-bd94-4a12-92ff-8b839ed93af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939923090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.939923090
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.854922805
Short name T51
Test name
Test status
Simulation time 41581365 ps
CPU time 1.27 seconds
Started Aug 11 06:26:38 PM PDT 24
Finished Aug 11 06:26:39 PM PDT 24
Peak memory 225636 kb
Host smart-6eae9001-69fc-48d9-bbbf-c0e18c09d25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854922805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.854922805
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.133512044
Short name T309
Test name
Test status
Simulation time 147269612 ps
CPU time 3.13 seconds
Started Aug 11 06:26:46 PM PDT 24
Finished Aug 11 06:26:49 PM PDT 24
Peak memory 218636 kb
Host smart-c0b0a373-40ea-4e81-8b0e-a26b7ce346fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133512044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.133512044
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3185637499
Short name T159
Test name
Test status
Simulation time 111978337 ps
CPU time 1.24 seconds
Started Aug 11 06:26:49 PM PDT 24
Finished Aug 11 06:26:50 PM PDT 24
Peak memory 218276 kb
Host smart-81c4ecb8-ae9b-4427-a594-51a4f9763a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185637499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3185637499
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3579829016
Short name T182
Test name
Test status
Simulation time 97553694 ps
CPU time 0.93 seconds
Started Aug 11 06:26:37 PM PDT 24
Finished Aug 11 06:26:38 PM PDT 24
Peak memory 223956 kb
Host smart-65338624-218b-4052-aa66-97538ef7296b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579829016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3579829016
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3026593431
Short name T318
Test name
Test status
Simulation time 61598176 ps
CPU time 2.24 seconds
Started Aug 11 06:26:45 PM PDT 24
Finished Aug 11 06:26:48 PM PDT 24
Peak memory 218704 kb
Host smart-e7948870-21d2-4b30-8de3-5b034029d1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026593431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3026593431
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%