Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.69 98.25 93.73 97.02 91.86 96.37 99.77 92.80


Total test records in report: 1110
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T1012 /workspace/coverage/cover_reg_top/12.edn_tl_errors.339907600 Aug 12 06:38:46 PM PDT 24 Aug 12 06:38:48 PM PDT 24 105575012 ps
T305 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2296850778 Aug 12 06:38:19 PM PDT 24 Aug 12 06:38:21 PM PDT 24 156300586 ps
T1013 /workspace/coverage/cover_reg_top/1.edn_intr_test.1470821526 Aug 12 06:38:20 PM PDT 24 Aug 12 06:38:20 PM PDT 24 21285309 ps
T1014 /workspace/coverage/cover_reg_top/13.edn_intr_test.4153480853 Aug 12 06:38:38 PM PDT 24 Aug 12 06:38:39 PM PDT 24 35215434 ps
T1015 /workspace/coverage/cover_reg_top/41.edn_intr_test.1552616987 Aug 12 06:39:01 PM PDT 24 Aug 12 06:39:02 PM PDT 24 19330543 ps
T1016 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2615795041 Aug 12 06:38:47 PM PDT 24 Aug 12 06:38:50 PM PDT 24 55983647 ps
T1017 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3301438887 Aug 12 06:38:35 PM PDT 24 Aug 12 06:38:37 PM PDT 24 48891672 ps
T1018 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2514662220 Aug 12 06:38:41 PM PDT 24 Aug 12 06:38:42 PM PDT 24 14399409 ps
T1019 /workspace/coverage/cover_reg_top/11.edn_intr_test.1468259876 Aug 12 06:38:31 PM PDT 24 Aug 12 06:38:32 PM PDT 24 15846886 ps
T1020 /workspace/coverage/cover_reg_top/30.edn_intr_test.1759042526 Aug 12 06:38:33 PM PDT 24 Aug 12 06:38:34 PM PDT 24 30821897 ps
T1021 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1632743077 Aug 12 06:38:38 PM PDT 24 Aug 12 06:38:40 PM PDT 24 60263847 ps
T1022 /workspace/coverage/cover_reg_top/26.edn_intr_test.2309071198 Aug 12 06:38:52 PM PDT 24 Aug 12 06:38:53 PM PDT 24 42230125 ps
T275 /workspace/coverage/cover_reg_top/15.edn_csr_rw.381402169 Aug 12 06:38:41 PM PDT 24 Aug 12 06:38:42 PM PDT 24 14610560 ps
T306 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.458349577 Aug 12 06:38:37 PM PDT 24 Aug 12 06:38:39 PM PDT 24 252278359 ps
T1023 /workspace/coverage/cover_reg_top/25.edn_intr_test.985894975 Aug 12 06:38:52 PM PDT 24 Aug 12 06:38:53 PM PDT 24 39353348 ps
T1024 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2680449324 Aug 12 06:38:25 PM PDT 24 Aug 12 06:38:26 PM PDT 24 16414034 ps
T1025 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1824755936 Aug 12 06:38:56 PM PDT 24 Aug 12 06:38:58 PM PDT 24 54538291 ps
T276 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1438884789 Aug 12 06:38:28 PM PDT 24 Aug 12 06:38:29 PM PDT 24 30653935 ps
T1026 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2775696665 Aug 12 06:38:29 PM PDT 24 Aug 12 06:38:31 PM PDT 24 38705003 ps
T1027 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3394041677 Aug 12 06:38:45 PM PDT 24 Aug 12 06:38:47 PM PDT 24 172398752 ps
T1028 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2287289520 Aug 12 06:38:34 PM PDT 24 Aug 12 06:38:36 PM PDT 24 63343554 ps
T1029 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2429825383 Aug 12 06:38:27 PM PDT 24 Aug 12 06:38:28 PM PDT 24 30702800 ps
T1030 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2258597025 Aug 12 06:38:50 PM PDT 24 Aug 12 06:38:53 PM PDT 24 55570659 ps
T1031 /workspace/coverage/cover_reg_top/2.edn_intr_test.2334827015 Aug 12 06:38:29 PM PDT 24 Aug 12 06:38:30 PM PDT 24 38275339 ps
T1032 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1117222873 Aug 12 06:38:42 PM PDT 24 Aug 12 06:38:43 PM PDT 24 183451209 ps
T1033 /workspace/coverage/cover_reg_top/6.edn_intr_test.62108613 Aug 12 06:38:28 PM PDT 24 Aug 12 06:38:29 PM PDT 24 13721657 ps
T1034 /workspace/coverage/cover_reg_top/10.edn_intr_test.2719975157 Aug 12 06:38:27 PM PDT 24 Aug 12 06:38:29 PM PDT 24 26783668 ps
T1035 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3844314337 Aug 12 06:38:37 PM PDT 24 Aug 12 06:38:39 PM PDT 24 321693213 ps
T1036 /workspace/coverage/cover_reg_top/28.edn_intr_test.865729438 Aug 12 06:38:51 PM PDT 24 Aug 12 06:38:52 PM PDT 24 39442072 ps
T1037 /workspace/coverage/cover_reg_top/35.edn_intr_test.2035694065 Aug 12 06:38:33 PM PDT 24 Aug 12 06:38:34 PM PDT 24 40652275 ps
T1038 /workspace/coverage/cover_reg_top/43.edn_intr_test.2495923303 Aug 12 06:38:55 PM PDT 24 Aug 12 06:38:56 PM PDT 24 12456337 ps
T1039 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3771936134 Aug 12 06:38:29 PM PDT 24 Aug 12 06:38:30 PM PDT 24 31901517 ps
T1040 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.601966034 Aug 12 06:38:29 PM PDT 24 Aug 12 06:38:31 PM PDT 24 16952266 ps
T1041 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.498221197 Aug 12 06:38:50 PM PDT 24 Aug 12 06:38:51 PM PDT 24 89987807 ps
T277 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1848970182 Aug 12 06:38:29 PM PDT 24 Aug 12 06:38:30 PM PDT 24 207975588 ps
T1042 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2762751746 Aug 12 06:38:27 PM PDT 24 Aug 12 06:38:28 PM PDT 24 381415265 ps
T1043 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2720841200 Aug 12 06:38:27 PM PDT 24 Aug 12 06:38:29 PM PDT 24 26075439 ps
T1044 /workspace/coverage/cover_reg_top/37.edn_intr_test.3320127683 Aug 12 06:38:32 PM PDT 24 Aug 12 06:38:33 PM PDT 24 60748939 ps
T1045 /workspace/coverage/cover_reg_top/7.edn_intr_test.2340662158 Aug 12 06:38:28 PM PDT 24 Aug 12 06:38:29 PM PDT 24 13953229 ps
T1046 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1983982731 Aug 12 06:38:25 PM PDT 24 Aug 12 06:38:26 PM PDT 24 18264867 ps
T1047 /workspace/coverage/cover_reg_top/44.edn_intr_test.2976235787 Aug 12 06:38:56 PM PDT 24 Aug 12 06:38:58 PM PDT 24 12530568 ps
T1048 /workspace/coverage/cover_reg_top/8.edn_intr_test.1888308556 Aug 12 06:38:29 PM PDT 24 Aug 12 06:38:31 PM PDT 24 14547123 ps
T1049 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2244119775 Aug 12 06:38:29 PM PDT 24 Aug 12 06:38:30 PM PDT 24 27085619 ps
T278 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3598560552 Aug 12 06:38:32 PM PDT 24 Aug 12 06:38:33 PM PDT 24 13263980 ps
T1050 /workspace/coverage/cover_reg_top/3.edn_intr_test.2385166199 Aug 12 06:38:24 PM PDT 24 Aug 12 06:38:25 PM PDT 24 25396827 ps
T1051 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1650002179 Aug 12 06:38:33 PM PDT 24 Aug 12 06:38:35 PM PDT 24 113743583 ps
T1052 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2107976156 Aug 12 06:38:27 PM PDT 24 Aug 12 06:38:29 PM PDT 24 363473383 ps
T1053 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2349107318 Aug 12 06:38:24 PM PDT 24 Aug 12 06:38:27 PM PDT 24 490389853 ps
T1054 /workspace/coverage/cover_reg_top/5.edn_intr_test.1985464620 Aug 12 06:38:31 PM PDT 24 Aug 12 06:38:32 PM PDT 24 13715389 ps
T1055 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1875033906 Aug 12 06:38:38 PM PDT 24 Aug 12 06:38:39 PM PDT 24 30513984 ps
T1056 /workspace/coverage/cover_reg_top/22.edn_intr_test.3532064039 Aug 12 06:38:44 PM PDT 24 Aug 12 06:38:45 PM PDT 24 25384315 ps
T1057 /workspace/coverage/cover_reg_top/49.edn_intr_test.607629803 Aug 12 06:38:49 PM PDT 24 Aug 12 06:38:50 PM PDT 24 40641501 ps
T1058 /workspace/coverage/cover_reg_top/21.edn_intr_test.1246542000 Aug 12 06:38:52 PM PDT 24 Aug 12 06:38:53 PM PDT 24 12885644 ps
T1059 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1395975498 Aug 12 06:38:25 PM PDT 24 Aug 12 06:38:26 PM PDT 24 31192081 ps
T1060 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1778149954 Aug 12 06:38:28 PM PDT 24 Aug 12 06:38:30 PM PDT 24 90583323 ps
T1061 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3444648170 Aug 12 06:38:40 PM PDT 24 Aug 12 06:38:41 PM PDT 24 17668722 ps
T1062 /workspace/coverage/cover_reg_top/36.edn_intr_test.1637552691 Aug 12 06:38:39 PM PDT 24 Aug 12 06:38:40 PM PDT 24 16539710 ps
T1063 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1912762866 Aug 12 06:38:32 PM PDT 24 Aug 12 06:38:33 PM PDT 24 17556502 ps
T1064 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2597702266 Aug 12 06:38:27 PM PDT 24 Aug 12 06:38:29 PM PDT 24 47984716 ps
T1065 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2562392128 Aug 12 06:38:50 PM PDT 24 Aug 12 06:38:51 PM PDT 24 117093888 ps
T1066 /workspace/coverage/cover_reg_top/20.edn_intr_test.1961408864 Aug 12 06:38:46 PM PDT 24 Aug 12 06:38:47 PM PDT 24 101589186 ps
T1067 /workspace/coverage/cover_reg_top/14.edn_intr_test.4281199996 Aug 12 06:38:45 PM PDT 24 Aug 12 06:38:46 PM PDT 24 56513743 ps
T1068 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3780147223 Aug 12 06:38:32 PM PDT 24 Aug 12 06:38:33 PM PDT 24 133934782 ps
T1069 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2320048248 Aug 12 06:38:26 PM PDT 24 Aug 12 06:38:27 PM PDT 24 20349768 ps
T1070 /workspace/coverage/cover_reg_top/42.edn_intr_test.3265564704 Aug 12 06:38:33 PM PDT 24 Aug 12 06:38:39 PM PDT 24 18647031 ps
T1071 /workspace/coverage/cover_reg_top/45.edn_intr_test.2186831035 Aug 12 06:38:59 PM PDT 24 Aug 12 06:39:00 PM PDT 24 22540047 ps
T1072 /workspace/coverage/cover_reg_top/32.edn_intr_test.2101230791 Aug 12 06:38:55 PM PDT 24 Aug 12 06:38:56 PM PDT 24 110313669 ps
T1073 /workspace/coverage/cover_reg_top/29.edn_intr_test.2677442373 Aug 12 06:39:12 PM PDT 24 Aug 12 06:39:13 PM PDT 24 21211284 ps
T309 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.117315218 Aug 12 06:38:38 PM PDT 24 Aug 12 06:38:41 PM PDT 24 258628652 ps
T1074 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2648125289 Aug 12 06:38:27 PM PDT 24 Aug 12 06:38:29 PM PDT 24 26361638 ps
T1075 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.416816605 Aug 12 06:39:10 PM PDT 24 Aug 12 06:39:13 PM PDT 24 166630283 ps
T1076 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1859416976 Aug 12 06:38:41 PM PDT 24 Aug 12 06:38:42 PM PDT 24 25385367 ps
T1077 /workspace/coverage/cover_reg_top/46.edn_intr_test.1373301957 Aug 12 06:38:59 PM PDT 24 Aug 12 06:39:00 PM PDT 24 14166868 ps
T279 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3909799962 Aug 12 06:38:15 PM PDT 24 Aug 12 06:38:16 PM PDT 24 16601547 ps
T1078 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1622094067 Aug 12 06:38:39 PM PDT 24 Aug 12 06:38:46 PM PDT 24 39457636 ps
T1079 /workspace/coverage/cover_reg_top/23.edn_intr_test.3813098363 Aug 12 06:38:46 PM PDT 24 Aug 12 06:38:47 PM PDT 24 70876442 ps
T1080 /workspace/coverage/cover_reg_top/15.edn_intr_test.3400019031 Aug 12 06:38:28 PM PDT 24 Aug 12 06:38:29 PM PDT 24 16034385 ps
T1081 /workspace/coverage/cover_reg_top/38.edn_intr_test.2408909720 Aug 12 06:38:51 PM PDT 24 Aug 12 06:38:57 PM PDT 24 15959674 ps
T1082 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2515776144 Aug 12 06:38:31 PM PDT 24 Aug 12 06:38:35 PM PDT 24 424251189 ps
T1083 /workspace/coverage/cover_reg_top/31.edn_intr_test.484412604 Aug 12 06:38:43 PM PDT 24 Aug 12 06:38:44 PM PDT 24 25272792 ps
T1084 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2630547316 Aug 12 06:38:28 PM PDT 24 Aug 12 06:38:31 PM PDT 24 58520625 ps
T280 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.815748662 Aug 12 06:38:38 PM PDT 24 Aug 12 06:38:39 PM PDT 24 143345467 ps
T1085 /workspace/coverage/cover_reg_top/19.edn_intr_test.1190702125 Aug 12 06:38:32 PM PDT 24 Aug 12 06:38:33 PM PDT 24 62166066 ps
T1086 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.134489830 Aug 12 06:38:29 PM PDT 24 Aug 12 06:38:32 PM PDT 24 157128272 ps
T1087 /workspace/coverage/cover_reg_top/12.edn_intr_test.3745435997 Aug 12 06:38:53 PM PDT 24 Aug 12 06:38:54 PM PDT 24 73715842 ps
T1088 /workspace/coverage/cover_reg_top/33.edn_intr_test.2179997378 Aug 12 06:39:01 PM PDT 24 Aug 12 06:39:02 PM PDT 24 22049560 ps
T1089 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1051853654 Aug 12 06:38:29 PM PDT 24 Aug 12 06:38:31 PM PDT 24 117280563 ps
T1090 /workspace/coverage/cover_reg_top/40.edn_intr_test.84548527 Aug 12 06:38:51 PM PDT 24 Aug 12 06:38:52 PM PDT 24 42270624 ps
T1091 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2838733370 Aug 12 06:38:59 PM PDT 24 Aug 12 06:39:01 PM PDT 24 28509601 ps
T1092 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2229917806 Aug 12 06:38:40 PM PDT 24 Aug 12 06:38:42 PM PDT 24 93547023 ps
T1093 /workspace/coverage/cover_reg_top/39.edn_intr_test.3649964832 Aug 12 06:38:48 PM PDT 24 Aug 12 06:38:49 PM PDT 24 46359171 ps
T1094 /workspace/coverage/cover_reg_top/10.edn_tl_errors.4107175611 Aug 12 06:38:28 PM PDT 24 Aug 12 06:38:30 PM PDT 24 88415369 ps
T1095 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3543890366 Aug 12 06:38:30 PM PDT 24 Aug 12 06:38:31 PM PDT 24 64235961 ps
T1096 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2433661357 Aug 12 06:38:26 PM PDT 24 Aug 12 06:38:27 PM PDT 24 18739244 ps
T1097 /workspace/coverage/cover_reg_top/0.edn_intr_test.4039182425 Aug 12 06:38:30 PM PDT 24 Aug 12 06:38:31 PM PDT 24 23762814 ps
T1098 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.443091337 Aug 12 06:38:31 PM PDT 24 Aug 12 06:38:32 PM PDT 24 172904746 ps
T1099 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2951953647 Aug 12 06:38:19 PM PDT 24 Aug 12 06:38:21 PM PDT 24 35202723 ps
T1100 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3763953791 Aug 12 06:38:44 PM PDT 24 Aug 12 06:38:45 PM PDT 24 53559259 ps
T1101 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2301209394 Aug 12 06:38:46 PM PDT 24 Aug 12 06:38:47 PM PDT 24 38668089 ps
T307 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1555077714 Aug 12 06:38:51 PM PDT 24 Aug 12 06:38:52 PM PDT 24 92653695 ps
T281 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3942312267 Aug 12 06:38:49 PM PDT 24 Aug 12 06:38:50 PM PDT 24 12787625 ps
T1102 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3892357358 Aug 12 06:38:29 PM PDT 24 Aug 12 06:38:32 PM PDT 24 297386493 ps
T1103 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2889120435 Aug 12 06:38:58 PM PDT 24 Aug 12 06:39:04 PM PDT 24 75559368 ps
T1104 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3954446417 Aug 12 06:38:29 PM PDT 24 Aug 12 06:38:30 PM PDT 24 37976550 ps
T1105 /workspace/coverage/cover_reg_top/9.edn_intr_test.210286575 Aug 12 06:38:46 PM PDT 24 Aug 12 06:38:47 PM PDT 24 20977980 ps
T1106 /workspace/coverage/cover_reg_top/47.edn_intr_test.1801210112 Aug 12 06:38:30 PM PDT 24 Aug 12 06:38:31 PM PDT 24 146229365 ps
T1107 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1913740010 Aug 12 06:38:30 PM PDT 24 Aug 12 06:38:32 PM PDT 24 62172994 ps
T1108 /workspace/coverage/cover_reg_top/11.edn_tl_errors.157158764 Aug 12 06:38:27 PM PDT 24 Aug 12 06:38:30 PM PDT 24 159007088 ps
T1109 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3971661060 Aug 12 06:38:31 PM PDT 24 Aug 12 06:38:32 PM PDT 24 16675396 ps
T1110 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3740200656 Aug 12 06:38:27 PM PDT 24 Aug 12 06:38:28 PM PDT 24 46763894 ps

Test location /workspace/coverage/default/198.edn_genbits.498517804
Short name T11
Test name
Test status
Simulation time 93237564 ps
CPU time 1.35 seconds
Started Aug 12 06:22:36 PM PDT 24
Finished Aug 12 06:22:38 PM PDT 24
Peak memory 220480 kb
Host smart-7126825c-8a8a-4e63-a3ee-1e1267ef6895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498517804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.498517804
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.23598409
Short name T29
Test name
Test status
Simulation time 48990310 ps
CPU time 1.23 seconds
Started Aug 12 06:22:08 PM PDT 24
Finished Aug 12 06:22:09 PM PDT 24
Peak memory 219788 kb
Host smart-ab1e6d09-688a-4540-a895-d905774d7b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23598409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.23598409
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2776875466
Short name T39
Test name
Test status
Simulation time 20933922648 ps
CPU time 124.55 seconds
Started Aug 12 06:21:22 PM PDT 24
Finished Aug 12 06:23:27 PM PDT 24
Peak memory 223348 kb
Host smart-148d40c1-2d76-41eb-8661-c5759c0462ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776875466 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2776875466
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1795905071
Short name T18
Test name
Test status
Simulation time 273635149 ps
CPU time 4.72 seconds
Started Aug 12 06:20:37 PM PDT 24
Finished Aug 12 06:20:42 PM PDT 24
Peak memory 242488 kb
Host smart-3eb94d0f-3e45-457d-8560-6be088b973de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795905071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1795905071
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/132.edn_genbits.3191724976
Short name T30
Test name
Test status
Simulation time 88552790 ps
CPU time 1.32 seconds
Started Aug 12 06:22:29 PM PDT 24
Finished Aug 12 06:22:35 PM PDT 24
Peak memory 219628 kb
Host smart-609ab6a1-9ab6-457e-88df-8f2d308519be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191724976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3191724976
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.322802496
Short name T5
Test name
Test status
Simulation time 24700756 ps
CPU time 0.91 seconds
Started Aug 12 06:21:47 PM PDT 24
Finished Aug 12 06:21:48 PM PDT 24
Peak memory 219276 kb
Host smart-92f9b2a2-9727-460e-a8a7-116d9783cd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322802496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.322802496
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.4280293888
Short name T207
Test name
Test status
Simulation time 38997979 ps
CPU time 1.21 seconds
Started Aug 12 06:20:56 PM PDT 24
Finished Aug 12 06:20:57 PM PDT 24
Peak memory 218816 kb
Host smart-bc945d75-2f82-4715-b094-21b46bb51e70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280293888 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.4280293888
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_regwen.3290620771
Short name T3
Test name
Test status
Simulation time 40961668 ps
CPU time 1.02 seconds
Started Aug 12 06:20:38 PM PDT 24
Finished Aug 12 06:20:39 PM PDT 24
Peak memory 207616 kb
Host smart-7d66f31c-f861-4b3e-8fd4-5115a412fd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290620771 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3290620771
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/110.edn_alert.1785148918
Short name T98
Test name
Test status
Simulation time 69433564 ps
CPU time 1.09 seconds
Started Aug 12 06:22:18 PM PDT 24
Finished Aug 12 06:22:20 PM PDT 24
Peak memory 220728 kb
Host smart-9e58581d-e946-4ea8-8d31-badc290f4127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785148918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1785148918
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/113.edn_alert.3862381574
Short name T117
Test name
Test status
Simulation time 24241279 ps
CPU time 1.17 seconds
Started Aug 12 06:22:19 PM PDT 24
Finished Aug 12 06:22:20 PM PDT 24
Peak memory 220116 kb
Host smart-c1f28428-aa82-4f0c-9279-ab960e850065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862381574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3862381574
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/139.edn_alert.4235728283
Short name T293
Test name
Test status
Simulation time 42612837 ps
CPU time 1.32 seconds
Started Aug 12 06:22:22 PM PDT 24
Finished Aug 12 06:22:23 PM PDT 24
Peak memory 220300 kb
Host smart-3b41433c-2e0a-4986-8688-10af53339639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235728283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.4235728283
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1008692639
Short name T242
Test name
Test status
Simulation time 271723385 ps
CPU time 1.59 seconds
Started Aug 12 06:38:26 PM PDT 24
Finished Aug 12 06:38:28 PM PDT 24
Peak memory 206616 kb
Host smart-3ca3b998-4035-4ae2-846e-73d58cb3c8ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008692639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1008692639
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3691925463
Short name T76
Test name
Test status
Simulation time 17986638301 ps
CPU time 159.92 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:23:59 PM PDT 24
Peak memory 223332 kb
Host smart-fb608584-f03a-4a2d-9d9f-16e8e15a34ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691925463 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3691925463
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1213557
Short name T129
Test name
Test status
Simulation time 172284702 ps
CPU time 1.1 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 218940 kb
Host smart-978f5078-bed7-4f56-9dd6-c80f07aa2fa0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213557 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disab
le_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disa
ble_auto_req_mode.1213557
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1299964992
Short name T14
Test name
Test status
Simulation time 49161649 ps
CPU time 1.1 seconds
Started Aug 12 06:21:26 PM PDT 24
Finished Aug 12 06:21:27 PM PDT 24
Peak memory 220044 kb
Host smart-56610900-487b-4de4-8ccf-53beefda129e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299964992 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1299964992
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2296850778
Short name T305
Test name
Test status
Simulation time 156300586 ps
CPU time 1.57 seconds
Started Aug 12 06:38:19 PM PDT 24
Finished Aug 12 06:38:21 PM PDT 24
Peak memory 207032 kb
Host smart-bdb30efe-59da-4114-9530-1f9374b2e25b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296850778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2296850778
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/5.edn_disable.2098706371
Short name T212
Test name
Test status
Simulation time 11619344 ps
CPU time 0.88 seconds
Started Aug 12 06:20:41 PM PDT 24
Finished Aug 12 06:20:42 PM PDT 24
Peak memory 216952 kb
Host smart-35810847-2c40-4e41-9864-c537dbd09a8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098706371 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2098706371
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable.1467058794
Short name T206
Test name
Test status
Simulation time 13727603 ps
CPU time 0.91 seconds
Started Aug 12 06:20:52 PM PDT 24
Finished Aug 12 06:20:53 PM PDT 24
Peak memory 217172 kb
Host smart-f26ac682-2ba2-4c9f-8fd6-a65a30ef6192
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467058794 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1467058794
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable.3329319037
Short name T177
Test name
Test status
Simulation time 18836012 ps
CPU time 0.85 seconds
Started Aug 12 06:21:06 PM PDT 24
Finished Aug 12 06:21:07 PM PDT 24
Peak memory 217044 kb
Host smart-3467eee5-b972-4631-aaa2-ff1e5504b708
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329319037 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3329319037
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3755662023
Short name T881
Test name
Test status
Simulation time 123361944 ps
CPU time 1.19 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 217832 kb
Host smart-0d5c9f3e-9566-4b41-894f-a76b67ca6c9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755662023 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3755662023
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/114.edn_alert.663471396
Short name T310
Test name
Test status
Simulation time 101027920 ps
CPU time 1.22 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 221956 kb
Host smart-207b45ea-5cc6-422e-b679-6526ba18bbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663471396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.663471396
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert.147528093
Short name T513
Test name
Test status
Simulation time 229254667 ps
CPU time 1.05 seconds
Started Aug 12 06:20:58 PM PDT 24
Finished Aug 12 06:20:59 PM PDT 24
Peak memory 220108 kb
Host smart-e2f4f0fb-d69c-430d-af5b-6fa295157491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147528093 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.147528093
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/144.edn_alert.1698339780
Short name T42
Test name
Test status
Simulation time 47913116 ps
CPU time 1.29 seconds
Started Aug 12 06:22:22 PM PDT 24
Finished Aug 12 06:22:23 PM PDT 24
Peak memory 219552 kb
Host smart-6c5dc5f7-4a7f-456f-bee1-29f1c77e7568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698339780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1698339780
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/265.edn_genbits.994825010
Short name T95
Test name
Test status
Simulation time 36159499 ps
CPU time 1.18 seconds
Started Aug 12 06:22:49 PM PDT 24
Finished Aug 12 06:22:50 PM PDT 24
Peak memory 219180 kb
Host smart-18a37416-3d7a-494f-a65a-ac8dc801f979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994825010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.994825010
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1316927258
Short name T195
Test name
Test status
Simulation time 210113924 ps
CPU time 1.38 seconds
Started Aug 12 06:22:13 PM PDT 24
Finished Aug 12 06:22:14 PM PDT 24
Peak memory 216096 kb
Host smart-fb0587c5-c816-4277-b83f-88d28feccea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316927258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1316927258
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/103.edn_alert.3696851678
Short name T142
Test name
Test status
Simulation time 49118221 ps
CPU time 1.14 seconds
Started Aug 12 06:22:13 PM PDT 24
Finished Aug 12 06:22:14 PM PDT 24
Peak memory 219900 kb
Host smart-90d22128-fd3d-4449-917b-e0dd4145b70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696851678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.3696851678
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/115.edn_alert.2009537015
Short name T596
Test name
Test status
Simulation time 33421103 ps
CPU time 1.27 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 216076 kb
Host smart-e8a74601-2222-438e-a9a7-fa06e5445fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009537015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.2009537015
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/116.edn_alert.517309727
Short name T702
Test name
Test status
Simulation time 26058572 ps
CPU time 1.22 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 218964 kb
Host smart-b7b089c8-33c4-47a3-a2d8-c8aa83ce3278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517309727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.517309727
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/121.edn_alert.398693450
Short name T31
Test name
Test status
Simulation time 29791654 ps
CPU time 1.23 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:13 PM PDT 24
Peak memory 220116 kb
Host smart-5aa9edea-8cb7-4700-a644-7ae07da1e8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398693450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.398693450
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert.1337316224
Short name T485
Test name
Test status
Simulation time 83519071 ps
CPU time 1.3 seconds
Started Aug 12 06:20:50 PM PDT 24
Finished Aug 12 06:20:51 PM PDT 24
Peak memory 220388 kb
Host smart-f850d459-3f57-4993-98c4-171b8e48963b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337316224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1337316224
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2637241952
Short name T135
Test name
Test status
Simulation time 96296979 ps
CPU time 1.02 seconds
Started Aug 12 06:20:51 PM PDT 24
Finished Aug 12 06:20:52 PM PDT 24
Peak memory 219792 kb
Host smart-a018d847-760a-41b0-8278-2d3b27876476
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637241952 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2637241952
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_disable.245854137
Short name T102
Test name
Test status
Simulation time 17551863 ps
CPU time 0.96 seconds
Started Aug 12 06:20:41 PM PDT 24
Finished Aug 12 06:20:42 PM PDT 24
Peak memory 219564 kb
Host smart-6f679e43-6f78-4567-954b-ad8df8a26fec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245854137 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.245854137
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/87.edn_alert.1886836535
Short name T187
Test name
Test status
Simulation time 225914571 ps
CPU time 1.27 seconds
Started Aug 12 06:22:13 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 220984 kb
Host smart-1d55e727-ac12-48cf-8342-73f46016043a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886836535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1886836535
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/0.edn_intr.2883805274
Short name T34
Test name
Test status
Simulation time 20126807 ps
CPU time 1.03 seconds
Started Aug 12 06:20:36 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 216360 kb
Host smart-ce303c7b-6e32-462c-90ba-29cda23f51c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883805274 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2883805274
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.744219677
Short name T235
Test name
Test status
Simulation time 2111812977 ps
CPU time 46.3 seconds
Started Aug 12 06:20:44 PM PDT 24
Finished Aug 12 06:21:30 PM PDT 24
Peak memory 219476 kb
Host smart-8d66a0ab-0d27-4b8f-bc05-4557137c8f7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744219677 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.744219677
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/214.edn_genbits.4099282454
Short name T96
Test name
Test status
Simulation time 41330541 ps
CPU time 1.41 seconds
Started Aug 12 06:22:52 PM PDT 24
Finished Aug 12 06:22:54 PM PDT 24
Peak memory 218960 kb
Host smart-b9c6f88e-1f1e-4db1-92c7-8475803b1f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099282454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4099282454
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_disable.282425434
Short name T224
Test name
Test status
Simulation time 26229294 ps
CPU time 0.82 seconds
Started Aug 12 06:21:44 PM PDT 24
Finished Aug 12 06:21:45 PM PDT 24
Peak memory 215828 kb
Host smart-cbd6e403-37de-4a96-86f2-773c87c774b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282425434 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.282425434
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/11.edn_intr.3759258887
Short name T36
Test name
Test status
Simulation time 32908619 ps
CPU time 0.86 seconds
Started Aug 12 06:21:00 PM PDT 24
Finished Aug 12 06:21:01 PM PDT 24
Peak memory 216344 kb
Host smart-696bddb4-12ca-4e38-979d-1e5475fa5ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759258887 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3759258887
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/102.edn_alert.4102094214
Short name T564
Test name
Test status
Simulation time 51763776 ps
CPU time 1.29 seconds
Started Aug 12 06:22:16 PM PDT 24
Finished Aug 12 06:22:18 PM PDT 24
Peak memory 216044 kb
Host smart-012992f2-806f-4fb5-99ab-8a097358a234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102094214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.4102094214
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/109.edn_alert.2504012010
Short name T295
Test name
Test status
Simulation time 65051639 ps
CPU time 1.09 seconds
Started Aug 12 06:22:21 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 218872 kb
Host smart-4b770441-931b-48f4-a6eb-719b78579612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504012010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.2504012010
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.1759920902
Short name T217
Test name
Test status
Simulation time 14767799 ps
CPU time 0.95 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 217120 kb
Host smart-3d49817b-b756-4840-bd32-fe752ae2cd48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759920902 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1759920902
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.557478175
Short name T571
Test name
Test status
Simulation time 54063619 ps
CPU time 1.18 seconds
Started Aug 12 06:20:54 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 220064 kb
Host smart-03cd70e2-6df5-4d03-9bcd-ec20178d3b6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557478175 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.557478175
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/126.edn_alert.2826731107
Short name T886
Test name
Test status
Simulation time 97235962 ps
CPU time 1.18 seconds
Started Aug 12 06:22:46 PM PDT 24
Finished Aug 12 06:22:47 PM PDT 24
Peak memory 220056 kb
Host smart-d1b589cc-34f8-41d5-bac2-f99a1fd48a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826731107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2826731107
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/17.edn_disable.1156762667
Short name T211
Test name
Test status
Simulation time 89409014 ps
CPU time 0.84 seconds
Started Aug 12 06:20:56 PM PDT 24
Finished Aug 12 06:20:57 PM PDT 24
Peak memory 218772 kb
Host smart-5b76662e-be85-4513-93d3-010c0236f132
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156762667 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1156762667
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.2729830787
Short name T203
Test name
Test status
Simulation time 24745311 ps
CPU time 0.92 seconds
Started Aug 12 06:21:14 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 220156 kb
Host smart-c2ad7df9-00e5-41fc-ba62-05e2f5339754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729830787 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2729830787
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/35.edn_err.2983634910
Short name T170
Test name
Test status
Simulation time 19717749 ps
CPU time 1.11 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:48 PM PDT 24
Peak memory 219192 kb
Host smart-4bab6049-7007-424f-ad06-9c0eb91f88d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983634910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2983634910
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/36.edn_disable.2269995729
Short name T194
Test name
Test status
Simulation time 27186797 ps
CPU time 0.82 seconds
Started Aug 12 06:21:29 PM PDT 24
Finished Aug 12 06:21:30 PM PDT 24
Peak memory 216968 kb
Host smart-e5c11004-ae0e-4658-972f-9e8edf0a721d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269995729 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2269995729
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/46.edn_err.287010217
Short name T199
Test name
Test status
Simulation time 30831833 ps
CPU time 0.96 seconds
Started Aug 12 06:21:51 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 224176 kb
Host smart-7fdb222e-c5a9-44d4-8a7d-6382d50280a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287010217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.287010217
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.4025977176
Short name T24
Test name
Test status
Simulation time 40892390 ps
CPU time 1.1 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 219312 kb
Host smart-f26b3151-c247-4cc4-b239-d661ee06307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025977176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.4025977176
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert_test.1061586770
Short name T83
Test name
Test status
Simulation time 81638367 ps
CPU time 0.81 seconds
Started Aug 12 06:20:51 PM PDT 24
Finished Aug 12 06:20:52 PM PDT 24
Peak memory 206840 kb
Host smart-5b999bfe-a188-42c4-836c-4c790f0bde13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061586770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1061586770
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3909799962
Short name T279
Test name
Test status
Simulation time 16601547 ps
CPU time 0.89 seconds
Started Aug 12 06:38:15 PM PDT 24
Finished Aug 12 06:38:16 PM PDT 24
Peak memory 206548 kb
Host smart-cbe9fdfc-3f10-4231-a2f6-b258559b19ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909799962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3909799962
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.117315218
Short name T309
Test name
Test status
Simulation time 258628652 ps
CPU time 2.33 seconds
Started Aug 12 06:38:38 PM PDT 24
Finished Aug 12 06:38:41 PM PDT 24
Peak memory 214868 kb
Host smart-f9642c35-d701-452f-9816-9da912ca149a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117315218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.117315218
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/102.edn_genbits.3741979136
Short name T343
Test name
Test status
Simulation time 27446476 ps
CPU time 1.19 seconds
Started Aug 12 06:22:13 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 220296 kb
Host smart-847ab86a-0503-478e-920e-6045d3ee698d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741979136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3741979136
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1427916803
Short name T647
Test name
Test status
Simulation time 49917575 ps
CPU time 1.27 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 217828 kb
Host smart-98b3404c-697b-4a4a-86fa-9527fac41be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427916803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1427916803
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2384670394
Short name T349
Test name
Test status
Simulation time 75896208 ps
CPU time 2.7 seconds
Started Aug 12 06:22:59 PM PDT 24
Finished Aug 12 06:23:02 PM PDT 24
Peak memory 218924 kb
Host smart-09c8094b-2921-43ec-84aa-bfd47aa2a66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384670394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2384670394
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.924401909
Short name T288
Test name
Test status
Simulation time 22852855 ps
CPU time 1.01 seconds
Started Aug 12 06:38:35 PM PDT 24
Finished Aug 12 06:38:36 PM PDT 24
Peak memory 206728 kb
Host smart-642201af-58d2-4804-bc40-5cb2810359b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924401909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.924401909
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.edn_regwen.1376476378
Short name T722
Test name
Test status
Simulation time 29654160 ps
CPU time 0.95 seconds
Started Aug 12 06:20:34 PM PDT 24
Finished Aug 12 06:20:35 PM PDT 24
Peak memory 207488 kb
Host smart-a921dbab-a534-4fbd-8a78-64c1b7c5d5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376476378 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1376476378
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/100.edn_genbits.3691499256
Short name T333
Test name
Test status
Simulation time 38776211 ps
CPU time 1.63 seconds
Started Aug 12 06:22:08 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 218860 kb
Host smart-8117adeb-e8e7-452c-a1f5-9e25dcd97d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691499256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3691499256
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_genbits.2861267317
Short name T712
Test name
Test status
Simulation time 89987621 ps
CPU time 1.29 seconds
Started Aug 12 06:21:08 PM PDT 24
Finished Aug 12 06:21:09 PM PDT 24
Peak memory 217676 kb
Host smart-31e4ccfa-1989-4240-b00b-8088a8d6f4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861267317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2861267317
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.681777591
Short name T859
Test name
Test status
Simulation time 72938329 ps
CPU time 1.57 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 218860 kb
Host smart-1772c67b-97c6-4308-93b8-512f8a748f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681777591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.681777591
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_genbits.4040392091
Short name T853
Test name
Test status
Simulation time 48294533 ps
CPU time 1.56 seconds
Started Aug 12 06:20:54 PM PDT 24
Finished Aug 12 06:20:55 PM PDT 24
Peak memory 218620 kb
Host smart-3f2b90d1-43d6-41e3-aa7f-8c5b30a2f904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040392091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.4040392091
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3083677019
Short name T40
Test name
Test status
Simulation time 1576809461 ps
CPU time 40.54 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:21:36 PM PDT 24
Peak memory 217236 kb
Host smart-05dcf767-af3e-4fbe-9467-0b61da2da078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083677019 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3083677019
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/183.edn_genbits.3349840379
Short name T334
Test name
Test status
Simulation time 147647632 ps
CPU time 1.65 seconds
Started Aug 12 06:22:40 PM PDT 24
Finished Aug 12 06:22:41 PM PDT 24
Peak memory 218060 kb
Host smart-11fa5312-844e-423c-ab24-9a86eeff12e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349840379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3349840379
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3836718598
Short name T331
Test name
Test status
Simulation time 45402034 ps
CPU time 1.65 seconds
Started Aug 12 06:22:49 PM PDT 24
Finished Aug 12 06:22:51 PM PDT 24
Peak memory 220456 kb
Host smart-35a554af-eea0-4a3d-9216-37624d3f0e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836718598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3836718598
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3972922342
Short name T338
Test name
Test status
Simulation time 36287996 ps
CPU time 1.69 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:56 PM PDT 24
Peak memory 219016 kb
Host smart-71de9629-e5a9-40bf-acc9-7d558de6eb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972922342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3972922342
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_genbits.3531835443
Short name T77
Test name
Test status
Simulation time 49440952 ps
CPU time 1.19 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:47 PM PDT 24
Peak memory 219296 kb
Host smart-3c483c8d-40e1-4b98-84b5-df9273ab75aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531835443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3531835443
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2072968447
Short name T107
Test name
Test status
Simulation time 22746552 ps
CPU time 1.02 seconds
Started Aug 12 06:21:01 PM PDT 24
Finished Aug 12 06:21:03 PM PDT 24
Peak memory 216352 kb
Host smart-69623380-b35d-44f7-9635-9588dd1e6ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072968447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2072968447
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/164.edn_genbits.837823161
Short name T55
Test name
Test status
Simulation time 46741832 ps
CPU time 1.55 seconds
Started Aug 12 06:22:36 PM PDT 24
Finished Aug 12 06:22:38 PM PDT 24
Peak memory 219068 kb
Host smart-7e1a9854-809a-4459-8a49-7771fb12b521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837823161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.837823161
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.4123015390
Short name T120
Test name
Test status
Simulation time 30582738 ps
CPU time 0.92 seconds
Started Aug 12 06:20:56 PM PDT 24
Finished Aug 12 06:20:57 PM PDT 24
Peak memory 216280 kb
Host smart-641c18f6-bc2e-4661-8e03-93be4662bb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123015390 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.4123015390
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/114.edn_genbits.3655811841
Short name T837
Test name
Test status
Simulation time 73769141 ps
CPU time 1.49 seconds
Started Aug 12 06:22:10 PM PDT 24
Finished Aug 12 06:22:12 PM PDT 24
Peak memory 220092 kb
Host smart-d76719c2-84c5-49e6-acf6-1989fc871e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655811841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3655811841
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_err.1570884510
Short name T362
Test name
Test status
Simulation time 46580432 ps
CPU time 0.95 seconds
Started Aug 12 06:20:54 PM PDT 24
Finished Aug 12 06:20:55 PM PDT 24
Peak memory 219280 kb
Host smart-e6090e3e-2841-4743-8964-47358cffc5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570884510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1570884510
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2320048248
Short name T1069
Test name
Test status
Simulation time 20349768 ps
CPU time 1.3 seconds
Started Aug 12 06:38:26 PM PDT 24
Finished Aug 12 06:38:27 PM PDT 24
Peak memory 206576 kb
Host smart-257a7fd5-0285-43bd-a4db-638b42b14112
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320048248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2320048248
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.388254514
Short name T1003
Test name
Test status
Simulation time 238710630 ps
CPU time 3.27 seconds
Started Aug 12 06:38:26 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 206736 kb
Host smart-1116a518-4dfc-4ec6-abb6-2e567708b61a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388254514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.388254514
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2015589200
Short name T991
Test name
Test status
Simulation time 35791020 ps
CPU time 0.92 seconds
Started Aug 12 06:38:09 PM PDT 24
Finished Aug 12 06:38:11 PM PDT 24
Peak memory 206744 kb
Host smart-029a32d5-6d9c-4b2f-9224-6fc6785b25af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015589200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2015589200
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4085406613
Short name T978
Test name
Test status
Simulation time 23657044 ps
CPU time 1.18 seconds
Started Aug 12 06:38:23 PM PDT 24
Finished Aug 12 06:38:24 PM PDT 24
Peak memory 217044 kb
Host smart-a54fd0e4-9d04-4674-99e1-476ae1ea98bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085406613 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.4085406613
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3886696392
Short name T271
Test name
Test status
Simulation time 19263968 ps
CPU time 0.93 seconds
Started Aug 12 06:38:04 PM PDT 24
Finished Aug 12 06:38:05 PM PDT 24
Peak memory 206612 kb
Host smart-069da9e0-cd9a-4b13-9812-89b116ec8dc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886696392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3886696392
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.4039182425
Short name T1097
Test name
Test status
Simulation time 23762814 ps
CPU time 0.81 seconds
Started Aug 12 06:38:30 PM PDT 24
Finished Aug 12 06:38:31 PM PDT 24
Peak memory 206604 kb
Host smart-621db6c7-8388-4a9e-8d53-7d4aec91c55b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039182425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.4039182425
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2429825383
Short name T1029
Test name
Test status
Simulation time 30702800 ps
CPU time 1.26 seconds
Started Aug 12 06:38:27 PM PDT 24
Finished Aug 12 06:38:28 PM PDT 24
Peak memory 206688 kb
Host smart-3ce5f497-2cbf-4fef-8032-4195d9dfa660
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429825383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2429825383
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2720841200
Short name T1043
Test name
Test status
Simulation time 26075439 ps
CPU time 1.83 seconds
Started Aug 12 06:38:27 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 218684 kb
Host smart-3a095924-9789-43b6-b231-e7233456d277
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720841200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2720841200
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3276750366
Short name T984
Test name
Test status
Simulation time 30683088 ps
CPU time 1.03 seconds
Started Aug 12 06:38:31 PM PDT 24
Finished Aug 12 06:38:32 PM PDT 24
Peak memory 206604 kb
Host smart-cf2d3c5f-f8dd-42a2-83bf-b9dabaa38ea9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276750366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3276750366
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2951953647
Short name T1099
Test name
Test status
Simulation time 35202723 ps
CPU time 2.07 seconds
Started Aug 12 06:38:19 PM PDT 24
Finished Aug 12 06:38:21 PM PDT 24
Peak memory 206672 kb
Host smart-20f33331-0465-4a61-8e22-a4564e16aab6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951953647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2951953647
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1913740010
Short name T1107
Test name
Test status
Simulation time 62172994 ps
CPU time 1.31 seconds
Started Aug 12 06:38:30 PM PDT 24
Finished Aug 12 06:38:32 PM PDT 24
Peak memory 217952 kb
Host smart-931bc72e-3c19-452d-ba36-ee494a80c08f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913740010 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1913740010
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.345677524
Short name T1005
Test name
Test status
Simulation time 49672062 ps
CPU time 0.95 seconds
Started Aug 12 06:38:20 PM PDT 24
Finished Aug 12 06:38:21 PM PDT 24
Peak memory 206628 kb
Host smart-126e9d9f-9d3e-43e2-9a38-d871550334a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345677524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.345677524
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1470821526
Short name T1013
Test name
Test status
Simulation time 21285309 ps
CPU time 0.83 seconds
Started Aug 12 06:38:20 PM PDT 24
Finished Aug 12 06:38:20 PM PDT 24
Peak memory 206496 kb
Host smart-599b872f-436d-4efb-a6f1-d35f7bf1cddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470821526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1470821526
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1424034018
Short name T980
Test name
Test status
Simulation time 227348613 ps
CPU time 2.36 seconds
Started Aug 12 06:38:15 PM PDT 24
Finished Aug 12 06:38:17 PM PDT 24
Peak memory 214956 kb
Host smart-d9ca422c-a051-4e36-a167-83e555e19079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424034018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1424034018
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.893687610
Short name T298
Test name
Test status
Simulation time 997347111 ps
CPU time 2.16 seconds
Started Aug 12 06:38:34 PM PDT 24
Finished Aug 12 06:38:36 PM PDT 24
Peak memory 206736 kb
Host smart-df41b055-5c7b-4bef-bc2b-f78dafec437f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893687610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.893687610
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2775696665
Short name T1026
Test name
Test status
Simulation time 38705003 ps
CPU time 1.12 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:31 PM PDT 24
Peak memory 216804 kb
Host smart-61160fe7-5923-414c-a48d-bb3591f0d857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775696665 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2775696665
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2838733370
Short name T1091
Test name
Test status
Simulation time 28509601 ps
CPU time 0.89 seconds
Started Aug 12 06:38:59 PM PDT 24
Finished Aug 12 06:39:01 PM PDT 24
Peak memory 206540 kb
Host smart-ea561ae1-937c-46b7-8f1a-3fcc77a45276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838733370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2838733370
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2719975157
Short name T1034
Test name
Test status
Simulation time 26783668 ps
CPU time 0.92 seconds
Started Aug 12 06:38:27 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 206532 kb
Host smart-ffbb5b82-adcf-4733-859e-0390bc200457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719975157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2719975157
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.512512826
Short name T283
Test name
Test status
Simulation time 23086396 ps
CPU time 0.94 seconds
Started Aug 12 06:38:39 PM PDT 24
Finished Aug 12 06:38:40 PM PDT 24
Peak memory 206760 kb
Host smart-1809f26d-41f9-4a2f-8ea1-734b50d501d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512512826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.512512826
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.4107175611
Short name T1094
Test name
Test status
Simulation time 88415369 ps
CPU time 1.58 seconds
Started Aug 12 06:38:28 PM PDT 24
Finished Aug 12 06:38:30 PM PDT 24
Peak memory 214856 kb
Host smart-88c83d72-2d21-4fea-a410-111917342784
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107175611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.4107175611
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2229917806
Short name T1092
Test name
Test status
Simulation time 93547023 ps
CPU time 1.72 seconds
Started Aug 12 06:38:40 PM PDT 24
Finished Aug 12 06:38:42 PM PDT 24
Peak memory 214876 kb
Host smart-cd24955b-f334-4369-8106-422ff1a0708b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229917806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2229917806
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1995917888
Short name T995
Test name
Test status
Simulation time 25048526 ps
CPU time 1.54 seconds
Started Aug 12 06:38:49 PM PDT 24
Finished Aug 12 06:38:51 PM PDT 24
Peak memory 219020 kb
Host smart-30f6be42-88eb-4a0a-830f-fd4a7fc23d2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995917888 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1995917888
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3942312267
Short name T281
Test name
Test status
Simulation time 12787625 ps
CPU time 0.96 seconds
Started Aug 12 06:38:49 PM PDT 24
Finished Aug 12 06:38:50 PM PDT 24
Peak memory 206620 kb
Host smart-0b218d38-f059-4576-881d-fb319c7d8fc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942312267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3942312267
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1468259876
Short name T1019
Test name
Test status
Simulation time 15846886 ps
CPU time 0.82 seconds
Started Aug 12 06:38:31 PM PDT 24
Finished Aug 12 06:38:32 PM PDT 24
Peak memory 206588 kb
Host smart-35a3577d-d0e3-4ecd-b8d3-99e8a2216476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468259876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1468259876
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3790693194
Short name T1004
Test name
Test status
Simulation time 36677537 ps
CPU time 1.17 seconds
Started Aug 12 06:38:49 PM PDT 24
Finished Aug 12 06:38:50 PM PDT 24
Peak memory 206616 kb
Host smart-e69aa356-eb68-4814-8bdc-0cf3f6f09ccf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790693194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3790693194
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.157158764
Short name T1108
Test name
Test status
Simulation time 159007088 ps
CPU time 1.95 seconds
Started Aug 12 06:38:27 PM PDT 24
Finished Aug 12 06:38:30 PM PDT 24
Peak memory 214852 kb
Host smart-61e45c31-851e-4ed4-97df-e3107e003670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157158764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.157158764
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.134489830
Short name T1086
Test name
Test status
Simulation time 157128272 ps
CPU time 2.4 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:32 PM PDT 24
Peak memory 206732 kb
Host smart-808e3b71-cf88-4f01-ac4a-c4ca459fb4ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134489830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.134489830
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2889120435
Short name T1103
Test name
Test status
Simulation time 75559368 ps
CPU time 1.08 seconds
Started Aug 12 06:38:58 PM PDT 24
Finished Aug 12 06:39:04 PM PDT 24
Peak memory 214968 kb
Host smart-702983a9-3043-4ce9-873d-a503d5b368b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889120435 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2889120435
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1848970182
Short name T277
Test name
Test status
Simulation time 207975588 ps
CPU time 0.9 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:30 PM PDT 24
Peak memory 206620 kb
Host smart-7ad9acba-36d5-44af-91ac-2f55aa5c28f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848970182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1848970182
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3745435997
Short name T1087
Test name
Test status
Simulation time 73715842 ps
CPU time 0.89 seconds
Started Aug 12 06:38:53 PM PDT 24
Finished Aug 12 06:38:54 PM PDT 24
Peak memory 206560 kb
Host smart-bfa4c452-4e82-4695-8f6d-c4d39a086019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745435997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3745435997
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2842032108
Short name T285
Test name
Test status
Simulation time 43836687 ps
CPU time 0.92 seconds
Started Aug 12 06:38:46 PM PDT 24
Finished Aug 12 06:38:47 PM PDT 24
Peak memory 206640 kb
Host smart-365be998-846a-447e-8b76-a554de69cc42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842032108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2842032108
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.339907600
Short name T1012
Test name
Test status
Simulation time 105575012 ps
CPU time 2.66 seconds
Started Aug 12 06:38:46 PM PDT 24
Finished Aug 12 06:38:48 PM PDT 24
Peak memory 214860 kb
Host smart-a767d6e8-43cb-4e62-b8fd-90ebdcb8534a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339907600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.339907600
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.416816605
Short name T1075
Test name
Test status
Simulation time 166630283 ps
CPU time 2.19 seconds
Started Aug 12 06:39:10 PM PDT 24
Finished Aug 12 06:39:13 PM PDT 24
Peak memory 207032 kb
Host smart-e753ed73-b8b5-4df8-b73c-06e5c07b3636
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416816605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.416816605
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1912762866
Short name T1063
Test name
Test status
Simulation time 17556502 ps
CPU time 1.04 seconds
Started Aug 12 06:38:32 PM PDT 24
Finished Aug 12 06:38:33 PM PDT 24
Peak memory 215040 kb
Host smart-20419f5d-3822-4e96-86fe-fe96aea6eac1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912762866 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1912762866
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3436002166
Short name T269
Test name
Test status
Simulation time 14306536 ps
CPU time 0.89 seconds
Started Aug 12 06:38:42 PM PDT 24
Finished Aug 12 06:38:43 PM PDT 24
Peak memory 206604 kb
Host smart-6e83c1f1-c216-4dd2-9ace-fbb76ba73e3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436002166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3436002166
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.4153480853
Short name T1014
Test name
Test status
Simulation time 35215434 ps
CPU time 0.81 seconds
Started Aug 12 06:38:38 PM PDT 24
Finished Aug 12 06:38:39 PM PDT 24
Peak memory 206360 kb
Host smart-feb476cd-81c8-4384-9198-6cec435da1fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153480853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.4153480853
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3911193432
Short name T290
Test name
Test status
Simulation time 91352977 ps
CPU time 1.22 seconds
Started Aug 12 06:38:49 PM PDT 24
Finished Aug 12 06:38:51 PM PDT 24
Peak memory 206768 kb
Host smart-94f04bfe-c7b3-40f8-b99e-d2b7e6117cb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911193432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3911193432
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2648125289
Short name T1074
Test name
Test status
Simulation time 26361638 ps
CPU time 1.38 seconds
Started Aug 12 06:38:27 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 214940 kb
Host smart-93820201-ad04-4c05-9f48-6936112c3409
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648125289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2648125289
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2107976156
Short name T1052
Test name
Test status
Simulation time 363473383 ps
CPU time 2.37 seconds
Started Aug 12 06:38:27 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 206760 kb
Host smart-21a4a620-7ed4-4cd7-b27d-2d28a96fc167
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107976156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2107976156
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1778149954
Short name T1060
Test name
Test status
Simulation time 90583323 ps
CPU time 1.39 seconds
Started Aug 12 06:38:28 PM PDT 24
Finished Aug 12 06:38:30 PM PDT 24
Peak memory 214964 kb
Host smart-59448263-5ec6-41c3-a266-4d7edfbcceda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778149954 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1778149954
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3954446417
Short name T1104
Test name
Test status
Simulation time 37976550 ps
CPU time 0.8 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:30 PM PDT 24
Peak memory 206344 kb
Host smart-6add225f-9b10-426e-969d-b26d282806e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954446417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3954446417
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.4281199996
Short name T1067
Test name
Test status
Simulation time 56513743 ps
CPU time 0.84 seconds
Started Aug 12 06:38:45 PM PDT 24
Finished Aug 12 06:38:46 PM PDT 24
Peak memory 206552 kb
Host smart-53979a9b-705a-4708-baff-3adc4cd1f001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281199996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.4281199996
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3485445204
Short name T286
Test name
Test status
Simulation time 18586117 ps
CPU time 1.07 seconds
Started Aug 12 06:38:37 PM PDT 24
Finished Aug 12 06:38:39 PM PDT 24
Peak memory 206632 kb
Host smart-a86328e5-1347-473f-a095-6a9951ca410a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485445204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3485445204
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3301438887
Short name T1017
Test name
Test status
Simulation time 48891672 ps
CPU time 1.8 seconds
Started Aug 12 06:38:35 PM PDT 24
Finished Aug 12 06:38:37 PM PDT 24
Peak memory 214832 kb
Host smart-10a09a36-d788-455d-9b4a-0b4166d6e994
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301438887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3301438887
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1930411393
Short name T263
Test name
Test status
Simulation time 191093440 ps
CPU time 1.62 seconds
Started Aug 12 06:38:30 PM PDT 24
Finished Aug 12 06:38:32 PM PDT 24
Peak memory 206624 kb
Host smart-38597d3e-51dd-44d8-b586-9095dbd15fda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930411393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1930411393
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2762751746
Short name T1042
Test name
Test status
Simulation time 381415265 ps
CPU time 1.33 seconds
Started Aug 12 06:38:27 PM PDT 24
Finished Aug 12 06:38:28 PM PDT 24
Peak memory 214908 kb
Host smart-bef85ecc-55ce-4cf3-8ebf-5874fb4d95e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762751746 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2762751746
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.381402169
Short name T275
Test name
Test status
Simulation time 14610560 ps
CPU time 0.91 seconds
Started Aug 12 06:38:41 PM PDT 24
Finished Aug 12 06:38:42 PM PDT 24
Peak memory 206596 kb
Host smart-8698f2f2-6cf5-4990-ad12-84bfd3c4c8a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381402169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.381402169
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3400019031
Short name T1080
Test name
Test status
Simulation time 16034385 ps
CPU time 0.94 seconds
Started Aug 12 06:38:28 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 206528 kb
Host smart-5993686a-4c27-491b-b5fb-30721ec1ea82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400019031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3400019031
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3444648170
Short name T1061
Test name
Test status
Simulation time 17668722 ps
CPU time 1 seconds
Started Aug 12 06:38:40 PM PDT 24
Finished Aug 12 06:38:41 PM PDT 24
Peak memory 206616 kb
Host smart-77258773-dc6e-46c9-b482-a274bf80e00e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444648170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3444648170
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2258597025
Short name T1030
Test name
Test status
Simulation time 55570659 ps
CPU time 2.2 seconds
Started Aug 12 06:38:50 PM PDT 24
Finished Aug 12 06:38:53 PM PDT 24
Peak memory 214852 kb
Host smart-67a7ca25-0322-430f-b3da-ac2e1efdbfbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258597025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2258597025
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.532197513
Short name T993
Test name
Test status
Simulation time 31364369 ps
CPU time 2.1 seconds
Started Aug 12 06:38:57 PM PDT 24
Finished Aug 12 06:38:59 PM PDT 24
Peak memory 215004 kb
Host smart-5594cb75-7cbf-4a12-a87f-2fd4c321df0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532197513 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.532197513
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2301209394
Short name T1101
Test name
Test status
Simulation time 38668089 ps
CPU time 0.86 seconds
Started Aug 12 06:38:46 PM PDT 24
Finished Aug 12 06:38:47 PM PDT 24
Peak memory 206428 kb
Host smart-c22cc9e3-ff26-4d21-bc58-87bd244bbe66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301209394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2301209394
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3192942904
Short name T999
Test name
Test status
Simulation time 13277660 ps
CPU time 0.87 seconds
Started Aug 12 06:38:53 PM PDT 24
Finished Aug 12 06:38:54 PM PDT 24
Peak memory 206556 kb
Host smart-e79147c0-d728-484d-b32a-8394f664f8d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192942904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3192942904
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1859416976
Short name T1076
Test name
Test status
Simulation time 25385367 ps
CPU time 1.17 seconds
Started Aug 12 06:38:41 PM PDT 24
Finished Aug 12 06:38:42 PM PDT 24
Peak memory 206696 kb
Host smart-6f653e17-4234-493e-a733-7afec47df33b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859416976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1859416976
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2070936017
Short name T243
Test name
Test status
Simulation time 73066654 ps
CPU time 2.71 seconds
Started Aug 12 06:38:28 PM PDT 24
Finished Aug 12 06:38:31 PM PDT 24
Peak memory 214948 kb
Host smart-4dcd4ba1-8c66-40e0-861b-89c5e18adaa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070936017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2070936017
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.458349577
Short name T306
Test name
Test status
Simulation time 252278359 ps
CPU time 1.48 seconds
Started Aug 12 06:38:37 PM PDT 24
Finished Aug 12 06:38:39 PM PDT 24
Peak memory 206804 kb
Host smart-ec013c1b-4f74-454c-b48e-d3832acb6946
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458349577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.458349577
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1173229898
Short name T983
Test name
Test status
Simulation time 76922007 ps
CPU time 0.94 seconds
Started Aug 12 06:38:47 PM PDT 24
Finished Aug 12 06:38:48 PM PDT 24
Peak memory 214956 kb
Host smart-a323bdef-4343-4f53-be3c-2a5ba9695761
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173229898 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1173229898
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2762474496
Short name T270
Test name
Test status
Simulation time 16120996 ps
CPU time 0.92 seconds
Started Aug 12 06:38:33 PM PDT 24
Finished Aug 12 06:38:34 PM PDT 24
Peak memory 206616 kb
Host smart-41a6d07e-b5c7-4792-83d5-363093aca3c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762474496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2762474496
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1388206830
Short name T979
Test name
Test status
Simulation time 21575863 ps
CPU time 0.86 seconds
Started Aug 12 06:38:32 PM PDT 24
Finished Aug 12 06:38:33 PM PDT 24
Peak memory 206508 kb
Host smart-adf274ee-e007-4ef3-9400-293018058dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388206830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1388206830
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1824755936
Short name T1025
Test name
Test status
Simulation time 54538291 ps
CPU time 1.3 seconds
Started Aug 12 06:38:56 PM PDT 24
Finished Aug 12 06:38:58 PM PDT 24
Peak memory 206640 kb
Host smart-593689ad-9899-4969-b5ee-e335b66ede95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824755936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1824755936
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3779966157
Short name T1009
Test name
Test status
Simulation time 102668132 ps
CPU time 3.35 seconds
Started Aug 12 06:38:51 PM PDT 24
Finished Aug 12 06:38:55 PM PDT 24
Peak memory 215060 kb
Host smart-2bd11474-93b6-450c-8e2b-19a04bcda2b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779966157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3779966157
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3362680607
Short name T299
Test name
Test status
Simulation time 109913502 ps
CPU time 2.07 seconds
Started Aug 12 06:38:49 PM PDT 24
Finished Aug 12 06:38:52 PM PDT 24
Peak memory 206740 kb
Host smart-719dd6b0-f763-4b1e-9f43-97fe18e7bf1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362680607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3362680607
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2562392128
Short name T1065
Test name
Test status
Simulation time 117093888 ps
CPU time 1.4 seconds
Started Aug 12 06:38:50 PM PDT 24
Finished Aug 12 06:38:51 PM PDT 24
Peak memory 217968 kb
Host smart-eb52bb4a-c890-4ff1-9533-5219f423e016
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562392128 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2562392128
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1037811980
Short name T998
Test name
Test status
Simulation time 16200333 ps
CPU time 0.94 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:31 PM PDT 24
Peak memory 206672 kb
Host smart-99795430-21b8-43bf-bbb1-4360112726ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037811980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1037811980
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1925523077
Short name T1011
Test name
Test status
Simulation time 14536825 ps
CPU time 0.84 seconds
Started Aug 12 06:38:53 PM PDT 24
Finished Aug 12 06:38:54 PM PDT 24
Peak memory 206536 kb
Host smart-305851ba-02d8-498b-a4b6-cbf042467c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925523077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1925523077
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4067299466
Short name T289
Test name
Test status
Simulation time 89387500 ps
CPU time 1.09 seconds
Started Aug 12 06:38:31 PM PDT 24
Finished Aug 12 06:38:32 PM PDT 24
Peak memory 206672 kb
Host smart-9cb7de8c-6219-4614-a759-8e56ba7dab49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067299466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.4067299466
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2168463788
Short name T997
Test name
Test status
Simulation time 30596629 ps
CPU time 1.93 seconds
Started Aug 12 06:38:57 PM PDT 24
Finished Aug 12 06:38:59 PM PDT 24
Peak memory 214884 kb
Host smart-ce7dd078-ded3-4105-814b-3a06cbeb8423
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168463788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2168463788
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1650002179
Short name T1051
Test name
Test status
Simulation time 113743583 ps
CPU time 1.61 seconds
Started Aug 12 06:38:33 PM PDT 24
Finished Aug 12 06:38:35 PM PDT 24
Peak memory 207008 kb
Host smart-d23c7083-70cc-4462-b6cb-7f0ea23c5762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650002179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1650002179
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3543890366
Short name T1095
Test name
Test status
Simulation time 64235961 ps
CPU time 0.99 seconds
Started Aug 12 06:38:30 PM PDT 24
Finished Aug 12 06:38:31 PM PDT 24
Peak memory 214856 kb
Host smart-bd6c8466-d856-4551-b9ef-147c99858e62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543890366 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3543890366
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.423115572
Short name T274
Test name
Test status
Simulation time 41913480 ps
CPU time 0.84 seconds
Started Aug 12 06:39:01 PM PDT 24
Finished Aug 12 06:39:02 PM PDT 24
Peak memory 206580 kb
Host smart-60ff5f3a-e651-4e5a-9c6e-469505c50084
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423115572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.423115572
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1190702125
Short name T1085
Test name
Test status
Simulation time 62166066 ps
CPU time 0.84 seconds
Started Aug 12 06:38:32 PM PDT 24
Finished Aug 12 06:38:33 PM PDT 24
Peak memory 206352 kb
Host smart-316ed833-72a2-4c34-b78c-4477f78ed520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190702125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1190702125
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1622094067
Short name T1078
Test name
Test status
Simulation time 39457636 ps
CPU time 1.36 seconds
Started Aug 12 06:38:39 PM PDT 24
Finished Aug 12 06:38:46 PM PDT 24
Peak memory 206704 kb
Host smart-31a55f05-68b6-4aa4-9b78-e6d4b398a8f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622094067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1622094067
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2615795041
Short name T1016
Test name
Test status
Simulation time 55983647 ps
CPU time 2.26 seconds
Started Aug 12 06:38:47 PM PDT 24
Finished Aug 12 06:38:50 PM PDT 24
Peak memory 214880 kb
Host smart-37183257-110f-4792-9a45-f78accac207d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615795041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2615795041
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1740164253
Short name T1010
Test name
Test status
Simulation time 652623258 ps
CPU time 2.4 seconds
Started Aug 12 06:38:50 PM PDT 24
Finished Aug 12 06:38:52 PM PDT 24
Peak memory 206872 kb
Host smart-981f925b-5903-4165-a8df-e3664ec6ff11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740164253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1740164253
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1066463177
Short name T272
Test name
Test status
Simulation time 35601706 ps
CPU time 1.43 seconds
Started Aug 12 06:38:25 PM PDT 24
Finished Aug 12 06:38:28 PM PDT 24
Peak memory 206624 kb
Host smart-060c7526-0e39-4b5d-9972-b1973100cba7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066463177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1066463177
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2926824860
Short name T994
Test name
Test status
Simulation time 458755497 ps
CPU time 3.39 seconds
Started Aug 12 06:38:26 PM PDT 24
Finished Aug 12 06:38:30 PM PDT 24
Peak memory 206604 kb
Host smart-5f8ab992-5886-4bf8-a98b-101e20b612a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926824860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2926824860
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3314371863
Short name T992
Test name
Test status
Simulation time 43886026 ps
CPU time 0.83 seconds
Started Aug 12 06:38:25 PM PDT 24
Finished Aug 12 06:38:26 PM PDT 24
Peak memory 206432 kb
Host smart-f10ed4a6-dd43-4bc4-864f-8790213851b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314371863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3314371863
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3796100404
Short name T982
Test name
Test status
Simulation time 31110250 ps
CPU time 1.4 seconds
Started Aug 12 06:38:28 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 218236 kb
Host smart-36b5b48b-0872-4332-b8f5-070dd9fe06b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796100404 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3796100404
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3683080619
Short name T273
Test name
Test status
Simulation time 36473824 ps
CPU time 0.87 seconds
Started Aug 12 06:38:27 PM PDT 24
Finished Aug 12 06:38:28 PM PDT 24
Peak memory 206408 kb
Host smart-8282038d-07d0-4eec-9cbe-54f67e1d4781
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683080619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3683080619
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2334827015
Short name T1031
Test name
Test status
Simulation time 38275339 ps
CPU time 0.82 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:30 PM PDT 24
Peak memory 206392 kb
Host smart-583843d7-6409-432b-82e5-a215987430fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334827015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2334827015
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1395975498
Short name T1059
Test name
Test status
Simulation time 31192081 ps
CPU time 1.13 seconds
Started Aug 12 06:38:25 PM PDT 24
Finished Aug 12 06:38:26 PM PDT 24
Peak memory 206728 kb
Host smart-498641fc-1195-4f1c-94b3-76f9c7cc0bfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395975498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1395975498
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1051853654
Short name T1089
Test name
Test status
Simulation time 117280563 ps
CPU time 2.1 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:31 PM PDT 24
Peak memory 214856 kb
Host smart-fb3e69a6-a221-4825-9cf3-965129c2f270
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051853654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1051853654
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3780147223
Short name T1068
Test name
Test status
Simulation time 133934782 ps
CPU time 1.61 seconds
Started Aug 12 06:38:32 PM PDT 24
Finished Aug 12 06:38:33 PM PDT 24
Peak memory 206876 kb
Host smart-bf8a2759-6ca1-41a0-b25f-c2a01a99bb37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780147223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3780147223
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1961408864
Short name T1066
Test name
Test status
Simulation time 101589186 ps
CPU time 0.8 seconds
Started Aug 12 06:38:46 PM PDT 24
Finished Aug 12 06:38:47 PM PDT 24
Peak memory 206356 kb
Host smart-7243373b-eaf5-40a1-8794-d37f237cf847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961408864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1961408864
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1246542000
Short name T1058
Test name
Test status
Simulation time 12885644 ps
CPU time 0.86 seconds
Started Aug 12 06:38:52 PM PDT 24
Finished Aug 12 06:38:53 PM PDT 24
Peak memory 206532 kb
Host smart-f2cf5b29-0352-4cf2-b20f-26ac5c7d8d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246542000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1246542000
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3532064039
Short name T1056
Test name
Test status
Simulation time 25384315 ps
CPU time 0.83 seconds
Started Aug 12 06:38:44 PM PDT 24
Finished Aug 12 06:38:45 PM PDT 24
Peak memory 206524 kb
Host smart-9b801189-561e-480e-9316-159e0e151499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532064039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3532064039
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3813098363
Short name T1079
Test name
Test status
Simulation time 70876442 ps
CPU time 0.88 seconds
Started Aug 12 06:38:46 PM PDT 24
Finished Aug 12 06:38:47 PM PDT 24
Peak memory 206532 kb
Host smart-ced832ab-e0e2-47c2-8709-7a23f158815a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813098363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3813098363
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1369559556
Short name T988
Test name
Test status
Simulation time 21518817 ps
CPU time 0.81 seconds
Started Aug 12 06:38:57 PM PDT 24
Finished Aug 12 06:38:58 PM PDT 24
Peak memory 206540 kb
Host smart-132ad1af-8e8a-4be9-9e3c-3533f9b42d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369559556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1369559556
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.985894975
Short name T1023
Test name
Test status
Simulation time 39353348 ps
CPU time 0.8 seconds
Started Aug 12 06:38:52 PM PDT 24
Finished Aug 12 06:38:53 PM PDT 24
Peak memory 206356 kb
Host smart-a207df3d-783f-484b-800d-5ee874a1922d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985894975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.985894975
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2309071198
Short name T1022
Test name
Test status
Simulation time 42230125 ps
CPU time 0.8 seconds
Started Aug 12 06:38:52 PM PDT 24
Finished Aug 12 06:38:53 PM PDT 24
Peak memory 206356 kb
Host smart-aab84cd3-1436-463c-9f17-58258193605a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309071198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2309071198
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3172933684
Short name T996
Test name
Test status
Simulation time 19594783 ps
CPU time 0.86 seconds
Started Aug 12 06:38:49 PM PDT 24
Finished Aug 12 06:38:50 PM PDT 24
Peak memory 206528 kb
Host smart-147b3af0-9e1b-468c-b38f-ac7fa42e5f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172933684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3172933684
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.865729438
Short name T1036
Test name
Test status
Simulation time 39442072 ps
CPU time 0.81 seconds
Started Aug 12 06:38:51 PM PDT 24
Finished Aug 12 06:38:52 PM PDT 24
Peak memory 206572 kb
Host smart-35306db8-894c-41bc-9669-5c4337b48fef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865729438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.865729438
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2677442373
Short name T1073
Test name
Test status
Simulation time 21211284 ps
CPU time 0.83 seconds
Started Aug 12 06:39:12 PM PDT 24
Finished Aug 12 06:39:13 PM PDT 24
Peak memory 206372 kb
Host smart-5ba8013f-3509-4cba-9a70-389e5cf90df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677442373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2677442373
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.751294079
Short name T987
Test name
Test status
Simulation time 185708222 ps
CPU time 2.87 seconds
Started Aug 12 06:38:20 PM PDT 24
Finished Aug 12 06:38:23 PM PDT 24
Peak memory 206600 kb
Host smart-96501fc0-e62a-4fd7-8d30-d39e04148c10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751294079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.751294079
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3971661060
Short name T1109
Test name
Test status
Simulation time 16675396 ps
CPU time 0.93 seconds
Started Aug 12 06:38:31 PM PDT 24
Finished Aug 12 06:38:32 PM PDT 24
Peak memory 206620 kb
Host smart-177914a5-fa27-4a2f-b803-37229f117430
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971661060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3971661060
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1983982731
Short name T1046
Test name
Test status
Simulation time 18264867 ps
CPU time 1.23 seconds
Started Aug 12 06:38:25 PM PDT 24
Finished Aug 12 06:38:26 PM PDT 24
Peak memory 214960 kb
Host smart-08f8ed45-2a71-417a-85ca-ed3fc937c6fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983982731 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1983982731
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1967662597
Short name T1001
Test name
Test status
Simulation time 23973081 ps
CPU time 0.87 seconds
Started Aug 12 06:38:24 PM PDT 24
Finished Aug 12 06:38:25 PM PDT 24
Peak memory 206624 kb
Host smart-643f89ad-9697-475f-a949-1762a8379cd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967662597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1967662597
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2385166199
Short name T1050
Test name
Test status
Simulation time 25396827 ps
CPU time 0.87 seconds
Started Aug 12 06:38:24 PM PDT 24
Finished Aug 12 06:38:25 PM PDT 24
Peak memory 206496 kb
Host smart-dedb76f6-d42b-46f2-8497-97467427e4a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385166199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2385166199
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2433661357
Short name T1096
Test name
Test status
Simulation time 18739244 ps
CPU time 1.12 seconds
Started Aug 12 06:38:26 PM PDT 24
Finished Aug 12 06:38:27 PM PDT 24
Peak memory 206740 kb
Host smart-1e462d97-5413-466c-b68c-98a39fad211d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433661357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2433661357
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3765449306
Short name T990
Test name
Test status
Simulation time 171038232 ps
CPU time 3.47 seconds
Started Aug 12 06:38:28 PM PDT 24
Finished Aug 12 06:38:31 PM PDT 24
Peak memory 214960 kb
Host smart-f237aaf5-7d23-4028-93c4-41c6e5f36344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765449306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3765449306
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3844314337
Short name T1035
Test name
Test status
Simulation time 321693213 ps
CPU time 2.14 seconds
Started Aug 12 06:38:37 PM PDT 24
Finished Aug 12 06:38:39 PM PDT 24
Peak memory 214892 kb
Host smart-8d0ce93a-c054-4c94-b12f-01e021064961
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844314337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3844314337
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1759042526
Short name T1020
Test name
Test status
Simulation time 30821897 ps
CPU time 0.83 seconds
Started Aug 12 06:38:33 PM PDT 24
Finished Aug 12 06:38:34 PM PDT 24
Peak memory 206564 kb
Host smart-041fd880-65d2-4efe-b7c2-2c207e1e7a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759042526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1759042526
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.484412604
Short name T1083
Test name
Test status
Simulation time 25272792 ps
CPU time 0.83 seconds
Started Aug 12 06:38:43 PM PDT 24
Finished Aug 12 06:38:44 PM PDT 24
Peak memory 206540 kb
Host smart-48c20c30-3dc0-4913-a8f2-d7643ec2174b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484412604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.484412604
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2101230791
Short name T1072
Test name
Test status
Simulation time 110313669 ps
CPU time 0.88 seconds
Started Aug 12 06:38:55 PM PDT 24
Finished Aug 12 06:38:56 PM PDT 24
Peak memory 206336 kb
Host smart-2a9d431e-68da-42a6-b0ea-9e65757e9d4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101230791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2101230791
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2179997378
Short name T1088
Test name
Test status
Simulation time 22049560 ps
CPU time 0.89 seconds
Started Aug 12 06:39:01 PM PDT 24
Finished Aug 12 06:39:02 PM PDT 24
Peak memory 206508 kb
Host smart-2daad0a0-906b-4574-bafa-4f21c4c0c211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179997378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2179997378
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1547165411
Short name T1008
Test name
Test status
Simulation time 33996874 ps
CPU time 0.8 seconds
Started Aug 12 06:38:49 PM PDT 24
Finished Aug 12 06:38:50 PM PDT 24
Peak memory 206392 kb
Host smart-1228def1-4b98-4cb1-9ad5-6b69728dbe54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547165411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1547165411
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2035694065
Short name T1037
Test name
Test status
Simulation time 40652275 ps
CPU time 0.75 seconds
Started Aug 12 06:38:33 PM PDT 24
Finished Aug 12 06:38:34 PM PDT 24
Peak memory 206268 kb
Host smart-414347bf-272e-45dc-8b15-cb23b7dc3866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035694065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2035694065
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1637552691
Short name T1062
Test name
Test status
Simulation time 16539710 ps
CPU time 0.92 seconds
Started Aug 12 06:38:39 PM PDT 24
Finished Aug 12 06:38:40 PM PDT 24
Peak memory 206444 kb
Host smart-a30aff72-146b-4bc3-8655-3d0248afc32a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637552691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1637552691
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3320127683
Short name T1044
Test name
Test status
Simulation time 60748939 ps
CPU time 0.91 seconds
Started Aug 12 06:38:32 PM PDT 24
Finished Aug 12 06:38:33 PM PDT 24
Peak memory 206372 kb
Host smart-e2d5ea31-86a1-45dc-b921-6ca0dcabc0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320127683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3320127683
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2408909720
Short name T1081
Test name
Test status
Simulation time 15959674 ps
CPU time 0.92 seconds
Started Aug 12 06:38:51 PM PDT 24
Finished Aug 12 06:38:57 PM PDT 24
Peak memory 206524 kb
Host smart-263ecde9-b01b-4d53-bac5-39a91e9c34cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408909720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2408909720
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3649964832
Short name T1093
Test name
Test status
Simulation time 46359171 ps
CPU time 0.8 seconds
Started Aug 12 06:38:48 PM PDT 24
Finished Aug 12 06:38:49 PM PDT 24
Peak memory 206272 kb
Host smart-c2281e7d-1936-41e9-baeb-996130c27b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649964832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3649964832
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.815748662
Short name T280
Test name
Test status
Simulation time 143345467 ps
CPU time 1.63 seconds
Started Aug 12 06:38:38 PM PDT 24
Finished Aug 12 06:38:39 PM PDT 24
Peak memory 206660 kb
Host smart-0940015f-04d3-452f-a29e-752593d0ddb6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815748662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.815748662
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2287289520
Short name T1028
Test name
Test status
Simulation time 63343554 ps
CPU time 1.95 seconds
Started Aug 12 06:38:34 PM PDT 24
Finished Aug 12 06:38:36 PM PDT 24
Peak memory 206676 kb
Host smart-5f78459c-4066-4a9f-930b-d77574c1fd57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287289520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2287289520
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.601966034
Short name T1040
Test name
Test status
Simulation time 16952266 ps
CPU time 0.98 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:31 PM PDT 24
Peak memory 206620 kb
Host smart-b38bb23d-03ee-4033-91e7-ec5553ac4e6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601966034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.601966034
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.518990281
Short name T985
Test name
Test status
Simulation time 95042921 ps
CPU time 1.03 seconds
Started Aug 12 06:38:25 PM PDT 24
Finished Aug 12 06:38:27 PM PDT 24
Peak memory 214876 kb
Host smart-1b8ba178-1baa-4661-a77e-58f951d79262
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518990281 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.518990281
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2244119775
Short name T1049
Test name
Test status
Simulation time 27085619 ps
CPU time 0.88 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:30 PM PDT 24
Peak memory 206584 kb
Host smart-e2544404-0fad-489e-88b4-e33afa2af6ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244119775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2244119775
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3512702440
Short name T986
Test name
Test status
Simulation time 27509140 ps
CPU time 0.92 seconds
Started Aug 12 06:38:45 PM PDT 24
Finished Aug 12 06:38:46 PM PDT 24
Peak memory 206548 kb
Host smart-e51886b8-3a0c-468a-8840-414146865049
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512702440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3512702440
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2180945158
Short name T1006
Test name
Test status
Simulation time 33742645 ps
CPU time 0.99 seconds
Started Aug 12 06:38:36 PM PDT 24
Finished Aug 12 06:38:37 PM PDT 24
Peak memory 206672 kb
Host smart-366a15c6-9e09-4099-b945-f6a5bba46c3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180945158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2180945158
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2349107318
Short name T1053
Test name
Test status
Simulation time 490389853 ps
CPU time 2.91 seconds
Started Aug 12 06:38:24 PM PDT 24
Finished Aug 12 06:38:27 PM PDT 24
Peak memory 214908 kb
Host smart-8a9b56f7-152c-411d-9351-719a2f10298e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349107318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2349107318
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3745167790
Short name T308
Test name
Test status
Simulation time 121411513 ps
CPU time 2.58 seconds
Started Aug 12 06:38:30 PM PDT 24
Finished Aug 12 06:38:33 PM PDT 24
Peak memory 206684 kb
Host smart-ef7e7a53-a937-4561-981f-ea61b0871d36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745167790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3745167790
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.84548527
Short name T1090
Test name
Test status
Simulation time 42270624 ps
CPU time 0.82 seconds
Started Aug 12 06:38:51 PM PDT 24
Finished Aug 12 06:38:52 PM PDT 24
Peak memory 206512 kb
Host smart-f570b1ad-d8c9-4570-85cb-475177dc3374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84548527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.84548527
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1552616987
Short name T1015
Test name
Test status
Simulation time 19330543 ps
CPU time 0.88 seconds
Started Aug 12 06:39:01 PM PDT 24
Finished Aug 12 06:39:02 PM PDT 24
Peak memory 206552 kb
Host smart-fc89badb-86ba-4fd8-b1db-97faf6e59ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552616987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1552616987
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3265564704
Short name T1070
Test name
Test status
Simulation time 18647031 ps
CPU time 0.89 seconds
Started Aug 12 06:38:33 PM PDT 24
Finished Aug 12 06:38:39 PM PDT 24
Peak memory 206556 kb
Host smart-8ddc0431-d38e-404f-b4aa-bc6665ac7291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265564704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3265564704
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2495923303
Short name T1038
Test name
Test status
Simulation time 12456337 ps
CPU time 0.85 seconds
Started Aug 12 06:38:55 PM PDT 24
Finished Aug 12 06:38:56 PM PDT 24
Peak memory 206552 kb
Host smart-60a8215d-7e4e-48a1-8deb-c00766624cbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495923303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2495923303
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2976235787
Short name T1047
Test name
Test status
Simulation time 12530568 ps
CPU time 0.87 seconds
Started Aug 12 06:38:56 PM PDT 24
Finished Aug 12 06:38:58 PM PDT 24
Peak memory 206540 kb
Host smart-97103346-9cca-4058-a8ba-dcc66079aafc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976235787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2976235787
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2186831035
Short name T1071
Test name
Test status
Simulation time 22540047 ps
CPU time 0.87 seconds
Started Aug 12 06:38:59 PM PDT 24
Finished Aug 12 06:39:00 PM PDT 24
Peak memory 206508 kb
Host smart-6abdce5e-c71b-4b5f-8126-4be3bc76a6dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186831035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2186831035
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1373301957
Short name T1077
Test name
Test status
Simulation time 14166868 ps
CPU time 0.89 seconds
Started Aug 12 06:38:59 PM PDT 24
Finished Aug 12 06:39:00 PM PDT 24
Peak memory 206560 kb
Host smart-b358ab47-642e-4a17-9188-77b4670fc17f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373301957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1373301957
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1801210112
Short name T1106
Test name
Test status
Simulation time 146229365 ps
CPU time 0.9 seconds
Started Aug 12 06:38:30 PM PDT 24
Finished Aug 12 06:38:31 PM PDT 24
Peak memory 206388 kb
Host smart-6f0d1e63-9dfb-4ba8-8fb0-32bb95a189a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801210112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1801210112
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.212522254
Short name T1000
Test name
Test status
Simulation time 33219891 ps
CPU time 0.83 seconds
Started Aug 12 06:38:53 PM PDT 24
Finished Aug 12 06:38:54 PM PDT 24
Peak memory 206416 kb
Host smart-a5e05845-d9e4-44bf-9cfc-a0046f26d692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212522254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.212522254
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.607629803
Short name T1057
Test name
Test status
Simulation time 40641501 ps
CPU time 0.83 seconds
Started Aug 12 06:38:49 PM PDT 24
Finished Aug 12 06:38:50 PM PDT 24
Peak memory 206528 kb
Host smart-269c7cdc-591f-4549-b7cf-9366b7b3f9cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607629803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.607629803
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3266287203
Short name T989
Test name
Test status
Simulation time 28682108 ps
CPU time 1.28 seconds
Started Aug 12 06:38:27 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 217956 kb
Host smart-c93002f3-1b3a-4492-a5c2-96b24fce6267
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266287203 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3266287203
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2680449324
Short name T1024
Test name
Test status
Simulation time 16414034 ps
CPU time 0.95 seconds
Started Aug 12 06:38:25 PM PDT 24
Finished Aug 12 06:38:26 PM PDT 24
Peak memory 206608 kb
Host smart-6947a252-8062-4ae6-b879-e5fc52e15f4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680449324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2680449324
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1985464620
Short name T1054
Test name
Test status
Simulation time 13715389 ps
CPU time 0.86 seconds
Started Aug 12 06:38:31 PM PDT 24
Finished Aug 12 06:38:32 PM PDT 24
Peak memory 206564 kb
Host smart-d21de3ab-40e0-411d-8a1c-73436d5a4b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985464620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1985464620
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1889603464
Short name T284
Test name
Test status
Simulation time 18969355 ps
CPU time 1.14 seconds
Started Aug 12 06:38:40 PM PDT 24
Finished Aug 12 06:38:41 PM PDT 24
Peak memory 206728 kb
Host smart-ac4a7464-4d84-42fd-aeeb-c6f6b6c64bae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889603464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1889603464
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2515776144
Short name T1082
Test name
Test status
Simulation time 424251189 ps
CPU time 4 seconds
Started Aug 12 06:38:31 PM PDT 24
Finished Aug 12 06:38:35 PM PDT 24
Peak memory 214904 kb
Host smart-03fd988a-8e98-4c01-86f7-cf2c237fa3eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515776144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2515776144
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1117222873
Short name T1032
Test name
Test status
Simulation time 183451209 ps
CPU time 1.66 seconds
Started Aug 12 06:38:42 PM PDT 24
Finished Aug 12 06:38:43 PM PDT 24
Peak memory 206920 kb
Host smart-a9ac7380-3ee9-41e4-bf6e-957fb3d17c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117222873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1117222873
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3763953791
Short name T1100
Test name
Test status
Simulation time 53559259 ps
CPU time 1.37 seconds
Started Aug 12 06:38:44 PM PDT 24
Finished Aug 12 06:38:45 PM PDT 24
Peak memory 217912 kb
Host smart-89f23661-b974-44f7-968f-a3d7b8f886b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763953791 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3763953791
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2514662220
Short name T1018
Test name
Test status
Simulation time 14399409 ps
CPU time 0.9 seconds
Started Aug 12 06:38:41 PM PDT 24
Finished Aug 12 06:38:42 PM PDT 24
Peak memory 206624 kb
Host smart-ba55f510-c7e3-49de-ba08-6b18d3364c26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514662220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2514662220
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.62108613
Short name T1033
Test name
Test status
Simulation time 13721657 ps
CPU time 0.89 seconds
Started Aug 12 06:38:28 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 206532 kb
Host smart-9cfcdd5e-39a7-4af4-ae48-579ce901aea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62108613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.62108613
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4006757216
Short name T287
Test name
Test status
Simulation time 20483848 ps
CPU time 1.13 seconds
Started Aug 12 06:38:28 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 206688 kb
Host smart-4333f968-b54b-4b1a-9b46-a79404ad3fb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006757216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.4006757216
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3892357358
Short name T1102
Test name
Test status
Simulation time 297386493 ps
CPU time 2.61 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:32 PM PDT 24
Peak memory 214896 kb
Host smart-cccb8a11-1945-43bf-8a82-beea94eb07fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892357358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3892357358
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2630547316
Short name T1084
Test name
Test status
Simulation time 58520625 ps
CPU time 1.81 seconds
Started Aug 12 06:38:28 PM PDT 24
Finished Aug 12 06:38:31 PM PDT 24
Peak memory 206904 kb
Host smart-400a8b01-ea2b-45b6-a34a-9d4a0fb8dc41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630547316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2630547316
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1632743077
Short name T1021
Test name
Test status
Simulation time 60263847 ps
CPU time 1.55 seconds
Started Aug 12 06:38:38 PM PDT 24
Finished Aug 12 06:38:40 PM PDT 24
Peak memory 214936 kb
Host smart-f742309e-f5af-49e9-862e-a0620a4a6438
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632743077 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1632743077
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1438884789
Short name T276
Test name
Test status
Simulation time 30653935 ps
CPU time 0.84 seconds
Started Aug 12 06:38:28 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 206268 kb
Host smart-b3167db1-a8ac-4de7-a29c-d6567757b2c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438884789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1438884789
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2340662158
Short name T1045
Test name
Test status
Simulation time 13953229 ps
CPU time 0.93 seconds
Started Aug 12 06:38:28 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 206532 kb
Host smart-324ace6d-0bcb-434b-a7d2-b1489f1407db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340662158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2340662158
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1983085502
Short name T282
Test name
Test status
Simulation time 15752908 ps
CPU time 1.03 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:30 PM PDT 24
Peak memory 206848 kb
Host smart-5b4d6b1b-f692-4db2-ac10-ab4edb466ea6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983085502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1983085502
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2597702266
Short name T1064
Test name
Test status
Simulation time 47984716 ps
CPU time 1.92 seconds
Started Aug 12 06:38:27 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 218508 kb
Host smart-3016f361-a8c9-4865-bb31-91ababce8208
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597702266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2597702266
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.443091337
Short name T1098
Test name
Test status
Simulation time 172904746 ps
CPU time 1.64 seconds
Started Aug 12 06:38:31 PM PDT 24
Finished Aug 12 06:38:32 PM PDT 24
Peak memory 206752 kb
Host smart-28512165-861b-478c-9a5e-0b1b29ebc73e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443091337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.443091337
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3771936134
Short name T1039
Test name
Test status
Simulation time 31901517 ps
CPU time 1.23 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:30 PM PDT 24
Peak memory 215000 kb
Host smart-f493e053-17b3-43b2-9499-5227ee6d61f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771936134 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3771936134
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3598560552
Short name T278
Test name
Test status
Simulation time 13263980 ps
CPU time 0.9 seconds
Started Aug 12 06:38:32 PM PDT 24
Finished Aug 12 06:38:33 PM PDT 24
Peak memory 206584 kb
Host smart-98b2a10b-d74b-4d17-937d-486b85945fc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598560552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3598560552
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1888308556
Short name T1048
Test name
Test status
Simulation time 14547123 ps
CPU time 0.91 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:31 PM PDT 24
Peak memory 206564 kb
Host smart-d3c63fd7-a154-4afe-bcd6-ee6de34b4afd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888308556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1888308556
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3394041677
Short name T1027
Test name
Test status
Simulation time 172398752 ps
CPU time 1.41 seconds
Started Aug 12 06:38:45 PM PDT 24
Finished Aug 12 06:38:47 PM PDT 24
Peak memory 206684 kb
Host smart-b39d1882-b23e-4274-aead-095f4d27d0d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394041677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3394041677
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1297372996
Short name T981
Test name
Test status
Simulation time 39594240 ps
CPU time 2.65 seconds
Started Aug 12 06:38:43 PM PDT 24
Finished Aug 12 06:38:46 PM PDT 24
Peak memory 214884 kb
Host smart-3c8b7de2-929c-4224-aa8a-16b1e12599e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297372996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1297372996
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1555077714
Short name T307
Test name
Test status
Simulation time 92653695 ps
CPU time 1.61 seconds
Started Aug 12 06:38:51 PM PDT 24
Finished Aug 12 06:38:52 PM PDT 24
Peak memory 206648 kb
Host smart-43d545fd-e168-4a67-8829-e292bbb31537
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555077714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1555077714
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.711077361
Short name T1007
Test name
Test status
Simulation time 24559165 ps
CPU time 1.63 seconds
Started Aug 12 06:38:27 PM PDT 24
Finished Aug 12 06:38:29 PM PDT 24
Peak memory 215004 kb
Host smart-3ff84337-632d-4ba4-b76f-3a0bfb875770
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711077361 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.711077361
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3740200656
Short name T1110
Test name
Test status
Simulation time 46763894 ps
CPU time 0.91 seconds
Started Aug 12 06:38:27 PM PDT 24
Finished Aug 12 06:38:28 PM PDT 24
Peak memory 206432 kb
Host smart-2e51ea71-11f7-41ab-9511-26f2d7c3aa09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740200656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3740200656
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.210286575
Short name T1105
Test name
Test status
Simulation time 20977980 ps
CPU time 0.83 seconds
Started Aug 12 06:38:46 PM PDT 24
Finished Aug 12 06:38:47 PM PDT 24
Peak memory 206552 kb
Host smart-237c52bf-6d6a-4d9f-be56-aa2dbcd56b0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210286575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.210286575
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1875033906
Short name T1055
Test name
Test status
Simulation time 30513984 ps
CPU time 1.33 seconds
Started Aug 12 06:38:38 PM PDT 24
Finished Aug 12 06:38:39 PM PDT 24
Peak memory 206712 kb
Host smart-65b2edf8-2004-4795-bfcc-74cf5a9eed18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875033906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1875033906
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1413653875
Short name T1002
Test name
Test status
Simulation time 38748763 ps
CPU time 2.59 seconds
Started Aug 12 06:38:29 PM PDT 24
Finished Aug 12 06:38:32 PM PDT 24
Peak memory 214968 kb
Host smart-d8b49085-2e26-408e-b7ab-6aea5e4bc33a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413653875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1413653875
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.498221197
Short name T1041
Test name
Test status
Simulation time 89987807 ps
CPU time 1.51 seconds
Started Aug 12 06:38:50 PM PDT 24
Finished Aug 12 06:38:51 PM PDT 24
Peak memory 206828 kb
Host smart-91b41cbf-7637-48d7-9891-331e8a08a50e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498221197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.498221197
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2877756276
Short name T404
Test name
Test status
Simulation time 26546926 ps
CPU time 1.12 seconds
Started Aug 12 06:20:33 PM PDT 24
Finished Aug 12 06:20:35 PM PDT 24
Peak memory 219172 kb
Host smart-5e717003-747c-4bee-848c-b5861944e236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877756276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2877756276
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2989592033
Short name T473
Test name
Test status
Simulation time 17750939 ps
CPU time 1.06 seconds
Started Aug 12 06:20:34 PM PDT 24
Finished Aug 12 06:20:35 PM PDT 24
Peak memory 207304 kb
Host smart-3f74e07a-e518-465e-8323-e02f53b82254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989592033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2989592033
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3678884636
Short name T933
Test name
Test status
Simulation time 22499935 ps
CPU time 0.95 seconds
Started Aug 12 06:20:38 PM PDT 24
Finished Aug 12 06:20:39 PM PDT 24
Peak memory 215808 kb
Host smart-1acf4fb2-590a-4e43-adba-908a286f48a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678884636 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3678884636
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2297573068
Short name T929
Test name
Test status
Simulation time 38075081 ps
CPU time 1.28 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 219948 kb
Host smart-8dd94ef4-ed1b-432e-830f-6a6ccf99d8ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297573068 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2297573068
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1639718922
Short name T438
Test name
Test status
Simulation time 25698660 ps
CPU time 0.95 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:36 PM PDT 24
Peak memory 219168 kb
Host smart-050bb5a3-144f-40eb-a4be-82c45f688b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639718922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1639718922
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2577502536
Short name T80
Test name
Test status
Simulation time 72893491 ps
CPU time 1.27 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 219104 kb
Host smart-7bea02a0-f874-4e75-86c6-9d22e9208d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577502536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2577502536
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_smoke.1902588015
Short name T686
Test name
Test status
Simulation time 15166002 ps
CPU time 0.97 seconds
Started Aug 12 06:20:36 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 215680 kb
Host smart-0540a314-59c5-4cdc-94e1-1e90bb6baa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902588015 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1902588015
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.500705729
Short name T257
Test name
Test status
Simulation time 255580378 ps
CPU time 2.66 seconds
Started Aug 12 06:20:34 PM PDT 24
Finished Aug 12 06:20:36 PM PDT 24
Peak memory 220772 kb
Host smart-7f5ae11f-69b2-4211-a3f0-ab5b96a7a7c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500705729 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.500705729
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.986697176
Short name T829
Test name
Test status
Simulation time 3090226573 ps
CPU time 75.63 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 218616 kb
Host smart-13e89a6b-ab2d-41f0-b5a1-5b2c56e923af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986697176 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.986697176
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.3778494387
Short name T921
Test name
Test status
Simulation time 98824090 ps
CPU time 1.17 seconds
Started Aug 12 06:20:36 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 219388 kb
Host smart-1b9577b5-e5b0-4ce2-8ca9-1583b224ec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778494387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3778494387
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3745230501
Short name T517
Test name
Test status
Simulation time 48003557 ps
CPU time 0.96 seconds
Started Aug 12 06:20:37 PM PDT 24
Finished Aug 12 06:20:38 PM PDT 24
Peak memory 207224 kb
Host smart-531bd789-f95f-489e-a583-d1e36c9cd68a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745230501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3745230501
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.978435937
Short name T654
Test name
Test status
Simulation time 13224843 ps
CPU time 0.94 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 207852 kb
Host smart-8266e5e3-5e74-49a4-ad43-675981a0e51b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978435937 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.978435937
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1293136568
Short name T976
Test name
Test status
Simulation time 44901226 ps
CPU time 1.32 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 220500 kb
Host smart-466d2e44-2fcc-40e7-b74b-b914a1340fb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293136568 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1293136568
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2500230532
Short name T551
Test name
Test status
Simulation time 20264524 ps
CPU time 1.09 seconds
Started Aug 12 06:20:36 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 219048 kb
Host smart-f348a421-bf62-48ba-ae07-390cc740b380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500230532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2500230532
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.277473673
Short name T695
Test name
Test status
Simulation time 99817212 ps
CPU time 1.5 seconds
Started Aug 12 06:20:40 PM PDT 24
Finished Aug 12 06:20:42 PM PDT 24
Peak memory 219228 kb
Host smart-1ea79344-ae90-49f5-88e8-b3f9e40f5c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277473673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.277473673
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1689642663
Short name T766
Test name
Test status
Simulation time 24670000 ps
CPU time 0.99 seconds
Started Aug 12 06:20:33 PM PDT 24
Finished Aug 12 06:20:35 PM PDT 24
Peak memory 215960 kb
Host smart-efbd6bf2-d57f-4420-a56f-dab96b724b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689642663 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1689642663
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.486518581
Short name T71
Test name
Test status
Simulation time 3557499330 ps
CPU time 5.27 seconds
Started Aug 12 06:20:42 PM PDT 24
Finished Aug 12 06:20:47 PM PDT 24
Peak memory 241532 kb
Host smart-48f0007f-0490-4e41-892a-a064454d5ff9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486518581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.486518581
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1458318914
Short name T429
Test name
Test status
Simulation time 16243120 ps
CPU time 0.97 seconds
Started Aug 12 06:20:34 PM PDT 24
Finished Aug 12 06:20:35 PM PDT 24
Peak memory 215624 kb
Host smart-68eb0cf9-23da-4784-8b55-03ba556b3020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458318914 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1458318914
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2983983676
Short name T533
Test name
Test status
Simulation time 484043203 ps
CPU time 5.43 seconds
Started Aug 12 06:20:38 PM PDT 24
Finished Aug 12 06:20:43 PM PDT 24
Peak memory 217584 kb
Host smart-706f52b0-0107-4ca4-9e1b-906c73e410c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983983676 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2983983676
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2260447347
Short name T791
Test name
Test status
Simulation time 5434771569 ps
CPU time 149.82 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:23:05 PM PDT 24
Peak memory 222356 kb
Host smart-9d5fff69-4265-4e9d-ba1a-a3ed3f2ece7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260447347 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2260447347
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1042885854
Short name T680
Test name
Test status
Simulation time 54996739 ps
CPU time 1.26 seconds
Started Aug 12 06:20:50 PM PDT 24
Finished Aug 12 06:20:52 PM PDT 24
Peak memory 216080 kb
Host smart-8bd6425a-2349-4454-9c75-a6a540fb2a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042885854 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1042885854
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2502283439
Short name T880
Test name
Test status
Simulation time 27244138 ps
CPU time 0.89 seconds
Started Aug 12 06:20:57 PM PDT 24
Finished Aug 12 06:20:58 PM PDT 24
Peak memory 207232 kb
Host smart-15190c8f-e61d-47b7-8a74-1ebf9e8f6f0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502283439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2502283439
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1916050473
Short name T890
Test name
Test status
Simulation time 70045015 ps
CPU time 1.17 seconds
Started Aug 12 06:20:59 PM PDT 24
Finished Aug 12 06:21:01 PM PDT 24
Peak memory 218980 kb
Host smart-06642488-b06e-4492-a71b-0a9ee2d9a9c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916050473 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1916050473
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3389029229
Short name T670
Test name
Test status
Simulation time 78334042 ps
CPU time 0.86 seconds
Started Aug 12 06:20:46 PM PDT 24
Finished Aug 12 06:20:47 PM PDT 24
Peak memory 219124 kb
Host smart-cdd2f4c8-0e6f-48c7-93f1-ffab77c5257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389029229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3389029229
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3678344497
Short name T620
Test name
Test status
Simulation time 25143850 ps
CPU time 1.15 seconds
Started Aug 12 06:20:49 PM PDT 24
Finished Aug 12 06:20:50 PM PDT 24
Peak memory 217720 kb
Host smart-decd053b-7a57-4831-b846-661b17ed1a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678344497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3678344497
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.670188296
Short name T264
Test name
Test status
Simulation time 25413678 ps
CPU time 0.94 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 215980 kb
Host smart-82c1ee0b-c410-4b47-820b-1d93bdb99e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670188296 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.670188296
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3508096401
Short name T624
Test name
Test status
Simulation time 40834362 ps
CPU time 0.93 seconds
Started Aug 12 06:20:45 PM PDT 24
Finished Aug 12 06:20:46 PM PDT 24
Peak memory 215476 kb
Host smart-a3a5b9a0-daf9-4354-a474-f2650462d688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508096401 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3508096401
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3389522097
Short name T326
Test name
Test status
Simulation time 479299038 ps
CPU time 2.8 seconds
Started Aug 12 06:20:47 PM PDT 24
Finished Aug 12 06:20:50 PM PDT 24
Peak memory 217620 kb
Host smart-16087a1b-48e4-4b35-9179-0e7fc0020883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389522097 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3389522097
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_alert.1628765591
Short name T311
Test name
Test status
Simulation time 42140662 ps
CPU time 1.13 seconds
Started Aug 12 06:22:18 PM PDT 24
Finished Aug 12 06:22:19 PM PDT 24
Peak memory 219348 kb
Host smart-24c2538d-62cb-4908-bd05-f818489f4ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628765591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.1628765591
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/101.edn_alert.189481997
Short name T201
Test name
Test status
Simulation time 69056610 ps
CPU time 1.14 seconds
Started Aug 12 06:22:09 PM PDT 24
Finished Aug 12 06:22:10 PM PDT 24
Peak memory 219648 kb
Host smart-08cc3ae2-24ce-4f25-9e8e-b1d6439d67a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189481997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.189481997
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.4273491502
Short name T786
Test name
Test status
Simulation time 32201361 ps
CPU time 1.31 seconds
Started Aug 12 06:22:22 PM PDT 24
Finished Aug 12 06:22:23 PM PDT 24
Peak memory 220036 kb
Host smart-7870d650-057a-4bec-9729-b03ae3980ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273491502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.4273491502
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.543313443
Short name T667
Test name
Test status
Simulation time 37148258 ps
CPU time 0.99 seconds
Started Aug 12 06:22:11 PM PDT 24
Finished Aug 12 06:22:12 PM PDT 24
Peak memory 217748 kb
Host smart-37600688-28a5-458a-b027-8316a6da787d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543313443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.543313443
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.3815882352
Short name T805
Test name
Test status
Simulation time 94911627 ps
CPU time 1.16 seconds
Started Aug 12 06:22:18 PM PDT 24
Finished Aug 12 06:22:19 PM PDT 24
Peak memory 216028 kb
Host smart-1052408d-7072-4670-a358-16bf79597bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815882352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3815882352
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2532074189
Short name T302
Test name
Test status
Simulation time 95286123 ps
CPU time 1.19 seconds
Started Aug 12 06:22:21 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 217716 kb
Host smart-6420a4e4-5740-4502-b768-ec7913f420f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532074189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2532074189
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.296721577
Short name T321
Test name
Test status
Simulation time 52429688 ps
CPU time 1.26 seconds
Started Aug 12 06:22:20 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 221344 kb
Host smart-3b009a2a-9d47-42b7-b84c-c2b20cc8ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296721577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.296721577
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.3006217841
Short name T572
Test name
Test status
Simulation time 68336661 ps
CPU time 2.41 seconds
Started Aug 12 06:22:18 PM PDT 24
Finished Aug 12 06:22:21 PM PDT 24
Peak memory 220560 kb
Host smart-b007a541-bb55-40a6-a921-30be0b52749e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006217841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3006217841
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.3379114287
Short name T615
Test name
Test status
Simulation time 85822117 ps
CPU time 1.17 seconds
Started Aug 12 06:22:07 PM PDT 24
Finished Aug 12 06:22:09 PM PDT 24
Peak memory 218752 kb
Host smart-25feb42f-8dd9-4a39-8d6a-5a1c7138dcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379114287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3379114287
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.1813343612
Short name T119
Test name
Test status
Simulation time 38341421 ps
CPU time 1.48 seconds
Started Aug 12 06:22:10 PM PDT 24
Finished Aug 12 06:22:12 PM PDT 24
Peak memory 220356 kb
Host smart-502496d4-b0d9-4542-b747-ead46feb2ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813343612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1813343612
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.2244286855
Short name T589
Test name
Test status
Simulation time 22424807 ps
CPU time 1.18 seconds
Started Aug 12 06:22:07 PM PDT 24
Finished Aug 12 06:22:09 PM PDT 24
Peak memory 219032 kb
Host smart-5136106a-d78b-4fb7-aa94-5a7c08c67f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244286855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2244286855
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.3666257759
Short name T260
Test name
Test status
Simulation time 63393122 ps
CPU time 1.44 seconds
Started Aug 12 06:22:20 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 219200 kb
Host smart-a00b82f9-86c8-4294-881d-9e13fe6fe9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666257759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3666257759
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.2843972815
Short name T469
Test name
Test status
Simulation time 118142143 ps
CPU time 1.12 seconds
Started Aug 12 06:22:18 PM PDT 24
Finished Aug 12 06:22:20 PM PDT 24
Peak memory 220728 kb
Host smart-d82e66f4-90eb-419f-b57f-eda8eeacc0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843972815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2843972815
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.505183527
Short name T51
Test name
Test status
Simulation time 43014181 ps
CPU time 1.61 seconds
Started Aug 12 06:22:20 PM PDT 24
Finished Aug 12 06:22:21 PM PDT 24
Peak memory 219064 kb
Host smart-61731fd6-d403-4ae2-95c6-7221a94f0f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505183527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.505183527
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.730268441
Short name T963
Test name
Test status
Simulation time 52469801 ps
CPU time 1.47 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:14 PM PDT 24
Peak memory 219216 kb
Host smart-a69d7ae3-9787-4cbb-8be9-b285e2882f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730268441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.730268441
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2417774301
Short name T541
Test name
Test status
Simulation time 33677213 ps
CPU time 1.34 seconds
Started Aug 12 06:20:54 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 215992 kb
Host smart-57918450-d01b-42a2-98a1-0213a933fa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417774301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2417774301
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.878490922
Short name T772
Test name
Test status
Simulation time 27057085 ps
CPU time 0.88 seconds
Started Aug 12 06:20:54 PM PDT 24
Finished Aug 12 06:20:55 PM PDT 24
Peak memory 207248 kb
Host smart-7ef1b3d2-dec6-453d-9a2f-ae00053ab759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878490922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.878490922
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.957218270
Short name T677
Test name
Test status
Simulation time 19562317 ps
CPU time 0.89 seconds
Started Aug 12 06:21:02 PM PDT 24
Finished Aug 12 06:21:03 PM PDT 24
Peak memory 215832 kb
Host smart-878368c8-fb83-448d-83fb-e048410afeeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957218270 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.957218270
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.818796164
Short name T253
Test name
Test status
Simulation time 33942715 ps
CPU time 1.11 seconds
Started Aug 12 06:20:54 PM PDT 24
Finished Aug 12 06:20:55 PM PDT 24
Peak memory 217988 kb
Host smart-02748a47-21ae-4b94-9ee0-6236be627fb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818796164 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.818796164
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3481428926
Short name T761
Test name
Test status
Simulation time 39829786 ps
CPU time 1.01 seconds
Started Aug 12 06:20:53 PM PDT 24
Finished Aug 12 06:20:55 PM PDT 24
Peak memory 220640 kb
Host smart-e01525f1-bfae-4905-97f4-9543a71f46e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481428926 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3481428926
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2937949728
Short name T110
Test name
Test status
Simulation time 29872531 ps
CPU time 1.29 seconds
Started Aug 12 06:20:57 PM PDT 24
Finished Aug 12 06:20:58 PM PDT 24
Peak memory 219064 kb
Host smart-6eb614f8-33bc-4389-9314-24c7bcd7e654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937949728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2937949728
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.325178983
Short name T860
Test name
Test status
Simulation time 125715746 ps
CPU time 0.89 seconds
Started Aug 12 06:20:53 PM PDT 24
Finished Aug 12 06:20:59 PM PDT 24
Peak memory 215696 kb
Host smart-e9214855-c662-4a5e-9947-cef8ab35b3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325178983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.325178983
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1416568501
Short name T519
Test name
Test status
Simulation time 94304737 ps
CPU time 2.49 seconds
Started Aug 12 06:21:05 PM PDT 24
Finished Aug 12 06:21:08 PM PDT 24
Peak memory 217560 kb
Host smart-7514c5e9-5b26-4642-9ccd-547bc2038524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416568501 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1416568501
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_genbits.1156063413
Short name T891
Test name
Test status
Simulation time 120033603 ps
CPU time 1.56 seconds
Started Aug 12 06:22:21 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 219288 kb
Host smart-e2c56759-fb78-48ae-a4f7-e695d383885e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156063413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1156063413
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.3847753096
Short name T246
Test name
Test status
Simulation time 237098496 ps
CPU time 1.68 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 219480 kb
Host smart-be8631a0-c9a8-4c16-adf4-1f1b5d790a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847753096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3847753096
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.79795834
Short name T44
Test name
Test status
Simulation time 129148627 ps
CPU time 1.16 seconds
Started Aug 12 06:22:16 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 219460 kb
Host smart-0dc54848-ff23-4b01-a45b-a461d7b771ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79795834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.79795834
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.365351192
Short name T878
Test name
Test status
Simulation time 46001338 ps
CPU time 1.26 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:13 PM PDT 24
Peak memory 218988 kb
Host smart-1802f064-6899-46e3-a635-a57c26a67bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365351192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.365351192
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.2174022453
Short name T504
Test name
Test status
Simulation time 45428506 ps
CPU time 1.22 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:14 PM PDT 24
Peak memory 217864 kb
Host smart-c8354104-24c0-4118-a4da-cd7202814c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174022453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2174022453
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1805290669
Short name T499
Test name
Test status
Simulation time 27472538 ps
CPU time 1.35 seconds
Started Aug 12 06:22:10 PM PDT 24
Finished Aug 12 06:22:12 PM PDT 24
Peak memory 218812 kb
Host smart-e747eb25-ee85-4e04-bda1-2138cff1a52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805290669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1805290669
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.985671933
Short name T351
Test name
Test status
Simulation time 47238138 ps
CPU time 1.19 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:13 PM PDT 24
Peak memory 218804 kb
Host smart-56cd9ac2-3a8b-4540-9333-f14ff2fb51e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985671933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.985671933
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1849795040
Short name T930
Test name
Test status
Simulation time 102047326 ps
CPU time 1.1 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 216056 kb
Host smart-bee49a4b-81cc-424b-8829-647fcc2dce60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849795040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1849795040
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.4150700161
Short name T74
Test name
Test status
Simulation time 37881378 ps
CPU time 1.41 seconds
Started Aug 12 06:22:08 PM PDT 24
Finished Aug 12 06:22:10 PM PDT 24
Peak memory 219196 kb
Host smart-f47e6337-bb0a-463d-9441-8fe89d5d0e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150700161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.4150700161
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.3741803133
Short name T645
Test name
Test status
Simulation time 168922814 ps
CPU time 1.35 seconds
Started Aug 12 06:22:10 PM PDT 24
Finished Aug 12 06:22:11 PM PDT 24
Peak memory 216000 kb
Host smart-8901045c-e621-46e0-b4c8-e4e9472f1e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741803133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3741803133
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.2408762851
Short name T920
Test name
Test status
Simulation time 72364245 ps
CPU time 1.03 seconds
Started Aug 12 06:22:10 PM PDT 24
Finished Aug 12 06:22:11 PM PDT 24
Peak memory 218992 kb
Host smart-d2edad23-61b4-48ee-a9a7-637b532252a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408762851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2408762851
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.272706824
Short name T857
Test name
Test status
Simulation time 45199820 ps
CPU time 1.17 seconds
Started Aug 12 06:22:10 PM PDT 24
Finished Aug 12 06:22:11 PM PDT 24
Peak memory 221268 kb
Host smart-514551f8-ea35-4688-89e6-fa8a629207bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272706824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.272706824
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.196736169
Short name T314
Test name
Test status
Simulation time 92512638 ps
CPU time 1.35 seconds
Started Aug 12 06:22:09 PM PDT 24
Finished Aug 12 06:22:11 PM PDT 24
Peak memory 220404 kb
Host smart-2a43f48d-89e3-4b4d-80dc-4a413f7493ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196736169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.196736169
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.26436490
Short name T92
Test name
Test status
Simulation time 22756792 ps
CPU time 1.07 seconds
Started Aug 12 06:20:51 PM PDT 24
Finished Aug 12 06:20:52 PM PDT 24
Peak memory 219932 kb
Host smart-a0edbb80-be74-4573-a5f6-94976340891e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26436490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.26436490
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3051154139
Short name T432
Test name
Test status
Simulation time 15604586 ps
CPU time 0.87 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 207232 kb
Host smart-97d5abbb-2ea4-46cd-8c93-16da9bf9b8ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051154139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3051154139
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_err.230514779
Short name T171
Test name
Test status
Simulation time 29585350 ps
CPU time 1.35 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 226008 kb
Host smart-cf8c8c6d-5d71-4670-8e2a-74f044d8896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230514779 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.230514779
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_intr.1014068749
Short name T961
Test name
Test status
Simulation time 31824702 ps
CPU time 0.86 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 215728 kb
Host smart-1bcfd01d-003c-4d73-9965-95e502ee87bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014068749 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1014068749
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2401441545
Short name T85
Test name
Test status
Simulation time 15255150 ps
CPU time 0.97 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 215656 kb
Host smart-f1689183-9a63-4794-977a-ef5a04030a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401441545 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2401441545
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.4172026372
Short name T946
Test name
Test status
Simulation time 817911253 ps
CPU time 5.33 seconds
Started Aug 12 06:20:56 PM PDT 24
Finished Aug 12 06:21:01 PM PDT 24
Peak memory 215688 kb
Host smart-ab5f5ddc-1d95-4216-8ba8-3959dc108d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172026372 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.4172026372
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1599156749
Short name T234
Test name
Test status
Simulation time 3049266302 ps
CPU time 71.94 seconds
Started Aug 12 06:20:51 PM PDT 24
Finished Aug 12 06:22:03 PM PDT 24
Peak memory 218740 kb
Host smart-6f728b6b-626d-4de4-8ad1-70293905d890
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599156749 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1599156749
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.4018074518
Short name T317
Test name
Test status
Simulation time 24622669 ps
CPU time 1.24 seconds
Started Aug 12 06:22:11 PM PDT 24
Finished Aug 12 06:22:12 PM PDT 24
Peak memory 220624 kb
Host smart-86da6f69-73dc-4ecb-9881-4d46faaae868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018074518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.4018074518
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3308893252
Short name T81
Test name
Test status
Simulation time 30155337 ps
CPU time 1.29 seconds
Started Aug 12 06:22:11 PM PDT 24
Finished Aug 12 06:22:13 PM PDT 24
Peak memory 217828 kb
Host smart-c897de96-4402-4410-b3fe-798aa56cfd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308893252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3308893252
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.852409404
Short name T205
Test name
Test status
Simulation time 77360481 ps
CPU time 1.06 seconds
Started Aug 12 06:22:17 PM PDT 24
Finished Aug 12 06:22:18 PM PDT 24
Peak memory 217588 kb
Host smart-4af9d9c4-271d-4803-8323-6347d5536ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852409404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.852409404
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.2266382688
Short name T230
Test name
Test status
Simulation time 66696173 ps
CPU time 1.22 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 220156 kb
Host smart-168264a0-d970-446d-b002-3b05e6b175e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266382688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2266382688
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.2428254476
Short name T586
Test name
Test status
Simulation time 94961223 ps
CPU time 1.21 seconds
Started Aug 12 06:22:27 PM PDT 24
Finished Aug 12 06:22:28 PM PDT 24
Peak memory 217640 kb
Host smart-fe86fe9a-1ee1-4965-9a18-76f474b6b361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428254476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2428254476
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.4033399428
Short name T812
Test name
Test status
Simulation time 103950617 ps
CPU time 1.28 seconds
Started Aug 12 06:22:30 PM PDT 24
Finished Aug 12 06:22:32 PM PDT 24
Peak memory 221428 kb
Host smart-f434bd20-2780-4cae-a6cf-6bc8e4658cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033399428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.4033399428
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.3158984053
Short name T527
Test name
Test status
Simulation time 56400333 ps
CPU time 1.42 seconds
Started Aug 12 06:22:23 PM PDT 24
Finished Aug 12 06:22:24 PM PDT 24
Peak memory 218884 kb
Host smart-f49201d8-f0bc-4c45-a8a6-2a3426bfe9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158984053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3158984053
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.1344987355
Short name T956
Test name
Test status
Simulation time 37525795 ps
CPU time 1.11 seconds
Started Aug 12 06:22:44 PM PDT 24
Finished Aug 12 06:22:45 PM PDT 24
Peak memory 219004 kb
Host smart-7cb23e36-0862-47c1-b761-03db29cdc67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344987355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1344987355
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.661086589
Short name T672
Test name
Test status
Simulation time 42151310 ps
CPU time 1.48 seconds
Started Aug 12 06:22:19 PM PDT 24
Finished Aug 12 06:22:21 PM PDT 24
Peak memory 217876 kb
Host smart-8b993261-ac01-4590-a8bb-1345cae4bf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661086589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.661086589
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.1426218247
Short name T843
Test name
Test status
Simulation time 229996601 ps
CPU time 1.3 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 218820 kb
Host smart-eef22bfc-74ba-4ba0-805d-116d6227c074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426218247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1426218247
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.1722961112
Short name T561
Test name
Test status
Simulation time 63338503 ps
CPU time 1.3 seconds
Started Aug 12 06:22:20 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 219020 kb
Host smart-721f7f17-0ad8-48b8-b76e-65025a5dd1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722961112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1722961112
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3596142790
Short name T433
Test name
Test status
Simulation time 154179599 ps
CPU time 1.24 seconds
Started Aug 12 06:22:32 PM PDT 24
Finished Aug 12 06:22:33 PM PDT 24
Peak memory 219276 kb
Host smart-bd7b4cd9-9244-4184-a8a6-fba53a5ce481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596142790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3596142790
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.2626436372
Short name T500
Test name
Test status
Simulation time 98249635 ps
CPU time 1.46 seconds
Started Aug 12 06:22:33 PM PDT 24
Finished Aug 12 06:22:35 PM PDT 24
Peak memory 216108 kb
Host smart-506f6833-fd49-42b4-8cac-8323400b0cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626436372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2626436372
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.228529991
Short name T716
Test name
Test status
Simulation time 114203649 ps
CPU time 2.81 seconds
Started Aug 12 06:22:30 PM PDT 24
Finished Aug 12 06:22:33 PM PDT 24
Peak memory 220752 kb
Host smart-35503f8a-0a95-41e5-b6ad-334a6b788841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228529991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.228529991
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3134469296
Short name T487
Test name
Test status
Simulation time 30378246 ps
CPU time 1.28 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 220980 kb
Host smart-e933bfba-e6f9-49bf-8f93-d8fb7a9dfe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134469296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3134469296
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3538506074
Short name T439
Test name
Test status
Simulation time 57557641 ps
CPU time 1.5 seconds
Started Aug 12 06:22:34 PM PDT 24
Finished Aug 12 06:22:36 PM PDT 24
Peak memory 218824 kb
Host smart-55d020a7-813e-4af2-9668-5cce196e75b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538506074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3538506074
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.2277730794
Short name T297
Test name
Test status
Simulation time 105560074 ps
CPU time 1.13 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:13 PM PDT 24
Peak memory 219060 kb
Host smart-10c57ead-0e48-41d6-b362-6e3d5d3d7a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277730794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2277730794
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.133048900
Short name T353
Test name
Test status
Simulation time 33960126 ps
CPU time 1.23 seconds
Started Aug 12 06:22:21 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 220244 kb
Host smart-34bdc9d7-e4d1-4f90-9ae5-f8ecedf40f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133048900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.133048900
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1897449846
Short name T138
Test name
Test status
Simulation time 30222530 ps
CPU time 1.31 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 219504 kb
Host smart-a986b94b-6aa2-4f6c-a668-5675d4622e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897449846 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1897449846
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3813458212
Short name T530
Test name
Test status
Simulation time 15772807 ps
CPU time 0.88 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 207272 kb
Host smart-94395f30-4657-41e8-9121-27d8a86b7a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813458212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3813458212
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3231144352
Short name T729
Test name
Test status
Simulation time 18829803 ps
CPU time 0.83 seconds
Started Aug 12 06:20:54 PM PDT 24
Finished Aug 12 06:20:55 PM PDT 24
Peak memory 216944 kb
Host smart-aa7346ef-2b99-4c54-bfb7-0d2c73a0b404
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231144352 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3231144352
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3706445744
Short name T563
Test name
Test status
Simulation time 119195359 ps
CPU time 1.2 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 220048 kb
Host smart-dd8c796f-9cef-4ac5-8e81-aaa2e9526a84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706445744 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3706445744
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3464460869
Short name T66
Test name
Test status
Simulation time 27758223 ps
CPU time 0.87 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 219100 kb
Host smart-fc5d371e-a1d5-4f2b-9960-11cf3f2e7908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464460869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3464460869
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2346339849
Short name T481
Test name
Test status
Simulation time 58257687 ps
CPU time 1.22 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:57 PM PDT 24
Peak memory 218840 kb
Host smart-ec1a0b72-fd69-4fcf-9a55-56e93a9988e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346339849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2346339849
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2922338061
Short name T888
Test name
Test status
Simulation time 66488026 ps
CPU time 0.97 seconds
Started Aug 12 06:20:54 PM PDT 24
Finished Aug 12 06:20:55 PM PDT 24
Peak memory 224188 kb
Host smart-510cac8a-64aa-45a4-86f1-de6154a1a7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922338061 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2922338061
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.12556373
Short name T746
Test name
Test status
Simulation time 88652340 ps
CPU time 0.9 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:57 PM PDT 24
Peak memory 215664 kb
Host smart-223c9d83-e5d6-454f-936b-4f305a928971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12556373 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.12556373
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4008880216
Short name T648
Test name
Test status
Simulation time 275963520 ps
CPU time 3.17 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:59 PM PDT 24
Peak memory 217812 kb
Host smart-63cacf70-e7ac-45ad-8fc9-8a631a505be3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008880216 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4008880216
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_alert.3120464576
Short name T758
Test name
Test status
Simulation time 32557876 ps
CPU time 1.37 seconds
Started Aug 12 06:22:25 PM PDT 24
Finished Aug 12 06:22:26 PM PDT 24
Peak memory 221472 kb
Host smart-a0e1edff-61b5-4a9b-9872-6134b97bdb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120464576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3120464576
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.3287644988
Short name T463
Test name
Test status
Simulation time 6666079318 ps
CPU time 104.93 seconds
Started Aug 12 06:22:46 PM PDT 24
Finished Aug 12 06:24:31 PM PDT 24
Peak memory 221056 kb
Host smart-5e0e641b-72ce-4c2d-8fbc-b98008d961e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287644988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3287644988
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1740726629
Short name T228
Test name
Test status
Simulation time 37679913 ps
CPU time 1.1 seconds
Started Aug 12 06:22:37 PM PDT 24
Finished Aug 12 06:22:38 PM PDT 24
Peak memory 219156 kb
Host smart-99a9d0d9-fa28-4a6c-a7f3-f398b65ddc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740726629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1740726629
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.3852655930
Short name T395
Test name
Test status
Simulation time 53513136 ps
CPU time 0.99 seconds
Started Aug 12 06:22:45 PM PDT 24
Finished Aug 12 06:22:47 PM PDT 24
Peak memory 217688 kb
Host smart-1b9de93a-a1f7-4441-a15d-acf246dfc016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852655930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3852655930
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1448997116
Short name T452
Test name
Test status
Simulation time 65994481 ps
CPU time 1.09 seconds
Started Aug 12 06:22:28 PM PDT 24
Finished Aug 12 06:22:29 PM PDT 24
Peak memory 216020 kb
Host smart-9b71216e-ecfe-4314-9bb4-06c6d891fdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448997116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1448997116
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/133.edn_alert.740595655
Short name T616
Test name
Test status
Simulation time 42459172 ps
CPU time 1.11 seconds
Started Aug 12 06:22:23 PM PDT 24
Finished Aug 12 06:22:24 PM PDT 24
Peak memory 219176 kb
Host smart-74b582a7-70db-4be3-9255-15fa22d7834c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740595655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.740595655
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/134.edn_alert.2405255716
Short name T99
Test name
Test status
Simulation time 64566520 ps
CPU time 1 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 218652 kb
Host smart-b6a91e8d-3ed9-44be-a829-7f683008baa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405255716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2405255716
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.482993686
Short name T352
Test name
Test status
Simulation time 36681330 ps
CPU time 1 seconds
Started Aug 12 06:22:21 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 217716 kb
Host smart-a95fd356-fd36-4f4f-bcd1-5a0c68fc805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482993686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.482993686
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.1830431011
Short name T907
Test name
Test status
Simulation time 77893127 ps
CPU time 1.14 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 220112 kb
Host smart-9f714b03-9023-449b-a8d8-86c5523ff97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830431011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1830431011
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.3756351160
Short name T960
Test name
Test status
Simulation time 38155548 ps
CPU time 1.34 seconds
Started Aug 12 06:22:35 PM PDT 24
Finished Aug 12 06:22:37 PM PDT 24
Peak memory 217680 kb
Host smart-26ae8826-206f-4694-9042-87d363a11c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756351160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3756351160
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3785886744
Short name T655
Test name
Test status
Simulation time 86432638 ps
CPU time 1.12 seconds
Started Aug 12 06:22:22 PM PDT 24
Finished Aug 12 06:22:23 PM PDT 24
Peak memory 216016 kb
Host smart-e8b49807-5630-405b-aab4-4a3745d0671f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785886744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3785886744
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.3470566180
Short name T320
Test name
Test status
Simulation time 54289382 ps
CPU time 1.23 seconds
Started Aug 12 06:22:20 PM PDT 24
Finished Aug 12 06:22:21 PM PDT 24
Peak memory 216052 kb
Host smart-ff0052d6-66f6-4953-8963-e5f17d325373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470566180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.3470566180
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.1726068639
Short name T555
Test name
Test status
Simulation time 69575520 ps
CPU time 1.74 seconds
Started Aug 12 06:22:21 PM PDT 24
Finished Aug 12 06:22:23 PM PDT 24
Peak memory 220668 kb
Host smart-0be60d98-e5d3-4f54-b014-7ae1f3572465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726068639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1726068639
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.2696926974
Short name T591
Test name
Test status
Simulation time 42012763 ps
CPU time 1.22 seconds
Started Aug 12 06:22:16 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 220188 kb
Host smart-0979a92e-b675-457d-9b89-69396971ad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696926974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2696926974
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1944059750
Short name T12
Test name
Test status
Simulation time 686514937 ps
CPU time 2.15 seconds
Started Aug 12 06:22:22 PM PDT 24
Finished Aug 12 06:22:25 PM PDT 24
Peak memory 215700 kb
Host smart-30774074-e2d0-4fa9-bc67-56a51370699a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944059750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1944059750
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1116195834
Short name T861
Test name
Test status
Simulation time 86018014 ps
CPU time 1.53 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 217808 kb
Host smart-46fcb386-0f49-4f4e-8a4a-88f950915fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116195834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1116195834
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1310740047
Short name T850
Test name
Test status
Simulation time 96377483 ps
CPU time 1.2 seconds
Started Aug 12 06:20:54 PM PDT 24
Finished Aug 12 06:20:55 PM PDT 24
Peak memory 218752 kb
Host smart-6cc73696-b262-4f4a-9f55-745a6bde17ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310740047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1310740047
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3957796487
Short name T374
Test name
Test status
Simulation time 52233410 ps
CPU time 0.86 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:57 PM PDT 24
Peak memory 207224 kb
Host smart-16ab500f-9dbc-4b8e-be4b-22e9b2e1fbdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957796487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3957796487
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.182379071
Short name T577
Test name
Test status
Simulation time 13196987 ps
CPU time 0.93 seconds
Started Aug 12 06:20:53 PM PDT 24
Finished Aug 12 06:20:54 PM PDT 24
Peak memory 217084 kb
Host smart-3278ca14-2e41-4d67-bb13-3bcb88de6fd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182379071 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.182379071
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3462132924
Short name T265
Test name
Test status
Simulation time 41259134 ps
CPU time 1.04 seconds
Started Aug 12 06:20:56 PM PDT 24
Finished Aug 12 06:20:57 PM PDT 24
Peak memory 217676 kb
Host smart-65bbac31-dde3-440b-ab77-9795303e1c2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462132924 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3462132924
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_smoke.138634482
Short name T566
Test name
Test status
Simulation time 39142600 ps
CPU time 0.86 seconds
Started Aug 12 06:20:56 PM PDT 24
Finished Aug 12 06:20:57 PM PDT 24
Peak memory 215628 kb
Host smart-e87c1f73-3c54-4b03-82a2-2059796c68bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138634482 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.138634482
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2120562992
Short name T640
Test name
Test status
Simulation time 1392421096 ps
CPU time 4.51 seconds
Started Aug 12 06:20:50 PM PDT 24
Finished Aug 12 06:20:55 PM PDT 24
Peak memory 217564 kb
Host smart-45d6527e-fbfd-426b-8d69-7f097b94ebea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120562992 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2120562992
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_alert.3691179778
Short name T618
Test name
Test status
Simulation time 201333875 ps
CPU time 1.12 seconds
Started Aug 12 06:22:35 PM PDT 24
Finished Aug 12 06:22:36 PM PDT 24
Peak memory 218948 kb
Host smart-d61b0806-d3db-4ccd-871e-c276d3fc1150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691179778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3691179778
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.1167195209
Short name T706
Test name
Test status
Simulation time 94159704 ps
CPU time 1.47 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:14 PM PDT 24
Peak memory 220604 kb
Host smart-1234fcc8-263c-4f5f-866e-f60d6af2c926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167195209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1167195209
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.51973892
Short name T779
Test name
Test status
Simulation time 186888789 ps
CPU time 1.17 seconds
Started Aug 12 06:22:28 PM PDT 24
Finished Aug 12 06:22:29 PM PDT 24
Peak memory 219780 kb
Host smart-96772edb-46dd-434b-81ed-dc04c1708580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51973892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.51973892
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3288043399
Short name T874
Test name
Test status
Simulation time 117746136 ps
CPU time 1.53 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:14 PM PDT 24
Peak memory 220752 kb
Host smart-4e1a6974-499a-4e93-b7e4-f28535714bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288043399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3288043399
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3986770605
Short name T503
Test name
Test status
Simulation time 22479682 ps
CPU time 1.15 seconds
Started Aug 12 06:22:20 PM PDT 24
Finished Aug 12 06:22:21 PM PDT 24
Peak memory 219172 kb
Host smart-3e12c1b1-e93c-4555-aa98-cb8dbd921386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986770605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3986770605
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3518436029
Short name T403
Test name
Test status
Simulation time 41982948 ps
CPU time 1.86 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 218836 kb
Host smart-4541e54d-9694-4888-9118-32626f8cf6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518436029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3518436029
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.2169023931
Short name T927
Test name
Test status
Simulation time 28150012 ps
CPU time 1.32 seconds
Started Aug 12 06:22:25 PM PDT 24
Finished Aug 12 06:22:26 PM PDT 24
Peak memory 219776 kb
Host smart-65873f09-98e6-4eed-becf-56a0318c6190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169023931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2169023931
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.3042513735
Short name T789
Test name
Test status
Simulation time 41436300 ps
CPU time 1.33 seconds
Started Aug 12 06:22:40 PM PDT 24
Finished Aug 12 06:22:42 PM PDT 24
Peak memory 218716 kb
Host smart-bb51af86-f79c-4ba1-b795-edd2fd3f225d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042513735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3042513735
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3593033662
Short name T603
Test name
Test status
Simulation time 489295481 ps
CPU time 4.22 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:18 PM PDT 24
Peak memory 220632 kb
Host smart-665c1052-51d2-4566-ad61-583975cbbc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593033662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3593033662
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2356506223
Short name T91
Test name
Test status
Simulation time 24198861 ps
CPU time 1.16 seconds
Started Aug 12 06:22:21 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 220272 kb
Host smart-2ad630c5-039c-4360-ac96-c9ec6973bb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356506223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2356506223
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2349086268
Short name T720
Test name
Test status
Simulation time 29993481 ps
CPU time 1.33 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 217528 kb
Host smart-d22df457-4a73-42a9-8863-e307bbc30efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349086268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2349086268
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.3538299382
Short name T925
Test name
Test status
Simulation time 22330815 ps
CPU time 1.08 seconds
Started Aug 12 06:22:17 PM PDT 24
Finished Aug 12 06:22:18 PM PDT 24
Peak memory 218784 kb
Host smart-89153870-c579-4e3d-9231-ea30b3ed69ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538299382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.3538299382
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.3203689124
Short name T882
Test name
Test status
Simulation time 27289281 ps
CPU time 1.48 seconds
Started Aug 12 06:22:19 PM PDT 24
Finished Aug 12 06:22:21 PM PDT 24
Peak memory 219020 kb
Host smart-50d0ac8b-823a-4e0f-a315-c5526461c874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203689124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3203689124
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.1926036008
Short name T188
Test name
Test status
Simulation time 197963203 ps
CPU time 1.26 seconds
Started Aug 12 06:22:38 PM PDT 24
Finished Aug 12 06:22:40 PM PDT 24
Peak memory 221068 kb
Host smart-e18380fd-6a07-48e3-9652-451ae25235ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926036008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1926036008
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3507655839
Short name T402
Test name
Test status
Simulation time 45405573 ps
CPU time 1.1 seconds
Started Aug 12 06:22:26 PM PDT 24
Finished Aug 12 06:22:27 PM PDT 24
Peak memory 217736 kb
Host smart-e9eea00d-5861-4eac-8d8c-2a8622631c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507655839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3507655839
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.4061625174
Short name T105
Test name
Test status
Simulation time 29514068 ps
CPU time 1.22 seconds
Started Aug 12 06:22:20 PM PDT 24
Finished Aug 12 06:22:21 PM PDT 24
Peak memory 220144 kb
Host smart-4cd94325-2d48-4e33-9c31-4d850873d661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061625174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.4061625174
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.1130622537
Short name T756
Test name
Test status
Simulation time 49305783 ps
CPU time 1.89 seconds
Started Aug 12 06:22:17 PM PDT 24
Finished Aug 12 06:22:19 PM PDT 24
Peak memory 219244 kb
Host smart-368e67a2-52ce-4753-b4ee-db33cbd74310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130622537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1130622537
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.566820088
Short name T497
Test name
Test status
Simulation time 79793598 ps
CPU time 1.1 seconds
Started Aug 12 06:22:20 PM PDT 24
Finished Aug 12 06:22:21 PM PDT 24
Peak memory 220264 kb
Host smart-79c9a942-ec65-41d1-bb70-11b1978d5b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566820088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.566820088
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.1517195974
Short name T508
Test name
Test status
Simulation time 76466713 ps
CPU time 1.42 seconds
Started Aug 12 06:22:21 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 219396 kb
Host smart-53eae1d9-533d-472f-aa4d-f607a0bc4c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517195974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1517195974
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.3409423959
Short name T753
Test name
Test status
Simulation time 28494925 ps
CPU time 0.92 seconds
Started Aug 12 06:21:01 PM PDT 24
Finished Aug 12 06:21:02 PM PDT 24
Peak memory 215668 kb
Host smart-b2b847ef-15bb-4901-95e5-79b76f1cf62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409423959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3409423959
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.35074829
Short name T736
Test name
Test status
Simulation time 16596552 ps
CPU time 0.85 seconds
Started Aug 12 06:21:04 PM PDT 24
Finished Aug 12 06:21:05 PM PDT 24
Peak memory 215720 kb
Host smart-dcc4a22d-8e56-4ce7-8164-ff3dc5d47305
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35074829 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.35074829
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1065562333
Short name T296
Test name
Test status
Simulation time 92763077 ps
CPU time 1.17 seconds
Started Aug 12 06:20:57 PM PDT 24
Finished Aug 12 06:20:58 PM PDT 24
Peak memory 220132 kb
Host smart-8345eb86-07a3-46d1-88ab-55606b633ec7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065562333 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1065562333
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.78129644
Short name T139
Test name
Test status
Simulation time 35999934 ps
CPU time 1.09 seconds
Started Aug 12 06:21:00 PM PDT 24
Finished Aug 12 06:21:06 PM PDT 24
Peak memory 221172 kb
Host smart-aace1dac-7d5a-48a1-be59-a0cb395c1fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78129644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.78129644
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1827310724
Short name T428
Test name
Test status
Simulation time 41275863 ps
CPU time 1.35 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:57 PM PDT 24
Peak memory 218944 kb
Host smart-029498cb-035b-40ba-9eb5-177e6e52478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827310724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1827310724
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.4094934815
Short name T446
Test name
Test status
Simulation time 24538201 ps
CPU time 0.93 seconds
Started Aug 12 06:20:59 PM PDT 24
Finished Aug 12 06:21:00 PM PDT 24
Peak memory 215832 kb
Host smart-f8539766-6072-4961-82c7-d1f34f127f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094934815 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.4094934815
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1143809695
Short name T760
Test name
Test status
Simulation time 19445360 ps
CPU time 1.02 seconds
Started Aug 12 06:21:05 PM PDT 24
Finished Aug 12 06:21:06 PM PDT 24
Peak memory 215728 kb
Host smart-13004770-e199-464f-a72d-4fffc82b6c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143809695 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1143809695
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.945793016
Short name T480
Test name
Test status
Simulation time 619627500 ps
CPU time 2.82 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:59 PM PDT 24
Peak memory 220556 kb
Host smart-899150b3-9f91-42e6-b189-ad7f331270a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945793016 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.945793016
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_alert.3593769321
Short name T467
Test name
Test status
Simulation time 24736570 ps
CPU time 1.23 seconds
Started Aug 12 06:22:19 PM PDT 24
Finished Aug 12 06:22:21 PM PDT 24
Peak memory 218936 kb
Host smart-72656884-30d0-4fd6-9dfb-fc368df34458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593769321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3593769321
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2807723232
Short name T367
Test name
Test status
Simulation time 68641099 ps
CPU time 1.3 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 219168 kb
Host smart-f1e772f0-7aa0-4d09-a3d9-155ad93dbda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807723232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2807723232
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1809945086
Short name T894
Test name
Test status
Simulation time 84235703 ps
CPU time 1.12 seconds
Started Aug 12 06:22:40 PM PDT 24
Finished Aug 12 06:22:42 PM PDT 24
Peak memory 220212 kb
Host smart-9486b495-852b-40c3-a1bc-f6d34161baf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809945086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1809945086
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.1576804313
Short name T461
Test name
Test status
Simulation time 35631906 ps
CPU time 1.32 seconds
Started Aug 12 06:22:24 PM PDT 24
Finished Aug 12 06:22:25 PM PDT 24
Peak memory 220392 kb
Host smart-9e1c907f-b44a-4bfe-add4-d8444feaf086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576804313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1576804313
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.2173794909
Short name T151
Test name
Test status
Simulation time 47350198 ps
CPU time 1.12 seconds
Started Aug 12 06:22:27 PM PDT 24
Finished Aug 12 06:22:28 PM PDT 24
Peak memory 216048 kb
Host smart-9e951351-3e70-4b80-982e-cc340d501f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173794909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2173794909
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.1227735177
Short name T822
Test name
Test status
Simulation time 98505303 ps
CPU time 1.49 seconds
Started Aug 12 06:22:23 PM PDT 24
Finished Aug 12 06:22:25 PM PDT 24
Peak memory 219140 kb
Host smart-aae2dcf1-83eb-4d56-8c4b-a942ce627a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227735177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1227735177
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.601477557
Short name T323
Test name
Test status
Simulation time 76575926 ps
CPU time 1.14 seconds
Started Aug 12 06:22:32 PM PDT 24
Finished Aug 12 06:22:34 PM PDT 24
Peak memory 219440 kb
Host smart-6924ab7e-dc81-4bbc-93e6-50bef25528d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601477557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.601477557
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.213301043
Short name T797
Test name
Test status
Simulation time 46975387 ps
CPU time 1.68 seconds
Started Aug 12 06:22:53 PM PDT 24
Finished Aug 12 06:22:55 PM PDT 24
Peak memory 219016 kb
Host smart-87f5b536-e4ab-4f8d-a3b7-d40ace289eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213301043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.213301043
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.3101421477
Short name T903
Test name
Test status
Simulation time 93977567 ps
CPU time 1.14 seconds
Started Aug 12 06:22:38 PM PDT 24
Finished Aug 12 06:22:39 PM PDT 24
Peak memory 220212 kb
Host smart-96995063-e5e6-4848-9274-7c5e9bb4bd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101421477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3101421477
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.2166504033
Short name T534
Test name
Test status
Simulation time 41533127 ps
CPU time 1.6 seconds
Started Aug 12 06:22:40 PM PDT 24
Finished Aug 12 06:22:42 PM PDT 24
Peak memory 219060 kb
Host smart-799cc911-aa8a-4750-8dce-1b5cde7c5305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166504033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2166504033
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3564052231
Short name T267
Test name
Test status
Simulation time 27148083 ps
CPU time 1.19 seconds
Started Aug 12 06:22:32 PM PDT 24
Finished Aug 12 06:22:34 PM PDT 24
Peak memory 218832 kb
Host smart-a9294291-7e75-4406-b66a-e7776c38310c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564052231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3564052231
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2390562346
Short name T653
Test name
Test status
Simulation time 91054573 ps
CPU time 2.46 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:45 PM PDT 24
Peak memory 219828 kb
Host smart-fd22e205-aa6f-4ce5-bae9-41a272552b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390562346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2390562346
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3086568504
Short name T397
Test name
Test status
Simulation time 32586630 ps
CPU time 1.11 seconds
Started Aug 12 06:22:36 PM PDT 24
Finished Aug 12 06:22:37 PM PDT 24
Peak memory 219108 kb
Host smart-63c11737-0c85-4e4f-8b40-ec0adaed9ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086568504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3086568504
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3819273854
Short name T936
Test name
Test status
Simulation time 43570167 ps
CPU time 1.33 seconds
Started Aug 12 06:22:29 PM PDT 24
Finished Aug 12 06:22:30 PM PDT 24
Peak memory 218700 kb
Host smart-e54e81f2-4c90-4525-a7b2-334d01fbceb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819273854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3819273854
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.851134641
Short name T971
Test name
Test status
Simulation time 384546164 ps
CPU time 1.37 seconds
Started Aug 12 06:22:43 PM PDT 24
Finished Aug 12 06:22:50 PM PDT 24
Peak memory 219012 kb
Host smart-87663264-08da-499a-8df7-8f14a4df7842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851134641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.851134641
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3641243205
Short name T470
Test name
Test status
Simulation time 68808585 ps
CPU time 1.1 seconds
Started Aug 12 06:22:23 PM PDT 24
Finished Aug 12 06:22:24 PM PDT 24
Peak memory 217840 kb
Host smart-16090be1-a2aa-4a82-9df3-760c1baf9d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641243205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3641243205
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3533495140
Short name T56
Test name
Test status
Simulation time 89885560 ps
CPU time 1.3 seconds
Started Aug 12 06:22:46 PM PDT 24
Finished Aug 12 06:22:48 PM PDT 24
Peak memory 218848 kb
Host smart-8cfa6ca8-e020-45bd-ae57-c1a8f13fec5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533495140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3533495140
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.3654025746
Short name T806
Test name
Test status
Simulation time 25205304 ps
CPU time 1.38 seconds
Started Aug 12 06:22:31 PM PDT 24
Finished Aug 12 06:22:33 PM PDT 24
Peak memory 219248 kb
Host smart-58cf336b-fa5b-4248-83b3-2e9474546353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654025746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3654025746
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.2419315091
Short name T58
Test name
Test status
Simulation time 256088655 ps
CPU time 1.22 seconds
Started Aug 12 06:22:32 PM PDT 24
Finished Aug 12 06:22:34 PM PDT 24
Peak memory 216056 kb
Host smart-12e43f46-f3d1-4c55-8a5a-ace116b355b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419315091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2419315091
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.661996931
Short name T914
Test name
Test status
Simulation time 48317320 ps
CPU time 1.7 seconds
Started Aug 12 06:22:37 PM PDT 24
Finished Aug 12 06:22:39 PM PDT 24
Peak memory 218900 kb
Host smart-568f6e54-e49c-4e3a-a7e2-6a2b43e163ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661996931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.661996931
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.756832802
Short name T807
Test name
Test status
Simulation time 185107527 ps
CPU time 1.07 seconds
Started Aug 12 06:20:54 PM PDT 24
Finished Aug 12 06:20:55 PM PDT 24
Peak memory 220176 kb
Host smart-211ba71c-5862-435a-94e5-8703d66d7069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756832802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.756832802
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable.3256480821
Short name T193
Test name
Test status
Simulation time 34418773 ps
CPU time 0.82 seconds
Started Aug 12 06:20:54 PM PDT 24
Finished Aug 12 06:20:55 PM PDT 24
Peak memory 216896 kb
Host smart-1b2c7bca-baa5-4afa-82b7-5d20c28a63db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256480821 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3256480821
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.522831397
Short name T803
Test name
Test status
Simulation time 23984988 ps
CPU time 1 seconds
Started Aug 12 06:20:57 PM PDT 24
Finished Aug 12 06:20:58 PM PDT 24
Peak memory 220440 kb
Host smart-350c67ff-908a-490d-b521-4e0bec9c139c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522831397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.522831397
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.4198463277
Short name T443
Test name
Test status
Simulation time 26421182 ps
CPU time 1.22 seconds
Started Aug 12 06:21:05 PM PDT 24
Finished Aug 12 06:21:06 PM PDT 24
Peak memory 217696 kb
Host smart-63e8f1f5-bf85-4f87-83f6-50e9da7a3a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198463277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.4198463277
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1447021997
Short name T57
Test name
Test status
Simulation time 31097821 ps
CPU time 0.92 seconds
Started Aug 12 06:21:10 PM PDT 24
Finished Aug 12 06:21:11 PM PDT 24
Peak memory 215760 kb
Host smart-81c0d9fc-16d6-406c-b190-c803911debc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447021997 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1447021997
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1094726097
Short name T599
Test name
Test status
Simulation time 25518886 ps
CPU time 0.95 seconds
Started Aug 12 06:21:24 PM PDT 24
Finished Aug 12 06:21:25 PM PDT 24
Peak memory 215628 kb
Host smart-a634e0ab-f082-4ec8-b5ed-64974e275779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094726097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1094726097
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2914660410
Short name T847
Test name
Test status
Simulation time 564950140 ps
CPU time 5.61 seconds
Started Aug 12 06:20:57 PM PDT 24
Finished Aug 12 06:21:02 PM PDT 24
Peak memory 217728 kb
Host smart-319b400e-4820-4e6e-a761-85ea8b399460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914660410 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2914660410
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.267360999
Short name T972
Test name
Test status
Simulation time 8246579699 ps
CPU time 60.03 seconds
Started Aug 12 06:21:00 PM PDT 24
Finished Aug 12 06:22:00 PM PDT 24
Peak memory 224104 kb
Host smart-b07e2a12-f801-49ee-b657-cb5443eaa25c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267360999 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.267360999
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.533077266
Short name T652
Test name
Test status
Simulation time 84850592 ps
CPU time 1.18 seconds
Started Aug 12 06:22:37 PM PDT 24
Finished Aug 12 06:22:38 PM PDT 24
Peak memory 218908 kb
Host smart-87b97ff6-3969-4a05-98cc-6b99b6f5ca01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533077266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.533077266
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3552649192
Short name T884
Test name
Test status
Simulation time 292245933 ps
CPU time 3.97 seconds
Started Aug 12 06:22:36 PM PDT 24
Finished Aug 12 06:22:40 PM PDT 24
Peak memory 217792 kb
Host smart-f86cadf5-e289-4fc4-92fe-34d70ec39c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552649192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3552649192
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2857025443
Short name T100
Test name
Test status
Simulation time 102454339 ps
CPU time 1.07 seconds
Started Aug 12 06:22:27 PM PDT 24
Finished Aug 12 06:22:28 PM PDT 24
Peak memory 218952 kb
Host smart-80ca5710-170c-4b7b-8e33-a238f5b9c67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857025443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2857025443
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1241638176
Short name T820
Test name
Test status
Simulation time 67324371 ps
CPU time 1.36 seconds
Started Aug 12 06:22:36 PM PDT 24
Finished Aug 12 06:22:38 PM PDT 24
Peak memory 215740 kb
Host smart-9a9ff9e5-1586-40e7-a2bb-930214adf306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241638176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1241638176
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.2909804136
Short name T940
Test name
Test status
Simulation time 80342429 ps
CPU time 1.16 seconds
Started Aug 12 06:22:33 PM PDT 24
Finished Aug 12 06:22:34 PM PDT 24
Peak memory 219640 kb
Host smart-8dbab6bf-554f-490f-9cb5-dd1d0f6f8fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909804136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2909804136
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.2558533620
Short name T350
Test name
Test status
Simulation time 52907708 ps
CPU time 1.36 seconds
Started Aug 12 06:22:55 PM PDT 24
Finished Aug 12 06:22:57 PM PDT 24
Peak memory 219024 kb
Host smart-e8997b34-8478-44cb-b568-860f0eafb2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558533620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2558533620
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.790099777
Short name T322
Test name
Test status
Simulation time 87816478 ps
CPU time 1.24 seconds
Started Aug 12 06:22:35 PM PDT 24
Finished Aug 12 06:22:36 PM PDT 24
Peak memory 219032 kb
Host smart-1579858e-bee9-4e0d-b474-a3e699d6e464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790099777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.790099777
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1627868408
Short name T973
Test name
Test status
Simulation time 55282709 ps
CPU time 1.56 seconds
Started Aug 12 06:22:34 PM PDT 24
Finished Aug 12 06:22:36 PM PDT 24
Peak memory 218744 kb
Host smart-05abcf2b-0bcf-4979-885a-3bc68832bb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627868408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1627868408
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.1076737952
Short name T778
Test name
Test status
Simulation time 105411356 ps
CPU time 1.2 seconds
Started Aug 12 06:22:33 PM PDT 24
Finished Aug 12 06:22:34 PM PDT 24
Peak memory 220420 kb
Host smart-a6784427-8605-40c2-b5f5-e4ae3a485f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076737952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.1076737952
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/165.edn_alert.2105480487
Short name T735
Test name
Test status
Simulation time 60757322 ps
CPU time 1.2 seconds
Started Aug 12 06:22:27 PM PDT 24
Finished Aug 12 06:22:29 PM PDT 24
Peak memory 219032 kb
Host smart-bf3a9261-9ecf-493f-97bc-9f9d1198ea3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105480487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2105480487
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3890504012
Short name T863
Test name
Test status
Simulation time 69594410 ps
CPU time 1.28 seconds
Started Aug 12 06:22:27 PM PDT 24
Finished Aug 12 06:22:29 PM PDT 24
Peak memory 219332 kb
Host smart-f976c89d-45ed-45be-9407-e5ef5772f636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890504012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3890504012
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.2330662731
Short name T301
Test name
Test status
Simulation time 28656745 ps
CPU time 1.25 seconds
Started Aug 12 06:22:40 PM PDT 24
Finished Aug 12 06:22:41 PM PDT 24
Peak memory 219772 kb
Host smart-243cfcef-43bb-4bbd-acc0-b6a6e2f1e860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330662731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2330662731
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.335504063
Short name T366
Test name
Test status
Simulation time 94641396 ps
CPU time 1.01 seconds
Started Aug 12 06:22:23 PM PDT 24
Finished Aug 12 06:22:24 PM PDT 24
Peak memory 217732 kb
Host smart-e2ba1ad1-b34a-4d1c-a48e-0b783186dcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335504063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.335504063
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2005788518
Short name T549
Test name
Test status
Simulation time 87903387 ps
CPU time 1.26 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:43 PM PDT 24
Peak memory 219324 kb
Host smart-8a6024e7-1432-4d61-9934-ecb050c69b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005788518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2005788518
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1630472863
Short name T344
Test name
Test status
Simulation time 58703467 ps
CPU time 1.7 seconds
Started Aug 12 06:22:31 PM PDT 24
Finished Aug 12 06:22:33 PM PDT 24
Peak memory 220252 kb
Host smart-4ed38840-bc09-4dfe-9fde-542ac5188502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630472863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1630472863
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.3187639447
Short name T951
Test name
Test status
Simulation time 31946125 ps
CPU time 1.28 seconds
Started Aug 12 06:22:34 PM PDT 24
Finished Aug 12 06:22:36 PM PDT 24
Peak memory 221340 kb
Host smart-0f88f93d-ba87-4e27-ac6a-9c7448850f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187639447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3187639447
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.4257071927
Short name T391
Test name
Test status
Simulation time 143921782 ps
CPU time 2.96 seconds
Started Aug 12 06:22:34 PM PDT 24
Finished Aug 12 06:22:37 PM PDT 24
Peak memory 218952 kb
Host smart-ddba902a-8bc1-4240-83bf-c9c8426f8b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257071927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.4257071927
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2464202623
Short name T152
Test name
Test status
Simulation time 34006928 ps
CPU time 1.11 seconds
Started Aug 12 06:22:55 PM PDT 24
Finished Aug 12 06:22:57 PM PDT 24
Peak memory 219108 kb
Host smart-c4347018-55eb-40b8-bade-9baa512e681c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464202623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2464202623
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.4119905685
Short name T538
Test name
Test status
Simulation time 40697504 ps
CPU time 1.51 seconds
Started Aug 12 06:22:41 PM PDT 24
Finished Aug 12 06:22:43 PM PDT 24
Peak memory 218920 kb
Host smart-3fb1dfe0-d525-4d1c-b058-f39e3f894ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119905685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4119905685
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3257805598
Short name T387
Test name
Test status
Simulation time 41778523 ps
CPU time 1.07 seconds
Started Aug 12 06:21:00 PM PDT 24
Finished Aug 12 06:21:01 PM PDT 24
Peak memory 218800 kb
Host smart-da8c3b1d-db86-4429-8964-37488675fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257805598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3257805598
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1041878604
Short name T259
Test name
Test status
Simulation time 27413683 ps
CPU time 0.95 seconds
Started Aug 12 06:20:57 PM PDT 24
Finished Aug 12 06:20:58 PM PDT 24
Peak memory 207268 kb
Host smart-412b6f01-2318-406f-b7f7-16f329040477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041878604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1041878604
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2609796009
Short name T2
Test name
Test status
Simulation time 36765966 ps
CPU time 1.24 seconds
Started Aug 12 06:21:28 PM PDT 24
Finished Aug 12 06:21:29 PM PDT 24
Peak memory 218944 kb
Host smart-2c4e0a7a-e521-4a7e-92c1-ecf4979f791e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609796009 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2609796009
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3598501559
Short name T261
Test name
Test status
Simulation time 29188721 ps
CPU time 0.85 seconds
Started Aug 12 06:21:07 PM PDT 24
Finished Aug 12 06:21:08 PM PDT 24
Peak memory 219076 kb
Host smart-6ceed1f3-f5fb-409e-9d2e-88cbf508675a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598501559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3598501559
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.553207262
Short name T493
Test name
Test status
Simulation time 69648185 ps
CPU time 1.38 seconds
Started Aug 12 06:21:00 PM PDT 24
Finished Aug 12 06:21:02 PM PDT 24
Peak memory 220272 kb
Host smart-037b048f-41ff-457a-ae81-33cd543b8d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553207262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.553207262
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.2368431312
Short name T121
Test name
Test status
Simulation time 41678824 ps
CPU time 0.84 seconds
Started Aug 12 06:21:02 PM PDT 24
Finished Aug 12 06:21:03 PM PDT 24
Peak memory 216412 kb
Host smart-b8b0ef0e-f00e-48e4-8c1a-ab9e502b249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368431312 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2368431312
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1444958128
Short name T369
Test name
Test status
Simulation time 24741030 ps
CPU time 0.91 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 215652 kb
Host smart-32869aaa-f4c9-4de8-a753-d3162ccfbe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444958128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1444958128
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3836691847
Short name T324
Test name
Test status
Simulation time 77985054 ps
CPU time 2.08 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:58 PM PDT 24
Peak memory 217712 kb
Host smart-2be7d046-f00f-4156-b594-baa8be982263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836691847 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3836691847
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/170.edn_alert.2831392629
Short name T568
Test name
Test status
Simulation time 43675198 ps
CPU time 1.12 seconds
Started Aug 12 06:22:38 PM PDT 24
Finished Aug 12 06:22:39 PM PDT 24
Peak memory 219040 kb
Host smart-7412c2d0-651f-4b1f-8d21-f5eb1ed8f46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831392629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2831392629
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1668288099
Short name T354
Test name
Test status
Simulation time 25702582 ps
CPU time 1.18 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:56 PM PDT 24
Peak memory 219000 kb
Host smart-e3754d5c-b22c-4ad4-8222-e4bb19f6357f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668288099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1668288099
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.121559107
Short name T899
Test name
Test status
Simulation time 35090334 ps
CPU time 1.01 seconds
Started Aug 12 06:22:43 PM PDT 24
Finished Aug 12 06:22:44 PM PDT 24
Peak memory 219036 kb
Host smart-d1ec8b76-afcb-4b5d-8301-20aa359c091d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121559107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.121559107
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.2247264692
Short name T46
Test name
Test status
Simulation time 109088187 ps
CPU time 1.38 seconds
Started Aug 12 06:23:02 PM PDT 24
Finished Aug 12 06:23:03 PM PDT 24
Peak memory 219108 kb
Host smart-0fe90e12-0063-47c5-9872-8e97a55c4685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247264692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2247264692
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1494375946
Short name T885
Test name
Test status
Simulation time 45514428 ps
CPU time 1.21 seconds
Started Aug 12 06:22:51 PM PDT 24
Finished Aug 12 06:22:52 PM PDT 24
Peak memory 219896 kb
Host smart-18f49226-eedc-4947-bffb-31b43c453f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494375946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1494375946
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.4141113795
Short name T582
Test name
Test status
Simulation time 56897151 ps
CPU time 1.71 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:44 PM PDT 24
Peak memory 218956 kb
Host smart-0c5b256f-5df5-4198-acb1-daba12ab4970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141113795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.4141113795
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.2541174716
Short name T666
Test name
Test status
Simulation time 26868866 ps
CPU time 1.31 seconds
Started Aug 12 06:22:44 PM PDT 24
Finished Aug 12 06:22:46 PM PDT 24
Peak memory 220668 kb
Host smart-1f61566a-3e1e-4a1c-89ff-f87ab56ed8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541174716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2541174716
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.154161174
Short name T385
Test name
Test status
Simulation time 40111516 ps
CPU time 1.34 seconds
Started Aug 12 06:22:39 PM PDT 24
Finished Aug 12 06:22:41 PM PDT 24
Peak memory 218852 kb
Host smart-85a674d5-6cc1-4337-93b7-b05ee0113584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154161174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.154161174
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.4008226918
Short name T430
Test name
Test status
Simulation time 27035803 ps
CPU time 1.18 seconds
Started Aug 12 06:22:41 PM PDT 24
Finished Aug 12 06:22:43 PM PDT 24
Peak memory 219984 kb
Host smart-baa9ae5b-6576-4b50-9ec2-765609959de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008226918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.4008226918
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2252655143
Short name T839
Test name
Test status
Simulation time 30994138 ps
CPU time 1.3 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:44 PM PDT 24
Peak memory 219992 kb
Host smart-b5830d9c-0b10-431b-bea5-67827b9b70e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252655143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2252655143
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.2480092032
Short name T747
Test name
Test status
Simulation time 64890297 ps
CPU time 1.08 seconds
Started Aug 12 06:22:40 PM PDT 24
Finished Aug 12 06:22:41 PM PDT 24
Peak memory 218992 kb
Host smart-71b08374-4fd9-4a21-998b-64da887a0a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480092032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2480092032
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.2364793736
Short name T945
Test name
Test status
Simulation time 38673713 ps
CPU time 1.16 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:44 PM PDT 24
Peak memory 217760 kb
Host smart-58fb8710-4839-497b-8e5a-5bdc61271db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364793736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2364793736
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.1784336303
Short name T607
Test name
Test status
Simulation time 39459788 ps
CPU time 1.15 seconds
Started Aug 12 06:22:36 PM PDT 24
Finished Aug 12 06:22:37 PM PDT 24
Peak memory 220116 kb
Host smart-f0a7d5aa-c58d-4f93-a0e3-4eaebf2653a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784336303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1784336303
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.40098483
Short name T417
Test name
Test status
Simulation time 182165517 ps
CPU time 2.49 seconds
Started Aug 12 06:22:28 PM PDT 24
Finished Aug 12 06:22:41 PM PDT 24
Peak memory 217784 kb
Host smart-dafe83af-c065-45ea-9d2d-a9641255f864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40098483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.40098483
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.563689725
Short name T441
Test name
Test status
Simulation time 39591716 ps
CPU time 1.23 seconds
Started Aug 12 06:22:27 PM PDT 24
Finished Aug 12 06:22:28 PM PDT 24
Peak memory 218944 kb
Host smart-07fe1c53-4e92-4cb5-bcdb-c92b8004ef0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563689725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.563689725
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.477284434
Short name T559
Test name
Test status
Simulation time 322540545 ps
CPU time 1.2 seconds
Started Aug 12 06:22:41 PM PDT 24
Finished Aug 12 06:22:43 PM PDT 24
Peak memory 217820 kb
Host smart-93888f52-b368-41d6-938b-f4273da00000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477284434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.477284434
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.29799760
Short name T104
Test name
Test status
Simulation time 145380632 ps
CPU time 1.06 seconds
Started Aug 12 06:22:46 PM PDT 24
Finished Aug 12 06:22:48 PM PDT 24
Peak memory 219056 kb
Host smart-1a54c2d5-6128-4937-9930-7695e447d5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29799760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.29799760
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.543466175
Short name T892
Test name
Test status
Simulation time 225533229 ps
CPU time 3.12 seconds
Started Aug 12 06:22:47 PM PDT 24
Finished Aug 12 06:22:50 PM PDT 24
Peak memory 218164 kb
Host smart-e06265af-fd81-421f-a3e0-a049522a099e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543466175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.543466175
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3105127085
Short name T189
Test name
Test status
Simulation time 80981511 ps
CPU time 1.19 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:43 PM PDT 24
Peak memory 220804 kb
Host smart-7972c480-26ae-4128-a5c3-c8b2e62339c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105127085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3105127085
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2771212204
Short name T424
Test name
Test status
Simulation time 77250527 ps
CPU time 1.08 seconds
Started Aug 12 06:22:40 PM PDT 24
Finished Aug 12 06:22:42 PM PDT 24
Peak memory 217768 kb
Host smart-9cd70ce3-f1eb-4ec3-9122-cebcf43d76ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771212204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2771212204
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1344485473
Short name T319
Test name
Test status
Simulation time 23010675 ps
CPU time 1.2 seconds
Started Aug 12 06:21:20 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 219888 kb
Host smart-2349ecd7-de99-420a-af8a-4becc74cf739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344485473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1344485473
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2811374406
Short name T454
Test name
Test status
Simulation time 26810463 ps
CPU time 0.87 seconds
Started Aug 12 06:21:23 PM PDT 24
Finished Aug 12 06:21:24 PM PDT 24
Peak memory 207220 kb
Host smart-3a9fc414-0c72-4f3b-81d3-109ae26c96f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811374406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2811374406
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2296773735
Short name T192
Test name
Test status
Simulation time 18398361 ps
CPU time 1.02 seconds
Started Aug 12 06:20:59 PM PDT 24
Finished Aug 12 06:21:00 PM PDT 24
Peak memory 217140 kb
Host smart-cf714c61-f443-4b22-9b46-1cb91f11383e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296773735 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2296773735
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.342269634
Short name T219
Test name
Test status
Simulation time 49563664 ps
CPU time 1.18 seconds
Started Aug 12 06:21:11 PM PDT 24
Finished Aug 12 06:21:13 PM PDT 24
Peak memory 226060 kb
Host smart-37de3f22-aeb4-4b97-8084-41f1df265044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342269634 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.342269634
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2452314602
Short name T919
Test name
Test status
Simulation time 57759673 ps
CPU time 1.35 seconds
Started Aug 12 06:21:03 PM PDT 24
Finished Aug 12 06:21:04 PM PDT 24
Peak memory 220320 kb
Host smart-d3bfc899-c4cf-4827-8236-bfebe4826eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452314602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2452314602
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.2247912136
Short name T832
Test name
Test status
Simulation time 40735876 ps
CPU time 0.94 seconds
Started Aug 12 06:21:15 PM PDT 24
Finished Aug 12 06:21:16 PM PDT 24
Peak memory 215672 kb
Host smart-dec42a4f-fbba-418a-bdbe-45e4cc9353e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247912136 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2247912136
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3383712025
Short name T340
Test name
Test status
Simulation time 149808160 ps
CPU time 2.09 seconds
Started Aug 12 06:20:59 PM PDT 24
Finished Aug 12 06:21:02 PM PDT 24
Peak memory 217604 kb
Host smart-8fbef6d6-33dc-4e21-a661-44072bb29cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383712025 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3383712025
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/180.edn_alert.452181027
Short name T229
Test name
Test status
Simulation time 52212557 ps
CPU time 1.13 seconds
Started Aug 12 06:22:49 PM PDT 24
Finished Aug 12 06:22:50 PM PDT 24
Peak memory 219484 kb
Host smart-440a038c-5255-4744-a824-9adb4217e734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452181027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.452181027
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3265079874
Short name T658
Test name
Test status
Simulation time 57423725 ps
CPU time 1.49 seconds
Started Aug 12 06:22:45 PM PDT 24
Finished Aug 12 06:22:46 PM PDT 24
Peak memory 218184 kb
Host smart-26efa1e0-1520-4855-a104-ad3554cb7467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265079874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3265079874
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.476921671
Short name T584
Test name
Test status
Simulation time 130467850 ps
CPU time 1.16 seconds
Started Aug 12 06:22:53 PM PDT 24
Finished Aug 12 06:22:54 PM PDT 24
Peak memory 219840 kb
Host smart-a288c39a-c4c8-4a6b-a0dc-9b07c2ebf086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476921671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.476921671
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.724995565
Short name T550
Test name
Test status
Simulation time 89380031 ps
CPU time 1.15 seconds
Started Aug 12 06:22:39 PM PDT 24
Finished Aug 12 06:22:41 PM PDT 24
Peak memory 217920 kb
Host smart-0a184534-ee8d-4e82-bee5-855befafc44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724995565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.724995565
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2803637234
Short name T375
Test name
Test status
Simulation time 47784065 ps
CPU time 1.17 seconds
Started Aug 12 06:22:40 PM PDT 24
Finished Aug 12 06:22:41 PM PDT 24
Peak memory 220116 kb
Host smart-19fa3018-3cf6-4fca-8566-4d577fca4bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803637234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2803637234
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1188980805
Short name T851
Test name
Test status
Simulation time 135892121 ps
CPU time 1.4 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:55 PM PDT 24
Peak memory 219420 kb
Host smart-29cd72f9-e3e4-4340-b14c-d9f9a932c458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188980805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1188980805
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.2850389818
Short name T118
Test name
Test status
Simulation time 84265545 ps
CPU time 1.13 seconds
Started Aug 12 06:22:49 PM PDT 24
Finished Aug 12 06:22:50 PM PDT 24
Peak memory 216024 kb
Host smart-be8d8e9c-b64c-4902-b655-29b464d8e795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850389818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2850389818
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/184.edn_alert.645396349
Short name T492
Test name
Test status
Simulation time 176497269 ps
CPU time 1.24 seconds
Started Aug 12 06:22:45 PM PDT 24
Finished Aug 12 06:22:47 PM PDT 24
Peak memory 219940 kb
Host smart-fbddf668-bf0e-4988-bdc3-d1d5b8eed5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645396349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.645396349
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.1051636773
Short name T792
Test name
Test status
Simulation time 33590617 ps
CPU time 1.02 seconds
Started Aug 12 06:22:41 PM PDT 24
Finished Aug 12 06:22:42 PM PDT 24
Peak memory 217532 kb
Host smart-fe695c36-2715-4930-9c62-e0e1f34ed811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051636773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1051636773
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2253728675
Short name T10
Test name
Test status
Simulation time 32610567 ps
CPU time 1.24 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:43 PM PDT 24
Peak memory 219464 kb
Host smart-894b7109-7580-48c4-a6ce-ee98e101b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253728675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2253728675
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1265524524
Short name T303
Test name
Test status
Simulation time 60331517 ps
CPU time 1.39 seconds
Started Aug 12 06:22:48 PM PDT 24
Finished Aug 12 06:22:49 PM PDT 24
Peak memory 218856 kb
Host smart-676cb30c-d6b6-49a2-b2b5-f0028147ce94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265524524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1265524524
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.3279761642
Short name T752
Test name
Test status
Simulation time 83301416 ps
CPU time 1.18 seconds
Started Aug 12 06:22:33 PM PDT 24
Finished Aug 12 06:22:34 PM PDT 24
Peak memory 218848 kb
Host smart-b51a2e07-33d8-4d3b-b884-f1f6d52b63e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279761642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3279761642
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.868845233
Short name T775
Test name
Test status
Simulation time 66006996 ps
CPU time 1.49 seconds
Started Aug 12 06:22:33 PM PDT 24
Finished Aug 12 06:22:34 PM PDT 24
Peak memory 219220 kb
Host smart-fb4870d3-4ef1-4d2f-b42a-ee619eabb6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868845233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.868845233
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.2110388055
Short name T318
Test name
Test status
Simulation time 224358150 ps
CPU time 1.25 seconds
Started Aug 12 06:22:48 PM PDT 24
Finished Aug 12 06:22:50 PM PDT 24
Peak memory 220436 kb
Host smart-78c9c062-8711-42ca-bb0f-2cefe55dffa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110388055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2110388055
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.1646965067
Short name T552
Test name
Test status
Simulation time 39419090 ps
CPU time 1.05 seconds
Started Aug 12 06:22:45 PM PDT 24
Finished Aug 12 06:22:46 PM PDT 24
Peak memory 219108 kb
Host smart-fe3342a2-ce15-4017-94ee-65c6119e40f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646965067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1646965067
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2697625610
Short name T184
Test name
Test status
Simulation time 21947266 ps
CPU time 1.14 seconds
Started Aug 12 06:22:30 PM PDT 24
Finished Aug 12 06:22:31 PM PDT 24
Peak memory 220012 kb
Host smart-4b5f656d-38b5-47dc-89c0-d9d43b715788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697625610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2697625610
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3035232137
Short name T328
Test name
Test status
Simulation time 35405556 ps
CPU time 1.45 seconds
Started Aug 12 06:23:04 PM PDT 24
Finished Aug 12 06:23:05 PM PDT 24
Peak memory 218912 kb
Host smart-84688f04-b3ab-48d3-813a-9a8bad491bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035232137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3035232137
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2445495776
Short name T185
Test name
Test status
Simulation time 49073696 ps
CPU time 1.11 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:43 PM PDT 24
Peak memory 219976 kb
Host smart-1d4c472a-f209-45c3-9bf3-83992e4b1cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445495776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2445495776
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2979188257
Short name T629
Test name
Test status
Simulation time 152640471 ps
CPU time 1.09 seconds
Started Aug 12 06:22:35 PM PDT 24
Finished Aug 12 06:22:36 PM PDT 24
Peak memory 219752 kb
Host smart-e3da7310-aca1-4053-a097-423f789c9a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979188257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2979188257
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2963660964
Short name T506
Test name
Test status
Simulation time 76530880 ps
CPU time 1.13 seconds
Started Aug 12 06:21:22 PM PDT 24
Finished Aug 12 06:21:24 PM PDT 24
Peak memory 220068 kb
Host smart-356973a6-462c-46bc-9bbf-b7c24fe8eeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963660964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2963660964
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1652468023
Short name T877
Test name
Test status
Simulation time 90800299 ps
CPU time 0.92 seconds
Started Aug 12 06:21:17 PM PDT 24
Finished Aug 12 06:21:18 PM PDT 24
Peak memory 207280 kb
Host smart-8f6afbea-205c-49a6-968f-ee47cc80243e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652468023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1652468023
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1233498696
Short name T94
Test name
Test status
Simulation time 12739070 ps
CPU time 0.89 seconds
Started Aug 12 06:21:03 PM PDT 24
Finished Aug 12 06:21:04 PM PDT 24
Peak memory 215996 kb
Host smart-ae9ae4f3-7c55-413e-a601-28ec719862da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233498696 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1233498696
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2137654293
Short name T738
Test name
Test status
Simulation time 40148560 ps
CPU time 1.13 seconds
Started Aug 12 06:21:10 PM PDT 24
Finished Aug 12 06:21:11 PM PDT 24
Peak memory 217628 kb
Host smart-c9f06799-e731-43ad-b49c-a1a941608a46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137654293 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2137654293
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.391331011
Short name T167
Test name
Test status
Simulation time 27883154 ps
CPU time 0.94 seconds
Started Aug 12 06:21:22 PM PDT 24
Finished Aug 12 06:21:23 PM PDT 24
Peak memory 224172 kb
Host smart-783743a8-578e-472a-bece-ee2dc42e648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391331011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.391331011
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1507096847
Short name T47
Test name
Test status
Simulation time 174134965 ps
CPU time 1.44 seconds
Started Aug 12 06:21:11 PM PDT 24
Finished Aug 12 06:21:12 PM PDT 24
Peak memory 217828 kb
Host smart-7536543d-bf24-4074-997b-5aa769f2a4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507096847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1507096847
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2221041272
Short name T518
Test name
Test status
Simulation time 58436403 ps
CPU time 0.91 seconds
Started Aug 12 06:20:57 PM PDT 24
Finished Aug 12 06:20:58 PM PDT 24
Peak memory 215624 kb
Host smart-905bcd4b-7f81-4ec5-9420-a6d6cedb3a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221041272 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2221041272
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.856037749
Short name T804
Test name
Test status
Simulation time 39672849 ps
CPU time 0.92 seconds
Started Aug 12 06:21:00 PM PDT 24
Finished Aug 12 06:21:01 PM PDT 24
Peak memory 215496 kb
Host smart-4fa7c561-aab7-427e-87eb-b2032c60af79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856037749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.856037749
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1160910380
Short name T255
Test name
Test status
Simulation time 762231386 ps
CPU time 1.51 seconds
Started Aug 12 06:21:15 PM PDT 24
Finished Aug 12 06:21:17 PM PDT 24
Peak memory 215624 kb
Host smart-b58a930c-8ae3-44b8-a604-f14b61341f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160910380 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1160910380
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_alert.1871438721
Short name T150
Test name
Test status
Simulation time 44269519 ps
CPU time 1.07 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:44 PM PDT 24
Peak memory 219068 kb
Host smart-0f62f4a8-d0ec-4e2d-a916-612027600646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871438721 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1871438721
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.2304893636
Short name T931
Test name
Test status
Simulation time 385787282 ps
CPU time 4.57 seconds
Started Aug 12 06:22:34 PM PDT 24
Finished Aug 12 06:22:39 PM PDT 24
Peak memory 217900 kb
Host smart-4a0ca705-8eeb-4af2-bbc0-711b9a3912df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304893636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2304893636
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.2293793907
Short name T623
Test name
Test status
Simulation time 269929756 ps
CPU time 1.13 seconds
Started Aug 12 06:22:48 PM PDT 24
Finished Aug 12 06:22:49 PM PDT 24
Peak memory 219852 kb
Host smart-9cbd43d4-ec44-4d32-aeae-3e06ebe91654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293793907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2293793907
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2283881189
Short name T529
Test name
Test status
Simulation time 31753008 ps
CPU time 1.17 seconds
Started Aug 12 06:22:44 PM PDT 24
Finished Aug 12 06:22:45 PM PDT 24
Peak memory 215664 kb
Host smart-b52d3fdb-2b54-4811-90f0-14b9b55f6f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283881189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2283881189
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2215535652
Short name T474
Test name
Test status
Simulation time 94084296 ps
CPU time 1.17 seconds
Started Aug 12 06:22:50 PM PDT 24
Finished Aug 12 06:22:52 PM PDT 24
Peak memory 219808 kb
Host smart-f483fa05-bcfe-468c-b57b-a5778ab987b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215535652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2215535652
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2585555754
Short name T932
Test name
Test status
Simulation time 114865523 ps
CPU time 1.3 seconds
Started Aug 12 06:22:27 PM PDT 24
Finished Aug 12 06:22:28 PM PDT 24
Peak memory 217760 kb
Host smart-171093ac-2e84-43fe-8857-921b879c0f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585555754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2585555754
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.1859527364
Short name T703
Test name
Test status
Simulation time 266484413 ps
CPU time 1.11 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:43 PM PDT 24
Peak memory 219968 kb
Host smart-ee5dedba-d4db-4f4c-b3ce-7ebd223ca30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859527364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1859527364
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2741927082
Short name T935
Test name
Test status
Simulation time 157908250 ps
CPU time 1.19 seconds
Started Aug 12 06:22:40 PM PDT 24
Finished Aug 12 06:22:42 PM PDT 24
Peak memory 217848 kb
Host smart-814c763f-0daa-4770-aebd-233de3f2c543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741927082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2741927082
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.827467378
Short name T147
Test name
Test status
Simulation time 27320055 ps
CPU time 1.22 seconds
Started Aug 12 06:22:45 PM PDT 24
Finished Aug 12 06:22:47 PM PDT 24
Peak memory 216060 kb
Host smart-fe42f4d1-c7bf-4ec2-9bff-1a109e8fa92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827467378 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.827467378
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.803563259
Short name T763
Test name
Test status
Simulation time 56994328 ps
CPU time 1.48 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:56 PM PDT 24
Peak memory 218924 kb
Host smart-7f63aba0-b156-4bf3-9717-174b10435c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803563259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.803563259
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2742878071
Short name T49
Test name
Test status
Simulation time 67820515 ps
CPU time 1.14 seconds
Started Aug 12 06:22:51 PM PDT 24
Finished Aug 12 06:22:52 PM PDT 24
Peak memory 218952 kb
Host smart-b2cd849c-b609-4308-9056-bab371277e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742878071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2742878071
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.2203306804
Short name T456
Test name
Test status
Simulation time 23429692 ps
CPU time 1.04 seconds
Started Aug 12 06:22:36 PM PDT 24
Finished Aug 12 06:22:37 PM PDT 24
Peak memory 217912 kb
Host smart-743a503f-d2aa-45be-a4ea-7acee7d535d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203306804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2203306804
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.2610315880
Short name T922
Test name
Test status
Simulation time 23678564 ps
CPU time 1.13 seconds
Started Aug 12 06:22:53 PM PDT 24
Finished Aug 12 06:22:54 PM PDT 24
Peak memory 218936 kb
Host smart-24295f14-9597-40ac-b999-fadf89a6d0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610315880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2610315880
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.1193792299
Short name T558
Test name
Test status
Simulation time 44265039 ps
CPU time 1.42 seconds
Started Aug 12 06:22:51 PM PDT 24
Finished Aug 12 06:22:52 PM PDT 24
Peak memory 215640 kb
Host smart-484adde5-ec35-4f6d-bada-9e312670826a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193792299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1193792299
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.2159710759
Short name T725
Test name
Test status
Simulation time 34878002 ps
CPU time 1.31 seconds
Started Aug 12 06:22:55 PM PDT 24
Finished Aug 12 06:22:57 PM PDT 24
Peak memory 220340 kb
Host smart-a2d23b41-11b1-4018-b2c7-a4602271882d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159710759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.2159710759
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.2559915973
Short name T916
Test name
Test status
Simulation time 84156561 ps
CPU time 1.35 seconds
Started Aug 12 06:22:35 PM PDT 24
Finished Aug 12 06:22:36 PM PDT 24
Peak memory 218104 kb
Host smart-95f9ff0f-28d7-4888-8462-a311fef9d700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559915973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2559915973
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.593706845
Short name T130
Test name
Test status
Simulation time 47519481 ps
CPU time 1.19 seconds
Started Aug 12 06:22:36 PM PDT 24
Finished Aug 12 06:22:38 PM PDT 24
Peak memory 218940 kb
Host smart-f289da5a-5e78-4e71-a2d5-71845009acf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593706845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.593706845
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/199.edn_alert.3776883494
Short name T266
Test name
Test status
Simulation time 26847090 ps
CPU time 1.24 seconds
Started Aug 12 06:22:48 PM PDT 24
Finished Aug 12 06:22:49 PM PDT 24
Peak memory 219072 kb
Host smart-12bc17e0-817d-4ced-ab63-623bedc7caa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776883494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3776883494
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.236608803
Short name T465
Test name
Test status
Simulation time 105556513 ps
CPU time 1.47 seconds
Started Aug 12 06:22:33 PM PDT 24
Finished Aug 12 06:22:35 PM PDT 24
Peak memory 220704 kb
Host smart-c7afb41a-7946-484b-9466-81efeaf2fdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236608803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.236608803
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2734083528
Short name T608
Test name
Test status
Simulation time 45038176 ps
CPU time 1.21 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 221832 kb
Host smart-8dfec307-2945-4e6e-9c05-4575a37198a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734083528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2734083528
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2606152313
Short name T619
Test name
Test status
Simulation time 32277363 ps
CPU time 1.05 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:36 PM PDT 24
Peak memory 207436 kb
Host smart-a4fa67ad-e4f6-46ef-8c5d-8dd13743996c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606152313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2606152313
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.697607364
Short name T777
Test name
Test status
Simulation time 30980086 ps
CPU time 0.85 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:36 PM PDT 24
Peak memory 215868 kb
Host smart-2b4ece80-b638-4d3f-90b1-c15c68a20822
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697607364 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.697607364
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2845606915
Short name T488
Test name
Test status
Simulation time 108933601 ps
CPU time 1.06 seconds
Started Aug 12 06:20:38 PM PDT 24
Finished Aug 12 06:20:39 PM PDT 24
Peak memory 219944 kb
Host smart-0fe0a0e7-b528-4fb0-9222-da3706ccbb05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845606915 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2845606915
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1232823205
Short name T8
Test name
Test status
Simulation time 30398063 ps
CPU time 1.14 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 229964 kb
Host smart-1f7cc656-0516-4bd7-a338-b80273c6857d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232823205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1232823205
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.201228369
Short name T944
Test name
Test status
Simulation time 69786244 ps
CPU time 1.62 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:36 PM PDT 24
Peak memory 217940 kb
Host smart-857c1da1-67c3-4193-8f88-f3e0ab05ec2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201228369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.201228369
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3527000054
Short name T754
Test name
Test status
Simulation time 22308846 ps
CPU time 1.09 seconds
Started Aug 12 06:20:41 PM PDT 24
Finished Aug 12 06:20:42 PM PDT 24
Peak memory 215796 kb
Host smart-d92fe496-04c5-414a-8980-d251513a20b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527000054 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3527000054
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2677056236
Short name T661
Test name
Test status
Simulation time 17280804 ps
CPU time 1 seconds
Started Aug 12 06:20:34 PM PDT 24
Finished Aug 12 06:20:35 PM PDT 24
Peak memory 207424 kb
Host smart-592ae984-c380-414b-a476-8bcf0c70d11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677056236 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2677056236
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1782622656
Short name T20
Test name
Test status
Simulation time 881932140 ps
CPU time 13.26 seconds
Started Aug 12 06:20:37 PM PDT 24
Finished Aug 12 06:20:50 PM PDT 24
Peak memory 239732 kb
Host smart-11991f5d-c77f-4ec1-9cf6-25de6252e1a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782622656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1782622656
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.954282736
Short name T371
Test name
Test status
Simulation time 18965115 ps
CPU time 1.01 seconds
Started Aug 12 06:20:36 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 215704 kb
Host smart-472dc496-3864-4550-8f26-a5c1d48e48d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954282736 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.954282736
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3035049728
Short name T622
Test name
Test status
Simulation time 135516881 ps
CPU time 2.88 seconds
Started Aug 12 06:20:34 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 218700 kb
Host smart-d1e8dd4a-5cb7-41ba-b66f-4f370a64b823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035049728 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3035049728
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.80739080
Short name T418
Test name
Test status
Simulation time 8682602971 ps
CPU time 27.61 seconds
Started Aug 12 06:20:34 PM PDT 24
Finished Aug 12 06:21:02 PM PDT 24
Peak memory 218736 kb
Host smart-8d6b03a8-e0e3-4c54-bdec-d5cc58fb91e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80739080 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.80739080
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1591066502
Short name T609
Test name
Test status
Simulation time 151589673 ps
CPU time 1.13 seconds
Started Aug 12 06:21:13 PM PDT 24
Finished Aug 12 06:21:14 PM PDT 24
Peak memory 220008 kb
Host smart-012f1bb1-cc95-429c-87d1-f57c957bb0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591066502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1591066502
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3818971724
Short name T26
Test name
Test status
Simulation time 15544232 ps
CPU time 0.92 seconds
Started Aug 12 06:21:00 PM PDT 24
Finished Aug 12 06:21:01 PM PDT 24
Peak memory 207332 kb
Host smart-4f5573c1-35da-4adc-97c6-61f9bab203a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818971724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3818971724
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2992808347
Short name T496
Test name
Test status
Simulation time 19345710 ps
CPU time 0.94 seconds
Started Aug 12 06:21:17 PM PDT 24
Finished Aug 12 06:21:18 PM PDT 24
Peak memory 216592 kb
Host smart-04c878a1-5936-4dd3-8108-8096eab87c65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992808347 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2992808347
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.337605681
Short name T208
Test name
Test status
Simulation time 56170296 ps
CPU time 1.36 seconds
Started Aug 12 06:21:10 PM PDT 24
Finished Aug 12 06:21:12 PM PDT 24
Peak memory 217732 kb
Host smart-f41146ae-f8b3-448e-833c-1cf6754ec79d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337605681 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.337605681
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2030062434
Short name T521
Test name
Test status
Simulation time 44435890 ps
CPU time 0.94 seconds
Started Aug 12 06:21:02 PM PDT 24
Finished Aug 12 06:21:03 PM PDT 24
Peak memory 224136 kb
Host smart-4988f298-f144-4865-9de6-29944375496e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030062434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2030062434
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.723998153
Short name T723
Test name
Test status
Simulation time 66934468 ps
CPU time 1.12 seconds
Started Aug 12 06:21:23 PM PDT 24
Finished Aug 12 06:21:24 PM PDT 24
Peak memory 217760 kb
Host smart-4de66fc4-e87f-4cb7-9263-cb7ee6e46783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723998153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.723998153
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2101588527
Short name T952
Test name
Test status
Simulation time 34090399 ps
CPU time 0.95 seconds
Started Aug 12 06:21:13 PM PDT 24
Finished Aug 12 06:21:14 PM PDT 24
Peak memory 215744 kb
Host smart-a8efb0cc-601d-440a-80cd-126a58276b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101588527 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2101588527
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.324219288
Short name T86
Test name
Test status
Simulation time 60439917 ps
CPU time 0.91 seconds
Started Aug 12 06:21:01 PM PDT 24
Finished Aug 12 06:21:02 PM PDT 24
Peak memory 215668 kb
Host smart-3c986c86-d66a-4ea4-a67b-d0f2f44d6953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324219288 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.324219288
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3835334815
Short name T814
Test name
Test status
Simulation time 438093270 ps
CPU time 1.72 seconds
Started Aug 12 06:21:11 PM PDT 24
Finished Aug 12 06:21:13 PM PDT 24
Peak memory 217868 kb
Host smart-617af3d6-c77d-49f2-9802-52d18cbb419c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835334815 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3835334815
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/200.edn_genbits.4138327219
Short name T342
Test name
Test status
Simulation time 128802248 ps
CPU time 1.62 seconds
Started Aug 12 06:22:47 PM PDT 24
Finished Aug 12 06:22:49 PM PDT 24
Peak memory 219000 kb
Host smart-8c6f450a-d22e-4718-997b-772e1cfaabe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138327219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.4138327219
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.706230434
Short name T528
Test name
Test status
Simulation time 45651174 ps
CPU time 1.27 seconds
Started Aug 12 06:22:53 PM PDT 24
Finished Aug 12 06:22:54 PM PDT 24
Peak memory 217788 kb
Host smart-f18b11ce-5ac2-43af-968e-be3d8a29c90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706230434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.706230434
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2292827576
Short name T636
Test name
Test status
Simulation time 56223578 ps
CPU time 1.26 seconds
Started Aug 12 06:22:41 PM PDT 24
Finished Aug 12 06:22:43 PM PDT 24
Peak memory 217644 kb
Host smart-754b9286-dd45-4c2d-8b1a-25b044688160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292827576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2292827576
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.306723557
Short name T813
Test name
Test status
Simulation time 107625405 ps
CPU time 1.24 seconds
Started Aug 12 06:22:40 PM PDT 24
Finished Aug 12 06:22:42 PM PDT 24
Peak memory 220396 kb
Host smart-097ac40b-08c3-495e-ac0f-68678cda2888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306723557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.306723557
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3435147765
Short name T78
Test name
Test status
Simulation time 29037113 ps
CPU time 1.21 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:44 PM PDT 24
Peak memory 217792 kb
Host smart-bb9516b3-2c11-4371-a60b-41f8a04bd991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435147765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3435147765
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1050554870
Short name T626
Test name
Test status
Simulation time 186800178 ps
CPU time 1.37 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:55 PM PDT 24
Peak memory 219624 kb
Host smart-610f9cfd-2552-41f4-bac9-acea192a7ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050554870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1050554870
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3813128808
Short name T43
Test name
Test status
Simulation time 41614022 ps
CPU time 1.09 seconds
Started Aug 12 06:22:28 PM PDT 24
Finished Aug 12 06:22:30 PM PDT 24
Peak memory 217808 kb
Host smart-bd69c1ad-2f27-44a8-85c9-2007c1cfc05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813128808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3813128808
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2676944324
Short name T872
Test name
Test status
Simulation time 69197684 ps
CPU time 0.94 seconds
Started Aug 12 06:22:37 PM PDT 24
Finished Aug 12 06:22:38 PM PDT 24
Peak memory 217648 kb
Host smart-b5332784-f9f4-4fa4-865e-060ee1d25a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676944324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2676944324
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4272236571
Short name T515
Test name
Test status
Simulation time 45294365 ps
CPU time 1.21 seconds
Started Aug 12 06:22:38 PM PDT 24
Finished Aug 12 06:22:39 PM PDT 24
Peak memory 219208 kb
Host smart-fa7794fd-ec18-468a-b937-7b7e58cc6dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272236571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4272236571
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3291788977
Short name T93
Test name
Test status
Simulation time 39782345 ps
CPU time 1.4 seconds
Started Aug 12 06:22:37 PM PDT 24
Finished Aug 12 06:22:39 PM PDT 24
Peak memory 218964 kb
Host smart-fa5125a5-652b-4c05-9842-de6a18a01920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291788977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3291788977
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.2984500477
Short name T848
Test name
Test status
Simulation time 30925250 ps
CPU time 0.83 seconds
Started Aug 12 06:21:14 PM PDT 24
Finished Aug 12 06:21:15 PM PDT 24
Peak memory 207252 kb
Host smart-8b38b858-6733-4a13-97aa-364aa0502fc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984500477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2984500477
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3018633948
Short name T79
Test name
Test status
Simulation time 29905058 ps
CPU time 0.89 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 219192 kb
Host smart-babd1f2a-ace4-4909-9f8a-6cb770b6596c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018633948 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3018633948
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3315884714
Short name T928
Test name
Test status
Simulation time 21582921 ps
CPU time 1.19 seconds
Started Aug 12 06:21:00 PM PDT 24
Finished Aug 12 06:21:02 PM PDT 24
Peak memory 217724 kb
Host smart-707a1000-789d-4e9f-a9bc-9cca4efe45e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315884714 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3315884714
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2685582225
Short name T124
Test name
Test status
Simulation time 23125316 ps
CPU time 1.08 seconds
Started Aug 12 06:21:15 PM PDT 24
Finished Aug 12 06:21:17 PM PDT 24
Peak memory 220388 kb
Host smart-cd1e2b0d-c0bb-488e-a570-20eaf8527a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685582225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2685582225
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.564837657
Short name T713
Test name
Test status
Simulation time 34434738 ps
CPU time 1.36 seconds
Started Aug 12 06:20:58 PM PDT 24
Finished Aug 12 06:21:00 PM PDT 24
Peak memory 218832 kb
Host smart-0a8260fb-8661-45fd-b84c-7ab56a7f6ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564837657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.564837657
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1964993694
Short name T453
Test name
Test status
Simulation time 36842948 ps
CPU time 0.86 seconds
Started Aug 12 06:21:27 PM PDT 24
Finished Aug 12 06:21:28 PM PDT 24
Peak memory 215728 kb
Host smart-02a727d0-e54f-4ecc-947b-3ba7986228f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964993694 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1964993694
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.970513835
Short name T744
Test name
Test status
Simulation time 27280631 ps
CPU time 0.91 seconds
Started Aug 12 06:20:57 PM PDT 24
Finished Aug 12 06:20:58 PM PDT 24
Peak memory 215684 kb
Host smart-fc5aa615-2521-4935-b091-94adf5717294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970513835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.970513835
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.747947302
Short name T111
Test name
Test status
Simulation time 280741037 ps
CPU time 2.11 seconds
Started Aug 12 06:20:57 PM PDT 24
Finished Aug 12 06:20:59 PM PDT 24
Peak memory 217600 kb
Host smart-754de7a5-3f9c-447d-a61b-41f27582971d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747947302 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.747947302
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/210.edn_genbits.751633601
Short name T460
Test name
Test status
Simulation time 36897864 ps
CPU time 1.45 seconds
Started Aug 12 06:22:49 PM PDT 24
Finished Aug 12 06:22:51 PM PDT 24
Peak memory 217616 kb
Host smart-b975757f-d41d-4bac-b094-e7298984c39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751633601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.751633601
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.4149655986
Short name T844
Test name
Test status
Simulation time 62959078 ps
CPU time 2.49 seconds
Started Aug 12 06:22:47 PM PDT 24
Finished Aug 12 06:22:50 PM PDT 24
Peak memory 220600 kb
Host smart-0634ba8e-025c-4fc6-b676-88598a644326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149655986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.4149655986
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1946964714
Short name T262
Test name
Test status
Simulation time 82596594 ps
CPU time 1.08 seconds
Started Aug 12 06:22:43 PM PDT 24
Finished Aug 12 06:22:44 PM PDT 24
Peak memory 217888 kb
Host smart-e69c48f4-9041-4a0f-ace9-31ba29534179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946964714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1946964714
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2885306050
Short name T373
Test name
Test status
Simulation time 41122988 ps
CPU time 1.43 seconds
Started Aug 12 06:22:49 PM PDT 24
Finished Aug 12 06:22:51 PM PDT 24
Peak memory 219020 kb
Host smart-c08e4ba7-19e9-4977-b6e5-af1cbb5528d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885306050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2885306050
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.4077213263
Short name T831
Test name
Test status
Simulation time 35797438 ps
CPU time 1.34 seconds
Started Aug 12 06:23:08 PM PDT 24
Finished Aug 12 06:23:10 PM PDT 24
Peak memory 218920 kb
Host smart-3b9014eb-c377-423f-815e-f71f686eb195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077213263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.4077213263
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4036489546
Short name T392
Test name
Test status
Simulation time 78927712 ps
CPU time 1.17 seconds
Started Aug 12 06:22:57 PM PDT 24
Finished Aug 12 06:22:59 PM PDT 24
Peak memory 219096 kb
Host smart-b09082cc-ff97-4d81-bea9-c771993e0608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036489546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4036489546
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2310616557
Short name T431
Test name
Test status
Simulation time 55050401 ps
CPU time 1.32 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:06 PM PDT 24
Peak memory 217600 kb
Host smart-f18f425b-ff8c-42cf-a2d2-41c397e4e2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310616557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2310616557
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3800330518
Short name T604
Test name
Test status
Simulation time 42204443 ps
CPU time 1.59 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:44 PM PDT 24
Peak memory 217504 kb
Host smart-2eb37968-6e7e-4039-8a56-a4bccbcb8d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800330518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3800330518
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1754659825
Short name T641
Test name
Test status
Simulation time 36569164 ps
CPU time 1.17 seconds
Started Aug 12 06:21:00 PM PDT 24
Finished Aug 12 06:21:01 PM PDT 24
Peak memory 218892 kb
Host smart-fdb7340e-28bb-4dc9-9f10-3f044889d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754659825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1754659825
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1096933432
Short name T360
Test name
Test status
Simulation time 254706846 ps
CPU time 0.9 seconds
Started Aug 12 06:21:00 PM PDT 24
Finished Aug 12 06:21:01 PM PDT 24
Peak memory 207280 kb
Host smart-f654ebce-11fb-4487-8683-c52ab0704ee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096933432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1096933432
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1855516517
Short name T213
Test name
Test status
Simulation time 46722237 ps
CPU time 0.89 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 216908 kb
Host smart-cc9f703d-9ff4-4ed5-85a9-0e8e0525522f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855516517 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1855516517
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1842657544
Short name T768
Test name
Test status
Simulation time 232151743 ps
CPU time 1.04 seconds
Started Aug 12 06:20:58 PM PDT 24
Finished Aug 12 06:20:59 PM PDT 24
Peak memory 220196 kb
Host smart-877d05cc-5187-4fd8-be73-c0218d7774cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842657544 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1842657544
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1160496957
Short name T168
Test name
Test status
Simulation time 36728520 ps
CPU time 0.93 seconds
Started Aug 12 06:21:13 PM PDT 24
Finished Aug 12 06:21:14 PM PDT 24
Peak memory 218996 kb
Host smart-02cddbff-3ebe-411b-a628-ba08ff4a12a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160496957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1160496957
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1191376198
Short name T405
Test name
Test status
Simulation time 113388627 ps
CPU time 1.08 seconds
Started Aug 12 06:20:57 PM PDT 24
Finished Aug 12 06:20:58 PM PDT 24
Peak memory 217688 kb
Host smart-bc7ccd51-bfd7-47bc-9e86-d9463b624d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191376198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1191376198
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1495442497
Short name T248
Test name
Test status
Simulation time 31217454 ps
CPU time 0.91 seconds
Started Aug 12 06:21:02 PM PDT 24
Finished Aug 12 06:21:03 PM PDT 24
Peak memory 215728 kb
Host smart-e008f548-b5de-4f56-8a1c-7121194d14f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495442497 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1495442497
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.4272638942
Short name T866
Test name
Test status
Simulation time 30834668 ps
CPU time 1.04 seconds
Started Aug 12 06:21:00 PM PDT 24
Finished Aug 12 06:21:02 PM PDT 24
Peak memory 215796 kb
Host smart-d10a16e9-360e-4ee4-98b9-1157d1681cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272638942 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.4272638942
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2428516604
Short name T256
Test name
Test status
Simulation time 52318487 ps
CPU time 1.2 seconds
Started Aug 12 06:20:59 PM PDT 24
Finished Aug 12 06:21:00 PM PDT 24
Peak memory 207344 kb
Host smart-5fef8abb-b368-4ea8-9c0b-dd9276dbabb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428516604 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2428516604
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1087215161
Short name T676
Test name
Test status
Simulation time 2488581300 ps
CPU time 58.67 seconds
Started Aug 12 06:21:00 PM PDT 24
Finished Aug 12 06:21:59 PM PDT 24
Peak memory 218036 kb
Host smart-6bd91886-b3fc-47e6-85ac-549224efdde6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087215161 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1087215161
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3609431157
Short name T101
Test name
Test status
Simulation time 112721434 ps
CPU time 1.18 seconds
Started Aug 12 06:22:49 PM PDT 24
Finished Aug 12 06:22:50 PM PDT 24
Peak memory 219468 kb
Host smart-72fa88e2-e7a8-4eac-bd87-5b500eb7ea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609431157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3609431157
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1570433018
Short name T13
Test name
Test status
Simulation time 30372620 ps
CPU time 1.31 seconds
Started Aug 12 06:22:50 PM PDT 24
Finished Aug 12 06:22:51 PM PDT 24
Peak memory 220168 kb
Host smart-87a01858-4301-4de0-8633-af3cc13e0416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570433018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1570433018
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1749525564
Short name T408
Test name
Test status
Simulation time 33166282 ps
CPU time 1.37 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:55 PM PDT 24
Peak memory 217652 kb
Host smart-3db2ce70-a852-469e-8a56-8c0e7bae4d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749525564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1749525564
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2225265655
Short name T728
Test name
Test status
Simulation time 200113982 ps
CPU time 1 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:55 PM PDT 24
Peak memory 217740 kb
Host smart-a9a2e99b-0497-4489-8b35-5d6a26a5da51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225265655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2225265655
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3418084505
Short name T477
Test name
Test status
Simulation time 99043662 ps
CPU time 3.22 seconds
Started Aug 12 06:22:58 PM PDT 24
Finished Aug 12 06:23:02 PM PDT 24
Peak memory 220684 kb
Host smart-bd05b428-3e68-4689-ba21-2e028abe9e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418084505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3418084505
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3263267079
Short name T327
Test name
Test status
Simulation time 86073333 ps
CPU time 1.08 seconds
Started Aug 12 06:22:38 PM PDT 24
Finished Aug 12 06:22:39 PM PDT 24
Peak memory 217804 kb
Host smart-32f1197e-30a5-4ece-8df2-fee8ee6594fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263267079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3263267079
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.242540339
Short name T484
Test name
Test status
Simulation time 44922400 ps
CPU time 1.59 seconds
Started Aug 12 06:22:48 PM PDT 24
Finished Aug 12 06:22:49 PM PDT 24
Peak memory 218876 kb
Host smart-7170c265-2b56-4b28-9e3e-0057f0ed26a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242540339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.242540339
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1313017312
Short name T384
Test name
Test status
Simulation time 1080215339 ps
CPU time 8 seconds
Started Aug 12 06:23:06 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 220504 kb
Host smart-12f77b3e-91fc-4586-a20e-99e9aff7a06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313017312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1313017312
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1537351898
Short name T562
Test name
Test status
Simulation time 33408537 ps
CPU time 1.69 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:07 PM PDT 24
Peak memory 219464 kb
Host smart-c86e0baf-4cff-4849-9ad8-8c70840f19e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537351898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1537351898
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3450181333
Short name T347
Test name
Test status
Simulation time 83857370 ps
CPU time 1.41 seconds
Started Aug 12 06:22:53 PM PDT 24
Finished Aug 12 06:22:55 PM PDT 24
Peak memory 219252 kb
Host smart-480ad7d4-9347-4009-9696-f2e7b2161497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450181333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3450181333
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.4094173261
Short name T750
Test name
Test status
Simulation time 26096095 ps
CPU time 1.29 seconds
Started Aug 12 06:21:21 PM PDT 24
Finished Aug 12 06:21:23 PM PDT 24
Peak memory 219140 kb
Host smart-0a2af104-1584-4a0e-9a67-0fec998e0a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094173261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.4094173261
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3171691694
Short name T958
Test name
Test status
Simulation time 11746246 ps
CPU time 0.85 seconds
Started Aug 12 06:21:02 PM PDT 24
Finished Aug 12 06:21:03 PM PDT 24
Peak memory 207204 kb
Host smart-2edd3b3a-a596-40fd-9c8b-d2b91aec407f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171691694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3171691694
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1581949800
Short name T970
Test name
Test status
Simulation time 55378214 ps
CPU time 0.81 seconds
Started Aug 12 06:21:02 PM PDT 24
Finished Aug 12 06:21:03 PM PDT 24
Peak memory 216020 kb
Host smart-21e3ba78-a5d3-4e83-9f71-3afe5d3235f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581949800 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1581949800
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3158931452
Short name T939
Test name
Test status
Simulation time 36254398 ps
CPU time 1.22 seconds
Started Aug 12 06:21:11 PM PDT 24
Finished Aug 12 06:21:12 PM PDT 24
Peak memory 217628 kb
Host smart-e8dd5ce2-5f64-400e-a469-a74c3f9221de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158931452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3158931452
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2897746315
Short name T191
Test name
Test status
Simulation time 69718755 ps
CPU time 0.86 seconds
Started Aug 12 06:21:18 PM PDT 24
Finished Aug 12 06:21:19 PM PDT 24
Peak memory 218868 kb
Host smart-2a380fe6-1f59-4622-b224-7355ecf4d96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897746315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2897746315
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1850353951
Short name T69
Test name
Test status
Simulation time 81086435 ps
CPU time 1.36 seconds
Started Aug 12 06:20:58 PM PDT 24
Finished Aug 12 06:21:00 PM PDT 24
Peak memory 219484 kb
Host smart-d7a385c9-d073-495a-99b8-cb1a4b428625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850353951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1850353951
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1438578943
Short name T915
Test name
Test status
Simulation time 49917558 ps
CPU time 0.86 seconds
Started Aug 12 06:21:13 PM PDT 24
Finished Aug 12 06:21:14 PM PDT 24
Peak memory 215792 kb
Host smart-e0ba894c-d290-4b29-81db-b7e34edbcfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438578943 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1438578943
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3947033490
Short name T68
Test name
Test status
Simulation time 18633518 ps
CPU time 0.96 seconds
Started Aug 12 06:20:57 PM PDT 24
Finished Aug 12 06:20:58 PM PDT 24
Peak memory 215664 kb
Host smart-518c7d6f-8137-4723-ba69-f0661e11f3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947033490 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3947033490
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3786682554
Short name T900
Test name
Test status
Simulation time 337394910 ps
CPU time 6.34 seconds
Started Aug 12 06:21:01 PM PDT 24
Finished Aug 12 06:21:07 PM PDT 24
Peak memory 217704 kb
Host smart-c5cbdc39-56ec-47f3-ba77-9ab167a93b3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786682554 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3786682554
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3736313573
Short name T232
Test name
Test status
Simulation time 39622881864 ps
CPU time 109.59 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:23:08 PM PDT 24
Peak memory 224104 kb
Host smart-afee8a80-1a90-4f30-bb68-1953ace69c73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736313573 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3736313573
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1454623307
Short name T400
Test name
Test status
Simulation time 61312280 ps
CPU time 1.2 seconds
Started Aug 12 06:22:41 PM PDT 24
Finished Aug 12 06:22:42 PM PDT 24
Peak memory 217740 kb
Host smart-3f14e0bf-971b-480b-bd99-ae1788a6fa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454623307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1454623307
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1228633478
Short name T842
Test name
Test status
Simulation time 61717409 ps
CPU time 2.26 seconds
Started Aug 12 06:22:50 PM PDT 24
Finished Aug 12 06:22:53 PM PDT 24
Peak memory 220628 kb
Host smart-7087b241-f564-4e2b-af5e-b4221afba465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228633478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1228633478
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3636904823
Short name T668
Test name
Test status
Simulation time 42000801 ps
CPU time 1.76 seconds
Started Aug 12 06:22:52 PM PDT 24
Finished Aug 12 06:22:53 PM PDT 24
Peak memory 219116 kb
Host smart-1835c839-d86d-493d-ac49-4afd3aca7cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636904823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3636904823
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.4125290071
Short name T382
Test name
Test status
Simulation time 125939765 ps
CPU time 1.61 seconds
Started Aug 12 06:22:47 PM PDT 24
Finished Aug 12 06:22:49 PM PDT 24
Peak memory 220432 kb
Host smart-7c8fa6c3-78c8-4138-bde5-13f42b7ae7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125290071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.4125290071
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3998089486
Short name T683
Test name
Test status
Simulation time 30509202 ps
CPU time 1.18 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:55 PM PDT 24
Peak memory 219104 kb
Host smart-a5fcbcfe-aee5-49cb-b6b1-38971eb20c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998089486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3998089486
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.4162414481
Short name T698
Test name
Test status
Simulation time 98377837 ps
CPU time 1.12 seconds
Started Aug 12 06:22:58 PM PDT 24
Finished Aug 12 06:22:59 PM PDT 24
Peak memory 217720 kb
Host smart-d0c72d75-c4e1-4bd1-8476-22cff97a7330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162414481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.4162414481
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.214684962
Short name T65
Test name
Test status
Simulation time 53279136 ps
CPU time 1.96 seconds
Started Aug 12 06:22:46 PM PDT 24
Finished Aug 12 06:22:48 PM PDT 24
Peak memory 220100 kb
Host smart-a34eb0c7-5757-44ea-b0ca-34dedfee9f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214684962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.214684962
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.30050587
Short name T325
Test name
Test status
Simulation time 47667659 ps
CPU time 1.62 seconds
Started Aug 12 06:23:00 PM PDT 24
Finished Aug 12 06:23:02 PM PDT 24
Peak memory 219092 kb
Host smart-31a5605c-1427-44b0-b7ba-7877891a9e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30050587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.30050587
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1896661580
Short name T389
Test name
Test status
Simulation time 164814079 ps
CPU time 1.06 seconds
Started Aug 12 06:22:57 PM PDT 24
Finished Aug 12 06:22:58 PM PDT 24
Peak memory 217776 kb
Host smart-afb9cfff-2344-461c-9133-a48f500485e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896661580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1896661580
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2770931175
Short name T911
Test name
Test status
Simulation time 95539326 ps
CPU time 1.53 seconds
Started Aug 12 06:22:50 PM PDT 24
Finished Aug 12 06:22:51 PM PDT 24
Peak memory 218968 kb
Host smart-c7df4e57-db88-43fa-9a28-fb9daf277412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770931175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2770931175
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1308845151
Short name T114
Test name
Test status
Simulation time 85418200 ps
CPU time 1.12 seconds
Started Aug 12 06:21:16 PM PDT 24
Finished Aug 12 06:21:17 PM PDT 24
Peak memory 220628 kb
Host smart-20714331-9cff-472c-b4e3-3d7c7cca8947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308845151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1308845151
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2596963301
Short name T545
Test name
Test status
Simulation time 47349819 ps
CPU time 0.85 seconds
Started Aug 12 06:21:16 PM PDT 24
Finished Aug 12 06:21:17 PM PDT 24
Peak memory 207268 kb
Host smart-6f4ce4e6-88c9-420f-bc2d-ecdcc033c53a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596963301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2596963301
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3412196439
Short name T830
Test name
Test status
Simulation time 30644919 ps
CPU time 0.82 seconds
Started Aug 12 06:21:12 PM PDT 24
Finished Aug 12 06:21:13 PM PDT 24
Peak memory 216976 kb
Host smart-294bd3d3-731c-4a55-b5ec-ca7000ccfd54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412196439 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3412196439
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.4089770415
Short name T216
Test name
Test status
Simulation time 23168683 ps
CPU time 1.16 seconds
Started Aug 12 06:21:20 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 220200 kb
Host smart-dc99af02-f71e-4d98-849c-d2cf622b88cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089770415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.4089770415
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1894580635
Short name T531
Test name
Test status
Simulation time 48137773 ps
CPU time 1.13 seconds
Started Aug 12 06:21:01 PM PDT 24
Finished Aug 12 06:21:02 PM PDT 24
Peak memory 217656 kb
Host smart-f464d54b-4628-41a4-8e7f-a92fc2c30c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894580635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1894580635
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.205450804
Short name T87
Test name
Test status
Simulation time 22124851 ps
CPU time 1.1 seconds
Started Aug 12 06:21:16 PM PDT 24
Finished Aug 12 06:21:17 PM PDT 24
Peak memory 216024 kb
Host smart-b52e3ad3-8d24-4d4c-9078-99181b5c7b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205450804 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.205450804
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3182644658
Short name T291
Test name
Test status
Simulation time 23747767 ps
CPU time 0.92 seconds
Started Aug 12 06:21:02 PM PDT 24
Finished Aug 12 06:21:03 PM PDT 24
Peak memory 214908 kb
Host smart-e2661d1d-56fb-4972-b669-2dacca3addff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182644658 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3182644658
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3454811593
Short name T614
Test name
Test status
Simulation time 140114692 ps
CPU time 3.1 seconds
Started Aug 12 06:21:02 PM PDT 24
Finished Aug 12 06:21:05 PM PDT 24
Peak memory 215760 kb
Host smart-b7f57e5a-5111-4122-874b-b1990e091f3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454811593 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3454811593
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1742310640
Short name T237
Test name
Test status
Simulation time 5857790860 ps
CPU time 43.55 seconds
Started Aug 12 06:21:24 PM PDT 24
Finished Aug 12 06:22:07 PM PDT 24
Peak memory 221504 kb
Host smart-153c6d80-a040-4f9c-aef1-0a6170dd538f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742310640 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1742310640
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3783732804
Short name T554
Test name
Test status
Simulation time 40872233 ps
CPU time 1.7 seconds
Started Aug 12 06:22:41 PM PDT 24
Finished Aug 12 06:22:43 PM PDT 24
Peak memory 219008 kb
Host smart-b41f839a-d457-4600-aac0-ff63aaaf24d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783732804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3783732804
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1478788435
Short name T445
Test name
Test status
Simulation time 43564574 ps
CPU time 1.55 seconds
Started Aug 12 06:22:47 PM PDT 24
Finished Aug 12 06:22:53 PM PDT 24
Peak memory 217764 kb
Host smart-65da8a09-fbfd-4590-bc98-5b46581cdfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478788435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1478788435
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2193395349
Short name T785
Test name
Test status
Simulation time 34834601 ps
CPU time 1.34 seconds
Started Aug 12 06:23:01 PM PDT 24
Finished Aug 12 06:23:02 PM PDT 24
Peak memory 218856 kb
Host smart-44a9dd7c-ef16-4fe5-a5a5-39035959edd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193395349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2193395349
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.250682583
Short name T693
Test name
Test status
Simulation time 40175173 ps
CPU time 1.14 seconds
Started Aug 12 06:22:41 PM PDT 24
Finished Aug 12 06:22:42 PM PDT 24
Peak memory 215648 kb
Host smart-d377cd77-7eed-4c7b-8eff-44e47a5deddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250682583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.250682583
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.4189555404
Short name T836
Test name
Test status
Simulation time 72149955 ps
CPU time 1.56 seconds
Started Aug 12 06:22:58 PM PDT 24
Finished Aug 12 06:22:59 PM PDT 24
Peak memory 220628 kb
Host smart-92774a69-9d27-423b-8e71-cb9a55f9e7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189555404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.4189555404
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3647369244
Short name T718
Test name
Test status
Simulation time 45316478 ps
CPU time 0.93 seconds
Started Aug 12 06:22:52 PM PDT 24
Finished Aug 12 06:22:53 PM PDT 24
Peak memory 217780 kb
Host smart-cd97721e-82cf-45ed-824c-8a9a74b8f930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647369244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3647369244
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3087300259
Short name T974
Test name
Test status
Simulation time 68513882 ps
CPU time 0.99 seconds
Started Aug 12 06:22:52 PM PDT 24
Finished Aug 12 06:22:54 PM PDT 24
Peak memory 217756 kb
Host smart-449f353d-2ba8-4ca6-8d9c-fb285b9f9ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087300259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3087300259
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3635306997
Short name T569
Test name
Test status
Simulation time 48982935 ps
CPU time 1.48 seconds
Started Aug 12 06:22:41 PM PDT 24
Finished Aug 12 06:22:42 PM PDT 24
Peak memory 218900 kb
Host smart-dd1b1859-6965-4534-925d-6f0a29f0765a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635306997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3635306997
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3325829985
Short name T788
Test name
Test status
Simulation time 67179067 ps
CPU time 1.63 seconds
Started Aug 12 06:22:53 PM PDT 24
Finished Aug 12 06:22:54 PM PDT 24
Peak memory 220656 kb
Host smart-ae76ae5d-4e70-4028-a2b7-1c8fd985f478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325829985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3325829985
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1833558187
Short name T88
Test name
Test status
Simulation time 172721427 ps
CPU time 1.07 seconds
Started Aug 12 06:22:48 PM PDT 24
Finished Aug 12 06:22:49 PM PDT 24
Peak memory 217532 kb
Host smart-47328b2e-18bd-4cb2-9aac-362142f48ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833558187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1833558187
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.4098265152
Short name T196
Test name
Test status
Simulation time 114420492 ps
CPU time 1.27 seconds
Started Aug 12 06:21:14 PM PDT 24
Finished Aug 12 06:21:15 PM PDT 24
Peak memory 216048 kb
Host smart-d8bde4e2-9adf-4499-9606-f4f74bd51887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098265152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.4098265152
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.853922257
Short name T388
Test name
Test status
Simulation time 22639370 ps
CPU time 0.86 seconds
Started Aug 12 06:21:23 PM PDT 24
Finished Aug 12 06:21:24 PM PDT 24
Peak memory 207236 kb
Host smart-980e65f6-f6bd-418c-87f3-c39d402e651f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853922257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.853922257
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3462294685
Short name T179
Test name
Test status
Simulation time 11664989 ps
CPU time 0.9 seconds
Started Aug 12 06:21:21 PM PDT 24
Finished Aug 12 06:21:22 PM PDT 24
Peak memory 216944 kb
Host smart-45dd8b46-bdae-41ab-80c9-5a21670b00bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462294685 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3462294685
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1667838573
Short name T156
Test name
Test status
Simulation time 48057199 ps
CPU time 1.5 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 217532 kb
Host smart-a402cbd4-e3f8-4820-b5d4-24d2ddb96b9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667838573 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1667838573
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1615660376
Short name T173
Test name
Test status
Simulation time 18080434 ps
CPU time 1.16 seconds
Started Aug 12 06:21:14 PM PDT 24
Finished Aug 12 06:21:15 PM PDT 24
Peak memory 224472 kb
Host smart-9baae4f8-8104-4e8e-b3f7-8b4e83fec14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615660376 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1615660376
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.371936792
Short name T770
Test name
Test status
Simulation time 41278881 ps
CPU time 1.09 seconds
Started Aug 12 06:21:17 PM PDT 24
Finished Aug 12 06:21:18 PM PDT 24
Peak memory 218824 kb
Host smart-63cbc39a-fbcd-4267-a723-f507511d2163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371936792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.371936792
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1190076529
Short name T63
Test name
Test status
Simulation time 93883253 ps
CPU time 0.97 seconds
Started Aug 12 06:21:14 PM PDT 24
Finished Aug 12 06:21:15 PM PDT 24
Peak memory 224196 kb
Host smart-83ef5a65-cc54-4d74-a057-8aa6cba5904d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190076529 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1190076529
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3073072382
Short name T363
Test name
Test status
Simulation time 17208845 ps
CPU time 0.95 seconds
Started Aug 12 06:21:17 PM PDT 24
Finished Aug 12 06:21:18 PM PDT 24
Peak memory 215676 kb
Host smart-aafd8009-4c20-460f-ada6-3c8c2bf79d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073072382 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3073072382
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1553642362
Short name T726
Test name
Test status
Simulation time 2046296901 ps
CPU time 4.14 seconds
Started Aug 12 06:21:20 PM PDT 24
Finished Aug 12 06:21:24 PM PDT 24
Peak memory 217844 kb
Host smart-c7af8f0b-ad2b-4c67-8096-b86414d72cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553642362 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1553642362
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3651593440
Short name T236
Test name
Test status
Simulation time 2082134299 ps
CPU time 47.51 seconds
Started Aug 12 06:21:12 PM PDT 24
Finished Aug 12 06:22:00 PM PDT 24
Peak memory 217960 kb
Host smart-69a9a1b2-cb67-4cee-8839-59be981ef107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651593440 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3651593440
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.995013088
Short name T612
Test name
Test status
Simulation time 56198082 ps
CPU time 1.23 seconds
Started Aug 12 06:22:42 PM PDT 24
Finished Aug 12 06:22:44 PM PDT 24
Peak memory 217492 kb
Host smart-fc34dbfa-4011-45c0-a18d-319d426fa47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995013088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.995013088
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1133135392
Short name T605
Test name
Test status
Simulation time 90308542 ps
CPU time 1.11 seconds
Started Aug 12 06:22:57 PM PDT 24
Finished Aug 12 06:22:58 PM PDT 24
Peak memory 217876 kb
Host smart-09f8f5fb-0b0c-49dc-a0b9-97a1df8d0e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133135392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1133135392
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2741250982
Short name T50
Test name
Test status
Simulation time 91039641 ps
CPU time 1.29 seconds
Started Aug 12 06:23:04 PM PDT 24
Finished Aug 12 06:23:05 PM PDT 24
Peak memory 219312 kb
Host smart-952dd684-1c82-4493-ac7c-716d5838cf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741250982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2741250982
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1475479355
Short name T53
Test name
Test status
Simulation time 24684473 ps
CPU time 1.23 seconds
Started Aug 12 06:22:44 PM PDT 24
Finished Aug 12 06:22:45 PM PDT 24
Peak memory 219212 kb
Host smart-36b6fef6-66ab-4ac6-ad40-d240aaac7c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475479355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1475479355
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1994946461
Short name T339
Test name
Test status
Simulation time 128652155 ps
CPU time 3.1 seconds
Started Aug 12 06:22:59 PM PDT 24
Finished Aug 12 06:23:02 PM PDT 24
Peak memory 220740 kb
Host smart-6bd1b6a8-95c5-4b7a-8a83-aa831815c9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994946461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1994946461
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.470135183
Short name T372
Test name
Test status
Simulation time 57938954 ps
CPU time 0.98 seconds
Started Aug 12 06:22:51 PM PDT 24
Finished Aug 12 06:22:52 PM PDT 24
Peak memory 215752 kb
Host smart-b0bf6269-3042-4407-8f87-abb05bee38d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470135183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.470135183
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2899835984
Short name T337
Test name
Test status
Simulation time 42149955 ps
CPU time 1.22 seconds
Started Aug 12 06:22:56 PM PDT 24
Finished Aug 12 06:22:57 PM PDT 24
Peak memory 217664 kb
Host smart-6b388843-090c-4efd-bc7a-07b412efb20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899835984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2899835984
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3699956800
Short name T852
Test name
Test status
Simulation time 66646238 ps
CPU time 1.09 seconds
Started Aug 12 06:22:52 PM PDT 24
Finished Aug 12 06:22:53 PM PDT 24
Peak memory 219008 kb
Host smart-8bfcf87a-113e-4b2a-b681-c5dc42a6d7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699956800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3699956800
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1715678981
Short name T924
Test name
Test status
Simulation time 42557358 ps
CPU time 1.7 seconds
Started Aug 12 06:22:58 PM PDT 24
Finished Aug 12 06:23:00 PM PDT 24
Peak memory 220932 kb
Host smart-39fd0be3-760b-464b-9e4b-c9908f2e98d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715678981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1715678981
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2037859769
Short name T627
Test name
Test status
Simulation time 218536599 ps
CPU time 1.13 seconds
Started Aug 12 06:22:48 PM PDT 24
Finished Aug 12 06:22:49 PM PDT 24
Peak memory 217780 kb
Host smart-61a9cd2b-1d55-453a-a39f-b8ca1c567329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037859769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2037859769
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.140488934
Short name T268
Test name
Test status
Simulation time 96791441 ps
CPU time 1.21 seconds
Started Aug 12 06:21:14 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 219948 kb
Host smart-18d19427-9005-4a09-9e41-34407a190fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140488934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.140488934
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.414549415
Short name T697
Test name
Test status
Simulation time 35203095 ps
CPU time 0.83 seconds
Started Aug 12 06:21:14 PM PDT 24
Finished Aug 12 06:21:15 PM PDT 24
Peak memory 207240 kb
Host smart-3da7ff6f-8147-45fe-82a0-e26b567c149d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414549415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.414549415
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2417012050
Short name T54
Test name
Test status
Simulation time 19283438 ps
CPU time 0.92 seconds
Started Aug 12 06:21:14 PM PDT 24
Finished Aug 12 06:21:15 PM PDT 24
Peak memory 217016 kb
Host smart-e48f2239-2c96-4d52-97c8-d56c442981af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417012050 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2417012050
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1083393324
Short name T849
Test name
Test status
Simulation time 94855416 ps
CPU time 1.11 seconds
Started Aug 12 06:21:21 PM PDT 24
Finished Aug 12 06:21:22 PM PDT 24
Peak memory 217616 kb
Host smart-269a40ed-ed6d-45fa-b8ae-70c05bc48062
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083393324 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1083393324
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2078687651
Short name T489
Test name
Test status
Simulation time 27867800 ps
CPU time 1.08 seconds
Started Aug 12 06:21:20 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 220620 kb
Host smart-a96f22c5-7589-44f6-83dd-636f074928d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078687651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2078687651
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2791361333
Short name T48
Test name
Test status
Simulation time 76798573 ps
CPU time 1.57 seconds
Started Aug 12 06:21:15 PM PDT 24
Finished Aug 12 06:21:17 PM PDT 24
Peak memory 217780 kb
Host smart-12164782-e968-4353-8740-860a2f702128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791361333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2791361333
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.4242536150
Short name T468
Test name
Test status
Simulation time 21437401 ps
CPU time 1.24 seconds
Started Aug 12 06:21:14 PM PDT 24
Finished Aug 12 06:21:15 PM PDT 24
Peak memory 224404 kb
Host smart-acae6793-032e-4056-bac1-a5c76324a1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242536150 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.4242536150
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3709210548
Short name T244
Test name
Test status
Simulation time 39731417 ps
CPU time 0.86 seconds
Started Aug 12 06:21:21 PM PDT 24
Finished Aug 12 06:21:22 PM PDT 24
Peak memory 215684 kb
Host smart-dd20a358-5bf4-4805-b7aa-00e13f5aeda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709210548 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3709210548
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1009507833
Short name T809
Test name
Test status
Simulation time 511615161 ps
CPU time 5.42 seconds
Started Aug 12 06:21:20 PM PDT 24
Finished Aug 12 06:21:25 PM PDT 24
Peak memory 215660 kb
Host smart-5ce538d3-1fa6-4b8a-886d-a4b356caba71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009507833 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1009507833
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1771079103
Short name T241
Test name
Test status
Simulation time 5632774945 ps
CPU time 128.73 seconds
Started Aug 12 06:21:07 PM PDT 24
Finished Aug 12 06:23:16 PM PDT 24
Peak memory 217820 kb
Host smart-ec01f296-2daa-47a3-9800-c9b1f7e106bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771079103 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1771079103
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.292929253
Short name T965
Test name
Test status
Simulation time 29341774 ps
CPU time 1.27 seconds
Started Aug 12 06:22:46 PM PDT 24
Finished Aug 12 06:22:47 PM PDT 24
Peak memory 218784 kb
Host smart-a3255c67-e205-4fa2-a2c3-e71b3cca825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292929253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.292929253
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.51225901
Short name T771
Test name
Test status
Simulation time 122508288 ps
CPU time 1.34 seconds
Started Aug 12 06:22:44 PM PDT 24
Finished Aug 12 06:22:46 PM PDT 24
Peak memory 217700 kb
Host smart-a3cbfd0e-ad97-40bd-a42f-3f9c72edeedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51225901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.51225901
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.506926407
Short name T821
Test name
Test status
Simulation time 51468468 ps
CPU time 1.28 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:56 PM PDT 24
Peak memory 219256 kb
Host smart-06be4e6a-7333-4d30-a905-b90badb38e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506926407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.506926407
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3908089681
Short name T689
Test name
Test status
Simulation time 34189511 ps
CPU time 1.34 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:56 PM PDT 24
Peak memory 220300 kb
Host smart-4c9883b6-8b63-4ac9-af8b-9773a9c304a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908089681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3908089681
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2208761889
Short name T934
Test name
Test status
Simulation time 32734139 ps
CPU time 1.15 seconds
Started Aug 12 06:23:03 PM PDT 24
Finished Aug 12 06:23:04 PM PDT 24
Peak memory 219044 kb
Host smart-60a90ac1-e1af-4c63-841e-42100d9df326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208761889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2208761889
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.431753149
Short name T447
Test name
Test status
Simulation time 36619140 ps
CPU time 1.41 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:56 PM PDT 24
Peak memory 219056 kb
Host smart-03751171-1018-43f9-9823-da1a4b5837f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431753149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.431753149
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2341925177
Short name T828
Test name
Test status
Simulation time 99565786 ps
CPU time 1.31 seconds
Started Aug 12 06:23:07 PM PDT 24
Finished Aug 12 06:23:08 PM PDT 24
Peak memory 219264 kb
Host smart-d114c277-c038-4397-b2d4-e386b0bc430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341925177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2341925177
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1665958723
Short name T532
Test name
Test status
Simulation time 43932455 ps
CPU time 1.31 seconds
Started Aug 12 06:22:44 PM PDT 24
Finished Aug 12 06:22:46 PM PDT 24
Peak memory 217992 kb
Host smart-498ce14f-8418-4fbf-86be-fcc1ddde36ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665958723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1665958723
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1681894599
Short name T522
Test name
Test status
Simulation time 73873515 ps
CPU time 1.28 seconds
Started Aug 12 06:22:56 PM PDT 24
Finished Aug 12 06:22:58 PM PDT 24
Peak memory 219344 kb
Host smart-984dbc39-5b3e-4587-ba2f-d28728b98e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681894599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1681894599
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1867185044
Short name T597
Test name
Test status
Simulation time 51201713 ps
CPU time 1.18 seconds
Started Aug 12 06:21:16 PM PDT 24
Finished Aug 12 06:21:17 PM PDT 24
Peak memory 221348 kb
Host smart-49ddc9f6-0eed-4c62-942d-ace826650c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867185044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1867185044
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.801782982
Short name T368
Test name
Test status
Simulation time 37398184 ps
CPU time 1.24 seconds
Started Aug 12 06:21:17 PM PDT 24
Finished Aug 12 06:21:19 PM PDT 24
Peak memory 207320 kb
Host smart-a5ba6ed7-844b-4eb7-8cd5-f8dc95dd5c12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801782982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.801782982
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1044808624
Short name T52
Test name
Test status
Simulation time 18433607 ps
CPU time 0.9 seconds
Started Aug 12 06:21:16 PM PDT 24
Finished Aug 12 06:21:17 PM PDT 24
Peak memory 216896 kb
Host smart-a8cc8bd5-150c-4dd5-8ca0-f483fe17e048
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044808624 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1044808624
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.451242770
Short name T21
Test name
Test status
Simulation time 49059629 ps
CPU time 1.18 seconds
Started Aug 12 06:21:16 PM PDT 24
Finished Aug 12 06:21:17 PM PDT 24
Peak memory 219956 kb
Host smart-7143e64b-f009-4395-9343-c2116746fa38
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451242770 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.451242770
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1200633571
Short name T144
Test name
Test status
Simulation time 30304859 ps
CPU time 1.16 seconds
Started Aug 12 06:21:23 PM PDT 24
Finished Aug 12 06:21:25 PM PDT 24
Peak memory 230024 kb
Host smart-b738a1cf-d5f0-460e-aaad-08e39cfa14c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200633571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1200633571
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2770390984
Short name T740
Test name
Test status
Simulation time 102318502 ps
CPU time 1.26 seconds
Started Aug 12 06:21:13 PM PDT 24
Finished Aug 12 06:21:14 PM PDT 24
Peak memory 217788 kb
Host smart-39a88317-d6c0-464c-8f90-12deabd1e8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770390984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2770390984
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.192810350
Short name T719
Test name
Test status
Simulation time 34008996 ps
CPU time 0.99 seconds
Started Aug 12 06:21:13 PM PDT 24
Finished Aug 12 06:21:14 PM PDT 24
Peak memory 224168 kb
Host smart-a58c6501-605d-4c2e-a5bd-ae9bad2eac04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192810350 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.192810350
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3456555730
Short name T70
Test name
Test status
Simulation time 36800440 ps
CPU time 0.92 seconds
Started Aug 12 06:21:14 PM PDT 24
Finished Aug 12 06:21:15 PM PDT 24
Peak memory 215716 kb
Host smart-36a50263-966c-4415-b9fe-cda668e0a253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456555730 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3456555730
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2820564685
Short name T486
Test name
Test status
Simulation time 332630798 ps
CPU time 2.21 seconds
Started Aug 12 06:21:26 PM PDT 24
Finished Aug 12 06:21:29 PM PDT 24
Peak memory 215728 kb
Host smart-14a52e46-83a2-4de7-a7e0-683d784dec42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820564685 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2820564685
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/270.edn_genbits.3643298340
Short name T587
Test name
Test status
Simulation time 64003591 ps
CPU time 1.04 seconds
Started Aug 12 06:23:02 PM PDT 24
Finished Aug 12 06:23:03 PM PDT 24
Peak memory 217724 kb
Host smart-3875dc2d-b48e-43aa-bd53-2a0bf198bb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643298340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3643298340
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.291375553
Short name T734
Test name
Test status
Simulation time 66253147 ps
CPU time 1.24 seconds
Started Aug 12 06:22:59 PM PDT 24
Finished Aug 12 06:23:00 PM PDT 24
Peak memory 217656 kb
Host smart-c317e36c-1d47-4ded-91fa-cd186c9a40af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291375553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.291375553
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2260183383
Short name T917
Test name
Test status
Simulation time 49647460 ps
CPU time 1.26 seconds
Started Aug 12 06:22:35 PM PDT 24
Finished Aug 12 06:22:36 PM PDT 24
Peak memory 218876 kb
Host smart-43bbdf58-a9fb-4909-98f9-88674e978d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260183383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2260183383
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2607942435
Short name T638
Test name
Test status
Simulation time 113580631 ps
CPU time 1.28 seconds
Started Aug 12 06:22:41 PM PDT 24
Finished Aug 12 06:22:42 PM PDT 24
Peak memory 219332 kb
Host smart-ee2982ff-22c9-4adf-ba1f-bd5175939e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607942435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2607942435
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3198084269
Short name T904
Test name
Test status
Simulation time 38562980 ps
CPU time 1.39 seconds
Started Aug 12 06:22:53 PM PDT 24
Finished Aug 12 06:22:54 PM PDT 24
Peak memory 215672 kb
Host smart-1064f696-cd73-41cc-80ee-203c61960036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198084269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3198084269
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3129859411
Short name T252
Test name
Test status
Simulation time 266908152 ps
CPU time 3.74 seconds
Started Aug 12 06:22:51 PM PDT 24
Finished Aug 12 06:23:00 PM PDT 24
Peak memory 219148 kb
Host smart-f045b37a-cead-4d88-861b-aec86a57831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129859411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3129859411
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.508353835
Short name T593
Test name
Test status
Simulation time 111771997 ps
CPU time 1.18 seconds
Started Aug 12 06:22:52 PM PDT 24
Finished Aug 12 06:22:54 PM PDT 24
Peak memory 217792 kb
Host smart-68f5e89c-5846-470d-846e-29c6022b0c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508353835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.508353835
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1960274703
Short name T679
Test name
Test status
Simulation time 80603258 ps
CPU time 2.87 seconds
Started Aug 12 06:22:48 PM PDT 24
Finished Aug 12 06:22:51 PM PDT 24
Peak memory 220576 kb
Host smart-c29bac47-dd78-4482-8186-f53b5ccba5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960274703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1960274703
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2425606645
Short name T613
Test name
Test status
Simulation time 37632900 ps
CPU time 1.35 seconds
Started Aug 12 06:22:56 PM PDT 24
Finished Aug 12 06:22:58 PM PDT 24
Peak memory 218880 kb
Host smart-9c4c8fc2-7ff7-4bb6-b692-fbbfbfd4ab5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425606645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2425606645
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1088691107
Short name T396
Test name
Test status
Simulation time 35419048 ps
CPU time 1.09 seconds
Started Aug 12 06:23:04 PM PDT 24
Finished Aug 12 06:23:05 PM PDT 24
Peak memory 220484 kb
Host smart-76114245-0bc3-4ed2-b8c3-d9e08e012f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088691107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1088691107
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3514949203
Short name T300
Test name
Test status
Simulation time 29447349 ps
CPU time 1.3 seconds
Started Aug 12 06:21:24 PM PDT 24
Finished Aug 12 06:21:25 PM PDT 24
Peak memory 219828 kb
Host smart-508b7556-90db-441d-96a6-9f39292223f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514949203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3514949203
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2387598435
Short name T646
Test name
Test status
Simulation time 23195926 ps
CPU time 0.99 seconds
Started Aug 12 06:21:12 PM PDT 24
Finished Aug 12 06:21:14 PM PDT 24
Peak memory 207272 kb
Host smart-3312e1d7-1277-418f-9854-40de386fb5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387598435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2387598435
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.4164033394
Short name T601
Test name
Test status
Simulation time 17949703 ps
CPU time 0.85 seconds
Started Aug 12 06:21:22 PM PDT 24
Finished Aug 12 06:21:23 PM PDT 24
Peak memory 216940 kb
Host smart-56459ff2-611c-4517-82a6-0c4527a5dbfc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164033394 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4164033394
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.679814451
Short name T160
Test name
Test status
Simulation time 45581460 ps
CPU time 1.05 seconds
Started Aug 12 06:21:17 PM PDT 24
Finished Aug 12 06:21:18 PM PDT 24
Peak memory 219896 kb
Host smart-588c88d3-8f4e-4ca2-8444-2009ecad4fa1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679814451 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.679814451
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1275011078
Short name T126
Test name
Test status
Simulation time 24535704 ps
CPU time 1.01 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 220412 kb
Host smart-6e82151b-73dc-492b-90f8-f07251c1a19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275011078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1275011078
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.4082868928
Short name T694
Test name
Test status
Simulation time 103658232 ps
CPU time 1.18 seconds
Started Aug 12 06:21:21 PM PDT 24
Finished Aug 12 06:21:22 PM PDT 24
Peak memory 219064 kb
Host smart-c8d4db74-95ae-4418-aa3b-408c4a5570af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082868928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4082868928
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1873420502
Short name T35
Test name
Test status
Simulation time 20787393 ps
CPU time 1.1 seconds
Started Aug 12 06:21:23 PM PDT 24
Finished Aug 12 06:21:24 PM PDT 24
Peak memory 216460 kb
Host smart-f247b940-82e2-4f8b-b500-b93c5b0489d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873420502 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1873420502
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3749706906
Short name T45
Test name
Test status
Simulation time 25821698 ps
CPU time 0.95 seconds
Started Aug 12 06:21:23 PM PDT 24
Finished Aug 12 06:21:25 PM PDT 24
Peak memory 215668 kb
Host smart-2f1e3a6e-7ed7-45e7-9a08-4610282f8b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749706906 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3749706906
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3677088172
Short name T977
Test name
Test status
Simulation time 324610948 ps
CPU time 3.16 seconds
Started Aug 12 06:21:17 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 217860 kb
Host smart-b75d41b4-83d7-4a2e-bfdc-319a003bea48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677088172 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3677088172
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/280.edn_genbits.3167217558
Short name T764
Test name
Test status
Simulation time 32279578 ps
CPU time 1.24 seconds
Started Aug 12 06:22:50 PM PDT 24
Finished Aug 12 06:22:51 PM PDT 24
Peak memory 220440 kb
Host smart-68a94ccf-80cf-4286-984c-c7ce7962d36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167217558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3167217558
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2206494079
Short name T455
Test name
Test status
Simulation time 86354082 ps
CPU time 1.57 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 218980 kb
Host smart-3ecd3fea-1317-471e-b8e5-faa7bf72b2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206494079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2206494079
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.852576255
Short name T815
Test name
Test status
Simulation time 51477895 ps
CPU time 1.18 seconds
Started Aug 12 06:22:57 PM PDT 24
Finished Aug 12 06:22:59 PM PDT 24
Peak memory 217616 kb
Host smart-19806e65-91a1-4777-8057-d40607016a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852576255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.852576255
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.386211661
Short name T823
Test name
Test status
Simulation time 44648699 ps
CPU time 1.4 seconds
Started Aug 12 06:23:06 PM PDT 24
Finished Aug 12 06:23:07 PM PDT 24
Peak memory 218916 kb
Host smart-7202ce57-58c8-4495-804d-6e0c541ba6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386211661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.386211661
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2704617646
Short name T800
Test name
Test status
Simulation time 65718478 ps
CPU time 1.14 seconds
Started Aug 12 06:22:50 PM PDT 24
Finished Aug 12 06:22:52 PM PDT 24
Peak memory 219384 kb
Host smart-7a964c57-b1ce-4167-902e-2a3bbf043219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704617646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2704617646
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2020627333
Short name T304
Test name
Test status
Simulation time 29385284 ps
CPU time 1.36 seconds
Started Aug 12 06:23:09 PM PDT 24
Finished Aug 12 06:23:10 PM PDT 24
Peak memory 218948 kb
Host smart-5179bf71-6136-4086-9978-06ee6dfe9177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020627333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2020627333
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2935022952
Short name T879
Test name
Test status
Simulation time 42295537 ps
CPU time 1.71 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:56 PM PDT 24
Peak memory 220416 kb
Host smart-75acba05-348e-409b-abf9-e6e9bdc0a33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935022952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2935022952
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3311555162
Short name T865
Test name
Test status
Simulation time 40043775 ps
CPU time 1.42 seconds
Started Aug 12 06:23:07 PM PDT 24
Finished Aug 12 06:23:09 PM PDT 24
Peak memory 219144 kb
Host smart-970046a0-31cb-4958-8bd4-d03773bd75c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311555162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3311555162
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1207549259
Short name T505
Test name
Test status
Simulation time 81226120 ps
CPU time 2.63 seconds
Started Aug 12 06:23:08 PM PDT 24
Finished Aug 12 06:23:11 PM PDT 24
Peak memory 220512 kb
Host smart-09bfc46c-31e4-480e-be61-b6bba4a450ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207549259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1207549259
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1755466332
Short name T146
Test name
Test status
Simulation time 44770859 ps
CPU time 1.13 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 219160 kb
Host smart-119fef63-145b-4a70-90e6-6c6baa6c4c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755466332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1755466332
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2124272529
Short name T407
Test name
Test status
Simulation time 42557748 ps
CPU time 0.83 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 207052 kb
Host smart-66ebccf3-3e12-4ad7-afb4-cbb310b53f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124272529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2124272529
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.493948322
Short name T585
Test name
Test status
Simulation time 17903991 ps
CPU time 0.86 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 216612 kb
Host smart-850cf740-7126-4d64-91e8-0767e92ac845
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493948322 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.493948322
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3758630032
Short name T783
Test name
Test status
Simulation time 206341823 ps
CPU time 1.03 seconds
Started Aug 12 06:21:18 PM PDT 24
Finished Aug 12 06:21:19 PM PDT 24
Peak memory 218852 kb
Host smart-6ac26344-cec9-4f3b-b175-b683314dd621
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758630032 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3758630032
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1617116858
Short name T466
Test name
Test status
Simulation time 43782523 ps
CPU time 0.89 seconds
Started Aug 12 06:21:26 PM PDT 24
Finished Aug 12 06:21:27 PM PDT 24
Peak memory 220016 kb
Host smart-93a8a44e-f7b9-4f86-96bb-4469e569a170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617116858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1617116858
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3648737575
Short name T893
Test name
Test status
Simulation time 33124748 ps
CPU time 1.38 seconds
Started Aug 12 06:21:11 PM PDT 24
Finished Aug 12 06:21:13 PM PDT 24
Peak memory 218836 kb
Host smart-05a2982e-05fd-4b5a-8bc5-d72f129410aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648737575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3648737575
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.4141106991
Short name T801
Test name
Test status
Simulation time 38034855 ps
CPU time 1.01 seconds
Started Aug 12 06:21:18 PM PDT 24
Finished Aug 12 06:21:19 PM PDT 24
Peak memory 224380 kb
Host smart-26b0da05-b1b9-4d69-a61a-87a85b418ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141106991 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4141106991
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3753379684
Short name T816
Test name
Test status
Simulation time 35454384 ps
CPU time 0.83 seconds
Started Aug 12 06:21:07 PM PDT 24
Finished Aug 12 06:21:08 PM PDT 24
Peak memory 215472 kb
Host smart-7367f63e-c1b4-4fa9-a508-4f1dd56f80b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753379684 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3753379684
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2814826342
Short name T699
Test name
Test status
Simulation time 234998158 ps
CPU time 2.99 seconds
Started Aug 12 06:21:14 PM PDT 24
Finished Aug 12 06:21:17 PM PDT 24
Peak memory 220276 kb
Host smart-908c1242-43a4-40d2-a7ad-19a446a92d6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814826342 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2814826342
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2380275115
Short name T231
Test name
Test status
Simulation time 19999803768 ps
CPU time 42.34 seconds
Started Aug 12 06:21:18 PM PDT 24
Finished Aug 12 06:22:01 PM PDT 24
Peak memory 218728 kb
Host smart-412754c9-d90f-4e46-a6bd-4369b7cf9c05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380275115 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2380275115
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1072062170
Short name T949
Test name
Test status
Simulation time 87485763 ps
CPU time 1.38 seconds
Started Aug 12 06:23:00 PM PDT 24
Finished Aug 12 06:23:02 PM PDT 24
Peak memory 218760 kb
Host smart-03bd7a68-8f30-4440-83e5-e920c2311ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072062170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1072062170
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2598870234
Short name T875
Test name
Test status
Simulation time 48818932 ps
CPU time 1.22 seconds
Started Aug 12 06:23:07 PM PDT 24
Finished Aug 12 06:23:08 PM PDT 24
Peak memory 217772 kb
Host smart-c2499ef6-7e70-4a2c-9415-6aeddb2ddbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598870234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2598870234
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1475491889
Short name T637
Test name
Test status
Simulation time 263627033 ps
CPU time 2.71 seconds
Started Aug 12 06:23:00 PM PDT 24
Finished Aug 12 06:23:03 PM PDT 24
Peak memory 220648 kb
Host smart-4846738b-47bf-47df-bae7-c8e2d33901e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475491889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1475491889
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.792422041
Short name T898
Test name
Test status
Simulation time 190259148 ps
CPU time 1.06 seconds
Started Aug 12 06:23:00 PM PDT 24
Finished Aug 12 06:23:01 PM PDT 24
Peak memory 219864 kb
Host smart-4ab25950-d253-4e21-be6b-ff99d5e4f110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792422041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.792422041
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1657762659
Short name T330
Test name
Test status
Simulation time 96620788 ps
CPU time 1.27 seconds
Started Aug 12 06:22:58 PM PDT 24
Finished Aug 12 06:23:00 PM PDT 24
Peak memory 217932 kb
Host smart-42376bfb-24f9-4a15-998a-1e69dcb5923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657762659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1657762659
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2575866850
Short name T947
Test name
Test status
Simulation time 203610424 ps
CPU time 2.12 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:56 PM PDT 24
Peak memory 220512 kb
Host smart-489cda71-82a8-4406-97e8-54b4e8185720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575866850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2575866850
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1757714725
Short name T651
Test name
Test status
Simulation time 52077037 ps
CPU time 1.36 seconds
Started Aug 12 06:23:07 PM PDT 24
Finished Aug 12 06:23:08 PM PDT 24
Peak memory 219276 kb
Host smart-cfec6d18-39fc-427d-b93a-68662db2eb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757714725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1757714725
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1850204127
Short name T632
Test name
Test status
Simulation time 71368660 ps
CPU time 1.63 seconds
Started Aug 12 06:22:54 PM PDT 24
Finished Aug 12 06:22:56 PM PDT 24
Peak memory 219188 kb
Host smart-3cf66528-7f4e-4996-8a32-48242943fc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850204127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1850204127
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3778774926
Short name T462
Test name
Test status
Simulation time 38959952 ps
CPU time 1.42 seconds
Started Aug 12 06:22:57 PM PDT 24
Finished Aug 12 06:22:59 PM PDT 24
Peak memory 219104 kb
Host smart-b0932e36-6a15-41f9-83dd-36fd09bf3329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778774926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3778774926
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.957509139
Short name T444
Test name
Test status
Simulation time 106378151 ps
CPU time 1.06 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:36 PM PDT 24
Peak memory 218848 kb
Host smart-6e41c0b5-4519-429a-9ed7-6ffb76303616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957509139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.957509139
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3366614642
Short name T25
Test name
Test status
Simulation time 45670471 ps
CPU time 0.99 seconds
Started Aug 12 06:20:42 PM PDT 24
Finished Aug 12 06:20:43 PM PDT 24
Peak memory 215692 kb
Host smart-94c754a7-e0f8-4e65-93f8-fa08e59be7c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366614642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3366614642
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2791017557
Short name T691
Test name
Test status
Simulation time 70083788 ps
CPU time 1.34 seconds
Started Aug 12 06:20:49 PM PDT 24
Finished Aug 12 06:20:55 PM PDT 24
Peak memory 217756 kb
Host smart-a5fed62b-ba8a-4720-80d3-5ea0c9f655fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791017557 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2791017557
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2779368238
Short name T6
Test name
Test status
Simulation time 21449898 ps
CPU time 1 seconds
Started Aug 12 06:20:41 PM PDT 24
Finished Aug 12 06:20:42 PM PDT 24
Peak memory 219320 kb
Host smart-9be17e69-ebf0-40ea-af3b-c45658eb7b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779368238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2779368238
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1480523741
Short name T701
Test name
Test status
Simulation time 67335950 ps
CPU time 1.66 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:37 PM PDT 24
Peak memory 216928 kb
Host smart-f9e9f954-44c9-443d-9f62-b91390fb019a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480523741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1480523741
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.741483526
Short name T737
Test name
Test status
Simulation time 53982943 ps
CPU time 0.86 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:36 PM PDT 24
Peak memory 215652 kb
Host smart-c9e45211-0bb2-43c5-853b-4ef3bd648552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741483526 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.741483526
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.4124615344
Short name T313
Test name
Test status
Simulation time 28518027 ps
CPU time 0.93 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:36 PM PDT 24
Peak memory 207468 kb
Host smart-74a0fb94-e012-41ad-b8d6-7a7f75c03410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124615344 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4124615344
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2586880278
Short name T19
Test name
Test status
Simulation time 1711460800 ps
CPU time 7.84 seconds
Started Aug 12 06:20:42 PM PDT 24
Finished Aug 12 06:20:50 PM PDT 24
Peak memory 241136 kb
Host smart-2c494379-6dbd-4ff2-8690-c954f9a8bfee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586880278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2586880278
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1275279619
Short name T426
Test name
Test status
Simulation time 33425604 ps
CPU time 1.04 seconds
Started Aug 12 06:20:39 PM PDT 24
Finished Aug 12 06:20:40 PM PDT 24
Peak memory 215652 kb
Host smart-8a074ece-b795-4c31-af0f-e7f72b3d1a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275279619 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1275279619
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3269298125
Short name T75
Test name
Test status
Simulation time 461743275 ps
CPU time 2.87 seconds
Started Aug 12 06:20:35 PM PDT 24
Finished Aug 12 06:20:38 PM PDT 24
Peak memory 215640 kb
Host smart-d2f4550f-c16a-4220-b2f7-47761e7790f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269298125 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3269298125
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1461213871
Short name T240
Test name
Test status
Simulation time 3420227669 ps
CPU time 84.26 seconds
Started Aug 12 06:20:37 PM PDT 24
Finished Aug 12 06:22:02 PM PDT 24
Peak memory 218176 kb
Host smart-53d7f769-2727-4f77-b685-be589bf840e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461213871 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1461213871
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1912262116
Short name T782
Test name
Test status
Simulation time 50725022 ps
CPU time 1.2 seconds
Started Aug 12 06:21:25 PM PDT 24
Finished Aug 12 06:21:27 PM PDT 24
Peak memory 220164 kb
Host smart-8a230834-8dcf-408e-93e0-4c5a4ef45828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912262116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1912262116
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1288128237
Short name T639
Test name
Test status
Simulation time 23280571 ps
CPU time 0.96 seconds
Started Aug 12 06:21:30 PM PDT 24
Finished Aug 12 06:21:31 PM PDT 24
Peak memory 207268 kb
Host smart-485a033f-b05f-4622-9194-46f011e973b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288128237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1288128237
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.554722954
Short name T873
Test name
Test status
Simulation time 22550874 ps
CPU time 0.87 seconds
Started Aug 12 06:21:41 PM PDT 24
Finished Aug 12 06:21:42 PM PDT 24
Peak memory 216588 kb
Host smart-ec34c4fb-b922-4cef-9e34-2d03888bc473
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554722954 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.554722954
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1866789979
Short name T133
Test name
Test status
Simulation time 126588639 ps
CPU time 1.23 seconds
Started Aug 12 06:21:23 PM PDT 24
Finished Aug 12 06:21:24 PM PDT 24
Peak memory 217512 kb
Host smart-bf8090c1-f941-4b90-ad06-9b828af423a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866789979 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1866789979
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1331757548
Short name T590
Test name
Test status
Simulation time 37571553 ps
CPU time 0.85 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 218844 kb
Host smart-26121082-45b2-4428-a1c7-d14186dab61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331757548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1331757548
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3281482227
Short name T748
Test name
Test status
Simulation time 107463341 ps
CPU time 1.2 seconds
Started Aug 12 06:21:18 PM PDT 24
Finished Aug 12 06:21:19 PM PDT 24
Peak memory 217836 kb
Host smart-197ceb64-edf6-43e2-8b18-f2493047bca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281482227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3281482227
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1451488291
Short name T871
Test name
Test status
Simulation time 40360987 ps
CPU time 0.98 seconds
Started Aug 12 06:21:24 PM PDT 24
Finished Aug 12 06:21:25 PM PDT 24
Peak memory 224220 kb
Host smart-9302be10-7b80-427c-b41d-34f575cf86ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451488291 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1451488291
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3058019551
Short name T833
Test name
Test status
Simulation time 48375729 ps
CPU time 0.94 seconds
Started Aug 12 06:21:25 PM PDT 24
Finished Aug 12 06:21:27 PM PDT 24
Peak memory 215620 kb
Host smart-973c8991-978a-4caa-b558-9fb95e7019c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058019551 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3058019551
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3060974387
Short name T251
Test name
Test status
Simulation time 606900458 ps
CPU time 3.42 seconds
Started Aug 12 06:21:23 PM PDT 24
Finished Aug 12 06:21:26 PM PDT 24
Peak memory 217608 kb
Host smart-03dd3f96-7a2f-49bf-90a1-8d48e378ad68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060974387 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3060974387
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2477899678
Short name T239
Test name
Test status
Simulation time 12901937472 ps
CPU time 67.26 seconds
Started Aug 12 06:21:25 PM PDT 24
Finished Aug 12 06:22:32 PM PDT 24
Peak memory 217696 kb
Host smart-1760d8e5-2187-407d-8c84-74f10c084a7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477899678 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2477899678
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2322603350
Short name T183
Test name
Test status
Simulation time 39719279 ps
CPU time 1.1 seconds
Started Aug 12 06:21:27 PM PDT 24
Finished Aug 12 06:21:28 PM PDT 24
Peak memory 218728 kb
Host smart-d51aa045-6743-4e7b-ba8c-e2411f4d8f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322603350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2322603350
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.4239117999
Short name T663
Test name
Test status
Simulation time 15040892 ps
CPU time 0.92 seconds
Started Aug 12 06:21:26 PM PDT 24
Finished Aug 12 06:21:27 PM PDT 24
Peak memory 215656 kb
Host smart-25d2365b-1815-4a25-bc52-20edc9f2d8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239117999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.4239117999
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3095131686
Short name T634
Test name
Test status
Simulation time 37974330 ps
CPU time 0.87 seconds
Started Aug 12 06:21:37 PM PDT 24
Finished Aug 12 06:21:38 PM PDT 24
Peak memory 216960 kb
Host smart-5ed4c68e-41e3-4d8f-b276-3c4312253ec4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095131686 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3095131686
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.40346270
Short name T23
Test name
Test status
Simulation time 36241283 ps
CPU time 1.33 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 220208 kb
Host smart-1fca3251-6a78-4389-b717-74e1e14cba82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40346270 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_dis
able_auto_req_mode.40346270
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1464192487
Short name T163
Test name
Test status
Simulation time 113145077 ps
CPU time 1.14 seconds
Started Aug 12 06:21:20 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 225996 kb
Host smart-05b917b1-57dc-44b6-bc9e-fce3ba4e6c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464192487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1464192487
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3467782949
Short name T625
Test name
Test status
Simulation time 54240140 ps
CPU time 1.38 seconds
Started Aug 12 06:21:17 PM PDT 24
Finished Aug 12 06:21:18 PM PDT 24
Peak memory 219228 kb
Host smart-61606507-f906-43c3-82ca-92f3d10c1c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467782949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3467782949
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3427826720
Short name T709
Test name
Test status
Simulation time 25265289 ps
CPU time 0.97 seconds
Started Aug 12 06:21:39 PM PDT 24
Finished Aug 12 06:21:40 PM PDT 24
Peak memory 215936 kb
Host smart-c718aa9d-6b5c-4a6c-929d-78babb88cc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427826720 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3427826720
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1668854331
Short name T909
Test name
Test status
Simulation time 15104132 ps
CPU time 0.94 seconds
Started Aug 12 06:21:26 PM PDT 24
Finished Aug 12 06:21:27 PM PDT 24
Peak memory 215640 kb
Host smart-9a6f609f-28dc-4f4e-aad5-f58c8a39f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668854331 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1668854331
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.257223200
Short name T926
Test name
Test status
Simulation time 752859436 ps
CPU time 5.45 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:25 PM PDT 24
Peak memory 215888 kb
Host smart-27ce44fe-943f-4198-b42e-9b3522ee1a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257223200 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.257223200
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2451455177
Short name T112
Test name
Test status
Simulation time 12380413224 ps
CPU time 41.97 seconds
Started Aug 12 06:21:26 PM PDT 24
Finished Aug 12 06:22:08 PM PDT 24
Peak memory 217476 kb
Host smart-7060b3d0-d867-41b5-a749-21dcfa309a48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451455177 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2451455177
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3946450273
Short name T731
Test name
Test status
Simulation time 206432099 ps
CPU time 1.12 seconds
Started Aug 12 06:21:27 PM PDT 24
Finished Aug 12 06:21:29 PM PDT 24
Peak memory 220192 kb
Host smart-7f710814-a3f3-406b-ae09-b6ce7fc00efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946450273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3946450273
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.4268756322
Short name T520
Test name
Test status
Simulation time 16198919 ps
CPU time 0.9 seconds
Started Aug 12 06:21:30 PM PDT 24
Finished Aug 12 06:21:31 PM PDT 24
Peak memory 207264 kb
Host smart-ae580566-3721-414c-9bce-f0b60efcba93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268756322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.4268756322
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3449510398
Short name T178
Test name
Test status
Simulation time 13750572 ps
CPU time 0.9 seconds
Started Aug 12 06:21:28 PM PDT 24
Finished Aug 12 06:21:30 PM PDT 24
Peak memory 216940 kb
Host smart-81b839de-180d-4dc4-9582-32da36afcb48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449510398 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3449510398
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_genbits.3838828679
Short name T845
Test name
Test status
Simulation time 447826225 ps
CPU time 1.25 seconds
Started Aug 12 06:21:25 PM PDT 24
Finished Aug 12 06:21:26 PM PDT 24
Peak memory 217568 kb
Host smart-f0ae04c4-345f-4d72-882e-88230e77c3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838828679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3838828679
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1912179075
Short name T755
Test name
Test status
Simulation time 37794645 ps
CPU time 0.93 seconds
Started Aug 12 06:21:22 PM PDT 24
Finished Aug 12 06:21:23 PM PDT 24
Peak memory 215764 kb
Host smart-b484e93f-2754-4d3d-b17e-e241f810b8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912179075 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1912179075
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.4124386081
Short name T73
Test name
Test status
Simulation time 16722805 ps
CPU time 0.96 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:47 PM PDT 24
Peak memory 215664 kb
Host smart-74b946ed-2402-4288-b25f-65bc31c6843b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124386081 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.4124386081
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.592047100
Short name T682
Test name
Test status
Simulation time 245546880 ps
CPU time 2.93 seconds
Started Aug 12 06:21:18 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 215760 kb
Host smart-a9cafc49-a8b6-4056-a011-010ca6e4f714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592047100 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.592047100
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3761293338
Short name T611
Test name
Test status
Simulation time 3075728314 ps
CPU time 70.25 seconds
Started Aug 12 06:21:27 PM PDT 24
Finished Aug 12 06:22:37 PM PDT 24
Peak memory 218788 kb
Host smart-bc2502a4-d755-45b8-86ae-3004aca1d591
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761293338 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3761293338
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2390219760
Short name T876
Test name
Test status
Simulation time 149019575 ps
CPU time 1.22 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 219388 kb
Host smart-11a3a4cd-245b-427d-8f26-88b791d03710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390219760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2390219760
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2030031418
Short name T356
Test name
Test status
Simulation time 15960231 ps
CPU time 0.96 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 207232 kb
Host smart-abbbf322-3c51-4b4d-8249-8ce26cc10cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030031418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2030031418
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.607881597
Short name T665
Test name
Test status
Simulation time 13444146 ps
CPU time 0.91 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 217152 kb
Host smart-c7ece1ff-6f73-4e91-a157-a4f6278fef47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607881597 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.607881597
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2903196948
Short name T128
Test name
Test status
Simulation time 34277793 ps
CPU time 1.22 seconds
Started Aug 12 06:21:20 PM PDT 24
Finished Aug 12 06:21:21 PM PDT 24
Peak memory 217668 kb
Host smart-5375a7c3-db61-43c1-89a0-d9ce8a845621
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903196948 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2903196948
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1741323611
Short name T923
Test name
Test status
Simulation time 35042129 ps
CPU time 1.04 seconds
Started Aug 12 06:21:34 PM PDT 24
Finished Aug 12 06:21:35 PM PDT 24
Peak memory 218988 kb
Host smart-cb11370c-49b0-44de-9a52-ec3292b514c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741323611 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1741323611
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3643096782
Short name T540
Test name
Test status
Simulation time 69345820 ps
CPU time 1.22 seconds
Started Aug 12 06:21:24 PM PDT 24
Finished Aug 12 06:21:25 PM PDT 24
Peak memory 220064 kb
Host smart-117ea985-3fdf-426a-9fa2-3f7ae1f9b70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643096782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3643096782
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2017442353
Short name T501
Test name
Test status
Simulation time 21492069 ps
CPU time 1.09 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 215820 kb
Host smart-4de38a0b-462a-4375-9656-6aa74aa41c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017442353 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2017442353
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.4103008004
Short name T901
Test name
Test status
Simulation time 51762789 ps
CPU time 0.9 seconds
Started Aug 12 06:21:25 PM PDT 24
Finished Aug 12 06:21:26 PM PDT 24
Peak memory 215652 kb
Host smart-c82b1228-074a-41eb-9f22-50724b442a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103008004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.4103008004
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3550617459
Short name T781
Test name
Test status
Simulation time 380661445 ps
CPU time 4.29 seconds
Started Aug 12 06:21:22 PM PDT 24
Finished Aug 12 06:21:27 PM PDT 24
Peak memory 215728 kb
Host smart-2b9d260f-0157-4493-ba68-4248cf959209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550617459 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3550617459
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.2348831131
Short name T294
Test name
Test status
Simulation time 47438515 ps
CPU time 1.26 seconds
Started Aug 12 06:21:27 PM PDT 24
Finished Aug 12 06:21:28 PM PDT 24
Peak memory 219164 kb
Host smart-4f30ddc8-0901-411c-8fbb-ffadd917663d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348831131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2348831131
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.215276512
Short name T757
Test name
Test status
Simulation time 17044661 ps
CPU time 0.94 seconds
Started Aug 12 06:21:24 PM PDT 24
Finished Aug 12 06:21:25 PM PDT 24
Peak memory 215636 kb
Host smart-5eb41f6f-1df2-4566-b7e7-92625eabe42c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215276512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.215276512
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3396155649
Short name T869
Test name
Test status
Simulation time 28750706 ps
CPU time 0.95 seconds
Started Aug 12 06:21:36 PM PDT 24
Finished Aug 12 06:21:38 PM PDT 24
Peak memory 207620 kb
Host smart-a547c939-80a1-4076-89a4-ac3e99072099
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396155649 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3396155649
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1506397489
Short name T158
Test name
Test status
Simulation time 39331427 ps
CPU time 1.29 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:21:20 PM PDT 24
Peak memory 217716 kb
Host smart-2b60d307-e3c1-48a9-bc90-f8e6cbf7455d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506397489 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1506397489
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.248142296
Short name T908
Test name
Test status
Simulation time 30092467 ps
CPU time 0.87 seconds
Started Aug 12 06:21:31 PM PDT 24
Finished Aug 12 06:21:32 PM PDT 24
Peak memory 219144 kb
Host smart-e86c7d6b-ce87-4654-8990-36e65436a021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248142296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.248142296
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3654357761
Short name T790
Test name
Test status
Simulation time 57726973 ps
CPU time 1.2 seconds
Started Aug 12 06:21:27 PM PDT 24
Finished Aug 12 06:21:29 PM PDT 24
Peak memory 218804 kb
Host smart-5be1be32-6b86-47b3-be2f-0bc6d109347f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654357761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3654357761
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.300562476
Short name T700
Test name
Test status
Simulation time 36957437 ps
CPU time 0.91 seconds
Started Aug 12 06:21:31 PM PDT 24
Finished Aug 12 06:21:32 PM PDT 24
Peak memory 215936 kb
Host smart-407df85e-38e2-4a08-a526-64e30bdfb85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300562476 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.300562476
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1381154874
Short name T442
Test name
Test status
Simulation time 21928022 ps
CPU time 1 seconds
Started Aug 12 06:21:41 PM PDT 24
Finished Aug 12 06:21:42 PM PDT 24
Peak memory 215664 kb
Host smart-ddcf2597-cef1-4940-be91-a53b3c8bee5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381154874 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1381154874
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4223070239
Short name T773
Test name
Test status
Simulation time 147934458 ps
CPU time 1.2 seconds
Started Aug 12 06:21:37 PM PDT 24
Finished Aug 12 06:21:39 PM PDT 24
Peak memory 217756 kb
Host smart-76c62ad5-073d-41d9-a4a1-7ebb4a7a0661
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223070239 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4223070239
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.4066916485
Short name T724
Test name
Test status
Simulation time 5227962771 ps
CPU time 138.48 seconds
Started Aug 12 06:21:34 PM PDT 24
Finished Aug 12 06:23:52 PM PDT 24
Peak memory 218728 kb
Host smart-d7f544ae-ef79-426a-84d0-3dfcb6af6c70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066916485 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.4066916485
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.369612564
Short name T512
Test name
Test status
Simulation time 80935921 ps
CPU time 1.16 seconds
Started Aug 12 06:21:27 PM PDT 24
Finished Aug 12 06:21:29 PM PDT 24
Peak memory 219000 kb
Host smart-ee70638b-d342-415a-b2ec-bbe8979deecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369612564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.369612564
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1177929990
Short name T542
Test name
Test status
Simulation time 17480906 ps
CPU time 1 seconds
Started Aug 12 06:21:26 PM PDT 24
Finished Aug 12 06:21:27 PM PDT 24
Peak memory 215640 kb
Host smart-cd5a4bb1-0554-426e-b612-b6e96b9cdc0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177929990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1177929990
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1966863590
Short name T165
Test name
Test status
Simulation time 88695939 ps
CPU time 0.83 seconds
Started Aug 12 06:21:34 PM PDT 24
Finished Aug 12 06:21:35 PM PDT 24
Peak memory 215800 kb
Host smart-470a6d88-33de-4cad-839d-e5a3073add26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966863590 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1966863590
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2972437143
Short name T567
Test name
Test status
Simulation time 37065086 ps
CPU time 1.2 seconds
Started Aug 12 06:21:28 PM PDT 24
Finished Aug 12 06:21:29 PM PDT 24
Peak memory 217656 kb
Host smart-4afccb92-2f7f-4d2d-aa42-c84fc8ea5208
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972437143 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2972437143
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_genbits.588760863
Short name T448
Test name
Test status
Simulation time 45129927 ps
CPU time 1.75 seconds
Started Aug 12 06:21:28 PM PDT 24
Finished Aug 12 06:21:30 PM PDT 24
Peak memory 219052 kb
Host smart-9c3fda47-bcb0-4b61-8a22-ad82b8412222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588760863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.588760863
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1765217016
Short name T913
Test name
Test status
Simulation time 38398525 ps
CPU time 0.93 seconds
Started Aug 12 06:21:25 PM PDT 24
Finished Aug 12 06:21:26 PM PDT 24
Peak memory 215860 kb
Host smart-e3b2095e-3473-4a17-9f90-9e84d1c1cd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765217016 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1765217016
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.4196430084
Short name T434
Test name
Test status
Simulation time 16542644 ps
CPU time 0.95 seconds
Started Aug 12 06:21:25 PM PDT 24
Finished Aug 12 06:21:26 PM PDT 24
Peak memory 215644 kb
Host smart-0c516ffe-b0cf-400d-b6c1-f960f5b760d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196430084 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.4196430084
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.479097954
Short name T794
Test name
Test status
Simulation time 55527028 ps
CPU time 1.8 seconds
Started Aug 12 06:21:52 PM PDT 24
Finished Aug 12 06:21:54 PM PDT 24
Peak memory 217680 kb
Host smart-ace390b3-ea74-424a-ba0c-681c2cd96c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479097954 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.479097954
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2594787758
Short name T113
Test name
Test status
Simulation time 9628046693 ps
CPU time 59.75 seconds
Started Aug 12 06:21:19 PM PDT 24
Finished Aug 12 06:22:19 PM PDT 24
Peak memory 219460 kb
Host smart-72799acb-1e72-4e9a-ae9f-3b7a8275e765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594787758 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2594787758
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.865845554
Short name T490
Test name
Test status
Simulation time 32120153 ps
CPU time 1.22 seconds
Started Aug 12 06:21:45 PM PDT 24
Finished Aug 12 06:21:47 PM PDT 24
Peak memory 219088 kb
Host smart-3b5e25c8-175a-41cf-bf05-b8d81dd60cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865845554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.865845554
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.422773669
Short name T436
Test name
Test status
Simulation time 28053229 ps
CPU time 1.08 seconds
Started Aug 12 06:21:29 PM PDT 24
Finished Aug 12 06:21:30 PM PDT 24
Peak memory 207236 kb
Host smart-fe3f3a9c-cb2a-47e8-a52f-0ecc8cf56422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422773669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.422773669
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2020697786
Short name T546
Test name
Test status
Simulation time 149304425 ps
CPU time 1.08 seconds
Started Aug 12 06:21:44 PM PDT 24
Finished Aug 12 06:21:45 PM PDT 24
Peak memory 216064 kb
Host smart-f924c530-c428-40bc-ad05-8e0855cf5c4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020697786 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2020697786
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2739733925
Short name T798
Test name
Test status
Simulation time 19156353 ps
CPU time 1.06 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:48 PM PDT 24
Peak memory 219296 kb
Host smart-ee081436-a6c8-4aa5-95c7-024c2e9a790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739733925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2739733925
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.791563963
Short name T348
Test name
Test status
Simulation time 78366730 ps
CPU time 1.42 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 218128 kb
Host smart-c5415506-c1a2-4d06-9abb-6e20fdacbe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791563963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.791563963
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2331380925
Short name T17
Test name
Test status
Simulation time 24996469 ps
CPU time 1.05 seconds
Started Aug 12 06:21:41 PM PDT 24
Finished Aug 12 06:21:42 PM PDT 24
Peak memory 224448 kb
Host smart-3e4ea578-338e-4fa3-858f-05fc868a6faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331380925 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2331380925
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2593325500
Short name T380
Test name
Test status
Simulation time 113801399 ps
CPU time 0.89 seconds
Started Aug 12 06:21:29 PM PDT 24
Finished Aug 12 06:21:30 PM PDT 24
Peak memory 215440 kb
Host smart-e68457e4-6a94-469f-8108-22ede1b5c046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593325500 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2593325500
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3632688929
Short name T855
Test name
Test status
Simulation time 1139575019 ps
CPU time 4.15 seconds
Started Aug 12 06:21:31 PM PDT 24
Finished Aug 12 06:21:36 PM PDT 24
Peak memory 217720 kb
Host smart-c971df62-d4f9-49b0-9a15-93dc80d6e1e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632688929 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3632688929
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1316035167
Short name T238
Test name
Test status
Simulation time 5815012041 ps
CPU time 68.23 seconds
Started Aug 12 06:21:31 PM PDT 24
Finished Aug 12 06:22:39 PM PDT 24
Peak memory 218760 kb
Host smart-1adac539-1463-4455-9836-6a71f063851e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316035167 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1316035167
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2981379330
Short name T479
Test name
Test status
Simulation time 67514022 ps
CPU time 1.18 seconds
Started Aug 12 06:21:38 PM PDT 24
Finished Aug 12 06:21:39 PM PDT 24
Peak memory 220144 kb
Host smart-09e687fe-b640-4c2b-b207-6685216db564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981379330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2981379330
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2139949722
Short name T393
Test name
Test status
Simulation time 14225124 ps
CPU time 0.94 seconds
Started Aug 12 06:21:35 PM PDT 24
Finished Aug 12 06:21:36 PM PDT 24
Peak memory 215612 kb
Host smart-12ac088f-2b58-4ae8-88cc-57e10785b595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139949722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2139949722
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3409570029
Short name T867
Test name
Test status
Simulation time 13673550 ps
CPU time 0.95 seconds
Started Aug 12 06:21:30 PM PDT 24
Finished Aug 12 06:21:31 PM PDT 24
Peak memory 216840 kb
Host smart-9ee2db1f-c92c-4194-a06d-86f5e75b8fc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409570029 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3409570029
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2638567381
Short name T509
Test name
Test status
Simulation time 92286225 ps
CPU time 1.13 seconds
Started Aug 12 06:21:30 PM PDT 24
Finished Aug 12 06:21:31 PM PDT 24
Peak memory 220188 kb
Host smart-4baf5b34-6e45-402a-a807-0948265b2460
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638567381 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2638567381
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3499023511
Short name T210
Test name
Test status
Simulation time 24029640 ps
CPU time 1.2 seconds
Started Aug 12 06:21:28 PM PDT 24
Finished Aug 12 06:21:30 PM PDT 24
Peak memory 220648 kb
Host smart-eca71172-1a7e-42e5-809f-6b63e2375751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499023511 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3499023511
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1535783127
Short name T730
Test name
Test status
Simulation time 36360900 ps
CPU time 1.34 seconds
Started Aug 12 06:21:52 PM PDT 24
Finished Aug 12 06:21:54 PM PDT 24
Peak memory 218972 kb
Host smart-f628c6f9-5968-41e9-9bbf-9666ea3f705f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535783127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1535783127
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2320981585
Short name T32
Test name
Test status
Simulation time 29060960 ps
CPU time 0.88 seconds
Started Aug 12 06:21:34 PM PDT 24
Finished Aug 12 06:21:35 PM PDT 24
Peak memory 216520 kb
Host smart-e509a968-60ca-4baa-80b6-c4f38b6bfdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320981585 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2320981585
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.190361235
Short name T415
Test name
Test status
Simulation time 24424561 ps
CPU time 0.9 seconds
Started Aug 12 06:21:32 PM PDT 24
Finished Aug 12 06:21:33 PM PDT 24
Peak memory 215628 kb
Host smart-ea3fa1c4-9e3f-49c8-a2f1-ab597d52048e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190361235 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.190361235
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2311925502
Short name T673
Test name
Test status
Simulation time 112484673 ps
CPU time 2.52 seconds
Started Aug 12 06:21:28 PM PDT 24
Finished Aug 12 06:21:31 PM PDT 24
Peak memory 217660 kb
Host smart-3185f288-7b64-42dc-9a71-7efacce8a291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311925502 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2311925502
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.86822671
Short name T690
Test name
Test status
Simulation time 2291283520 ps
CPU time 54.53 seconds
Started Aug 12 06:21:40 PM PDT 24
Finished Aug 12 06:22:34 PM PDT 24
Peak memory 218584 kb
Host smart-5477bdcd-0ff7-454d-9967-af0e6a014c21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86822671 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.86822671
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2769279754
Short name T802
Test name
Test status
Simulation time 24539708 ps
CPU time 1.16 seconds
Started Aug 12 06:21:31 PM PDT 24
Finished Aug 12 06:21:32 PM PDT 24
Peak memory 219204 kb
Host smart-5198f41e-2af7-4353-aa2c-4ee8a4f0fdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769279754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2769279754
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3598875481
Short name T510
Test name
Test status
Simulation time 89297581 ps
CPU time 0.84 seconds
Started Aug 12 06:21:33 PM PDT 24
Finished Aug 12 06:21:34 PM PDT 24
Peak memory 207268 kb
Host smart-2353112f-f394-431e-a59f-cb238b833636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598875481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3598875481
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1291283344
Short name T941
Test name
Test status
Simulation time 40119047 ps
CPU time 0.83 seconds
Started Aug 12 06:21:30 PM PDT 24
Finished Aug 12 06:21:31 PM PDT 24
Peak memory 216940 kb
Host smart-6628158b-f0a6-4228-a9ff-8f24f4d8bc81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291283344 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1291283344
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.4133038041
Short name T127
Test name
Test status
Simulation time 249924649 ps
CPU time 1.07 seconds
Started Aug 12 06:21:32 PM PDT 24
Finished Aug 12 06:21:34 PM PDT 24
Peak memory 217636 kb
Host smart-d94113f3-279b-4075-97f2-1b490fcd9f6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133038041 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.4133038041
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.46109612
Short name T910
Test name
Test status
Simulation time 19457889 ps
CPU time 1.13 seconds
Started Aug 12 06:21:34 PM PDT 24
Finished Aug 12 06:21:35 PM PDT 24
Peak memory 219060 kb
Host smart-49125742-ac56-4fe3-89f5-4352f5dba723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46109612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.46109612
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.4240092583
Short name T560
Test name
Test status
Simulation time 167690441 ps
CPU time 1.83 seconds
Started Aug 12 06:21:29 PM PDT 24
Finished Aug 12 06:21:31 PM PDT 24
Peak memory 219252 kb
Host smart-2c99d438-d87f-4075-beeb-ce0c330b7a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240092583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4240092583
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2904719646
Short name T727
Test name
Test status
Simulation time 33115181 ps
CPU time 0.85 seconds
Started Aug 12 06:21:27 PM PDT 24
Finished Aug 12 06:21:28 PM PDT 24
Peak memory 215956 kb
Host smart-a62fdb2e-c9d5-4e75-96ff-fbdaaa14a528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904719646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2904719646
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1022056854
Short name T708
Test name
Test status
Simulation time 25207185 ps
CPU time 0.92 seconds
Started Aug 12 06:21:29 PM PDT 24
Finished Aug 12 06:21:30 PM PDT 24
Peak memory 215716 kb
Host smart-95a69b11-c438-43c7-9f48-84d0635d9e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022056854 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1022056854
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2676030911
Short name T254
Test name
Test status
Simulation time 370286870 ps
CPU time 6.74 seconds
Started Aug 12 06:21:27 PM PDT 24
Finished Aug 12 06:21:34 PM PDT 24
Peak memory 215648 kb
Host smart-b793e9c9-2478-4b43-9cd0-2322c0f9670c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676030911 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2676030911
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_alert.3215406535
Short name T959
Test name
Test status
Simulation time 113789546 ps
CPU time 1.16 seconds
Started Aug 12 06:21:45 PM PDT 24
Finished Aug 12 06:21:46 PM PDT 24
Peak memory 220316 kb
Host smart-cce7637b-2def-4f35-9ee1-3761f9dc2bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215406535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3215406535
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2644079126
Short name T440
Test name
Test status
Simulation time 39498620 ps
CPU time 0.82 seconds
Started Aug 12 06:21:39 PM PDT 24
Finished Aug 12 06:21:40 PM PDT 24
Peak memory 207044 kb
Host smart-2fe531ec-044c-4329-b18b-745cdf0d1946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644079126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2644079126
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1881680605
Short name T896
Test name
Test status
Simulation time 45792199 ps
CPU time 1.07 seconds
Started Aug 12 06:21:43 PM PDT 24
Finished Aug 12 06:21:44 PM PDT 24
Peak memory 217708 kb
Host smart-c6510ed1-b206-4f6f-8850-d93de36b7af7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881680605 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1881680605
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.204165924
Short name T464
Test name
Test status
Simulation time 19214900 ps
CPU time 1.11 seconds
Started Aug 12 06:21:32 PM PDT 24
Finished Aug 12 06:21:34 PM PDT 24
Peak memory 219216 kb
Host smart-3f75e7d1-c1ad-4914-b7fb-9dd0c82d45be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204165924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.204165924
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1191098208
Short name T906
Test name
Test status
Simulation time 67354262 ps
CPU time 1.24 seconds
Started Aug 12 06:21:39 PM PDT 24
Finished Aug 12 06:21:40 PM PDT 24
Peak memory 220240 kb
Host smart-b2474f54-371a-45d7-936e-b2c091027c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191098208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1191098208
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.414735304
Short name T482
Test name
Test status
Simulation time 24395478 ps
CPU time 0.98 seconds
Started Aug 12 06:21:28 PM PDT 24
Finished Aug 12 06:21:30 PM PDT 24
Peak memory 215920 kb
Host smart-3e9b75bf-a9d9-4664-ac18-ef76abc15227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414735304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.414735304
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.104116022
Short name T819
Test name
Test status
Simulation time 23975411 ps
CPU time 0.93 seconds
Started Aug 12 06:21:37 PM PDT 24
Finished Aug 12 06:21:38 PM PDT 24
Peak memory 215552 kb
Host smart-8423bf5b-d522-4627-bf41-dce91a38aeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104116022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.104116022
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1104473730
Short name T684
Test name
Test status
Simulation time 305285810 ps
CPU time 6.21 seconds
Started Aug 12 06:21:32 PM PDT 24
Finished Aug 12 06:21:38 PM PDT 24
Peak memory 217716 kb
Host smart-9530881e-a38a-438e-bc33-9fa74017b4b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104473730 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1104473730
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_alert.2019025512
Short name T776
Test name
Test status
Simulation time 75466151 ps
CPU time 1.15 seconds
Started Aug 12 06:20:44 PM PDT 24
Finished Aug 12 06:20:45 PM PDT 24
Peak memory 218884 kb
Host smart-90994376-f67b-4ada-9e3d-3efbc170a48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019025512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2019025512
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1752208462
Short name T412
Test name
Test status
Simulation time 54686177 ps
CPU time 0.93 seconds
Started Aug 12 06:20:45 PM PDT 24
Finished Aug 12 06:20:46 PM PDT 24
Peak memory 215608 kb
Host smart-6b58fc8c-9eed-4a79-8bcc-f9a1bf89651a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752208462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1752208462
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.4112138956
Short name T649
Test name
Test status
Simulation time 38464660 ps
CPU time 0.86 seconds
Started Aug 12 06:20:45 PM PDT 24
Finished Aug 12 06:20:46 PM PDT 24
Peak memory 215772 kb
Host smart-f1295482-19b7-4a96-972e-8cce7c5dd3c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112138956 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.4112138956
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2311528277
Short name T214
Test name
Test status
Simulation time 135580590 ps
CPU time 1.1 seconds
Started Aug 12 06:20:41 PM PDT 24
Finished Aug 12 06:20:42 PM PDT 24
Peak memory 220084 kb
Host smart-c329e839-b8f1-40ac-a178-e130652b77e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311528277 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2311528277
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.4011884586
Short name T143
Test name
Test status
Simulation time 92006510 ps
CPU time 1.04 seconds
Started Aug 12 06:20:47 PM PDT 24
Finished Aug 12 06:20:48 PM PDT 24
Peak memory 229744 kb
Host smart-db49e047-39a3-494c-b751-6811b82d0aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011884586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.4011884586
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1313376800
Short name T854
Test name
Test status
Simulation time 141902112 ps
CPU time 1.21 seconds
Started Aug 12 06:20:43 PM PDT 24
Finished Aug 12 06:20:44 PM PDT 24
Peak memory 217976 kb
Host smart-0b2958c6-be56-4644-bd6f-4c4619d03e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313376800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1313376800
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1672996286
Short name T650
Test name
Test status
Simulation time 24406057 ps
CPU time 1.04 seconds
Started Aug 12 06:20:47 PM PDT 24
Finished Aug 12 06:20:48 PM PDT 24
Peak memory 215780 kb
Host smart-d2544e32-b3f2-46a2-82a9-c66f8aa2b8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672996286 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1672996286
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3438998626
Short name T28
Test name
Test status
Simulation time 40722856 ps
CPU time 0.92 seconds
Started Aug 12 06:20:39 PM PDT 24
Finished Aug 12 06:20:40 PM PDT 24
Peak memory 207440 kb
Host smart-214d51b9-a9e3-4244-aa36-ca0e394daa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438998626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3438998626
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1103506288
Short name T72
Test name
Test status
Simulation time 1093530879 ps
CPU time 5.11 seconds
Started Aug 12 06:20:44 PM PDT 24
Finished Aug 12 06:20:49 PM PDT 24
Peak memory 239768 kb
Host smart-2b3b6bbe-8efe-4b42-8292-efd5fb1a4b22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103506288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1103506288
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1243715976
Short name T759
Test name
Test status
Simulation time 25739294 ps
CPU time 0.95 seconds
Started Aug 12 06:20:41 PM PDT 24
Finished Aug 12 06:20:42 PM PDT 24
Peak memory 215664 kb
Host smart-75ee9bd2-208e-4b32-a9f4-0cd6fce218c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243715976 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1243715976
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2737954417
Short name T536
Test name
Test status
Simulation time 42122597 ps
CPU time 1.07 seconds
Started Aug 12 06:20:49 PM PDT 24
Finished Aug 12 06:20:50 PM PDT 24
Peak memory 207060 kb
Host smart-15fce829-7af5-4966-bb68-bb21c9fce37e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737954417 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2737954417
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1418885858
Short name T233
Test name
Test status
Simulation time 2833130902 ps
CPU time 41.82 seconds
Started Aug 12 06:20:42 PM PDT 24
Finished Aug 12 06:21:24 PM PDT 24
Peak memory 221124 kb
Host smart-ec67194c-6709-494f-944f-712d0f5ee118
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418885858 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1418885858
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.67656217
Short name T136
Test name
Test status
Simulation time 48675504 ps
CPU time 1.29 seconds
Started Aug 12 06:21:41 PM PDT 24
Finished Aug 12 06:21:42 PM PDT 24
Peak memory 220036 kb
Host smart-61141cae-e758-4325-8d0d-fad61a9d8f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67656217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.67656217
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2185326360
Short name T84
Test name
Test status
Simulation time 36733025 ps
CPU time 0.81 seconds
Started Aug 12 06:21:45 PM PDT 24
Finished Aug 12 06:21:46 PM PDT 24
Peak memory 207100 kb
Host smart-31cc15c3-8415-4cee-aaaf-c006d1f8b3ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185326360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2185326360
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2649827647
Short name T617
Test name
Test status
Simulation time 17338341 ps
CPU time 0.85 seconds
Started Aug 12 06:21:31 PM PDT 24
Finished Aug 12 06:21:32 PM PDT 24
Peak memory 217008 kb
Host smart-4a85ef84-41ab-449c-ae90-a7aa665d21dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649827647 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2649827647
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1857849343
Short name T22
Test name
Test status
Simulation time 32345133 ps
CPU time 1.15 seconds
Started Aug 12 06:21:31 PM PDT 24
Finished Aug 12 06:21:32 PM PDT 24
Peak memory 218912 kb
Host smart-9584afd7-c1da-4106-b77a-ad37b83ae71d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857849343 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1857849343
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.713245891
Short name T715
Test name
Test status
Simulation time 34959101 ps
CPU time 1.17 seconds
Started Aug 12 06:21:41 PM PDT 24
Finished Aug 12 06:21:43 PM PDT 24
Peak memory 224380 kb
Host smart-03d2c371-bd75-4628-bbcb-f73100ad7e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713245891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.713245891
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.4130284245
Short name T329
Test name
Test status
Simulation time 224948484 ps
CPU time 2.91 seconds
Started Aug 12 06:21:44 PM PDT 24
Finished Aug 12 06:21:47 PM PDT 24
Peak memory 220824 kb
Host smart-63c0974b-0f46-4abd-aee7-e8d81f273d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130284245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4130284245
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1117083212
Short name T4
Test name
Test status
Simulation time 20071710 ps
CPU time 1.05 seconds
Started Aug 12 06:21:38 PM PDT 24
Finished Aug 12 06:21:39 PM PDT 24
Peak memory 216580 kb
Host smart-2aff7d35-e55c-4a58-9b36-9256b70735e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117083212 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1117083212
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.743432666
Short name T557
Test name
Test status
Simulation time 24933188 ps
CPU time 0.88 seconds
Started Aug 12 06:21:30 PM PDT 24
Finished Aug 12 06:21:31 PM PDT 24
Peak memory 215668 kb
Host smart-3e012fd4-78c0-4179-bb46-bf4be36e2996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743432666 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.743432666
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.49344404
Short name T796
Test name
Test status
Simulation time 313761980 ps
CPU time 6.5 seconds
Started Aug 12 06:21:28 PM PDT 24
Finished Aug 12 06:21:35 PM PDT 24
Peak memory 215672 kb
Host smart-e5ce6fcc-82cf-4f0b-9c52-ee2e478b8109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49344404 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.49344404
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1561708041
Short name T414
Test name
Test status
Simulation time 3147564525 ps
CPU time 64.6 seconds
Started Aug 12 06:21:27 PM PDT 24
Finished Aug 12 06:22:32 PM PDT 24
Peak memory 218320 kb
Host smart-0bfe9c6a-8132-4cf8-a615-17a23ede465a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561708041 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1561708041
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3211006999
Short name T526
Test name
Test status
Simulation time 33748225 ps
CPU time 1.24 seconds
Started Aug 12 06:21:35 PM PDT 24
Finished Aug 12 06:21:36 PM PDT 24
Peak memory 218932 kb
Host smart-0216c4c3-63fd-4487-af8e-e31f0d65b664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211006999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3211006999
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2410397141
Short name T82
Test name
Test status
Simulation time 23663773 ps
CPU time 0.86 seconds
Started Aug 12 06:21:32 PM PDT 24
Finished Aug 12 06:21:33 PM PDT 24
Peak memory 215540 kb
Host smart-9ea74055-75ce-4a41-9133-cf1080cb40f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410397141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2410397141
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3668219643
Short name T218
Test name
Test status
Simulation time 38995523 ps
CPU time 0.81 seconds
Started Aug 12 06:21:41 PM PDT 24
Finished Aug 12 06:21:45 PM PDT 24
Peak memory 216904 kb
Host smart-bd15cb39-a376-4099-b06f-2dd2d52d962c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668219643 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3668219643
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.793975264
Short name T600
Test name
Test status
Simulation time 67591653 ps
CPU time 1.11 seconds
Started Aug 12 06:21:38 PM PDT 24
Finished Aug 12 06:21:39 PM PDT 24
Peak memory 220332 kb
Host smart-cd47b20e-f395-488a-a0b4-8b90ed0686b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793975264 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.793975264
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.358739389
Short name T514
Test name
Test status
Simulation time 44778092 ps
CPU time 1.11 seconds
Started Aug 12 06:21:32 PM PDT 24
Finished Aug 12 06:21:33 PM PDT 24
Peak memory 220284 kb
Host smart-37d2864a-1175-4dc7-bb22-ea3c7ed46ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358739389 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.358739389
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3559757820
Short name T953
Test name
Test status
Simulation time 91392572 ps
CPU time 2.65 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 220068 kb
Host smart-88f3cd16-d300-4a68-9290-91d39a3e8be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559757820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3559757820
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2771897788
Short name T905
Test name
Test status
Simulation time 20726256 ps
CPU time 1.1 seconds
Started Aug 12 06:21:45 PM PDT 24
Finished Aug 12 06:21:47 PM PDT 24
Peak memory 215740 kb
Host smart-88caddd3-7d5a-4cd3-a353-cf385dad3316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771897788 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2771897788
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2244833106
Short name T357
Test name
Test status
Simulation time 15473894 ps
CPU time 0.99 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 215628 kb
Host smart-2e5529c3-ac1b-4e10-b800-5f6d0b405d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244833106 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2244833106
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.695808356
Short name T621
Test name
Test status
Simulation time 160987481 ps
CPU time 3.48 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 215772 kb
Host smart-9edf5b85-19ca-4c91-8ee5-f0b0a946c5d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695808356 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.695808356
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_alert.3694412939
Short name T422
Test name
Test status
Simulation time 27258929 ps
CPU time 1.19 seconds
Started Aug 12 06:21:40 PM PDT 24
Finished Aug 12 06:21:42 PM PDT 24
Peak memory 220192 kb
Host smart-70bb5208-f6ba-4c4b-9309-daa70f0372ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694412939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3694412939
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3236189077
Short name T386
Test name
Test status
Simulation time 13433739 ps
CPU time 0.88 seconds
Started Aug 12 06:21:31 PM PDT 24
Finished Aug 12 06:21:32 PM PDT 24
Peak memory 207484 kb
Host smart-259bf65a-f3bf-4ef1-b99a-e9d4b33a4d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236189077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3236189077
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2687919028
Short name T221
Test name
Test status
Simulation time 12431413 ps
CPU time 0.92 seconds
Started Aug 12 06:21:32 PM PDT 24
Finished Aug 12 06:21:33 PM PDT 24
Peak memory 216156 kb
Host smart-48ee7114-9841-420e-9cc0-4bf960a7b024
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687919028 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2687919028
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2203916713
Short name T209
Test name
Test status
Simulation time 158536482 ps
CPU time 1.02 seconds
Started Aug 12 06:21:41 PM PDT 24
Finished Aug 12 06:21:42 PM PDT 24
Peak memory 220080 kb
Host smart-5f5f29ab-1266-4a13-af8c-d09cd3afbaf0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203916713 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2203916713
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1538384582
Short name T176
Test name
Test status
Simulation time 18095792 ps
CPU time 1.02 seconds
Started Aug 12 06:21:43 PM PDT 24
Finished Aug 12 06:21:44 PM PDT 24
Peak memory 219036 kb
Host smart-1b173ab5-aaa6-438c-9f3e-85feeaee3ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538384582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1538384582
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3421905187
Short name T449
Test name
Test status
Simulation time 216672399 ps
CPU time 1.02 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 217656 kb
Host smart-e0ae5f9f-5854-4281-8015-2363a1df4242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421905187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3421905187
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.269922258
Short name T767
Test name
Test status
Simulation time 25123140 ps
CPU time 0.86 seconds
Started Aug 12 06:21:41 PM PDT 24
Finished Aug 12 06:21:42 PM PDT 24
Peak memory 216384 kb
Host smart-4997ea2f-6fc3-4da7-85da-b2a02d9f5a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269922258 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.269922258
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1661965994
Short name T692
Test name
Test status
Simulation time 21270630 ps
CPU time 0.99 seconds
Started Aug 12 06:21:44 PM PDT 24
Finished Aug 12 06:21:45 PM PDT 24
Peak memory 215744 kb
Host smart-0aa54e03-6579-4324-bea1-c1f958d4e4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661965994 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1661965994
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1697853265
Short name T507
Test name
Test status
Simulation time 1282784945 ps
CPU time 3.18 seconds
Started Aug 12 06:21:42 PM PDT 24
Finished Aug 12 06:21:45 PM PDT 24
Peak memory 217568 kb
Host smart-abd9d31f-f54d-49b7-b27e-1a75a3570cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697853265 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1697853265
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.87500878
Short name T912
Test name
Test status
Simulation time 9228196573 ps
CPU time 52.42 seconds
Started Aug 12 06:21:44 PM PDT 24
Finished Aug 12 06:22:37 PM PDT 24
Peak memory 219100 kb
Host smart-cec3a0a3-a4ed-467b-812f-caecc74a2c00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87500878 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.87500878
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.556775254
Short name T868
Test name
Test status
Simulation time 24774025 ps
CPU time 1.19 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:48 PM PDT 24
Peak memory 218940 kb
Host smart-53a50367-e499-4a81-b4ae-8731de665c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556775254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.556775254
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1313151986
Short name T732
Test name
Test status
Simulation time 38558998 ps
CPU time 1.05 seconds
Started Aug 12 06:21:43 PM PDT 24
Finished Aug 12 06:21:44 PM PDT 24
Peak memory 207252 kb
Host smart-98f2e9ae-2064-4293-8276-287faeafc82b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313151986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1313151986
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.4032729029
Short name T41
Test name
Test status
Simulation time 11696244 ps
CPU time 0.92 seconds
Started Aug 12 06:21:45 PM PDT 24
Finished Aug 12 06:21:46 PM PDT 24
Peak memory 215992 kb
Host smart-8e800844-aa36-4e0f-8c3d-586195ad32be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032729029 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.4032729029
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2128413933
Short name T642
Test name
Test status
Simulation time 31643710 ps
CPU time 1.18 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 217588 kb
Host smart-b007c6f7-c49f-42e9-8326-011f29121f0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128413933 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2128413933
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2814216111
Short name T950
Test name
Test status
Simulation time 47151465 ps
CPU time 0.79 seconds
Started Aug 12 06:21:42 PM PDT 24
Finished Aug 12 06:21:43 PM PDT 24
Peak memory 219668 kb
Host smart-ef7f8d75-6712-49ee-9fbd-5305e79cea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814216111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2814216111
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3028062236
Short name T749
Test name
Test status
Simulation time 49167848 ps
CPU time 1.06 seconds
Started Aug 12 06:21:45 PM PDT 24
Finished Aug 12 06:21:47 PM PDT 24
Peak memory 217864 kb
Host smart-3327ca3b-b329-4342-83e3-5608b62b6e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028062236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3028062236
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2698527402
Short name T358
Test name
Test status
Simulation time 25731516 ps
CPU time 0.97 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 215988 kb
Host smart-37bf7014-e12c-4eb4-8c52-811838422acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698527402 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2698527402
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.254052697
Short name T410
Test name
Test status
Simulation time 18759964 ps
CPU time 1.01 seconds
Started Aug 12 06:21:38 PM PDT 24
Finished Aug 12 06:21:39 PM PDT 24
Peak memory 215700 kb
Host smart-8848835f-560f-4361-8d3f-4f34426ec9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254052697 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.254052697
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1363700023
Short name T249
Test name
Test status
Simulation time 384851914 ps
CPU time 6.46 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:56 PM PDT 24
Peak memory 217632 kb
Host smart-3a4b69d5-18a5-4e94-80f2-5091030e5723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363700023 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1363700023
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3826465270
Short name T594
Test name
Test status
Simulation time 3475410392 ps
CPU time 46.34 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:22:35 PM PDT 24
Peak memory 219564 kb
Host smart-abc4c4ab-fe8e-45b2-bfce-dfdb777839f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826465270 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3826465270
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2433805395
Short name T678
Test name
Test status
Simulation time 99050838 ps
CPU time 1.2 seconds
Started Aug 12 06:21:43 PM PDT 24
Finished Aug 12 06:21:45 PM PDT 24
Peak memory 216044 kb
Host smart-fd18eae2-d625-413c-b913-e9ac9d766190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433805395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2433805395
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2338564173
Short name T383
Test name
Test status
Simulation time 18374871 ps
CPU time 0.95 seconds
Started Aug 12 06:21:40 PM PDT 24
Finished Aug 12 06:21:41 PM PDT 24
Peak memory 215676 kb
Host smart-142b442b-c40a-4c62-b47b-ff922866e522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338564173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2338564173
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2431497377
Short name T103
Test name
Test status
Simulation time 68281591 ps
CPU time 0.82 seconds
Started Aug 12 06:21:47 PM PDT 24
Finished Aug 12 06:21:48 PM PDT 24
Peak memory 217072 kb
Host smart-cbc83515-a705-4e13-831d-e9214300699f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431497377 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2431497377
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1861160070
Short name T644
Test name
Test status
Simulation time 41120739 ps
CPU time 1.29 seconds
Started Aug 12 06:21:36 PM PDT 24
Finished Aug 12 06:21:38 PM PDT 24
Peak memory 217724 kb
Host smart-0702d54a-5784-4086-a46c-988d0a0f5147
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861160070 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1861160070
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.678567750
Short name T687
Test name
Test status
Simulation time 28035396 ps
CPU time 0.82 seconds
Started Aug 12 06:21:40 PM PDT 24
Finished Aug 12 06:21:41 PM PDT 24
Peak memory 218904 kb
Host smart-ba16cac9-c377-4a9c-a733-d21eba77b504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678567750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.678567750
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.4763332
Short name T478
Test name
Test status
Simulation time 32264687 ps
CPU time 1.37 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:47 PM PDT 24
Peak memory 220300 kb
Host smart-9a5044a0-b6e2-4af2-a7d9-38bbc3efaa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4763332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.4763332
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1454626400
Short name T59
Test name
Test status
Simulation time 41569561 ps
CPU time 0.99 seconds
Started Aug 12 06:21:31 PM PDT 24
Finished Aug 12 06:21:32 PM PDT 24
Peak memory 224216 kb
Host smart-127886fa-61e8-44f8-b732-247258a6a8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454626400 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1454626400
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2458781724
Short name T64
Test name
Test status
Simulation time 104510699 ps
CPU time 0.88 seconds
Started Aug 12 06:21:55 PM PDT 24
Finished Aug 12 06:21:56 PM PDT 24
Peak memory 215644 kb
Host smart-aae67d70-d3b1-4b07-8b90-ba91133af43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458781724 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2458781724
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3936660166
Short name T451
Test name
Test status
Simulation time 1105187447 ps
CPU time 3.44 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 217600 kb
Host smart-dd64dea4-e700-476d-942c-127b8e5d13dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936660166 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3936660166
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2797360180
Short name T38
Test name
Test status
Simulation time 2281174527 ps
CPU time 56.44 seconds
Started Aug 12 06:21:32 PM PDT 24
Finished Aug 12 06:22:29 PM PDT 24
Peak memory 218324 kb
Host smart-078924de-edf6-4b66-bd64-604605c259da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797360180 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2797360180
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.874902791
Short name T704
Test name
Test status
Simulation time 23801649 ps
CPU time 1.17 seconds
Started Aug 12 06:21:43 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 220948 kb
Host smart-5ddae2ec-a500-4e8b-93cf-b35dc532144e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874902791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.874902791
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3167304398
Short name T394
Test name
Test status
Simulation time 66038241 ps
CPU time 1 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 207132 kb
Host smart-47d380ee-8627-4656-a955-00766f828994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167304398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3167304398
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.4128287118
Short name T226
Test name
Test status
Simulation time 12207560 ps
CPU time 0.87 seconds
Started Aug 12 06:21:57 PM PDT 24
Finished Aug 12 06:21:58 PM PDT 24
Peak memory 215820 kb
Host smart-658d45f9-27d9-4547-bd38-a0edfd9e5fbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128287118 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.4128287118
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3610687646
Short name T157
Test name
Test status
Simulation time 47296114 ps
CPU time 1.13 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 219920 kb
Host smart-10f258a7-a257-4bf4-8967-9b016d5c3b93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610687646 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3610687646
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.903774435
Short name T155
Test name
Test status
Simulation time 20486384 ps
CPU time 1.12 seconds
Started Aug 12 06:22:04 PM PDT 24
Finished Aug 12 06:22:05 PM PDT 24
Peak memory 220408 kb
Host smart-6ee55ee7-2026-4765-97cf-919b81da7833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903774435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.903774435
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.746221243
Short name T742
Test name
Test status
Simulation time 29541742 ps
CPU time 1.32 seconds
Started Aug 12 06:21:45 PM PDT 24
Finished Aug 12 06:21:47 PM PDT 24
Peak memory 219008 kb
Host smart-8bbf827f-3013-4d30-898c-849175a7f8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746221243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.746221243
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1883923403
Short name T61
Test name
Test status
Simulation time 32748421 ps
CPU time 1.01 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 224176 kb
Host smart-703eecb3-dc18-44a3-85f4-fd03777af424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883923403 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1883923403
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.713357309
Short name T826
Test name
Test status
Simulation time 15291750 ps
CPU time 0.97 seconds
Started Aug 12 06:21:44 PM PDT 24
Finished Aug 12 06:21:45 PM PDT 24
Peak memory 215700 kb
Host smart-d7eaf9fa-53c9-4e09-92e8-00fe82170fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713357309 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.713357309
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3384791840
Short name T476
Test name
Test status
Simulation time 573355478 ps
CPU time 5.55 seconds
Started Aug 12 06:21:37 PM PDT 24
Finished Aug 12 06:21:43 PM PDT 24
Peak memory 217628 kb
Host smart-f23052c5-9543-49ff-82fa-7069f0510d0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384791840 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3384791840
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.720633334
Short name T494
Test name
Test status
Simulation time 18891464713 ps
CPU time 60.28 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:22:51 PM PDT 24
Peak memory 219568 kb
Host smart-fc1c422f-9127-4894-a13c-1ee867916f57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720633334 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.720633334
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.24746896
Short name T628
Test name
Test status
Simulation time 75461396 ps
CPU time 1.14 seconds
Started Aug 12 06:21:55 PM PDT 24
Finished Aug 12 06:22:02 PM PDT 24
Peak memory 220448 kb
Host smart-88fc06e9-acf2-445b-8898-11de3feec8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24746896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.24746896
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3605615261
Short name T471
Test name
Test status
Simulation time 17256167 ps
CPU time 0.95 seconds
Started Aug 12 06:21:44 PM PDT 24
Finished Aug 12 06:21:45 PM PDT 24
Peak memory 215636 kb
Host smart-a31082a9-20e5-4cea-abb2-dbfad2e45d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605615261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3605615261
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2702224945
Short name T544
Test name
Test status
Simulation time 14422845 ps
CPU time 0.87 seconds
Started Aug 12 06:21:43 PM PDT 24
Finished Aug 12 06:21:44 PM PDT 24
Peak memory 215836 kb
Host smart-067ed8b8-9f0e-4846-844a-0bff115af149
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702224945 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2702224945
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3123886620
Short name T937
Test name
Test status
Simulation time 68824255 ps
CPU time 1.03 seconds
Started Aug 12 06:22:06 PM PDT 24
Finished Aug 12 06:22:07 PM PDT 24
Peak memory 220028 kb
Host smart-a891fb6f-2b41-4b11-a635-eb1b69b1d138
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123886620 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3123886620
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_genbits.1562276917
Short name T669
Test name
Test status
Simulation time 129544024 ps
CPU time 1.17 seconds
Started Aug 12 06:21:52 PM PDT 24
Finished Aug 12 06:21:54 PM PDT 24
Peak memory 217780 kb
Host smart-8b723a53-1bcc-41c4-99d2-8d10a13fdb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562276917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1562276917
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2482706964
Short name T60
Test name
Test status
Simulation time 22175762 ps
CPU time 1.22 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 224336 kb
Host smart-8ef6288a-c4f6-485a-b28e-10650194b1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482706964 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2482706964
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1505427865
Short name T361
Test name
Test status
Simulation time 19084170 ps
CPU time 0.97 seconds
Started Aug 12 06:21:51 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 215656 kb
Host smart-c4a4a877-a83f-44a7-b577-112689160166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505427865 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1505427865
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3090661083
Short name T897
Test name
Test status
Simulation time 978916758 ps
CPU time 5.28 seconds
Started Aug 12 06:21:53 PM PDT 24
Finished Aug 12 06:21:58 PM PDT 24
Peak memory 220860 kb
Host smart-61e10e10-5cbe-4725-a50d-70f2521365fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090661083 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3090661083
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_alert.1630431297
Short name T90
Test name
Test status
Simulation time 29911753 ps
CPU time 1.29 seconds
Started Aug 12 06:21:45 PM PDT 24
Finished Aug 12 06:21:47 PM PDT 24
Peak memory 220924 kb
Host smart-e085556d-124a-4c65-bf72-62e46b0f7743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630431297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1630431297
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.887438960
Short name T943
Test name
Test status
Simulation time 18609494 ps
CPU time 0.92 seconds
Started Aug 12 06:21:53 PM PDT 24
Finished Aug 12 06:21:54 PM PDT 24
Peak memory 215584 kb
Host smart-08713324-27b5-4bc4-8618-5afe8aa66788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887438960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.887438960
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.663779137
Short name T838
Test name
Test status
Simulation time 14488974 ps
CPU time 0.9 seconds
Started Aug 12 06:21:44 PM PDT 24
Finished Aug 12 06:21:45 PM PDT 24
Peak memory 216060 kb
Host smart-84a0fea3-0d10-4253-9d44-8f7105495e24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663779137 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.663779137
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.3083780532
Short name T148
Test name
Test status
Simulation time 29368350 ps
CPU time 1.33 seconds
Started Aug 12 06:21:47 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 226336 kb
Host smart-96f160be-b8f3-4061-a468-d1e616958fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083780532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3083780532
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_intr.254488160
Short name T247
Test name
Test status
Simulation time 23360334 ps
CPU time 1.16 seconds
Started Aug 12 06:21:59 PM PDT 24
Finished Aug 12 06:22:00 PM PDT 24
Peak memory 215764 kb
Host smart-4e9a2af3-df43-4fec-b67e-6782e2833660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254488160 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.254488160
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3514241973
Short name T743
Test name
Test status
Simulation time 18288232 ps
CPU time 0.96 seconds
Started Aug 12 06:21:44 PM PDT 24
Finished Aug 12 06:21:45 PM PDT 24
Peak memory 215656 kb
Host smart-e857f2bc-f67d-4dab-89d0-9e23b2945ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514241973 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3514241973
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1298360318
Short name T258
Test name
Test status
Simulation time 451547107 ps
CPU time 4.48 seconds
Started Aug 12 06:21:52 PM PDT 24
Finished Aug 12 06:21:57 PM PDT 24
Peak memory 217740 kb
Host smart-ee0df690-aa12-4d38-98cf-1273dd5904c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298360318 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1298360318
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_alert.3009662098
Short name T458
Test name
Test status
Simulation time 38447454 ps
CPU time 1.34 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 216016 kb
Host smart-8918cd8f-fa64-4538-9c56-47a2293b949e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009662098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3009662098
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2842188408
Short name T390
Test name
Test status
Simulation time 26404986 ps
CPU time 0.89 seconds
Started Aug 12 06:21:52 PM PDT 24
Finished Aug 12 06:21:53 PM PDT 24
Peak memory 215616 kb
Host smart-c6b1ae11-1be7-47b2-8cc8-74a3f579a709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842188408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2842188408
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.464684283
Short name T787
Test name
Test status
Simulation time 34762181 ps
CPU time 0.85 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 216920 kb
Host smart-9112b8bb-8562-4800-86a6-50cdffb66ae7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464684283 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.464684283
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3524408044
Short name T161
Test name
Test status
Simulation time 30634779 ps
CPU time 1.32 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 217568 kb
Host smart-8f28fa43-914b-4b65-8473-58ce8899be29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524408044 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3524408044
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1299356957
Short name T125
Test name
Test status
Simulation time 34374544 ps
CPU time 1.17 seconds
Started Aug 12 06:21:53 PM PDT 24
Finished Aug 12 06:21:54 PM PDT 24
Peak memory 221068 kb
Host smart-d750e98f-1e1a-4344-b437-21f8cd6cd3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299356957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1299356957
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.4186710338
Short name T346
Test name
Test status
Simulation time 57637146 ps
CPU time 1.28 seconds
Started Aug 12 06:21:39 PM PDT 24
Finished Aug 12 06:21:41 PM PDT 24
Peak memory 218880 kb
Host smart-26bf358b-b876-42b5-bba7-5536fea39a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186710338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.4186710338
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.4025714194
Short name T37
Test name
Test status
Simulation time 36298023 ps
CPU time 0.83 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 216288 kb
Host smart-6acdf6d3-2357-4079-b0b3-43937ca9a25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025714194 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.4025714194
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2021026808
Short name T547
Test name
Test status
Simulation time 30859110 ps
CPU time 0.93 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 215700 kb
Host smart-76077527-4605-4392-8bf8-14de8d3f9d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021026808 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2021026808
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.591834635
Short name T419
Test name
Test status
Simulation time 472960968 ps
CPU time 5.37 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:55 PM PDT 24
Peak memory 217668 kb
Host smart-6043b154-cb69-4577-a78e-a89ceed62fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591834635 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.591834635
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_alert.3352209119
Short name T180
Test name
Test status
Simulation time 113553139 ps
CPU time 1.12 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 220976 kb
Host smart-fe0e94d8-45f0-4cbc-9247-920c8ccc69d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352209119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3352209119
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1066170379
Short name T365
Test name
Test status
Simulation time 36472742 ps
CPU time 0.8 seconds
Started Aug 12 06:22:00 PM PDT 24
Finished Aug 12 06:22:00 PM PDT 24
Peak memory 207056 kb
Host smart-178b2d10-ac0f-4b68-9ff5-f29bf9dc23a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066170379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1066170379
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1871258335
Short name T524
Test name
Test status
Simulation time 25332031 ps
CPU time 0.82 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 215824 kb
Host smart-51c478ab-3899-4462-abf5-35eab7a26555
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871258335 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1871258335
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2655105523
Short name T222
Test name
Test status
Simulation time 111976636 ps
CPU time 1.09 seconds
Started Aug 12 06:21:52 PM PDT 24
Finished Aug 12 06:21:53 PM PDT 24
Peak memory 220280 kb
Host smart-315a849c-cad6-47b8-9037-8663a5184e62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655105523 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2655105523
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3674490916
Short name T675
Test name
Test status
Simulation time 32669166 ps
CPU time 1 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 224320 kb
Host smart-f695c8a4-50a6-4c71-b4fd-5568d4c00310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674490916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3674490916
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.4224770376
Short name T631
Test name
Test status
Simulation time 36102879 ps
CPU time 1.28 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:48 PM PDT 24
Peak memory 219116 kb
Host smart-7d5f6e33-98d9-4d89-b2f7-8f9a39070313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224770376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.4224770376
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2735429229
Short name T33
Test name
Test status
Simulation time 23702623 ps
CPU time 0.9 seconds
Started Aug 12 06:21:51 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 216556 kb
Host smart-70e7974e-b007-4bda-91c5-938d19644217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735429229 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2735429229
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.824232008
Short name T573
Test name
Test status
Simulation time 20323495 ps
CPU time 1.1 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 215672 kb
Host smart-153bb352-e942-4444-a5e6-aaafd7509b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824232008 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.824232008
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.72805302
Short name T579
Test name
Test status
Simulation time 147662221 ps
CPU time 1.99 seconds
Started Aug 12 06:21:47 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 215648 kb
Host smart-b795bd4d-a3a7-4611-8bfc-bc6bb1ed2c4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72805302 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.72805302
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_alert.995949844
Short name T427
Test name
Test status
Simulation time 132264172 ps
CPU time 1.15 seconds
Started Aug 12 06:20:41 PM PDT 24
Finished Aug 12 06:20:42 PM PDT 24
Peak memory 220184 kb
Host smart-9f7bbd78-6188-49ab-940f-40967dbb54c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995949844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.995949844
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2281660962
Short name T975
Test name
Test status
Simulation time 55698438 ps
CPU time 1.01 seconds
Started Aug 12 06:20:46 PM PDT 24
Finished Aug 12 06:20:48 PM PDT 24
Peak memory 215612 kb
Host smart-0d01e305-bbe9-42f1-86c6-d057b7e9386f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281660962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2281660962
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2644850294
Short name T883
Test name
Test status
Simulation time 41200798 ps
CPU time 1.05 seconds
Started Aug 12 06:20:44 PM PDT 24
Finished Aug 12 06:20:45 PM PDT 24
Peak memory 219920 kb
Host smart-cd19d6db-11bb-44a1-ae09-fd71301b8fd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644850294 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2644850294
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3038475895
Short name T592
Test name
Test status
Simulation time 45221090 ps
CPU time 0.92 seconds
Started Aug 12 06:20:42 PM PDT 24
Finished Aug 12 06:20:43 PM PDT 24
Peak memory 224128 kb
Host smart-3a80de2f-fd8a-4a83-9f1d-d942737a248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038475895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3038475895
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3175624514
Short name T741
Test name
Test status
Simulation time 180996659 ps
CPU time 1.11 seconds
Started Aug 12 06:20:44 PM PDT 24
Finished Aug 12 06:20:45 PM PDT 24
Peak memory 217700 kb
Host smart-aed116fc-58b7-4ea0-a3d2-6c23d5a4e1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175624514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3175624514
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3110515070
Short name T516
Test name
Test status
Simulation time 29837339 ps
CPU time 0.93 seconds
Started Aug 12 06:20:43 PM PDT 24
Finished Aug 12 06:20:44 PM PDT 24
Peak memory 216396 kb
Host smart-2460ef31-7f87-43e5-97f8-929a8b359e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110515070 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3110515070
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.226888586
Short name T27
Test name
Test status
Simulation time 22634135 ps
CPU time 0.94 seconds
Started Aug 12 06:20:40 PM PDT 24
Finished Aug 12 06:20:41 PM PDT 24
Peak memory 207444 kb
Host smart-19b7bb19-2ca0-437e-8502-a131ce45f80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226888586 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.226888586
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2540844679
Short name T610
Test name
Test status
Simulation time 49064299 ps
CPU time 0.96 seconds
Started Aug 12 06:20:45 PM PDT 24
Finished Aug 12 06:20:46 PM PDT 24
Peak memory 215704 kb
Host smart-7bda1cf3-c8b2-4331-9d5b-8edb79d96bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540844679 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2540844679
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1490686817
Short name T664
Test name
Test status
Simulation time 224443312 ps
CPU time 1.76 seconds
Started Aug 12 06:20:48 PM PDT 24
Finished Aug 12 06:20:49 PM PDT 24
Peak memory 217752 kb
Host smart-3b105e20-cd4e-4b28-9054-fd247e298747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490686817 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1490686817
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/50.edn_alert.82462060
Short name T840
Test name
Test status
Simulation time 112563284 ps
CPU time 1.09 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 219384 kb
Host smart-09b3561f-c749-4891-af88-2348f611512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82462060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.82462060
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1890543171
Short name T215
Test name
Test status
Simulation time 19828487 ps
CPU time 0.98 seconds
Started Aug 12 06:21:39 PM PDT 24
Finished Aug 12 06:21:40 PM PDT 24
Peak memory 220176 kb
Host smart-2be2aeb1-c14f-4ac0-bfa7-fe18f9e5f836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890543171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1890543171
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1058966085
Short name T420
Test name
Test status
Simulation time 108558574 ps
CPU time 1.35 seconds
Started Aug 12 06:21:40 PM PDT 24
Finished Aug 12 06:21:42 PM PDT 24
Peak memory 217780 kb
Host smart-94fcea75-1e7d-4d06-b511-bfa3b4d57226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058966085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1058966085
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3303049837
Short name T769
Test name
Test status
Simulation time 83148833 ps
CPU time 1.13 seconds
Started Aug 12 06:21:54 PM PDT 24
Finished Aug 12 06:21:55 PM PDT 24
Peak memory 221136 kb
Host smart-318c749f-5f82-4799-81b0-9f07fc6aba80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303049837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3303049837
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1586978065
Short name T164
Test name
Test status
Simulation time 86544821 ps
CPU time 1.16 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 225980 kb
Host smart-6674f21e-e013-4553-8923-20a1fb24e059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586978065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1586978065
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4234645987
Short name T543
Test name
Test status
Simulation time 50383850 ps
CPU time 1.18 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 219064 kb
Host smart-f07fec16-5344-48a0-a86f-bcebd076f3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234645987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4234645987
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1892027047
Short name T137
Test name
Test status
Simulation time 45286401 ps
CPU time 1.3 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:48 PM PDT 24
Peak memory 219052 kb
Host smart-37aeb953-944f-4cd7-b1d9-3d3edf62b735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892027047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1892027047
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2383456118
Short name T190
Test name
Test status
Simulation time 30308260 ps
CPU time 0.95 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 215584 kb
Host smart-63f79f8d-2e74-4f63-b015-f95c7f2aee5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383456118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2383456118
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1847310574
Short name T643
Test name
Test status
Simulation time 196122126 ps
CPU time 1.09 seconds
Started Aug 12 06:21:51 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 217856 kb
Host smart-73829839-6637-42a2-8c62-100bfb9d9c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847310574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1847310574
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1089458168
Short name T810
Test name
Test status
Simulation time 29900320 ps
CPU time 1.2 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 219796 kb
Host smart-4d8e4428-2dc9-480f-840b-06586a3198c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089458168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1089458168
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.1141166338
Short name T198
Test name
Test status
Simulation time 31093876 ps
CPU time 0.86 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 218952 kb
Host smart-4e37f952-c930-4490-a16d-1be3e56c96a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141166338 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1141166338
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.762649872
Short name T539
Test name
Test status
Simulation time 63780320 ps
CPU time 1.57 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 217768 kb
Host smart-c1f11f3c-7543-4fc0-929a-e62ab7c1774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762649872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.762649872
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.101477269
Short name T315
Test name
Test status
Simulation time 102326194 ps
CPU time 1.27 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 216080 kb
Host smart-49eadc25-89e7-49ec-b247-3896f7c1eef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101477269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.101477269
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.3698495551
Short name T472
Test name
Test status
Simulation time 18318439 ps
CPU time 1.06 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:47 PM PDT 24
Peak memory 219388 kb
Host smart-9b23d353-3082-4eef-8fc6-57382ed0159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698495551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3698495551
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2366995939
Short name T416
Test name
Test status
Simulation time 40354229 ps
CPU time 1.42 seconds
Started Aug 12 06:21:52 PM PDT 24
Finished Aug 12 06:21:53 PM PDT 24
Peak memory 219140 kb
Host smart-0c3cc536-4d7b-4597-8e18-8d9bea16fa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366995939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2366995939
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.811536875
Short name T502
Test name
Test status
Simulation time 299305646 ps
CPU time 1.38 seconds
Started Aug 12 06:21:51 PM PDT 24
Finished Aug 12 06:21:53 PM PDT 24
Peak memory 220552 kb
Host smart-a6f5b4de-1723-4b93-b9b7-f3a94b2f7252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811536875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.811536875
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_genbits.2180418641
Short name T370
Test name
Test status
Simulation time 33219330 ps
CPU time 1.03 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 217848 kb
Host smart-cd08497c-c967-4c21-b92b-9fccbd783dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180418641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2180418641
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3593595929
Short name T574
Test name
Test status
Simulation time 38103871 ps
CPU time 1.15 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 219060 kb
Host smart-782c6c35-0515-41d4-be36-bdc7801a2da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593595929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3593595929
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.4019743631
Short name T202
Test name
Test status
Simulation time 31503140 ps
CPU time 0.89 seconds
Started Aug 12 06:22:07 PM PDT 24
Finished Aug 12 06:22:08 PM PDT 24
Peak memory 220008 kb
Host smart-209caa43-804e-4770-8529-bbc1e928716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019743631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.4019743631
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2945875436
Short name T659
Test name
Test status
Simulation time 47428818 ps
CPU time 1.43 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:48 PM PDT 24
Peak memory 218740 kb
Host smart-4ee0c2f1-7749-4527-9a72-3ccca1dbdcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945875436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2945875436
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3117160214
Short name T581
Test name
Test status
Simulation time 54521329 ps
CPU time 1.27 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 221016 kb
Host smart-46d264d0-af7b-4a52-9c98-7d711d337510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117160214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3117160214
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.2723857174
Short name T379
Test name
Test status
Simulation time 19328651 ps
CPU time 1.05 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 218980 kb
Host smart-7370690a-3600-4efa-8437-eb0920dd4895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723857174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2723857174
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2587523143
Short name T97
Test name
Test status
Simulation time 36308284 ps
CPU time 1.35 seconds
Started Aug 12 06:22:01 PM PDT 24
Finished Aug 12 06:22:03 PM PDT 24
Peak memory 217820 kb
Host smart-e34ae8c6-ed56-488d-a78b-c9fc4a07e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587523143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2587523143
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1976269529
Short name T870
Test name
Test status
Simulation time 24906691 ps
CPU time 1.22 seconds
Started Aug 12 06:21:47 PM PDT 24
Finished Aug 12 06:21:48 PM PDT 24
Peak memory 220372 kb
Host smart-a9d406ac-a6d7-4ba6-9f21-3110c85392bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976269529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1976269529
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2925416144
Short name T705
Test name
Test status
Simulation time 25809236 ps
CPU time 0.95 seconds
Started Aug 12 06:22:01 PM PDT 24
Finished Aug 12 06:22:02 PM PDT 24
Peak memory 220456 kb
Host smart-81cf437d-ebad-4370-ba36-20b3794c98c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925416144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2925416144
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3696977619
Short name T762
Test name
Test status
Simulation time 56182407 ps
CPU time 1.19 seconds
Started Aug 12 06:21:56 PM PDT 24
Finished Aug 12 06:21:57 PM PDT 24
Peak memory 218896 kb
Host smart-31031b71-38c9-452f-99f9-168edbf506dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696977619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3696977619
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.993585214
Short name T918
Test name
Test status
Simulation time 95347182 ps
CPU time 1.29 seconds
Started Aug 12 06:21:51 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 216040 kb
Host smart-f6f36796-eda5-41f2-81c5-46b7ca78f1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993585214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.993585214
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2498962671
Short name T523
Test name
Test status
Simulation time 19129708 ps
CPU time 1.14 seconds
Started Aug 12 06:22:09 PM PDT 24
Finished Aug 12 06:22:10 PM PDT 24
Peak memory 219336 kb
Host smart-f1132918-d4b7-4bb7-8f3c-b264d98520ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498962671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2498962671
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2670134273
Short name T537
Test name
Test status
Simulation time 409530645 ps
CPU time 4.47 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:54 PM PDT 24
Peak memory 220580 kb
Host smart-b0c16355-7107-4eec-afa2-ae47091b8c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670134273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2670134273
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1027232486
Short name T733
Test name
Test status
Simulation time 62857223 ps
CPU time 1.1 seconds
Started Aug 12 06:20:42 PM PDT 24
Finished Aug 12 06:20:43 PM PDT 24
Peak memory 220784 kb
Host smart-306a7e39-cf52-48c0-9e7a-5061e147a5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027232486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1027232486
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3970405654
Short name T799
Test name
Test status
Simulation time 47800442 ps
CPU time 0.9 seconds
Started Aug 12 06:20:48 PM PDT 24
Finished Aug 12 06:20:49 PM PDT 24
Peak memory 215644 kb
Host smart-69342b44-efdd-44ca-95cf-bef4bc0bee03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970405654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3970405654
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2455211071
Short name T409
Test name
Test status
Simulation time 52425194 ps
CPU time 0.88 seconds
Started Aug 12 06:20:46 PM PDT 24
Finished Aug 12 06:20:47 PM PDT 24
Peak memory 216556 kb
Host smart-00cb556c-e8ad-4b7b-9d5d-ec68ec79926b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455211071 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2455211071
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2816483769
Short name T962
Test name
Test status
Simulation time 182570824 ps
CPU time 1.02 seconds
Started Aug 12 06:20:40 PM PDT 24
Finished Aug 12 06:20:41 PM PDT 24
Peak memory 220132 kb
Host smart-95ace601-72e9-4b50-b7d9-bac98b23c302
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816483769 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2816483769
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.351515352
Short name T123
Test name
Test status
Simulation time 36534438 ps
CPU time 1.04 seconds
Started Aug 12 06:20:42 PM PDT 24
Finished Aug 12 06:20:43 PM PDT 24
Peak memory 220272 kb
Host smart-c1854d67-bdeb-4ba0-86d8-f04a640f979e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351515352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.351515352
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.952293503
Short name T423
Test name
Test status
Simulation time 281685869 ps
CPU time 4.07 seconds
Started Aug 12 06:20:44 PM PDT 24
Finished Aug 12 06:20:48 PM PDT 24
Peak memory 220548 kb
Host smart-1070d3d9-2012-46c8-a291-351340df8d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952293503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.952293503
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3105866838
Short name T721
Test name
Test status
Simulation time 20811445 ps
CPU time 1.12 seconds
Started Aug 12 06:20:42 PM PDT 24
Finished Aug 12 06:20:43 PM PDT 24
Peak memory 215780 kb
Host smart-4eb823b2-faad-464f-8c59-9acd9151d77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105866838 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3105866838
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3786521189
Short name T784
Test name
Test status
Simulation time 47691403 ps
CPU time 0.93 seconds
Started Aug 12 06:20:47 PM PDT 24
Finished Aug 12 06:20:48 PM PDT 24
Peak memory 207440 kb
Host smart-cd9588bd-4167-4b37-b283-9057a8ec13b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786521189 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3786521189
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1253354940
Short name T808
Test name
Test status
Simulation time 29467192 ps
CPU time 0.99 seconds
Started Aug 12 06:20:43 PM PDT 24
Finished Aug 12 06:20:44 PM PDT 24
Peak memory 215648 kb
Host smart-4917573e-0d2b-4747-823d-63279cefb62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253354940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1253354940
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1591377794
Short name T889
Test name
Test status
Simulation time 399940435 ps
CPU time 4.17 seconds
Started Aug 12 06:20:42 PM PDT 24
Finished Aug 12 06:20:46 PM PDT 24
Peak memory 219096 kb
Host smart-53cda10c-2fd4-478f-8fc9-244af71de51f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591377794 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1591377794
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_alert.3708680584
Short name T316
Test name
Test status
Simulation time 40331312 ps
CPU time 1.14 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 220364 kb
Host smart-e163c637-65be-40d0-9b0a-0c9b6da55ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708680584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.3708680584
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.2514845469
Short name T172
Test name
Test status
Simulation time 30392821 ps
CPU time 0.9 seconds
Started Aug 12 06:21:47 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 217992 kb
Host smart-dc02f353-830e-46bb-bc07-1a1e41aba536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514845469 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2514845469
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3346825791
Short name T633
Test name
Test status
Simulation time 32759309 ps
CPU time 1.3 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 215676 kb
Host smart-ba619cef-2312-49b3-a13e-46e46d6d4b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346825791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3346825791
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.996725432
Short name T580
Test name
Test status
Simulation time 22808123 ps
CPU time 1.12 seconds
Started Aug 12 06:21:46 PM PDT 24
Finished Aug 12 06:21:48 PM PDT 24
Peak memory 219068 kb
Host smart-d4923295-2b7b-43b4-b5c0-ae222ce3e91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996725432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.996725432
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.3143147311
Short name T16
Test name
Test status
Simulation time 22329540 ps
CPU time 0.98 seconds
Started Aug 12 06:21:45 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 224356 kb
Host smart-611fc51a-688b-4c89-9ca8-0d66e2d1123a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143147311 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3143147311
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2077825028
Short name T109
Test name
Test status
Simulation time 72443775 ps
CPU time 1.09 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 216792 kb
Host smart-da021322-fdfd-4436-95b2-b372245f644d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077825028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2077825028
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.199569163
Short name T292
Test name
Test status
Simulation time 93277569 ps
CPU time 1.21 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 220616 kb
Host smart-fdf72451-1a0a-43fb-a429-def0660e5d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199569163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.199569163
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1755417451
Short name T220
Test name
Test status
Simulation time 48481924 ps
CPU time 1.01 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 220644 kb
Host smart-d3be9cfb-a463-4263-af39-fdde3841e497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755417451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1755417451
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1195787927
Short name T578
Test name
Test status
Simulation time 156744628 ps
CPU time 2.83 seconds
Started Aug 12 06:21:44 PM PDT 24
Finished Aug 12 06:21:47 PM PDT 24
Peak memory 218000 kb
Host smart-0f9f400d-e8a3-4fd0-b21c-b62643f895ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195787927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1195787927
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.1616712900
Short name T159
Test name
Test status
Simulation time 42435736 ps
CPU time 1.49 seconds
Started Aug 12 06:21:47 PM PDT 24
Finished Aug 12 06:21:49 PM PDT 24
Peak memory 216020 kb
Host smart-71631ff2-37be-4a50-8b95-d732f3a0b311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616712900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.1616712900
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.3077775866
Short name T204
Test name
Test status
Simulation time 20111262 ps
CPU time 1.06 seconds
Started Aug 12 06:21:52 PM PDT 24
Finished Aug 12 06:21:53 PM PDT 24
Peak memory 220152 kb
Host smart-406436f5-c42a-416d-8c42-0b2edaaf458c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077775866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3077775866
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/64.edn_alert.377593890
Short name T498
Test name
Test status
Simulation time 27481884 ps
CPU time 1.28 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 219224 kb
Host smart-9b69d4fc-0eaf-4bc2-bcac-054e5ea5f878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377593890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.377593890
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1698400872
Short name T483
Test name
Test status
Simulation time 33233507 ps
CPU time 0.89 seconds
Started Aug 12 06:22:00 PM PDT 24
Finished Aug 12 06:22:01 PM PDT 24
Peak memory 219092 kb
Host smart-1116b4b0-b959-464e-bd79-ae6a07a91173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698400872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1698400872
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1060129924
Short name T707
Test name
Test status
Simulation time 65775152 ps
CPU time 1.17 seconds
Started Aug 12 06:21:58 PM PDT 24
Finished Aug 12 06:22:00 PM PDT 24
Peak memory 217856 kb
Host smart-3273ef4c-5d7b-412d-8eaa-75d29238901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060129924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1060129924
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3079620520
Short name T491
Test name
Test status
Simulation time 113846372 ps
CPU time 1.34 seconds
Started Aug 12 06:22:10 PM PDT 24
Finished Aug 12 06:22:11 PM PDT 24
Peak memory 220184 kb
Host smart-43eff621-b878-47cd-a608-a9a07d45022c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079620520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3079620520
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.3779391509
Short name T376
Test name
Test status
Simulation time 35936293 ps
CPU time 0.91 seconds
Started Aug 12 06:22:06 PM PDT 24
Finished Aug 12 06:22:07 PM PDT 24
Peak memory 219228 kb
Host smart-76f87c40-f5e9-46c5-8875-fe657c8b73d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779391509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3779391509
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3606379530
Short name T67
Test name
Test status
Simulation time 53731998 ps
CPU time 1.04 seconds
Started Aug 12 06:21:54 PM PDT 24
Finished Aug 12 06:21:55 PM PDT 24
Peak memory 219148 kb
Host smart-801e1b59-0ebb-46b1-929c-1c87c8dc9597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606379530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3606379530
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.4133057234
Short name T635
Test name
Test status
Simulation time 89094396 ps
CPU time 1.26 seconds
Started Aug 12 06:22:07 PM PDT 24
Finished Aug 12 06:22:08 PM PDT 24
Peak memory 220216 kb
Host smart-02c1e8c3-f5a8-49ca-bb89-1006d5b65088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133057234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.4133057234
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2029804513
Short name T62
Test name
Test status
Simulation time 18833771 ps
CPU time 1.13 seconds
Started Aug 12 06:21:58 PM PDT 24
Finished Aug 12 06:21:59 PM PDT 24
Peak memory 224280 kb
Host smart-0c94d347-d1a8-4664-830e-250c19c49e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029804513 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2029804513
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2508337459
Short name T332
Test name
Test status
Simulation time 32118820 ps
CPU time 1.23 seconds
Started Aug 12 06:21:58 PM PDT 24
Finished Aug 12 06:21:59 PM PDT 24
Peak memory 217776 kb
Host smart-2e1e2436-622a-498a-98b3-592367f8440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508337459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2508337459
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.246098012
Short name T535
Test name
Test status
Simulation time 95066962 ps
CPU time 1.11 seconds
Started Aug 12 06:21:51 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 219204 kb
Host smart-f90dd057-8ac8-41f4-818a-d16429c7a34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246098012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.246098012
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3595939654
Short name T685
Test name
Test status
Simulation time 69330889 ps
CPU time 1.12 seconds
Started Aug 12 06:21:57 PM PDT 24
Finished Aug 12 06:21:58 PM PDT 24
Peak memory 225844 kb
Host smart-1793fe89-ecdb-47f2-a1c2-1409b627bffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595939654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3595939654
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1966341434
Short name T834
Test name
Test status
Simulation time 142018472 ps
CPU time 1.44 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:51 PM PDT 24
Peak memory 218980 kb
Host smart-25dd5d0d-2720-46c6-ba25-4e12a370aac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966341434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1966341434
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.3815958932
Short name T964
Test name
Test status
Simulation time 197783141 ps
CPU time 1.23 seconds
Started Aug 12 06:21:51 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 219828 kb
Host smart-1b8f8a57-0845-4659-b073-a414b4ab1a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815958932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3815958932
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.3392400197
Short name T364
Test name
Test status
Simulation time 26605628 ps
CPU time 0.93 seconds
Started Aug 12 06:22:05 PM PDT 24
Finished Aug 12 06:22:06 PM PDT 24
Peak memory 219312 kb
Host smart-6f5b7fb8-9821-42d7-985e-d4d03893190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392400197 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3392400197
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3580466018
Short name T378
Test name
Test status
Simulation time 273865368 ps
CPU time 3.61 seconds
Started Aug 12 06:21:48 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 219272 kb
Host smart-7076909f-981d-40f3-8c8a-4d382222fc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580466018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3580466018
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3014928401
Short name T381
Test name
Test status
Simulation time 22507867 ps
CPU time 1.13 seconds
Started Aug 12 06:21:58 PM PDT 24
Finished Aug 12 06:21:59 PM PDT 24
Peak memory 220324 kb
Host smart-bac9301d-7010-4aaa-84f3-bfe579576db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014928401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3014928401
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.4137470641
Short name T864
Test name
Test status
Simulation time 19206194 ps
CPU time 1.07 seconds
Started Aug 12 06:22:11 PM PDT 24
Finished Aug 12 06:22:12 PM PDT 24
Peak memory 219168 kb
Host smart-1c784171-60e8-48d8-be4e-b07d4d3f1f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137470641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.4137470641
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4040069138
Short name T955
Test name
Test status
Simulation time 58247554 ps
CPU time 1.46 seconds
Started Aug 12 06:21:51 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 220672 kb
Host smart-f94f5e4c-60fb-45fc-9d33-2c0b1c93f2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040069138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4040069138
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3566853081
Short name T227
Test name
Test status
Simulation time 44138924 ps
CPU time 1.14 seconds
Started Aug 12 06:20:43 PM PDT 24
Finished Aug 12 06:20:44 PM PDT 24
Peak memory 220228 kb
Host smart-e2326c46-49c2-4fab-b1c3-cf41a58a6537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566853081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3566853081
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3336292640
Short name T245
Test name
Test status
Simulation time 50196863 ps
CPU time 0.94 seconds
Started Aug 12 06:20:43 PM PDT 24
Finished Aug 12 06:20:44 PM PDT 24
Peak memory 215576 kb
Host smart-94e73813-f22f-4f31-8fc4-ecbb806cbf72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336292640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3336292640
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2320505708
Short name T825
Test name
Test status
Simulation time 20652236 ps
CPU time 0.84 seconds
Started Aug 12 06:20:45 PM PDT 24
Finished Aug 12 06:20:46 PM PDT 24
Peak memory 215804 kb
Host smart-05097dd3-6d91-47a9-84ff-47ecb4d1a414
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320505708 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2320505708
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1134832179
Short name T817
Test name
Test status
Simulation time 27505556 ps
CPU time 1.16 seconds
Started Aug 12 06:20:46 PM PDT 24
Finished Aug 12 06:20:52 PM PDT 24
Peak memory 217592 kb
Host smart-7f57f6e2-24e8-45f6-a9cf-929f024594cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134832179 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1134832179
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3105882229
Short name T200
Test name
Test status
Simulation time 19348160 ps
CPU time 1.12 seconds
Started Aug 12 06:20:47 PM PDT 24
Finished Aug 12 06:20:49 PM PDT 24
Peak memory 219196 kb
Host smart-c2d70579-b446-4bdd-acbd-ffe9a139ec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105882229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3105882229
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3536845501
Short name T671
Test name
Test status
Simulation time 30020878 ps
CPU time 1.28 seconds
Started Aug 12 06:20:42 PM PDT 24
Finished Aug 12 06:20:43 PM PDT 24
Peak memory 218908 kb
Host smart-eaeddcfc-fb04-4636-820d-8280ecce158d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536845501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3536845501
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3777040543
Short name T399
Test name
Test status
Simulation time 25634837 ps
CPU time 0.97 seconds
Started Aug 12 06:20:47 PM PDT 24
Finished Aug 12 06:20:49 PM PDT 24
Peak memory 215812 kb
Host smart-59d6df89-cc23-464f-86e6-46ed60378f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777040543 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3777040543
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1159016288
Short name T938
Test name
Test status
Simulation time 126577544 ps
CPU time 0.91 seconds
Started Aug 12 06:20:49 PM PDT 24
Finished Aug 12 06:20:50 PM PDT 24
Peak memory 207484 kb
Host smart-27185628-c0d1-4a8d-b430-a33941c60cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159016288 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1159016288
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3811735091
Short name T841
Test name
Test status
Simulation time 28774655 ps
CPU time 0.94 seconds
Started Aug 12 06:20:44 PM PDT 24
Finished Aug 12 06:20:45 PM PDT 24
Peak memory 215668 kb
Host smart-e019593e-c8c3-433f-9bff-1c6f2ea7a33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811735091 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3811735091
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3288153871
Short name T887
Test name
Test status
Simulation time 834608884 ps
CPU time 4.65 seconds
Started Aug 12 06:20:43 PM PDT 24
Finished Aug 12 06:20:48 PM PDT 24
Peak memory 215696 kb
Host smart-a4e4b192-a31e-4b32-8702-b883e002655d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288153871 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3288153871
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/70.edn_alert.1422239394
Short name T681
Test name
Test status
Simulation time 27812590 ps
CPU time 1.31 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 220984 kb
Host smart-bd843a37-b55b-4cf3-a008-5850491d86df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422239394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1422239394
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.384902701
Short name T856
Test name
Test status
Simulation time 20920844 ps
CPU time 0.96 seconds
Started Aug 12 06:21:52 PM PDT 24
Finished Aug 12 06:21:53 PM PDT 24
Peak memory 224336 kb
Host smart-c6b63caf-827b-4293-b075-923be0e30516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384902701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.384902701
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2387770576
Short name T401
Test name
Test status
Simulation time 79243999 ps
CPU time 1.4 seconds
Started Aug 12 06:22:05 PM PDT 24
Finished Aug 12 06:22:06 PM PDT 24
Peak memory 219240 kb
Host smart-f3785d10-0d23-46af-9113-3452f5ccab9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387770576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2387770576
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2455451669
Short name T818
Test name
Test status
Simulation time 74766025 ps
CPU time 1.18 seconds
Started Aug 12 06:21:57 PM PDT 24
Finished Aug 12 06:21:58 PM PDT 24
Peak memory 220140 kb
Host smart-2a9dae19-71a0-4afe-a3fb-d4721048eaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455451669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2455451669
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.945403904
Short name T714
Test name
Test status
Simulation time 32478233 ps
CPU time 1.07 seconds
Started Aug 12 06:21:56 PM PDT 24
Finished Aug 12 06:21:58 PM PDT 24
Peak memory 221296 kb
Host smart-c0f05970-ad6b-419f-a93f-8fc145eb97a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945403904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.945403904
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.11517476
Short name T250
Test name
Test status
Simulation time 56537029 ps
CPU time 1.22 seconds
Started Aug 12 06:21:53 PM PDT 24
Finished Aug 12 06:21:54 PM PDT 24
Peak memory 219216 kb
Host smart-c9ffba74-a6ef-4e56-b1c6-0ef201491858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11517476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.11517476
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.2258917115
Short name T131
Test name
Test status
Simulation time 181317807 ps
CPU time 1.15 seconds
Started Aug 12 06:22:07 PM PDT 24
Finished Aug 12 06:22:08 PM PDT 24
Peak memory 219028 kb
Host smart-a4919f80-8a93-4d29-a577-3aeaacaf0575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258917115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.2258917115
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3338411722
Short name T153
Test name
Test status
Simulation time 26003276 ps
CPU time 1.23 seconds
Started Aug 12 06:21:52 PM PDT 24
Finished Aug 12 06:21:54 PM PDT 24
Peak memory 230096 kb
Host smart-127790e2-ec7f-4bbd-8db3-53e9a05e300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338411722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3338411722
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1862287400
Short name T335
Test name
Test status
Simulation time 64300893 ps
CPU time 1.08 seconds
Started Aug 12 06:22:09 PM PDT 24
Finished Aug 12 06:22:11 PM PDT 24
Peak memory 220184 kb
Host smart-6a4916d0-787b-40a5-a7a2-a4660b67ce73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862287400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1862287400
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3049737071
Short name T583
Test name
Test status
Simulation time 79242543 ps
CPU time 1.16 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 219040 kb
Host smart-8bd953a3-58bc-4cb7-9af3-1b3ffc060fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049737071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3049737071
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2012722654
Short name T162
Test name
Test status
Simulation time 30131362 ps
CPU time 0.94 seconds
Started Aug 12 06:21:49 PM PDT 24
Finished Aug 12 06:21:50 PM PDT 24
Peak memory 218992 kb
Host smart-060fdcdb-c641-4742-ae6e-f83369efaa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012722654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2012722654
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1899505484
Short name T827
Test name
Test status
Simulation time 41162226 ps
CPU time 1.57 seconds
Started Aug 12 06:21:50 PM PDT 24
Finished Aug 12 06:21:52 PM PDT 24
Peak memory 218916 kb
Host smart-9b74b9c6-1b79-4795-b533-d1a0d281d8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899505484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1899505484
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.3314280989
Short name T312
Test name
Test status
Simulation time 74929790 ps
CPU time 1.13 seconds
Started Aug 12 06:22:02 PM PDT 24
Finished Aug 12 06:22:03 PM PDT 24
Peak memory 219884 kb
Host smart-d3cbe741-b473-407f-9567-f38bf454f97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314280989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.3314280989
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.433545581
Short name T169
Test name
Test status
Simulation time 19139806 ps
CPU time 1.07 seconds
Started Aug 12 06:21:52 PM PDT 24
Finished Aug 12 06:21:53 PM PDT 24
Peak memory 219112 kb
Host smart-97296522-10f0-4015-aa79-7f4f3dd67de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433545581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.433545581
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3217760491
Short name T406
Test name
Test status
Simulation time 49536677 ps
CPU time 1.22 seconds
Started Aug 12 06:21:56 PM PDT 24
Finished Aug 12 06:21:57 PM PDT 24
Peak memory 218928 kb
Host smart-bb26c414-ab9b-433a-9694-a9e63c9ac853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217760491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3217760491
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.3333032719
Short name T966
Test name
Test status
Simulation time 82962978 ps
CPU time 1.15 seconds
Started Aug 12 06:21:59 PM PDT 24
Finished Aug 12 06:22:00 PM PDT 24
Peak memory 221808 kb
Host smart-5c4140b4-85c1-4013-8894-9feef30839a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333032719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.3333032719
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.581514861
Short name T862
Test name
Test status
Simulation time 19018945 ps
CPU time 1.22 seconds
Started Aug 12 06:22:11 PM PDT 24
Finished Aug 12 06:22:12 PM PDT 24
Peak memory 224320 kb
Host smart-05b329ee-9383-497b-b787-db7b02103427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581514861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.581514861
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2815757685
Short name T895
Test name
Test status
Simulation time 32296323 ps
CPU time 1.29 seconds
Started Aug 12 06:22:13 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 217772 kb
Host smart-ddb7b116-a216-4d8d-9530-d20132465485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815757685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2815757685
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.3176066727
Short name T174
Test name
Test status
Simulation time 26366114 ps
CPU time 1.16 seconds
Started Aug 12 06:21:55 PM PDT 24
Finished Aug 12 06:21:56 PM PDT 24
Peak memory 220096 kb
Host smart-6a2da6b8-82bd-4b99-842d-c8a127cf754a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176066727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3176066727
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.1568579831
Short name T175
Test name
Test status
Simulation time 30085407 ps
CPU time 1 seconds
Started Aug 12 06:22:06 PM PDT 24
Finished Aug 12 06:22:07 PM PDT 24
Peak memory 224176 kb
Host smart-a89c267f-0447-44ca-bc0f-70372f84f713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568579831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1568579831
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2458389681
Short name T475
Test name
Test status
Simulation time 85584379 ps
CPU time 1.25 seconds
Started Aug 12 06:22:10 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 219304 kb
Host smart-cd532725-ff72-4479-8b71-45cc0d7c07fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458389681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2458389681
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2372787052
Short name T140
Test name
Test status
Simulation time 28891161 ps
CPU time 1.35 seconds
Started Aug 12 06:22:09 PM PDT 24
Finished Aug 12 06:22:10 PM PDT 24
Peak memory 219856 kb
Host smart-8f21f396-5644-4267-b062-ef1ddbf4faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372787052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2372787052
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3283332323
Short name T745
Test name
Test status
Simulation time 38566766 ps
CPU time 1.16 seconds
Started Aug 12 06:22:09 PM PDT 24
Finished Aug 12 06:22:10 PM PDT 24
Peak memory 220408 kb
Host smart-1165c27f-1950-4adf-802c-74c6efaa6381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283332323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3283332323
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2289383768
Short name T660
Test name
Test status
Simulation time 101574688 ps
CPU time 1.35 seconds
Started Aug 12 06:22:09 PM PDT 24
Finished Aug 12 06:22:11 PM PDT 24
Peak memory 220128 kb
Host smart-5476dd01-65a5-40b4-9372-6476644635d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289383768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2289383768
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.1536216837
Short name T967
Test name
Test status
Simulation time 66326119 ps
CPU time 1.17 seconds
Started Aug 12 06:22:18 PM PDT 24
Finished Aug 12 06:22:19 PM PDT 24
Peak memory 219440 kb
Host smart-228ac1b3-7cca-440a-84ce-4dfb8bea9d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536216837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1536216837
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2419631676
Short name T154
Test name
Test status
Simulation time 26966873 ps
CPU time 1.22 seconds
Started Aug 12 06:22:09 PM PDT 24
Finished Aug 12 06:22:10 PM PDT 24
Peak memory 221384 kb
Host smart-ed08afd5-e274-4062-8d16-735b9b9fc51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419631676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2419631676
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.562436558
Short name T450
Test name
Test status
Simulation time 70745322 ps
CPU time 1.68 seconds
Started Aug 12 06:22:05 PM PDT 24
Finished Aug 12 06:22:07 PM PDT 24
Peak memory 219008 kb
Host smart-f5123cb9-6b4a-4a29-a8c2-e1948594a3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562436558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.562436558
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.73489462
Short name T846
Test name
Test status
Simulation time 107782345 ps
CPU time 1.29 seconds
Started Aug 12 06:22:08 PM PDT 24
Finished Aug 12 06:22:10 PM PDT 24
Peak memory 220200 kb
Host smart-6da5712e-b35b-4ec0-a5dd-93d494d9fc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73489462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.73489462
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.4026177976
Short name T186
Test name
Test status
Simulation time 22321062 ps
CPU time 0.92 seconds
Started Aug 12 06:22:21 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 219248 kb
Host smart-f02a3227-f4e7-440f-b415-fd025657b88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026177976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.4026177976
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1592737645
Short name T336
Test name
Test status
Simulation time 86412847 ps
CPU time 1.42 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 217912 kb
Host smart-39e8ae33-4d0f-45a4-a0e5-4ead9e31fa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592737645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1592737645
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1661570461
Short name T106
Test name
Test status
Simulation time 139466432 ps
CPU time 1.16 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:57 PM PDT 24
Peak memory 216040 kb
Host smart-2bb5151b-bce4-4532-8d2a-24413a0defdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661570461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1661570461
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1857464460
Short name T598
Test name
Test status
Simulation time 15502209 ps
CPU time 0.96 seconds
Started Aug 12 06:20:45 PM PDT 24
Finished Aug 12 06:20:46 PM PDT 24
Peak memory 207204 kb
Host smart-6ac013a9-8bb7-4460-895d-8a6526b76745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857464460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1857464460
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3294641939
Short name T225
Test name
Test status
Simulation time 116555391 ps
CPU time 1.16 seconds
Started Aug 12 06:20:47 PM PDT 24
Finished Aug 12 06:20:48 PM PDT 24
Peak memory 220180 kb
Host smart-d1d33690-aeaa-456f-8843-5b937c947ef0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294641939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3294641939
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3755701557
Short name T696
Test name
Test status
Simulation time 60017039 ps
CPU time 0.79 seconds
Started Aug 12 06:20:50 PM PDT 24
Finished Aug 12 06:20:51 PM PDT 24
Peak memory 218900 kb
Host smart-cfa62c64-36fd-4c9e-ac1b-beae588c4369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755701557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3755701557
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1593143934
Short name T553
Test name
Test status
Simulation time 320182853 ps
CPU time 1.17 seconds
Started Aug 12 06:20:44 PM PDT 24
Finished Aug 12 06:20:45 PM PDT 24
Peak memory 217692 kb
Host smart-3f6a508f-52cd-4c88-9cff-b9aafd916f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593143934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1593143934
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.405094835
Short name T15
Test name
Test status
Simulation time 29408275 ps
CPU time 1.07 seconds
Started Aug 12 06:20:41 PM PDT 24
Finished Aug 12 06:20:43 PM PDT 24
Peak memory 224408 kb
Host smart-bcf1a1a9-cf62-48d1-86f4-0956ccb253da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405094835 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.405094835
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.789692057
Short name T656
Test name
Test status
Simulation time 15674098 ps
CPU time 0.97 seconds
Started Aug 12 06:20:46 PM PDT 24
Finished Aug 12 06:20:47 PM PDT 24
Peak memory 207612 kb
Host smart-c3a4a37f-80c1-4f6b-9166-0812196af51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789692057 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.789692057
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1048492301
Short name T421
Test name
Test status
Simulation time 39275925 ps
CPU time 0.88 seconds
Started Aug 12 06:20:46 PM PDT 24
Finished Aug 12 06:20:47 PM PDT 24
Peak memory 215624 kb
Host smart-c758cac4-5374-46ad-a12b-08c2b53f7057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048492301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1048492301
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2100423877
Short name T425
Test name
Test status
Simulation time 33583271 ps
CPU time 1.23 seconds
Started Aug 12 06:20:41 PM PDT 24
Finished Aug 12 06:20:43 PM PDT 24
Peak memory 217448 kb
Host smart-1094b28a-bf24-49bc-9ced-d6f9d6e962e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100423877 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2100423877
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1244103652
Short name T459
Test name
Test status
Simulation time 5204085517 ps
CPU time 116.21 seconds
Started Aug 12 06:20:43 PM PDT 24
Finished Aug 12 06:22:39 PM PDT 24
Peak memory 217132 kb
Host smart-0478d8e4-c3ab-463e-afcc-1809acc638fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244103652 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1244103652
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.3709208331
Short name T630
Test name
Test status
Simulation time 30018569 ps
CPU time 1.31 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 219544 kb
Host smart-2b7217bc-eaf8-4f6c-9b1c-0afe7c63c8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709208331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3709208331
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3611746960
Short name T548
Test name
Test status
Simulation time 43570273 ps
CPU time 1.22 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 225952 kb
Host smart-bb8c0bc8-11c1-4cba-8ef2-f3c6b63aaf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611746960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3611746960
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2948678676
Short name T511
Test name
Test status
Simulation time 58044996 ps
CPU time 1.61 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:14 PM PDT 24
Peak memory 219040 kb
Host smart-687057fa-89e9-46a2-8156-e55e0e739fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948678676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2948678676
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2479143270
Short name T968
Test name
Test status
Simulation time 149302467 ps
CPU time 1.41 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:14 PM PDT 24
Peak memory 216044 kb
Host smart-ae864dd2-c436-4a60-bd08-0f53a18a2deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479143270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2479143270
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.806731514
Short name T902
Test name
Test status
Simulation time 18900118 ps
CPU time 1.07 seconds
Started Aug 12 06:22:04 PM PDT 24
Finished Aug 12 06:22:06 PM PDT 24
Peak memory 219140 kb
Host smart-214212b2-f721-401b-a4fe-9ed7abc1ecf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806731514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.806731514
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3586830760
Short name T355
Test name
Test status
Simulation time 87016857 ps
CPU time 1.2 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:13 PM PDT 24
Peak memory 219908 kb
Host smart-38b11048-34c4-44a2-bc7b-9fde037d346d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586830760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3586830760
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2353710439
Short name T457
Test name
Test status
Simulation time 32776982 ps
CPU time 1.42 seconds
Started Aug 12 06:22:01 PM PDT 24
Finished Aug 12 06:22:03 PM PDT 24
Peak memory 216180 kb
Host smart-107fd62d-5c57-4faf-96de-93642a955d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353710439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2353710439
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.1369500757
Short name T525
Test name
Test status
Simulation time 18865523 ps
CPU time 1.04 seconds
Started Aug 12 06:22:07 PM PDT 24
Finished Aug 12 06:22:08 PM PDT 24
Peak memory 219152 kb
Host smart-0407876c-24de-4703-ae0c-c632706ada67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369500757 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1369500757
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3505354251
Short name T948
Test name
Test status
Simulation time 54145697 ps
CPU time 1.64 seconds
Started Aug 12 06:22:06 PM PDT 24
Finished Aug 12 06:22:08 PM PDT 24
Peak memory 219056 kb
Host smart-f25c56bf-3c81-40fa-8d26-74caaff72435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505354251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3505354251
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.3978523284
Short name T1
Test name
Test status
Simulation time 33132750 ps
CPU time 1.2 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 219884 kb
Host smart-935cd5ca-1c24-4d59-99fb-a2087e83b06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978523284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.3978523284
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2009703539
Short name T108
Test name
Test status
Simulation time 21825167 ps
CPU time 0.93 seconds
Started Aug 12 06:22:11 PM PDT 24
Finished Aug 12 06:22:12 PM PDT 24
Peak memory 219124 kb
Host smart-0fb36a0d-87d8-46cf-ae55-6fc17478ab70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009703539 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2009703539
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.559049588
Short name T957
Test name
Test status
Simulation time 42125768 ps
CPU time 1.38 seconds
Started Aug 12 06:22:13 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 218832 kb
Host smart-364d98a0-07c4-42a6-b439-279cf2af7c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559049588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.559049588
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.4057712935
Short name T858
Test name
Test status
Simulation time 82212023 ps
CPU time 1.09 seconds
Started Aug 12 06:22:18 PM PDT 24
Finished Aug 12 06:22:19 PM PDT 24
Peak memory 219344 kb
Host smart-1466d5f7-455d-437e-9a53-f0f44a047257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057712935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.4057712935
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1117826302
Short name T824
Test name
Test status
Simulation time 22521859 ps
CPU time 1.21 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 224312 kb
Host smart-2e27ce83-3207-4210-98ba-f770efe1d314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117826302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1117826302
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1983840478
Short name T602
Test name
Test status
Simulation time 30252600 ps
CPU time 1.31 seconds
Started Aug 12 06:22:11 PM PDT 24
Finished Aug 12 06:22:13 PM PDT 24
Peak memory 218952 kb
Host smart-a1d08196-e620-44ad-9dec-8857404f2970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983840478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1983840478
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3522855191
Short name T739
Test name
Test status
Simulation time 28106410 ps
CPU time 1.23 seconds
Started Aug 12 06:22:17 PM PDT 24
Finished Aug 12 06:22:18 PM PDT 24
Peak memory 216088 kb
Host smart-a75959dd-e9f2-431b-a9fa-81b1ea90435b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522855191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3522855191
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1454537770
Short name T711
Test name
Test status
Simulation time 101508564 ps
CPU time 1.06 seconds
Started Aug 12 06:22:16 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 220324 kb
Host smart-ad7c0fd7-0efd-495b-896d-659c0db75e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454537770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1454537770
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3555226438
Short name T411
Test name
Test status
Simulation time 45757120 ps
CPU time 1.17 seconds
Started Aug 12 06:22:11 PM PDT 24
Finished Aug 12 06:22:12 PM PDT 24
Peak memory 217664 kb
Host smart-357e77fd-2019-4447-bf0e-e6d34ecc3e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555226438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3555226438
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.428397743
Short name T710
Test name
Test status
Simulation time 79387409 ps
CPU time 1.12 seconds
Started Aug 12 06:22:11 PM PDT 24
Finished Aug 12 06:22:12 PM PDT 24
Peak memory 230068 kb
Host smart-04b8888c-02b3-42b8-b87c-c1aeba754cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428397743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.428397743
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1808131259
Short name T341
Test name
Test status
Simulation time 57395200 ps
CPU time 1.94 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:14 PM PDT 24
Peak memory 218900 kb
Host smart-775ff200-e3be-4d76-a7ce-ad5cd9fa1ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808131259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1808131259
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1770668752
Short name T795
Test name
Test status
Simulation time 48669497 ps
CPU time 0.96 seconds
Started Aug 12 06:22:18 PM PDT 24
Finished Aug 12 06:22:19 PM PDT 24
Peak memory 220556 kb
Host smart-9cd21c8f-284d-4de2-9127-15222b47efa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770668752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1770668752
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3882118769
Short name T398
Test name
Test status
Simulation time 103953859 ps
CPU time 1.57 seconds
Started Aug 12 06:22:06 PM PDT 24
Finished Aug 12 06:22:08 PM PDT 24
Peak memory 219160 kb
Host smart-56d41b59-17ee-491b-b72f-b00f5d68f418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882118769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3882118769
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.2199771599
Short name T717
Test name
Test status
Simulation time 42005049 ps
CPU time 1.12 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 220004 kb
Host smart-a845492a-fc9e-4137-8f30-7b81ef97fbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199771599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2199771599
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.91183680
Short name T688
Test name
Test status
Simulation time 28002979 ps
CPU time 1.23 seconds
Started Aug 12 06:22:07 PM PDT 24
Finished Aug 12 06:22:13 PM PDT 24
Peak memory 221576 kb
Host smart-b5175748-1248-4496-9333-0a600147be2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91183680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.91183680
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1821859449
Short name T575
Test name
Test status
Simulation time 39271214 ps
CPU time 1.53 seconds
Started Aug 12 06:22:08 PM PDT 24
Finished Aug 12 06:22:10 PM PDT 24
Peak memory 215684 kb
Host smart-06a69b59-70f9-49ef-ada4-70c936f02864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821859449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1821859449
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2770014349
Short name T556
Test name
Test status
Simulation time 31573316 ps
CPU time 1.29 seconds
Started Aug 12 06:22:10 PM PDT 24
Finished Aug 12 06:22:11 PM PDT 24
Peak memory 221348 kb
Host smart-9263e080-721b-4817-b947-fa367dca35db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770014349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2770014349
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.996294037
Short name T122
Test name
Test status
Simulation time 53611950 ps
CPU time 0.99 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 220328 kb
Host smart-4a069c73-12c6-4afa-870b-fcb450601453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996294037 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.996294037
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3569292212
Short name T657
Test name
Test status
Simulation time 53446426 ps
CPU time 1.33 seconds
Started Aug 12 06:22:11 PM PDT 24
Finished Aug 12 06:22:12 PM PDT 24
Peak memory 217728 kb
Host smart-5440682d-bc54-4cc2-8296-86e9add6a14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569292212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3569292212
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.4119694944
Short name T942
Test name
Test status
Simulation time 31020555 ps
CPU time 1.27 seconds
Started Aug 12 06:20:47 PM PDT 24
Finished Aug 12 06:20:49 PM PDT 24
Peak memory 220344 kb
Host smart-e72bb96f-d086-4995-8d4c-ffba22ae6d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119694944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.4119694944
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.283718757
Short name T565
Test name
Test status
Simulation time 32486868 ps
CPU time 0.92 seconds
Started Aug 12 06:20:53 PM PDT 24
Finished Aug 12 06:20:54 PM PDT 24
Peak memory 207320 kb
Host smart-ce7ecf61-ee96-4083-a256-1274eaaf4e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283718757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.283718757
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.554776890
Short name T495
Test name
Test status
Simulation time 23811915 ps
CPU time 0.91 seconds
Started Aug 12 06:20:43 PM PDT 24
Finished Aug 12 06:20:44 PM PDT 24
Peak memory 216712 kb
Host smart-37dbe75e-e2c8-45d8-9be7-d3b8b74b89dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554776890 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.554776890
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2827927995
Short name T134
Test name
Test status
Simulation time 109129313 ps
CPU time 1.13 seconds
Started Aug 12 06:20:55 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 220116 kb
Host smart-3126caa9-69ca-4d63-9ae9-5816c5793cf2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827927995 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2827927995
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.4202136409
Short name T149
Test name
Test status
Simulation time 115186054 ps
CPU time 1.29 seconds
Started Aug 12 06:20:43 PM PDT 24
Finished Aug 12 06:20:44 PM PDT 24
Peak memory 226192 kb
Host smart-f33fdf8d-1b7e-4892-958e-b4eb01f8e036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202136409 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.4202136409
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2790082471
Short name T89
Test name
Test status
Simulation time 34512612 ps
CPU time 1.08 seconds
Started Aug 12 06:20:50 PM PDT 24
Finished Aug 12 06:20:52 PM PDT 24
Peak memory 219004 kb
Host smart-8ce3bb0f-5bfe-4a47-8b37-c6357bf6f0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790082471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2790082471
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1004189684
Short name T606
Test name
Test status
Simulation time 30251151 ps
CPU time 0.9 seconds
Started Aug 12 06:20:47 PM PDT 24
Finished Aug 12 06:20:48 PM PDT 24
Peak memory 215936 kb
Host smart-bab2b203-72ea-4c4b-acc2-16330dcc6a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004189684 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1004189684
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2199041796
Short name T595
Test name
Test status
Simulation time 38755785 ps
CPU time 0.91 seconds
Started Aug 12 06:20:54 PM PDT 24
Finished Aug 12 06:20:56 PM PDT 24
Peak memory 207468 kb
Host smart-25f40446-6959-47c4-a667-886bdc7523c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199041796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2199041796
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2484425515
Short name T765
Test name
Test status
Simulation time 16262111 ps
CPU time 0.98 seconds
Started Aug 12 06:20:42 PM PDT 24
Finished Aug 12 06:20:43 PM PDT 24
Peak memory 215652 kb
Host smart-2cd744c1-0525-4d83-b0c6-1bba2ba2d32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484425515 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2484425515
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1272157872
Short name T377
Test name
Test status
Simulation time 415117913 ps
CPU time 4.72 seconds
Started Aug 12 06:20:47 PM PDT 24
Finished Aug 12 06:20:52 PM PDT 24
Peak memory 217620 kb
Host smart-2c80a541-8049-4a12-8568-7be226ad4081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272157872 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1272157872
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/90.edn_alert.906159534
Short name T116
Test name
Test status
Simulation time 107822308 ps
CPU time 1.2 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:19 PM PDT 24
Peak memory 220724 kb
Host smart-7d55517c-1b2c-4639-b166-b6f36350514b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906159534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.906159534
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1344500016
Short name T132
Test name
Test status
Simulation time 20350562 ps
CPU time 1.24 seconds
Started Aug 12 06:22:18 PM PDT 24
Finished Aug 12 06:22:20 PM PDT 24
Peak memory 229920 kb
Host smart-d4f4d1d9-500c-468e-b4c5-089cc92cc9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344500016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1344500016
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3937122116
Short name T435
Test name
Test status
Simulation time 56689272 ps
CPU time 1.4 seconds
Started Aug 12 06:22:03 PM PDT 24
Finished Aug 12 06:22:04 PM PDT 24
Peak memory 220400 kb
Host smart-853ec04b-9360-4f5b-bacd-8dc393476349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937122116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3937122116
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.3252575248
Short name T774
Test name
Test status
Simulation time 135043496 ps
CPU time 1.15 seconds
Started Aug 12 06:22:13 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 220000 kb
Host smart-8950b18f-0f0a-476c-83d2-9e7d9dca7129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252575248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.3252575248
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2880891457
Short name T181
Test name
Test status
Simulation time 21665834 ps
CPU time 0.9 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:13 PM PDT 24
Peak memory 219180 kb
Host smart-e34bfd77-5123-4982-b19d-5b04032d8d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880891457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2880891457
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.688577740
Short name T780
Test name
Test status
Simulation time 389096453 ps
CPU time 2.13 seconds
Started Aug 12 06:22:13 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 220500 kb
Host smart-74acc82f-28b8-4083-84ec-7693c9e5caa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688577740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.688577740
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.3366276717
Short name T954
Test name
Test status
Simulation time 101233870 ps
CPU time 1.15 seconds
Started Aug 12 06:22:11 PM PDT 24
Finished Aug 12 06:22:12 PM PDT 24
Peak memory 220960 kb
Host smart-01d4a39f-a97a-4823-a9c8-cb16ff8b59c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366276717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.3366276717
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3914492895
Short name T7
Test name
Test status
Simulation time 36548570 ps
CPU time 1.43 seconds
Started Aug 12 06:22:13 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 220364 kb
Host smart-cb345bf0-bf85-43c6-b311-32f3c8bd6412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914492895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3914492895
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3094398979
Short name T413
Test name
Test status
Simulation time 69796077 ps
CPU time 2.53 seconds
Started Aug 12 06:22:04 PM PDT 24
Finished Aug 12 06:22:07 PM PDT 24
Peak memory 219004 kb
Host smart-ddac4db6-9744-4af5-b8c7-aa5d7d0a72bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094398979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3094398979
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2558645442
Short name T811
Test name
Test status
Simulation time 79394212 ps
CPU time 1.25 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 219380 kb
Host smart-b8c19f07-bffb-4501-b4b5-aff4a28915cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558645442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2558645442
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3558623999
Short name T182
Test name
Test status
Simulation time 18363847 ps
CPU time 1.04 seconds
Started Aug 12 06:22:19 PM PDT 24
Finished Aug 12 06:22:21 PM PDT 24
Peak memory 218880 kb
Host smart-dbacd502-79c0-4001-87fa-772b0926c6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558623999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3558623999
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1857829820
Short name T751
Test name
Test status
Simulation time 40359261 ps
CPU time 1.64 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 217704 kb
Host smart-2e5b5cb4-44aa-4330-be3b-f1dd086e65b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857829820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1857829820
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.4112379798
Short name T115
Test name
Test status
Simulation time 88187690 ps
CPU time 1.18 seconds
Started Aug 12 06:22:14 PM PDT 24
Finished Aug 12 06:22:15 PM PDT 24
Peak memory 221176 kb
Host smart-dc522858-a3f3-431b-bd20-21fe8dd17332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112379798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.4112379798
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.2591349732
Short name T145
Test name
Test status
Simulation time 20508424 ps
CPU time 1.21 seconds
Started Aug 12 06:22:11 PM PDT 24
Finished Aug 12 06:22:13 PM PDT 24
Peak memory 229968 kb
Host smart-baac4a11-97fc-497e-82bc-109ebafcff64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591349732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2591349732
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.4031912870
Short name T437
Test name
Test status
Simulation time 57752368 ps
CPU time 1.27 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:16 PM PDT 24
Peak memory 218924 kb
Host smart-7bd5db49-32a2-41bf-b112-5cd81d16494e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031912870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.4031912870
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3404583484
Short name T662
Test name
Test status
Simulation time 39725960 ps
CPU time 1.21 seconds
Started Aug 12 06:22:16 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 219180 kb
Host smart-2d8d2fde-435b-4c72-be9d-d3ba4875c6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404583484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3404583484
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.3906978496
Short name T223
Test name
Test status
Simulation time 20439299 ps
CPU time 1.22 seconds
Started Aug 12 06:22:16 PM PDT 24
Finished Aug 12 06:22:19 PM PDT 24
Peak memory 230060 kb
Host smart-bf0e595f-fb83-44fb-a84b-8c9c0f8fef7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906978496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3906978496
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2947202169
Short name T576
Test name
Test status
Simulation time 52245042 ps
CPU time 1.59 seconds
Started Aug 12 06:22:18 PM PDT 24
Finished Aug 12 06:22:20 PM PDT 24
Peak memory 218856 kb
Host smart-2c951e57-be39-46df-9192-38091f53e391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947202169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2947202169
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1177039464
Short name T674
Test name
Test status
Simulation time 28967897 ps
CPU time 1.37 seconds
Started Aug 12 06:22:09 PM PDT 24
Finished Aug 12 06:22:10 PM PDT 24
Peak memory 216008 kb
Host smart-47bdbbee-2335-4fba-b724-21401df57510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177039464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1177039464
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1359107222
Short name T359
Test name
Test status
Simulation time 19802980 ps
CPU time 1.03 seconds
Started Aug 12 06:22:18 PM PDT 24
Finished Aug 12 06:22:19 PM PDT 24
Peak memory 219040 kb
Host smart-b181500a-1dbb-438a-b8ed-b68e75c9088b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359107222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1359107222
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2810478048
Short name T570
Test name
Test status
Simulation time 37400797 ps
CPU time 1.75 seconds
Started Aug 12 06:22:20 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 220128 kb
Host smart-95ec84fc-16b0-496f-865a-f5f3fd031720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810478048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2810478048
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1466591335
Short name T141
Test name
Test status
Simulation time 95760481 ps
CPU time 1.25 seconds
Started Aug 12 06:22:21 PM PDT 24
Finished Aug 12 06:22:22 PM PDT 24
Peak memory 218800 kb
Host smart-e1d203ab-7f2b-4f05-999a-addb37473dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466591335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1466591335
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1800614629
Short name T9
Test name
Test status
Simulation time 20676505 ps
CPU time 1.07 seconds
Started Aug 12 06:22:06 PM PDT 24
Finished Aug 12 06:22:07 PM PDT 24
Peak memory 219220 kb
Host smart-4cdd5884-2b4c-432e-93ce-2276dd19843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800614629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1800614629
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1398018269
Short name T793
Test name
Test status
Simulation time 58832786 ps
CPU time 1.31 seconds
Started Aug 12 06:22:19 PM PDT 24
Finished Aug 12 06:22:21 PM PDT 24
Peak memory 217852 kb
Host smart-b35b86d2-bbe1-4323-b69e-2228abc1e844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398018269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1398018269
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2645046630
Short name T197
Test name
Test status
Simulation time 228366488 ps
CPU time 1.23 seconds
Started Aug 12 06:22:09 PM PDT 24
Finished Aug 12 06:22:11 PM PDT 24
Peak memory 220148 kb
Host smart-21408808-647a-4653-96f0-bc4cc21b5773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645046630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2645046630
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2957991771
Short name T835
Test name
Test status
Simulation time 56205008 ps
CPU time 1.12 seconds
Started Aug 12 06:22:08 PM PDT 24
Finished Aug 12 06:22:09 PM PDT 24
Peak memory 220484 kb
Host smart-752ac81b-518f-4b8f-9d0c-e1cbb47ca3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957991771 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2957991771
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1601391899
Short name T345
Test name
Test status
Simulation time 40892370 ps
CPU time 1.47 seconds
Started Aug 12 06:22:12 PM PDT 24
Finished Aug 12 06:22:14 PM PDT 24
Peak memory 219640 kb
Host smart-e4fd912f-7c25-4351-8de6-ec2b8cacd33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601391899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1601391899
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.146850287
Short name T166
Test name
Test status
Simulation time 79122014 ps
CPU time 1.18 seconds
Started Aug 12 06:22:16 PM PDT 24
Finished Aug 12 06:22:19 PM PDT 24
Peak memory 219512 kb
Host smart-a569c80e-e6d8-4e7a-b97e-7ba75fc49995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146850287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.146850287
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2795212563
Short name T588
Test name
Test status
Simulation time 27235148 ps
CPU time 1.09 seconds
Started Aug 12 06:22:15 PM PDT 24
Finished Aug 12 06:22:17 PM PDT 24
Peak memory 218992 kb
Host smart-8d8ea4dc-6758-440e-a735-2f22c7dac8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795212563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2795212563
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1714419041
Short name T969
Test name
Test status
Simulation time 269742869 ps
CPU time 2.47 seconds
Started Aug 12 06:22:10 PM PDT 24
Finished Aug 12 06:22:13 PM PDT 24
Peak memory 220116 kb
Host smart-f8c284a0-98e3-45dc-ae69-c594cbc54287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714419041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1714419041
Directory /workspace/99.edn_genbits/latest
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