Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 2 0 2 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 8 0 8 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 74024 1 T1 121 T2 23 T3 399
all_pins[1] 74024 1 T1 121 T2 23 T3 399



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 143367 1 T1 242 T2 46 T3 785
values[0x1] 4681 1 T3 13 T4 70 T41 46
transitions[0x0=>0x1] 4257 1 T3 9 T4 65 T41 43
transitions[0x1=>0x0] 4270 1 T3 9 T4 65 T41 44



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 70274 1 T1 121 T2 23 T3 395
all_pins[0] values[0x1] 3750 1 T3 4 T4 59 T41 36
all_pins[0] transitions[0x0=>0x1] 3525 1 T3 2 T4 56 T41 36
all_pins[0] transitions[0x1=>0x0] 706 1 T3 7 T4 8 T41 10
all_pins[1] values[0x0] 73093 1 T1 121 T2 23 T3 390
all_pins[1] values[0x1] 931 1 T3 9 T4 11 T41 10
all_pins[1] transitions[0x0=>0x1] 732 1 T3 7 T4 9 T41 7
all_pins[1] transitions[0x1=>0x0] 3564 1 T3 2 T4 57 T41 34

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