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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.68 98.25 93.91 97.02 91.28 96.37 99.77 93.18


Total test records in report: 1111
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T1018 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3785667271 Aug 13 06:47:57 PM PDT 24 Aug 13 06:48:00 PM PDT 24 57621462 ps
T257 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.638276929 Aug 13 06:47:54 PM PDT 24 Aug 13 06:47:56 PM PDT 24 663333004 ps
T1019 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2982880914 Aug 13 06:47:57 PM PDT 24 Aug 13 06:47:58 PM PDT 24 28396240 ps
T1020 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4132401286 Aug 13 06:48:02 PM PDT 24 Aug 13 06:48:04 PM PDT 24 96378525 ps
T258 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2472606398 Aug 13 06:48:00 PM PDT 24 Aug 13 06:48:01 PM PDT 24 19051487 ps
T290 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1784828918 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:04 PM PDT 24 131741458 ps
T1021 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2272425301 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:03 PM PDT 24 138257217 ps
T1022 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2483869676 Aug 13 06:48:06 PM PDT 24 Aug 13 06:48:07 PM PDT 24 182489624 ps
T1023 /workspace/coverage/cover_reg_top/3.edn_intr_test.1702955727 Aug 13 06:47:53 PM PDT 24 Aug 13 06:47:54 PM PDT 24 14725294 ps
T1024 /workspace/coverage/cover_reg_top/49.edn_intr_test.177691478 Aug 13 06:47:56 PM PDT 24 Aug 13 06:47:57 PM PDT 24 53821726 ps
T1025 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1324740001 Aug 13 06:48:09 PM PDT 24 Aug 13 06:48:10 PM PDT 24 25020746 ps
T1026 /workspace/coverage/cover_reg_top/29.edn_intr_test.2877397090 Aug 13 06:48:09 PM PDT 24 Aug 13 06:48:10 PM PDT 24 46990800 ps
T1027 /workspace/coverage/cover_reg_top/1.edn_intr_test.3195946302 Aug 13 06:48:10 PM PDT 24 Aug 13 06:48:11 PM PDT 24 13744969 ps
T1028 /workspace/coverage/cover_reg_top/25.edn_intr_test.943700023 Aug 13 06:48:05 PM PDT 24 Aug 13 06:48:06 PM PDT 24 34198548 ps
T1029 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3112424414 Aug 13 06:48:11 PM PDT 24 Aug 13 06:48:12 PM PDT 24 16062179 ps
T1030 /workspace/coverage/cover_reg_top/41.edn_intr_test.3048180994 Aug 13 06:48:25 PM PDT 24 Aug 13 06:48:26 PM PDT 24 20990106 ps
T1031 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3200127635 Aug 13 06:48:10 PM PDT 24 Aug 13 06:48:11 PM PDT 24 18806413 ps
T1032 /workspace/coverage/cover_reg_top/33.edn_intr_test.4193726527 Aug 13 06:48:03 PM PDT 24 Aug 13 06:48:04 PM PDT 24 49199859 ps
T1033 /workspace/coverage/cover_reg_top/48.edn_intr_test.1233881857 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:02 PM PDT 24 57682084 ps
T1034 /workspace/coverage/cover_reg_top/10.edn_intr_test.781016087 Aug 13 06:48:08 PM PDT 24 Aug 13 06:48:10 PM PDT 24 17069339 ps
T1035 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3365283199 Aug 13 06:48:07 PM PDT 24 Aug 13 06:48:10 PM PDT 24 161703459 ps
T1036 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3249459438 Aug 13 06:47:54 PM PDT 24 Aug 13 06:47:55 PM PDT 24 17152550 ps
T1037 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2475158720 Aug 13 06:48:04 PM PDT 24 Aug 13 06:48:14 PM PDT 24 830626591 ps
T1038 /workspace/coverage/cover_reg_top/4.edn_intr_test.1239575802 Aug 13 06:47:57 PM PDT 24 Aug 13 06:47:58 PM PDT 24 102775118 ps
T259 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3321624287 Aug 13 06:48:09 PM PDT 24 Aug 13 06:48:10 PM PDT 24 58380239 ps
T1039 /workspace/coverage/cover_reg_top/20.edn_intr_test.2818241730 Aug 13 06:48:04 PM PDT 24 Aug 13 06:48:05 PM PDT 24 26720542 ps
T1040 /workspace/coverage/cover_reg_top/40.edn_intr_test.1024913623 Aug 13 06:48:07 PM PDT 24 Aug 13 06:48:08 PM PDT 24 46311444 ps
T1041 /workspace/coverage/cover_reg_top/11.edn_intr_test.2863572244 Aug 13 06:48:25 PM PDT 24 Aug 13 06:48:26 PM PDT 24 29889413 ps
T1042 /workspace/coverage/cover_reg_top/6.edn_tl_errors.174985371 Aug 13 06:47:58 PM PDT 24 Aug 13 06:48:03 PM PDT 24 621400731 ps
T1043 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3797934425 Aug 13 06:47:53 PM PDT 24 Aug 13 06:47:54 PM PDT 24 92002932 ps
T1044 /workspace/coverage/cover_reg_top/35.edn_intr_test.3023938956 Aug 13 06:48:15 PM PDT 24 Aug 13 06:48:16 PM PDT 24 41748091 ps
T1045 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4206381602 Aug 13 06:47:51 PM PDT 24 Aug 13 06:47:52 PM PDT 24 29661657 ps
T288 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3693698669 Aug 13 06:48:11 PM PDT 24 Aug 13 06:48:13 PM PDT 24 160544477 ps
T1046 /workspace/coverage/cover_reg_top/2.edn_intr_test.2764925509 Aug 13 06:47:54 PM PDT 24 Aug 13 06:47:55 PM PDT 24 48611311 ps
T260 /workspace/coverage/cover_reg_top/6.edn_csr_rw.740395244 Aug 13 06:47:50 PM PDT 24 Aug 13 06:47:51 PM PDT 24 16206911 ps
T1047 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1901111666 Aug 13 06:48:16 PM PDT 24 Aug 13 06:48:21 PM PDT 24 122092427 ps
T1048 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2237659665 Aug 13 06:47:59 PM PDT 24 Aug 13 06:48:00 PM PDT 24 483424196 ps
T1049 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1546189626 Aug 13 06:48:08 PM PDT 24 Aug 13 06:48:09 PM PDT 24 59164764 ps
T1050 /workspace/coverage/cover_reg_top/34.edn_intr_test.4075476390 Aug 13 06:48:21 PM PDT 24 Aug 13 06:48:22 PM PDT 24 14947507 ps
T1051 /workspace/coverage/cover_reg_top/23.edn_intr_test.2664864316 Aug 13 06:48:17 PM PDT 24 Aug 13 06:48:18 PM PDT 24 23757615 ps
T1052 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3910429559 Aug 13 06:47:53 PM PDT 24 Aug 13 06:47:54 PM PDT 24 16452508 ps
T1053 /workspace/coverage/cover_reg_top/14.edn_intr_test.3897522243 Aug 13 06:48:08 PM PDT 24 Aug 13 06:48:09 PM PDT 24 17457743 ps
T1054 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2475944373 Aug 13 06:48:08 PM PDT 24 Aug 13 06:48:09 PM PDT 24 15547602 ps
T1055 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1684023759 Aug 13 06:47:56 PM PDT 24 Aug 13 06:47:58 PM PDT 24 25408998 ps
T1056 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2278775925 Aug 13 06:48:08 PM PDT 24 Aug 13 06:48:10 PM PDT 24 100083593 ps
T1057 /workspace/coverage/cover_reg_top/6.edn_intr_test.3661001039 Aug 13 06:48:13 PM PDT 24 Aug 13 06:48:14 PM PDT 24 14649139 ps
T1058 /workspace/coverage/cover_reg_top/13.edn_intr_test.2813888422 Aug 13 06:48:17 PM PDT 24 Aug 13 06:48:21 PM PDT 24 18065378 ps
T1059 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2959948873 Aug 13 06:48:02 PM PDT 24 Aug 13 06:48:03 PM PDT 24 34313473 ps
T1060 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3520390696 Aug 13 06:47:55 PM PDT 24 Aug 13 06:47:57 PM PDT 24 101213954 ps
T261 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2736822632 Aug 13 06:48:05 PM PDT 24 Aug 13 06:48:07 PM PDT 24 61455561 ps
T1061 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3947783679 Aug 13 06:47:52 PM PDT 24 Aug 13 06:47:54 PM PDT 24 97904585 ps
T1062 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1310315913 Aug 13 06:48:03 PM PDT 24 Aug 13 06:48:05 PM PDT 24 28989594 ps
T1063 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2772197136 Aug 13 06:47:51 PM PDT 24 Aug 13 06:47:52 PM PDT 24 22090659 ps
T1064 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2738762651 Aug 13 06:47:54 PM PDT 24 Aug 13 06:47:55 PM PDT 24 24411038 ps
T1065 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2810727160 Aug 13 06:48:04 PM PDT 24 Aug 13 06:48:06 PM PDT 24 50182668 ps
T289 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.182986089 Aug 13 06:48:06 PM PDT 24 Aug 13 06:48:09 PM PDT 24 168975223 ps
T1066 /workspace/coverage/cover_reg_top/31.edn_intr_test.2509091744 Aug 13 06:48:14 PM PDT 24 Aug 13 06:48:15 PM PDT 24 154745936 ps
T1067 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3237780210 Aug 13 06:47:57 PM PDT 24 Aug 13 06:47:58 PM PDT 24 53930513 ps
T1068 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1004805099 Aug 13 06:48:04 PM PDT 24 Aug 13 06:48:06 PM PDT 24 142045016 ps
T1069 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.866511369 Aug 13 06:48:06 PM PDT 24 Aug 13 06:48:08 PM PDT 24 27524714 ps
T265 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1488613395 Aug 13 06:47:55 PM PDT 24 Aug 13 06:47:58 PM PDT 24 60059541 ps
T1070 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1896503174 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:04 PM PDT 24 114175767 ps
T1071 /workspace/coverage/cover_reg_top/21.edn_intr_test.2939258378 Aug 13 06:48:14 PM PDT 24 Aug 13 06:48:15 PM PDT 24 12744946 ps
T1072 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2643569272 Aug 13 06:48:06 PM PDT 24 Aug 13 06:48:08 PM PDT 24 124418550 ps
T1073 /workspace/coverage/cover_reg_top/46.edn_intr_test.2080765687 Aug 13 06:48:29 PM PDT 24 Aug 13 06:48:30 PM PDT 24 47459416 ps
T1074 /workspace/coverage/cover_reg_top/42.edn_intr_test.880692890 Aug 13 06:48:02 PM PDT 24 Aug 13 06:48:03 PM PDT 24 13807280 ps
T262 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2685799680 Aug 13 06:47:55 PM PDT 24 Aug 13 06:47:56 PM PDT 24 34062998 ps
T1075 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3051990896 Aug 13 06:47:58 PM PDT 24 Aug 13 06:48:00 PM PDT 24 98385897 ps
T1076 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1060720710 Aug 13 06:47:53 PM PDT 24 Aug 13 06:47:54 PM PDT 24 191666845 ps
T1077 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2303580601 Aug 13 06:48:08 PM PDT 24 Aug 13 06:48:09 PM PDT 24 84057210 ps
T1078 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3604861409 Aug 13 06:48:18 PM PDT 24 Aug 13 06:48:20 PM PDT 24 308501905 ps
T1079 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4072568253 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:03 PM PDT 24 29914838 ps
T291 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2545422056 Aug 13 06:47:55 PM PDT 24 Aug 13 06:47:58 PM PDT 24 193942316 ps
T1080 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3930335564 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:07 PM PDT 24 48681714 ps
T1081 /workspace/coverage/cover_reg_top/18.edn_intr_test.1006616202 Aug 13 06:48:05 PM PDT 24 Aug 13 06:48:06 PM PDT 24 13104274 ps
T1082 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3351560240 Aug 13 06:48:07 PM PDT 24 Aug 13 06:48:09 PM PDT 24 132280680 ps
T1083 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.12060892 Aug 13 06:48:24 PM PDT 24 Aug 13 06:48:25 PM PDT 24 68612556 ps
T1084 /workspace/coverage/cover_reg_top/22.edn_intr_test.3215619817 Aug 13 06:48:22 PM PDT 24 Aug 13 06:48:23 PM PDT 24 41224585 ps
T1085 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.150556718 Aug 13 06:48:06 PM PDT 24 Aug 13 06:48:07 PM PDT 24 73746144 ps
T263 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3801392584 Aug 13 06:48:15 PM PDT 24 Aug 13 06:48:16 PM PDT 24 196379893 ps
T1086 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4069941999 Aug 13 06:48:07 PM PDT 24 Aug 13 06:48:09 PM PDT 24 106333803 ps
T1087 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1610987067 Aug 13 06:48:05 PM PDT 24 Aug 13 06:48:06 PM PDT 24 58826836 ps
T1088 /workspace/coverage/cover_reg_top/7.edn_intr_test.1976344740 Aug 13 06:47:55 PM PDT 24 Aug 13 06:47:56 PM PDT 24 43970268 ps
T1089 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.265073005 Aug 13 06:47:55 PM PDT 24 Aug 13 06:47:56 PM PDT 24 43708400 ps
T292 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2384952917 Aug 13 06:48:19 PM PDT 24 Aug 13 06:48:21 PM PDT 24 87221741 ps
T1090 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3516881702 Aug 13 06:48:05 PM PDT 24 Aug 13 06:48:06 PM PDT 24 67217040 ps
T1091 /workspace/coverage/cover_reg_top/44.edn_intr_test.2234444738 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:02 PM PDT 24 12768835 ps
T293 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1480101358 Aug 13 06:47:56 PM PDT 24 Aug 13 06:48:02 PM PDT 24 291594526 ps
T1092 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3022050084 Aug 13 06:48:11 PM PDT 24 Aug 13 06:48:13 PM PDT 24 27851564 ps
T1093 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1131753635 Aug 13 06:47:51 PM PDT 24 Aug 13 06:47:53 PM PDT 24 47657542 ps
T1094 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2130336605 Aug 13 06:47:53 PM PDT 24 Aug 13 06:47:54 PM PDT 24 43182330 ps
T1095 /workspace/coverage/cover_reg_top/8.edn_intr_test.3544238776 Aug 13 06:48:03 PM PDT 24 Aug 13 06:48:04 PM PDT 24 19546053 ps
T1096 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1728717558 Aug 13 06:47:53 PM PDT 24 Aug 13 06:47:59 PM PDT 24 12495590 ps
T264 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1662476916 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:02 PM PDT 24 26812472 ps
T1097 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2403580932 Aug 13 06:47:51 PM PDT 24 Aug 13 06:47:53 PM PDT 24 100077460 ps
T1098 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.355836074 Aug 13 06:48:16 PM PDT 24 Aug 13 06:48:18 PM PDT 24 32537821 ps
T1099 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1436556246 Aug 13 06:48:20 PM PDT 24 Aug 13 06:48:22 PM PDT 24 237481662 ps
T1100 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.325687337 Aug 13 06:48:00 PM PDT 24 Aug 13 06:48:02 PM PDT 24 102675405 ps
T1101 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.731279532 Aug 13 06:48:12 PM PDT 24 Aug 13 06:48:13 PM PDT 24 99534445 ps
T1102 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3768502815 Aug 13 06:47:58 PM PDT 24 Aug 13 06:47:59 PM PDT 24 122415937 ps
T1103 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2987837885 Aug 13 06:48:17 PM PDT 24 Aug 13 06:48:19 PM PDT 24 80804746 ps
T266 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1699603175 Aug 13 06:48:10 PM PDT 24 Aug 13 06:48:12 PM PDT 24 63268053 ps
T267 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.544681803 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:05 PM PDT 24 112585677 ps
T1104 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3664165023 Aug 13 06:48:05 PM PDT 24 Aug 13 06:48:06 PM PDT 24 14814743 ps
T1105 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2227355344 Aug 13 06:48:03 PM PDT 24 Aug 13 06:48:05 PM PDT 24 105501210 ps
T1106 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2678044191 Aug 13 06:48:16 PM PDT 24 Aug 13 06:48:17 PM PDT 24 15124782 ps
T1107 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3169367511 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:04 PM PDT 24 51584116 ps
T1108 /workspace/coverage/cover_reg_top/16.edn_tl_errors.767904617 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:03 PM PDT 24 129847286 ps
T1109 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.102408336 Aug 13 06:48:15 PM PDT 24 Aug 13 06:48:16 PM PDT 24 31160643 ps
T1110 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3803886277 Aug 13 06:47:59 PM PDT 24 Aug 13 06:48:00 PM PDT 24 28535257 ps
T1111 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.237787069 Aug 13 06:48:08 PM PDT 24 Aug 13 06:48:10 PM PDT 24 87389204 ps

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3277679690
Short name T4
Test name
Test status
Simulation time 14345248616 ps
CPU time 52.12 seconds
Started Aug 13 06:46:27 PM PDT 24
Finished Aug 13 06:47:19 PM PDT 24
Peak memory 218228 kb
Host smart-fb262042-1d56-4d5c-acaf-cff4f210bac2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277679690 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3277679690
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.edn_genbits.994020529
Short name T43
Test name
Test status
Simulation time 291783180 ps
CPU time 1.58 seconds
Started Aug 13 06:46:26 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 219436 kb
Host smart-9371923e-194a-48ea-b0e9-914303b2e6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994020529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.994020529
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3268064369
Short name T44
Test name
Test status
Simulation time 32494746 ps
CPU time 1.16 seconds
Started Aug 13 06:45:28 PM PDT 24
Finished Aug 13 06:45:29 PM PDT 24
Peak memory 219924 kb
Host smart-233041ff-f1fd-40df-aced-cd83741d20ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268064369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3268064369
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/43.edn_err.4236516441
Short name T6
Test name
Test status
Simulation time 25608117 ps
CPU time 1.18 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 217648 kb
Host smart-6995440e-f385-4aba-a3df-b154fabe1f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236516441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.4236516441
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/4.edn_sec_cm.144080360
Short name T18
Test name
Test status
Simulation time 912395434 ps
CPU time 4.44 seconds
Started Aug 13 06:45:21 PM PDT 24
Finished Aug 13 06:45:26 PM PDT 24
Peak memory 239456 kb
Host smart-37d883bb-4744-436a-965a-d9fe0b9732fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144080360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.144080360
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.40995874
Short name T82
Test name
Test status
Simulation time 50402669 ps
CPU time 1.51 seconds
Started Aug 13 06:45:24 PM PDT 24
Finished Aug 13 06:45:25 PM PDT 24
Peak memory 217392 kb
Host smart-b088e322-782b-40eb-b3b8-29923445937b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40995874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disa
ble_auto_req_mode.40995874
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/76.edn_alert.3975015873
Short name T99
Test name
Test status
Simulation time 41357561 ps
CPU time 1.12 seconds
Started Aug 13 06:46:39 PM PDT 24
Finished Aug 13 06:46:40 PM PDT 24
Peak memory 218860 kb
Host smart-d2d22c5a-e0c9-4c85-8104-a98e455b4032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975015873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3975015873
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/21.edn_stress_all.1012831239
Short name T198
Test name
Test status
Simulation time 498487935 ps
CPU time 6.12 seconds
Started Aug 13 06:45:41 PM PDT 24
Finished Aug 13 06:45:48 PM PDT 24
Peak memory 217724 kb
Host smart-545d7594-8d5f-451b-953b-a7f10cdfb4ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012831239 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1012831239
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_alert.250401953
Short name T26
Test name
Test status
Simulation time 23292555 ps
CPU time 1.16 seconds
Started Aug 13 06:45:59 PM PDT 24
Finished Aug 13 06:46:00 PM PDT 24
Peak memory 215964 kb
Host smart-7a5b1bd2-2abf-4ec6-bbd3-29fdef5244d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250401953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.250401953
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.340827861
Short name T220
Test name
Test status
Simulation time 5067912404 ps
CPU time 124.16 seconds
Started Aug 13 06:45:50 PM PDT 24
Finished Aug 13 06:47:55 PM PDT 24
Peak memory 218520 kb
Host smart-06f796e7-ab61-41e0-bf71-728ffa73aa29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340827861 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.340827861
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.edn_err.1445238989
Short name T16
Test name
Test status
Simulation time 66344676 ps
CPU time 1.22 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:45:58 PM PDT 24
Peak memory 226020 kb
Host smart-955db4f8-b777-4e8c-8ec0-c0576ea70d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445238989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1445238989
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3696877403
Short name T12
Test name
Test status
Simulation time 559016118 ps
CPU time 2.12 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:45:59 PM PDT 24
Peak memory 215784 kb
Host smart-3ce45149-aa06-49d7-922b-67082ea18f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696877403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3696877403
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.4133374057
Short name T125
Test name
Test status
Simulation time 419150681 ps
CPU time 1.45 seconds
Started Aug 13 06:46:41 PM PDT 24
Finished Aug 13 06:46:43 PM PDT 24
Peak memory 220196 kb
Host smart-541f6e9e-4a8c-4699-a74a-a5065fb11bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133374057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.4133374057
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/2.edn_regwen.3619890729
Short name T236
Test name
Test status
Simulation time 45621827 ps
CPU time 0.88 seconds
Started Aug 13 06:45:10 PM PDT 24
Finished Aug 13 06:45:11 PM PDT 24
Peak memory 207572 kb
Host smart-24ef8f9f-08e6-4202-8a57-176e2e6370c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619890729 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3619890729
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_alert.762919408
Short name T100
Test name
Test status
Simulation time 47626814 ps
CPU time 1.19 seconds
Started Aug 13 06:45:20 PM PDT 24
Finished Aug 13 06:45:21 PM PDT 24
Peak memory 220764 kb
Host smart-052e8fae-7d41-4cc5-9bee-47e20f7821fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762919408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.762919408
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3835096933
Short name T253
Test name
Test status
Simulation time 33562586 ps
CPU time 0.84 seconds
Started Aug 13 06:47:54 PM PDT 24
Finished Aug 13 06:47:56 PM PDT 24
Peak memory 207164 kb
Host smart-7b8708df-a31a-4374-ab65-df9bf01de337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835096933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3835096933
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.850583170
Short name T233
Test name
Test status
Simulation time 54596189 ps
CPU time 1.66 seconds
Started Aug 13 06:47:56 PM PDT 24
Finished Aug 13 06:47:58 PM PDT 24
Peak memory 207300 kb
Host smart-e21bc406-3ca4-46d0-a22d-7d903b176cc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850583170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.850583170
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/default/33.edn_disable.192611556
Short name T59
Test name
Test status
Simulation time 101768388 ps
CPU time 0.84 seconds
Started Aug 13 06:46:05 PM PDT 24
Finished Aug 13 06:46:05 PM PDT 24
Peak memory 216872 kb
Host smart-ea6a3221-1ae7-495a-9a93-f455fc0ffbe7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192611556 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.192611556
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable.666909371
Short name T201
Test name
Test status
Simulation time 127225649 ps
CPU time 0.9 seconds
Started Aug 13 06:45:48 PM PDT 24
Finished Aug 13 06:45:49 PM PDT 24
Peak memory 216840 kb
Host smart-e508654b-55ea-48c3-a03d-fe97c4e508d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666909371 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.666909371
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable.799369803
Short name T196
Test name
Test status
Simulation time 52033132 ps
CPU time 0.86 seconds
Started Aug 13 06:45:25 PM PDT 24
Finished Aug 13 06:45:26 PM PDT 24
Peak memory 216776 kb
Host smart-d4452817-826b-4867-bf50-35f2aae3e4e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799369803 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.799369803
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.4087659021
Short name T151
Test name
Test status
Simulation time 133060395 ps
CPU time 1.22 seconds
Started Aug 13 06:45:54 PM PDT 24
Finished Aug 13 06:45:55 PM PDT 24
Peak memory 217308 kb
Host smart-6913cc16-4e60-48c3-a735-2f62cf83a5d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087659021 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.4087659021
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_intr.2668679504
Short name T38
Test name
Test status
Simulation time 23403094 ps
CPU time 0.94 seconds
Started Aug 13 06:45:20 PM PDT 24
Finished Aug 13 06:45:21 PM PDT 24
Peak memory 216016 kb
Host smart-b8a9b2b2-e84a-40d2-bea2-4667e1f7a530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668679504 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2668679504
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/119.edn_alert.590450137
Short name T303
Test name
Test status
Simulation time 86103686 ps
CPU time 1.2 seconds
Started Aug 13 06:46:50 PM PDT 24
Finished Aug 13 06:46:51 PM PDT 24
Peak memory 220044 kb
Host smart-52ec12ef-e9e1-4a90-92af-a089e4d1a68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590450137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.590450137
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.2441476020
Short name T249
Test name
Test status
Simulation time 25064991 ps
CPU time 1.18 seconds
Started Aug 13 06:47:10 PM PDT 24
Finished Aug 13 06:47:11 PM PDT 24
Peak memory 218856 kb
Host smart-443ee711-2cde-415b-805c-4ff1f45a57e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441476020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2441476020
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert.2089881389
Short name T741
Test name
Test status
Simulation time 51199296 ps
CPU time 1.17 seconds
Started Aug 13 06:45:28 PM PDT 24
Finished Aug 13 06:45:29 PM PDT 24
Peak memory 220192 kb
Host smart-abe27c0b-a44f-4f1a-b921-e5c41fc2d639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089881389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2089881389
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/169.edn_alert.574483626
Short name T138
Test name
Test status
Simulation time 176758374 ps
CPU time 1.25 seconds
Started Aug 13 06:47:07 PM PDT 24
Finished Aug 13 06:47:09 PM PDT 24
Peak memory 218868 kb
Host smart-90258fbc-18dc-4e75-9dd1-7438279a745c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574483626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.574483626
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/36.edn_disable.1659174494
Short name T29
Test name
Test status
Simulation time 18078084 ps
CPU time 0.88 seconds
Started Aug 13 06:46:12 PM PDT 24
Finished Aug 13 06:46:13 PM PDT 24
Peak memory 215904 kb
Host smart-35067206-8a8a-4b3b-a9a4-54caee222d78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659174494 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1659174494
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/65.edn_alert.1672820673
Short name T92
Test name
Test status
Simulation time 51141325 ps
CPU time 1.24 seconds
Started Aug 13 06:46:43 PM PDT 24
Finished Aug 13 06:46:44 PM PDT 24
Peak memory 216008 kb
Host smart-6ec2a907-9139-480f-bbbd-4443cf3bc58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672820673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1672820673
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/120.edn_alert.451824626
Short name T439
Test name
Test status
Simulation time 35079881 ps
CPU time 1.14 seconds
Started Aug 13 06:46:48 PM PDT 24
Finished Aug 13 06:46:50 PM PDT 24
Peak memory 219684 kb
Host smart-e3529599-796b-4cbd-9a85-f30a353dec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451824626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.451824626
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/197.edn_alert.4204716908
Short name T53
Test name
Test status
Simulation time 52681716 ps
CPU time 1.21 seconds
Started Aug 13 06:47:09 PM PDT 24
Finished Aug 13 06:47:11 PM PDT 24
Peak memory 221068 kb
Host smart-097934f3-9ad7-42eb-a160-7eb6662cba27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204716908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.4204716908
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert.2744345747
Short name T515
Test name
Test status
Simulation time 67936114 ps
CPU time 1.16 seconds
Started Aug 13 06:45:48 PM PDT 24
Finished Aug 13 06:45:50 PM PDT 24
Peak memory 220856 kb
Host smart-fbd88dca-78be-49ea-9abc-9008b3546ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744345747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2744345747
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2113516721
Short name T21
Test name
Test status
Simulation time 28703669 ps
CPU time 1.3 seconds
Started Aug 13 06:47:14 PM PDT 24
Finished Aug 13 06:47:15 PM PDT 24
Peak memory 220380 kb
Host smart-25169948-281a-4bda-ad88-9ac2ab7b5286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113516721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2113516721
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3924064394
Short name T42
Test name
Test status
Simulation time 2458133199 ps
CPU time 62.86 seconds
Started Aug 13 06:46:14 PM PDT 24
Finished Aug 13 06:47:17 PM PDT 24
Peak memory 218532 kb
Host smart-3b9b2f37-451b-47a6-a762-b38b000f2761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924064394 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3924064394
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3213914449
Short name T106
Test name
Test status
Simulation time 29319164 ps
CPU time 1.14 seconds
Started Aug 13 06:45:38 PM PDT 24
Finished Aug 13 06:45:39 PM PDT 24
Peak memory 219044 kb
Host smart-ae1cbe6c-ecc2-4148-9246-d9b994400889
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213914449 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3213914449
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_intr.1978838193
Short name T111
Test name
Test status
Simulation time 27068598 ps
CPU time 0.84 seconds
Started Aug 13 06:45:05 PM PDT 24
Finished Aug 13 06:45:06 PM PDT 24
Peak memory 215800 kb
Host smart-345db589-9401-4ff9-9728-8f4386c56c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978838193 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1978838193
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_err.10338427
Short name T194
Test name
Test status
Simulation time 23051812 ps
CPU time 1.06 seconds
Started Aug 13 06:45:09 PM PDT 24
Finished Aug 13 06:45:11 PM PDT 24
Peak memory 229772 kb
Host smart-cb699765-c186-407a-9f62-2522a8570968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10338427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.10338427
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/101.edn_alert.3497937767
Short name T140
Test name
Test status
Simulation time 122560685 ps
CPU time 1.21 seconds
Started Aug 13 06:46:35 PM PDT 24
Finished Aug 13 06:46:36 PM PDT 24
Peak memory 218832 kb
Host smart-744a62df-c806-4a46-8a78-37a6fcbd1053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497937767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3497937767
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/127.edn_alert.1913605993
Short name T971
Test name
Test status
Simulation time 71713908 ps
CPU time 1.09 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 215996 kb
Host smart-3df452bf-be2c-41de-b6ae-92b481dc164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913605993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1913605993
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/129.edn_alert.1250601280
Short name T187
Test name
Test status
Simulation time 47329522 ps
CPU time 1.32 seconds
Started Aug 13 06:46:54 PM PDT 24
Finished Aug 13 06:46:55 PM PDT 24
Peak memory 221588 kb
Host smart-109e4504-edff-4a54-8890-e467e6fb6ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250601280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1250601280
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.789188324
Short name T155
Test name
Test status
Simulation time 138553028 ps
CPU time 1.26 seconds
Started Aug 13 06:45:37 PM PDT 24
Finished Aug 13 06:45:38 PM PDT 24
Peak memory 217220 kb
Host smart-a32f687e-f5e2-46c1-9d61-4efd76012e30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789188324 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.789188324
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable.3010849324
Short name T758
Test name
Test status
Simulation time 43249873 ps
CPU time 0.89 seconds
Started Aug 13 06:45:34 PM PDT 24
Finished Aug 13 06:45:35 PM PDT 24
Peak memory 216832 kb
Host smart-ef0f80a1-aa7d-4b51-8961-6dfb94ba85aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010849324 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3010849324
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/191.edn_alert.42391366
Short name T132
Test name
Test status
Simulation time 109714860 ps
CPU time 1.21 seconds
Started Aug 13 06:47:15 PM PDT 24
Finished Aug 13 06:47:17 PM PDT 24
Peak memory 219068 kb
Host smart-7169e881-c80c-4f75-95d4-d236e8bfc849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42391366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.42391366
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.288332003
Short name T752
Test name
Test status
Simulation time 36444177 ps
CPU time 1.17 seconds
Started Aug 13 06:45:42 PM PDT 24
Finished Aug 13 06:45:43 PM PDT 24
Peak memory 217200 kb
Host smart-5886898e-9f90-4bee-b57c-b371b86d3e4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288332003 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.288332003
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_disable.112045136
Short name T178
Test name
Test status
Simulation time 33886816 ps
CPU time 0.89 seconds
Started Aug 13 06:45:51 PM PDT 24
Finished Aug 13 06:45:52 PM PDT 24
Peak memory 216836 kb
Host smart-ee8b0bcc-dec0-4025-bd1d-91537bef94e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112045136 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.112045136
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.3671864133
Short name T181
Test name
Test status
Simulation time 31273386 ps
CPU time 0.91 seconds
Started Aug 13 06:45:59 PM PDT 24
Finished Aug 13 06:46:00 PM PDT 24
Peak memory 218552 kb
Host smart-3bda436a-3a57-4361-abff-81d6b3a6a2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671864133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3671864133
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/44.edn_disable.2762583915
Short name T209
Test name
Test status
Simulation time 11297121 ps
CPU time 0.88 seconds
Started Aug 13 06:46:33 PM PDT 24
Finished Aug 13 06:46:33 PM PDT 24
Peak memory 216788 kb
Host smart-6acd12a2-c2c0-4203-bd71-51a865bc85fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762583915 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2762583915
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/59.edn_err.2339502452
Short name T190
Test name
Test status
Simulation time 51970363 ps
CPU time 0.87 seconds
Started Aug 13 06:46:32 PM PDT 24
Finished Aug 13 06:46:33 PM PDT 24
Peak memory 218448 kb
Host smart-7e2939e5-7bda-4642-9066-fb9545e246ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339502452 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2339502452
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/191.edn_genbits.3023315801
Short name T14
Test name
Test status
Simulation time 35294475 ps
CPU time 1.39 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:13 PM PDT 24
Peak memory 220380 kb
Host smart-ca2052f5-89b8-4f6f-b02d-94c5cd7cc0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023315801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3023315801
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.1547528674
Short name T355
Test name
Test status
Simulation time 21654899 ps
CPU time 1 seconds
Started Aug 13 06:45:26 PM PDT 24
Finished Aug 13 06:45:27 PM PDT 24
Peak memory 215288 kb
Host smart-546fc564-e056-4ab0-8c26-1e81d9ed5ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547528674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1547528674
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/104.edn_genbits.4002043709
Short name T274
Test name
Test status
Simulation time 63399256 ps
CPU time 1.59 seconds
Started Aug 13 06:46:34 PM PDT 24
Finished Aug 13 06:46:36 PM PDT 24
Peak memory 219000 kb
Host smart-52f653c7-18b1-42d8-ae99-3a32968baf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002043709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.4002043709
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1400882871
Short name T103
Test name
Test status
Simulation time 24238885 ps
CPU time 1.13 seconds
Started Aug 13 06:46:20 PM PDT 24
Finished Aug 13 06:46:21 PM PDT 24
Peak memory 216168 kb
Host smart-a9367e24-a8c0-4dbe-a5e1-4096814636f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400882871 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1400882871
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/213.edn_genbits.956414724
Short name T23
Test name
Test status
Simulation time 147936420 ps
CPU time 3.35 seconds
Started Aug 13 06:47:05 PM PDT 24
Finished Aug 13 06:47:08 PM PDT 24
Peak memory 220296 kb
Host smart-b884567c-784e-4897-9e6a-55705c103d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956414724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.956414724
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.209768798
Short name T659
Test name
Test status
Simulation time 50281624 ps
CPU time 1.24 seconds
Started Aug 13 06:46:55 PM PDT 24
Finished Aug 13 06:46:56 PM PDT 24
Peak memory 220600 kb
Host smart-f22f1696-fa33-4b7a-b27a-a385e55bc99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209768798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.209768798
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.1144079711
Short name T95
Test name
Test status
Simulation time 47473726 ps
CPU time 1.52 seconds
Started Aug 13 06:46:46 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 218936 kb
Host smart-8f18ccbd-f83f-47c0-919f-fefc21dd913b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144079711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1144079711
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.583424632
Short name T332
Test name
Test status
Simulation time 111893909 ps
CPU time 1.37 seconds
Started Aug 13 06:46:56 PM PDT 24
Finished Aug 13 06:46:58 PM PDT 24
Peak memory 220228 kb
Host smart-c41e6dfa-d220-4624-a01c-4090cd5ed477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583424632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.583424632
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.237787069
Short name T1111
Test name
Test status
Simulation time 87389204 ps
CPU time 1.74 seconds
Started Aug 13 06:48:08 PM PDT 24
Finished Aug 13 06:48:10 PM PDT 24
Peak memory 215384 kb
Host smart-cc647db6-70ad-4c21-8552-09753b83a344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237787069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.237787069
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/default/105.edn_genbits.3816519138
Short name T342
Test name
Test status
Simulation time 76650794 ps
CPU time 1.05 seconds
Started Aug 13 06:46:38 PM PDT 24
Finished Aug 13 06:46:39 PM PDT 24
Peak memory 217564 kb
Host smart-568d889f-1837-4a32-9959-20f6469041ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816519138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3816519138
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2946151435
Short name T321
Test name
Test status
Simulation time 154268619 ps
CPU time 2.37 seconds
Started Aug 13 06:46:53 PM PDT 24
Finished Aug 13 06:46:56 PM PDT 24
Peak memory 219252 kb
Host smart-e8d559a0-8cc9-43fe-b15d-ad4fb8a7c246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946151435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2946151435
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_stress_all.2955551009
Short name T760
Test name
Test status
Simulation time 423734605 ps
CPU time 3.93 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:40 PM PDT 24
Peak memory 217612 kb
Host smart-f821ba57-95ea-4e32-9961-987c05b6edfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955551009 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2955551009
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/126.edn_genbits.369104273
Short name T310
Test name
Test status
Simulation time 64341257 ps
CPU time 1.24 seconds
Started Aug 13 06:46:51 PM PDT 24
Finished Aug 13 06:46:52 PM PDT 24
Peak memory 219296 kb
Host smart-822e2693-f43a-4e0f-9528-dd38035a0366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369104273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.369104273
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.3014441503
Short name T51
Test name
Test status
Simulation time 59616207 ps
CPU time 1.43 seconds
Started Aug 13 06:46:58 PM PDT 24
Finished Aug 13 06:46:59 PM PDT 24
Peak memory 218944 kb
Host smart-1b806807-0227-4f30-b1eb-b8eb22641479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014441503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3014441503
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_genbits.3190563642
Short name T324
Test name
Test status
Simulation time 128313587 ps
CPU time 1.36 seconds
Started Aug 13 06:45:50 PM PDT 24
Finished Aug 13 06:45:52 PM PDT 24
Peak memory 219280 kb
Host smart-887df988-03a2-491a-986a-cb5a66572078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190563642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3190563642
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1309288571
Short name T313
Test name
Test status
Simulation time 96056758 ps
CPU time 1.52 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 219244 kb
Host smart-45bb0132-8d7a-428b-b3a1-0633411bb2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309288571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1309288571
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1188256381
Short name T286
Test name
Test status
Simulation time 35441439 ps
CPU time 1.57 seconds
Started Aug 13 06:46:14 PM PDT 24
Finished Aug 13 06:46:16 PM PDT 24
Peak memory 217120 kb
Host smart-8ad44db1-d971-4e55-a64b-bc5d3f7c1e29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188256381 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1188256381
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_intr.4114815515
Short name T109
Test name
Test status
Simulation time 21016193 ps
CPU time 1.08 seconds
Started Aug 13 06:45:22 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 216096 kb
Host smart-52b7afce-4180-4a20-b7c1-faa75b03178c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114815515 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.4114815515
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/17.edn_stress_all.1005732611
Short name T115
Test name
Test status
Simulation time 436507191 ps
CPU time 2.59 seconds
Started Aug 13 06:45:32 PM PDT 24
Finished Aug 13 06:45:34 PM PDT 24
Peak memory 217588 kb
Host smart-73b88990-a62b-4f44-835c-b889b45b7394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005732611 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1005732611
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/182.edn_alert.262049563
Short name T118
Test name
Test status
Simulation time 37125928 ps
CPU time 1.23 seconds
Started Aug 13 06:47:11 PM PDT 24
Finished Aug 13 06:47:12 PM PDT 24
Peak memory 220620 kb
Host smart-d4feaa80-0f1d-4344-92b5-0bcc1b13a507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262049563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.262049563
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.731279532
Short name T1101
Test name
Test status
Simulation time 99534445 ps
CPU time 1.54 seconds
Started Aug 13 06:48:12 PM PDT 24
Finished Aug 13 06:48:13 PM PDT 24
Peak memory 207220 kb
Host smart-6caa8b2f-99b1-455e-a16f-2f249c6f643f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731279532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.731279532
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2475158720
Short name T1037
Test name
Test status
Simulation time 830626591 ps
CPU time 4.97 seconds
Started Aug 13 06:48:04 PM PDT 24
Finished Aug 13 06:48:14 PM PDT 24
Peak memory 207220 kb
Host smart-9597b839-ac28-4681-a01e-189da1b85b46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475158720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2475158720
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.439289248
Short name T1006
Test name
Test status
Simulation time 159717268 ps
CPU time 0.8 seconds
Started Aug 13 06:48:08 PM PDT 24
Finished Aug 13 06:48:08 PM PDT 24
Peak memory 206944 kb
Host smart-daabdf60-8aab-4a98-a588-bd01c7638c11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439289248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.439289248
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2278775925
Short name T1056
Test name
Test status
Simulation time 100083593 ps
CPU time 1.6 seconds
Started Aug 13 06:48:08 PM PDT 24
Finished Aug 13 06:48:10 PM PDT 24
Peak memory 215568 kb
Host smart-983a8de1-eedc-411d-9acc-3a0b27676548
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278775925 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2278775925
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1662476916
Short name T264
Test name
Test status
Simulation time 26812472 ps
CPU time 0.88 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:02 PM PDT 24
Peak memory 207216 kb
Host smart-270dda4b-e82f-496d-9b0d-30f944a50854
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662476916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1662476916
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3184230683
Short name T984
Test name
Test status
Simulation time 12762277 ps
CPU time 0.86 seconds
Started Aug 13 06:48:14 PM PDT 24
Finished Aug 13 06:48:15 PM PDT 24
Peak memory 207036 kb
Host smart-1210e951-6a2f-407b-817a-8675e5478f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184230683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3184230683
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3511889708
Short name T272
Test name
Test status
Simulation time 98751200 ps
CPU time 1.04 seconds
Started Aug 13 06:47:59 PM PDT 24
Finished Aug 13 06:48:05 PM PDT 24
Peak memory 207264 kb
Host smart-cbe9c36e-a876-4266-a450-d9180daa9a1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511889708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3511889708
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2403580932
Short name T1097
Test name
Test status
Simulation time 100077460 ps
CPU time 1.88 seconds
Started Aug 13 06:47:51 PM PDT 24
Finished Aug 13 06:47:53 PM PDT 24
Peak memory 215356 kb
Host smart-22b5030c-1f65-496e-b289-02744d7fa98c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403580932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2403580932
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1004805099
Short name T1068
Test name
Test status
Simulation time 142045016 ps
CPU time 1.43 seconds
Started Aug 13 06:48:04 PM PDT 24
Finished Aug 13 06:48:06 PM PDT 24
Peak memory 207232 kb
Host smart-c7579087-99cb-4a60-8518-d7be1bfae142
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004805099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1004805099
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1684023759
Short name T1055
Test name
Test status
Simulation time 25408998 ps
CPU time 1.2 seconds
Started Aug 13 06:47:56 PM PDT 24
Finished Aug 13 06:47:58 PM PDT 24
Peak memory 207292 kb
Host smart-52476199-282d-4d1b-bce4-fe376d030254
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684023759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1684023759
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1488613395
Short name T265
Test name
Test status
Simulation time 60059541 ps
CPU time 3.34 seconds
Started Aug 13 06:47:55 PM PDT 24
Finished Aug 13 06:47:58 PM PDT 24
Peak memory 207256 kb
Host smart-5e063c65-f42b-44be-bd5c-dce886826d4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488613395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1488613395
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2685799680
Short name T262
Test name
Test status
Simulation time 34062998 ps
CPU time 0.98 seconds
Started Aug 13 06:47:55 PM PDT 24
Finished Aug 13 06:47:56 PM PDT 24
Peak memory 207224 kb
Host smart-6e5b398b-5180-4238-bc6f-1f8cdc087189
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685799680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2685799680
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3078422836
Short name T994
Test name
Test status
Simulation time 60646526 ps
CPU time 1.1 seconds
Started Aug 13 06:48:08 PM PDT 24
Finished Aug 13 06:48:09 PM PDT 24
Peak memory 215512 kb
Host smart-a31b51a6-06c0-4ccc-a2bb-064f39f373ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078422836 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3078422836
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3930335564
Short name T1080
Test name
Test status
Simulation time 48681714 ps
CPU time 0.84 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:07 PM PDT 24
Peak memory 207268 kb
Host smart-bfc01ae2-b977-46a5-b143-0506c71e62e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930335564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3930335564
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3195946302
Short name T1027
Test name
Test status
Simulation time 13744969 ps
CPU time 0.88 seconds
Started Aug 13 06:48:10 PM PDT 24
Finished Aug 13 06:48:11 PM PDT 24
Peak memory 207068 kb
Host smart-ea26ba49-d38d-42e1-be6d-349b6d3f9592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195946302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3195946302
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3797934425
Short name T1043
Test name
Test status
Simulation time 92002932 ps
CPU time 1.28 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:54 PM PDT 24
Peak memory 207296 kb
Host smart-bea68c9a-9c56-4683-8b32-cbe2a8270ce8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797934425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3797934425
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.327316608
Short name T1001
Test name
Test status
Simulation time 321403639 ps
CPU time 3.04 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:56 PM PDT 24
Peak memory 215424 kb
Host smart-0eb75fef-b4ad-4853-baa6-e9a10f89d35e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327316608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.327316608
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3971233255
Short name T283
Test name
Test status
Simulation time 162257721 ps
CPU time 2.44 seconds
Started Aug 13 06:48:02 PM PDT 24
Finished Aug 13 06:48:09 PM PDT 24
Peak memory 207464 kb
Host smart-a2e30084-87f3-43ac-aac3-5423a040c38d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971233255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3971233255
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.303588362
Short name T230
Test name
Test status
Simulation time 37100542 ps
CPU time 1.03 seconds
Started Aug 13 06:48:06 PM PDT 24
Finished Aug 13 06:48:08 PM PDT 24
Peak memory 215468 kb
Host smart-a62d0e2b-f6ae-4ca5-8ebc-0c64b79de9e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303588362 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.303588362
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3249459438
Short name T1036
Test name
Test status
Simulation time 17152550 ps
CPU time 0.92 seconds
Started Aug 13 06:47:54 PM PDT 24
Finished Aug 13 06:47:55 PM PDT 24
Peak memory 207180 kb
Host smart-3dbec066-0457-4703-b742-bce72a8c2dfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249459438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3249459438
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.781016087
Short name T1034
Test name
Test status
Simulation time 17069339 ps
CPU time 0.94 seconds
Started Aug 13 06:48:08 PM PDT 24
Finished Aug 13 06:48:10 PM PDT 24
Peak memory 207084 kb
Host smart-3af52efc-3529-47e5-a2b4-450fb58f23d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781016087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.781016087
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.810713681
Short name T271
Test name
Test status
Simulation time 26838204 ps
CPU time 1.15 seconds
Started Aug 13 06:48:02 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 207140 kb
Host smart-0747ffca-7373-4d62-ab05-b758b796a182
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810713681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.810713681
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3336031046
Short name T229
Test name
Test status
Simulation time 203688208 ps
CPU time 3.47 seconds
Started Aug 13 06:47:58 PM PDT 24
Finished Aug 13 06:48:02 PM PDT 24
Peak memory 215460 kb
Host smart-01dea79b-5223-40b5-81b3-8c41d7505128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336031046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3336031046
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1784828918
Short name T290
Test name
Test status
Simulation time 131741458 ps
CPU time 1.94 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:04 PM PDT 24
Peak memory 207188 kb
Host smart-899acb7b-dda0-4e65-bacb-e50dccf7cab6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784828918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1784828918
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2303580601
Short name T1077
Test name
Test status
Simulation time 84057210 ps
CPU time 1.16 seconds
Started Aug 13 06:48:08 PM PDT 24
Finished Aug 13 06:48:09 PM PDT 24
Peak memory 215452 kb
Host smart-ca37c79a-c7ee-48c1-9241-f6c440561bbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303580601 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2303580601
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3664165023
Short name T1104
Test name
Test status
Simulation time 14814743 ps
CPU time 0.86 seconds
Started Aug 13 06:48:05 PM PDT 24
Finished Aug 13 06:48:06 PM PDT 24
Peak memory 207216 kb
Host smart-52513291-2272-4327-be8c-ca54d83aee6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664165023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3664165023
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2863572244
Short name T1041
Test name
Test status
Simulation time 29889413 ps
CPU time 0.78 seconds
Started Aug 13 06:48:25 PM PDT 24
Finished Aug 13 06:48:26 PM PDT 24
Peak memory 206920 kb
Host smart-e3c5bd6f-895a-4c8c-b5b7-df2afde4b155
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863572244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2863572244
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.98029300
Short name T270
Test name
Test status
Simulation time 45267981 ps
CPU time 0.93 seconds
Started Aug 13 06:48:17 PM PDT 24
Finished Aug 13 06:48:18 PM PDT 24
Peak memory 207224 kb
Host smart-acda7a49-1f8b-4467-bad0-4f1c7ad4b59d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98029300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_out
standing.98029300
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3826464967
Short name T996
Test name
Test status
Simulation time 99519471 ps
CPU time 1.96 seconds
Started Aug 13 06:47:54 PM PDT 24
Finished Aug 13 06:47:57 PM PDT 24
Peak memory 215512 kb
Host smart-4a4e00bc-42f7-4e36-8a5e-8a07a3ca90a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826464967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3826464967
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2643569272
Short name T1072
Test name
Test status
Simulation time 124418550 ps
CPU time 1.67 seconds
Started Aug 13 06:48:06 PM PDT 24
Finished Aug 13 06:48:08 PM PDT 24
Peak memory 207188 kb
Host smart-3e7465ca-adb0-406d-92eb-021e37ee0c13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643569272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2643569272
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4072568253
Short name T1079
Test name
Test status
Simulation time 29914838 ps
CPU time 1.03 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 215424 kb
Host smart-7d76f90c-7593-445f-8e26-d42574fa302b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072568253 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.4072568253
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1546189626
Short name T1049
Test name
Test status
Simulation time 59164764 ps
CPU time 0.85 seconds
Started Aug 13 06:48:08 PM PDT 24
Finished Aug 13 06:48:09 PM PDT 24
Peak memory 207052 kb
Host smart-8d2d6c43-f22a-4360-bdd7-4a7a4b44117f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546189626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1546189626
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.744904044
Short name T986
Test name
Test status
Simulation time 16333563 ps
CPU time 0.9 seconds
Started Aug 13 06:48:04 PM PDT 24
Finished Aug 13 06:48:05 PM PDT 24
Peak memory 207108 kb
Host smart-b540ffa0-b55e-431c-b3e0-be5e9b36c143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744904044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.744904044
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1020844632
Short name T256
Test name
Test status
Simulation time 28028561 ps
CPU time 1.31 seconds
Started Aug 13 06:48:09 PM PDT 24
Finished Aug 13 06:48:11 PM PDT 24
Peak memory 207236 kb
Host smart-a8d63773-108d-4d98-8140-71333054bb20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020844632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1020844632
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1896503174
Short name T1070
Test name
Test status
Simulation time 114175767 ps
CPU time 2.52 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:04 PM PDT 24
Peak memory 219464 kb
Host smart-b948b8d0-001f-43a2-92e9-a06f536fc525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896503174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1896503174
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.295240165
Short name T1017
Test name
Test status
Simulation time 103027169 ps
CPU time 2.52 seconds
Started Aug 13 06:47:51 PM PDT 24
Finished Aug 13 06:47:54 PM PDT 24
Peak memory 207220 kb
Host smart-dec9bf62-96b6-4dbb-ad73-e1525aff41e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295240165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.295240165
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3797208568
Short name T1016
Test name
Test status
Simulation time 33875671 ps
CPU time 1.58 seconds
Started Aug 13 06:47:59 PM PDT 24
Finished Aug 13 06:48:01 PM PDT 24
Peak memory 215556 kb
Host smart-4b1c74f8-3f29-4111-b103-43a42cd93ca6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797208568 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3797208568
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3321624287
Short name T259
Test name
Test status
Simulation time 58380239 ps
CPU time 0.83 seconds
Started Aug 13 06:48:09 PM PDT 24
Finished Aug 13 06:48:10 PM PDT 24
Peak memory 206992 kb
Host smart-f517287a-8d72-440c-9452-a9b252ae8640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321624287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3321624287
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2813888422
Short name T1058
Test name
Test status
Simulation time 18065378 ps
CPU time 0.78 seconds
Started Aug 13 06:48:17 PM PDT 24
Finished Aug 13 06:48:21 PM PDT 24
Peak memory 206916 kb
Host smart-94c45659-1b04-4c06-bd9c-53569d7a3523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813888422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2813888422
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1610987067
Short name T1087
Test name
Test status
Simulation time 58826836 ps
CPU time 1.31 seconds
Started Aug 13 06:48:05 PM PDT 24
Finished Aug 13 06:48:06 PM PDT 24
Peak memory 207228 kb
Host smart-36b4ac70-f6df-4862-a50a-c6d75e84eb96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610987067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1610987067
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3785667271
Short name T1018
Test name
Test status
Simulation time 57621462 ps
CPU time 2.86 seconds
Started Aug 13 06:47:57 PM PDT 24
Finished Aug 13 06:48:00 PM PDT 24
Peak memory 215352 kb
Host smart-ef3b33eb-07c7-4f9f-a4dd-814461ebcf6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785667271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3785667271
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3604861409
Short name T1078
Test name
Test status
Simulation time 308501905 ps
CPU time 2.41 seconds
Started Aug 13 06:48:18 PM PDT 24
Finished Aug 13 06:48:20 PM PDT 24
Peak memory 207124 kb
Host smart-676eb98f-ab33-4522-b464-0652491dc7b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604861409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3604861409
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3516881702
Short name T1090
Test name
Test status
Simulation time 67217040 ps
CPU time 1.31 seconds
Started Aug 13 06:48:05 PM PDT 24
Finished Aug 13 06:48:06 PM PDT 24
Peak memory 223744 kb
Host smart-1e00eabc-f62a-40c0-a1f5-874429b405d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516881702 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3516881702
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2678044191
Short name T1106
Test name
Test status
Simulation time 15124782 ps
CPU time 0.9 seconds
Started Aug 13 06:48:16 PM PDT 24
Finished Aug 13 06:48:17 PM PDT 24
Peak memory 207184 kb
Host smart-19972b81-21b0-4693-92d9-615fcce2144f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678044191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2678044191
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3897522243
Short name T1053
Test name
Test status
Simulation time 17457743 ps
CPU time 0.94 seconds
Started Aug 13 06:48:08 PM PDT 24
Finished Aug 13 06:48:09 PM PDT 24
Peak memory 207032 kb
Host smart-1029586a-a605-460c-af4b-15b31eb279fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897522243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3897522243
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.12060892
Short name T1083
Test name
Test status
Simulation time 68612556 ps
CPU time 1.03 seconds
Started Aug 13 06:48:24 PM PDT 24
Finished Aug 13 06:48:25 PM PDT 24
Peak memory 207240 kb
Host smart-28337ed1-6a04-4166-8f9c-700769d48d36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12060892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_out
standing.12060892
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3169367511
Short name T1107
Test name
Test status
Simulation time 51584116 ps
CPU time 2.22 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:04 PM PDT 24
Peak memory 215376 kb
Host smart-d2791741-ed7e-435e-9788-9dd790085475
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169367511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3169367511
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2987837885
Short name T1103
Test name
Test status
Simulation time 80804746 ps
CPU time 1.57 seconds
Started Aug 13 06:48:17 PM PDT 24
Finished Aug 13 06:48:19 PM PDT 24
Peak memory 215664 kb
Host smart-53c4c6ec-7126-45bd-a7b3-148722e4e003
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987837885 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2987837885
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2483869676
Short name T1022
Test name
Test status
Simulation time 182489624 ps
CPU time 0.88 seconds
Started Aug 13 06:48:06 PM PDT 24
Finished Aug 13 06:48:07 PM PDT 24
Peak memory 207044 kb
Host smart-fb8939a3-da0c-4ecf-acbf-8cb0fb6dfb5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483869676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2483869676
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1084570751
Short name T995
Test name
Test status
Simulation time 12661204 ps
CPU time 0.82 seconds
Started Aug 13 06:48:10 PM PDT 24
Finished Aug 13 06:48:11 PM PDT 24
Peak memory 207080 kb
Host smart-b46eb5a0-74c3-404f-8795-274934606c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084570751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1084570751
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2851153009
Short name T273
Test name
Test status
Simulation time 27517849 ps
CPU time 1.01 seconds
Started Aug 13 06:48:12 PM PDT 24
Finished Aug 13 06:48:13 PM PDT 24
Peak memory 207296 kb
Host smart-bc8f250c-44ed-48f6-946f-d05dd7ff5dde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851153009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2851153009
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3365283199
Short name T1035
Test name
Test status
Simulation time 161703459 ps
CPU time 2.75 seconds
Started Aug 13 06:48:07 PM PDT 24
Finished Aug 13 06:48:10 PM PDT 24
Peak memory 215428 kb
Host smart-bb6df524-83af-4fef-ba7f-a497d349a9cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365283199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3365283199
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1436556246
Short name T1099
Test name
Test status
Simulation time 237481662 ps
CPU time 2.05 seconds
Started Aug 13 06:48:20 PM PDT 24
Finished Aug 13 06:48:22 PM PDT 24
Peak memory 207244 kb
Host smart-ed3c73ab-a186-4243-8eb1-0b2d2fbbd6f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436556246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1436556246
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3200127635
Short name T1031
Test name
Test status
Simulation time 18806413 ps
CPU time 1.03 seconds
Started Aug 13 06:48:10 PM PDT 24
Finished Aug 13 06:48:11 PM PDT 24
Peak memory 207248 kb
Host smart-584caf96-a6d2-4945-9b0b-dcf19bf714c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200127635 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3200127635
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2959948873
Short name T1059
Test name
Test status
Simulation time 34313473 ps
CPU time 0.79 seconds
Started Aug 13 06:48:02 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 206960 kb
Host smart-6e1bcadd-d19d-4103-90ea-5d0e984ca928
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959948873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2959948873
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1922053678
Short name T1013
Test name
Test status
Simulation time 12031330 ps
CPU time 0.86 seconds
Started Aug 13 06:47:59 PM PDT 24
Finished Aug 13 06:48:00 PM PDT 24
Peak memory 207064 kb
Host smart-68dd18ed-5499-4466-a0fb-c9fd26481280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922053678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1922053678
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3237780210
Short name T1067
Test name
Test status
Simulation time 53930513 ps
CPU time 1.03 seconds
Started Aug 13 06:47:57 PM PDT 24
Finished Aug 13 06:47:58 PM PDT 24
Peak memory 207260 kb
Host smart-3a2e6277-a20c-4f84-8837-2e43c2d2ae5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237780210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3237780210
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.767904617
Short name T1108
Test name
Test status
Simulation time 129847286 ps
CPU time 2.23 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 215468 kb
Host smart-85d28089-b708-4439-b377-e5fa6a93eeb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767904617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.767904617
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2237659665
Short name T1048
Test name
Test status
Simulation time 483424196 ps
CPU time 1.38 seconds
Started Aug 13 06:47:59 PM PDT 24
Finished Aug 13 06:48:00 PM PDT 24
Peak memory 215540 kb
Host smart-02f34ddd-382a-46db-89b7-d4ed70e895d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237659665 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2237659665
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2602566179
Short name T1009
Test name
Test status
Simulation time 17918944 ps
CPU time 0.82 seconds
Started Aug 13 06:48:18 PM PDT 24
Finished Aug 13 06:48:19 PM PDT 24
Peak memory 207012 kb
Host smart-6ab31486-0c79-4714-9137-ef77e10c0fde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602566179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2602566179
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2913803265
Short name T993
Test name
Test status
Simulation time 84096238 ps
CPU time 0.82 seconds
Started Aug 13 06:48:10 PM PDT 24
Finished Aug 13 06:48:11 PM PDT 24
Peak memory 207084 kb
Host smart-0d8aee04-6023-4538-b849-26ce5f973aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913803265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2913803265
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.150556718
Short name T1085
Test name
Test status
Simulation time 73746144 ps
CPU time 0.95 seconds
Started Aug 13 06:48:06 PM PDT 24
Finished Aug 13 06:48:07 PM PDT 24
Peak memory 207240 kb
Host smart-cda4817a-39dd-4854-8c7c-210509a9e37f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150556718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.150556718
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3451568759
Short name T1012
Test name
Test status
Simulation time 1027734427 ps
CPU time 2.84 seconds
Started Aug 13 06:48:11 PM PDT 24
Finished Aug 13 06:48:15 PM PDT 24
Peak memory 215476 kb
Host smart-6fe72cf5-492f-49f8-b0f2-7be0a713ada9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451568759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3451568759
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1480101358
Short name T293
Test name
Test status
Simulation time 291594526 ps
CPU time 5.43 seconds
Started Aug 13 06:47:56 PM PDT 24
Finished Aug 13 06:48:02 PM PDT 24
Peak memory 207236 kb
Host smart-4d76aeac-a7dd-448c-9a8e-a7d329c3a869
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480101358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1480101358
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3768502815
Short name T1102
Test name
Test status
Simulation time 122415937 ps
CPU time 1.43 seconds
Started Aug 13 06:47:58 PM PDT 24
Finished Aug 13 06:47:59 PM PDT 24
Peak memory 215512 kb
Host smart-b5d42991-c5d0-465d-b7bf-72a2de7aeee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768502815 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3768502815
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3801392584
Short name T263
Test name
Test status
Simulation time 196379893 ps
CPU time 0.92 seconds
Started Aug 13 06:48:15 PM PDT 24
Finished Aug 13 06:48:16 PM PDT 24
Peak memory 207172 kb
Host smart-bd13c6ab-b62d-4179-aad8-a33a868733fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801392584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3801392584
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1006616202
Short name T1081
Test name
Test status
Simulation time 13104274 ps
CPU time 0.91 seconds
Started Aug 13 06:48:05 PM PDT 24
Finished Aug 13 06:48:06 PM PDT 24
Peak memory 207072 kb
Host smart-e71568e3-2af8-4dca-8f08-ad16f0466875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006616202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1006616202
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1519488628
Short name T252
Test name
Test status
Simulation time 94793764 ps
CPU time 1.11 seconds
Started Aug 13 06:48:07 PM PDT 24
Finished Aug 13 06:48:08 PM PDT 24
Peak memory 207172 kb
Host smart-b1df2453-fb39-4aef-8790-de8244ee5888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519488628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1519488628
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2049185923
Short name T988
Test name
Test status
Simulation time 43407522 ps
CPU time 2.86 seconds
Started Aug 13 06:48:11 PM PDT 24
Finished Aug 13 06:48:14 PM PDT 24
Peak memory 223592 kb
Host smart-a16797af-c58f-4fe6-869f-47e31df63b83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049185923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2049185923
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2384952917
Short name T292
Test name
Test status
Simulation time 87221741 ps
CPU time 2.42 seconds
Started Aug 13 06:48:19 PM PDT 24
Finished Aug 13 06:48:21 PM PDT 24
Peak memory 207224 kb
Host smart-f7b16c09-185b-4d6b-9acf-c10b2ef1d608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384952917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2384952917
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3022050084
Short name T1092
Test name
Test status
Simulation time 27851564 ps
CPU time 1.32 seconds
Started Aug 13 06:48:11 PM PDT 24
Finished Aug 13 06:48:13 PM PDT 24
Peak memory 215536 kb
Host smart-d8da7a31-8c10-49d1-9f5c-fe91705dc510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022050084 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3022050084
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1324740001
Short name T1025
Test name
Test status
Simulation time 25020746 ps
CPU time 0.88 seconds
Started Aug 13 06:48:09 PM PDT 24
Finished Aug 13 06:48:10 PM PDT 24
Peak memory 207180 kb
Host smart-24f95bc9-727d-44bd-91d4-3f9d9dc653ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324740001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1324740001
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1284908503
Short name T990
Test name
Test status
Simulation time 19597749 ps
CPU time 0.86 seconds
Started Aug 13 06:48:08 PM PDT 24
Finished Aug 13 06:48:14 PM PDT 24
Peak memory 207052 kb
Host smart-5cadcd71-65a0-44a9-9f1b-68704f787273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284908503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1284908503
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4069941999
Short name T1086
Test name
Test status
Simulation time 106333803 ps
CPU time 1.31 seconds
Started Aug 13 06:48:07 PM PDT 24
Finished Aug 13 06:48:09 PM PDT 24
Peak memory 207232 kb
Host smart-dc4cdfc0-03c5-4440-8cf0-34f3fe9904fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069941999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.4069941999
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2948323186
Short name T1010
Test name
Test status
Simulation time 350364253 ps
CPU time 3.11 seconds
Started Aug 13 06:47:59 PM PDT 24
Finished Aug 13 06:48:06 PM PDT 24
Peak memory 215440 kb
Host smart-64327962-085f-4e7a-8ed6-a74971f762a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948323186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2948323186
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3693698669
Short name T288
Test name
Test status
Simulation time 160544477 ps
CPU time 2.04 seconds
Started Aug 13 06:48:11 PM PDT 24
Finished Aug 13 06:48:13 PM PDT 24
Peak memory 207268 kb
Host smart-a5eac29a-57bc-4247-8e0b-9630eeecf4e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693698669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3693698669
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2736822632
Short name T261
Test name
Test status
Simulation time 61455561 ps
CPU time 1.18 seconds
Started Aug 13 06:48:05 PM PDT 24
Finished Aug 13 06:48:07 PM PDT 24
Peak memory 207176 kb
Host smart-b64b387a-6ed3-4841-8867-1fc16a4c615b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736822632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2736822632
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1699603175
Short name T266
Test name
Test status
Simulation time 63268053 ps
CPU time 1.98 seconds
Started Aug 13 06:48:10 PM PDT 24
Finished Aug 13 06:48:12 PM PDT 24
Peak memory 207284 kb
Host smart-6c16453a-82f8-4e41-9a4f-a6659eb9af4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699603175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1699603175
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.4010329971
Short name T255
Test name
Test status
Simulation time 14207113 ps
CPU time 0.87 seconds
Started Aug 13 06:48:06 PM PDT 24
Finished Aug 13 06:48:07 PM PDT 24
Peak memory 207156 kb
Host smart-64babe3c-8f4f-4622-ad13-85a38ef5bd5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010329971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.4010329971
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.265073005
Short name T1089
Test name
Test status
Simulation time 43708400 ps
CPU time 1.21 seconds
Started Aug 13 06:47:55 PM PDT 24
Finished Aug 13 06:47:56 PM PDT 24
Peak memory 215504 kb
Host smart-db75db86-8edd-46e7-8a34-b71f874310df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265073005 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.265073005
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2475944373
Short name T1054
Test name
Test status
Simulation time 15547602 ps
CPU time 0.95 seconds
Started Aug 13 06:48:08 PM PDT 24
Finished Aug 13 06:48:09 PM PDT 24
Peak memory 207188 kb
Host smart-6c51ae1d-8389-46f0-afab-7c5d03e81d64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475944373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2475944373
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2764925509
Short name T1046
Test name
Test status
Simulation time 48611311 ps
CPU time 0.8 seconds
Started Aug 13 06:47:54 PM PDT 24
Finished Aug 13 06:47:55 PM PDT 24
Peak memory 206892 kb
Host smart-2481f633-4dec-4f0d-a7b7-5012d9e46680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764925509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2764925509
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.102408336
Short name T1109
Test name
Test status
Simulation time 31160643 ps
CPU time 1.34 seconds
Started Aug 13 06:48:15 PM PDT 24
Finished Aug 13 06:48:16 PM PDT 24
Peak memory 207240 kb
Host smart-76041807-086c-4f84-8e0a-973848196bbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102408336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.102408336
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3520390696
Short name T1060
Test name
Test status
Simulation time 101213954 ps
CPU time 2.11 seconds
Started Aug 13 06:47:55 PM PDT 24
Finished Aug 13 06:47:57 PM PDT 24
Peak memory 215388 kb
Host smart-be9b4bbe-f96d-44e9-81dd-8589a38bdf09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520390696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3520390696
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2227355344
Short name T1105
Test name
Test status
Simulation time 105501210 ps
CPU time 2.57 seconds
Started Aug 13 06:48:03 PM PDT 24
Finished Aug 13 06:48:05 PM PDT 24
Peak memory 207360 kb
Host smart-ef28df9d-388b-4a76-a8e3-2c0004b34397
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227355344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2227355344
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2818241730
Short name T1039
Test name
Test status
Simulation time 26720542 ps
CPU time 0.89 seconds
Started Aug 13 06:48:04 PM PDT 24
Finished Aug 13 06:48:05 PM PDT 24
Peak memory 207076 kb
Host smart-f2a7a3c7-db70-4b60-8488-c6b24d02a98e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818241730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2818241730
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2939258378
Short name T1071
Test name
Test status
Simulation time 12744946 ps
CPU time 0.84 seconds
Started Aug 13 06:48:14 PM PDT 24
Finished Aug 13 06:48:15 PM PDT 24
Peak memory 207092 kb
Host smart-5fa38db4-d62f-43e6-959b-0a10d5ece9cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939258378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2939258378
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3215619817
Short name T1084
Test name
Test status
Simulation time 41224585 ps
CPU time 0.87 seconds
Started Aug 13 06:48:22 PM PDT 24
Finished Aug 13 06:48:23 PM PDT 24
Peak memory 207092 kb
Host smart-1b888a5e-b1dc-4bd1-b138-2e585de9d5e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215619817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3215619817
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2664864316
Short name T1051
Test name
Test status
Simulation time 23757615 ps
CPU time 0.85 seconds
Started Aug 13 06:48:17 PM PDT 24
Finished Aug 13 06:48:18 PM PDT 24
Peak memory 207092 kb
Host smart-d6170422-a5ed-4bb5-97df-5b1e44158516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664864316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2664864316
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3301729070
Short name T1008
Test name
Test status
Simulation time 43489740 ps
CPU time 0.77 seconds
Started Aug 13 06:48:03 PM PDT 24
Finished Aug 13 06:48:04 PM PDT 24
Peak memory 206920 kb
Host smart-19c45147-0988-4a80-8b47-e1931754e53f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301729070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3301729070
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.943700023
Short name T1028
Test name
Test status
Simulation time 34198548 ps
CPU time 0.83 seconds
Started Aug 13 06:48:05 PM PDT 24
Finished Aug 13 06:48:06 PM PDT 24
Peak memory 207048 kb
Host smart-4090b379-c707-4440-a03e-096b15e20475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943700023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.943700023
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1482212581
Short name T989
Test name
Test status
Simulation time 59406502 ps
CPU time 0.92 seconds
Started Aug 13 06:48:11 PM PDT 24
Finished Aug 13 06:48:12 PM PDT 24
Peak memory 207076 kb
Host smart-0cdd01e5-0051-4134-a9c8-29cc8395bce2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482212581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1482212581
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.99076637
Short name T997
Test name
Test status
Simulation time 16743365 ps
CPU time 0.9 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 207076 kb
Host smart-b660b24d-2ac9-4da3-9280-d9a72c1cacaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99076637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.99076637
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2354334140
Short name T1007
Test name
Test status
Simulation time 172793117 ps
CPU time 0.89 seconds
Started Aug 13 06:48:09 PM PDT 24
Finished Aug 13 06:48:10 PM PDT 24
Peak memory 207024 kb
Host smart-45573c2a-dc53-4c14-9538-db7e19905774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354334140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2354334140
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2877397090
Short name T1026
Test name
Test status
Simulation time 46990800 ps
CPU time 0.87 seconds
Started Aug 13 06:48:09 PM PDT 24
Finished Aug 13 06:48:10 PM PDT 24
Peak memory 207096 kb
Host smart-86eccc30-c79e-43d1-97a4-08f9875bc799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877397090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2877397090
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.638276929
Short name T257
Test name
Test status
Simulation time 663333004 ps
CPU time 1.54 seconds
Started Aug 13 06:47:54 PM PDT 24
Finished Aug 13 06:47:56 PM PDT 24
Peak memory 207148 kb
Host smart-d46865f8-26e7-4670-b25b-79dce2dcfdb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638276929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.638276929
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3351560240
Short name T1082
Test name
Test status
Simulation time 132280680 ps
CPU time 1.96 seconds
Started Aug 13 06:48:07 PM PDT 24
Finished Aug 13 06:48:09 PM PDT 24
Peak memory 207240 kb
Host smart-ad938b09-75e6-4401-9245-523562bd6e8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351560240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3351560240
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2472606398
Short name T258
Test name
Test status
Simulation time 19051487 ps
CPU time 0.8 seconds
Started Aug 13 06:48:00 PM PDT 24
Finished Aug 13 06:48:01 PM PDT 24
Peak memory 206984 kb
Host smart-cb67a659-85c2-488f-9ddb-450219f07014
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472606398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2472606398
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.765087803
Short name T985
Test name
Test status
Simulation time 179662160 ps
CPU time 1.17 seconds
Started Aug 13 06:48:06 PM PDT 24
Finished Aug 13 06:48:07 PM PDT 24
Peak memory 215404 kb
Host smart-92c2af12-9fdf-48fc-b097-81b4241896b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765087803 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.765087803
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1728717558
Short name T1096
Test name
Test status
Simulation time 12495590 ps
CPU time 0.87 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:59 PM PDT 24
Peak memory 207204 kb
Host smart-821541dd-307c-4e6e-b994-1154c862bb18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728717558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1728717558
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1702955727
Short name T1023
Test name
Test status
Simulation time 14725294 ps
CPU time 0.85 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:54 PM PDT 24
Peak memory 207072 kb
Host smart-a5f7afbe-5885-4b1e-ad20-f27cdbc67fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702955727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1702955727
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3232426728
Short name T251
Test name
Test status
Simulation time 75925160 ps
CPU time 1.32 seconds
Started Aug 13 06:48:02 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 207236 kb
Host smart-2a0637ab-a49e-4ad2-9284-c2892357d812
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232426728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3232426728
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3051990896
Short name T1075
Test name
Test status
Simulation time 98385897 ps
CPU time 2.16 seconds
Started Aug 13 06:47:58 PM PDT 24
Finished Aug 13 06:48:00 PM PDT 24
Peak memory 215480 kb
Host smart-0e9d4dbc-a86c-4f90-8752-1e82ac6d4f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051990896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3051990896
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2810727160
Short name T1065
Test name
Test status
Simulation time 50182668 ps
CPU time 1.63 seconds
Started Aug 13 06:48:04 PM PDT 24
Finished Aug 13 06:48:06 PM PDT 24
Peak memory 207276 kb
Host smart-6e77dae0-57b3-4e1a-929a-dcfaba3936e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810727160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2810727160
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.239104229
Short name T999
Test name
Test status
Simulation time 32283670 ps
CPU time 0.81 seconds
Started Aug 13 06:48:11 PM PDT 24
Finished Aug 13 06:48:12 PM PDT 24
Peak memory 207080 kb
Host smart-2b95877e-be9e-40f0-8be0-7b9cf1ce70db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239104229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.239104229
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2509091744
Short name T1066
Test name
Test status
Simulation time 154745936 ps
CPU time 0.87 seconds
Started Aug 13 06:48:14 PM PDT 24
Finished Aug 13 06:48:15 PM PDT 24
Peak memory 206924 kb
Host smart-e030c44c-13b7-4eb6-ad96-1774122c61ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509091744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2509091744
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.494231605
Short name T981
Test name
Test status
Simulation time 14907775 ps
CPU time 0.96 seconds
Started Aug 13 06:48:08 PM PDT 24
Finished Aug 13 06:48:10 PM PDT 24
Peak memory 207088 kb
Host smart-4bc10633-778a-4f70-9ae0-f0715b81e615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494231605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.494231605
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.4193726527
Short name T1032
Test name
Test status
Simulation time 49199859 ps
CPU time 0.88 seconds
Started Aug 13 06:48:03 PM PDT 24
Finished Aug 13 06:48:04 PM PDT 24
Peak memory 207092 kb
Host smart-3c13588f-045f-46d2-8afb-b875a46a45d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193726527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.4193726527
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.4075476390
Short name T1050
Test name
Test status
Simulation time 14947507 ps
CPU time 0.9 seconds
Started Aug 13 06:48:21 PM PDT 24
Finished Aug 13 06:48:22 PM PDT 24
Peak memory 207048 kb
Host smart-1a54783c-8cd5-4dbd-b286-c994f5a318a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075476390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.4075476390
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3023938956
Short name T1044
Test name
Test status
Simulation time 41748091 ps
CPU time 0.85 seconds
Started Aug 13 06:48:15 PM PDT 24
Finished Aug 13 06:48:16 PM PDT 24
Peak memory 207160 kb
Host smart-49b8a2dd-2adf-4e0e-a8fd-cb1049c041a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023938956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3023938956
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2561038248
Short name T982
Test name
Test status
Simulation time 13338040 ps
CPU time 0.91 seconds
Started Aug 13 06:48:11 PM PDT 24
Finished Aug 13 06:48:12 PM PDT 24
Peak memory 207088 kb
Host smart-4788f0ef-fdb7-449b-b915-864fcfd98a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561038248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2561038248
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.236197879
Short name T1003
Test name
Test status
Simulation time 16646467 ps
CPU time 0.81 seconds
Started Aug 13 06:48:08 PM PDT 24
Finished Aug 13 06:48:09 PM PDT 24
Peak memory 207084 kb
Host smart-5676e0e4-77ac-404b-990c-c10bb96d8ac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236197879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.236197879
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3747169068
Short name T1005
Test name
Test status
Simulation time 17749574 ps
CPU time 0.99 seconds
Started Aug 13 06:48:29 PM PDT 24
Finished Aug 13 06:48:30 PM PDT 24
Peak memory 207084 kb
Host smart-7cffb20b-e33a-4c5c-9abf-5edf3bf64598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747169068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3747169068
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.331496853
Short name T983
Test name
Test status
Simulation time 16140871 ps
CPU time 0.89 seconds
Started Aug 13 06:48:12 PM PDT 24
Finished Aug 13 06:48:13 PM PDT 24
Peak memory 207084 kb
Host smart-598ce773-2f09-4bee-b998-a2f97a2e8600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331496853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.331496853
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2534830008
Short name T998
Test name
Test status
Simulation time 18533735 ps
CPU time 0.98 seconds
Started Aug 13 06:48:05 PM PDT 24
Finished Aug 13 06:48:06 PM PDT 24
Peak memory 207116 kb
Host smart-497c2ba9-b909-470c-99f4-813e285a5aac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534830008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2534830008
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.544681803
Short name T267
Test name
Test status
Simulation time 112585677 ps
CPU time 3.29 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:05 PM PDT 24
Peak memory 207256 kb
Host smart-14144679-6825-482f-baca-ee355aa65e90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544681803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.544681803
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4206381602
Short name T1045
Test name
Test status
Simulation time 29661657 ps
CPU time 0.97 seconds
Started Aug 13 06:47:51 PM PDT 24
Finished Aug 13 06:47:52 PM PDT 24
Peak memory 207164 kb
Host smart-fb51f956-0384-4988-a7f2-4da378035492
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206381602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.4206381602
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.325687337
Short name T1100
Test name
Test status
Simulation time 102675405 ps
CPU time 1.36 seconds
Started Aug 13 06:48:00 PM PDT 24
Finished Aug 13 06:48:02 PM PDT 24
Peak memory 223464 kb
Host smart-3b023f8d-c7f4-484a-aea8-7315edf86ec0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325687337 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.325687337
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1239575802
Short name T1038
Test name
Test status
Simulation time 102775118 ps
CPU time 0.84 seconds
Started Aug 13 06:47:57 PM PDT 24
Finished Aug 13 06:47:58 PM PDT 24
Peak memory 206936 kb
Host smart-e1e6e599-5bf5-4fac-b105-26ffa4650f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239575802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1239575802
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4132401286
Short name T1020
Test name
Test status
Simulation time 96378525 ps
CPU time 1.06 seconds
Started Aug 13 06:48:02 PM PDT 24
Finished Aug 13 06:48:04 PM PDT 24
Peak memory 207304 kb
Host smart-08dd9e17-1954-4870-9138-5fcdd17f7aa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132401286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.4132401286
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1901111666
Short name T1047
Test name
Test status
Simulation time 122092427 ps
CPU time 4.3 seconds
Started Aug 13 06:48:16 PM PDT 24
Finished Aug 13 06:48:21 PM PDT 24
Peak memory 215496 kb
Host smart-7dd12939-9053-4a87-9824-5cc8eade7031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901111666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1901111666
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.904100126
Short name T284
Test name
Test status
Simulation time 479947120 ps
CPU time 2.33 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:56 PM PDT 24
Peak memory 207188 kb
Host smart-2202cd1f-fe24-459c-94d1-8d5533ce5338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904100126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.904100126
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1024913623
Short name T1040
Test name
Test status
Simulation time 46311444 ps
CPU time 0.87 seconds
Started Aug 13 06:48:07 PM PDT 24
Finished Aug 13 06:48:08 PM PDT 24
Peak memory 207028 kb
Host smart-c2fb4877-25fe-4db7-b7f5-74a8fc77705d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024913623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1024913623
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3048180994
Short name T1030
Test name
Test status
Simulation time 20990106 ps
CPU time 0.83 seconds
Started Aug 13 06:48:25 PM PDT 24
Finished Aug 13 06:48:26 PM PDT 24
Peak memory 206892 kb
Host smart-4d16e007-fca1-4d79-9e3d-57c4670eec24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048180994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3048180994
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.880692890
Short name T1074
Test name
Test status
Simulation time 13807280 ps
CPU time 0.89 seconds
Started Aug 13 06:48:02 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 207032 kb
Host smart-d7b8f843-ea66-4ade-8f2b-c9d099a4edd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880692890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.880692890
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3746122822
Short name T987
Test name
Test status
Simulation time 52560296 ps
CPU time 0.91 seconds
Started Aug 13 06:48:04 PM PDT 24
Finished Aug 13 06:48:05 PM PDT 24
Peak memory 207092 kb
Host smart-31e85d48-e684-421d-b4f6-51db278930e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746122822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3746122822
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2234444738
Short name T1091
Test name
Test status
Simulation time 12768835 ps
CPU time 0.88 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:02 PM PDT 24
Peak memory 207092 kb
Host smart-984f5353-fe09-43c9-ad27-a37e2690a468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234444738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2234444738
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3620584907
Short name T1004
Test name
Test status
Simulation time 22886238 ps
CPU time 0.87 seconds
Started Aug 13 06:48:00 PM PDT 24
Finished Aug 13 06:48:04 PM PDT 24
Peak memory 207056 kb
Host smart-ba3b81a7-bfe0-4855-8ce1-5a427b86acf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620584907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3620584907
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2080765687
Short name T1073
Test name
Test status
Simulation time 47459416 ps
CPU time 0.85 seconds
Started Aug 13 06:48:29 PM PDT 24
Finished Aug 13 06:48:30 PM PDT 24
Peak memory 207048 kb
Host smart-8cf20435-6359-43d9-bfd2-534627ab13b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080765687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2080765687
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1347163049
Short name T1011
Test name
Test status
Simulation time 26811373 ps
CPU time 0.93 seconds
Started Aug 13 06:48:03 PM PDT 24
Finished Aug 13 06:48:04 PM PDT 24
Peak memory 207084 kb
Host smart-20ce2eb2-e8d1-4af6-bab1-7e3a01f503ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347163049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1347163049
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1233881857
Short name T1033
Test name
Test status
Simulation time 57682084 ps
CPU time 0.85 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:02 PM PDT 24
Peak memory 206928 kb
Host smart-eaa3a824-fffb-4395-9b63-247ff972aa20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233881857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1233881857
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.177691478
Short name T1024
Test name
Test status
Simulation time 53821726 ps
CPU time 0.84 seconds
Started Aug 13 06:47:56 PM PDT 24
Finished Aug 13 06:47:57 PM PDT 24
Peak memory 207084 kb
Host smart-1946588e-e8f5-43ce-b85b-c4511c91f86d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177691478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.177691478
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3947783679
Short name T1061
Test name
Test status
Simulation time 97904585 ps
CPU time 1.24 seconds
Started Aug 13 06:47:52 PM PDT 24
Finished Aug 13 06:47:54 PM PDT 24
Peak memory 215504 kb
Host smart-8765f35f-7d11-4c54-b41f-631ea90086e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947783679 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3947783679
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3910429559
Short name T1052
Test name
Test status
Simulation time 16452508 ps
CPU time 0.92 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:54 PM PDT 24
Peak memory 207252 kb
Host smart-0f4fc2b4-2f5c-41ad-bbff-84c816f37910
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910429559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3910429559
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1022338532
Short name T1002
Test name
Test status
Simulation time 25882176 ps
CPU time 0.85 seconds
Started Aug 13 06:48:04 PM PDT 24
Finished Aug 13 06:48:05 PM PDT 24
Peak memory 207144 kb
Host smart-b0936070-ffdc-4858-b796-a7c14a8db413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022338532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1022338532
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4272533562
Short name T268
Test name
Test status
Simulation time 28464835 ps
CPU time 0.96 seconds
Started Aug 13 06:47:59 PM PDT 24
Finished Aug 13 06:48:00 PM PDT 24
Peak memory 207264 kb
Host smart-695899d7-f534-4bfc-88af-6b6e44420d00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272533562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.4272533562
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3791038140
Short name T991
Test name
Test status
Simulation time 89561346 ps
CPU time 3.08 seconds
Started Aug 13 06:48:09 PM PDT 24
Finished Aug 13 06:48:13 PM PDT 24
Peak memory 215412 kb
Host smart-ce2dab3d-7ab8-41ce-ac8c-b951434bedfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791038140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3791038140
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1060720710
Short name T1076
Test name
Test status
Simulation time 191666845 ps
CPU time 1.53 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:54 PM PDT 24
Peak memory 207256 kb
Host smart-aae4a638-4d73-4941-875a-a00ffb95836b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060720710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1060720710
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2982880914
Short name T1019
Test name
Test status
Simulation time 28396240 ps
CPU time 1.37 seconds
Started Aug 13 06:47:57 PM PDT 24
Finished Aug 13 06:47:58 PM PDT 24
Peak memory 215532 kb
Host smart-e3cfb8d0-fa95-4ea0-a21c-27858e5ab72e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982880914 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2982880914
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.740395244
Short name T260
Test name
Test status
Simulation time 16206911 ps
CPU time 0.97 seconds
Started Aug 13 06:47:50 PM PDT 24
Finished Aug 13 06:47:51 PM PDT 24
Peak memory 207168 kb
Host smart-39becfa0-45d9-40bb-a77c-f1fa614aa5ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740395244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.740395244
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3661001039
Short name T1057
Test name
Test status
Simulation time 14649139 ps
CPU time 0.88 seconds
Started Aug 13 06:48:13 PM PDT 24
Finished Aug 13 06:48:14 PM PDT 24
Peak memory 207040 kb
Host smart-a36a0749-361f-47dd-b4d5-df3ddd87c064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661001039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3661001039
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2130336605
Short name T1094
Test name
Test status
Simulation time 43182330 ps
CPU time 1.55 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:54 PM PDT 24
Peak memory 207156 kb
Host smart-ddbe87a6-6e4b-4430-8319-d89c88b3915e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130336605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2130336605
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.174985371
Short name T1042
Test name
Test status
Simulation time 621400731 ps
CPU time 4.61 seconds
Started Aug 13 06:47:58 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 215428 kb
Host smart-49320e5c-c655-44e2-96aa-6a8b36bdf357
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174985371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.174985371
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2272425301
Short name T1021
Test name
Test status
Simulation time 138257217 ps
CPU time 2.16 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 215436 kb
Host smart-9aad1674-ce9a-45c2-ad12-c254dcd05029
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272425301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2272425301
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3803886277
Short name T1110
Test name
Test status
Simulation time 28535257 ps
CPU time 1 seconds
Started Aug 13 06:47:59 PM PDT 24
Finished Aug 13 06:48:00 PM PDT 24
Peak memory 215456 kb
Host smart-c6fc56b2-e1cb-4dea-bca0-a349ec5255b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803886277 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3803886277
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.4052535366
Short name T1015
Test name
Test status
Simulation time 44965496 ps
CPU time 0.86 seconds
Started Aug 13 06:47:54 PM PDT 24
Finished Aug 13 06:47:55 PM PDT 24
Peak memory 207112 kb
Host smart-9261c6ed-1c4c-4649-9edb-52be97e6c5c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052535366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.4052535366
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1976344740
Short name T1088
Test name
Test status
Simulation time 43970268 ps
CPU time 0.78 seconds
Started Aug 13 06:47:55 PM PDT 24
Finished Aug 13 06:47:56 PM PDT 24
Peak memory 206884 kb
Host smart-b1cb966e-fa4f-4d57-b870-ef2603c55585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976344740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1976344740
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.249354170
Short name T1014
Test name
Test status
Simulation time 76330016 ps
CPU time 1.06 seconds
Started Aug 13 06:47:49 PM PDT 24
Finished Aug 13 06:47:50 PM PDT 24
Peak memory 207184 kb
Host smart-f61f36a5-b8a0-4994-a0c5-c863f3a77ba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249354170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.249354170
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1310315913
Short name T1062
Test name
Test status
Simulation time 28989594 ps
CPU time 1.9 seconds
Started Aug 13 06:48:03 PM PDT 24
Finished Aug 13 06:48:05 PM PDT 24
Peak memory 215468 kb
Host smart-c6e32415-b178-452d-8842-45b89991a84a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310315913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1310315913
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2545422056
Short name T291
Test name
Test status
Simulation time 193942316 ps
CPU time 2.57 seconds
Started Aug 13 06:47:55 PM PDT 24
Finished Aug 13 06:47:58 PM PDT 24
Peak memory 207196 kb
Host smart-458a435c-3bcb-4fb9-b492-30fb04e87c07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545422056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2545422056
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.866511369
Short name T1069
Test name
Test status
Simulation time 27524714 ps
CPU time 1.67 seconds
Started Aug 13 06:48:06 PM PDT 24
Finished Aug 13 06:48:08 PM PDT 24
Peak memory 215468 kb
Host smart-eead8a35-d440-42f7-b52e-d8f99859f02c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866511369 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.866511369
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3558934119
Short name T254
Test name
Test status
Simulation time 74623940 ps
CPU time 0.81 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 206944 kb
Host smart-03f85d0a-566c-40e1-945a-f2b06120365c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558934119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3558934119
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3544238776
Short name T1095
Test name
Test status
Simulation time 19546053 ps
CPU time 0.82 seconds
Started Aug 13 06:48:03 PM PDT 24
Finished Aug 13 06:48:04 PM PDT 24
Peak memory 207060 kb
Host smart-3e8630f8-004d-4e29-8963-124168ae71bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544238776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3544238776
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.355836074
Short name T1098
Test name
Test status
Simulation time 32537821 ps
CPU time 1.08 seconds
Started Aug 13 06:48:16 PM PDT 24
Finished Aug 13 06:48:18 PM PDT 24
Peak memory 207192 kb
Host smart-aa4e5bdd-0c6f-4209-9c59-63c06222a5c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355836074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.355836074
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2772197136
Short name T1063
Test name
Test status
Simulation time 22090659 ps
CPU time 1.47 seconds
Started Aug 13 06:47:51 PM PDT 24
Finished Aug 13 06:47:52 PM PDT 24
Peak memory 219264 kb
Host smart-1876cfb0-c3b7-4cbf-a101-96d8a1f16f47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772197136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2772197136
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1131753635
Short name T1093
Test name
Test status
Simulation time 47657542 ps
CPU time 1.57 seconds
Started Aug 13 06:47:51 PM PDT 24
Finished Aug 13 06:47:53 PM PDT 24
Peak memory 207320 kb
Host smart-5013e556-9e49-4bb5-843c-b5e29cf23903
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131753635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1131753635
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3112424414
Short name T1029
Test name
Test status
Simulation time 16062179 ps
CPU time 1 seconds
Started Aug 13 06:48:11 PM PDT 24
Finished Aug 13 06:48:12 PM PDT 24
Peak memory 207264 kb
Host smart-1f2b3a2c-559a-46e9-841f-d1f5b522a81c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112424414 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3112424414
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2738762651
Short name T1064
Test name
Test status
Simulation time 24411038 ps
CPU time 0.86 seconds
Started Aug 13 06:47:54 PM PDT 24
Finished Aug 13 06:47:55 PM PDT 24
Peak memory 207208 kb
Host smart-f0c1692f-dd7f-4ac8-9070-7728416a1366
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738762651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2738762651
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2476308543
Short name T992
Test name
Test status
Simulation time 42097163 ps
CPU time 0.8 seconds
Started Aug 13 06:48:09 PM PDT 24
Finished Aug 13 06:48:10 PM PDT 24
Peak memory 206860 kb
Host smart-b1991060-a342-47ff-b537-72294cf5b6dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476308543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2476308543
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3198813047
Short name T269
Test name
Test status
Simulation time 52085690 ps
CPU time 0.98 seconds
Started Aug 13 06:48:06 PM PDT 24
Finished Aug 13 06:48:07 PM PDT 24
Peak memory 207216 kb
Host smart-286ddea6-a2d7-4bce-82d8-8c4fe5cf5514
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198813047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3198813047
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2270432051
Short name T1000
Test name
Test status
Simulation time 136991614 ps
CPU time 1.62 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 215428 kb
Host smart-f4a258be-8537-411a-8922-8ffd2dee9e1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270432051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2270432051
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.182986089
Short name T289
Test name
Test status
Simulation time 168975223 ps
CPU time 2.49 seconds
Started Aug 13 06:48:06 PM PDT 24
Finished Aug 13 06:48:09 PM PDT 24
Peak memory 207216 kb
Host smart-f4b1bf0e-72ef-4bee-8726-d5dc0acfe07b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182986089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.182986089
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3374867541
Short name T924
Test name
Test status
Simulation time 26048415 ps
CPU time 1.24 seconds
Started Aug 13 06:45:10 PM PDT 24
Finished Aug 13 06:45:11 PM PDT 24
Peak memory 220384 kb
Host smart-6e637ece-3aca-43b7-9393-9bb055c07f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374867541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3374867541
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.869359486
Short name T589
Test name
Test status
Simulation time 23153717 ps
CPU time 0.84 seconds
Started Aug 13 06:45:11 PM PDT 24
Finished Aug 13 06:45:12 PM PDT 24
Peak memory 215268 kb
Host smart-632e31e3-57ee-4043-9eee-4e538f74b600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869359486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.869359486
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1564041255
Short name T437
Test name
Test status
Simulation time 16635961 ps
CPU time 0.81 seconds
Started Aug 13 06:45:31 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 215752 kb
Host smart-292e0ccb-a47f-4ca8-9cc1-eb16ccf7a4ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564041255 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1564041255
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3689308569
Short name T615
Test name
Test status
Simulation time 23715174 ps
CPU time 1.07 seconds
Started Aug 13 06:44:55 PM PDT 24
Finished Aug 13 06:44:56 PM PDT 24
Peak memory 218564 kb
Host smart-72db095a-2665-4734-bdcb-f409a7fc400c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689308569 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3689308569
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2785524074
Short name T566
Test name
Test status
Simulation time 29540502 ps
CPU time 1.28 seconds
Started Aug 13 06:45:11 PM PDT 24
Finished Aug 13 06:45:12 PM PDT 24
Peak memory 219776 kb
Host smart-4196e15c-bc46-414f-9b73-cedeba3ca59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785524074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2785524074
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2053132181
Short name T47
Test name
Test status
Simulation time 53015033 ps
CPU time 1.61 seconds
Started Aug 13 06:45:03 PM PDT 24
Finished Aug 13 06:45:05 PM PDT 24
Peak memory 218764 kb
Host smart-f9f38cfa-813f-457d-a701-640c14d3ea8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053132181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2053132181
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.4127655972
Short name T113
Test name
Test status
Simulation time 21359070 ps
CPU time 1.07 seconds
Started Aug 13 06:45:10 PM PDT 24
Finished Aug 13 06:45:11 PM PDT 24
Peak memory 216052 kb
Host smart-0b2684c1-bdc4-4bc9-8766-5c52101a22ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127655972 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.4127655972
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1176627560
Short name T694
Test name
Test status
Simulation time 18403392 ps
CPU time 1.01 seconds
Started Aug 13 06:45:06 PM PDT 24
Finished Aug 13 06:45:07 PM PDT 24
Peak memory 207380 kb
Host smart-4917ed4f-58cf-42de-a982-1d4f566f86c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176627560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1176627560
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3697248609
Short name T70
Test name
Test status
Simulation time 2181052992 ps
CPU time 4.15 seconds
Started Aug 13 06:45:08 PM PDT 24
Finished Aug 13 06:45:12 PM PDT 24
Peak memory 237096 kb
Host smart-69439a19-3d03-430f-a37c-d30f9a16e265
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697248609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3697248609
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.1412945443
Short name T560
Test name
Test status
Simulation time 69641022 ps
CPU time 0.9 seconds
Started Aug 13 06:45:05 PM PDT 24
Finished Aug 13 06:45:08 PM PDT 24
Peak memory 215596 kb
Host smart-8f68932e-dd8b-43e5-9e29-0dee11a40d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412945443 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1412945443
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3522109780
Short name T240
Test name
Test status
Simulation time 217426298 ps
CPU time 1.68 seconds
Started Aug 13 06:45:03 PM PDT 24
Finished Aug 13 06:45:05 PM PDT 24
Peak memory 217612 kb
Host smart-af257a64-5206-4c5c-a03f-9f40d09dde46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522109780 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3522109780
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3246450245
Short name T225
Test name
Test status
Simulation time 15040968617 ps
CPU time 88.83 seconds
Started Aug 13 06:45:07 PM PDT 24
Finished Aug 13 06:46:36 PM PDT 24
Peak memory 219040 kb
Host smart-9dcd5265-c2f9-498b-826f-bf1371f965d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246450245 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3246450245
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1126835412
Short name T381
Test name
Test status
Simulation time 43757442 ps
CPU time 1.18 seconds
Started Aug 13 06:45:10 PM PDT 24
Finished Aug 13 06:45:11 PM PDT 24
Peak memory 221360 kb
Host smart-a59af6e8-a3e6-4e4b-8131-fd11111b26d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126835412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1126835412
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.2663009374
Short name T361
Test name
Test status
Simulation time 44373011 ps
CPU time 0.86 seconds
Started Aug 13 06:45:16 PM PDT 24
Finished Aug 13 06:45:17 PM PDT 24
Peak memory 206800 kb
Host smart-25516235-c615-4c05-8aca-bbe5141cc97c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663009374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2663009374
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2158958838
Short name T686
Test name
Test status
Simulation time 56556216 ps
CPU time 0.84 seconds
Started Aug 13 06:45:10 PM PDT 24
Finished Aug 13 06:45:11 PM PDT 24
Peak memory 215720 kb
Host smart-c5c22b64-9d4c-48b6-9f43-0f10d028fdcb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158958838 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2158958838
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_genbits.30456810
Short name T436
Test name
Test status
Simulation time 68291925 ps
CPU time 1.09 seconds
Started Aug 13 06:45:07 PM PDT 24
Finished Aug 13 06:45:08 PM PDT 24
Peak memory 219164 kb
Host smart-19cff952-fae0-4e84-8c22-72ab6eb85d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30456810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.30456810
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.3127218913
Short name T914
Test name
Test status
Simulation time 49325342 ps
CPU time 0.96 seconds
Started Aug 13 06:45:11 PM PDT 24
Finished Aug 13 06:45:12 PM PDT 24
Peak memory 207384 kb
Host smart-a4c3f03e-8ffa-45ff-aa6f-bb077006a58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127218913 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3127218913
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1597512966
Short name T71
Test name
Test status
Simulation time 537109636 ps
CPU time 5.01 seconds
Started Aug 13 06:45:16 PM PDT 24
Finished Aug 13 06:45:21 PM PDT 24
Peak memory 242912 kb
Host smart-cc9b55d5-cb28-49ce-9bd3-43cc2754adbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597512966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1597512966
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2358507652
Short name T658
Test name
Test status
Simulation time 35381756 ps
CPU time 0.89 seconds
Started Aug 13 06:45:21 PM PDT 24
Finished Aug 13 06:45:22 PM PDT 24
Peak memory 207364 kb
Host smart-3eed7439-82f8-4e21-a0f4-c71c20067875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358507652 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2358507652
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.4257117537
Short name T393
Test name
Test status
Simulation time 530507204 ps
CPU time 5.81 seconds
Started Aug 13 06:44:55 PM PDT 24
Finished Aug 13 06:45:01 PM PDT 24
Peak memory 217500 kb
Host smart-c0aee33d-a5a0-461d-a109-31453b950405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257117537 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.4257117537
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2559460213
Short name T539
Test name
Test status
Simulation time 4347498452 ps
CPU time 72.54 seconds
Started Aug 13 06:45:08 PM PDT 24
Finished Aug 13 06:46:20 PM PDT 24
Peak memory 217868 kb
Host smart-60aaebe7-c264-402e-939d-16bd83335993
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559460213 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2559460213
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1252604013
Short name T586
Test name
Test status
Simulation time 178992890 ps
CPU time 1.35 seconds
Started Aug 13 06:45:22 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 219408 kb
Host smart-e9f40fb3-e1ba-487c-b42c-3bbcff945141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252604013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1252604013
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2919204776
Short name T869
Test name
Test status
Simulation time 36295110 ps
CPU time 0.93 seconds
Started Aug 13 06:45:23 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 207076 kb
Host smart-b952c585-0425-42b3-9160-5be466611950
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919204776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2919204776
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1149982779
Short name T965
Test name
Test status
Simulation time 58985907 ps
CPU time 0.84 seconds
Started Aug 13 06:45:28 PM PDT 24
Finished Aug 13 06:45:29 PM PDT 24
Peak memory 216608 kb
Host smart-773b36b8-ea74-47d0-ac59-51058f791750
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149982779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1149982779
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1733507393
Short name T535
Test name
Test status
Simulation time 21758481 ps
CPU time 1.13 seconds
Started Aug 13 06:45:32 PM PDT 24
Finished Aug 13 06:45:33 PM PDT 24
Peak memory 218624 kb
Host smart-326730e5-e336-414f-aba4-84417a20190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733507393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1733507393
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3526308191
Short name T608
Test name
Test status
Simulation time 67242611 ps
CPU time 1.28 seconds
Started Aug 13 06:45:32 PM PDT 24
Finished Aug 13 06:45:34 PM PDT 24
Peak memory 220416 kb
Host smart-fb6a7d39-5b01-453c-9563-d0f7e93d992d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526308191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3526308191
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.1772458143
Short name T866
Test name
Test status
Simulation time 37906906 ps
CPU time 0.93 seconds
Started Aug 13 06:45:28 PM PDT 24
Finished Aug 13 06:45:29 PM PDT 24
Peak memory 215560 kb
Host smart-e9bf22e0-66e6-4eca-aa32-b34ec5f47e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772458143 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1772458143
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.410619150
Short name T613
Test name
Test status
Simulation time 1270699741 ps
CPU time 4.18 seconds
Started Aug 13 06:45:32 PM PDT 24
Finished Aug 13 06:45:36 PM PDT 24
Peak memory 215684 kb
Host smart-c567d3ee-8887-4d3a-95ca-2e78aac9ef82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410619150 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.410619150
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_alert.634319093
Short name T578
Test name
Test status
Simulation time 30722914 ps
CPU time 1.3 seconds
Started Aug 13 06:46:49 PM PDT 24
Finished Aug 13 06:46:51 PM PDT 24
Peak memory 220044 kb
Host smart-4868da9f-49fd-41c2-943e-6189fe711687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634319093 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.634319093
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.2082487696
Short name T50
Test name
Test status
Simulation time 67150603 ps
CPU time 1.55 seconds
Started Aug 13 06:46:37 PM PDT 24
Finished Aug 13 06:46:38 PM PDT 24
Peak memory 218960 kb
Host smart-52e84c16-f114-472a-9ebb-d815040dd7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082487696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2082487696
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.1495976057
Short name T606
Test name
Test status
Simulation time 72605292 ps
CPU time 1.16 seconds
Started Aug 13 06:47:03 PM PDT 24
Finished Aug 13 06:47:04 PM PDT 24
Peak memory 219368 kb
Host smart-c5134593-8219-43ed-8cf1-214367d5fcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495976057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1495976057
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2512060549
Short name T747
Test name
Test status
Simulation time 82762063 ps
CPU time 1.4 seconds
Started Aug 13 06:46:52 PM PDT 24
Finished Aug 13 06:46:54 PM PDT 24
Peak memory 218932 kb
Host smart-0013388d-7e01-4696-9d25-19ae48a61ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512060549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2512060549
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.331667834
Short name T567
Test name
Test status
Simulation time 33111932 ps
CPU time 1.17 seconds
Started Aug 13 06:46:30 PM PDT 24
Finished Aug 13 06:46:31 PM PDT 24
Peak memory 219436 kb
Host smart-9bb33e79-293b-42bb-91a3-b8cbf840570d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331667834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.331667834
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.2750352159
Short name T793
Test name
Test status
Simulation time 32606792 ps
CPU time 1.35 seconds
Started Aug 13 06:46:46 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 217996 kb
Host smart-ce5ff303-00c8-4850-b2b3-27a4a83c1b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750352159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2750352159
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2574175260
Short name T45
Test name
Test status
Simulation time 55268822 ps
CPU time 1.11 seconds
Started Aug 13 06:46:56 PM PDT 24
Finished Aug 13 06:46:57 PM PDT 24
Peak memory 220520 kb
Host smart-16c21585-d991-4471-abf5-61150e46925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574175260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2574175260
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/105.edn_alert.2099355221
Short name T519
Test name
Test status
Simulation time 99405991 ps
CPU time 1.07 seconds
Started Aug 13 06:46:38 PM PDT 24
Finished Aug 13 06:46:40 PM PDT 24
Peak memory 218880 kb
Host smart-6ab842a9-c6c3-4be3-8e83-b0a5724cd938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099355221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2099355221
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/106.edn_alert.3794844771
Short name T217
Test name
Test status
Simulation time 78458971 ps
CPU time 1.13 seconds
Started Aug 13 06:46:54 PM PDT 24
Finished Aug 13 06:46:55 PM PDT 24
Peak memory 220732 kb
Host smart-41dfee87-5182-4315-9916-4e79732ca1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794844771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3794844771
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.1730542685
Short name T766
Test name
Test status
Simulation time 212642968 ps
CPU time 2.53 seconds
Started Aug 13 06:46:47 PM PDT 24
Finished Aug 13 06:46:50 PM PDT 24
Peak memory 217840 kb
Host smart-07f290f5-9518-4d35-8a7f-394c07fbe5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730542685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1730542685
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.2345337816
Short name T719
Test name
Test status
Simulation time 27774782 ps
CPU time 1.3 seconds
Started Aug 13 06:46:55 PM PDT 24
Finished Aug 13 06:46:57 PM PDT 24
Peak memory 218836 kb
Host smart-9d353def-6f47-42a8-bdb3-81508c3d1b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345337816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2345337816
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/108.edn_alert.287608465
Short name T725
Test name
Test status
Simulation time 73710304 ps
CPU time 1.14 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:01 PM PDT 24
Peak memory 219876 kb
Host smart-05e90b90-6a06-4684-8d02-d5510ab03e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287608465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.287608465
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.581777922
Short name T968
Test name
Test status
Simulation time 50877552 ps
CPU time 1.49 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:08 PM PDT 24
Peak memory 217732 kb
Host smart-e544b434-3e8b-49fa-a878-b7836d9d2e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581777922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.581777922
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3066019341
Short name T634
Test name
Test status
Simulation time 27247538 ps
CPU time 1.22 seconds
Started Aug 13 06:46:43 PM PDT 24
Finished Aug 13 06:46:45 PM PDT 24
Peak memory 220056 kb
Host smart-24f41e1e-279b-485e-aa9a-705686ee3c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066019341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3066019341
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.144614365
Short name T390
Test name
Test status
Simulation time 222064408 ps
CPU time 3.04 seconds
Started Aug 13 06:46:52 PM PDT 24
Finished Aug 13 06:46:55 PM PDT 24
Peak memory 220364 kb
Host smart-9d335795-db64-4d81-bc9b-b7fe2e4ced57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144614365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.144614365
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1446863083
Short name T713
Test name
Test status
Simulation time 65766730 ps
CPU time 1.11 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 219448 kb
Host smart-893b2b81-5da8-41d0-afc9-77ad104e4915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446863083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1446863083
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1007732415
Short name T362
Test name
Test status
Simulation time 44637077 ps
CPU time 0.89 seconds
Started Aug 13 06:45:23 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 215540 kb
Host smart-f65bcfe7-e3cd-40ea-b16e-b269db546bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007732415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1007732415
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.1707658975
Short name T806
Test name
Test status
Simulation time 30000981 ps
CPU time 0.82 seconds
Started Aug 13 06:45:30 PM PDT 24
Finished Aug 13 06:45:31 PM PDT 24
Peak memory 216820 kb
Host smart-4913af5b-a860-4665-b6bd-305d8c35fab1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707658975 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1707658975
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.822171824
Short name T405
Test name
Test status
Simulation time 58287895 ps
CPU time 1.13 seconds
Started Aug 13 06:45:27 PM PDT 24
Finished Aug 13 06:45:29 PM PDT 24
Peak memory 218680 kb
Host smart-6a84f052-d9e9-44da-8e6d-c1872c3eb313
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822171824 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.822171824
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1708109502
Short name T785
Test name
Test status
Simulation time 19138699 ps
CPU time 1.23 seconds
Started Aug 13 06:45:25 PM PDT 24
Finished Aug 13 06:45:31 PM PDT 24
Peak memory 224160 kb
Host smart-c5c1dcf2-466e-452e-90ff-9665f00feac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708109502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1708109502
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1910465901
Short name T862
Test name
Test status
Simulation time 364419262 ps
CPU time 1.26 seconds
Started Aug 13 06:45:30 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 217640 kb
Host smart-8cb2625d-190e-4072-99ec-ffb58b041ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910465901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1910465901
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.648444662
Short name T667
Test name
Test status
Simulation time 36938053 ps
CPU time 0.96 seconds
Started Aug 13 06:45:20 PM PDT 24
Finished Aug 13 06:45:21 PM PDT 24
Peak memory 215884 kb
Host smart-2e4f4d57-083b-40ba-a7be-345bb0b59e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648444662 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.648444662
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2204377335
Short name T905
Test name
Test status
Simulation time 16111243 ps
CPU time 1.05 seconds
Started Aug 13 06:45:31 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 215580 kb
Host smart-3189cac2-f217-474a-bbd9-842ef6480052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204377335 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2204377335
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.338054932
Short name T602
Test name
Test status
Simulation time 363777264 ps
CPU time 4.07 seconds
Started Aug 13 06:45:34 PM PDT 24
Finished Aug 13 06:45:38 PM PDT 24
Peak memory 217640 kb
Host smart-b21704b1-8297-4e03-a6f2-868d1477df8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338054932 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.338054932
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3399987622
Short name T423
Test name
Test status
Simulation time 1458803008 ps
CPU time 41.88 seconds
Started Aug 13 06:45:40 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 217032 kb
Host smart-7c2e74a7-e137-41d1-9b28-d3ce551bae74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399987622 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3399987622
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1982809770
Short name T727
Test name
Test status
Simulation time 23114418 ps
CPU time 1.14 seconds
Started Aug 13 06:46:44 PM PDT 24
Finished Aug 13 06:46:45 PM PDT 24
Peak memory 218784 kb
Host smart-dd68ecde-2cfc-491d-8cbd-b1e05adc78ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982809770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1982809770
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2656850155
Short name T605
Test name
Test status
Simulation time 45772361 ps
CPU time 1.55 seconds
Started Aug 13 06:47:04 PM PDT 24
Finished Aug 13 06:47:05 PM PDT 24
Peak memory 218800 kb
Host smart-89a1a74e-151b-428c-8c1f-9e9a4403c0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656850155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2656850155
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.1178477359
Short name T801
Test name
Test status
Simulation time 76278012 ps
CPU time 1.16 seconds
Started Aug 13 06:46:51 PM PDT 24
Finished Aug 13 06:46:53 PM PDT 24
Peak memory 221028 kb
Host smart-0ae4c700-308c-4eb2-b2b7-f93b3971779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178477359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.1178477359
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.532636414
Short name T881
Test name
Test status
Simulation time 31788276 ps
CPU time 1.47 seconds
Started Aug 13 06:46:54 PM PDT 24
Finished Aug 13 06:46:56 PM PDT 24
Peak memory 218840 kb
Host smart-47f974f9-052a-415a-9478-c56dbf936499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532636414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.532636414
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3851494736
Short name T878
Test name
Test status
Simulation time 22070705 ps
CPU time 1.13 seconds
Started Aug 13 06:46:47 PM PDT 24
Finished Aug 13 06:46:48 PM PDT 24
Peak memory 221104 kb
Host smart-efe0f8d5-24b6-49b5-99fe-edba84031033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851494736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3851494736
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.1116039561
Short name T435
Test name
Test status
Simulation time 75758752 ps
CPU time 1.15 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:46 PM PDT 24
Peak memory 217716 kb
Host smart-48037868-609d-421f-817e-4ee7ba7f45c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116039561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1116039561
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.1362243857
Short name T792
Test name
Test status
Simulation time 81693167 ps
CPU time 1.19 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 218876 kb
Host smart-83a95301-e67a-4fbb-a3d6-ce01dc811719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362243857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1362243857
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.2757139978
Short name T336
Test name
Test status
Simulation time 204590056 ps
CPU time 2.92 seconds
Started Aug 13 06:46:59 PM PDT 24
Finished Aug 13 06:47:03 PM PDT 24
Peak memory 220496 kb
Host smart-2805f4e7-dcaf-4d2e-9e64-79c6380e84ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757139978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2757139978
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.2707464894
Short name T662
Test name
Test status
Simulation time 138223406 ps
CPU time 1.24 seconds
Started Aug 13 06:46:59 PM PDT 24
Finished Aug 13 06:47:01 PM PDT 24
Peak memory 215944 kb
Host smart-dd14a455-d070-4981-a0c8-51559051406b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707464894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.2707464894
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.2902741098
Short name T364
Test name
Test status
Simulation time 34267182 ps
CPU time 1.32 seconds
Started Aug 13 06:46:52 PM PDT 24
Finished Aug 13 06:46:53 PM PDT 24
Peak memory 218672 kb
Host smart-d9d889d5-db4e-4818-92d9-c9af79fb61c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902741098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2902741098
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.847515959
Short name T584
Test name
Test status
Simulation time 90518126 ps
CPU time 1.19 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 220656 kb
Host smart-0b7b4e56-ffb1-4cc2-af9c-5de83489fdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847515959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.847515959
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.138454567
Short name T510
Test name
Test status
Simulation time 101497408 ps
CPU time 1.12 seconds
Started Aug 13 06:46:59 PM PDT 24
Finished Aug 13 06:47:01 PM PDT 24
Peak memory 215564 kb
Host smart-b12ea9ea-7a5a-46c8-a2e0-e8ba77462da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138454567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.138454567
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.2563994606
Short name T575
Test name
Test status
Simulation time 43257079 ps
CPU time 1.16 seconds
Started Aug 13 06:46:59 PM PDT 24
Finished Aug 13 06:47:01 PM PDT 24
Peak memory 219460 kb
Host smart-a62c5e21-98b4-42b3-9a6c-03de9d908e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563994606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.2563994606
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.2012459917
Short name T363
Test name
Test status
Simulation time 24554331 ps
CPU time 1.2 seconds
Started Aug 13 06:46:51 PM PDT 24
Finished Aug 13 06:46:53 PM PDT 24
Peak memory 217952 kb
Host smart-4cfe53f7-60d4-43f9-84bd-568cf83d41fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012459917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2012459917
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1764334515
Short name T120
Test name
Test status
Simulation time 50685092 ps
CPU time 1.26 seconds
Started Aug 13 06:46:44 PM PDT 24
Finished Aug 13 06:46:45 PM PDT 24
Peak memory 216148 kb
Host smart-334cc5df-e1b3-4d31-a2b4-8f87b936be51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764334515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1764334515
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.2951055825
Short name T945
Test name
Test status
Simulation time 84963706 ps
CPU time 1.23 seconds
Started Aug 13 06:47:10 PM PDT 24
Finished Aug 13 06:47:11 PM PDT 24
Peak memory 219132 kb
Host smart-7d1b7a67-08b6-444a-8645-afea2b6de378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951055825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2951055825
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1729872373
Short name T889
Test name
Test status
Simulation time 35902145 ps
CPU time 1.14 seconds
Started Aug 13 06:46:52 PM PDT 24
Finished Aug 13 06:46:53 PM PDT 24
Peak memory 218900 kb
Host smart-3cd13280-4985-4167-8c62-600952894280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729872373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1729872373
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.4129344617
Short name T369
Test name
Test status
Simulation time 118354655 ps
CPU time 2.77 seconds
Started Aug 13 06:46:54 PM PDT 24
Finished Aug 13 06:46:57 PM PDT 24
Peak memory 219472 kb
Host smart-bd36e84f-99ab-44f1-b191-80bbf68bdb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129344617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4129344617
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2814266610
Short name T500
Test name
Test status
Simulation time 84429345 ps
CPU time 1.17 seconds
Started Aug 13 06:46:49 PM PDT 24
Finished Aug 13 06:46:50 PM PDT 24
Peak memory 217548 kb
Host smart-f805f1fe-2836-4eb2-bc96-d66bd3387643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814266610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2814266610
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1912654169
Short name T403
Test name
Test status
Simulation time 36200505 ps
CPU time 1.05 seconds
Started Aug 13 06:45:33 PM PDT 24
Finished Aug 13 06:45:34 PM PDT 24
Peak memory 218884 kb
Host smart-c1e141c2-a32e-4e51-bbb9-d6d72d14bd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912654169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1912654169
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.2435488579
Short name T543
Test name
Test status
Simulation time 16275996 ps
CPU time 0.83 seconds
Started Aug 13 06:45:54 PM PDT 24
Finished Aug 13 06:45:55 PM PDT 24
Peak memory 216588 kb
Host smart-8b6ecdc2-3a15-4291-96d9-f4e25e2b6547
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435488579 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2435488579
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3925224245
Short name T499
Test name
Test status
Simulation time 55463046 ps
CPU time 1.09 seconds
Started Aug 13 06:45:30 PM PDT 24
Finished Aug 13 06:45:31 PM PDT 24
Peak memory 217172 kb
Host smart-d2e0285f-5ae3-4077-acd6-e5741e8267f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925224245 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3925224245
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.4004890673
Short name T107
Test name
Test status
Simulation time 45831108 ps
CPU time 1.02 seconds
Started Aug 13 06:45:30 PM PDT 24
Finished Aug 13 06:45:31 PM PDT 24
Peak memory 218768 kb
Host smart-f8fa883d-013b-4650-b95d-695b78ab7f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004890673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.4004890673
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3691726330
Short name T74
Test name
Test status
Simulation time 62959723 ps
CPU time 1.25 seconds
Started Aug 13 06:45:30 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 218728 kb
Host smart-74f4c3e8-5844-46d0-a170-dd1dbdc53233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691726330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3691726330
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1804775744
Short name T693
Test name
Test status
Simulation time 35283411 ps
CPU time 0.9 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 215496 kb
Host smart-bb684a06-dcc5-4466-9dfa-bc818cc5f5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804775744 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1804775744
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.24419459
Short name T547
Test name
Test status
Simulation time 37778017 ps
CPU time 0.86 seconds
Started Aug 13 06:45:27 PM PDT 24
Finished Aug 13 06:45:28 PM PDT 24
Peak memory 215560 kb
Host smart-c0272431-24d8-48d3-be73-aa1afb4f5701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24419459 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.24419459
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1111852334
Short name T955
Test name
Test status
Simulation time 3851020742 ps
CPU time 48.64 seconds
Started Aug 13 06:45:27 PM PDT 24
Finished Aug 13 06:46:16 PM PDT 24
Peak memory 221416 kb
Host smart-78b0b68d-e082-4ae7-9669-bde6bf26027c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111852334 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1111852334
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3633534269
Short name T746
Test name
Test status
Simulation time 144808829 ps
CPU time 1.08 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:01 PM PDT 24
Peak memory 217616 kb
Host smart-d48dd683-8267-4bcf-9127-4e9384100ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633534269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3633534269
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3526236914
Short name T153
Test name
Test status
Simulation time 90664979 ps
CPU time 1.21 seconds
Started Aug 13 06:46:57 PM PDT 24
Finished Aug 13 06:46:58 PM PDT 24
Peak memory 220032 kb
Host smart-c0e5914b-1976-4d81-84a6-72ceb683701c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526236914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3526236914
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.543116097
Short name T927
Test name
Test status
Simulation time 190837930 ps
CPU time 1.3 seconds
Started Aug 13 06:47:04 PM PDT 24
Finished Aug 13 06:47:05 PM PDT 24
Peak memory 218824 kb
Host smart-6d767c95-5b8b-4318-8a46-2b391ccd3e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543116097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.543116097
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3033074136
Short name T27
Test name
Test status
Simulation time 144229828 ps
CPU time 1.21 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 220584 kb
Host smart-7ba6b1f7-0500-4e61-b4b7-5b42e95f0ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033074136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3033074136
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3953535918
Short name T635
Test name
Test status
Simulation time 46907077 ps
CPU time 1.59 seconds
Started Aug 13 06:46:46 PM PDT 24
Finished Aug 13 06:46:48 PM PDT 24
Peak memory 219072 kb
Host smart-a7bc54b7-062f-4523-921b-862f4042bb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953535918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3953535918
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.1944533157
Short name T890
Test name
Test status
Simulation time 38322875 ps
CPU time 1.22 seconds
Started Aug 13 06:46:47 PM PDT 24
Finished Aug 13 06:46:48 PM PDT 24
Peak memory 218916 kb
Host smart-8952afd7-d1ee-43bb-9be8-2c8992b8f155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944533157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1944533157
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.1009534735
Short name T330
Test name
Test status
Simulation time 143085962 ps
CPU time 3.31 seconds
Started Aug 13 06:46:46 PM PDT 24
Finished Aug 13 06:46:49 PM PDT 24
Peak memory 219140 kb
Host smart-c5462395-7792-4d7d-8915-11eebfb85ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009534735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1009534735
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.3637933007
Short name T832
Test name
Test status
Simulation time 27748723 ps
CPU time 1.22 seconds
Started Aug 13 06:47:03 PM PDT 24
Finished Aug 13 06:47:05 PM PDT 24
Peak memory 216020 kb
Host smart-3a17859e-1901-4413-b25d-b75b2c9d6587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637933007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.3637933007
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.89588582
Short name T931
Test name
Test status
Simulation time 32413958 ps
CPU time 1.3 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 219668 kb
Host smart-e5e20d50-825d-414e-a3fb-ff74c4095c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89588582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.89588582
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.864174717
Short name T765
Test name
Test status
Simulation time 82379122 ps
CPU time 1.13 seconds
Started Aug 13 06:47:04 PM PDT 24
Finished Aug 13 06:47:06 PM PDT 24
Peak memory 218888 kb
Host smart-92459c2a-743e-4c2c-ad24-056593a877af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864174717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.864174717
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.4272926227
Short name T729
Test name
Test status
Simulation time 58388604 ps
CPU time 1.46 seconds
Started Aug 13 06:46:53 PM PDT 24
Finished Aug 13 06:46:55 PM PDT 24
Peak memory 218820 kb
Host smart-9b66b8ec-315f-4fd2-ba8c-54140a163599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272926227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.4272926227
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.814971175
Short name T598
Test name
Test status
Simulation time 29410415 ps
CPU time 1.23 seconds
Started Aug 13 06:46:52 PM PDT 24
Finished Aug 13 06:46:53 PM PDT 24
Peak memory 221052 kb
Host smart-ab009b15-c164-4f2a-bcbf-5f9a0267df52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814971175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.814971175
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.4239907964
Short name T409
Test name
Test status
Simulation time 54290127 ps
CPU time 1.98 seconds
Started Aug 13 06:46:51 PM PDT 24
Finished Aug 13 06:46:53 PM PDT 24
Peak memory 219816 kb
Host smart-3c5318db-1ad2-47ee-bdd7-db6944694b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239907964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.4239907964
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2097574349
Short name T661
Test name
Test status
Simulation time 51582856 ps
CPU time 1.18 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:46 PM PDT 24
Peak memory 217784 kb
Host smart-d121eac7-d073-4cdd-93e4-fc22c2272e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097574349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2097574349
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3699417479
Short name T89
Test name
Test status
Simulation time 47452136 ps
CPU time 1.07 seconds
Started Aug 13 06:46:46 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 217556 kb
Host smart-abe326ef-cc7e-4718-a7ac-fe7cf7e940fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699417479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3699417479
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.4267823284
Short name T214
Test name
Test status
Simulation time 63589588 ps
CPU time 1.1 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 220064 kb
Host smart-6dbac743-038b-4b5c-8869-70c957c1580f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267823284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.4267823284
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.789077285
Short name T358
Test name
Test status
Simulation time 10657368 ps
CPU time 0.82 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 207084 kb
Host smart-df1fa0c5-20aa-462e-98f4-d85961781cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789077285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.789077285
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.3629289461
Short name T902
Test name
Test status
Simulation time 19289085 ps
CPU time 1.09 seconds
Started Aug 13 06:45:27 PM PDT 24
Finished Aug 13 06:45:28 PM PDT 24
Peak memory 218668 kb
Host smart-54190ca9-c681-444a-aad1-d8989e55caf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629289461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3629289461
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1006826135
Short name T683
Test name
Test status
Simulation time 72175523 ps
CPU time 1.59 seconds
Started Aug 13 06:45:24 PM PDT 24
Finished Aug 13 06:45:25 PM PDT 24
Peak memory 218800 kb
Host smart-197b0315-d1f4-42a5-b6cd-d33ee6c09d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006826135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1006826135
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.935622415
Short name T110
Test name
Test status
Simulation time 23200965 ps
CPU time 1.08 seconds
Started Aug 13 06:45:34 PM PDT 24
Finished Aug 13 06:45:35 PM PDT 24
Peak memory 216056 kb
Host smart-590f6c10-693a-43ed-95b3-191daf28a1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935622415 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.935622415
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3650373566
Short name T675
Test name
Test status
Simulation time 14708521 ps
CPU time 0.95 seconds
Started Aug 13 06:45:23 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 215604 kb
Host smart-9e4dccf1-50f2-4245-8e45-0e0d3e47843e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650373566 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3650373566
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1189365040
Short name T929
Test name
Test status
Simulation time 680995936 ps
CPU time 4.15 seconds
Started Aug 13 06:45:32 PM PDT 24
Finished Aug 13 06:45:36 PM PDT 24
Peak memory 215460 kb
Host smart-3f928ebf-452c-4de8-8538-21fe6536fd95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189365040 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1189365040
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_alert.2575190985
Short name T157
Test name
Test status
Simulation time 29555363 ps
CPU time 1.34 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:46 PM PDT 24
Peak memory 220072 kb
Host smart-59e71da8-ab49-4865-8814-75ca46c3e44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575190985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2575190985
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1553545852
Short name T779
Test name
Test status
Simulation time 68581746 ps
CPU time 1.05 seconds
Started Aug 13 06:46:52 PM PDT 24
Finished Aug 13 06:46:53 PM PDT 24
Peak memory 217572 kb
Host smart-b17c493a-b3cc-4739-b1a9-23ec89bdbbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553545852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1553545852
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3414468705
Short name T735
Test name
Test status
Simulation time 36198790 ps
CPU time 1.11 seconds
Started Aug 13 06:47:13 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 219032 kb
Host smart-04a4f361-59b1-4fc3-af62-8e4581d1b320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414468705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3414468705
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.1953327351
Short name T287
Test name
Test status
Simulation time 29503711 ps
CPU time 1.27 seconds
Started Aug 13 06:46:42 PM PDT 24
Finished Aug 13 06:46:44 PM PDT 24
Peak memory 217760 kb
Host smart-1222aa13-7df3-4c91-83c0-d676d445f5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953327351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1953327351
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.595470830
Short name T879
Test name
Test status
Simulation time 78531004 ps
CPU time 1.23 seconds
Started Aug 13 06:46:50 PM PDT 24
Finished Aug 13 06:46:51 PM PDT 24
Peak memory 220252 kb
Host smart-a8c5952e-5a0f-43f1-87d3-1ad31cd788a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595470830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.595470830
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/133.edn_alert.2924317971
Short name T160
Test name
Test status
Simulation time 77866215 ps
CPU time 1.15 seconds
Started Aug 13 06:46:52 PM PDT 24
Finished Aug 13 06:46:54 PM PDT 24
Peak memory 220280 kb
Host smart-d614c340-b02b-4afb-a318-4023ab6a6cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924317971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2924317971
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1059163372
Short name T72
Test name
Test status
Simulation time 30548559 ps
CPU time 1.26 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:03 PM PDT 24
Peak memory 217856 kb
Host smart-87840e8e-8336-4cde-82b0-78fb27ac2134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059163372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1059163372
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.532513022
Short name T546
Test name
Test status
Simulation time 28039992 ps
CPU time 1.26 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 220132 kb
Host smart-96bbc6e1-666b-4a22-a338-4b8fb704e37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532513022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.532513022
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.2919422364
Short name T572
Test name
Test status
Simulation time 29122739 ps
CPU time 1.36 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 220348 kb
Host smart-62199d82-8daf-4aa1-922a-f5fe6c92e141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919422364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2919422364
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.1778865228
Short name T17
Test name
Test status
Simulation time 49218854 ps
CPU time 1.12 seconds
Started Aug 13 06:46:53 PM PDT 24
Finished Aug 13 06:46:54 PM PDT 24
Peak memory 221084 kb
Host smart-6e2eedb7-e668-4669-bd97-f76a69ee1802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778865228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1778865228
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.804114489
Short name T642
Test name
Test status
Simulation time 101138117 ps
CPU time 1.44 seconds
Started Aug 13 06:47:07 PM PDT 24
Finished Aug 13 06:47:08 PM PDT 24
Peak memory 217720 kb
Host smart-99474c81-2444-4eae-a068-ab59f5935675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804114489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.804114489
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3797839133
Short name T568
Test name
Test status
Simulation time 27797339 ps
CPU time 1.15 seconds
Started Aug 13 06:47:11 PM PDT 24
Finished Aug 13 06:47:12 PM PDT 24
Peak memory 218936 kb
Host smart-d1d9eb94-a33b-4b53-b28a-8eb4e012eeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797839133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3797839133
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.415549665
Short name T545
Test name
Test status
Simulation time 43506947 ps
CPU time 1.48 seconds
Started Aug 13 06:47:07 PM PDT 24
Finished Aug 13 06:47:08 PM PDT 24
Peak memory 217576 kb
Host smart-3f971221-1a70-4c3a-9e03-bdbde6afe657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415549665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.415549665
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.200169366
Short name T897
Test name
Test status
Simulation time 48323854 ps
CPU time 1.87 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 218772 kb
Host smart-853e76a3-2e99-4f21-be60-da94b94ce756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200169366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.200169366
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.2369124097
Short name T967
Test name
Test status
Simulation time 29075674 ps
CPU time 1.32 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:03 PM PDT 24
Peak memory 220084 kb
Host smart-57e0818e-7f4f-4262-9d14-a35aae7a02a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369124097 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2369124097
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.503482077
Short name T756
Test name
Test status
Simulation time 64235887 ps
CPU time 1.07 seconds
Started Aug 13 06:46:52 PM PDT 24
Finished Aug 13 06:46:54 PM PDT 24
Peak memory 217644 kb
Host smart-bcf589f9-e6bd-4c65-b42c-62eb59013e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503482077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.503482077
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.4116214734
Short name T173
Test name
Test status
Simulation time 33273911 ps
CPU time 1.3 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:03 PM PDT 24
Peak memory 215992 kb
Host smart-1083680c-4272-43bd-be18-3c72eafaf242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116214734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.4116214734
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2232809867
Short name T434
Test name
Test status
Simulation time 125699423 ps
CPU time 1.2 seconds
Started Aug 13 06:47:05 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 217496 kb
Host smart-3daf7714-be04-488f-920b-09d95b94ea7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232809867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2232809867
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1396422404
Short name T366
Test name
Test status
Simulation time 167402579 ps
CPU time 1.28 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:38 PM PDT 24
Peak memory 219820 kb
Host smart-0856ca5e-af62-4bd9-812a-cd783bbd79e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396422404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1396422404
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2209038172
Short name T749
Test name
Test status
Simulation time 15938252 ps
CPU time 0.94 seconds
Started Aug 13 06:45:34 PM PDT 24
Finished Aug 13 06:45:35 PM PDT 24
Peak memory 207072 kb
Host smart-ec154825-34dd-4a9a-ae01-1f6bab91c9e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209038172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2209038172
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2740664800
Short name T570
Test name
Test status
Simulation time 33352845 ps
CPU time 0.84 seconds
Started Aug 13 06:45:44 PM PDT 24
Finished Aug 13 06:45:45 PM PDT 24
Peak memory 216544 kb
Host smart-52471339-26a6-41c3-834c-6e68e5aa2645
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740664800 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2740664800
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1852492000
Short name T963
Test name
Test status
Simulation time 95897508 ps
CPU time 1.11 seconds
Started Aug 13 06:45:42 PM PDT 24
Finished Aug 13 06:45:43 PM PDT 24
Peak memory 217180 kb
Host smart-298d81e0-fb93-42bf-a4e1-9a50056d4886
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852492000 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1852492000
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3974913138
Short name T827
Test name
Test status
Simulation time 17874485 ps
CPU time 1.03 seconds
Started Aug 13 06:45:32 PM PDT 24
Finished Aug 13 06:45:33 PM PDT 24
Peak memory 218728 kb
Host smart-579cd335-1013-42ec-bf9a-a0e8654298c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974913138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3974913138
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.885276692
Short name T467
Test name
Test status
Simulation time 135165413 ps
CPU time 2.99 seconds
Started Aug 13 06:45:40 PM PDT 24
Finished Aug 13 06:45:43 PM PDT 24
Peak memory 217824 kb
Host smart-72a7a424-864d-4d43-8d80-63f06006a658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885276692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.885276692
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2981193877
Short name T636
Test name
Test status
Simulation time 27493139 ps
CPU time 0.95 seconds
Started Aug 13 06:45:37 PM PDT 24
Finished Aug 13 06:45:38 PM PDT 24
Peak memory 215672 kb
Host smart-ff73e094-ab60-4a7e-b3fb-b610c8ba23f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981193877 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2981193877
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.812210805
Short name T651
Test name
Test status
Simulation time 107374434 ps
CPU time 0.86 seconds
Started Aug 13 06:45:38 PM PDT 24
Finished Aug 13 06:45:39 PM PDT 24
Peak memory 215608 kb
Host smart-5127d603-e310-4a12-891b-fded8ca7329c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812210805 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.812210805
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3397011366
Short name T978
Test name
Test status
Simulation time 98644059 ps
CPU time 1.14 seconds
Started Aug 13 06:45:48 PM PDT 24
Finished Aug 13 06:45:50 PM PDT 24
Peak memory 215628 kb
Host smart-5165b81c-1a10-4f7f-9202-3cdef813d73d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397011366 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3397011366
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_alert.338200106
Short name T279
Test name
Test status
Simulation time 382237708 ps
CPU time 1.34 seconds
Started Aug 13 06:47:13 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 215960 kb
Host smart-13911a05-e4b2-4cd5-b0f3-5bd18f3b4123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338200106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.338200106
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2857698410
Short name T939
Test name
Test status
Simulation time 53994959 ps
CPU time 1.41 seconds
Started Aug 13 06:46:58 PM PDT 24
Finished Aug 13 06:47:00 PM PDT 24
Peak memory 217728 kb
Host smart-b60e3d5a-44b2-4624-8714-4649651692e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857698410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2857698410
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.4185202385
Short name T569
Test name
Test status
Simulation time 85323992 ps
CPU time 1.21 seconds
Started Aug 13 06:47:10 PM PDT 24
Finished Aug 13 06:47:11 PM PDT 24
Peak memory 218932 kb
Host smart-069359f3-5835-4d1f-8bf7-d216dfd43a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185202385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.4185202385
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.545540850
Short name T772
Test name
Test status
Simulation time 58437238 ps
CPU time 1.5 seconds
Started Aug 13 06:46:56 PM PDT 24
Finished Aug 13 06:47:03 PM PDT 24
Peak memory 219016 kb
Host smart-7beefd05-82f0-4688-92f6-30d894dd875f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545540850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.545540850
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.311896560
Short name T712
Test name
Test status
Simulation time 88413599 ps
CPU time 1.22 seconds
Started Aug 13 06:47:08 PM PDT 24
Finished Aug 13 06:47:09 PM PDT 24
Peak memory 220084 kb
Host smart-fbc355a8-7773-43a7-9477-0080537eaccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311896560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.311896560
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3419967579
Short name T808
Test name
Test status
Simulation time 33391948 ps
CPU time 1.26 seconds
Started Aug 13 06:47:05 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 217560 kb
Host smart-50a223d8-da0d-49b9-9579-5c8c220e81b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419967579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3419967579
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.2984564939
Short name T948
Test name
Test status
Simulation time 348615814 ps
CPU time 1.42 seconds
Started Aug 13 06:47:03 PM PDT 24
Finished Aug 13 06:47:04 PM PDT 24
Peak memory 220156 kb
Host smart-1ea33dfb-1599-42f5-a8f2-121a198d5074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984564939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2984564939
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.2399702219
Short name T974
Test name
Test status
Simulation time 134653533 ps
CPU time 2.95 seconds
Started Aug 13 06:47:08 PM PDT 24
Finished Aug 13 06:47:11 PM PDT 24
Peak memory 220612 kb
Host smart-238e813b-d3ab-4e65-8456-1c675765edac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399702219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2399702219
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.502198107
Short name T664
Test name
Test status
Simulation time 74906964 ps
CPU time 1.09 seconds
Started Aug 13 06:47:12 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 220676 kb
Host smart-31ca11e1-bd77-4558-8214-634a7bb1ada3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502198107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.502198107
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.259481898
Short name T950
Test name
Test status
Simulation time 92367269 ps
CPU time 1.14 seconds
Started Aug 13 06:47:21 PM PDT 24
Finished Aug 13 06:47:23 PM PDT 24
Peak memory 218844 kb
Host smart-b82fad6c-ee14-437a-b95b-5cde7d059d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259481898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.259481898
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3399042851
Short name T699
Test name
Test status
Simulation time 77014776 ps
CPU time 1.18 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 221908 kb
Host smart-d1114689-c399-4d7e-bf64-a558361fa3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399042851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3399042851
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.3985534320
Short name T459
Test name
Test status
Simulation time 57173073 ps
CPU time 1.19 seconds
Started Aug 13 06:46:58 PM PDT 24
Finished Aug 13 06:47:00 PM PDT 24
Peak memory 219304 kb
Host smart-071b79ab-9610-434f-a05f-b4832f472578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985534320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3985534320
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1139766493
Short name T942
Test name
Test status
Simulation time 71866470 ps
CPU time 1.11 seconds
Started Aug 13 06:47:02 PM PDT 24
Finished Aug 13 06:47:03 PM PDT 24
Peak memory 218984 kb
Host smart-f71de077-87f4-471f-97b5-bc1b383d9241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139766493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1139766493
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2886673991
Short name T349
Test name
Test status
Simulation time 80986794 ps
CPU time 1.51 seconds
Started Aug 13 06:46:58 PM PDT 24
Finished Aug 13 06:47:00 PM PDT 24
Peak memory 217572 kb
Host smart-c84275be-93bd-4e53-8e22-f977800a3ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886673991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2886673991
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.3293615683
Short name T579
Test name
Test status
Simulation time 121368341 ps
CPU time 1.22 seconds
Started Aug 13 06:47:07 PM PDT 24
Finished Aug 13 06:47:08 PM PDT 24
Peak memory 219172 kb
Host smart-1fda84bd-2e73-4eb9-bc2f-b8a68556b742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293615683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3293615683
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1279607163
Short name T670
Test name
Test status
Simulation time 40174455 ps
CPU time 1.11 seconds
Started Aug 13 06:47:02 PM PDT 24
Finished Aug 13 06:47:03 PM PDT 24
Peak memory 217596 kb
Host smart-92372458-f25d-4911-ab2d-801270899e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279607163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1279607163
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.3810415016
Short name T302
Test name
Test status
Simulation time 307591779 ps
CPU time 1.06 seconds
Started Aug 13 06:46:52 PM PDT 24
Finished Aug 13 06:46:53 PM PDT 24
Peak memory 219928 kb
Host smart-a046bb09-3cfb-48b8-9a0d-65069537379f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810415016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3810415016
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.1104531798
Short name T650
Test name
Test status
Simulation time 307397484 ps
CPU time 1.29 seconds
Started Aug 13 06:47:03 PM PDT 24
Finished Aug 13 06:47:04 PM PDT 24
Peak memory 217720 kb
Host smart-7267b25c-ddb1-4d70-8f51-888af5747af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104531798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1104531798
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.374299513
Short name T917
Test name
Test status
Simulation time 78419153 ps
CPU time 1.13 seconds
Started Aug 13 06:46:59 PM PDT 24
Finished Aug 13 06:47:01 PM PDT 24
Peak memory 220132 kb
Host smart-d50dd1b4-bf51-43f3-a527-d1e83805830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374299513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.374299513
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2648040657
Short name T312
Test name
Test status
Simulation time 213066205 ps
CPU time 2.64 seconds
Started Aug 13 06:47:08 PM PDT 24
Finished Aug 13 06:47:11 PM PDT 24
Peak memory 220412 kb
Host smart-0c325b47-d485-468f-a41e-dc69d47ccd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648040657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2648040657
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3321518475
Short name T351
Test name
Test status
Simulation time 50725255 ps
CPU time 1.39 seconds
Started Aug 13 06:45:31 PM PDT 24
Finished Aug 13 06:45:33 PM PDT 24
Peak memory 221820 kb
Host smart-ed523953-04eb-4efd-85d0-92ad8fa84969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321518475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3321518475
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3864076852
Short name T413
Test name
Test status
Simulation time 13984315 ps
CPU time 0.86 seconds
Started Aug 13 06:45:28 PM PDT 24
Finished Aug 13 06:45:29 PM PDT 24
Peak memory 207308 kb
Host smart-805ca91a-56ac-434b-8e5c-afab538b07b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864076852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3864076852
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3509336937
Short name T386
Test name
Test status
Simulation time 15823578 ps
CPU time 0.94 seconds
Started Aug 13 06:45:42 PM PDT 24
Finished Aug 13 06:45:43 PM PDT 24
Peak memory 216712 kb
Host smart-7bf8081d-ad53-45bb-9c6d-bdecb7bae5f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509336937 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3509336937
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1323691002
Short name T980
Test name
Test status
Simulation time 48092659 ps
CPU time 1.16 seconds
Started Aug 13 06:45:40 PM PDT 24
Finished Aug 13 06:45:42 PM PDT 24
Peak memory 217280 kb
Host smart-97d6358d-e388-4101-bfe4-9d6c14daefab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323691002 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1323691002
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_genbits.2452967985
Short name T523
Test name
Test status
Simulation time 66852563 ps
CPU time 1.14 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:38 PM PDT 24
Peak memory 217660 kb
Host smart-9c608a7b-d86d-4fda-9453-5f2ef9fe4877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452967985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2452967985
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2170095604
Short name T885
Test name
Test status
Simulation time 21420894 ps
CPU time 1.08 seconds
Started Aug 13 06:45:41 PM PDT 24
Finished Aug 13 06:45:42 PM PDT 24
Peak memory 215972 kb
Host smart-b46f6101-dc19-4ecb-a8cf-95d52c9385c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170095604 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2170095604
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.764403451
Short name T796
Test name
Test status
Simulation time 25123880 ps
CPU time 1 seconds
Started Aug 13 06:45:35 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 215608 kb
Host smart-aa374f25-9af4-4a85-8629-6c0ae4a5de84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764403451 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.764403451
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3983926112
Short name T892
Test name
Test status
Simulation time 332040755 ps
CPU time 6.58 seconds
Started Aug 13 06:45:40 PM PDT 24
Finished Aug 13 06:45:47 PM PDT 24
Peak memory 220040 kb
Host smart-e0bf6044-58ab-49a1-a52e-902da81b6da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983926112 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3983926112
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3244931700
Short name T938
Test name
Test status
Simulation time 12555117381 ps
CPU time 88.59 seconds
Started Aug 13 06:45:28 PM PDT 24
Finished Aug 13 06:46:56 PM PDT 24
Peak memory 220512 kb
Host smart-3ba53e41-12ce-4ed7-8fc4-aae3dfe926f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244931700 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3244931700
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2998990071
Short name T798
Test name
Test status
Simulation time 23050349 ps
CPU time 1.21 seconds
Started Aug 13 06:47:08 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 219776 kb
Host smart-ac2c2426-1ede-4ac2-a6ce-42d2f9438808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998990071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2998990071
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2827229716
Short name T961
Test name
Test status
Simulation time 40077928 ps
CPU time 1.26 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:01 PM PDT 24
Peak memory 219056 kb
Host smart-d05a8f36-2116-4cb6-9967-316ae6264747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827229716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2827229716
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.418027639
Short name T25
Test name
Test status
Simulation time 69694634 ps
CPU time 1.02 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 218848 kb
Host smart-17a2cde4-78c2-4590-aa09-65ddf283162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418027639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.418027639
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.922814977
Short name T639
Test name
Test status
Simulation time 378587825 ps
CPU time 4.27 seconds
Started Aug 13 06:47:19 PM PDT 24
Finished Aug 13 06:47:23 PM PDT 24
Peak memory 217980 kb
Host smart-6734107c-e723-43bf-9a08-82113c0f82a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922814977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.922814977
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.2912608672
Short name T715
Test name
Test status
Simulation time 33234612 ps
CPU time 1.4 seconds
Started Aug 13 06:46:57 PM PDT 24
Finished Aug 13 06:46:59 PM PDT 24
Peak memory 220436 kb
Host smart-7b4869e8-a6ec-4ae4-859e-e0b1a08ac5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912608672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.2912608672
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3665466307
Short name T641
Test name
Test status
Simulation time 79675080 ps
CPU time 1.36 seconds
Started Aug 13 06:47:07 PM PDT 24
Finished Aug 13 06:47:08 PM PDT 24
Peak memory 220472 kb
Host smart-96f2b439-615f-45d8-b929-792a787be526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665466307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3665466307
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2537368588
Short name T215
Test name
Test status
Simulation time 68540164 ps
CPU time 1.26 seconds
Started Aug 13 06:47:03 PM PDT 24
Finished Aug 13 06:47:05 PM PDT 24
Peak memory 220008 kb
Host smart-e771b019-87c9-4df3-8938-e6399ce6dfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537368588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2537368588
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.4198433569
Short name T698
Test name
Test status
Simulation time 58602880 ps
CPU time 1.43 seconds
Started Aug 13 06:46:58 PM PDT 24
Finished Aug 13 06:47:00 PM PDT 24
Peak memory 220372 kb
Host smart-674137b0-290e-491d-b540-f171b08d9329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198433569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.4198433569
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.154478893
Short name T633
Test name
Test status
Simulation time 73448723 ps
CPU time 1.19 seconds
Started Aug 13 06:47:04 PM PDT 24
Finished Aug 13 06:47:05 PM PDT 24
Peak memory 218868 kb
Host smart-533fe1a9-8c94-438a-beff-6f10c4826f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154478893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.154478893
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.2764302301
Short name T325
Test name
Test status
Simulation time 150769909 ps
CPU time 1.32 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 220364 kb
Host smart-02ed87f2-a2b0-4d8d-a673-fe59e3983114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764302301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2764302301
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2100659350
Short name T296
Test name
Test status
Simulation time 29538735 ps
CPU time 1.24 seconds
Started Aug 13 06:46:59 PM PDT 24
Finished Aug 13 06:47:01 PM PDT 24
Peak memory 219988 kb
Host smart-10e135d0-ace8-46ac-af1c-135f95bb93cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100659350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2100659350
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2723964198
Short name T935
Test name
Test status
Simulation time 42166000 ps
CPU time 1.48 seconds
Started Aug 13 06:47:05 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 220316 kb
Host smart-8d7afd3e-6fc9-44ec-9241-f783e68de60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723964198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2723964198
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2735287954
Short name T300
Test name
Test status
Simulation time 37785952 ps
CPU time 1.19 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 220964 kb
Host smart-177e2e72-2ce0-4ebe-b138-a72b8a28ad08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735287954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2735287954
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.780689674
Short name T903
Test name
Test status
Simulation time 76963340 ps
CPU time 1.62 seconds
Started Aug 13 06:47:16 PM PDT 24
Finished Aug 13 06:47:18 PM PDT 24
Peak memory 218828 kb
Host smart-b3dfd588-bab9-4ab0-a4db-e753c71be1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780689674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.780689674
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.2571977851
Short name T148
Test name
Test status
Simulation time 24744557 ps
CPU time 1.15 seconds
Started Aug 13 06:47:05 PM PDT 24
Finished Aug 13 06:47:06 PM PDT 24
Peak memory 221076 kb
Host smart-b18a4db3-e404-4b7b-9f5f-2831c2703a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571977851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2571977851
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.4234518177
Short name T46
Test name
Test status
Simulation time 69610445 ps
CPU time 1.36 seconds
Started Aug 13 06:47:10 PM PDT 24
Finished Aug 13 06:47:11 PM PDT 24
Peak memory 218980 kb
Host smart-5c58f57c-c3fb-426a-ad35-b8a4d2610448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234518177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.4234518177
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1083100439
Short name T695
Test name
Test status
Simulation time 92341221 ps
CPU time 1.17 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 219020 kb
Host smart-66737e81-a63f-4f1c-8f3a-62d690e8508f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083100439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1083100439
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.860077371
Short name T863
Test name
Test status
Simulation time 135499189 ps
CPU time 1.01 seconds
Started Aug 13 06:47:09 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 217648 kb
Host smart-1f5ee461-dd9f-4042-983c-b7faf0d731eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860077371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.860077371
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.8923091
Short name T117
Test name
Test status
Simulation time 47072133 ps
CPU time 1.23 seconds
Started Aug 13 06:46:59 PM PDT 24
Finished Aug 13 06:47:01 PM PDT 24
Peak memory 220228 kb
Host smart-9142db23-0001-4ebc-b63d-c4690a4a3c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8923091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.8923091
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.3393496021
Short name T410
Test name
Test status
Simulation time 47811203 ps
CPU time 1.38 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:03 PM PDT 24
Peak memory 218808 kb
Host smart-330667fe-35b6-4b29-a8d4-aecea623b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393496021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3393496021
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.938135628
Short name T285
Test name
Test status
Simulation time 37453391 ps
CPU time 1.31 seconds
Started Aug 13 06:45:44 PM PDT 24
Finished Aug 13 06:45:46 PM PDT 24
Peak memory 220036 kb
Host smart-7c268e4f-804e-4566-93d2-235941d1cd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938135628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.938135628
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.826561977
Short name T697
Test name
Test status
Simulation time 41015193 ps
CPU time 0.84 seconds
Started Aug 13 06:45:35 PM PDT 24
Finished Aug 13 06:45:36 PM PDT 24
Peak memory 215264 kb
Host smart-a51b606e-0eff-4955-ab87-ec984f546ee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826561977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.826561977
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.259762096
Short name T934
Test name
Test status
Simulation time 104927978 ps
CPU time 0.82 seconds
Started Aug 13 06:45:30 PM PDT 24
Finished Aug 13 06:45:31 PM PDT 24
Peak memory 216924 kb
Host smart-0754f165-a9e6-4dd4-8206-a6f7822c49b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259762096 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.259762096
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3008583421
Short name T687
Test name
Test status
Simulation time 96367682 ps
CPU time 1.14 seconds
Started Aug 13 06:45:32 PM PDT 24
Finished Aug 13 06:45:34 PM PDT 24
Peak memory 217356 kb
Host smart-71299521-aef6-402a-bd9f-922a97f4bc20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008583421 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3008583421
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.326349615
Short name T959
Test name
Test status
Simulation time 46544620 ps
CPU time 0.97 seconds
Started Aug 13 06:45:31 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 220708 kb
Host smart-3285cca2-cce4-46ad-94ff-6ccde4f8950d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326349615 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.326349615
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3044884546
Short name T308
Test name
Test status
Simulation time 41231701 ps
CPU time 1.46 seconds
Started Aug 13 06:45:30 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 218968 kb
Host smart-d6d04689-20ff-4aa0-a4c3-411488946b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044884546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3044884546
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3478485270
Short name T537
Test name
Test status
Simulation time 34326718 ps
CPU time 0.89 seconds
Started Aug 13 06:45:52 PM PDT 24
Finished Aug 13 06:45:53 PM PDT 24
Peak memory 215616 kb
Host smart-f8f277c8-3f42-4488-b9ae-d888188975b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478485270 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3478485270
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.900576063
Short name T603
Test name
Test status
Simulation time 38446598 ps
CPU time 0.85 seconds
Started Aug 13 06:45:40 PM PDT 24
Finished Aug 13 06:45:41 PM PDT 24
Peak memory 215624 kb
Host smart-39e3e82b-5797-4e2c-a972-8412fb26766b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900576063 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.900576063
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2404217479
Short name T350
Test name
Test status
Simulation time 112207409 ps
CPU time 2.59 seconds
Started Aug 13 06:45:34 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 217652 kb
Host smart-0113e973-017b-419d-9263-41082eed8081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404217479 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2404217479
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3848876180
Short name T223
Test name
Test status
Simulation time 14959523599 ps
CPU time 79.58 seconds
Started Aug 13 06:45:38 PM PDT 24
Finished Aug 13 06:46:58 PM PDT 24
Peak memory 218500 kb
Host smart-526cfa1e-38dd-4329-a9c2-98b0589c6f8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848876180 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3848876180
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.632742379
Short name T852
Test name
Test status
Simulation time 93759643 ps
CPU time 1.22 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 215996 kb
Host smart-0f645535-36fa-4303-9236-e7afbda02736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632742379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.632742379
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.699326446
Short name T888
Test name
Test status
Simulation time 67851008 ps
CPU time 1.09 seconds
Started Aug 13 06:47:07 PM PDT 24
Finished Aug 13 06:47:08 PM PDT 24
Peak memory 217492 kb
Host smart-50c866d7-5f9b-4662-86a7-730694f555cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699326446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.699326446
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1498290861
Short name T521
Test name
Test status
Simulation time 46668759 ps
CPU time 1.21 seconds
Started Aug 13 06:46:57 PM PDT 24
Finished Aug 13 06:46:58 PM PDT 24
Peak memory 220032 kb
Host smart-c1326378-7642-4acc-a064-2d02b84a1849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498290861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1498290861
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1104928614
Short name T337
Test name
Test status
Simulation time 59242862 ps
CPU time 1.12 seconds
Started Aug 13 06:47:07 PM PDT 24
Finished Aug 13 06:47:09 PM PDT 24
Peak memory 220192 kb
Host smart-439b0e33-0be6-4126-8557-7981b84f3e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104928614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1104928614
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.3137735671
Short name T592
Test name
Test status
Simulation time 45897037 ps
CPU time 1.19 seconds
Started Aug 13 06:47:10 PM PDT 24
Finished Aug 13 06:47:12 PM PDT 24
Peak memory 219260 kb
Host smart-cc4b65a4-7fc8-4f0b-a10d-c5ce2a2929bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137735671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.3137735671
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.460478173
Short name T334
Test name
Test status
Simulation time 38445875 ps
CPU time 1.87 seconds
Started Aug 13 06:47:15 PM PDT 24
Finished Aug 13 06:47:17 PM PDT 24
Peak memory 220356 kb
Host smart-7f4e6faa-7377-4774-ac97-3028deb4d577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460478173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.460478173
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.436198718
Short name T813
Test name
Test status
Simulation time 83343017 ps
CPU time 1.1 seconds
Started Aug 13 06:46:54 PM PDT 24
Finished Aug 13 06:46:55 PM PDT 24
Peak memory 220052 kb
Host smart-cff4eb4b-6b73-4a25-8a86-04e8cc520d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436198718 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.436198718
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1037357163
Short name T718
Test name
Test status
Simulation time 110271293 ps
CPU time 1 seconds
Started Aug 13 06:47:11 PM PDT 24
Finished Aug 13 06:47:12 PM PDT 24
Peak memory 217592 kb
Host smart-536aaaa6-a68b-4d55-8a0a-198d1d31328b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037357163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1037357163
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.843581753
Short name T676
Test name
Test status
Simulation time 29462846 ps
CPU time 1.31 seconds
Started Aug 13 06:47:02 PM PDT 24
Finished Aug 13 06:47:04 PM PDT 24
Peak memory 220068 kb
Host smart-80c44d5e-815e-44d2-b37c-8930f0422e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843581753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.843581753
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.71911803
Short name T673
Test name
Test status
Simulation time 76408018 ps
CPU time 1.17 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:01 PM PDT 24
Peak memory 217680 kb
Host smart-30b0d632-ef66-4ce1-9bce-c4948b16e97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71911803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.71911803
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.184876846
Short name T11
Test name
Test status
Simulation time 30865929 ps
CPU time 1.22 seconds
Started Aug 13 06:47:09 PM PDT 24
Finished Aug 13 06:47:10 PM PDT 24
Peak memory 219816 kb
Host smart-e277b286-24b8-41f5-8daf-5383d956c2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184876846 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.184876846
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/166.edn_alert.2857657003
Short name T299
Test name
Test status
Simulation time 109857302 ps
CPU time 1.22 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 221096 kb
Host smart-4de62506-718b-4392-b662-7c79e88ddf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857657003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2857657003
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.1870489247
Short name T452
Test name
Test status
Simulation time 100153968 ps
CPU time 1.16 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:03 PM PDT 24
Peak memory 219036 kb
Host smart-6a0fc1b5-935a-4b6c-9e6f-1813c55f6b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870489247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1870489247
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.3732791593
Short name T630
Test name
Test status
Simulation time 73696017 ps
CPU time 1.12 seconds
Started Aug 13 06:47:03 PM PDT 24
Finished Aug 13 06:47:04 PM PDT 24
Peak memory 219008 kb
Host smart-c2699aa1-efeb-488a-a49e-e2cc787362c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732791593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.3732791593
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.921846333
Short name T448
Test name
Test status
Simulation time 64795436 ps
CPU time 1.14 seconds
Started Aug 13 06:47:04 PM PDT 24
Finished Aug 13 06:47:05 PM PDT 24
Peak memory 219936 kb
Host smart-73dec9e9-5ee6-4709-8861-ed96d5ea7ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921846333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.921846333
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.2764034002
Short name T972
Test name
Test status
Simulation time 24581071 ps
CPU time 1.22 seconds
Started Aug 13 06:46:56 PM PDT 24
Finished Aug 13 06:46:58 PM PDT 24
Peak memory 220072 kb
Host smart-0dd4b758-0b79-44c2-8e80-782ef3e4ec3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764034002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2764034002
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1365663202
Short name T247
Test name
Test status
Simulation time 75865414 ps
CPU time 1.32 seconds
Started Aug 13 06:47:04 PM PDT 24
Finished Aug 13 06:47:05 PM PDT 24
Peak memory 218912 kb
Host smart-92c400ce-94dc-45a4-8529-b810d8e85ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365663202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1365663202
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.877101938
Short name T440
Test name
Test status
Simulation time 90045990 ps
CPU time 1.14 seconds
Started Aug 13 06:47:09 PM PDT 24
Finished Aug 13 06:47:10 PM PDT 24
Peak memory 215708 kb
Host smart-dff260c7-8bcc-45de-adab-b440069d31af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877101938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.877101938
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3069409160
Short name T732
Test name
Test status
Simulation time 76022703 ps
CPU time 1.07 seconds
Started Aug 13 06:45:32 PM PDT 24
Finished Aug 13 06:45:33 PM PDT 24
Peak memory 218728 kb
Host smart-7b2646c6-a923-407f-9078-9288444c9b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069409160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3069409160
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2320506723
Short name T345
Test name
Test status
Simulation time 22100327 ps
CPU time 0.85 seconds
Started Aug 13 06:45:29 PM PDT 24
Finished Aug 13 06:45:30 PM PDT 24
Peak memory 215264 kb
Host smart-914f515b-36ce-44f2-be90-6d4a995e1261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320506723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2320506723
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.268601246
Short name T94
Test name
Test status
Simulation time 98156739 ps
CPU time 1.22 seconds
Started Aug 13 06:45:51 PM PDT 24
Finished Aug 13 06:45:52 PM PDT 24
Peak memory 217104 kb
Host smart-51ab874a-5e96-492c-8272-231af69a8612
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268601246 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.268601246
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3137323291
Short name T161
Test name
Test status
Simulation time 18956294 ps
CPU time 1.03 seconds
Started Aug 13 06:45:50 PM PDT 24
Finished Aug 13 06:45:52 PM PDT 24
Peak memory 218596 kb
Host smart-72da502c-fbe1-4384-9901-5dd7470537fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137323291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3137323291
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2141597080
Short name T851
Test name
Test status
Simulation time 161329060 ps
CPU time 1.58 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 219092 kb
Host smart-e62aa5ea-5aa2-4638-bde2-67d1c0b8d29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141597080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2141597080
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3581020498
Short name T39
Test name
Test status
Simulation time 32902727 ps
CPU time 0.94 seconds
Started Aug 13 06:45:55 PM PDT 24
Finished Aug 13 06:45:56 PM PDT 24
Peak memory 215856 kb
Host smart-482478c2-ce21-435b-8ef5-0e9c1b93d190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581020498 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3581020498
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1489183834
Short name T372
Test name
Test status
Simulation time 18453415 ps
CPU time 1.02 seconds
Started Aug 13 06:45:59 PM PDT 24
Finished Aug 13 06:46:01 PM PDT 24
Peak memory 215540 kb
Host smart-4bf1bbea-ba09-4214-8e26-ae599e9d0c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489183834 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1489183834
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/170.edn_alert.193937714
Short name T601
Test name
Test status
Simulation time 68114790 ps
CPU time 1.13 seconds
Started Aug 13 06:47:04 PM PDT 24
Finished Aug 13 06:47:06 PM PDT 24
Peak memory 219036 kb
Host smart-6f5f34ba-bef7-41cf-99ef-64b2f31379f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193937714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.193937714
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1434471051
Short name T97
Test name
Test status
Simulation time 95261618 ps
CPU time 1.16 seconds
Started Aug 13 06:47:12 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 217472 kb
Host smart-97827f4e-60e0-467a-80d7-869c0d1eb0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434471051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1434471051
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1748721637
Short name T561
Test name
Test status
Simulation time 74417198 ps
CPU time 1.14 seconds
Started Aug 13 06:47:05 PM PDT 24
Finished Aug 13 06:47:06 PM PDT 24
Peak memory 220224 kb
Host smart-7aeb862b-7622-4706-a681-428fdc69a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748721637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1748721637
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.2685784245
Short name T814
Test name
Test status
Simulation time 95422727 ps
CPU time 1.05 seconds
Started Aug 13 06:46:55 PM PDT 24
Finished Aug 13 06:46:57 PM PDT 24
Peak memory 217820 kb
Host smart-ed16d3b4-06fd-40d1-a74a-f61af3cec280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685784245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2685784245
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1408716633
Short name T216
Test name
Test status
Simulation time 69505288 ps
CPU time 1.1 seconds
Started Aug 13 06:47:12 PM PDT 24
Finished Aug 13 06:47:13 PM PDT 24
Peak memory 220580 kb
Host smart-623baebf-0209-4946-9eb3-3700839927b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408716633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1408716633
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3292607674
Short name T710
Test name
Test status
Simulation time 143309337 ps
CPU time 2.22 seconds
Started Aug 13 06:47:02 PM PDT 24
Finished Aug 13 06:47:05 PM PDT 24
Peak memory 220544 kb
Host smart-fddc86c6-a7fb-4efe-8912-82617d7fd0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292607674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3292607674
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.883435574
Short name T474
Test name
Test status
Simulation time 26216149 ps
CPU time 1.24 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 220920 kb
Host smart-bd3d898a-50df-4b08-80b2-90b59fba36bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883435574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.883435574
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/174.edn_alert.2614315841
Short name T864
Test name
Test status
Simulation time 26360315 ps
CPU time 1.2 seconds
Started Aug 13 06:46:58 PM PDT 24
Finished Aug 13 06:46:59 PM PDT 24
Peak memory 219072 kb
Host smart-acb44652-0ef5-4ec4-8f9d-c4ccd7f9feb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614315841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.2614315841
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3056324882
Short name T338
Test name
Test status
Simulation time 58728685 ps
CPU time 1.52 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 220344 kb
Host smart-982c810b-de34-4eee-9871-780117b80484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056324882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3056324882
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.2433609772
Short name T810
Test name
Test status
Simulation time 28444791 ps
CPU time 1.28 seconds
Started Aug 13 06:46:54 PM PDT 24
Finished Aug 13 06:46:55 PM PDT 24
Peak memory 216012 kb
Host smart-cc048a16-ff34-4909-ae24-1e44de806354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433609772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2433609772
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.875730054
Short name T444
Test name
Test status
Simulation time 53711928 ps
CPU time 1.06 seconds
Started Aug 13 06:47:15 PM PDT 24
Finished Aug 13 06:47:21 PM PDT 24
Peak memory 217568 kb
Host smart-84984cb9-f42f-4e36-87dc-e7049d34a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875730054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.875730054
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.4104649530
Short name T524
Test name
Test status
Simulation time 168531720 ps
CPU time 1.15 seconds
Started Aug 13 06:47:21 PM PDT 24
Finished Aug 13 06:47:22 PM PDT 24
Peak memory 219516 kb
Host smart-03ca8eac-8f69-49cf-920a-55a852791822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104649530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.4104649530
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.1800584680
Short name T421
Test name
Test status
Simulation time 50004670 ps
CPU time 1.49 seconds
Started Aug 13 06:47:04 PM PDT 24
Finished Aug 13 06:47:06 PM PDT 24
Peak memory 217616 kb
Host smart-a8f45817-d879-4cde-aab7-b38706811588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800584680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1800584680
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.3408086354
Short name T294
Test name
Test status
Simulation time 66292852 ps
CPU time 1.21 seconds
Started Aug 13 06:46:58 PM PDT 24
Finished Aug 13 06:46:59 PM PDT 24
Peak memory 218792 kb
Host smart-6be59898-2e09-489b-b03d-31c468563113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408086354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3408086354
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.1255689372
Short name T590
Test name
Test status
Simulation time 37266338 ps
CPU time 1.37 seconds
Started Aug 13 06:47:12 PM PDT 24
Finished Aug 13 06:47:13 PM PDT 24
Peak memory 218780 kb
Host smart-c9b30c24-b537-41bd-a82e-426861a76f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255689372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1255689372
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.4152478008
Short name T937
Test name
Test status
Simulation time 199139943 ps
CPU time 1.32 seconds
Started Aug 13 06:47:07 PM PDT 24
Finished Aug 13 06:47:09 PM PDT 24
Peak memory 219932 kb
Host smart-285284c5-3274-46d7-84fa-b904a36c40e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152478008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.4152478008
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.1722212633
Short name T531
Test name
Test status
Simulation time 177631073 ps
CPU time 0.97 seconds
Started Aug 13 06:47:17 PM PDT 24
Finished Aug 13 06:47:19 PM PDT 24
Peak memory 217588 kb
Host smart-df87b53b-28da-43e9-a1cd-a352b666f784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722212633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1722212633
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3153561520
Short name T757
Test name
Test status
Simulation time 26403163 ps
CPU time 1.17 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 220132 kb
Host smart-d2e8889e-9297-41e0-9f01-3f2d6e019dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153561520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3153561520
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.3345589910
Short name T487
Test name
Test status
Simulation time 170689452 ps
CPU time 1.23 seconds
Started Aug 13 06:47:07 PM PDT 24
Finished Aug 13 06:47:09 PM PDT 24
Peak memory 220104 kb
Host smart-c15fd6a6-2be0-4a94-9075-2068282808a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345589910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3345589910
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.3502683127
Short name T923
Test name
Test status
Simulation time 18818992 ps
CPU time 0.96 seconds
Started Aug 13 06:45:52 PM PDT 24
Finished Aug 13 06:45:53 PM PDT 24
Peak memory 207088 kb
Host smart-4a8228c7-e3d7-4dcb-9db9-4bc5d9c98d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502683127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3502683127
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3904548129
Short name T607
Test name
Test status
Simulation time 35192040 ps
CPU time 0.9 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 215740 kb
Host smart-b3764b44-62e6-47a3-b631-2cbc2d52ac16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904548129 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3904548129
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.906427819
Short name T278
Test name
Test status
Simulation time 31355073 ps
CPU time 1.12 seconds
Started Aug 13 06:45:32 PM PDT 24
Finished Aug 13 06:45:33 PM PDT 24
Peak memory 218984 kb
Host smart-4168c5ac-4da9-4005-9517-123714441b83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906427819 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.906427819
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3401712095
Short name T776
Test name
Test status
Simulation time 30110791 ps
CPU time 1.33 seconds
Started Aug 13 06:45:32 PM PDT 24
Finished Aug 13 06:45:34 PM PDT 24
Peak memory 225956 kb
Host smart-b16ec294-40d1-4d41-83b3-8c88f31bba0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401712095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3401712095
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.1466987589
Short name T396
Test name
Test status
Simulation time 21209846 ps
CPU time 1.14 seconds
Started Aug 13 06:45:32 PM PDT 24
Finished Aug 13 06:45:34 PM PDT 24
Peak memory 224420 kb
Host smart-546a0fa0-fabc-47fc-afd4-93184f573bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466987589 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1466987589
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2675617593
Short name T380
Test name
Test status
Simulation time 66034965 ps
CPU time 0.88 seconds
Started Aug 13 06:45:39 PM PDT 24
Finished Aug 13 06:45:40 PM PDT 24
Peak memory 215544 kb
Host smart-17da6473-c185-49aa-abb5-c2f937b31122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675617593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2675617593
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3390759697
Short name T318
Test name
Test status
Simulation time 1465808926 ps
CPU time 2.76 seconds
Started Aug 13 06:45:47 PM PDT 24
Finished Aug 13 06:45:50 PM PDT 24
Peak memory 215644 kb
Host smart-e05fa03b-9569-4c05-a551-aef7f7b37ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390759697 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3390759697
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/180.edn_alert.669844708
Short name T619
Test name
Test status
Simulation time 55737186 ps
CPU time 1.23 seconds
Started Aug 13 06:47:01 PM PDT 24
Finished Aug 13 06:47:02 PM PDT 24
Peak memory 219432 kb
Host smart-cb1f1434-df9f-4d2a-9a1b-08fe85fd72bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669844708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.669844708
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.4285872330
Short name T483
Test name
Test status
Simulation time 73370358 ps
CPU time 1.28 seconds
Started Aug 13 06:47:14 PM PDT 24
Finished Aug 13 06:47:15 PM PDT 24
Peak memory 220480 kb
Host smart-59b823af-0c8f-4ebc-95bf-6e7a6c5720d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285872330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4285872330
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.3255911403
Short name T147
Test name
Test status
Simulation time 29399601 ps
CPU time 1.16 seconds
Started Aug 13 06:47:07 PM PDT 24
Finished Aug 13 06:47:08 PM PDT 24
Peak memory 218724 kb
Host smart-adc08064-13bd-4df2-b8d2-4b94ca8c207d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255911403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3255911403
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.210914649
Short name T795
Test name
Test status
Simulation time 119133139 ps
CPU time 1.15 seconds
Started Aug 13 06:47:05 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 219264 kb
Host smart-e131b761-3dc2-436f-a6e4-f370b6906445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210914649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.210914649
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.398957699
Short name T468
Test name
Test status
Simulation time 86877891 ps
CPU time 1.18 seconds
Started Aug 13 06:47:19 PM PDT 24
Finished Aug 13 06:47:21 PM PDT 24
Peak memory 220944 kb
Host smart-67dc5650-f43d-4649-9c92-f1d2fc7c9880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398957699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.398957699
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.1971307131
Short name T846
Test name
Test status
Simulation time 111081883 ps
CPU time 2.41 seconds
Started Aug 13 06:47:12 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 219912 kb
Host smart-3c1d8462-b567-45a0-9559-604616124c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971307131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1971307131
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3543771384
Short name T143
Test name
Test status
Simulation time 138960404 ps
CPU time 1.3 seconds
Started Aug 13 06:46:59 PM PDT 24
Finished Aug 13 06:47:00 PM PDT 24
Peak memory 215912 kb
Host smart-51eaf4e0-eb85-48b7-b59d-e9643006fe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543771384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3543771384
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.1459947110
Short name T859
Test name
Test status
Simulation time 68748058 ps
CPU time 1.09 seconds
Started Aug 13 06:47:14 PM PDT 24
Finished Aug 13 06:47:15 PM PDT 24
Peak memory 217956 kb
Host smart-112f0643-1f30-4f3c-a405-09cf2ce788bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459947110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1459947110
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.3368624273
Short name T56
Test name
Test status
Simulation time 101212000 ps
CPU time 1.18 seconds
Started Aug 13 06:47:00 PM PDT 24
Finished Aug 13 06:47:01 PM PDT 24
Peak memory 219496 kb
Host smart-7a52ee49-b46e-4cc9-be35-b8277abd4954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368624273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.3368624273
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1445800497
Short name T559
Test name
Test status
Simulation time 49317103 ps
CPU time 1.16 seconds
Started Aug 13 06:47:20 PM PDT 24
Finished Aug 13 06:47:21 PM PDT 24
Peak memory 217452 kb
Host smart-e97821bd-292d-4a6b-8dd4-5be20f4897cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445800497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1445800497
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.1323290088
Short name T182
Test name
Test status
Simulation time 129599000 ps
CPU time 1.16 seconds
Started Aug 13 06:47:14 PM PDT 24
Finished Aug 13 06:47:15 PM PDT 24
Peak memory 219020 kb
Host smart-ddb71cf0-5fec-4b94-9421-7191833685f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323290088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.1323290088
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.2213454123
Short name T49
Test name
Test status
Simulation time 37815597 ps
CPU time 1.42 seconds
Started Aug 13 06:47:08 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 218912 kb
Host smart-51f86094-1c17-44ff-aed4-dc966906002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213454123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2213454123
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.3638214611
Short name T276
Test name
Test status
Simulation time 257956557 ps
CPU time 1.08 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 218748 kb
Host smart-aebb801f-04c9-41e2-aec7-1564c73615a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638214611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3638214611
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.1664585507
Short name T102
Test name
Test status
Simulation time 61615764 ps
CPU time 1.4 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 218960 kb
Host smart-88ae08c3-7e1d-4f17-8c9d-ef01aa361cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664585507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1664585507
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.4003204763
Short name T165
Test name
Test status
Simulation time 300821473 ps
CPU time 1.2 seconds
Started Aug 13 06:47:10 PM PDT 24
Finished Aug 13 06:47:11 PM PDT 24
Peak memory 219560 kb
Host smart-826217c7-7e48-4ead-ade1-df20ffb345df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003204763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.4003204763
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.2080319424
Short name T340
Test name
Test status
Simulation time 131251545 ps
CPU time 1.04 seconds
Started Aug 13 06:47:16 PM PDT 24
Finished Aug 13 06:47:17 PM PDT 24
Peak memory 217796 kb
Host smart-69d67b14-3a85-4964-9a84-692fcc2243c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080319424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2080319424
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.1997381857
Short name T809
Test name
Test status
Simulation time 28987719 ps
CPU time 1.15 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:08 PM PDT 24
Peak memory 220132 kb
Host smart-b966b922-2882-49f9-8ef3-387d4f1c85e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997381857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1997381857
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.751336346
Short name T356
Test name
Test status
Simulation time 259018976 ps
CPU time 1.19 seconds
Started Aug 13 06:47:14 PM PDT 24
Finished Aug 13 06:47:20 PM PDT 24
Peak memory 217656 kb
Host smart-a6e9c1db-8505-4e10-b540-534e9a428940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751336346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.751336346
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2003680100
Short name T804
Test name
Test status
Simulation time 304536128 ps
CPU time 1.39 seconds
Started Aug 13 06:45:35 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 220048 kb
Host smart-27c63507-a8cd-4684-b01a-682eecba9e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003680100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2003680100
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3621761710
Short name T837
Test name
Test status
Simulation time 39275608 ps
CPU time 0.9 seconds
Started Aug 13 06:45:26 PM PDT 24
Finished Aug 13 06:45:27 PM PDT 24
Peak memory 207088 kb
Host smart-5cd88b4c-11e9-48cb-9b0a-a3187c24e792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621761710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3621761710
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3913086630
Short name T158
Test name
Test status
Simulation time 26935453 ps
CPU time 0.87 seconds
Started Aug 13 06:45:47 PM PDT 24
Finished Aug 13 06:45:48 PM PDT 24
Peak memory 215712 kb
Host smart-b4b94711-97cf-430d-87b7-f9dfba05cb9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913086630 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3913086630
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2700808305
Short name T154
Test name
Test status
Simulation time 50781895 ps
CPU time 1.15 seconds
Started Aug 13 06:45:50 PM PDT 24
Finished Aug 13 06:45:51 PM PDT 24
Peak memory 217208 kb
Host smart-e5d805ff-2c94-4ced-8d6e-ecb78459955e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700808305 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2700808305
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3916843531
Short name T414
Test name
Test status
Simulation time 230972338 ps
CPU time 1.02 seconds
Started Aug 13 06:45:38 PM PDT 24
Finished Aug 13 06:45:39 PM PDT 24
Peak memory 220032 kb
Host smart-3c18551e-76b0-4dac-804a-17036df8a38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916843531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3916843531
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1954109097
Short name T656
Test name
Test status
Simulation time 756275891 ps
CPU time 4.93 seconds
Started Aug 13 06:45:33 PM PDT 24
Finished Aug 13 06:45:38 PM PDT 24
Peak memory 218972 kb
Host smart-f0b8f8af-5a7f-4acd-9d0e-9bbebc329ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954109097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1954109097
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1556002484
Short name T36
Test name
Test status
Simulation time 32714636 ps
CPU time 0.82 seconds
Started Aug 13 06:45:31 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 215924 kb
Host smart-6e76f0d2-4d22-4bac-ba68-a4c7e5b0025e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556002484 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1556002484
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2900074424
Short name T874
Test name
Test status
Simulation time 37286288 ps
CPU time 0.91 seconds
Started Aug 13 06:45:52 PM PDT 24
Finished Aug 13 06:45:53 PM PDT 24
Peak memory 215576 kb
Host smart-84f53da3-b68a-43e3-ad28-6972ab8a9f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900074424 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2900074424
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3070359385
Short name T823
Test name
Test status
Simulation time 185745279 ps
CPU time 3.91 seconds
Started Aug 13 06:45:51 PM PDT 24
Finished Aug 13 06:45:55 PM PDT 24
Peak memory 217500 kb
Host smart-d2e60154-cc35-4bf2-9796-1c1d1680bbf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070359385 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3070359385
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_alert.771059987
Short name T58
Test name
Test status
Simulation time 73566161 ps
CPU time 1.12 seconds
Started Aug 13 06:47:19 PM PDT 24
Finished Aug 13 06:47:21 PM PDT 24
Peak memory 219028 kb
Host smart-4967bb70-e7c2-4ab7-a7d8-3f742c9b84b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771059987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.771059987
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.404214410
Short name T331
Test name
Test status
Simulation time 183459464 ps
CPU time 1.15 seconds
Started Aug 13 06:47:14 PM PDT 24
Finished Aug 13 06:47:15 PM PDT 24
Peak memory 215624 kb
Host smart-ee2de476-f4c0-4aaa-b2d8-88186634c8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404214410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.404214410
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.1468831675
Short name T973
Test name
Test status
Simulation time 28805988 ps
CPU time 1.26 seconds
Started Aug 13 06:47:09 PM PDT 24
Finished Aug 13 06:47:10 PM PDT 24
Peak memory 220052 kb
Host smart-01f51d53-1c8e-47c3-943f-34ea7fc966c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468831675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.1468831675
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2131952974
Short name T90
Test name
Test status
Simulation time 51605357 ps
CPU time 1.25 seconds
Started Aug 13 06:47:17 PM PDT 24
Finished Aug 13 06:47:18 PM PDT 24
Peak memory 219004 kb
Host smart-7d043582-f345-49ef-8ef5-1dc4bb327f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131952974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2131952974
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.4175962210
Short name T301
Test name
Test status
Simulation time 29117640 ps
CPU time 1.13 seconds
Started Aug 13 06:47:10 PM PDT 24
Finished Aug 13 06:47:11 PM PDT 24
Peak memory 218936 kb
Host smart-6c2844ab-8690-4863-9402-c140b33daa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175962210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.4175962210
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.1774874108
Short name T341
Test name
Test status
Simulation time 72675800 ps
CPU time 1.03 seconds
Started Aug 13 06:47:26 PM PDT 24
Finished Aug 13 06:47:27 PM PDT 24
Peak memory 217424 kb
Host smart-c6e53280-7a74-4888-bf4d-689d0f722ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774874108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1774874108
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.520834977
Short name T701
Test name
Test status
Simulation time 23210152 ps
CPU time 1.19 seconds
Started Aug 13 06:47:08 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 220852 kb
Host smart-60bde1d9-2759-4ca9-9ff5-dad8e7ffa1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520834977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.520834977
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.1463488429
Short name T830
Test name
Test status
Simulation time 143147741 ps
CPU time 1.06 seconds
Started Aug 13 06:47:18 PM PDT 24
Finished Aug 13 06:47:20 PM PDT 24
Peak memory 217576 kb
Host smart-b29da14f-0251-424e-9517-3902a5159116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463488429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1463488429
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.293145683
Short name T105
Test name
Test status
Simulation time 193177984 ps
CPU time 1.22 seconds
Started Aug 13 06:47:07 PM PDT 24
Finished Aug 13 06:47:08 PM PDT 24
Peak memory 215996 kb
Host smart-5d70cdfc-183b-4070-8a9d-4d47431ae3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293145683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.293145683
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.2192559099
Short name T840
Test name
Test status
Simulation time 296838091 ps
CPU time 1.53 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 219472 kb
Host smart-9171578e-ad54-42ba-bd05-4e9cfbae7e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192559099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2192559099
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.557283017
Short name T904
Test name
Test status
Simulation time 46371478 ps
CPU time 1.14 seconds
Started Aug 13 06:47:13 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 218748 kb
Host smart-04823ffe-e95f-4b6d-89fd-c3913e98aac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557283017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.557283017
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2823080068
Short name T427
Test name
Test status
Simulation time 72942447 ps
CPU time 1.05 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 217564 kb
Host smart-ce72cfec-33fe-4dcd-8819-f231cf213030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823080068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2823080068
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3626685398
Short name T219
Test name
Test status
Simulation time 231861328 ps
CPU time 3.71 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:10 PM PDT 24
Peak memory 218920 kb
Host smart-70fe8db1-6204-46d8-afc3-af80e49047ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626685398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3626685398
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.871786983
Short name T755
Test name
Test status
Simulation time 41104598 ps
CPU time 1.16 seconds
Started Aug 13 06:47:18 PM PDT 24
Finished Aug 13 06:47:19 PM PDT 24
Peak memory 221152 kb
Host smart-778a0d0c-c7ef-4390-9ac4-597d2e26bf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871786983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.871786983
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3312549557
Short name T86
Test name
Test status
Simulation time 41728944 ps
CPU time 1.39 seconds
Started Aug 13 06:47:12 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 217792 kb
Host smart-7fca5a96-6b40-4f4e-9cfd-2c04dd7b3e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312549557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3312549557
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.849901601
Short name T505
Test name
Test status
Simulation time 86941925 ps
CPU time 1.18 seconds
Started Aug 13 06:47:12 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 219620 kb
Host smart-5b404ec7-7212-4b1a-87f0-d614a83e206f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849901601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.849901601
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2421613280
Short name T555
Test name
Test status
Simulation time 148989101 ps
CPU time 1.54 seconds
Started Aug 13 06:47:18 PM PDT 24
Finished Aug 13 06:47:19 PM PDT 24
Peak memory 218996 kb
Host smart-04a2d988-b8c5-48aa-b1a1-48f5f7672782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421613280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2421613280
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1573585922
Short name T246
Test name
Test status
Simulation time 25294782 ps
CPU time 1.19 seconds
Started Aug 13 06:45:27 PM PDT 24
Finished Aug 13 06:45:29 PM PDT 24
Peak memory 220072 kb
Host smart-858f46d3-b7c6-4770-9c0e-86ce24b9ee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573585922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1573585922
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.124749743
Short name T573
Test name
Test status
Simulation time 17795167 ps
CPU time 0.96 seconds
Started Aug 13 06:45:07 PM PDT 24
Finished Aug 13 06:45:08 PM PDT 24
Peak memory 207060 kb
Host smart-fff874ae-e4b2-4edf-836a-e2ea449a483b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124749743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.124749743
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1771999632
Short name T865
Test name
Test status
Simulation time 20825879 ps
CPU time 0.91 seconds
Started Aug 13 06:45:06 PM PDT 24
Finished Aug 13 06:45:07 PM PDT 24
Peak memory 216812 kb
Host smart-d2f4d617-dd6c-4407-9be3-f33d78d65023
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771999632 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1771999632
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3678088579
Short name T128
Test name
Test status
Simulation time 110931703 ps
CPU time 1.1 seconds
Started Aug 13 06:45:05 PM PDT 24
Finished Aug 13 06:45:06 PM PDT 24
Peak memory 217340 kb
Host smart-3a3ee55b-ec38-44d0-ba5c-6a392d502169
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678088579 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3678088579
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3261093856
Short name T69
Test name
Test status
Simulation time 47896474 ps
CPU time 1.07 seconds
Started Aug 13 06:45:15 PM PDT 24
Finished Aug 13 06:45:17 PM PDT 24
Peak memory 229796 kb
Host smart-34d399ac-738c-4a6d-b828-20c109507b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261093856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3261093856
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2932787664
Short name T383
Test name
Test status
Simulation time 31303765 ps
CPU time 1.3 seconds
Started Aug 13 06:45:05 PM PDT 24
Finished Aug 13 06:45:07 PM PDT 24
Peak memory 217636 kb
Host smart-2f9705f0-9ae0-42ca-b032-045b8f769171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932787664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2932787664
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3743115959
Short name T485
Test name
Test status
Simulation time 21874628 ps
CPU time 1.07 seconds
Started Aug 13 06:45:20 PM PDT 24
Finished Aug 13 06:45:21 PM PDT 24
Peak memory 215700 kb
Host smart-9f30d464-705f-48b1-8b2e-80405b93dc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743115959 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3743115959
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1201019547
Short name T19
Test name
Test status
Simulation time 462025876 ps
CPU time 4.1 seconds
Started Aug 13 06:45:30 PM PDT 24
Finished Aug 13 06:45:34 PM PDT 24
Peak memory 239380 kb
Host smart-a5eee25d-eed2-4f92-b1c6-fe50d8e06ae9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201019547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1201019547
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.4078657492
Short name T682
Test name
Test status
Simulation time 17780289 ps
CPU time 0.99 seconds
Started Aug 13 06:44:59 PM PDT 24
Finished Aug 13 06:45:00 PM PDT 24
Peak memory 215588 kb
Host smart-8278f5d7-8d40-4f15-90e0-dd97484d251c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078657492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.4078657492
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1604359619
Short name T775
Test name
Test status
Simulation time 150744082 ps
CPU time 1.43 seconds
Started Aug 13 06:45:19 PM PDT 24
Finished Aug 13 06:45:20 PM PDT 24
Peak memory 215552 kb
Host smart-a322d019-b4e3-4388-8394-f6cb33fc3fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604359619 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1604359619
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1640677074
Short name T199
Test name
Test status
Simulation time 1882057683 ps
CPU time 54.28 seconds
Started Aug 13 06:45:10 PM PDT 24
Finished Aug 13 06:46:04 PM PDT 24
Peak memory 220640 kb
Host smart-b5f95579-ae7d-4cad-a7c7-881570d2156d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640677074 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1640677074
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.330929118
Short name T10
Test name
Test status
Simulation time 133289204 ps
CPU time 1.09 seconds
Started Aug 13 06:45:33 PM PDT 24
Finished Aug 13 06:45:34 PM PDT 24
Peak memory 220652 kb
Host smart-2407fecc-caae-413a-879d-44ccc161e837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330929118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.330929118
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1577109111
Short name T28
Test name
Test status
Simulation time 82961139 ps
CPU time 0.8 seconds
Started Aug 13 06:45:46 PM PDT 24
Finished Aug 13 06:45:47 PM PDT 24
Peak memory 206728 kb
Host smart-283d2350-e7a5-4f6e-9028-0a90ed5ca4cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577109111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1577109111
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1807591190
Short name T849
Test name
Test status
Simulation time 27090205 ps
CPU time 0.81 seconds
Started Aug 13 06:45:49 PM PDT 24
Finished Aug 13 06:45:50 PM PDT 24
Peak memory 216552 kb
Host smart-83644def-5c94-48e3-9b3a-5efb1348be04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807591190 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1807591190
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.252474250
Short name T843
Test name
Test status
Simulation time 20166421 ps
CPU time 1.19 seconds
Started Aug 13 06:45:59 PM PDT 24
Finished Aug 13 06:46:00 PM PDT 24
Peak memory 224220 kb
Host smart-c95ec163-c422-404e-8624-4ccec3afcb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252474250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.252474250
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3116122620
Short name T767
Test name
Test status
Simulation time 37867477 ps
CPU time 1.55 seconds
Started Aug 13 06:45:53 PM PDT 24
Finished Aug 13 06:45:54 PM PDT 24
Peak memory 220168 kb
Host smart-fd8fb079-275b-41c3-b853-10208f3a978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116122620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3116122620
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1449094782
Short name T392
Test name
Test status
Simulation time 36561164 ps
CPU time 0.85 seconds
Started Aug 13 06:45:30 PM PDT 24
Finished Aug 13 06:45:31 PM PDT 24
Peak memory 215468 kb
Host smart-bebfbf37-6c23-486d-b0a6-f3004ea81fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449094782 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1449094782
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1100512859
Short name T478
Test name
Test status
Simulation time 61812326 ps
CPU time 0.95 seconds
Started Aug 13 06:45:35 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 215628 kb
Host smart-e94162ea-c7ce-43c5-912c-5946a9b24b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100512859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1100512859
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2313383921
Short name T79
Test name
Test status
Simulation time 177326660 ps
CPU time 3.83 seconds
Started Aug 13 06:45:50 PM PDT 24
Finished Aug 13 06:45:55 PM PDT 24
Peak memory 217336 kb
Host smart-0613c89d-679e-41d7-b323-7a85aae0bcda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313383921 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2313383921
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3145645834
Short name T416
Test name
Test status
Simulation time 4454902762 ps
CPU time 109.83 seconds
Started Aug 13 06:45:33 PM PDT 24
Finished Aug 13 06:47:23 PM PDT 24
Peak memory 221684 kb
Host smart-31d3712e-23ac-4dba-8050-59b30cfb25a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145645834 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3145645834
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1455841207
Short name T506
Test name
Test status
Simulation time 78045403 ps
CPU time 1.12 seconds
Started Aug 13 06:47:21 PM PDT 24
Finished Aug 13 06:47:22 PM PDT 24
Peak memory 217676 kb
Host smart-c99b0005-b24d-4dd8-be48-29f02a6f2361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455841207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1455841207
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1961508838
Short name T314
Test name
Test status
Simulation time 44881980 ps
CPU time 1.72 seconds
Started Aug 13 06:47:15 PM PDT 24
Finished Aug 13 06:47:17 PM PDT 24
Peak memory 219072 kb
Host smart-a3685447-09e7-4c3f-903c-704e9dcc9788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961508838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1961508838
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2433902168
Short name T782
Test name
Test status
Simulation time 89698911 ps
CPU time 1.54 seconds
Started Aug 13 06:47:32 PM PDT 24
Finished Aug 13 06:47:33 PM PDT 24
Peak memory 218884 kb
Host smart-1d1c8982-d20b-4056-a659-012e1b22c761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433902168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2433902168
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1034682124
Short name T774
Test name
Test status
Simulation time 104182977 ps
CPU time 1.1 seconds
Started Aug 13 06:47:19 PM PDT 24
Finished Aug 13 06:47:21 PM PDT 24
Peak memory 217684 kb
Host smart-118440c3-515f-4bd6-be15-002fa67ce32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034682124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1034682124
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2535149189
Short name T490
Test name
Test status
Simulation time 172586938 ps
CPU time 1.94 seconds
Started Aug 13 06:47:29 PM PDT 24
Finished Aug 13 06:47:31 PM PDT 24
Peak memory 219388 kb
Host smart-cd24abac-aaf2-4f36-aef0-1c9c2f694da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535149189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2535149189
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.883076012
Short name T320
Test name
Test status
Simulation time 24194198 ps
CPU time 1.24 seconds
Started Aug 13 06:47:22 PM PDT 24
Finished Aug 13 06:47:24 PM PDT 24
Peak memory 219052 kb
Host smart-9a1fb427-b732-4972-af9c-723f5408d9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883076012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.883076012
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3721102519
Short name T408
Test name
Test status
Simulation time 48828692 ps
CPU time 1.2 seconds
Started Aug 13 06:47:10 PM PDT 24
Finished Aug 13 06:47:12 PM PDT 24
Peak memory 220236 kb
Host smart-3398ef5c-e69b-4694-8790-d2f2a255bfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721102519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3721102519
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2673432556
Short name T458
Test name
Test status
Simulation time 36675131 ps
CPU time 1.56 seconds
Started Aug 13 06:47:08 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 217852 kb
Host smart-0b664ed2-12a4-42a2-a33a-69fa61580d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673432556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2673432556
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3692307965
Short name T856
Test name
Test status
Simulation time 8792653043 ps
CPU time 121.09 seconds
Started Aug 13 06:47:18 PM PDT 24
Finished Aug 13 06:49:19 PM PDT 24
Peak memory 220844 kb
Host smart-7579cb46-6c8c-4d5f-bc65-d1bb074661cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692307965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3692307965
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.411835144
Short name T738
Test name
Test status
Simulation time 91198731 ps
CPU time 1.44 seconds
Started Aug 13 06:47:13 PM PDT 24
Finished Aug 13 06:47:15 PM PDT 24
Peak memory 219096 kb
Host smart-b66a5c2f-66c2-4650-8af5-2b87d381c732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411835144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.411835144
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3837968686
Short name T304
Test name
Test status
Simulation time 91589805 ps
CPU time 1.16 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:38 PM PDT 24
Peak memory 221516 kb
Host smart-67312cef-abce-4b6d-80af-7161f6f22932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837968686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3837968686
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3296285255
Short name T454
Test name
Test status
Simulation time 47822821 ps
CPU time 0.89 seconds
Started Aug 13 06:45:56 PM PDT 24
Finished Aug 13 06:45:57 PM PDT 24
Peak memory 207340 kb
Host smart-5ccef0d7-467a-4049-a648-bc57c829b99a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296285255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3296285255
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3006734016
Short name T690
Test name
Test status
Simulation time 55346764 ps
CPU time 0.86 seconds
Started Aug 13 06:45:59 PM PDT 24
Finished Aug 13 06:46:00 PM PDT 24
Peak memory 215656 kb
Host smart-355d2b50-6392-4229-a482-7c77c485719f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006734016 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3006734016
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.165345425
Short name T925
Test name
Test status
Simulation time 23701975 ps
CPU time 1.08 seconds
Started Aug 13 06:45:44 PM PDT 24
Finished Aug 13 06:45:46 PM PDT 24
Peak memory 217196 kb
Host smart-aaa2c3db-1b40-451f-a218-832f2629f521
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165345425 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.165345425
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3801706963
Short name T177
Test name
Test status
Simulation time 18188099 ps
CPU time 1.13 seconds
Started Aug 13 06:45:50 PM PDT 24
Finished Aug 13 06:45:52 PM PDT 24
Peak memory 218732 kb
Host smart-0f09a787-d82f-46d6-bf15-8e787832f857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801706963 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3801706963
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.4286383464
Short name T513
Test name
Test status
Simulation time 84185220 ps
CPU time 2.04 seconds
Started Aug 13 06:45:30 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 219944 kb
Host smart-8d523255-247a-4abf-9b3c-40b7f65a876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286383464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.4286383464
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1526956792
Short name T37
Test name
Test status
Simulation time 23138396 ps
CPU time 0.92 seconds
Started Aug 13 06:45:43 PM PDT 24
Finished Aug 13 06:45:44 PM PDT 24
Peak memory 216028 kb
Host smart-22f2f3e1-09dd-488d-9f10-b41262427bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526956792 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1526956792
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1552498109
Short name T242
Test name
Test status
Simulation time 31188052 ps
CPU time 0.93 seconds
Started Aug 13 06:45:33 PM PDT 24
Finished Aug 13 06:45:35 PM PDT 24
Peak memory 215572 kb
Host smart-b056a3f1-1bd4-41b8-8f5d-425532728d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552498109 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1552498109
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.751227598
Short name T81
Test name
Test status
Simulation time 3555295494 ps
CPU time 96.83 seconds
Started Aug 13 06:45:50 PM PDT 24
Finished Aug 13 06:47:27 PM PDT 24
Peak memory 217392 kb
Host smart-0d420597-fa09-4682-908f-22a956057e8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751227598 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.751227598
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.4182841178
Short name T637
Test name
Test status
Simulation time 19728703 ps
CPU time 1.1 seconds
Started Aug 13 06:47:02 PM PDT 24
Finished Aug 13 06:47:04 PM PDT 24
Peak memory 220024 kb
Host smart-fb2696c3-0e3f-44ff-86ce-842bd0ee4df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182841178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.4182841178
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3002841363
Short name T489
Test name
Test status
Simulation time 47380677 ps
CPU time 1.5 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:08 PM PDT 24
Peak memory 215624 kb
Host smart-4b49398f-06b6-43da-a0f0-852f46a5e20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002841363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3002841363
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3758711485
Short name T232
Test name
Test status
Simulation time 42728330 ps
CPU time 1.16 seconds
Started Aug 13 06:47:04 PM PDT 24
Finished Aug 13 06:47:05 PM PDT 24
Peak memory 218812 kb
Host smart-f0d5d8a8-b691-419c-b9e1-5669e101a1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758711485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3758711485
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3088456462
Short name T315
Test name
Test status
Simulation time 35620926 ps
CPU time 1.37 seconds
Started Aug 13 06:47:20 PM PDT 24
Finished Aug 13 06:47:21 PM PDT 24
Peak memory 218840 kb
Host smart-c5bf7c8d-7106-46e4-8222-316b96362a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088456462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3088456462
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1921669543
Short name T298
Test name
Test status
Simulation time 59469053 ps
CPU time 1.37 seconds
Started Aug 13 06:47:20 PM PDT 24
Finished Aug 13 06:47:21 PM PDT 24
Peak memory 219216 kb
Host smart-7c3f0823-5dbf-4184-bc22-bff7c28697d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921669543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1921669543
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3251333970
Short name T370
Test name
Test status
Simulation time 38330331 ps
CPU time 1.31 seconds
Started Aug 13 06:47:17 PM PDT 24
Finished Aug 13 06:47:18 PM PDT 24
Peak memory 217556 kb
Host smart-6ad89d90-7f17-4638-b52c-5a134e48ddec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251333970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3251333970
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4145869838
Short name T326
Test name
Test status
Simulation time 48052822 ps
CPU time 1.54 seconds
Started Aug 13 06:47:10 PM PDT 24
Finished Aug 13 06:47:11 PM PDT 24
Peak memory 218972 kb
Host smart-90fe403b-98c9-4802-9fdd-78df5476d7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145869838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4145869838
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2632203393
Short name T48
Test name
Test status
Simulation time 242179574 ps
CPU time 1.9 seconds
Started Aug 13 06:47:17 PM PDT 24
Finished Aug 13 06:47:24 PM PDT 24
Peak memory 219468 kb
Host smart-0dd17a81-af76-490f-8519-f5c387a28680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632203393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2632203393
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2630588400
Short name T335
Test name
Test status
Simulation time 145990321 ps
CPU time 2.95 seconds
Started Aug 13 06:47:13 PM PDT 24
Finished Aug 13 06:47:16 PM PDT 24
Peak memory 219576 kb
Host smart-7d206d9c-01fa-4a0e-b5b9-34fffc89dc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630588400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2630588400
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3165109343
Short name T726
Test name
Test status
Simulation time 31630169 ps
CPU time 1.2 seconds
Started Aug 13 06:45:49 PM PDT 24
Finished Aug 13 06:45:50 PM PDT 24
Peak memory 218920 kb
Host smart-fa5a2242-1b43-4352-96f1-a842eecec569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165109343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3165109343
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1036424743
Short name T600
Test name
Test status
Simulation time 60066853 ps
CPU time 0.93 seconds
Started Aug 13 06:45:46 PM PDT 24
Finished Aug 13 06:45:47 PM PDT 24
Peak memory 207068 kb
Host smart-bfc0d50d-f2b6-423e-83f1-8ba5f860a125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036424743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1036424743
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1673136993
Short name T708
Test name
Test status
Simulation time 23746022 ps
CPU time 0.9 seconds
Started Aug 13 06:46:00 PM PDT 24
Finished Aug 13 06:46:01 PM PDT 24
Peak memory 207468 kb
Host smart-7745df6f-dfff-4daa-8355-8c85321dac97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673136993 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1673136993
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3160603567
Short name T486
Test name
Test status
Simulation time 62333986 ps
CPU time 1.15 seconds
Started Aug 13 06:45:58 PM PDT 24
Finished Aug 13 06:45:59 PM PDT 24
Peak memory 218980 kb
Host smart-4648ca43-8f8b-40aa-a2ea-5b7b3ac2587d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160603567 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3160603567
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2271431591
Short name T127
Test name
Test status
Simulation time 26889025 ps
CPU time 0.98 seconds
Started Aug 13 06:45:44 PM PDT 24
Finished Aug 13 06:45:45 PM PDT 24
Peak memory 219900 kb
Host smart-fbf34205-67f4-4f64-8326-c46bbf037ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271431591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2271431591
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.4035529222
Short name T684
Test name
Test status
Simulation time 129765906 ps
CPU time 1.55 seconds
Started Aug 13 06:45:59 PM PDT 24
Finished Aug 13 06:46:01 PM PDT 24
Peak memory 219168 kb
Host smart-16feda70-c128-450d-bfab-a88629ddd81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035529222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4035529222
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1041522481
Short name T112
Test name
Test status
Simulation time 33447887 ps
CPU time 0.9 seconds
Started Aug 13 06:45:44 PM PDT 24
Finished Aug 13 06:45:45 PM PDT 24
Peak memory 215928 kb
Host smart-47de4669-1386-43a4-a7e2-2dc395a74888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041522481 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1041522481
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2762758932
Short name T928
Test name
Test status
Simulation time 16372197 ps
CPU time 0.97 seconds
Started Aug 13 06:45:48 PM PDT 24
Finished Aug 13 06:45:50 PM PDT 24
Peak memory 215624 kb
Host smart-86a51b4c-5429-4e9a-b445-1ca8b8112c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762758932 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2762758932
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.872446763
Short name T976
Test name
Test status
Simulation time 900792686 ps
CPU time 4.87 seconds
Started Aug 13 06:45:48 PM PDT 24
Finished Aug 13 06:45:53 PM PDT 24
Peak memory 215592 kb
Host smart-671250b9-ba6d-4810-ba20-10fe474319c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872446763 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.872446763
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2979569172
Short name T41
Test name
Test status
Simulation time 10564720645 ps
CPU time 62.46 seconds
Started Aug 13 06:45:54 PM PDT 24
Finished Aug 13 06:46:56 PM PDT 24
Peak memory 219504 kb
Host smart-264d6827-c566-4247-a3f6-8fdea590f3d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979569172 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2979569172
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3116164906
Short name T384
Test name
Test status
Simulation time 42044007 ps
CPU time 1.41 seconds
Started Aug 13 06:47:12 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 218712 kb
Host smart-b5fb67af-a66b-4ad7-9469-b0ce12dc2519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116164906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3116164906
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1009214554
Short name T367
Test name
Test status
Simulation time 58131214 ps
CPU time 1.17 seconds
Started Aug 13 06:47:22 PM PDT 24
Finished Aug 13 06:47:24 PM PDT 24
Peak memory 217532 kb
Host smart-b9afda1a-8c47-45fe-a413-1419c5656a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009214554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1009214554
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.312124671
Short name T457
Test name
Test status
Simulation time 73974820 ps
CPU time 1.55 seconds
Started Aug 13 06:47:21 PM PDT 24
Finished Aug 13 06:47:23 PM PDT 24
Peak memory 219136 kb
Host smart-86594f9c-2e65-4d45-98fb-19cbb581525c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312124671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.312124671
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3247440035
Short name T503
Test name
Test status
Simulation time 55204933 ps
CPU time 1.13 seconds
Started Aug 13 06:47:25 PM PDT 24
Finished Aug 13 06:47:26 PM PDT 24
Peak memory 219336 kb
Host smart-a93a598b-63e4-44dc-81d6-15a97d87ef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247440035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3247440035
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2516820555
Short name T365
Test name
Test status
Simulation time 17106725 ps
CPU time 1.02 seconds
Started Aug 13 06:47:30 PM PDT 24
Finished Aug 13 06:47:31 PM PDT 24
Peak memory 217560 kb
Host smart-2ac2c8aa-d427-4b98-9dc8-93e732c2adf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516820555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2516820555
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.409822463
Short name T438
Test name
Test status
Simulation time 164932912 ps
CPU time 1.37 seconds
Started Aug 13 06:47:15 PM PDT 24
Finished Aug 13 06:47:22 PM PDT 24
Peak memory 219056 kb
Host smart-bc78f10c-8ed9-491f-811e-7e2d804e9a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409822463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.409822463
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1973531440
Short name T960
Test name
Test status
Simulation time 34464251 ps
CPU time 1.39 seconds
Started Aug 13 06:47:36 PM PDT 24
Finished Aug 13 06:47:38 PM PDT 24
Peak memory 217652 kb
Host smart-5b650853-5dc9-45cc-84e8-2623aa4d5cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973531440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1973531440
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.237582520
Short name T696
Test name
Test status
Simulation time 41631222 ps
CPU time 1.51 seconds
Started Aug 13 06:47:29 PM PDT 24
Finished Aug 13 06:47:31 PM PDT 24
Peak memory 218728 kb
Host smart-26ce505e-afd6-4b3f-ab89-4c34ce4efead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237582520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.237582520
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3140765034
Short name T516
Test name
Test status
Simulation time 73961308 ps
CPU time 1.09 seconds
Started Aug 13 06:47:19 PM PDT 24
Finished Aug 13 06:47:20 PM PDT 24
Peak memory 217752 kb
Host smart-144782e4-2127-473a-ae4c-bbd88feac468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140765034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3140765034
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1886148388
Short name T373
Test name
Test status
Simulation time 123303354 ps
CPU time 1.27 seconds
Started Aug 13 06:47:36 PM PDT 24
Finished Aug 13 06:47:38 PM PDT 24
Peak memory 217536 kb
Host smart-700f4917-5af6-4908-baf0-5735f40612a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886148388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1886148388
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1223553079
Short name T739
Test name
Test status
Simulation time 77514173 ps
CPU time 1.07 seconds
Started Aug 13 06:46:07 PM PDT 24
Finished Aug 13 06:46:08 PM PDT 24
Peak memory 220184 kb
Host smart-3431c381-d45f-4619-a8dc-b2dd4de5b056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223553079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1223553079
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3419338163
Short name T244
Test name
Test status
Simulation time 11781664 ps
CPU time 0.82 seconds
Started Aug 13 06:45:39 PM PDT 24
Finished Aug 13 06:45:40 PM PDT 24
Peak memory 206872 kb
Host smart-af4a38e0-ee4d-42ee-8afa-bdb73c14018f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419338163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3419338163
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1838396619
Short name T122
Test name
Test status
Simulation time 11983424 ps
CPU time 0.94 seconds
Started Aug 13 06:45:41 PM PDT 24
Finished Aug 13 06:45:42 PM PDT 24
Peak memory 217004 kb
Host smart-2eee5a8a-24f3-40f8-aa8b-74763744e95f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838396619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1838396619
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3342849256
Short name T156
Test name
Test status
Simulation time 44825382 ps
CPU time 1.11 seconds
Started Aug 13 06:45:35 PM PDT 24
Finished Aug 13 06:45:36 PM PDT 24
Peak memory 217168 kb
Host smart-a007de5f-e7f7-4815-8d22-09eb1ff21f7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342849256 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3342849256
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1471045080
Short name T164
Test name
Test status
Simulation time 19395097 ps
CPU time 1.01 seconds
Started Aug 13 06:45:49 PM PDT 24
Finished Aug 13 06:45:50 PM PDT 24
Peak memory 218732 kb
Host smart-e0170943-1f85-41de-93b2-68ea10e20dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471045080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1471045080
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.236508441
Short name T495
Test name
Test status
Simulation time 70170074 ps
CPU time 1.9 seconds
Started Aug 13 06:45:55 PM PDT 24
Finished Aug 13 06:45:57 PM PDT 24
Peak memory 219152 kb
Host smart-e5a0e780-66e1-438e-8683-03796a306dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236508441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.236508441
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.676121785
Short name T395
Test name
Test status
Simulation time 28472829 ps
CPU time 0.97 seconds
Started Aug 13 06:45:46 PM PDT 24
Finished Aug 13 06:45:47 PM PDT 24
Peak memory 215756 kb
Host smart-6db90eec-aa32-4f99-abad-84e82262326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676121785 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.676121785
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2863152953
Short name T898
Test name
Test status
Simulation time 14525581 ps
CPU time 1.01 seconds
Started Aug 13 06:45:49 PM PDT 24
Finished Aug 13 06:45:50 PM PDT 24
Peak memory 215584 kb
Host smart-9bb2dc28-5ac7-488e-9c54-752aa0e0862a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863152953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2863152953
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.467755876
Short name T936
Test name
Test status
Simulation time 133992919 ps
CPU time 1.91 seconds
Started Aug 13 06:45:51 PM PDT 24
Finished Aug 13 06:45:53 PM PDT 24
Peak memory 215552 kb
Host smart-4ae0e354-e984-4669-bbe0-da5687993a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467755876 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.467755876
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3259063582
Short name T577
Test name
Test status
Simulation time 58476520685 ps
CPU time 113.87 seconds
Started Aug 13 06:45:49 PM PDT 24
Finished Aug 13 06:47:43 PM PDT 24
Peak memory 216800 kb
Host smart-91477f91-508b-4d49-90ec-f2bd465c613a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259063582 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3259063582
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.4234971262
Short name T385
Test name
Test status
Simulation time 35836076 ps
CPU time 1.43 seconds
Started Aug 13 06:47:24 PM PDT 24
Finished Aug 13 06:47:26 PM PDT 24
Peak memory 220188 kb
Host smart-40d11ea9-892b-4ca2-b2ef-18602a17c19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234971262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.4234971262
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2453502527
Short name T309
Test name
Test status
Simulation time 65426842 ps
CPU time 1.16 seconds
Started Aug 13 06:47:18 PM PDT 24
Finished Aug 13 06:47:19 PM PDT 24
Peak memory 219136 kb
Host smart-cd8c8803-51e6-474e-9362-0c3d6afcc503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453502527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2453502527
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1847273704
Short name T319
Test name
Test status
Simulation time 267031081 ps
CPU time 1.34 seconds
Started Aug 13 06:47:21 PM PDT 24
Finished Aug 13 06:47:22 PM PDT 24
Peak memory 219068 kb
Host smart-74faea84-af2b-4e14-b757-51ff577a587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847273704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1847273704
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1709879067
Short name T527
Test name
Test status
Simulation time 320378727 ps
CPU time 1.16 seconds
Started Aug 13 06:47:14 PM PDT 24
Finished Aug 13 06:47:15 PM PDT 24
Peak memory 217620 kb
Host smart-93ac138d-4fe5-4509-a301-88fa13e55817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709879067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1709879067
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2205814086
Short name T899
Test name
Test status
Simulation time 48452367 ps
CPU time 1.46 seconds
Started Aug 13 06:47:21 PM PDT 24
Finished Aug 13 06:47:23 PM PDT 24
Peak memory 219032 kb
Host smart-d36d35d7-4cbd-4f7d-9c27-f4bb89e96bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205814086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2205814086
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3607359042
Short name T721
Test name
Test status
Simulation time 48997616 ps
CPU time 1.79 seconds
Started Aug 13 06:47:30 PM PDT 24
Finished Aug 13 06:47:32 PM PDT 24
Peak memory 218872 kb
Host smart-4eca6ea1-7018-411e-ad69-5a756f2d1f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607359042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3607359042
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.316586215
Short name T799
Test name
Test status
Simulation time 47919686 ps
CPU time 1.19 seconds
Started Aug 13 06:47:30 PM PDT 24
Finished Aug 13 06:47:32 PM PDT 24
Peak memory 217456 kb
Host smart-4da9022f-5bf8-429b-aa29-5592968fbe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316586215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.316586215
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2643482065
Short name T542
Test name
Test status
Simulation time 361774542 ps
CPU time 3.85 seconds
Started Aug 13 06:47:28 PM PDT 24
Finished Aug 13 06:47:32 PM PDT 24
Peak memory 218968 kb
Host smart-bb9a7583-aadb-42b3-bf31-b55cc8e73073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643482065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2643482065
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1260791934
Short name T677
Test name
Test status
Simulation time 20849906 ps
CPU time 1.03 seconds
Started Aug 13 06:47:29 PM PDT 24
Finished Aug 13 06:47:30 PM PDT 24
Peak memory 217504 kb
Host smart-563bdd16-d0aa-4403-b8ed-03fcb6f44367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260791934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1260791934
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.599800243
Short name T820
Test name
Test status
Simulation time 67331254 ps
CPU time 1.11 seconds
Started Aug 13 06:47:48 PM PDT 24
Finished Aug 13 06:47:50 PM PDT 24
Peak memory 219304 kb
Host smart-922621be-834a-459d-a838-5017442d3dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599800243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.599800243
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.696043868
Short name T691
Test name
Test status
Simulation time 109034768 ps
CPU time 1.27 seconds
Started Aug 13 06:45:54 PM PDT 24
Finished Aug 13 06:45:56 PM PDT 24
Peak memory 218860 kb
Host smart-17457275-900c-4f5c-80ba-ed05c3d8be7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696043868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.696043868
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2401958316
Short name T557
Test name
Test status
Simulation time 167402344 ps
CPU time 0.92 seconds
Started Aug 13 06:45:48 PM PDT 24
Finished Aug 13 06:45:49 PM PDT 24
Peak memory 215280 kb
Host smart-cba5622c-4ad5-49be-85fc-7fe67816f0a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401958316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2401958316
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3164831873
Short name T612
Test name
Test status
Simulation time 32989590 ps
CPU time 0.8 seconds
Started Aug 13 06:45:47 PM PDT 24
Finished Aug 13 06:45:48 PM PDT 24
Peak memory 216848 kb
Host smart-8489120b-a023-4342-9221-5ce469f654f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164831873 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3164831873
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1360288870
Short name T502
Test name
Test status
Simulation time 31813031 ps
CPU time 0.98 seconds
Started Aug 13 06:45:55 PM PDT 24
Finished Aug 13 06:45:56 PM PDT 24
Peak memory 217204 kb
Host smart-89259d9d-d06a-452e-b782-208d36458462
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360288870 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1360288870
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1186175598
Short name T671
Test name
Test status
Simulation time 24442628 ps
CPU time 1.06 seconds
Started Aug 13 06:45:49 PM PDT 24
Finished Aug 13 06:45:50 PM PDT 24
Peak memory 224256 kb
Host smart-0171b39a-fdbe-4d06-bed1-f647cd8218a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186175598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1186175598
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.419144021
Short name T771
Test name
Test status
Simulation time 61120296 ps
CPU time 1.23 seconds
Started Aug 13 06:45:48 PM PDT 24
Finished Aug 13 06:45:49 PM PDT 24
Peak memory 218720 kb
Host smart-b4080934-e927-4710-9a6b-cf421b2e3592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419144021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.419144021
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1201707230
Short name T5
Test name
Test status
Simulation time 21944524 ps
CPU time 1.2 seconds
Started Aug 13 06:45:48 PM PDT 24
Finished Aug 13 06:45:50 PM PDT 24
Peak memory 224272 kb
Host smart-9f455a6c-d934-42b0-a9b7-e71c740cec8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201707230 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1201707230
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2882414749
Short name T665
Test name
Test status
Simulation time 34613727 ps
CPU time 0.89 seconds
Started Aug 13 06:46:03 PM PDT 24
Finished Aug 13 06:46:04 PM PDT 24
Peak memory 215560 kb
Host smart-582c3e8b-dbbc-4126-a7ee-eb42f035f499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882414749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2882414749
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.848963855
Short name T376
Test name
Test status
Simulation time 22690924 ps
CPU time 1.05 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 206848 kb
Host smart-1fad7834-b249-4016-9866-41fb52594e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848963855 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.848963855
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1280203272
Short name T733
Test name
Test status
Simulation time 4163114950 ps
CPU time 98.43 seconds
Started Aug 13 06:45:56 PM PDT 24
Finished Aug 13 06:47:35 PM PDT 24
Peak memory 221772 kb
Host smart-f6716ea9-8bb8-4c56-bdb5-de17e639bc27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280203272 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1280203272
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.207624309
Short name T911
Test name
Test status
Simulation time 33194499 ps
CPU time 1.39 seconds
Started Aug 13 06:47:21 PM PDT 24
Finished Aug 13 06:47:23 PM PDT 24
Peak memory 217552 kb
Host smart-f5ac136c-bcd1-44e7-b23a-1b73a1f2174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207624309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.207624309
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1767464956
Short name T460
Test name
Test status
Simulation time 80000429 ps
CPU time 1.25 seconds
Started Aug 13 06:47:27 PM PDT 24
Finished Aug 13 06:47:29 PM PDT 24
Peak memory 217636 kb
Host smart-fcfdacee-257f-402f-837c-78289cfa3699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767464956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1767464956
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1963237608
Short name T553
Test name
Test status
Simulation time 105413773 ps
CPU time 1.16 seconds
Started Aug 13 06:47:13 PM PDT 24
Finished Aug 13 06:47:15 PM PDT 24
Peak memory 219240 kb
Host smart-54005b8b-1f47-4160-8840-e35c3150c7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963237608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1963237608
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.550082535
Short name T347
Test name
Test status
Simulation time 69701033 ps
CPU time 1.05 seconds
Started Aug 13 06:47:13 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 217736 kb
Host smart-0cf4a58b-97e2-4927-82ef-ca0562040fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550082535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.550082535
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.52366570
Short name T411
Test name
Test status
Simulation time 69518252 ps
CPU time 1.39 seconds
Started Aug 13 06:47:33 PM PDT 24
Finished Aug 13 06:47:34 PM PDT 24
Peak memory 219228 kb
Host smart-f1b2689d-b28a-4cce-9531-7c5372b80218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52366570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.52366570
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2937400285
Short name T406
Test name
Test status
Simulation time 104816693 ps
CPU time 1.33 seconds
Started Aug 13 06:47:31 PM PDT 24
Finished Aug 13 06:47:32 PM PDT 24
Peak memory 217644 kb
Host smart-d19f9ddf-8d07-4ead-90f7-136eae509c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937400285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2937400285
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2040311971
Short name T893
Test name
Test status
Simulation time 69367642 ps
CPU time 1.13 seconds
Started Aug 13 06:47:24 PM PDT 24
Finished Aug 13 06:47:26 PM PDT 24
Peak memory 217520 kb
Host smart-c8cdff22-6183-4899-9b24-76df8d323291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040311971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2040311971
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1989226103
Short name T722
Test name
Test status
Simulation time 142815635 ps
CPU time 1.77 seconds
Started Aug 13 06:47:17 PM PDT 24
Finished Aug 13 06:47:19 PM PDT 24
Peak memory 219340 kb
Host smart-36f33674-0a7c-451c-a39d-d3bcf0b38967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989226103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1989226103
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3075363874
Short name T918
Test name
Test status
Simulation time 67378565 ps
CPU time 1.78 seconds
Started Aug 13 06:47:24 PM PDT 24
Finished Aug 13 06:47:26 PM PDT 24
Peak memory 218840 kb
Host smart-9e315961-5a34-45b2-94f7-6b893f29f545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075363874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3075363874
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3569083759
Short name T374
Test name
Test status
Simulation time 36938866 ps
CPU time 1.05 seconds
Started Aug 13 06:47:10 PM PDT 24
Finished Aug 13 06:47:11 PM PDT 24
Peak memory 217504 kb
Host smart-ecc62864-01dc-4699-9dfb-00ebb5c19052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569083759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3569083759
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2140113552
Short name T643
Test name
Test status
Simulation time 85149454 ps
CPU time 1.23 seconds
Started Aug 13 06:45:44 PM PDT 24
Finished Aug 13 06:45:45 PM PDT 24
Peak memory 219000 kb
Host smart-fd3b5dd2-f620-471e-b30c-a2a1586cb53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140113552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2140113552
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1910257855
Short name T464
Test name
Test status
Simulation time 14852874 ps
CPU time 0.87 seconds
Started Aug 13 06:45:35 PM PDT 24
Finished Aug 13 06:45:36 PM PDT 24
Peak memory 215448 kb
Host smart-f2fcac02-5f20-4071-83ec-c7113702e425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910257855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1910257855
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3690997850
Short name T817
Test name
Test status
Simulation time 12098855 ps
CPU time 0.91 seconds
Started Aug 13 06:45:49 PM PDT 24
Finished Aug 13 06:45:50 PM PDT 24
Peak memory 217068 kb
Host smart-b37169f4-6ffd-47dd-b92c-44158161187b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690997850 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3690997850
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.2861754970
Short name T176
Test name
Test status
Simulation time 19574309 ps
CPU time 1.01 seconds
Started Aug 13 06:45:51 PM PDT 24
Finished Aug 13 06:45:52 PM PDT 24
Peak memory 218672 kb
Host smart-04d8b108-6d3b-429b-972a-4dc11c26e7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861754970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2861754970
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_intr.581125694
Short name T121
Test name
Test status
Simulation time 23313921 ps
CPU time 0.94 seconds
Started Aug 13 06:45:48 PM PDT 24
Finished Aug 13 06:45:54 PM PDT 24
Peak memory 216020 kb
Host smart-ee08a8b8-a70d-428b-942e-88a8a9b84d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581125694 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.581125694
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1331740119
Short name T906
Test name
Test status
Simulation time 48771981 ps
CPU time 0.92 seconds
Started Aug 13 06:45:50 PM PDT 24
Finished Aug 13 06:45:51 PM PDT 24
Peak memory 207360 kb
Host smart-f16af7ea-0708-4861-8f8c-069bce5c2ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331740119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1331740119
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1492340751
Short name T357
Test name
Test status
Simulation time 466822788 ps
CPU time 2.69 seconds
Started Aug 13 06:46:03 PM PDT 24
Finished Aug 13 06:46:06 PM PDT 24
Peak memory 217732 kb
Host smart-cfb53d0f-7602-4abe-ad82-93a8019f1092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492340751 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1492340751
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.4201084245
Short name T228
Test name
Test status
Simulation time 18238854862 ps
CPU time 85.03 seconds
Started Aug 13 06:45:42 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 218584 kb
Host smart-f135482e-b73b-4c2a-90f4-0fa2b6ba885b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201084245 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.4201084245
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1565350056
Short name T870
Test name
Test status
Simulation time 146761395 ps
CPU time 1.21 seconds
Started Aug 13 06:47:13 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 220432 kb
Host smart-91096734-17ee-4a15-8561-f12757532a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565350056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1565350056
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2557466111
Short name T723
Test name
Test status
Simulation time 158316258 ps
CPU time 2.18 seconds
Started Aug 13 06:47:20 PM PDT 24
Finished Aug 13 06:47:22 PM PDT 24
Peak memory 220504 kb
Host smart-2b935ea4-97d3-41b9-b52f-0bf70a6a45af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557466111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2557466111
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2579179540
Short name T76
Test name
Test status
Simulation time 57174137 ps
CPU time 1.07 seconds
Started Aug 13 06:47:14 PM PDT 24
Finished Aug 13 06:47:15 PM PDT 24
Peak memory 220228 kb
Host smart-b65b0168-580a-4f4f-80b9-11191e3cf7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579179540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2579179540
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.4250992196
Short name T455
Test name
Test status
Simulation time 75792700 ps
CPU time 1.01 seconds
Started Aug 13 06:47:35 PM PDT 24
Finished Aug 13 06:47:36 PM PDT 24
Peak memory 217620 kb
Host smart-96e48fbb-c6c3-4144-9d84-9cdb808eb4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250992196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4250992196
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.468933892
Short name T737
Test name
Test status
Simulation time 203536868 ps
CPU time 0.96 seconds
Started Aug 13 06:47:12 PM PDT 24
Finished Aug 13 06:47:13 PM PDT 24
Peak memory 217560 kb
Host smart-464b62b9-44de-4ff5-b92d-e9f258492573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468933892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.468933892
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1147864223
Short name T620
Test name
Test status
Simulation time 33440541 ps
CPU time 1.54 seconds
Started Aug 13 06:47:17 PM PDT 24
Finished Aug 13 06:47:19 PM PDT 24
Peak memory 218936 kb
Host smart-80bb9f8c-4b94-4465-897a-ea00da4a95c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147864223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1147864223
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1907919721
Short name T640
Test name
Test status
Simulation time 8745807027 ps
CPU time 118.1 seconds
Started Aug 13 06:47:28 PM PDT 24
Finished Aug 13 06:49:27 PM PDT 24
Peak memory 220796 kb
Host smart-42ad0eb9-cbf9-4433-a374-ec603e4557ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907919721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1907919721
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3435616475
Short name T316
Test name
Test status
Simulation time 175977490 ps
CPU time 2.69 seconds
Started Aug 13 06:47:18 PM PDT 24
Finished Aug 13 06:47:21 PM PDT 24
Peak memory 217824 kb
Host smart-1add1de3-3113-42d3-b13f-188010746fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435616475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3435616475
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2474303810
Short name T493
Test name
Test status
Simulation time 300160553 ps
CPU time 3.86 seconds
Started Aug 13 06:47:11 PM PDT 24
Finished Aug 13 06:47:15 PM PDT 24
Peak memory 220404 kb
Host smart-2d9e78dd-d3ac-457b-85ba-14aa2687334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474303810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2474303810
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1970683667
Short name T96
Test name
Test status
Simulation time 101457000 ps
CPU time 1.17 seconds
Started Aug 13 06:47:15 PM PDT 24
Finished Aug 13 06:47:16 PM PDT 24
Peak memory 217476 kb
Host smart-105129da-ef88-4deb-adc7-49a54819b141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970683667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1970683667
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2383824657
Short name T131
Test name
Test status
Simulation time 78699014 ps
CPU time 1.19 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:45:58 PM PDT 24
Peak memory 219244 kb
Host smart-40a7d9c6-fc11-4bf8-8892-659756173fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383824657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2383824657
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2203957904
Short name T912
Test name
Test status
Simulation time 29199562 ps
CPU time 0.91 seconds
Started Aug 13 06:46:07 PM PDT 24
Finished Aug 13 06:46:08 PM PDT 24
Peak memory 207120 kb
Host smart-cbb93002-96a6-4af6-b090-5b8f592dc837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203957904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2203957904
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.79788434
Short name T159
Test name
Test status
Simulation time 21386535 ps
CPU time 0.89 seconds
Started Aug 13 06:46:00 PM PDT 24
Finished Aug 13 06:46:01 PM PDT 24
Peak memory 215716 kb
Host smart-82102d7e-e348-4db1-819e-3d9db77a295a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79788434 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.79788434
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3810316595
Short name T479
Test name
Test status
Simulation time 50150000 ps
CPU time 1.1 seconds
Started Aug 13 06:45:49 PM PDT 24
Finished Aug 13 06:45:51 PM PDT 24
Peak memory 217240 kb
Host smart-568e47c4-f170-4e8a-94ce-df18c96edc22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810316595 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3810316595
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3459633981
Short name T163
Test name
Test status
Simulation time 18235588 ps
CPU time 1.12 seconds
Started Aug 13 06:45:55 PM PDT 24
Finished Aug 13 06:45:57 PM PDT 24
Peak memory 224184 kb
Host smart-1566b8fe-b8d3-47a3-b180-99ad4268ac7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459633981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3459633981
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1839481156
Short name T966
Test name
Test status
Simulation time 57961454 ps
CPU time 1.39 seconds
Started Aug 13 06:45:48 PM PDT 24
Finished Aug 13 06:45:50 PM PDT 24
Peak memory 220520 kb
Host smart-476ab263-741e-4d41-9b08-7bf858a8a573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839481156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1839481156
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.4140844993
Short name T394
Test name
Test status
Simulation time 41522857 ps
CPU time 0.88 seconds
Started Aug 13 06:45:52 PM PDT 24
Finished Aug 13 06:45:53 PM PDT 24
Peak memory 215612 kb
Host smart-519b5218-8352-4451-a0e9-0c662e849298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140844993 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.4140844993
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2336850506
Short name T753
Test name
Test status
Simulation time 16712648 ps
CPU time 0.99 seconds
Started Aug 13 06:45:58 PM PDT 24
Finished Aug 13 06:45:59 PM PDT 24
Peak memory 215564 kb
Host smart-e1e93399-af9c-48d4-adfd-da9564a5e5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336850506 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2336850506
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2615033487
Short name T352
Test name
Test status
Simulation time 230497318 ps
CPU time 4.87 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:06 PM PDT 24
Peak memory 220352 kb
Host smart-5096325b-8530-4e71-bd7c-d2ea81f77e44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615033487 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2615033487
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1324934629
Short name T614
Test name
Test status
Simulation time 5502710794 ps
CPU time 132.36 seconds
Started Aug 13 06:45:55 PM PDT 24
Finished Aug 13 06:48:08 PM PDT 24
Peak memory 221880 kb
Host smart-a17e1c93-69be-4d76-a4d8-64d8e835e5bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324934629 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1324934629
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2017619000
Short name T375
Test name
Test status
Simulation time 53038327 ps
CPU time 1.55 seconds
Started Aug 13 06:47:30 PM PDT 24
Finished Aug 13 06:47:37 PM PDT 24
Peak memory 217544 kb
Host smart-6a13025e-7cf7-4966-8a56-807aa230a7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017619000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2017619000
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1839452513
Short name T850
Test name
Test status
Simulation time 46947525 ps
CPU time 1.09 seconds
Started Aug 13 06:47:25 PM PDT 24
Finished Aug 13 06:47:26 PM PDT 24
Peak memory 217964 kb
Host smart-76d39d40-8d7a-474c-85a8-59dec9918984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839452513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1839452513
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1395778629
Short name T872
Test name
Test status
Simulation time 224761841 ps
CPU time 1.01 seconds
Started Aug 13 06:47:19 PM PDT 24
Finished Aug 13 06:47:20 PM PDT 24
Peak memory 217500 kb
Host smart-196b4f7e-a73e-4911-9c9d-ff65da8143de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395778629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1395778629
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.4113033881
Short name T1
Test name
Test status
Simulation time 44571732 ps
CPU time 1.18 seconds
Started Aug 13 06:47:17 PM PDT 24
Finished Aug 13 06:47:18 PM PDT 24
Peak memory 218852 kb
Host smart-bb8443f0-5bf1-48f2-b631-77edfe9aa761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113033881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.4113033881
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.836632185
Short name T453
Test name
Test status
Simulation time 110672366 ps
CPU time 1.2 seconds
Started Aug 13 06:47:33 PM PDT 24
Finished Aug 13 06:47:34 PM PDT 24
Peak memory 219284 kb
Host smart-1c802f42-db5c-4def-8593-d23916270864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836632185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.836632185
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.4178172154
Short name T743
Test name
Test status
Simulation time 50808847 ps
CPU time 1.83 seconds
Started Aug 13 06:47:22 PM PDT 24
Finished Aug 13 06:47:24 PM PDT 24
Peak memory 220336 kb
Host smart-e47bf17d-b4c8-4417-987f-70eb18868736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178172154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.4178172154
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3489942319
Short name T731
Test name
Test status
Simulation time 250417690 ps
CPU time 1.4 seconds
Started Aug 13 06:47:45 PM PDT 24
Finished Aug 13 06:47:46 PM PDT 24
Peak memory 218892 kb
Host smart-849eae16-08cf-4e86-b9e4-221e3a97c14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489942319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3489942319
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1784927909
Short name T538
Test name
Test status
Simulation time 45071166 ps
CPU time 1.08 seconds
Started Aug 13 06:47:24 PM PDT 24
Finished Aug 13 06:47:25 PM PDT 24
Peak memory 217568 kb
Host smart-e80cdacb-f57e-4939-84ec-f513f5f48c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784927909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1784927909
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1769069566
Short name T57
Test name
Test status
Simulation time 64828342 ps
CPU time 1.46 seconds
Started Aug 13 06:47:50 PM PDT 24
Finished Aug 13 06:47:51 PM PDT 24
Peak memory 217652 kb
Host smart-a6e14628-3777-40d2-90c5-8344c8d0a9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769069566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1769069566
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.378962948
Short name T477
Test name
Test status
Simulation time 68908872 ps
CPU time 2.09 seconds
Started Aug 13 06:47:20 PM PDT 24
Finished Aug 13 06:47:22 PM PDT 24
Peak memory 218864 kb
Host smart-005832e0-1f20-4a88-a0e1-0888cf1a245a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378962948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.378962948
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3914026758
Short name T773
Test name
Test status
Simulation time 24198270 ps
CPU time 1.22 seconds
Started Aug 13 06:45:58 PM PDT 24
Finished Aug 13 06:45:59 PM PDT 24
Peak memory 218936 kb
Host smart-c1658a62-3a80-49ae-a142-cf7cffe55bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914026758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3914026758
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.623196927
Short name T587
Test name
Test status
Simulation time 17734200 ps
CPU time 0.97 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:45:58 PM PDT 24
Peak memory 207340 kb
Host smart-8d240919-6fe0-4350-ab1d-e150732e851c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623196927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.623196927
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.713349319
Short name T134
Test name
Test status
Simulation time 49258681 ps
CPU time 1.08 seconds
Started Aug 13 06:45:54 PM PDT 24
Finished Aug 13 06:45:55 PM PDT 24
Peak memory 217068 kb
Host smart-5cf439ca-0545-40b1-87bc-b3c7b5921b31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713349319 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.713349319
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3929235928
Short name T631
Test name
Test status
Simulation time 30530784 ps
CPU time 1.02 seconds
Started Aug 13 06:46:00 PM PDT 24
Finished Aug 13 06:46:01 PM PDT 24
Peak memory 218944 kb
Host smart-695e4362-ba09-4320-bf23-6bc5d46cce97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929235928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3929235928
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3459321395
Short name T333
Test name
Test status
Simulation time 70284851 ps
CPU time 1.5 seconds
Started Aug 13 06:45:38 PM PDT 24
Finished Aug 13 06:45:40 PM PDT 24
Peak memory 217544 kb
Host smart-9a3be9c5-c11c-40a2-ada3-60289a36abc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459321395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3459321395
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2055811081
Short name T654
Test name
Test status
Simulation time 38825073 ps
CPU time 0.9 seconds
Started Aug 13 06:45:51 PM PDT 24
Finished Aug 13 06:45:52 PM PDT 24
Peak memory 215728 kb
Host smart-6a43e63e-64b6-4e7e-8a01-d21153b3b9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055811081 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2055811081
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.4050134119
Short name T462
Test name
Test status
Simulation time 44796958 ps
CPU time 0.91 seconds
Started Aug 13 06:45:48 PM PDT 24
Finished Aug 13 06:45:49 PM PDT 24
Peak memory 215596 kb
Host smart-3bdec173-0acd-4c9c-9a95-8da8942eeaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050134119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.4050134119
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.699746579
Short name T558
Test name
Test status
Simulation time 570389875 ps
CPU time 5.73 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:06 PM PDT 24
Peak memory 219036 kb
Host smart-0348b0af-cb1c-48ce-b880-67ea754f11d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699746579 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.699746579
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.540422453
Short name T114
Test name
Test status
Simulation time 5581911499 ps
CPU time 60.93 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:46:37 PM PDT 24
Peak memory 218716 kb
Host smart-dcba0bd5-21f3-46de-8b5a-e20abadf09bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540422453 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.540422453
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1938933636
Short name T933
Test name
Test status
Simulation time 41495634 ps
CPU time 1.18 seconds
Started Aug 13 06:47:09 PM PDT 24
Finished Aug 13 06:47:10 PM PDT 24
Peak memory 219032 kb
Host smart-d1be8761-f321-4146-b7e8-ca1c96582f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938933636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1938933636
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.951893229
Short name T55
Test name
Test status
Simulation time 54878451 ps
CPU time 1.43 seconds
Started Aug 13 06:47:32 PM PDT 24
Finished Aug 13 06:47:34 PM PDT 24
Peak memory 218912 kb
Host smart-a4c4c36b-dcdc-49ef-b1dc-37d16bd43ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951893229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.951893229
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.897989379
Short name T397
Test name
Test status
Simulation time 56133227 ps
CPU time 1.46 seconds
Started Aug 13 06:47:27 PM PDT 24
Finished Aug 13 06:47:29 PM PDT 24
Peak memory 218764 kb
Host smart-eef0a327-f33f-44c6-bde8-58dc45c77ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897989379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.897989379
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1575444157
Short name T652
Test name
Test status
Simulation time 60125995 ps
CPU time 2.04 seconds
Started Aug 13 06:47:27 PM PDT 24
Finished Aug 13 06:47:29 PM PDT 24
Peak memory 218652 kb
Host smart-6a19681c-8581-49c3-ab83-e109e56914f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575444157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1575444157
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.254015044
Short name T680
Test name
Test status
Simulation time 159768321 ps
CPU time 1.18 seconds
Started Aug 13 06:47:17 PM PDT 24
Finished Aug 13 06:47:19 PM PDT 24
Peak memory 217620 kb
Host smart-6bb67d82-58fd-44c8-a051-87d00500414d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254015044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.254015044
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2048023757
Short name T328
Test name
Test status
Simulation time 54645769 ps
CPU time 1.33 seconds
Started Aug 13 06:47:51 PM PDT 24
Finished Aug 13 06:47:53 PM PDT 24
Peak memory 219068 kb
Host smart-1ca0089c-f8d6-4a13-9d17-b69dd67bed05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048023757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2048023757
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3772510921
Short name T13
Test name
Test status
Simulation time 38400806 ps
CPU time 1.35 seconds
Started Aug 13 06:47:32 PM PDT 24
Finished Aug 13 06:47:33 PM PDT 24
Peak memory 217724 kb
Host smart-821093d3-fd1b-453c-802c-fedb570f62d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772510921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3772510921
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.4008800872
Short name T430
Test name
Test status
Simulation time 45507854 ps
CPU time 1.57 seconds
Started Aug 13 06:47:18 PM PDT 24
Finished Aug 13 06:47:19 PM PDT 24
Peak memory 218572 kb
Host smart-7e6a9b93-edcf-4099-94e4-c694a35075c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008800872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.4008800872
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1398995849
Short name T77
Test name
Test status
Simulation time 111558844 ps
CPU time 2.98 seconds
Started Aug 13 06:47:25 PM PDT 24
Finished Aug 13 06:47:28 PM PDT 24
Peak memory 219008 kb
Host smart-ece24137-1269-4e49-94b0-328158ebe6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398995849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1398995849
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2973982293
Short name T469
Test name
Test status
Simulation time 99359772 ps
CPU time 1.18 seconds
Started Aug 13 06:47:19 PM PDT 24
Finished Aug 13 06:47:20 PM PDT 24
Peak memory 217508 kb
Host smart-e60815b2-61a3-4af7-a55b-2b13bb45a9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973982293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2973982293
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.3842972345
Short name T941
Test name
Test status
Simulation time 119855741 ps
CPU time 0.96 seconds
Started Aug 13 06:45:53 PM PDT 24
Finished Aug 13 06:45:54 PM PDT 24
Peak memory 207132 kb
Host smart-d2abc31f-5302-4d0c-b657-9caa5840d828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842972345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3842972345
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1845523501
Short name T172
Test name
Test status
Simulation time 32518022 ps
CPU time 0.81 seconds
Started Aug 13 06:45:53 PM PDT 24
Finished Aug 13 06:45:54 PM PDT 24
Peak memory 216832 kb
Host smart-363b4dfc-dcc5-47b6-bcbc-84bce8d98810
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845523501 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1845523501
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2375849841
Short name T649
Test name
Test status
Simulation time 40910135 ps
CPU time 1.24 seconds
Started Aug 13 06:45:54 PM PDT 24
Finished Aug 13 06:45:55 PM PDT 24
Peak memory 217280 kb
Host smart-4520df8b-3725-4f8d-95da-0109e0a36350
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375849841 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2375849841
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.847166017
Short name T826
Test name
Test status
Simulation time 32597025 ps
CPU time 0.87 seconds
Started Aug 13 06:45:47 PM PDT 24
Finished Aug 13 06:45:48 PM PDT 24
Peak memory 219504 kb
Host smart-3f1459f7-5500-492e-b78b-8607b746f4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847166017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.847166017
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.500454616
Short name T471
Test name
Test status
Simulation time 30581427 ps
CPU time 1.38 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:03 PM PDT 24
Peak memory 218836 kb
Host smart-feb3a5ba-06f4-435c-91fb-b76d738b0b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500454616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.500454616
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1621814536
Short name T34
Test name
Test status
Simulation time 26820829 ps
CPU time 0.87 seconds
Started Aug 13 06:45:46 PM PDT 24
Finished Aug 13 06:45:47 PM PDT 24
Peak memory 215796 kb
Host smart-82921021-1fd5-41a0-a0fc-fb3ffa242ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621814536 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1621814536
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1083923751
Short name T824
Test name
Test status
Simulation time 29514490 ps
CPU time 0.93 seconds
Started Aug 13 06:45:55 PM PDT 24
Finished Aug 13 06:45:56 PM PDT 24
Peak memory 215600 kb
Host smart-5d467eb7-97cf-4162-a662-b3906966a832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083923751 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1083923751
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1774357102
Short name T504
Test name
Test status
Simulation time 106482322 ps
CPU time 2.55 seconds
Started Aug 13 06:45:50 PM PDT 24
Finished Aug 13 06:45:53 PM PDT 24
Peak memory 215516 kb
Host smart-53fddfe7-57e2-4d9d-b79d-8dc5214e64f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774357102 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1774357102
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2623723138
Short name T83
Test name
Test status
Simulation time 8769561679 ps
CPU time 106.79 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:47:44 PM PDT 24
Peak memory 221272 kb
Host smart-0a7b1914-fc72-4f49-940f-5271180fa583
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623723138 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2623723138
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2598350466
Short name T418
Test name
Test status
Simulation time 443746175 ps
CPU time 1.39 seconds
Started Aug 13 06:47:38 PM PDT 24
Finished Aug 13 06:47:39 PM PDT 24
Peak memory 217712 kb
Host smart-2c7e0578-cac7-41c1-be11-857cc81191cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598350466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2598350466
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1903123080
Short name T778
Test name
Test status
Simulation time 53105133 ps
CPU time 1.59 seconds
Started Aug 13 06:47:14 PM PDT 24
Finished Aug 13 06:47:16 PM PDT 24
Peak memory 215616 kb
Host smart-b3ca9d62-a928-4633-9807-344f89ad820a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903123080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1903123080
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.27201705
Short name T548
Test name
Test status
Simulation time 53547277 ps
CPU time 1.67 seconds
Started Aug 13 06:47:09 PM PDT 24
Finished Aug 13 06:47:11 PM PDT 24
Peak memory 219024 kb
Host smart-57fa651e-51f9-48f4-896a-26299a406900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27201705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.27201705
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.4067449771
Short name T311
Test name
Test status
Simulation time 44525769 ps
CPU time 1.65 seconds
Started Aug 13 06:47:45 PM PDT 24
Finished Aug 13 06:47:46 PM PDT 24
Peak memory 220136 kb
Host smart-e2cc584a-8586-442e-838e-38648105512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067449771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.4067449771
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.289547479
Short name T800
Test name
Test status
Simulation time 57962746 ps
CPU time 1.65 seconds
Started Aug 13 06:47:39 PM PDT 24
Finished Aug 13 06:47:41 PM PDT 24
Peak memory 218788 kb
Host smart-8b809d73-a681-4859-bf79-e55944991344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289547479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.289547479
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2587996677
Short name T404
Test name
Test status
Simulation time 85634830 ps
CPU time 1.42 seconds
Started Aug 13 06:47:23 PM PDT 24
Finished Aug 13 06:47:25 PM PDT 24
Peak memory 218872 kb
Host smart-acb88ce2-3e47-4d77-894e-518779c2a6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587996677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2587996677
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3257679315
Short name T482
Test name
Test status
Simulation time 288938323 ps
CPU time 1.87 seconds
Started Aug 13 06:47:22 PM PDT 24
Finished Aug 13 06:47:23 PM PDT 24
Peak memory 219328 kb
Host smart-107a173c-9c92-407c-953d-4d538211ea27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257679315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3257679315
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3641240493
Short name T554
Test name
Test status
Simulation time 140372938 ps
CPU time 2.99 seconds
Started Aug 13 06:47:36 PM PDT 24
Finished Aug 13 06:47:40 PM PDT 24
Peak memory 220384 kb
Host smart-7b519d01-9af4-4c13-8d6f-b6e2b0b57fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641240493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3641240493
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.233754610
Short name T807
Test name
Test status
Simulation time 68600867 ps
CPU time 1.49 seconds
Started Aug 13 06:47:23 PM PDT 24
Finished Aug 13 06:47:25 PM PDT 24
Peak memory 218860 kb
Host smart-fbb02500-d0fa-49e2-9693-92590b95d8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233754610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.233754610
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2549567175
Short name T884
Test name
Test status
Simulation time 137739680 ps
CPU time 3 seconds
Started Aug 13 06:47:18 PM PDT 24
Finished Aug 13 06:47:21 PM PDT 24
Peak memory 218844 kb
Host smart-5efc4bcd-da39-43af-84a3-3d047cbf0acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549567175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2549567175
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.522248487
Short name T174
Test name
Test status
Simulation time 49654321 ps
CPU time 1.02 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 218772 kb
Host smart-52a481bd-8038-4b8c-8f40-24c48c9f5984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522248487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.522248487
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.307432105
Short name T759
Test name
Test status
Simulation time 27855216 ps
CPU time 0.89 seconds
Started Aug 13 06:45:59 PM PDT 24
Finished Aug 13 06:46:00 PM PDT 24
Peak memory 207088 kb
Host smart-22156546-1591-45d8-ae43-276fa6d2b3c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307432105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.307432105
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.4063961546
Short name T93
Test name
Test status
Simulation time 42626562 ps
CPU time 0.85 seconds
Started Aug 13 06:45:59 PM PDT 24
Finished Aug 13 06:46:00 PM PDT 24
Peak memory 216544 kb
Host smart-145b01c1-9152-4777-97f0-335f235a13ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063961546 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.4063961546
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3500708811
Short name T124
Test name
Test status
Simulation time 136564517 ps
CPU time 1.01 seconds
Started Aug 13 06:45:56 PM PDT 24
Finished Aug 13 06:45:57 PM PDT 24
Peak memory 217108 kb
Host smart-dc003742-dec4-4b2b-ae08-f2ac406d2496
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500708811 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3500708811
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2085537785
Short name T168
Test name
Test status
Simulation time 19930341 ps
CPU time 1.15 seconds
Started Aug 13 06:46:09 PM PDT 24
Finished Aug 13 06:46:10 PM PDT 24
Peak memory 224160 kb
Host smart-09fb389f-2cd2-4f7d-bcc7-e0421ff5829e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085537785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2085537785
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1348042441
Short name T632
Test name
Test status
Simulation time 49951731 ps
CPU time 1.17 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 220400 kb
Host smart-ade2fc8e-b0cd-4668-99c5-bf2fe211d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348042441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1348042441
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.4233929732
Short name T638
Test name
Test status
Simulation time 30388089 ps
CPU time 1.12 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 224272 kb
Host smart-e119650c-9a30-4794-9be9-eabd49a0e2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233929732 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4233929732
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3311779335
Short name T344
Test name
Test status
Simulation time 48434255 ps
CPU time 0.91 seconds
Started Aug 13 06:46:18 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 215616 kb
Host smart-87112602-fb29-4fa0-9a1f-b3ab8d8b9638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311779335 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3311779335
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2345496513
Short name T714
Test name
Test status
Simulation time 26379705 ps
CPU time 1.17 seconds
Started Aug 13 06:46:00 PM PDT 24
Finished Aug 13 06:46:01 PM PDT 24
Peak memory 215700 kb
Host smart-54331958-4c7c-4559-ad15-a827bdcbc88c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345496513 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2345496513
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/290.edn_genbits.2179768579
Short name T481
Test name
Test status
Simulation time 120729407 ps
CPU time 1.02 seconds
Started Aug 13 06:47:30 PM PDT 24
Finished Aug 13 06:47:31 PM PDT 24
Peak memory 217480 kb
Host smart-ddd1349c-5793-469e-beea-734a6f14972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179768579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2179768579
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.474398237
Short name T896
Test name
Test status
Simulation time 54519729 ps
CPU time 1.92 seconds
Started Aug 13 06:47:40 PM PDT 24
Finished Aug 13 06:47:42 PM PDT 24
Peak memory 217780 kb
Host smart-af4d681d-5950-4ed9-ae01-62928d1bace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474398237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.474398237
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1636238913
Short name T627
Test name
Test status
Simulation time 63432748 ps
CPU time 1.34 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:55 PM PDT 24
Peak memory 217668 kb
Host smart-a897ca39-be61-46a1-98da-fab84c912e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636238913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1636238913
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2063138243
Short name T15
Test name
Test status
Simulation time 35166263 ps
CPU time 1.08 seconds
Started Aug 13 06:47:47 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 215680 kb
Host smart-0dd8da9a-a36f-4a43-9438-56cf96fff2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063138243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2063138243
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.863253161
Short name T329
Test name
Test status
Simulation time 50584680 ps
CPU time 1.14 seconds
Started Aug 13 06:47:38 PM PDT 24
Finished Aug 13 06:47:39 PM PDT 24
Peak memory 219416 kb
Host smart-6f1f1f51-2827-4462-b33a-311e7412a115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863253161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.863253161
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1880455116
Short name T22
Test name
Test status
Simulation time 44815389 ps
CPU time 1.14 seconds
Started Aug 13 06:47:27 PM PDT 24
Finished Aug 13 06:47:28 PM PDT 24
Peak memory 219316 kb
Host smart-1b4a3ed8-e866-4d61-8a57-12f3b9156780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880455116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1880455116
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3847376927
Short name T839
Test name
Test status
Simulation time 83893569 ps
CPU time 1.33 seconds
Started Aug 13 06:47:50 PM PDT 24
Finished Aug 13 06:47:51 PM PDT 24
Peak memory 219040 kb
Host smart-00e7350b-80ce-4c2e-a31b-084e1bc815ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847376927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3847376927
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2061763372
Short name T734
Test name
Test status
Simulation time 47988043 ps
CPU time 1.14 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:55 PM PDT 24
Peak memory 220488 kb
Host smart-50e479f9-6335-460c-bfe4-6b97901b42e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061763372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2061763372
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.694000179
Short name T857
Test name
Test status
Simulation time 26590512 ps
CPU time 1.23 seconds
Started Aug 13 06:47:32 PM PDT 24
Finished Aug 13 06:47:34 PM PDT 24
Peak memory 217724 kb
Host smart-48210638-352f-44d0-8fac-eba4c34e65ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694000179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.694000179
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1093423916
Short name T828
Test name
Test status
Simulation time 62038696 ps
CPU time 1.52 seconds
Started Aug 13 06:47:43 PM PDT 24
Finished Aug 13 06:47:44 PM PDT 24
Peak memory 218932 kb
Host smart-3c6ff334-77b3-4f7e-999e-4b9fafb1e87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093423916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1093423916
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1763266903
Short name T672
Test name
Test status
Simulation time 159416652 ps
CPU time 1.18 seconds
Started Aug 13 06:45:24 PM PDT 24
Finished Aug 13 06:45:25 PM PDT 24
Peak memory 219672 kb
Host smart-9c1edf77-b12d-4f1a-81c1-a4124b4bf26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763266903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1763266903
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.959347989
Short name T353
Test name
Test status
Simulation time 21591755 ps
CPU time 0.85 seconds
Started Aug 13 06:45:15 PM PDT 24
Finished Aug 13 06:45:16 PM PDT 24
Peak memory 207040 kb
Host smart-e467ce54-bb55-46c9-b6ba-e2abdb2bc421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959347989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.959347989
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.525145348
Short name T564
Test name
Test status
Simulation time 14235984 ps
CPU time 0.95 seconds
Started Aug 13 06:45:08 PM PDT 24
Finished Aug 13 06:45:09 PM PDT 24
Peak memory 217068 kb
Host smart-b97254fe-c41a-4404-88d1-037e2a07f4a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525145348 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.525145348
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1701325798
Short name T475
Test name
Test status
Simulation time 130459747 ps
CPU time 1.24 seconds
Started Aug 13 06:45:16 PM PDT 24
Finished Aug 13 06:45:17 PM PDT 24
Peak memory 217364 kb
Host smart-6da6bd4b-e406-4522-bdaa-321c410b1e08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701325798 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1701325798
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.167358698
Short name T609
Test name
Test status
Simulation time 28263395 ps
CPU time 0.85 seconds
Started Aug 13 06:45:06 PM PDT 24
Finished Aug 13 06:45:07 PM PDT 24
Peak memory 219476 kb
Host smart-7c812763-7671-475d-80e1-37984a872c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167358698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.167358698
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1695260730
Short name T648
Test name
Test status
Simulation time 53818637 ps
CPU time 1.96 seconds
Started Aug 13 06:45:01 PM PDT 24
Finished Aug 13 06:45:03 PM PDT 24
Peak memory 218972 kb
Host smart-eb51d2c4-b993-4145-99c7-3230078a86a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695260730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1695260730
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3490714151
Short name T35
Test name
Test status
Simulation time 20113423 ps
CPU time 1.09 seconds
Started Aug 13 06:45:18 PM PDT 24
Finished Aug 13 06:45:19 PM PDT 24
Peak memory 216104 kb
Host smart-8d378759-4f07-4b4c-b65b-05ecf30401a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490714151 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3490714151
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.447830309
Short name T31
Test name
Test status
Simulation time 17678972 ps
CPU time 0.99 seconds
Started Aug 13 06:45:21 PM PDT 24
Finished Aug 13 06:45:22 PM PDT 24
Peak memory 207480 kb
Host smart-04df5938-fa8f-4bdb-993b-9496e4e058ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447830309 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.447830309
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.518342774
Short name T20
Test name
Test status
Simulation time 2247866877 ps
CPU time 10.38 seconds
Started Aug 13 06:45:24 PM PDT 24
Finished Aug 13 06:45:34 PM PDT 24
Peak memory 241616 kb
Host smart-5147f26e-c147-44df-934a-0d0d92e44ee0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518342774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.518342774
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1431870632
Short name T491
Test name
Test status
Simulation time 52989813 ps
CPU time 0.94 seconds
Started Aug 13 06:45:04 PM PDT 24
Finished Aug 13 06:45:05 PM PDT 24
Peak memory 215584 kb
Host smart-d3d4eb0d-8050-4b43-b233-0f690765737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431870632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1431870632
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3487097355
Short name T819
Test name
Test status
Simulation time 536138935 ps
CPU time 5.91 seconds
Started Aug 13 06:45:24 PM PDT 24
Finished Aug 13 06:45:30 PM PDT 24
Peak memory 217580 kb
Host smart-b932fd2e-02ed-4504-8c37-317e81dfb5b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487097355 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3487097355
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_alert_test.41398733
Short name T463
Test name
Test status
Simulation time 41839964 ps
CPU time 0.84 seconds
Started Aug 13 06:46:00 PM PDT 24
Finished Aug 13 06:46:01 PM PDT 24
Peak memory 207136 kb
Host smart-0fb9d5c6-f10c-45be-8cd3-c00718cced37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41398733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.41398733
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3669140731
Short name T841
Test name
Test status
Simulation time 12499951 ps
CPU time 0.91 seconds
Started Aug 13 06:46:16 PM PDT 24
Finished Aug 13 06:46:17 PM PDT 24
Peak memory 215728 kb
Host smart-8b0b1783-d957-4fc1-a0be-59226710a290
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669140731 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3669140731
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2764372206
Short name T921
Test name
Test status
Simulation time 109731305 ps
CPU time 1.17 seconds
Started Aug 13 06:45:55 PM PDT 24
Finished Aug 13 06:45:56 PM PDT 24
Peak memory 217264 kb
Host smart-e1e431e6-ce35-4d98-a266-b5e951c6c3d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764372206 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2764372206
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1171126019
Short name T123
Test name
Test status
Simulation time 48464452 ps
CPU time 1.22 seconds
Started Aug 13 06:46:12 PM PDT 24
Finished Aug 13 06:46:13 PM PDT 24
Peak memory 229808 kb
Host smart-a2768b83-d86c-405b-a973-d96187aa9700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171126019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1171126019
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1928579657
Short name T91
Test name
Test status
Simulation time 70209125 ps
CPU time 1.44 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:45:59 PM PDT 24
Peak memory 218744 kb
Host smart-173b5167-1d47-4b8d-80c4-46bd9fd45789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928579657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1928579657
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3320295291
Short name T492
Test name
Test status
Simulation time 28941829 ps
CPU time 1.03 seconds
Started Aug 13 06:46:06 PM PDT 24
Finished Aug 13 06:46:07 PM PDT 24
Peak memory 224244 kb
Host smart-c2c558e6-4ff5-41ab-955a-03e12a9a82a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320295291 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3320295291
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2016246560
Short name T887
Test name
Test status
Simulation time 17676092 ps
CPU time 0.96 seconds
Started Aug 13 06:45:56 PM PDT 24
Finished Aug 13 06:45:57 PM PDT 24
Peak memory 215620 kb
Host smart-3df16fa6-d78d-4760-b497-7589531808c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016246560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2016246560
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1090242730
Short name T239
Test name
Test status
Simulation time 69458357 ps
CPU time 1.87 seconds
Started Aug 13 06:46:00 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 215516 kb
Host smart-34b10d2f-6374-4c52-b6d2-08a5d915a4b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090242730 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1090242730
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1002655166
Short name T583
Test name
Test status
Simulation time 2502703455 ps
CPU time 56.42 seconds
Started Aug 13 06:46:12 PM PDT 24
Finished Aug 13 06:47:09 PM PDT 24
Peak memory 219256 kb
Host smart-d950ff10-b6e3-4178-b281-c65a272ce478
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002655166 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1002655166
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3001718958
Short name T116
Test name
Test status
Simulation time 158682260 ps
CPU time 1.1 seconds
Started Aug 13 06:46:09 PM PDT 24
Finished Aug 13 06:46:10 PM PDT 24
Peak memory 219556 kb
Host smart-9d277150-6e9e-41d3-82c5-947e868bd827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001718958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3001718958
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.884128245
Short name T624
Test name
Test status
Simulation time 78441535 ps
CPU time 0.87 seconds
Started Aug 13 06:46:13 PM PDT 24
Finished Aug 13 06:46:14 PM PDT 24
Peak memory 207076 kb
Host smart-d0d697e7-35dd-41ac-bc52-850fb9a733ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884128245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.884128245
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3303438777
Short name T360
Test name
Test status
Simulation time 123093814 ps
CPU time 0.86 seconds
Started Aug 13 06:45:58 PM PDT 24
Finished Aug 13 06:45:59 PM PDT 24
Peak memory 216628 kb
Host smart-2f53de39-7a52-472f-a47b-d50b3f0f6077
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303438777 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3303438777
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1337906239
Short name T653
Test name
Test status
Simulation time 36564169 ps
CPU time 1.23 seconds
Started Aug 13 06:46:04 PM PDT 24
Finished Aug 13 06:46:05 PM PDT 24
Peak memory 218752 kb
Host smart-54ec5a1f-dce6-4ba5-ba73-0a72479e1483
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337906239 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1337906239
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2092560002
Short name T526
Test name
Test status
Simulation time 33025571 ps
CPU time 0.94 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:45:58 PM PDT 24
Peak memory 219980 kb
Host smart-c2d47d87-8063-4056-a937-74a9308e781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092560002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2092560002
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1422932540
Short name T317
Test name
Test status
Simulation time 70813451 ps
CPU time 1.09 seconds
Started Aug 13 06:46:05 PM PDT 24
Finished Aug 13 06:46:06 PM PDT 24
Peak memory 217512 kb
Host smart-756bae60-3804-4ec0-9600-528e7a9c5990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422932540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1422932540
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_smoke.3061008125
Short name T371
Test name
Test status
Simulation time 24926623 ps
CPU time 0.91 seconds
Started Aug 13 06:46:07 PM PDT 24
Finished Aug 13 06:46:08 PM PDT 24
Peak memory 215592 kb
Host smart-e96bd1bc-bb6d-4b9f-a24a-9cbba63cce78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061008125 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3061008125
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4027416696
Short name T237
Test name
Test status
Simulation time 166675183 ps
CPU time 2.28 seconds
Started Aug 13 06:45:56 PM PDT 24
Finished Aug 13 06:45:58 PM PDT 24
Peak memory 215732 kb
Host smart-af98ae88-b63a-4f84-a09e-effb9c3399f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027416696 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4027416696
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_alert.1492134391
Short name T957
Test name
Test status
Simulation time 39792521 ps
CPU time 1.25 seconds
Started Aug 13 06:46:08 PM PDT 24
Finished Aug 13 06:46:10 PM PDT 24
Peak memory 219932 kb
Host smart-74988d1c-5789-4036-b917-916d9a6b4a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492134391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1492134391
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3505763638
Short name T626
Test name
Test status
Simulation time 48539647 ps
CPU time 0.91 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:45:58 PM PDT 24
Peak memory 207096 kb
Host smart-91ee6fb5-ccdb-4877-94cd-82902fb9d4b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505763638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3505763638
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.58696381
Short name T969
Test name
Test status
Simulation time 11829069 ps
CPU time 0.91 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 217032 kb
Host smart-1764f0ed-6e17-4d74-a38e-caba2a7d1536
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58696381 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.58696381
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3938155919
Short name T205
Test name
Test status
Simulation time 64856638 ps
CPU time 1.21 seconds
Started Aug 13 06:45:55 PM PDT 24
Finished Aug 13 06:45:56 PM PDT 24
Peak memory 217144 kb
Host smart-4b1169d3-f743-4fee-891c-c5dc986270e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938155919 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3938155919
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.366485230
Short name T858
Test name
Test status
Simulation time 97048021 ps
CPU time 0.95 seconds
Started Aug 13 06:46:19 PM PDT 24
Finished Aug 13 06:46:21 PM PDT 24
Peak memory 218728 kb
Host smart-4bee5246-1c0f-4ccc-a2c4-36c5350b7b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366485230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.366485230
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.4075279645
Short name T794
Test name
Test status
Simulation time 41748742 ps
CPU time 1.53 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:03 PM PDT 24
Peak memory 217876 kb
Host smart-bb1666a6-cc12-440f-aa7c-8e9d316402af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075279645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.4075279645
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2268203651
Short name T657
Test name
Test status
Simulation time 30659301 ps
CPU time 0.92 seconds
Started Aug 13 06:46:13 PM PDT 24
Finished Aug 13 06:46:14 PM PDT 24
Peak memory 215740 kb
Host smart-aec33bd8-825e-4bcb-bf04-f4c8fa40a190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268203651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2268203651
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.43160988
Short name T400
Test name
Test status
Simulation time 16243283 ps
CPU time 0.98 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:45:58 PM PDT 24
Peak memory 215620 kb
Host smart-07c5fecb-85f8-4068-bc69-9e5d0d233306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43160988 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.43160988
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2360144537
Short name T238
Test name
Test status
Simulation time 140588514 ps
CPU time 2.8 seconds
Started Aug 13 06:46:15 PM PDT 24
Finished Aug 13 06:46:18 PM PDT 24
Peak memory 220280 kb
Host smart-e75ac321-9cab-4865-9e0a-7b4a59595991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360144537 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2360144537
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_alert.3770866528
Short name T742
Test name
Test status
Simulation time 89381153 ps
CPU time 1.19 seconds
Started Aug 13 06:45:55 PM PDT 24
Finished Aug 13 06:45:56 PM PDT 24
Peak memory 218636 kb
Host smart-cab05115-f694-46e6-a7f5-d6e4458e73a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770866528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3770866528
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.947964280
Short name T417
Test name
Test status
Simulation time 22884520 ps
CPU time 0.82 seconds
Started Aug 13 06:46:04 PM PDT 24
Finished Aug 13 06:46:04 PM PDT 24
Peak memory 207196 kb
Host smart-29707097-42ab-43b6-9f9a-232102ace695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947964280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.947964280
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1165496848
Short name T550
Test name
Test status
Simulation time 29994729 ps
CPU time 1.52 seconds
Started Aug 13 06:45:58 PM PDT 24
Finished Aug 13 06:46:00 PM PDT 24
Peak memory 219000 kb
Host smart-9e478bbe-11e2-455c-96c5-c7f063282592
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165496848 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1165496848
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2663212775
Short name T480
Test name
Test status
Simulation time 25969654 ps
CPU time 1 seconds
Started Aug 13 06:45:56 PM PDT 24
Finished Aug 13 06:45:57 PM PDT 24
Peak memory 218796 kb
Host smart-890c85fb-4eb5-4532-8b5b-0cee9266a426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663212775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2663212775
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3777467724
Short name T831
Test name
Test status
Simulation time 120234863 ps
CPU time 1.31 seconds
Started Aug 13 06:46:08 PM PDT 24
Finished Aug 13 06:46:09 PM PDT 24
Peak memory 220492 kb
Host smart-95180bb1-df0b-48e6-82db-e710d93b2860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777467724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3777467724
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.527551217
Short name T956
Test name
Test status
Simulation time 21289327 ps
CPU time 1.13 seconds
Started Aug 13 06:45:55 PM PDT 24
Finished Aug 13 06:45:57 PM PDT 24
Peak memory 215792 kb
Host smart-4c19d189-4e2d-4f2e-9c45-462d10469f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527551217 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.527551217
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2228687426
Short name T616
Test name
Test status
Simulation time 15833367 ps
CPU time 0.99 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 215572 kb
Host smart-242d695d-d9e8-40d9-beab-9e3ae7b294ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228687426 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2228687426
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3119602014
Short name T861
Test name
Test status
Simulation time 400462567 ps
CPU time 4.39 seconds
Started Aug 13 06:45:58 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 215628 kb
Host smart-795339c8-b448-4f72-9815-e17a7f99ee67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119602014 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3119602014
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3229179768
Short name T222
Test name
Test status
Simulation time 1787333315 ps
CPU time 46.73 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:46:44 PM PDT 24
Peak memory 218920 kb
Host smart-cdb38730-90a8-4ef1-913a-8431e4d64eaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229179768 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3229179768
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1019439891
Short name T629
Test name
Test status
Simulation time 38951033 ps
CPU time 1.09 seconds
Started Aug 13 06:45:50 PM PDT 24
Finished Aug 13 06:45:52 PM PDT 24
Peak memory 219684 kb
Host smart-bb4b4d01-f0f6-4d50-8a42-3c4c1ae39948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019439891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1019439891
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3007036976
Short name T354
Test name
Test status
Simulation time 24819456 ps
CPU time 1 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 215412 kb
Host smart-ca27796a-e9e0-4b8f-b0c9-61691cc10fa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007036976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3007036976
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3454119567
Short name T424
Test name
Test status
Simulation time 21979461 ps
CPU time 0.85 seconds
Started Aug 13 06:46:03 PM PDT 24
Finished Aug 13 06:46:04 PM PDT 24
Peak memory 216496 kb
Host smart-573f3749-d7c5-476d-906d-27cb5658ca81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454119567 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3454119567
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2080234595
Short name T277
Test name
Test status
Simulation time 89408406 ps
CPU time 1.04 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 217052 kb
Host smart-40a7382d-79af-416b-948e-987f7b8a3e2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080234595 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2080234595
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2689732778
Short name T588
Test name
Test status
Simulation time 32644375 ps
CPU time 0.86 seconds
Started Aug 13 06:45:56 PM PDT 24
Finished Aug 13 06:45:57 PM PDT 24
Peak memory 219516 kb
Host smart-e7df2195-267c-4c9b-b2c2-fab1d817ded0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689732778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2689732778
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.724687737
Short name T621
Test name
Test status
Simulation time 29031064 ps
CPU time 1.16 seconds
Started Aug 13 06:45:54 PM PDT 24
Finished Aug 13 06:45:56 PM PDT 24
Peak memory 217540 kb
Host smart-5727cb1d-a2ad-4875-b7ba-d980297127e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724687737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.724687737
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.554914549
Short name T790
Test name
Test status
Simulation time 22776052 ps
CPU time 1.09 seconds
Started Aug 13 06:45:52 PM PDT 24
Finished Aug 13 06:45:53 PM PDT 24
Peak memory 215624 kb
Host smart-e5b6f913-63c6-49d4-bddd-06598feb48e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554914549 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.554914549
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3547315041
Short name T520
Test name
Test status
Simulation time 17397313 ps
CPU time 1.02 seconds
Started Aug 13 06:46:04 PM PDT 24
Finished Aug 13 06:46:05 PM PDT 24
Peak memory 215544 kb
Host smart-d5248fbb-e394-47f7-a110-411404d7c2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547315041 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3547315041
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3262575985
Short name T685
Test name
Test status
Simulation time 78510013 ps
CPU time 1.43 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:45:59 PM PDT 24
Peak memory 215620 kb
Host smart-ed2d0369-d805-4618-8427-f31fc11dda42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262575985 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3262575985
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_alert.1650502310
Short name T700
Test name
Test status
Simulation time 39891324 ps
CPU time 1.08 seconds
Started Aug 13 06:46:06 PM PDT 24
Finished Aug 13 06:46:08 PM PDT 24
Peak memory 218880 kb
Host smart-3bcebf40-c581-4d84-8b34-4eb41a2ac95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650502310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1650502310
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1838742352
Short name T836
Test name
Test status
Simulation time 49551582 ps
CPU time 0.87 seconds
Started Aug 13 06:46:05 PM PDT 24
Finished Aug 13 06:46:11 PM PDT 24
Peak memory 207064 kb
Host smart-048cea8e-8037-4fe6-900a-ea069e9ff420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838742352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1838742352
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.647106617
Short name T835
Test name
Test status
Simulation time 10987801 ps
CPU time 0.9 seconds
Started Aug 13 06:46:07 PM PDT 24
Finished Aug 13 06:46:08 PM PDT 24
Peak memory 215708 kb
Host smart-2f7fd356-084c-4d64-bf29-8e600a139367
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647106617 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.647106617
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3211425005
Short name T73
Test name
Test status
Simulation time 88551465 ps
CPU time 1.09 seconds
Started Aug 13 06:46:10 PM PDT 24
Finished Aug 13 06:46:12 PM PDT 24
Peak memory 217204 kb
Host smart-dcc92abd-7daf-4f3f-b554-cd8d00c336a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211425005 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3211425005
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1775491407
Short name T883
Test name
Test status
Simulation time 25731188 ps
CPU time 0.94 seconds
Started Aug 13 06:45:52 PM PDT 24
Finished Aug 13 06:45:53 PM PDT 24
Peak memory 218916 kb
Host smart-e213cad8-86c1-4d7c-94b9-9565c23b7767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775491407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1775491407
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.4195283792
Short name T876
Test name
Test status
Simulation time 68058980 ps
CPU time 1.32 seconds
Started Aug 13 06:46:05 PM PDT 24
Finished Aug 13 06:46:06 PM PDT 24
Peak memory 218808 kb
Host smart-7753a3e5-c9f8-47d7-af21-e6b544247c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195283792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.4195283792
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3825428348
Short name T622
Test name
Test status
Simulation time 22022629 ps
CPU time 1.23 seconds
Started Aug 13 06:45:56 PM PDT 24
Finished Aug 13 06:45:57 PM PDT 24
Peak memory 224204 kb
Host smart-eb39c319-bf63-4630-b849-d0c433666506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825428348 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3825428348
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.337246494
Short name T85
Test name
Test status
Simulation time 25405044 ps
CPU time 0.93 seconds
Started Aug 13 06:46:03 PM PDT 24
Finished Aug 13 06:46:04 PM PDT 24
Peak memory 215520 kb
Host smart-2978f957-9bdb-42b6-ab49-309af2d53a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337246494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.337246494
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1009892499
Short name T494
Test name
Test status
Simulation time 253063786 ps
CPU time 4.73 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 220476 kb
Host smart-d7c0e9e9-a0ee-4ee8-ab59-dfa602c95041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009892499 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1009892499
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_alert.3700378707
Short name T407
Test name
Test status
Simulation time 79650582 ps
CPU time 1.16 seconds
Started Aug 13 06:46:00 PM PDT 24
Finished Aug 13 06:46:01 PM PDT 24
Peak memory 219552 kb
Host smart-ce7e6e96-acb5-4d0d-8238-085e64d316d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700378707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3700378707
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.554202778
Short name T80
Test name
Test status
Simulation time 17637310 ps
CPU time 0.84 seconds
Started Aug 13 06:46:14 PM PDT 24
Finished Aug 13 06:46:15 PM PDT 24
Peak memory 207172 kb
Host smart-40299652-a4a6-43c9-9ff8-a32dd524bebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554202778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.554202778
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.417838376
Short name T512
Test name
Test status
Simulation time 42023136 ps
CPU time 1 seconds
Started Aug 13 06:46:02 PM PDT 24
Finished Aug 13 06:46:03 PM PDT 24
Peak memory 217404 kb
Host smart-6d6e920d-d6f8-4884-aba7-fd585b0f3959
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417838376 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.417838376
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_genbits.2227992383
Short name T517
Test name
Test status
Simulation time 99613023 ps
CPU time 1.55 seconds
Started Aug 13 06:45:59 PM PDT 24
Finished Aug 13 06:46:00 PM PDT 24
Peak memory 219048 kb
Host smart-5c572c3a-083a-426e-ac1d-6f7a6060fff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227992383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2227992383
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2964503290
Short name T900
Test name
Test status
Simulation time 31380315 ps
CPU time 0.87 seconds
Started Aug 13 06:46:03 PM PDT 24
Finished Aug 13 06:46:04 PM PDT 24
Peak memory 215888 kb
Host smart-9d11d0aa-e052-472d-ba8d-1a3d9c0da818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964503290 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2964503290
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1860022368
Short name T511
Test name
Test status
Simulation time 34063488 ps
CPU time 0.95 seconds
Started Aug 13 06:45:53 PM PDT 24
Finished Aug 13 06:45:54 PM PDT 24
Peak memory 215572 kb
Host smart-39fc985a-395a-42a8-abdd-698597bdc051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860022368 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1860022368
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.938686029
Short name T930
Test name
Test status
Simulation time 260486440 ps
CPU time 5.27 seconds
Started Aug 13 06:46:03 PM PDT 24
Finished Aug 13 06:46:08 PM PDT 24
Peak memory 217712 kb
Host smart-a7ff2178-155b-49e5-a6d9-a1b2190f352a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938686029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.938686029
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2110967998
Short name T764
Test name
Test status
Simulation time 15418338803 ps
CPU time 87.44 seconds
Started Aug 13 06:46:02 PM PDT 24
Finished Aug 13 06:47:29 PM PDT 24
Peak memory 221400 kb
Host smart-ea903a2c-9da0-4191-aae6-ea8a86e62eaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110967998 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2110967998
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2221963969
Short name T166
Test name
Test status
Simulation time 38399740 ps
CPU time 1.06 seconds
Started Aug 13 06:45:54 PM PDT 24
Finished Aug 13 06:45:55 PM PDT 24
Peak memory 218696 kb
Host smart-2206a6f1-f1ab-4c63-897e-8f5aac0cc13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221963969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2221963969
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2616011432
Short name T429
Test name
Test status
Simulation time 82127424 ps
CPU time 0.98 seconds
Started Aug 13 06:45:57 PM PDT 24
Finished Aug 13 06:45:59 PM PDT 24
Peak memory 215260 kb
Host smart-4b39e85d-8c61-408f-990b-a57b900bd7f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616011432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2616011432
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.193342036
Short name T186
Test name
Test status
Simulation time 14118041 ps
CPU time 1 seconds
Started Aug 13 06:46:02 PM PDT 24
Finished Aug 13 06:46:03 PM PDT 24
Peak memory 219748 kb
Host smart-0748d865-0068-428f-9afe-c38d5fa93dc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193342036 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.193342036
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3528855095
Short name T212
Test name
Test status
Simulation time 58602555 ps
CPU time 1.15 seconds
Started Aug 13 06:46:05 PM PDT 24
Finished Aug 13 06:46:06 PM PDT 24
Peak memory 217296 kb
Host smart-8feb1576-917a-4a0e-90b8-c37f11d48e96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528855095 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3528855095
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.4214358251
Short name T142
Test name
Test status
Simulation time 32347274 ps
CPU time 1.02 seconds
Started Aug 13 06:46:04 PM PDT 24
Finished Aug 13 06:46:05 PM PDT 24
Peak memory 229772 kb
Host smart-3aaf310c-0f94-498b-9cf3-440832d12ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214358251 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.4214358251
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3484114461
Short name T571
Test name
Test status
Simulation time 201514857 ps
CPU time 2.78 seconds
Started Aug 13 06:45:56 PM PDT 24
Finished Aug 13 06:45:58 PM PDT 24
Peak memory 220328 kb
Host smart-205d598a-80af-4552-bab5-93270c2f786a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484114461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3484114461
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2515644988
Short name T40
Test name
Test status
Simulation time 19930066 ps
CPU time 1.15 seconds
Started Aug 13 06:45:53 PM PDT 24
Finished Aug 13 06:45:54 PM PDT 24
Peak memory 216036 kb
Host smart-3a8c4103-2f9a-48cf-9085-fe054ea8dce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515644988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2515644988
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2549830180
Short name T895
Test name
Test status
Simulation time 44722080 ps
CPU time 0.86 seconds
Started Aug 13 06:45:59 PM PDT 24
Finished Aug 13 06:46:00 PM PDT 24
Peak memory 215604 kb
Host smart-f9ad63ad-f611-43ef-8a48-e6170dbb60b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549830180 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2549830180
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1910956845
Short name T197
Test name
Test status
Simulation time 219635140 ps
CPU time 2.78 seconds
Started Aug 13 06:46:18 PM PDT 24
Finished Aug 13 06:46:21 PM PDT 24
Peak memory 217404 kb
Host smart-0e98ecc8-3af1-40db-87d1-c31aa4d972c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910956845 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1910956845
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_alert.2215554828
Short name T581
Test name
Test status
Simulation time 42433166 ps
CPU time 1.16 seconds
Started Aug 13 06:46:27 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 218924 kb
Host smart-b563e8b0-69d4-4c4f-99e1-aa3cdf80d622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215554828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2215554828
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3942680092
Short name T528
Test name
Test status
Simulation time 22470706 ps
CPU time 0.85 seconds
Started Aug 13 06:45:58 PM PDT 24
Finished Aug 13 06:45:59 PM PDT 24
Peak memory 207124 kb
Host smart-8d338aef-b9e7-40b2-a845-35abfa79807a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942680092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3942680092
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1012642931
Short name T821
Test name
Test status
Simulation time 12874861 ps
CPU time 0.89 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 216704 kb
Host smart-59ab0f66-a1e9-4cb1-b313-dee0a1c1de56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012642931 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1012642931
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1109035714
Short name T152
Test name
Test status
Simulation time 85503635 ps
CPU time 1.02 seconds
Started Aug 13 06:46:13 PM PDT 24
Finished Aug 13 06:46:14 PM PDT 24
Peak memory 217192 kb
Host smart-44725614-cd54-4814-b71b-4e626c97ed97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109035714 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1109035714
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2798347589
Short name T707
Test name
Test status
Simulation time 21122368 ps
CPU time 1.2 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 229872 kb
Host smart-eed2425d-8e15-4415-83fe-7acd060a1e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798347589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2798347589
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.346331985
Short name T415
Test name
Test status
Simulation time 91297536 ps
CPU time 1.4 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:25 PM PDT 24
Peak memory 219008 kb
Host smart-474d3618-0d20-4112-9bca-2aaae771dfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346331985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.346331985
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2938696848
Short name T940
Test name
Test status
Simulation time 23583418 ps
CPU time 1.04 seconds
Started Aug 13 06:46:11 PM PDT 24
Finished Aug 13 06:46:13 PM PDT 24
Peak memory 216104 kb
Host smart-48d318c4-410b-43bb-8653-c8f2057c6d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938696848 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2938696848
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1558300775
Short name T496
Test name
Test status
Simulation time 62414335 ps
CPU time 0.95 seconds
Started Aug 13 06:46:14 PM PDT 24
Finished Aug 13 06:46:15 PM PDT 24
Peak memory 215628 kb
Host smart-0ec8e52d-1e77-4300-ae1a-2ddb6d5fa20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558300775 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1558300775
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.687297509
Short name T728
Test name
Test status
Simulation time 56736674 ps
CPU time 1.61 seconds
Started Aug 13 06:46:14 PM PDT 24
Finished Aug 13 06:46:15 PM PDT 24
Peak memory 218728 kb
Host smart-7f4ff552-6172-4a3f-b887-babebc9c4745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687297509 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.687297509
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_alert.59537023
Short name T391
Test name
Test status
Simulation time 45343924 ps
CPU time 1.17 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 220080 kb
Host smart-b6423a06-eaf4-4cdc-95a0-5d873e4db815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59537023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.59537023
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1654715666
Short name T398
Test name
Test status
Simulation time 12575423 ps
CPU time 0.9 seconds
Started Aug 13 06:46:14 PM PDT 24
Finished Aug 13 06:46:15 PM PDT 24
Peak memory 215472 kb
Host smart-57739cac-5067-4625-84e9-b7c6bfead203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654715666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1654715666
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1027547790
Short name T534
Test name
Test status
Simulation time 14081274 ps
CPU time 0.94 seconds
Started Aug 13 06:46:21 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 216688 kb
Host smart-37e793d2-f4cb-40fa-b88b-aa5c42708992
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027547790 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1027547790
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.804775841
Short name T75
Test name
Test status
Simulation time 73928864 ps
CPU time 1.43 seconds
Started Aug 13 06:46:17 PM PDT 24
Finished Aug 13 06:46:19 PM PDT 24
Peak memory 217128 kb
Host smart-dce19ba0-905d-4ac3-a6dd-53e4cfbe2d34
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804775841 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.804775841
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2716238467
Short name T465
Test name
Test status
Simulation time 31296716 ps
CPU time 0.98 seconds
Started Aug 13 06:46:12 PM PDT 24
Finished Aug 13 06:46:14 PM PDT 24
Peak memory 218952 kb
Host smart-021c45ca-3208-40a3-85c0-b32ebea76eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716238467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2716238467
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2272321385
Short name T507
Test name
Test status
Simulation time 44168017 ps
CPU time 1.54 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 217740 kb
Host smart-1f42b393-acdc-49e6-ab6e-00dcad3930e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272321385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2272321385
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2346024582
Short name T33
Test name
Test status
Simulation time 34756064 ps
CPU time 0.89 seconds
Started Aug 13 06:46:08 PM PDT 24
Finished Aug 13 06:46:09 PM PDT 24
Peak memory 216104 kb
Host smart-6d79a49c-52ce-4386-99f5-84664b8acf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346024582 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2346024582
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3996891082
Short name T679
Test name
Test status
Simulation time 55270229 ps
CPU time 0.92 seconds
Started Aug 13 06:46:21 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 215540 kb
Host smart-0a3f5031-0f0f-4d17-b24e-7e608a6c1316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996891082 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3996891082
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1232552323
Short name T611
Test name
Test status
Simulation time 834968839 ps
CPU time 4.02 seconds
Started Aug 13 06:46:17 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 217508 kb
Host smart-f24efdf2-027d-4914-8986-33ebd2139ae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232552323 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1232552323
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2715095142
Short name T848
Test name
Test status
Simulation time 10850088810 ps
CPU time 65.18 seconds
Started Aug 13 06:46:13 PM PDT 24
Finished Aug 13 06:47:18 PM PDT 24
Peak memory 215776 kb
Host smart-3d972c39-32d3-44e2-84b2-2451bddf36ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715095142 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2715095142
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert_test.604683260
Short name T552
Test name
Test status
Simulation time 52646996 ps
CPU time 0.91 seconds
Started Aug 13 06:45:20 PM PDT 24
Finished Aug 13 06:45:21 PM PDT 24
Peak memory 207076 kb
Host smart-20ae7cac-c330-4cea-8db9-c3493580e112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604683260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.604683260
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1880541892
Short name T135
Test name
Test status
Simulation time 46664195 ps
CPU time 1.14 seconds
Started Aug 13 06:45:20 PM PDT 24
Finished Aug 13 06:45:21 PM PDT 24
Peak memory 217324 kb
Host smart-3649aa5f-daf9-46b7-8b64-211355a10814
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880541892 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1880541892
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3863929512
Short name T886
Test name
Test status
Simulation time 45532140 ps
CPU time 1.14 seconds
Started Aug 13 06:45:17 PM PDT 24
Finished Aug 13 06:45:19 PM PDT 24
Peak memory 224192 kb
Host smart-bbc83810-f88d-4fb8-9396-f4393258c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863929512 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3863929512
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3179940165
Short name T433
Test name
Test status
Simulation time 57780955 ps
CPU time 1.61 seconds
Started Aug 13 06:45:23 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 218816 kb
Host smart-de644782-c0dc-428c-9cdf-453fe780ea14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179940165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3179940165
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2553846009
Short name T720
Test name
Test status
Simulation time 86366080 ps
CPU time 0.95 seconds
Started Aug 13 06:45:22 PM PDT 24
Finished Aug 13 06:45:23 PM PDT 24
Peak memory 224024 kb
Host smart-7c6ae6ab-a61e-45e7-b2cf-0b7112bbc445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553846009 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2553846009
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3382108760
Short name T30
Test name
Test status
Simulation time 137842308 ps
CPU time 0.89 seconds
Started Aug 13 06:45:29 PM PDT 24
Finished Aug 13 06:45:30 PM PDT 24
Peak memory 207456 kb
Host smart-7e995e36-478e-4bc4-97fb-b0d0f0edf4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382108760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3382108760
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3658628607
Short name T346
Test name
Test status
Simulation time 19669590 ps
CPU time 1.05 seconds
Started Aug 13 06:45:17 PM PDT 24
Finished Aug 13 06:45:18 PM PDT 24
Peak memory 215580 kb
Host smart-54840627-d416-4137-8ca8-71ed76be597c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658628607 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3658628607
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3367136795
Short name T3
Test name
Test status
Simulation time 1090102881 ps
CPU time 3.21 seconds
Started Aug 13 06:45:21 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 215648 kb
Host smart-d8f7fef0-b6eb-4552-b0f9-4eb82856485b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367136795 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3367136795
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1068899051
Short name T751
Test name
Test status
Simulation time 2373214415 ps
CPU time 69.6 seconds
Started Aug 13 06:45:14 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 218784 kb
Host smart-5fe5730d-46bb-48da-bf82-9323babae9b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068899051 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1068899051
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1314756165
Short name T522
Test name
Test status
Simulation time 63267921 ps
CPU time 1.07 seconds
Started Aug 13 06:46:19 PM PDT 24
Finished Aug 13 06:46:20 PM PDT 24
Peak memory 220172 kb
Host smart-25ca753f-b7f2-429d-b226-b6c3ebb37e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314756165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1314756165
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.578985776
Short name T549
Test name
Test status
Simulation time 44154326 ps
CPU time 0.82 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:25 PM PDT 24
Peak memory 207044 kb
Host smart-9bd21421-eb0b-46db-907c-a639f197f3be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578985776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.578985776
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3375023522
Short name T202
Test name
Test status
Simulation time 35522365 ps
CPU time 0.83 seconds
Started Aug 13 06:46:10 PM PDT 24
Finished Aug 13 06:46:11 PM PDT 24
Peak memory 216868 kb
Host smart-0e2387c6-e916-443b-8e12-52e92e8ad63f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375023522 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3375023522
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.4285000942
Short name T763
Test name
Test status
Simulation time 42102101 ps
CPU time 0.78 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:23 PM PDT 24
Peak memory 218504 kb
Host smart-be231e07-f15f-4ea5-82c2-27c108813b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285000942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.4285000942
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2441149463
Short name T970
Test name
Test status
Simulation time 43839609 ps
CPU time 1.49 seconds
Started Aug 13 06:46:10 PM PDT 24
Finished Aug 13 06:46:12 PM PDT 24
Peak memory 219044 kb
Host smart-0b02a5ca-c05c-469d-8e69-faa07b2c6b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441149463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2441149463
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3136031831
Short name T431
Test name
Test status
Simulation time 33674026 ps
CPU time 0.9 seconds
Started Aug 13 06:46:16 PM PDT 24
Finished Aug 13 06:46:17 PM PDT 24
Peak memory 215688 kb
Host smart-2533c5a2-4dc2-4d75-a25e-3255e00ce694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136031831 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3136031831
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.4162191713
Short name T617
Test name
Test status
Simulation time 18120555 ps
CPU time 0.99 seconds
Started Aug 13 06:46:16 PM PDT 24
Finished Aug 13 06:46:17 PM PDT 24
Peak memory 215636 kb
Host smart-71cbe3ab-dbdf-44e9-8a04-12194e615c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162191713 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.4162191713
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2396433698
Short name T704
Test name
Test status
Simulation time 19102557 ps
CPU time 0.93 seconds
Started Aug 13 06:46:18 PM PDT 24
Finished Aug 13 06:46:19 PM PDT 24
Peak memory 207268 kb
Host smart-2b4c9627-c384-4c85-a938-57678b305c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396433698 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2396433698
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_alert.2311385764
Short name T136
Test name
Test status
Simulation time 96744989 ps
CPU time 1.18 seconds
Started Aug 13 06:46:00 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 219192 kb
Host smart-8a0b1f9a-5c45-404d-9a54-5bd06e6db0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311385764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2311385764
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3711692521
Short name T922
Test name
Test status
Simulation time 37693013 ps
CPU time 0.91 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 207080 kb
Host smart-48a98025-8997-4420-a2b1-5aef9c533e79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711692521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3711692521
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3312434237
Short name T769
Test name
Test status
Simulation time 10860153 ps
CPU time 0.91 seconds
Started Aug 13 06:46:10 PM PDT 24
Finished Aug 13 06:46:11 PM PDT 24
Peak memory 215740 kb
Host smart-48d69115-3b27-42c7-afc4-2766fc845ca6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312434237 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3312434237
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.180892212
Short name T932
Test name
Test status
Simulation time 38162886 ps
CPU time 1.12 seconds
Started Aug 13 06:46:21 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 217148 kb
Host smart-464b39d0-0164-49e9-89ff-222e3cc42bad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180892212 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.180892212
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.638306178
Short name T88
Test name
Test status
Simulation time 56953130 ps
CPU time 0.87 seconds
Started Aug 13 06:46:17 PM PDT 24
Finished Aug 13 06:46:19 PM PDT 24
Peak memory 218424 kb
Host smart-c63ace8c-39aa-4802-b33a-eff092619d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638306178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.638306178
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.434817171
Short name T666
Test name
Test status
Simulation time 68985888 ps
CPU time 1.68 seconds
Started Aug 13 06:46:26 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 220000 kb
Host smart-31abc404-e8ef-4bac-8bd7-eda3a4e8b151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434817171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.434817171
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2097837034
Short name T593
Test name
Test status
Simulation time 25246717 ps
CPU time 0.97 seconds
Started Aug 13 06:46:18 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 215608 kb
Host smart-0bef0906-623a-48bb-8af3-363e4303a6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097837034 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2097837034
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3689155182
Short name T668
Test name
Test status
Simulation time 19525653 ps
CPU time 1.03 seconds
Started Aug 13 06:46:20 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 215568 kb
Host smart-4d5a7dab-d53f-4bf9-8b1e-73a5cfecb2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689155182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3689155182
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3888006036
Short name T234
Test name
Test status
Simulation time 998790907 ps
CPU time 5.49 seconds
Started Aug 13 06:46:21 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 217468 kb
Host smart-c154976c-da9f-4aea-820a-01d74374ed70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888006036 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3888006036
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3899952265
Short name T224
Test name
Test status
Simulation time 9578391315 ps
CPU time 56.53 seconds
Started Aug 13 06:46:17 PM PDT 24
Finished Aug 13 06:47:14 PM PDT 24
Peak memory 223908 kb
Host smart-93ace814-28f7-406b-b0a0-cb7f78db5214
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899952265 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3899952265
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3833358709
Short name T306
Test name
Test status
Simulation time 27287746 ps
CPU time 1.35 seconds
Started Aug 13 06:46:01 PM PDT 24
Finished Aug 13 06:46:02 PM PDT 24
Peak memory 220264 kb
Host smart-92a27b75-c77d-4330-afca-3381f2c8691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833358709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3833358709
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.315867847
Short name T231
Test name
Test status
Simulation time 176678203 ps
CPU time 0.91 seconds
Started Aug 13 06:46:20 PM PDT 24
Finished Aug 13 06:46:21 PM PDT 24
Peak memory 206904 kb
Host smart-8e0b434f-f419-41ac-ae62-3d4f5ace6272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315867847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.315867847
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3031960806
Short name T218
Test name
Test status
Simulation time 13846871 ps
CPU time 0.93 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 217016 kb
Host smart-21b2eabd-ca1e-4a1b-ab30-acf0988190ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031960806 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3031960806
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3246391098
Short name T108
Test name
Test status
Simulation time 42306736 ps
CPU time 1.09 seconds
Started Aug 13 06:46:08 PM PDT 24
Finished Aug 13 06:46:09 PM PDT 24
Peak memory 218656 kb
Host smart-5ddcc716-383c-4456-8ed2-e97a95cccf27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246391098 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3246391098
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3102545560
Short name T139
Test name
Test status
Simulation time 40126573 ps
CPU time 1.16 seconds
Started Aug 13 06:46:30 PM PDT 24
Finished Aug 13 06:46:31 PM PDT 24
Peak memory 215568 kb
Host smart-3f8a5ac7-9557-4f0c-b2e2-356e89aed0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102545560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3102545560
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.265702898
Short name T562
Test name
Test status
Simulation time 150899474 ps
CPU time 1.76 seconds
Started Aug 13 06:46:13 PM PDT 24
Finished Aug 13 06:46:15 PM PDT 24
Peak memory 219172 kb
Host smart-96dc8b50-e775-4f7a-9c04-e33ee60b868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265702898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.265702898
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2529270622
Short name T868
Test name
Test status
Simulation time 38501404 ps
CPU time 0.89 seconds
Started Aug 13 06:46:21 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 215688 kb
Host smart-b336d3cc-4b81-4ec5-b594-39b05c3ca5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529270622 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2529270622
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3437636538
Short name T596
Test name
Test status
Simulation time 25752344 ps
CPU time 0.98 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 215564 kb
Host smart-bce23e54-10e8-4929-ab85-352e8e2afa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437636538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3437636538
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2908742798
Short name T536
Test name
Test status
Simulation time 40508104 ps
CPU time 1 seconds
Started Aug 13 06:46:06 PM PDT 24
Finished Aug 13 06:46:07 PM PDT 24
Peak memory 207116 kb
Host smart-fb7723d8-2e76-4f33-9ab2-d01fc0aa4a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908742798 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2908742798
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.502734057
Short name T227
Test name
Test status
Simulation time 2980807555 ps
CPU time 68.41 seconds
Started Aug 13 06:46:19 PM PDT 24
Finished Aug 13 06:47:28 PM PDT 24
Peak memory 220384 kb
Host smart-32569a23-21cc-465f-8bb2-e0f4f6e363d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502734057 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.502734057
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2809031525
Short name T297
Test name
Test status
Simulation time 43808194 ps
CPU time 1.2 seconds
Started Aug 13 06:46:13 PM PDT 24
Finished Aug 13 06:46:14 PM PDT 24
Peak memory 219096 kb
Host smart-5c826ebb-dddf-4f29-8f5b-c0eeec537e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809031525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2809031525
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.4190820055
Short name T847
Test name
Test status
Simulation time 35597997 ps
CPU time 1.04 seconds
Started Aug 13 06:46:26 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 207092 kb
Host smart-8c7f6796-87a5-4b7f-9109-b14297279025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190820055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4190820055
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1265037833
Short name T498
Test name
Test status
Simulation time 16206194 ps
CPU time 0.88 seconds
Started Aug 13 06:46:19 PM PDT 24
Finished Aug 13 06:46:20 PM PDT 24
Peak memory 215688 kb
Host smart-0b7a5cf8-417e-4920-a069-6b8b09de07bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265037833 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1265037833
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.354083171
Short name T815
Test name
Test status
Simulation time 54899844 ps
CPU time 1.25 seconds
Started Aug 13 06:46:18 PM PDT 24
Finished Aug 13 06:46:20 PM PDT 24
Peak memory 217204 kb
Host smart-7885f0b2-95a8-408c-8794-e3500fe4c1e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354083171 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.354083171
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_genbits.3129108101
Short name T348
Test name
Test status
Simulation time 36043863 ps
CPU time 1.55 seconds
Started Aug 13 06:46:15 PM PDT 24
Finished Aug 13 06:46:17 PM PDT 24
Peak memory 218868 kb
Host smart-cc238d99-d51e-473f-b167-097f0c304493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129108101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3129108101
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.984035325
Short name T802
Test name
Test status
Simulation time 23059285 ps
CPU time 1.15 seconds
Started Aug 13 06:46:20 PM PDT 24
Finished Aug 13 06:46:21 PM PDT 24
Peak memory 215668 kb
Host smart-c73aad2f-43ff-4c0a-b2bb-cf9fa8f6b8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984035325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.984035325
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3726881239
Short name T855
Test name
Test status
Simulation time 16035791 ps
CPU time 1.04 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:23 PM PDT 24
Peak memory 215640 kb
Host smart-2c9a34fa-8c0f-4774-a44a-4a5b8d5b2ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726881239 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3726881239
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3236826971
Short name T717
Test name
Test status
Simulation time 405209493 ps
CPU time 6.34 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:29 PM PDT 24
Peak memory 215780 kb
Host smart-febf1337-0568-4d24-b59c-91735aa14783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236826971 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3236826971
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_alert.2790239849
Short name T382
Test name
Test status
Simulation time 23962115 ps
CPU time 1.14 seconds
Started Aug 13 06:46:09 PM PDT 24
Finished Aug 13 06:46:10 PM PDT 24
Peak memory 220912 kb
Host smart-d3a4dfc1-edbe-46be-b3e3-36afab030125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790239849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2790239849
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1525901007
Short name T61
Test name
Test status
Simulation time 120748307 ps
CPU time 0.88 seconds
Started Aug 13 06:46:18 PM PDT 24
Finished Aug 13 06:46:19 PM PDT 24
Peak memory 206708 kb
Host smart-ff40ee16-9c8a-41c1-a6ea-229b174e6a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525901007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1525901007
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.406693122
Short name T565
Test name
Test status
Simulation time 21049316 ps
CPU time 1.07 seconds
Started Aug 13 06:46:16 PM PDT 24
Finished Aug 13 06:46:18 PM PDT 24
Peak memory 217060 kb
Host smart-99295c10-db5d-4dc7-9ceb-694a52df5d6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406693122 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.406693122
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2247888446
Short name T540
Test name
Test status
Simulation time 22157681 ps
CPU time 0.92 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:23 PM PDT 24
Peak memory 218836 kb
Host smart-2a31d696-72e6-4006-90ba-057ad24bb766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247888446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2247888446
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.353132361
Short name T359
Test name
Test status
Simulation time 47299493 ps
CPU time 1.57 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 218672 kb
Host smart-81c33c25-174e-4279-bb4f-3a3706a9ecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353132361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.353132361
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.216068650
Short name T709
Test name
Test status
Simulation time 20467874 ps
CPU time 1.05 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 216180 kb
Host smart-f238c7f4-7e77-4947-9251-981d77d3609a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216068650 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.216068650
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2283285353
Short name T533
Test name
Test status
Simulation time 43346560 ps
CPU time 0.93 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 215604 kb
Host smart-3e5eab70-178a-4b05-8caf-32a6695f92e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283285353 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2283285353
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1310347912
Short name T926
Test name
Test status
Simulation time 331684416 ps
CPU time 2.58 seconds
Started Aug 13 06:46:06 PM PDT 24
Finished Aug 13 06:46:08 PM PDT 24
Peak memory 215608 kb
Host smart-7049c3e4-31fd-4d27-9ffe-bf6a69470415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310347912 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1310347912
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_alert.2982798443
Short name T248
Test name
Test status
Simulation time 90295635 ps
CPU time 1.15 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 218640 kb
Host smart-7ca2b934-504e-4536-882b-d0496e511b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982798443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2982798443
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2020536969
Short name T645
Test name
Test status
Simulation time 34657994 ps
CPU time 0.98 seconds
Started Aug 13 06:46:18 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 215304 kb
Host smart-c1547783-8a45-4e6e-8bb5-16e9e473e28a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020536969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2020536969
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2996030542
Short name T171
Test name
Test status
Simulation time 17741108 ps
CPU time 0.79 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 216912 kb
Host smart-18d52bba-22f6-4771-837a-37e2613b93f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996030542 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2996030542
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.860201392
Short name T688
Test name
Test status
Simulation time 33017914 ps
CPU time 1.24 seconds
Started Aug 13 06:46:11 PM PDT 24
Finished Aug 13 06:46:13 PM PDT 24
Peak memory 217236 kb
Host smart-c83a611d-68c6-40f1-a27d-5602c6ca76cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860201392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.860201392
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2247226025
Short name T953
Test name
Test status
Simulation time 49437312 ps
CPU time 0.9 seconds
Started Aug 13 06:46:20 PM PDT 24
Finished Aug 13 06:46:21 PM PDT 24
Peak memory 220304 kb
Host smart-b877c34f-6264-4608-8c2e-a7c07c634bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247226025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2247226025
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3063991196
Short name T647
Test name
Test status
Simulation time 28280943 ps
CPU time 1.11 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:23 PM PDT 24
Peak memory 217640 kb
Host smart-e8e6e4a2-b0b6-443c-ae46-624c57fece07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063991196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3063991196
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1231083863
Short name T920
Test name
Test status
Simulation time 23996253 ps
CPU time 1.08 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 215652 kb
Host smart-0ec6fd47-e9ed-4e01-a488-0348f8bca8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231083863 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1231083863
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3724523910
Short name T379
Test name
Test status
Simulation time 46385377 ps
CPU time 0.94 seconds
Started Aug 13 06:46:15 PM PDT 24
Finished Aug 13 06:46:16 PM PDT 24
Peak memory 215548 kb
Host smart-9550df52-bd14-4761-9bd6-55006e0d9b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724523910 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3724523910
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2911212744
Short name T343
Test name
Test status
Simulation time 225270655 ps
CPU time 1.8 seconds
Started Aug 13 06:46:18 PM PDT 24
Finished Aug 13 06:46:20 PM PDT 24
Peak memory 220716 kb
Host smart-4012c6f0-54e3-4e19-b0dc-5157a6af1d7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911212744 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2911212744
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_alert.3592198625
Short name T660
Test name
Test status
Simulation time 44429130 ps
CPU time 1.15 seconds
Started Aug 13 06:46:13 PM PDT 24
Finished Aug 13 06:46:15 PM PDT 24
Peak memory 219924 kb
Host smart-9379c10a-9089-4248-b89e-13aef8cf2487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592198625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3592198625
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2048454835
Short name T977
Test name
Test status
Simulation time 24117983 ps
CPU time 0.83 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:23 PM PDT 24
Peak memory 206876 kb
Host smart-fa2a9b63-347f-4b52-8fd7-151ac03e4965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048454835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2048454835
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2755465113
Short name T730
Test name
Test status
Simulation time 15809347 ps
CPU time 0.83 seconds
Started Aug 13 06:46:06 PM PDT 24
Finished Aug 13 06:46:07 PM PDT 24
Peak memory 216904 kb
Host smart-928a788d-74da-401f-8f92-088bd8ba6d8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755465113 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2755465113
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3251507119
Short name T702
Test name
Test status
Simulation time 27000398 ps
CPU time 0.88 seconds
Started Aug 13 06:46:11 PM PDT 24
Finished Aug 13 06:46:12 PM PDT 24
Peak memory 218780 kb
Host smart-5782e17c-4c1a-4479-a672-b8fb7ddb4a1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251507119 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3251507119
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3677855976
Short name T426
Test name
Test status
Simulation time 20903168 ps
CPU time 0.92 seconds
Started Aug 13 06:46:20 PM PDT 24
Finished Aug 13 06:46:21 PM PDT 24
Peak memory 218596 kb
Host smart-2f230936-3b57-4bde-b139-8c88b8da3493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677855976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3677855976
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1188581786
Short name T787
Test name
Test status
Simulation time 248256070 ps
CPU time 1.61 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 220468 kb
Host smart-cf9711f8-3c54-4020-af82-4f3b1fb9143e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188581786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1188581786
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2135363487
Short name T786
Test name
Test status
Simulation time 24527239 ps
CPU time 1.12 seconds
Started Aug 13 06:46:15 PM PDT 24
Finished Aug 13 06:46:16 PM PDT 24
Peak memory 224420 kb
Host smart-fa451892-b2d9-43d5-a422-c68d96807d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135363487 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2135363487
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2102743796
Short name T544
Test name
Test status
Simulation time 17891936 ps
CPU time 1.07 seconds
Started Aug 13 06:46:21 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 215556 kb
Host smart-6f03b017-f275-41fa-8aeb-ce282f38b8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102743796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2102743796
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1583765550
Short name T705
Test name
Test status
Simulation time 303670525 ps
CPU time 1.96 seconds
Started Aug 13 06:46:14 PM PDT 24
Finished Aug 13 06:46:17 PM PDT 24
Peak memory 215544 kb
Host smart-f7e4bd57-3a20-4809-90bf-a482b5e6f543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583765550 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1583765550
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4151765296
Short name T422
Test name
Test status
Simulation time 20837442156 ps
CPU time 142.32 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:48:47 PM PDT 24
Peak memory 223616 kb
Host smart-787decb4-9fe2-4084-ab58-bca258f679f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151765296 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.4151765296
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2913523780
Short name T711
Test name
Test status
Simulation time 26223641 ps
CPU time 1.15 seconds
Started Aug 13 06:46:07 PM PDT 24
Finished Aug 13 06:46:08 PM PDT 24
Peak memory 220088 kb
Host smart-14fae412-271a-4e1d-99bf-0ac3a24dd112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913523780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2913523780
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.225074139
Short name T62
Test name
Test status
Simulation time 38413085 ps
CPU time 0.87 seconds
Started Aug 13 06:46:39 PM PDT 24
Finished Aug 13 06:46:40 PM PDT 24
Peak memory 207120 kb
Host smart-5ceda915-3a10-4628-884e-214038a27922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225074139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.225074139
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2255018794
Short name T185
Test name
Test status
Simulation time 13463900 ps
CPU time 0.96 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 217028 kb
Host smart-6c057aae-0949-4954-b2cb-b26c0d685a67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255018794 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2255018794
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3082966261
Short name T282
Test name
Test status
Simulation time 24738951 ps
CPU time 1.02 seconds
Started Aug 13 06:46:17 PM PDT 24
Finished Aug 13 06:46:18 PM PDT 24
Peak memory 218908 kb
Host smart-7bc31169-4d6d-4cae-a5d0-6dfd008894e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082966261 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3082966261
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2043426367
Short name T768
Test name
Test status
Simulation time 46954838 ps
CPU time 0.98 seconds
Started Aug 13 06:46:09 PM PDT 24
Finished Aug 13 06:46:11 PM PDT 24
Peak memory 219836 kb
Host smart-e232d08f-b6d1-4299-be79-ff607e8342d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043426367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2043426367
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3332831394
Short name T908
Test name
Test status
Simulation time 38103398 ps
CPU time 1.62 seconds
Started Aug 13 06:46:05 PM PDT 24
Finished Aug 13 06:46:07 PM PDT 24
Peak memory 218608 kb
Host smart-698c00b2-b23f-4b06-a5a7-7ba77b8e32fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332831394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3332831394
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2979583620
Short name T54
Test name
Test status
Simulation time 21325874 ps
CPU time 1.06 seconds
Started Aug 13 06:46:26 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 215764 kb
Host smart-989adee8-a173-43cb-affc-8e27722d7e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979583620 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2979583620
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2805734027
Short name T339
Test name
Test status
Simulation time 17041834 ps
CPU time 1.01 seconds
Started Aug 13 06:46:12 PM PDT 24
Finished Aug 13 06:46:14 PM PDT 24
Peak memory 215644 kb
Host smart-bf23fdab-8ae1-43f4-83e9-cfb42f1a6a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805734027 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2805734027
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1768570873
Short name T446
Test name
Test status
Simulation time 226084386 ps
CPU time 1.93 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 217520 kb
Host smart-8f849735-e8da-4e31-b01f-3cbb81caf401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768570873 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1768570873
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1530574429
Short name T419
Test name
Test status
Simulation time 60670762708 ps
CPU time 92.86 seconds
Started Aug 13 06:46:27 PM PDT 24
Finished Aug 13 06:48:00 PM PDT 24
Peak memory 216796 kb
Host smart-c3a2838f-31cd-47f5-bf16-cb8090f90047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530574429 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1530574429
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.75110502
Short name T860
Test name
Test status
Simulation time 91345804 ps
CPU time 1.13 seconds
Started Aug 13 06:46:20 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 219848 kb
Host smart-afcbda50-9d32-45a6-b1da-6ed991a0b499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75110502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.75110502
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3417198993
Short name T618
Test name
Test status
Simulation time 18354929 ps
CPU time 0.97 seconds
Started Aug 13 06:46:16 PM PDT 24
Finished Aug 13 06:46:17 PM PDT 24
Peak memory 215460 kb
Host smart-3f4a051c-d079-48ea-aa0b-d3e0a4ce0cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417198993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3417198993
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2558309033
Short name T428
Test name
Test status
Simulation time 22513675 ps
CPU time 0.91 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:25 PM PDT 24
Peak memory 216964 kb
Host smart-df1cc6a8-a8c6-44de-8848-819d815a5061
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558309033 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2558309033
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1948030723
Short name T797
Test name
Test status
Simulation time 35709913 ps
CPU time 1.27 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 217372 kb
Host smart-13c540fe-b221-4fef-82f8-0f184c4b34d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948030723 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1948030723
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3775238532
Short name T87
Test name
Test status
Simulation time 23619281 ps
CPU time 0.95 seconds
Started Aug 13 06:46:15 PM PDT 24
Finished Aug 13 06:46:17 PM PDT 24
Peak memory 218752 kb
Host smart-0579efdb-8712-428c-8739-c078e519f745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775238532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3775238532
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3368650870
Short name T681
Test name
Test status
Simulation time 88662869 ps
CPU time 1.44 seconds
Started Aug 13 06:46:37 PM PDT 24
Finished Aug 13 06:46:38 PM PDT 24
Peak memory 219296 kb
Host smart-392a7bbc-4edb-4b2a-90f4-d77bc452ba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368650870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3368650870
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.994932421
Short name T525
Test name
Test status
Simulation time 30137196 ps
CPU time 0.88 seconds
Started Aug 13 06:46:16 PM PDT 24
Finished Aug 13 06:46:17 PM PDT 24
Peak memory 215580 kb
Host smart-020eaf61-862d-43b9-90bb-881b6f9b818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994932421 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.994932421
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.189675497
Short name T488
Test name
Test status
Simulation time 14939991 ps
CPU time 0.97 seconds
Started Aug 13 06:46:33 PM PDT 24
Finished Aug 13 06:46:34 PM PDT 24
Peak memory 215708 kb
Host smart-8f3e31a7-fe03-4310-96c9-3ddfaaa5868e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189675497 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.189675497
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2933211717
Short name T476
Test name
Test status
Simulation time 89679955 ps
CPU time 1.45 seconds
Started Aug 13 06:46:16 PM PDT 24
Finished Aug 13 06:46:18 PM PDT 24
Peak memory 215608 kb
Host smart-db700cd7-b2c1-4528-a8b7-632d52d24c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933211717 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2933211717
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_alert.1841621565
Short name T946
Test name
Test status
Simulation time 54370867 ps
CPU time 1.09 seconds
Started Aug 13 06:46:40 PM PDT 24
Finished Aug 13 06:46:41 PM PDT 24
Peak memory 219288 kb
Host smart-68f3d567-b85b-47b5-b2b6-a21c50ef0042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841621565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1841621565
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3844675157
Short name T834
Test name
Test status
Simulation time 20412455 ps
CPU time 1.09 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:25 PM PDT 24
Peak memory 215316 kb
Host smart-4cc1696d-5157-4b86-ac57-0df308033990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844675157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3844675157
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2863056394
Short name T655
Test name
Test status
Simulation time 13306856 ps
CPU time 0.91 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:25 PM PDT 24
Peak memory 215880 kb
Host smart-ef31aa1a-3733-4fda-88b0-4e181a6092ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863056394 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2863056394
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1346722175
Short name T129
Test name
Test status
Simulation time 316363168 ps
CPU time 1.19 seconds
Started Aug 13 06:46:27 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 217280 kb
Host smart-3e4fdafb-67fe-4363-be8c-86a8b34babcb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346722175 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1346722175
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2099856846
Short name T947
Test name
Test status
Simulation time 21582210 ps
CPU time 1.05 seconds
Started Aug 13 06:46:37 PM PDT 24
Finished Aug 13 06:46:38 PM PDT 24
Peak memory 224212 kb
Host smart-321b1f4f-0e97-405e-9280-3233b2c1baee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099856846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2099856846
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1662476762
Short name T599
Test name
Test status
Simulation time 66360407 ps
CPU time 1.35 seconds
Started Aug 13 06:46:40 PM PDT 24
Finished Aug 13 06:46:41 PM PDT 24
Peak memory 219040 kb
Host smart-ff83ee29-1d35-4e15-b776-c4377e8a1835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662476762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1662476762
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1084248177
Short name T875
Test name
Test status
Simulation time 22947831 ps
CPU time 1.17 seconds
Started Aug 13 06:46:42 PM PDT 24
Finished Aug 13 06:46:43 PM PDT 24
Peak memory 224272 kb
Host smart-c9092aac-ab1b-4550-967c-8fb1b6a4880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084248177 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1084248177
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.163893772
Short name T880
Test name
Test status
Simulation time 57956205 ps
CPU time 0.91 seconds
Started Aug 13 06:46:32 PM PDT 24
Finished Aug 13 06:46:33 PM PDT 24
Peak memory 215620 kb
Host smart-f202d82d-b6db-477a-9686-e5a93038c9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163893772 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.163893772
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2155273113
Short name T597
Test name
Test status
Simulation time 335718411 ps
CPU time 1.92 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 215664 kb
Host smart-9c26892d-041d-444c-a1bc-5e2ea28b95dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155273113 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2155273113
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_alert.2115595311
Short name T130
Test name
Test status
Simulation time 27558918 ps
CPU time 1.26 seconds
Started Aug 13 06:45:29 PM PDT 24
Finished Aug 13 06:45:30 PM PDT 24
Peak memory 218796 kb
Host smart-6b206495-fefa-4f59-b419-dbc27b8445ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115595311 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2115595311
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.690637351
Short name T744
Test name
Test status
Simulation time 19618955 ps
CPU time 1 seconds
Started Aug 13 06:45:24 PM PDT 24
Finished Aug 13 06:45:25 PM PDT 24
Peak memory 215260 kb
Host smart-1ad3cc91-1d4a-4876-968e-dc6c3d921d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690637351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.690637351
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1020917499
Short name T678
Test name
Test status
Simulation time 18286282 ps
CPU time 0.84 seconds
Started Aug 13 06:45:12 PM PDT 24
Finished Aug 13 06:45:13 PM PDT 24
Peak memory 216504 kb
Host smart-ba6025b8-29bc-4ee9-b889-ae0ded4bb307
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020917499 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1020917499
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.4084269953
Short name T706
Test name
Test status
Simulation time 45585163 ps
CPU time 1.28 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:38 PM PDT 24
Peak memory 220208 kb
Host smart-9bc99ecf-4dd0-438e-83a9-e0a7252c923c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084269953 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.4084269953
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.4031654061
Short name T669
Test name
Test status
Simulation time 23861464 ps
CPU time 0.94 seconds
Started Aug 13 06:45:24 PM PDT 24
Finished Aug 13 06:45:25 PM PDT 24
Peak memory 218616 kb
Host smart-310b1abd-cf4c-40b0-b33b-e4c6addf04a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031654061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.4031654061
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1761958642
Short name T724
Test name
Test status
Simulation time 87275005 ps
CPU time 1.56 seconds
Started Aug 13 06:45:19 PM PDT 24
Finished Aug 13 06:45:21 PM PDT 24
Peak memory 219120 kb
Host smart-20077b60-16d8-4120-9e7b-c8ed5db09439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761958642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1761958642
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.24875650
Short name T770
Test name
Test status
Simulation time 22090611 ps
CPU time 1.14 seconds
Started Aug 13 06:45:14 PM PDT 24
Finished Aug 13 06:45:15 PM PDT 24
Peak memory 215784 kb
Host smart-320f3f3a-09c7-4568-8e5f-5c3360ceafa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24875650 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.24875650
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1455751897
Short name T761
Test name
Test status
Simulation time 18644759 ps
CPU time 1 seconds
Started Aug 13 06:45:21 PM PDT 24
Finished Aug 13 06:45:22 PM PDT 24
Peak memory 207392 kb
Host smart-d094d94c-96b9-493e-8b70-2156ed7ab461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455751897 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1455751897
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1246680913
Short name T461
Test name
Test status
Simulation time 39081595 ps
CPU time 0.92 seconds
Started Aug 13 06:45:24 PM PDT 24
Finished Aug 13 06:45:25 PM PDT 24
Peak memory 215524 kb
Host smart-533966e1-2c9b-43ba-ae57-b13bccfa3ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246680913 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1246680913
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2426724909
Short name T241
Test name
Test status
Simulation time 369352088 ps
CPU time 2.66 seconds
Started Aug 13 06:45:21 PM PDT 24
Finished Aug 13 06:45:23 PM PDT 24
Peak memory 217384 kb
Host smart-719d1470-1476-4499-8d26-952e3ea5c44d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426724909 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2426724909
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/50.edn_alert.3589371865
Short name T762
Test name
Test status
Simulation time 42566920 ps
CPU time 1.06 seconds
Started Aug 13 06:46:20 PM PDT 24
Finished Aug 13 06:46:21 PM PDT 24
Peak memory 218860 kb
Host smart-a6a2dd22-154a-47ad-8c88-a59861f11d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589371865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.3589371865
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1453428862
Short name T68
Test name
Test status
Simulation time 29016670 ps
CPU time 0.97 seconds
Started Aug 13 06:46:19 PM PDT 24
Finished Aug 13 06:46:20 PM PDT 24
Peak memory 223988 kb
Host smart-da3de77a-de23-423b-9aff-6737b46aa504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453428862 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1453428862
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1258563152
Short name T595
Test name
Test status
Simulation time 72920496 ps
CPU time 1.24 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:23 PM PDT 24
Peak memory 219320 kb
Host smart-fb7a8ec9-10dd-41a4-8323-20fee5a256ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258563152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1258563152
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.295117423
Short name T623
Test name
Test status
Simulation time 35343373 ps
CPU time 1.23 seconds
Started Aug 13 06:46:44 PM PDT 24
Finished Aug 13 06:46:45 PM PDT 24
Peak memory 220168 kb
Host smart-2d36f47a-d820-4374-851a-a2d090ceb468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295117423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.295117423
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.3451905194
Short name T604
Test name
Test status
Simulation time 23478531 ps
CPU time 0.96 seconds
Started Aug 13 06:46:30 PM PDT 24
Finished Aug 13 06:46:31 PM PDT 24
Peak memory 218716 kb
Host smart-9fc41055-d9a7-4f1e-89ba-d851f8619961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451905194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3451905194
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2940292960
Short name T574
Test name
Test status
Simulation time 65836719 ps
CPU time 1.1 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 219224 kb
Host smart-55091e3a-ca54-48df-bd1b-d0345c9727dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940292960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2940292960
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1663519042
Short name T716
Test name
Test status
Simulation time 36564720 ps
CPU time 1.37 seconds
Started Aug 13 06:46:33 PM PDT 24
Finished Aug 13 06:46:35 PM PDT 24
Peak memory 221220 kb
Host smart-71611ac9-7fd5-45d4-8a7a-8df8136e32a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663519042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1663519042
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3951738527
Short name T882
Test name
Test status
Simulation time 88751157 ps
CPU time 1.06 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 219728 kb
Host smart-3106e560-542c-43f5-af85-3764f2730703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951738527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3951738527
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.857642586
Short name T243
Test name
Test status
Simulation time 35228963 ps
CPU time 1.14 seconds
Started Aug 13 06:46:27 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 219076 kb
Host smart-321bf9df-2981-43c9-a25d-902a907f2de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857642586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.857642586
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2632734256
Short name T188
Test name
Test status
Simulation time 140165602 ps
CPU time 1.19 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 219780 kb
Host smart-8e897170-8641-4969-a3fd-423587ecdab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632734256 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2632734256
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2637951034
Short name T146
Test name
Test status
Simulation time 54391487 ps
CPU time 1.1 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 224256 kb
Host smart-fa2edc7d-54ad-447f-8301-e14fb0ea521b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637951034 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2637951034
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2146500183
Short name T853
Test name
Test status
Simulation time 68526231 ps
CPU time 1.36 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 220052 kb
Host smart-c36dc69b-a014-4be4-9f41-607f379bdd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146500183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2146500183
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3349932288
Short name T954
Test name
Test status
Simulation time 88681990 ps
CPU time 1.23 seconds
Started Aug 13 06:46:21 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 218700 kb
Host smart-4fa4d8ff-d6ce-4700-bc0a-3b008917adc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349932288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3349932288
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.709795112
Short name T910
Test name
Test status
Simulation time 20805641 ps
CPU time 1.09 seconds
Started Aug 13 06:46:19 PM PDT 24
Finished Aug 13 06:46:20 PM PDT 24
Peak memory 219728 kb
Host smart-fda32a0c-5cc1-4b65-8f6c-004292e9507a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709795112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.709795112
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1273559107
Short name T470
Test name
Test status
Simulation time 49029037 ps
CPU time 1.5 seconds
Started Aug 13 06:46:20 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 218660 kb
Host smart-29bc21fd-3399-49d3-92d5-dfdbe5a0956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273559107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1273559107
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.160314076
Short name T789
Test name
Test status
Simulation time 26433611 ps
CPU time 1.15 seconds
Started Aug 13 06:46:28 PM PDT 24
Finished Aug 13 06:46:30 PM PDT 24
Peak memory 220968 kb
Host smart-0f761276-2dde-498b-a52b-7c7d042cef1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160314076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.160314076
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.363591946
Short name T145
Test name
Test status
Simulation time 58105116 ps
CPU time 1.41 seconds
Started Aug 13 06:46:42 PM PDT 24
Finished Aug 13 06:46:43 PM PDT 24
Peak memory 225904 kb
Host smart-be03c100-a6ee-44e4-8321-eb0138b1031c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363591946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.363591946
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.985965231
Short name T245
Test name
Test status
Simulation time 82610054 ps
CPU time 1.27 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 218816 kb
Host smart-c64309f1-cf82-4432-95b3-7c1febbf0e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985965231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.985965231
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.4202077891
Short name T387
Test name
Test status
Simulation time 23637549 ps
CPU time 1.15 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 219060 kb
Host smart-561f81cb-d752-4934-9d30-30a3da1f3105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202077891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.4202077891
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.83274151
Short name T149
Test name
Test status
Simulation time 33684094 ps
CPU time 1.12 seconds
Started Aug 13 06:46:27 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 229936 kb
Host smart-d11faa55-3a84-4bbd-9c98-a630bd845542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83274151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.83274151
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3531684261
Short name T52
Test name
Test status
Simulation time 54671300 ps
CPU time 1.43 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 218836 kb
Host smart-52333a00-fcc2-4acf-b808-c988e7ac0d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531684261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3531684261
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.978612573
Short name T740
Test name
Test status
Simulation time 23500539 ps
CPU time 1.18 seconds
Started Aug 13 06:46:43 PM PDT 24
Finished Aug 13 06:46:45 PM PDT 24
Peak memory 218916 kb
Host smart-94cf9daf-2985-4576-8322-51f165a682b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978612573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.978612573
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1072389739
Short name T192
Test name
Test status
Simulation time 33368706 ps
CPU time 0.97 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 229620 kb
Host smart-29797cf3-1d31-40fc-9754-f6e062d80d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072389739 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1072389739
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.113503783
Short name T867
Test name
Test status
Simulation time 95714975 ps
CPU time 1.44 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 219376 kb
Host smart-0b4be9eb-5ea4-4093-b196-4a5b2fb06ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113503783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.113503783
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.2306710589
Short name T692
Test name
Test status
Simulation time 61907363 ps
CPU time 1.29 seconds
Started Aug 13 06:46:33 PM PDT 24
Finished Aug 13 06:46:34 PM PDT 24
Peak memory 218916 kb
Host smart-57193b3d-158c-4c30-8fc6-8644048453f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306710589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.2306710589
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3926726816
Short name T78
Test name
Test status
Simulation time 33191003 ps
CPU time 1.1 seconds
Started Aug 13 06:46:42 PM PDT 24
Finished Aug 13 06:46:43 PM PDT 24
Peak memory 218868 kb
Host smart-3cb4133f-d733-4c47-b8ba-df848b02997e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926726816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3926726816
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2391939029
Short name T388
Test name
Test status
Simulation time 103447216 ps
CPU time 1.44 seconds
Started Aug 13 06:46:37 PM PDT 24
Finished Aug 13 06:46:38 PM PDT 24
Peak memory 219408 kb
Host smart-0be91d66-0904-4e2a-89f7-bf403b703d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391939029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2391939029
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3020706577
Short name T441
Test name
Test status
Simulation time 44772401 ps
CPU time 1.12 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 219908 kb
Host smart-0b67d218-1624-4fc0-b2f8-b31fe4febcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020706577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3020706577
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_genbits.2523067851
Short name T84
Test name
Test status
Simulation time 69654688 ps
CPU time 1.15 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 217708 kb
Host smart-deb9933e-cf93-4df6-a45d-1e945ebe6a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523067851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2523067851
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1965976000
Short name T104
Test name
Test status
Simulation time 133003503 ps
CPU time 1.21 seconds
Started Aug 13 06:45:15 PM PDT 24
Finished Aug 13 06:45:17 PM PDT 24
Peak memory 220020 kb
Host smart-19ad02db-0550-4595-959c-8116f26e7bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965976000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1965976000
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2324417613
Short name T580
Test name
Test status
Simulation time 11996250 ps
CPU time 0.86 seconds
Started Aug 13 06:45:23 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 207272 kb
Host smart-41c052a3-a34e-4e1c-aa14-e602b3f9873a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324417613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2324417613
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.946296061
Short name T913
Test name
Test status
Simulation time 106929389 ps
CPU time 0.89 seconds
Started Aug 13 06:45:20 PM PDT 24
Finished Aug 13 06:45:21 PM PDT 24
Peak memory 216824 kb
Host smart-ea7aacf6-3a75-436f-b349-74e3ab41716f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946296061 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.946296061
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.618869928
Short name T805
Test name
Test status
Simulation time 178784297 ps
CPU time 1.13 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 217304 kb
Host smart-ecf048fb-baf0-427d-ab2a-712a6dbeec89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618869928 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.618869928
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3547697317
Short name T193
Test name
Test status
Simulation time 65854400 ps
CPU time 0.83 seconds
Started Aug 13 06:45:22 PM PDT 24
Finished Aug 13 06:45:22 PM PDT 24
Peak memory 219384 kb
Host smart-173367e2-4e52-49c2-b600-deae083090fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547697317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3547697317
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2339673361
Short name T750
Test name
Test status
Simulation time 35488962 ps
CPU time 1.31 seconds
Started Aug 13 06:45:31 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 217580 kb
Host smart-938fb46a-b4f6-4395-a706-31d4db40a484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339673361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2339673361
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_regwen.2332762028
Short name T816
Test name
Test status
Simulation time 26956804 ps
CPU time 0.99 seconds
Started Aug 13 06:45:19 PM PDT 24
Finished Aug 13 06:45:20 PM PDT 24
Peak memory 207376 kb
Host smart-fb7b2e4c-4566-4336-8e2a-b5d456f454d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332762028 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2332762028
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.746140559
Short name T377
Test name
Test status
Simulation time 28927026 ps
CPU time 0.99 seconds
Started Aug 13 06:45:14 PM PDT 24
Finished Aug 13 06:45:15 PM PDT 24
Peak memory 215600 kb
Host smart-203710fc-52df-4656-86e9-8e46a0d3b923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746140559 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.746140559
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.344317957
Short name T401
Test name
Test status
Simulation time 521284783 ps
CPU time 3.82 seconds
Started Aug 13 06:45:16 PM PDT 24
Finished Aug 13 06:45:20 PM PDT 24
Peak memory 218996 kb
Host smart-648c6638-b8cc-4e59-b4e8-ee23c96bb969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344317957 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.344317957
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2985096956
Short name T226
Test name
Test status
Simulation time 10215707482 ps
CPU time 34.94 seconds
Started Aug 13 06:45:16 PM PDT 24
Finished Aug 13 06:45:51 PM PDT 24
Peak memory 219380 kb
Host smart-00f9b16c-8636-4d99-936c-1cfcdffaf1b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985096956 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2985096956
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1586759756
Short name T9
Test name
Test status
Simulation time 30457212 ps
CPU time 1.27 seconds
Started Aug 13 06:46:19 PM PDT 24
Finished Aug 13 06:46:21 PM PDT 24
Peak memory 218860 kb
Host smart-754e3d2e-cef4-46d3-89f0-b8fbe9341519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586759756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1586759756
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3791723839
Short name T871
Test name
Test status
Simulation time 21999212 ps
CPU time 0.97 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:25 PM PDT 24
Peak memory 218872 kb
Host smart-f64b67ae-87b1-4326-8d8e-ade9fffc927e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791723839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3791723839
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2088453771
Short name T412
Test name
Test status
Simulation time 67077768 ps
CPU time 1.72 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 219024 kb
Host smart-d0947a8d-f517-4d2b-a343-8d5890135125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088453771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2088453771
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.2827546429
Short name T141
Test name
Test status
Simulation time 25403643 ps
CPU time 1.25 seconds
Started Aug 13 06:46:27 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 218996 kb
Host smart-86b8a307-9f00-4382-872f-7df392899dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827546429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.2827546429
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.74275601
Short name T66
Test name
Test status
Simulation time 140220777 ps
CPU time 1.17 seconds
Started Aug 13 06:46:43 PM PDT 24
Finished Aug 13 06:46:44 PM PDT 24
Peak memory 229948 kb
Host smart-e5afc985-149c-4a6b-842e-851afb18192e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74275601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.74275601
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3728539877
Short name T484
Test name
Test status
Simulation time 47433530 ps
CPU time 1.54 seconds
Started Aug 13 06:46:56 PM PDT 24
Finished Aug 13 06:46:57 PM PDT 24
Peak memory 218680 kb
Host smart-d57cbb76-430f-4b43-a0ba-bcabdb7d0164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728539877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3728539877
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1902176713
Short name T60
Test name
Test status
Simulation time 317809706 ps
CPU time 1.13 seconds
Started Aug 13 06:46:20 PM PDT 24
Finished Aug 13 06:46:21 PM PDT 24
Peak memory 218948 kb
Host smart-35998ced-d169-498f-b730-cf355d13b7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902176713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1902176713
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2295664828
Short name T162
Test name
Test status
Simulation time 19861200 ps
CPU time 1.05 seconds
Started Aug 13 06:46:21 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 218704 kb
Host smart-3b7c9b78-e9dd-40b4-86d3-b0dc08c20e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295664828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2295664828
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1949974345
Short name T845
Test name
Test status
Simulation time 81372389 ps
CPU time 1.77 seconds
Started Aug 13 06:46:30 PM PDT 24
Finished Aug 13 06:46:32 PM PDT 24
Peak memory 219040 kb
Host smart-4e432e0f-f182-42ae-9fec-65b9cb2eabce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949974345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1949974345
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.3369508726
Short name T24
Test name
Test status
Simulation time 280427001 ps
CPU time 1.45 seconds
Started Aug 13 06:46:42 PM PDT 24
Finished Aug 13 06:46:43 PM PDT 24
Peak memory 219364 kb
Host smart-cd618ce8-ba03-43b2-9053-37ca5a4cdeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369508726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3369508726
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1250995888
Short name T63
Test name
Test status
Simulation time 31503867 ps
CPU time 0.94 seconds
Started Aug 13 06:46:36 PM PDT 24
Finished Aug 13 06:46:37 PM PDT 24
Peak memory 224016 kb
Host smart-ec2ef363-c28f-4a5d-ba0c-783c1b3ab535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250995888 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1250995888
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3489688496
Short name T844
Test name
Test status
Simulation time 34480174 ps
CPU time 1.36 seconds
Started Aug 13 06:46:38 PM PDT 24
Finished Aug 13 06:46:40 PM PDT 24
Peak memory 218988 kb
Host smart-d6513fff-2b4f-4709-a079-c8ab723e930d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489688496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3489688496
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.3341483330
Short name T472
Test name
Test status
Simulation time 49919206 ps
CPU time 1.18 seconds
Started Aug 13 06:46:34 PM PDT 24
Finished Aug 13 06:46:40 PM PDT 24
Peak memory 221408 kb
Host smart-5b13a367-4c9d-4575-a646-e9bbbb65e2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341483330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.3341483330
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3756264319
Short name T64
Test name
Test status
Simulation time 28285662 ps
CPU time 1.08 seconds
Started Aug 13 06:46:30 PM PDT 24
Finished Aug 13 06:46:31 PM PDT 24
Peak memory 229888 kb
Host smart-127c653e-62e2-4484-ae72-54657b8c819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756264319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3756264319
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3006561616
Short name T509
Test name
Test status
Simulation time 61305336 ps
CPU time 1.23 seconds
Started Aug 13 06:46:38 PM PDT 24
Finished Aug 13 06:46:39 PM PDT 24
Peak memory 217684 kb
Host smart-e90252ea-5281-4566-bbf1-89ff228e29cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006561616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3006561616
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2997953053
Short name T211
Test name
Test status
Simulation time 28798824 ps
CPU time 0.9 seconds
Started Aug 13 06:46:41 PM PDT 24
Finished Aug 13 06:46:42 PM PDT 24
Peak memory 219516 kb
Host smart-a64b46d3-1685-4d6a-959e-225f721513bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997953053 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2997953053
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1489922044
Short name T445
Test name
Test status
Simulation time 273454322 ps
CPU time 3.35 seconds
Started Aug 13 06:46:41 PM PDT 24
Finished Aug 13 06:46:45 PM PDT 24
Peak memory 218992 kb
Host smart-e058c250-23b8-4ed9-a8e8-14fd01a329b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489922044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1489922044
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.11398236
Short name T518
Test name
Test status
Simulation time 34533959 ps
CPU time 1.1 seconds
Started Aug 13 06:46:41 PM PDT 24
Finished Aug 13 06:46:42 PM PDT 24
Peak memory 216004 kb
Host smart-c7495611-4220-45b1-a222-3dfd66f948dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11398236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.11398236
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2231227398
Short name T919
Test name
Test status
Simulation time 19024651 ps
CPU time 1.06 seconds
Started Aug 13 06:46:27 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 218840 kb
Host smart-2d426f44-39bf-4c18-95c2-113c8c2e0ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231227398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2231227398
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3171578350
Short name T425
Test name
Test status
Simulation time 40422214 ps
CPU time 1.36 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 217600 kb
Host smart-e0c7d777-0816-46cc-89f3-996c2fe2a830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171578350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3171578350
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.901719771
Short name T909
Test name
Test status
Simulation time 31101177 ps
CPU time 1.31 seconds
Started Aug 13 06:46:23 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 221476 kb
Host smart-b63f22b1-8b43-4b3b-817f-95543c040b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901719771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.901719771
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3253633696
Short name T854
Test name
Test status
Simulation time 21681419 ps
CPU time 1.01 seconds
Started Aug 13 06:46:43 PM PDT 24
Finished Aug 13 06:46:44 PM PDT 24
Peak memory 224196 kb
Host smart-5022f5fb-3c04-4726-a039-de84a8afebae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253633696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3253633696
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1671500579
Short name T907
Test name
Test status
Simulation time 102704635 ps
CPU time 1.19 seconds
Started Aug 13 06:46:21 PM PDT 24
Finished Aug 13 06:46:22 PM PDT 24
Peak memory 217720 kb
Host smart-803d6b20-7604-4e5d-9c2d-81b4341f1de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671500579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1671500579
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.598848441
Short name T894
Test name
Test status
Simulation time 57866871 ps
CPU time 1.04 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:23 PM PDT 24
Peak memory 220144 kb
Host smart-13143f78-1a38-44ab-bbdf-4adbb4b5805f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598848441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.598848441
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.2963409285
Short name T825
Test name
Test status
Simulation time 19392535 ps
CPU time 1.09 seconds
Started Aug 13 06:46:51 PM PDT 24
Finished Aug 13 06:46:52 PM PDT 24
Peak memory 218884 kb
Host smart-b26c5c59-0f80-4d8f-92b6-0a382e1ff231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963409285 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2963409285
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2223723197
Short name T307
Test name
Test status
Simulation time 69528676 ps
CPU time 1.34 seconds
Started Aug 13 06:46:32 PM PDT 24
Finished Aug 13 06:46:33 PM PDT 24
Peak memory 218676 kb
Host smart-4be9235b-a9f4-4c20-92bb-3ef995fd9166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223723197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2223723197
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3972418925
Short name T144
Test name
Test status
Simulation time 28690833 ps
CPU time 1.24 seconds
Started Aug 13 06:46:26 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 220932 kb
Host smart-88f0d85b-35f3-469a-86af-1b9b89481b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972418925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3972418925
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2802431306
Short name T235
Test name
Test status
Simulation time 23838164 ps
CPU time 0.94 seconds
Started Aug 13 06:46:50 PM PDT 24
Finished Aug 13 06:46:51 PM PDT 24
Peak memory 218784 kb
Host smart-8d113870-c7e0-4dbb-af1d-2259479c43ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802431306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2802431306
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4179720184
Short name T508
Test name
Test status
Simulation time 77466608 ps
CPU time 1.41 seconds
Started Aug 13 06:46:46 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 219032 kb
Host smart-fb6079d2-1e8f-4a7f-b97f-6f49e2aeb1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179720184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4179720184
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1113098517
Short name T812
Test name
Test status
Simulation time 85538831 ps
CPU time 1.16 seconds
Started Aug 13 06:45:31 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 220308 kb
Host smart-6d201b43-9885-44c1-be69-331729224189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113098517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1113098517
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1467774782
Short name T541
Test name
Test status
Simulation time 19234686 ps
CPU time 0.85 seconds
Started Aug 13 06:45:28 PM PDT 24
Finished Aug 13 06:45:29 PM PDT 24
Peak memory 207024 kb
Host smart-1109b880-ff37-43ca-adf0-1c12231339be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467774782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1467774782
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.4246882767
Short name T203
Test name
Test status
Simulation time 20944828 ps
CPU time 0.9 seconds
Started Aug 13 06:45:24 PM PDT 24
Finished Aug 13 06:45:25 PM PDT 24
Peak memory 216972 kb
Host smart-e0f2013e-2cfc-44b6-876d-ee308bfe847a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246882767 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4246882767
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1493703908
Short name T150
Test name
Test status
Simulation time 297939517 ps
CPU time 0.99 seconds
Started Aug 13 06:45:27 PM PDT 24
Finished Aug 13 06:45:29 PM PDT 24
Peak memory 220224 kb
Host smart-6152b46a-0d46-461e-8aa5-bb22bdb52e43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493703908 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1493703908
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2390047093
Short name T8
Test name
Test status
Simulation time 34248094 ps
CPU time 1.03 seconds
Started Aug 13 06:45:20 PM PDT 24
Finished Aug 13 06:45:21 PM PDT 24
Peak memory 229892 kb
Host smart-8a50460a-dfe1-4219-aeea-c3c24a6166ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390047093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2390047093
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2958299071
Short name T514
Test name
Test status
Simulation time 280688301 ps
CPU time 3.99 seconds
Started Aug 13 06:45:22 PM PDT 24
Finished Aug 13 06:45:26 PM PDT 24
Peak memory 220328 kb
Host smart-25a77f38-f68b-4df0-aa6f-199f03ed968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958299071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2958299071
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1784932019
Short name T195
Test name
Test status
Simulation time 28165450 ps
CPU time 0.99 seconds
Started Aug 13 06:45:23 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 215660 kb
Host smart-fc11b3cd-2d30-4a2f-94bc-39125664b445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784932019 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1784932019
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2381659035
Short name T610
Test name
Test status
Simulation time 18597685 ps
CPU time 1.02 seconds
Started Aug 13 06:45:07 PM PDT 24
Finished Aug 13 06:45:08 PM PDT 24
Peak memory 207356 kb
Host smart-bb1bbecf-b25d-4e1c-a4e6-a44f01d17f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381659035 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2381659035
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2355645419
Short name T780
Test name
Test status
Simulation time 15033360 ps
CPU time 0.98 seconds
Started Aug 13 06:45:23 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 215592 kb
Host smart-e8b24931-cc14-4551-95e2-2c6eff80e8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355645419 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2355645419
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1933726117
Short name T327
Test name
Test status
Simulation time 609660045 ps
CPU time 3.76 seconds
Started Aug 13 06:45:21 PM PDT 24
Finished Aug 13 06:45:25 PM PDT 24
Peak memory 217656 kb
Host smart-606dfbc3-97bc-4e43-8595-6c2217fa9c78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933726117 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1933726117
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3691640090
Short name T646
Test name
Test status
Simulation time 2012238835 ps
CPU time 45.07 seconds
Started Aug 13 06:45:30 PM PDT 24
Finished Aug 13 06:46:15 PM PDT 24
Peak memory 218208 kb
Host smart-3a14f9f1-0b70-4971-bff9-4342cf3f6bf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691640090 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3691640090
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.1290941018
Short name T281
Test name
Test status
Simulation time 41541146 ps
CPU time 1.34 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 216012 kb
Host smart-1aa79077-e5ef-4758-bb7c-cd489c795f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290941018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1290941018
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1028829238
Short name T389
Test name
Test status
Simulation time 43287205 ps
CPU time 0.86 seconds
Started Aug 13 06:46:26 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 218352 kb
Host smart-0c204bbc-ef92-45af-91a1-30cc43957f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028829238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1028829238
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1776700626
Short name T829
Test name
Test status
Simulation time 450498331 ps
CPU time 2.05 seconds
Started Aug 13 06:46:28 PM PDT 24
Finished Aug 13 06:46:30 PM PDT 24
Peak memory 219336 kb
Host smart-53bb7a7d-ca11-428f-a380-0f415fc27911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776700626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1776700626
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2345900504
Short name T530
Test name
Test status
Simulation time 93739610 ps
CPU time 1.26 seconds
Started Aug 13 06:46:46 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 221060 kb
Host smart-f70c5e77-d5da-4dbe-a014-215108649dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345900504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2345900504
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.442321190
Short name T736
Test name
Test status
Simulation time 22050727 ps
CPU time 1.01 seconds
Started Aug 13 06:46:26 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 224028 kb
Host smart-83996981-b962-449a-81cf-2f1810107d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442321190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.442321190
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.902613167
Short name T745
Test name
Test status
Simulation time 36343646 ps
CPU time 1.36 seconds
Started Aug 13 06:46:32 PM PDT 24
Finished Aug 13 06:46:33 PM PDT 24
Peak memory 217692 kb
Host smart-ed981ffa-7684-4cdd-91d0-aecda46ab9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902613167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.902613167
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.792568651
Short name T663
Test name
Test status
Simulation time 22675783 ps
CPU time 1.16 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:25 PM PDT 24
Peak memory 220460 kb
Host smart-560bc08c-66c4-4e28-b926-acb9acc5a4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792568651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.792568651
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.4288721481
Short name T200
Test name
Test status
Simulation time 35465131 ps
CPU time 0.94 seconds
Started Aug 13 06:46:26 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 219576 kb
Host smart-80674c2b-3ed7-49de-82fc-3b4429772d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288721481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.4288721481
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.141535501
Short name T2
Test name
Test status
Simulation time 36292786 ps
CPU time 1.31 seconds
Started Aug 13 06:46:39 PM PDT 24
Finished Aug 13 06:46:40 PM PDT 24
Peak memory 218796 kb
Host smart-e9ff8cea-e222-4fc2-a17a-3357cb1f458a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141535501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.141535501
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3812135115
Short name T949
Test name
Test status
Simulation time 23230073 ps
CPU time 1.12 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:25 PM PDT 24
Peak memory 218880 kb
Host smart-dd6bcfaa-79ec-4d42-b80c-4e1d0e51c1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812135115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3812135115
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2695867169
Short name T191
Test name
Test status
Simulation time 19868224 ps
CPU time 1.14 seconds
Started Aug 13 06:46:59 PM PDT 24
Finished Aug 13 06:47:00 PM PDT 24
Peak memory 224204 kb
Host smart-d7319914-7ffe-44c2-8a64-2f140a17cd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695867169 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2695867169
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2696970167
Short name T943
Test name
Test status
Simulation time 54848713 ps
CPU time 1.23 seconds
Started Aug 13 06:46:43 PM PDT 24
Finished Aug 13 06:46:45 PM PDT 24
Peak memory 219244 kb
Host smart-ab528737-8ce9-4ffd-bd99-4069bd978e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696970167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2696970167
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.3215250983
Short name T183
Test name
Test status
Simulation time 26425117 ps
CPU time 1.19 seconds
Started Aug 13 06:46:26 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 220180 kb
Host smart-ca25609e-1f2d-488c-9eea-0408400f2896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215250983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.3215250983
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.866573395
Short name T210
Test name
Test status
Simulation time 29596055 ps
CPU time 1.47 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:46 PM PDT 24
Peak memory 225924 kb
Host smart-204ae17d-b5ca-47ed-b5d0-15d99a34ba2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866573395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.866573395
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2231680383
Short name T979
Test name
Test status
Simulation time 116968849 ps
CPU time 1.22 seconds
Started Aug 13 06:47:03 PM PDT 24
Finished Aug 13 06:47:04 PM PDT 24
Peak memory 217788 kb
Host smart-174846d2-8ca2-4f49-8215-93c8c2947927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231680383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2231680383
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.2617319122
Short name T556
Test name
Test status
Simulation time 67027240 ps
CPU time 1.11 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:46 PM PDT 24
Peak memory 219052 kb
Host smart-18ab73a0-e7de-4f6e-9c8c-ab2b5cb9c37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617319122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2617319122
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.235991499
Short name T582
Test name
Test status
Simulation time 56388929 ps
CPU time 1.36 seconds
Started Aug 13 06:46:46 PM PDT 24
Finished Aug 13 06:46:48 PM PDT 24
Peak memory 225904 kb
Host smart-562d3875-c93f-4591-b158-e8a31dea4168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235991499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.235991499
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3230392996
Short name T399
Test name
Test status
Simulation time 45232216 ps
CPU time 1.44 seconds
Started Aug 13 06:46:28 PM PDT 24
Finished Aug 13 06:46:34 PM PDT 24
Peak memory 218620 kb
Host smart-f75a3cc9-c4af-4b03-a2ba-1d11465dc481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230392996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3230392996
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3102962533
Short name T777
Test name
Test status
Simulation time 41888107 ps
CPU time 0.96 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 229488 kb
Host smart-92349e2e-ed0a-4ae3-9922-58926dd9d4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102962533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3102962533
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3661630841
Short name T951
Test name
Test status
Simulation time 44604034 ps
CPU time 1.48 seconds
Started Aug 13 06:46:42 PM PDT 24
Finished Aug 13 06:46:44 PM PDT 24
Peak memory 217576 kb
Host smart-c4cbac01-5136-45fd-9779-4be66aaa08c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661630841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3661630841
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.3720302627
Short name T958
Test name
Test status
Simulation time 88110622 ps
CPU time 1.2 seconds
Started Aug 13 06:46:30 PM PDT 24
Finished Aug 13 06:46:31 PM PDT 24
Peak memory 221056 kb
Host smart-10b05ea8-dc72-4343-895b-c0540a81ec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720302627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3720302627
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.644306925
Short name T206
Test name
Test status
Simulation time 21164823 ps
CPU time 0.96 seconds
Started Aug 13 06:46:34 PM PDT 24
Finished Aug 13 06:46:35 PM PDT 24
Peak memory 215692 kb
Host smart-0b089550-ffd2-48d1-a763-1fd8ff781609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644306925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.644306925
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3582171816
Short name T901
Test name
Test status
Simulation time 18917674 ps
CPU time 1.02 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:24 PM PDT 24
Peak memory 217720 kb
Host smart-f223c6f1-39d3-48e4-bc6b-69eeb06c9971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582171816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3582171816
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.735677685
Short name T628
Test name
Test status
Simulation time 126419222 ps
CPU time 1.07 seconds
Started Aug 13 06:46:34 PM PDT 24
Finished Aug 13 06:46:36 PM PDT 24
Peak memory 218920 kb
Host smart-9b43ad96-dbf7-46ac-ab39-20d31ca126ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735677685 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.735677685
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2635790849
Short name T962
Test name
Test status
Simulation time 19989154 ps
CPU time 1.1 seconds
Started Aug 13 06:46:28 PM PDT 24
Finished Aug 13 06:46:30 PM PDT 24
Peak memory 219824 kb
Host smart-9cf58350-cc36-433e-9015-1e138c2308f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635790849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2635790849
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.4191199466
Short name T402
Test name
Test status
Simulation time 86772982 ps
CPU time 2.99 seconds
Started Aug 13 06:46:24 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 218840 kb
Host smart-1c6c4d8e-6738-4942-b0b0-efbb95b1fb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191199466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.4191199466
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.749880773
Short name T179
Test name
Test status
Simulation time 111582846 ps
CPU time 1.09 seconds
Started Aug 13 06:46:44 PM PDT 24
Finished Aug 13 06:46:45 PM PDT 24
Peak memory 218696 kb
Host smart-c3d4c96c-6ed1-44ef-97fc-1f75de372dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749880773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.749880773
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.850822876
Short name T204
Test name
Test status
Simulation time 47491083 ps
CPU time 1.03 seconds
Started Aug 13 06:46:49 PM PDT 24
Finished Aug 13 06:46:50 PM PDT 24
Peak memory 220960 kb
Host smart-1b75ad53-5fc7-4e93-9fb5-da69dcbfc510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850822876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.850822876
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1218677035
Short name T456
Test name
Test status
Simulation time 165357495 ps
CPU time 1.45 seconds
Started Aug 13 06:46:46 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 219420 kb
Host smart-75c5d71c-6e78-40d0-9e36-56a2bbc7a7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218677035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1218677035
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1405800328
Short name T838
Test name
Test status
Simulation time 94096181 ps
CPU time 1.28 seconds
Started Aug 13 06:45:23 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 216104 kb
Host smart-522cce32-7743-4b41-9556-e5ac72f0ec60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405800328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1405800328
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.931842840
Short name T915
Test name
Test status
Simulation time 21316933 ps
CPU time 0.92 seconds
Started Aug 13 06:45:24 PM PDT 24
Finished Aug 13 06:45:25 PM PDT 24
Peak memory 207084 kb
Host smart-9ee464ce-1174-4c83-8b4c-bb814eb5547a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931842840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.931842840
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1745178510
Short name T207
Test name
Test status
Simulation time 37809815 ps
CPU time 0.86 seconds
Started Aug 13 06:45:33 PM PDT 24
Finished Aug 13 06:45:34 PM PDT 24
Peak memory 216848 kb
Host smart-4cf724eb-732c-4d58-839e-6b27d9a9fbd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745178510 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1745178510
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3622680491
Short name T791
Test name
Test status
Simulation time 42652560 ps
CPU time 1.44 seconds
Started Aug 13 06:45:31 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 217056 kb
Host smart-40a11716-cea8-41d5-afe5-9d919a388cf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622680491 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3622680491
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2527570093
Short name T877
Test name
Test status
Simulation time 23426869 ps
CPU time 1.01 seconds
Started Aug 13 06:45:22 PM PDT 24
Finished Aug 13 06:45:23 PM PDT 24
Peak memory 218704 kb
Host smart-047977fb-2bd5-4d6a-80f0-35b3177521a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527570093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2527570093
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3740274552
Short name T323
Test name
Test status
Simulation time 101184285 ps
CPU time 1.86 seconds
Started Aug 13 06:45:19 PM PDT 24
Finished Aug 13 06:45:21 PM PDT 24
Peak memory 219572 kb
Host smart-1e0780b7-b102-4512-9d18-d7d649e2cdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740274552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3740274552
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2762232628
Short name T788
Test name
Test status
Simulation time 21976441 ps
CPU time 1.21 seconds
Started Aug 13 06:45:31 PM PDT 24
Finished Aug 13 06:45:32 PM PDT 24
Peak memory 224272 kb
Host smart-cd5eb0fe-42e8-4f5a-9cc5-f14b074d1328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762232628 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2762232628
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1877964688
Short name T32
Test name
Test status
Simulation time 42278200 ps
CPU time 0.88 seconds
Started Aug 13 06:45:28 PM PDT 24
Finished Aug 13 06:45:29 PM PDT 24
Peak memory 207396 kb
Host smart-10d5230c-d28a-465b-9d0b-6b9fc7e9266e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877964688 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1877964688
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2757681871
Short name T432
Test name
Test status
Simulation time 55821608 ps
CPU time 0.92 seconds
Started Aug 13 06:45:16 PM PDT 24
Finished Aug 13 06:45:17 PM PDT 24
Peak memory 207416 kb
Host smart-72b19df2-32ea-4d5b-9a50-32d730b2cdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757681871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2757681871
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1643129473
Short name T497
Test name
Test status
Simulation time 740077344 ps
CPU time 2.91 seconds
Started Aug 13 06:45:27 PM PDT 24
Finished Aug 13 06:45:30 PM PDT 24
Peak memory 220644 kb
Host smart-63003b73-a439-497e-ad52-a9af652f99a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643129473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1643129473
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2345364412
Short name T221
Test name
Test status
Simulation time 9874220111 ps
CPU time 58.59 seconds
Started Aug 13 06:45:12 PM PDT 24
Finished Aug 13 06:46:11 PM PDT 24
Peak memory 215812 kb
Host smart-e41c7de6-05cc-473b-bf84-4fee19b75ba5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345364412 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2345364412
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1502268354
Short name T803
Test name
Test status
Simulation time 65138177 ps
CPU time 1.22 seconds
Started Aug 13 06:46:32 PM PDT 24
Finished Aug 13 06:46:33 PM PDT 24
Peak memory 219964 kb
Host smart-f337f473-aaec-4940-9405-17323a1fb1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502268354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1502268354
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1303763260
Short name T133
Test name
Test status
Simulation time 34008704 ps
CPU time 1.17 seconds
Started Aug 13 06:46:35 PM PDT 24
Finished Aug 13 06:46:36 PM PDT 24
Peak memory 229824 kb
Host smart-bd2db253-7e16-46b3-945c-722a2f56ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303763260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1303763260
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.216863471
Short name T644
Test name
Test status
Simulation time 48252752 ps
CPU time 1.49 seconds
Started Aug 13 06:46:42 PM PDT 24
Finished Aug 13 06:46:43 PM PDT 24
Peak memory 217620 kb
Host smart-10fe98ea-b192-480c-b3b2-8f05ba6eb40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216863471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.216863471
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.3987225295
Short name T295
Test name
Test status
Simulation time 26256819 ps
CPU time 1.27 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:46 PM PDT 24
Peak memory 219520 kb
Host smart-6ff71c98-8dd8-4d1a-bb94-5527853a8ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987225295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.3987225295
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.451285196
Short name T842
Test name
Test status
Simulation time 74110897 ps
CPU time 1.01 seconds
Started Aug 13 06:46:26 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 219900 kb
Host smart-16ec6b90-56e5-4c1d-87d6-bf409160d0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451285196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.451285196
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.222262187
Short name T551
Test name
Test status
Simulation time 32892431 ps
CPU time 1.33 seconds
Started Aug 13 06:46:40 PM PDT 24
Finished Aug 13 06:46:41 PM PDT 24
Peak memory 218832 kb
Host smart-dde200b4-ae77-466b-86b6-c54a188fd69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222262187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.222262187
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2965779954
Short name T175
Test name
Test status
Simulation time 29905772 ps
CPU time 1.27 seconds
Started Aug 13 06:46:41 PM PDT 24
Finished Aug 13 06:46:42 PM PDT 24
Peak memory 216000 kb
Host smart-305ac3e6-bcde-4d1a-b9ed-617597c3d485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965779954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2965779954
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.4255570513
Short name T532
Test name
Test status
Simulation time 27314438 ps
CPU time 0.87 seconds
Started Aug 13 06:46:42 PM PDT 24
Finished Aug 13 06:46:43 PM PDT 24
Peak memory 218304 kb
Host smart-f0868099-ae37-4ed9-8132-b82697658761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255570513 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.4255570513
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2042674859
Short name T748
Test name
Test status
Simulation time 80285575 ps
CPU time 1.15 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:26 PM PDT 24
Peak memory 217648 kb
Host smart-d2285a71-d3d6-409a-95dd-7cad864e4cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042674859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2042674859
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.17429536
Short name T811
Test name
Test status
Simulation time 23813309 ps
CPU time 1.18 seconds
Started Aug 13 06:46:25 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 220252 kb
Host smart-890a4988-ae93-4498-a814-91591148240f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17429536 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.17429536
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.1890186135
Short name T783
Test name
Test status
Simulation time 30594883 ps
CPU time 1.14 seconds
Started Aug 13 06:46:29 PM PDT 24
Finished Aug 13 06:46:31 PM PDT 24
Peak memory 224200 kb
Host smart-abe3420d-cebc-44d7-a092-1feaec007c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890186135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1890186135
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.738260024
Short name T501
Test name
Test status
Simulation time 79873489 ps
CPU time 1.4 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 218956 kb
Host smart-b8e46a17-a290-41f3-8854-2432b76ac168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738260024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.738260024
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.4214547040
Short name T591
Test name
Test status
Simulation time 21445355 ps
CPU time 1.11 seconds
Started Aug 13 06:46:33 PM PDT 24
Finished Aug 13 06:46:35 PM PDT 24
Peak memory 220232 kb
Host smart-2a80bc3f-3d8d-4c6f-9819-025c65c3633f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214547040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.4214547040
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3690247739
Short name T65
Test name
Test status
Simulation time 24264230 ps
CPU time 1.08 seconds
Started Aug 13 06:46:34 PM PDT 24
Finished Aug 13 06:46:36 PM PDT 24
Peak memory 224232 kb
Host smart-17fcf2db-ce7d-499e-b6df-30a07efeeb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690247739 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3690247739
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2208752885
Short name T625
Test name
Test status
Simulation time 63492914 ps
CPU time 1.19 seconds
Started Aug 13 06:46:32 PM PDT 24
Finished Aug 13 06:46:33 PM PDT 24
Peak memory 220216 kb
Host smart-20eef25a-6d37-4b04-9e28-d411a40bc373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208752885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2208752885
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3327742185
Short name T250
Test name
Test status
Simulation time 53662299 ps
CPU time 1.35 seconds
Started Aug 13 06:46:47 PM PDT 24
Finished Aug 13 06:46:48 PM PDT 24
Peak memory 220564 kb
Host smart-6ac6b6b8-c6cd-4209-872a-b29676d0ba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327742185 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3327742185
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1673689912
Short name T169
Test name
Test status
Simulation time 21028121 ps
CPU time 0.89 seconds
Started Aug 13 06:46:47 PM PDT 24
Finished Aug 13 06:46:48 PM PDT 24
Peak memory 218760 kb
Host smart-0b9a674f-1d75-4a63-9494-73114ace3895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673689912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1673689912
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3908438060
Short name T891
Test name
Test status
Simulation time 71335232 ps
CPU time 1.08 seconds
Started Aug 13 06:46:35 PM PDT 24
Finished Aug 13 06:46:36 PM PDT 24
Peak memory 219176 kb
Host smart-9ffb743e-a1d1-4b35-b8a5-acd205818248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908438060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3908438060
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1284730937
Short name T98
Test name
Test status
Simulation time 78422687 ps
CPU time 1.17 seconds
Started Aug 13 06:46:27 PM PDT 24
Finished Aug 13 06:46:28 PM PDT 24
Peak memory 218756 kb
Host smart-a587ab94-6178-441b-b14a-57834199aa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284730937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1284730937
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.1023240646
Short name T7
Test name
Test status
Simulation time 26652472 ps
CPU time 1.15 seconds
Started Aug 13 06:46:47 PM PDT 24
Finished Aug 13 06:46:48 PM PDT 24
Peak memory 219984 kb
Host smart-80ec7fc6-7c59-4fb4-8369-53b891e4d144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023240646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1023240646
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1929069091
Short name T322
Test name
Test status
Simulation time 121149002 ps
CPU time 2.83 seconds
Started Aug 13 06:46:36 PM PDT 24
Finished Aug 13 06:46:39 PM PDT 24
Peak memory 218072 kb
Host smart-79aab751-c8ef-466f-b7af-5d5868d4550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929069091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1929069091
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.211422695
Short name T275
Test name
Test status
Simulation time 69819345 ps
CPU time 1.09 seconds
Started Aug 13 06:46:49 PM PDT 24
Finished Aug 13 06:46:50 PM PDT 24
Peak memory 218924 kb
Host smart-5ca44cb0-43de-48ad-a03b-05911dc86010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211422695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.211422695
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.555546528
Short name T833
Test name
Test status
Simulation time 18169999 ps
CPU time 1.03 seconds
Started Aug 13 06:46:48 PM PDT 24
Finished Aug 13 06:46:49 PM PDT 24
Peak memory 218576 kb
Host smart-981214c4-66b4-474a-8e2d-70a9fec006fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555546528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.555546528
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2872766166
Short name T101
Test name
Test status
Simulation time 51656915 ps
CPU time 1.55 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:46 PM PDT 24
Peak memory 219264 kb
Host smart-2f2f066a-6c29-4ed0-aa93-40e106d69752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872766166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2872766166
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.4255417940
Short name T975
Test name
Test status
Simulation time 51407271 ps
CPU time 1.32 seconds
Started Aug 13 06:46:28 PM PDT 24
Finished Aug 13 06:46:29 PM PDT 24
Peak memory 216004 kb
Host smart-be562e98-bde9-444f-901a-fd06041f8e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255417940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.4255417940
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1721267807
Short name T67
Test name
Test status
Simulation time 25522623 ps
CPU time 1.19 seconds
Started Aug 13 06:46:51 PM PDT 24
Finished Aug 13 06:46:53 PM PDT 24
Peak memory 224224 kb
Host smart-900a5dcf-5d28-4f83-a140-78a104df9de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721267807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1721267807
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3583741524
Short name T689
Test name
Test status
Simulation time 327180087 ps
CPU time 1.26 seconds
Started Aug 13 06:46:48 PM PDT 24
Finished Aug 13 06:46:49 PM PDT 24
Peak memory 220348 kb
Host smart-351573cf-2730-453c-a53c-84d645790eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583741524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3583741524
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2244623255
Short name T305
Test name
Test status
Simulation time 52442330 ps
CPU time 1.29 seconds
Started Aug 13 06:46:52 PM PDT 24
Finished Aug 13 06:46:54 PM PDT 24
Peak memory 220304 kb
Host smart-86649cc0-9196-4e02-a23c-1a80a6541287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244623255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2244623255
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2109287837
Short name T952
Test name
Test status
Simulation time 43831909 ps
CPU time 0.86 seconds
Started Aug 13 06:46:39 PM PDT 24
Finished Aug 13 06:46:40 PM PDT 24
Peak memory 219724 kb
Host smart-63c5e28c-0ca2-4eb7-8db0-3daa726c0d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109287837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2109287837
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2494966336
Short name T450
Test name
Test status
Simulation time 33428019 ps
CPU time 1.47 seconds
Started Aug 13 06:46:34 PM PDT 24
Finished Aug 13 06:46:36 PM PDT 24
Peak memory 217540 kb
Host smart-78917b4d-fa72-4ec0-9b95-7ce01ea1e540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494966336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2494966336
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert_test.1026734654
Short name T466
Test name
Test status
Simulation time 75330503 ps
CPU time 0.79 seconds
Started Aug 13 06:45:26 PM PDT 24
Finished Aug 13 06:45:26 PM PDT 24
Peak memory 207128 kb
Host smart-a5cb26de-af85-4f7b-ad35-b089554fcc17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026734654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1026734654
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1604160064
Short name T378
Test name
Test status
Simulation time 25278219 ps
CPU time 0.88 seconds
Started Aug 13 06:45:23 PM PDT 24
Finished Aug 13 06:45:24 PM PDT 24
Peak memory 216612 kb
Host smart-a3b7e672-b15f-4e7e-b063-f6b27c7c783e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604160064 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1604160064
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1343453631
Short name T944
Test name
Test status
Simulation time 48698284 ps
CPU time 1.52 seconds
Started Aug 13 06:45:45 PM PDT 24
Finished Aug 13 06:45:47 PM PDT 24
Peak memory 217180 kb
Host smart-cb5dd54a-ea29-4403-b492-69b8f874b766
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343453631 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1343453631
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3622750279
Short name T964
Test name
Test status
Simulation time 34926099 ps
CPU time 0.92 seconds
Started Aug 13 06:45:26 PM PDT 24
Finished Aug 13 06:45:27 PM PDT 24
Peak memory 220212 kb
Host smart-2f9054d1-9b08-49cf-9441-b1bd270df1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622750279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3622750279
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1244525615
Short name T822
Test name
Test status
Simulation time 81768623 ps
CPU time 1.21 seconds
Started Aug 13 06:45:36 PM PDT 24
Finished Aug 13 06:45:37 PM PDT 24
Peak memory 219184 kb
Host smart-296ab085-810d-4ec7-8eb1-ab1beebd57bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244525615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1244525615
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.363152459
Short name T781
Test name
Test status
Simulation time 38571899 ps
CPU time 0.86 seconds
Started Aug 13 06:45:33 PM PDT 24
Finished Aug 13 06:45:34 PM PDT 24
Peak memory 215508 kb
Host smart-f7aacd98-aebb-4ddd-9565-bdff57419ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363152459 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.363152459
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1078692578
Short name T916
Test name
Test status
Simulation time 49505200 ps
CPU time 0.9 seconds
Started Aug 13 06:45:26 PM PDT 24
Finished Aug 13 06:45:27 PM PDT 24
Peak memory 207392 kb
Host smart-3ff0c666-c6c5-4798-9a09-725519738b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078692578 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1078692578
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3462838197
Short name T447
Test name
Test status
Simulation time 53461212 ps
CPU time 0.94 seconds
Started Aug 13 06:45:32 PM PDT 24
Finished Aug 13 06:45:33 PM PDT 24
Peak memory 215560 kb
Host smart-4218e419-26b3-4a75-a651-1f8f3c4d1553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462838197 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3462838197
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1053286574
Short name T420
Test name
Test status
Simulation time 221065408 ps
CPU time 4.65 seconds
Started Aug 13 06:45:25 PM PDT 24
Finished Aug 13 06:45:30 PM PDT 24
Peak memory 217376 kb
Host smart-72fba042-1780-4903-ac99-5e170038183d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053286574 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1053286574
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/90.edn_alert.1203480201
Short name T119
Test name
Test status
Simulation time 45584751 ps
CPU time 1.15 seconds
Started Aug 13 06:46:22 PM PDT 24
Finished Aug 13 06:46:23 PM PDT 24
Peak memory 218316 kb
Host smart-1dbe28ee-5749-4208-836e-bf0c1eda7ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203480201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.1203480201
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3089840724
Short name T167
Test name
Test status
Simulation time 30888626 ps
CPU time 0.97 seconds
Started Aug 13 06:46:26 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 224004 kb
Host smart-a4b21b21-3625-4be2-8d8d-83bc860d185f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089840724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3089840724
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1442944847
Short name T585
Test name
Test status
Simulation time 50989270 ps
CPU time 1.85 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 218804 kb
Host smart-0b94a6c6-5f14-4358-a0c3-b2dd3499486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442944847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1442944847
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.138530835
Short name T137
Test name
Test status
Simulation time 82795549 ps
CPU time 1.29 seconds
Started Aug 13 06:46:56 PM PDT 24
Finished Aug 13 06:46:57 PM PDT 24
Peak memory 218984 kb
Host smart-1e1cf03f-b66e-498d-9169-2e47c04ad6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138530835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.138530835
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3390826749
Short name T126
Test name
Test status
Simulation time 40224949 ps
CPU time 1.01 seconds
Started Aug 13 06:46:36 PM PDT 24
Finished Aug 13 06:46:37 PM PDT 24
Peak memory 220940 kb
Host smart-3ac1633a-6980-49a5-be5f-7460daac7f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390826749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3390826749
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1653689195
Short name T594
Test name
Test status
Simulation time 143052720 ps
CPU time 3.27 seconds
Started Aug 13 06:46:48 PM PDT 24
Finished Aug 13 06:46:51 PM PDT 24
Peak memory 220420 kb
Host smart-63b6827b-907c-4063-b280-9f03a63be8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653689195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1653689195
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.1937379423
Short name T368
Test name
Test status
Simulation time 20330037 ps
CPU time 1.05 seconds
Started Aug 13 06:46:46 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 218616 kb
Host smart-2ea6cf70-49fd-496d-954e-f23077615e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937379423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1937379423
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3233812910
Short name T442
Test name
Test status
Simulation time 84169367 ps
CPU time 1.22 seconds
Started Aug 13 06:46:55 PM PDT 24
Finished Aug 13 06:46:57 PM PDT 24
Peak memory 219796 kb
Host smart-6a0eabbd-1416-45aa-8f7a-5c34645abd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233812910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3233812910
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.3311935349
Short name T818
Test name
Test status
Simulation time 73870656 ps
CPU time 1.14 seconds
Started Aug 13 06:46:49 PM PDT 24
Finished Aug 13 06:46:50 PM PDT 24
Peak memory 218764 kb
Host smart-2072c76a-49f6-45b3-a27c-a9fbcfb23938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311935349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3311935349
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.486378060
Short name T189
Test name
Test status
Simulation time 23092054 ps
CPU time 1.04 seconds
Started Aug 13 06:46:34 PM PDT 24
Finished Aug 13 06:46:35 PM PDT 24
Peak memory 224184 kb
Host smart-840d7e67-0e8d-44bc-a87e-1aaceadff805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486378060 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.486378060
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.17747085
Short name T576
Test name
Test status
Simulation time 89252796 ps
CPU time 1.35 seconds
Started Aug 13 06:46:41 PM PDT 24
Finished Aug 13 06:46:43 PM PDT 24
Peak memory 219368 kb
Host smart-8cb401dc-6840-4d20-b75c-3f037edcc49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17747085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.17747085
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.3642042132
Short name T563
Test name
Test status
Simulation time 97819447 ps
CPU time 1.27 seconds
Started Aug 13 06:46:52 PM PDT 24
Finished Aug 13 06:46:53 PM PDT 24
Peak memory 221000 kb
Host smart-0030ba4f-f8da-45a9-9d1c-ba9371d45a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642042132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3642042132
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3334437558
Short name T208
Test name
Test status
Simulation time 18409712 ps
CPU time 1.1 seconds
Started Aug 13 06:46:46 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 218856 kb
Host smart-521c8b7e-14ea-488d-b2f8-f1c476f73eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334437558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3334437558
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1798272115
Short name T784
Test name
Test status
Simulation time 61785195 ps
CPU time 1.71 seconds
Started Aug 13 06:46:28 PM PDT 24
Finished Aug 13 06:46:30 PM PDT 24
Peak memory 215584 kb
Host smart-2e599a40-7567-4d72-abad-60236403635b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798272115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1798272115
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3166738220
Short name T449
Test name
Test status
Simulation time 91436397 ps
CPU time 1.21 seconds
Started Aug 13 06:46:41 PM PDT 24
Finished Aug 13 06:46:42 PM PDT 24
Peak memory 220128 kb
Host smart-f5e5c53d-7d57-4503-ba00-6cdc08aa5a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166738220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3166738220
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.291744369
Short name T170
Test name
Test status
Simulation time 25228011 ps
CPU time 1.04 seconds
Started Aug 13 06:46:41 PM PDT 24
Finished Aug 13 06:46:42 PM PDT 24
Peak memory 224112 kb
Host smart-efc0b6fd-3b09-443e-be52-2e1a1af05b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291744369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.291744369
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3064328553
Short name T674
Test name
Test status
Simulation time 57648926 ps
CPU time 1.27 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:46 PM PDT 24
Peak memory 219660 kb
Host smart-8740e6fe-eb8b-411e-96be-5d343300916a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064328553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3064328553
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.377125872
Short name T180
Test name
Test status
Simulation time 40856282 ps
CPU time 1.12 seconds
Started Aug 13 06:46:43 PM PDT 24
Finished Aug 13 06:46:44 PM PDT 24
Peak memory 218836 kb
Host smart-501afac6-f704-4b35-b242-a97d30c66126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377125872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.377125872
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3239955497
Short name T529
Test name
Test status
Simulation time 59708848 ps
CPU time 0.84 seconds
Started Aug 13 06:46:58 PM PDT 24
Finished Aug 13 06:46:59 PM PDT 24
Peak memory 215548 kb
Host smart-7990bf27-100a-451e-8c1b-3a5c7376f84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239955497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3239955497
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_alert.956164101
Short name T473
Test name
Test status
Simulation time 26623123 ps
CPU time 1.17 seconds
Started Aug 13 06:46:47 PM PDT 24
Finished Aug 13 06:46:48 PM PDT 24
Peak memory 219056 kb
Host smart-53708f24-20a6-4658-b69d-d1b8211ee61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956164101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.956164101
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.4077699741
Short name T703
Test name
Test status
Simulation time 72417253 ps
CPU time 1.13 seconds
Started Aug 13 06:47:06 PM PDT 24
Finished Aug 13 06:47:07 PM PDT 24
Peak memory 225752 kb
Host smart-0e1b7d07-b874-4c2c-9c03-cf1830a1217b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077699741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.4077699741
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1969400201
Short name T443
Test name
Test status
Simulation time 85640064 ps
CPU time 1.52 seconds
Started Aug 13 06:46:49 PM PDT 24
Finished Aug 13 06:46:50 PM PDT 24
Peak memory 220496 kb
Host smart-f5ecd352-ddb3-4b15-8dc5-594951f1db75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969400201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1969400201
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.4054261403
Short name T280
Test name
Test status
Simulation time 30769411 ps
CPU time 1.3 seconds
Started Aug 13 06:46:44 PM PDT 24
Finished Aug 13 06:46:46 PM PDT 24
Peak memory 218988 kb
Host smart-c7f25dfb-668e-4396-8775-0b0c8c8918c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054261403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.4054261403
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.370956889
Short name T213
Test name
Test status
Simulation time 32003498 ps
CPU time 0.85 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:46 PM PDT 24
Peak memory 219352 kb
Host smart-7fbb1c01-050b-4462-9894-8f57c321dc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370956889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.370956889
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3917417046
Short name T873
Test name
Test status
Simulation time 22777337 ps
CPU time 1.23 seconds
Started Aug 13 06:46:47 PM PDT 24
Finished Aug 13 06:46:48 PM PDT 24
Peak memory 220228 kb
Host smart-c5ca993a-a592-4e19-a713-37b5a43e698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917417046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3917417046
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2451538364
Short name T754
Test name
Test status
Simulation time 30165107 ps
CPU time 1.29 seconds
Started Aug 13 06:46:45 PM PDT 24
Finished Aug 13 06:46:47 PM PDT 24
Peak memory 215980 kb
Host smart-7de1e777-7642-49c5-a11e-a31d3b697876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451538364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2451538364
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.606327368
Short name T184
Test name
Test status
Simulation time 29174952 ps
CPU time 0.97 seconds
Started Aug 13 06:46:53 PM PDT 24
Finished Aug 13 06:46:54 PM PDT 24
Peak memory 224008 kb
Host smart-b266ec25-cb22-44f6-8e93-e2f724622780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606327368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.606327368
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2259933793
Short name T451
Test name
Test status
Simulation time 88007221 ps
CPU time 1.33 seconds
Started Aug 13 06:46:58 PM PDT 24
Finished Aug 13 06:46:59 PM PDT 24
Peak memory 217548 kb
Host smart-499ba8d9-8da1-43d3-9618-1aa8db6fa62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259933793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2259933793
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%