Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

4203

1

T2

26

T5

29

T30

15

all_values[1]

4203

1

T2

26

T5

29

T30

15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4449

1

T2

26

T5

26

T30

13

auto[1]

3957

1

T2

26

T5

32

T30

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3221

1

T2

28

T5

30

T30

16

auto[1]

5185

1

T2

24

T5

28

T30

14

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4945

1

T2

33

T5

43

T30

24

auto[1]

3461

1

T2

19

T5

15

T30

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

917

1

T2

8

T5

6

T30

3

all_values[0]

auto[0]

auto[0]

auto[1]

406

1

T5

1

T44

13

T100

4

all_values[0]

auto[0]

auto[1]

auto[0]

740

1

T2

6

T5

12

T30

3

all_values[0]

auto[0]

auto[1]

auto[1]

442

1

T2

3

T5

3

T30

6

all_values[0]

auto[1]

auto[0]

auto[1]

886

1

T2

3

T5

3

T44

20

all_values[0]

auto[1]

auto[1]

auto[1]

812

1

T2

6

T5

4

T30

3

all_values[1]

auto[0]

auto[0]

auto[0]

872

1

T2

9

T5

8

T30

8

all_values[1]

auto[0]

auto[0]

auto[1]

423

1

T2

1

T5

3

T44

15

all_values[1]

auto[0]

auto[1]

auto[0]

692

1

T2

5

T5

4

T30

2

all_values[1]

auto[0]

auto[1]

auto[1]

453

1

T2

1

T5

6

T30

2

all_values[1]

auto[1]

auto[0]

auto[1]

945

1

T2

5

T5

5

T30

2

all_values[1]

auto[1]

auto[1]

auto[1]

818

1

T2

5

T5

3

T30

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal