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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.86 98.25 93.97 97.02 92.44 96.37 99.77 93.18


Total test records in report: 1115
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T1010 /workspace/coverage/cover_reg_top/2.edn_csr_rw.4145897845 Aug 14 04:35:16 PM PDT 24 Aug 14 04:35:17 PM PDT 24 14579482 ps
T1011 /workspace/coverage/cover_reg_top/7.edn_tl_errors.834368710 Aug 14 04:35:52 PM PDT 24 Aug 14 04:35:55 PM PDT 24 75232940 ps
T1012 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4193403496 Aug 14 04:35:57 PM PDT 24 Aug 14 04:35:59 PM PDT 24 86679984 ps
T1013 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2933416209 Aug 14 04:35:29 PM PDT 24 Aug 14 04:35:30 PM PDT 24 52906989 ps
T1014 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3468236900 Aug 14 04:35:56 PM PDT 24 Aug 14 04:35:57 PM PDT 24 31528890 ps
T1015 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.529579137 Aug 14 04:35:42 PM PDT 24 Aug 14 04:35:44 PM PDT 24 778545788 ps
T1016 /workspace/coverage/cover_reg_top/12.edn_tl_errors.152438195 Aug 14 04:35:57 PM PDT 24 Aug 14 04:36:00 PM PDT 24 256514410 ps
T275 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1952027331 Aug 14 04:35:49 PM PDT 24 Aug 14 04:35:50 PM PDT 24 32967733 ps
T1017 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1586227165 Aug 14 04:35:51 PM PDT 24 Aug 14 04:35:52 PM PDT 24 23211319 ps
T1018 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1610674514 Aug 14 04:35:53 PM PDT 24 Aug 14 04:35:54 PM PDT 24 50611631 ps
T1019 /workspace/coverage/cover_reg_top/8.edn_intr_test.2106850934 Aug 14 04:35:57 PM PDT 24 Aug 14 04:35:58 PM PDT 24 89303318 ps
T1020 /workspace/coverage/cover_reg_top/6.edn_intr_test.3032343002 Aug 14 04:35:49 PM PDT 24 Aug 14 04:35:50 PM PDT 24 20765163 ps
T1021 /workspace/coverage/cover_reg_top/22.edn_intr_test.504116218 Aug 14 04:35:54 PM PDT 24 Aug 14 04:35:55 PM PDT 24 72983387 ps
T1022 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2664191893 Aug 14 04:35:55 PM PDT 24 Aug 14 04:35:57 PM PDT 24 200817250 ps
T1023 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.849182095 Aug 14 04:35:30 PM PDT 24 Aug 14 04:35:31 PM PDT 24 75893633 ps
T1024 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1937240196 Aug 14 04:35:50 PM PDT 24 Aug 14 04:35:53 PM PDT 24 136006651 ps
T1025 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2726903959 Aug 14 04:35:58 PM PDT 24 Aug 14 04:36:00 PM PDT 24 256192966 ps
T1026 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2717299335 Aug 14 04:35:56 PM PDT 24 Aug 14 04:35:58 PM PDT 24 193200540 ps
T1027 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3322835110 Aug 14 04:35:53 PM PDT 24 Aug 14 04:35:54 PM PDT 24 222508482 ps
T1028 /workspace/coverage/cover_reg_top/12.edn_intr_test.3227834515 Aug 14 04:35:56 PM PDT 24 Aug 14 04:35:57 PM PDT 24 30650227 ps
T1029 /workspace/coverage/cover_reg_top/47.edn_intr_test.2123243505 Aug 14 04:35:52 PM PDT 24 Aug 14 04:35:53 PM PDT 24 23177003 ps
T1030 /workspace/coverage/cover_reg_top/5.edn_intr_test.1179743290 Aug 14 04:35:21 PM PDT 24 Aug 14 04:35:22 PM PDT 24 37177120 ps
T1031 /workspace/coverage/cover_reg_top/11.edn_intr_test.1481209092 Aug 14 04:35:44 PM PDT 24 Aug 14 04:35:45 PM PDT 24 30350698 ps
T276 /workspace/coverage/cover_reg_top/12.edn_csr_rw.584263418 Aug 14 04:35:50 PM PDT 24 Aug 14 04:35:51 PM PDT 24 14397587 ps
T1032 /workspace/coverage/cover_reg_top/16.edn_intr_test.828683094 Aug 14 04:35:55 PM PDT 24 Aug 14 04:35:56 PM PDT 24 38612949 ps
T1033 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1836138826 Aug 14 04:35:51 PM PDT 24 Aug 14 04:35:55 PM PDT 24 92764914 ps
T277 /workspace/coverage/cover_reg_top/16.edn_csr_rw.358307274 Aug 14 04:35:51 PM PDT 24 Aug 14 04:35:52 PM PDT 24 28435920 ps
T1034 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1742837157 Aug 14 04:35:37 PM PDT 24 Aug 14 04:35:38 PM PDT 24 30901018 ps
T1035 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1478538822 Aug 14 04:35:45 PM PDT 24 Aug 14 04:35:47 PM PDT 24 19257543 ps
T1036 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3193624982 Aug 14 04:35:51 PM PDT 24 Aug 14 04:35:53 PM PDT 24 45242444 ps
T1037 /workspace/coverage/cover_reg_top/11.edn_csr_rw.813240125 Aug 14 04:35:29 PM PDT 24 Aug 14 04:35:30 PM PDT 24 13650291 ps
T278 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1746160681 Aug 14 04:35:28 PM PDT 24 Aug 14 04:35:29 PM PDT 24 27717230 ps
T1038 /workspace/coverage/cover_reg_top/46.edn_intr_test.3268811694 Aug 14 04:35:48 PM PDT 24 Aug 14 04:35:49 PM PDT 24 12620728 ps
T279 /workspace/coverage/cover_reg_top/4.edn_csr_rw.11432465 Aug 14 04:35:19 PM PDT 24 Aug 14 04:35:20 PM PDT 24 28669900 ps
T1039 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1505580615 Aug 14 04:35:51 PM PDT 24 Aug 14 04:35:54 PM PDT 24 92838735 ps
T1040 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.387661411 Aug 14 04:35:47 PM PDT 24 Aug 14 04:35:48 PM PDT 24 18520583 ps
T1041 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.293340894 Aug 14 04:35:42 PM PDT 24 Aug 14 04:35:44 PM PDT 24 93060846 ps
T1042 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1663459621 Aug 14 04:35:29 PM PDT 24 Aug 14 04:35:34 PM PDT 24 2299036662 ps
T1043 /workspace/coverage/cover_reg_top/41.edn_intr_test.1208218489 Aug 14 04:36:01 PM PDT 24 Aug 14 04:36:02 PM PDT 24 63031167 ps
T1044 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.291679281 Aug 14 04:35:33 PM PDT 24 Aug 14 04:35:34 PM PDT 24 61327557 ps
T1045 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2162156328 Aug 14 04:35:19 PM PDT 24 Aug 14 04:35:20 PM PDT 24 16835988 ps
T1046 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2347847589 Aug 14 04:35:43 PM PDT 24 Aug 14 04:35:47 PM PDT 24 110564597 ps
T1047 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1484133041 Aug 14 04:35:44 PM PDT 24 Aug 14 04:35:45 PM PDT 24 52647615 ps
T1048 /workspace/coverage/cover_reg_top/2.edn_intr_test.1380001104 Aug 14 04:35:24 PM PDT 24 Aug 14 04:35:25 PM PDT 24 28164918 ps
T1049 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1860738273 Aug 14 04:35:45 PM PDT 24 Aug 14 04:35:46 PM PDT 24 44504685 ps
T1050 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4108192088 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:00 PM PDT 24 66356851 ps
T1051 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2757141638 Aug 14 04:35:54 PM PDT 24 Aug 14 04:35:55 PM PDT 24 16867302 ps
T1052 /workspace/coverage/cover_reg_top/6.edn_csr_rw.713601820 Aug 14 04:35:48 PM PDT 24 Aug 14 04:35:49 PM PDT 24 12156823 ps
T1053 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2602045597 Aug 14 04:35:48 PM PDT 24 Aug 14 04:35:55 PM PDT 24 270585290 ps
T1054 /workspace/coverage/cover_reg_top/39.edn_intr_test.1426428098 Aug 14 04:35:52 PM PDT 24 Aug 14 04:35:53 PM PDT 24 31977597 ps
T1055 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2645656326 Aug 14 04:35:18 PM PDT 24 Aug 14 04:35:21 PM PDT 24 97771093 ps
T1056 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3221409773 Aug 14 04:35:41 PM PDT 24 Aug 14 04:35:43 PM PDT 24 32028880 ps
T1057 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3722880968 Aug 14 04:35:16 PM PDT 24 Aug 14 04:35:17 PM PDT 24 29259283 ps
T1058 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2863170397 Aug 14 04:35:56 PM PDT 24 Aug 14 04:35:58 PM PDT 24 371071541 ps
T1059 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2232879201 Aug 14 04:35:49 PM PDT 24 Aug 14 04:35:52 PM PDT 24 254687075 ps
T1060 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1549432149 Aug 14 04:35:52 PM PDT 24 Aug 14 04:35:59 PM PDT 24 62396087 ps
T1061 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2049917047 Aug 14 04:35:36 PM PDT 24 Aug 14 04:35:37 PM PDT 24 15336751 ps
T1062 /workspace/coverage/cover_reg_top/45.edn_intr_test.3623748465 Aug 14 04:35:55 PM PDT 24 Aug 14 04:35:57 PM PDT 24 18899928 ps
T1063 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2047522121 Aug 14 04:35:20 PM PDT 24 Aug 14 04:35:22 PM PDT 24 68956972 ps
T1064 /workspace/coverage/cover_reg_top/48.edn_intr_test.2291956918 Aug 14 04:35:57 PM PDT 24 Aug 14 04:35:58 PM PDT 24 23472500 ps
T1065 /workspace/coverage/cover_reg_top/1.edn_tl_errors.123876644 Aug 14 04:35:41 PM PDT 24 Aug 14 04:35:45 PM PDT 24 118983066 ps
T1066 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3309635227 Aug 14 04:35:52 PM PDT 24 Aug 14 04:35:55 PM PDT 24 296117915 ps
T1067 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3230652390 Aug 14 04:35:40 PM PDT 24 Aug 14 04:35:42 PM PDT 24 77697351 ps
T1068 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.298564954 Aug 14 04:35:20 PM PDT 24 Aug 14 04:35:21 PM PDT 24 43779688 ps
T1069 /workspace/coverage/cover_reg_top/26.edn_intr_test.30185763 Aug 14 04:35:36 PM PDT 24 Aug 14 04:35:37 PM PDT 24 13728992 ps
T1070 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4289029942 Aug 14 04:35:45 PM PDT 24 Aug 14 04:35:46 PM PDT 24 253411234 ps
T1071 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1208120746 Aug 14 04:35:47 PM PDT 24 Aug 14 04:35:48 PM PDT 24 28713076 ps
T1072 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2258357852 Aug 14 04:35:17 PM PDT 24 Aug 14 04:35:19 PM PDT 24 259481856 ps
T280 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.4240723955 Aug 14 04:35:34 PM PDT 24 Aug 14 04:35:35 PM PDT 24 37325440 ps
T1073 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3144745524 Aug 14 04:35:20 PM PDT 24 Aug 14 04:35:21 PM PDT 24 29014568 ps
T1074 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2953440468 Aug 14 04:35:55 PM PDT 24 Aug 14 04:35:57 PM PDT 24 52833339 ps
T1075 /workspace/coverage/cover_reg_top/10.edn_intr_test.3751811908 Aug 14 04:37:00 PM PDT 24 Aug 14 04:37:01 PM PDT 24 32179011 ps
T1076 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3991854607 Aug 14 04:35:55 PM PDT 24 Aug 14 04:35:56 PM PDT 24 22009241 ps
T1077 /workspace/coverage/cover_reg_top/3.edn_intr_test.2280968312 Aug 14 04:35:18 PM PDT 24 Aug 14 04:35:19 PM PDT 24 39823323 ps
T1078 /workspace/coverage/cover_reg_top/34.edn_intr_test.2955168589 Aug 14 04:35:48 PM PDT 24 Aug 14 04:35:49 PM PDT 24 83019766 ps
T1079 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2040615869 Aug 14 04:35:57 PM PDT 24 Aug 14 04:35:58 PM PDT 24 27549285 ps
T281 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1676564576 Aug 14 04:35:47 PM PDT 24 Aug 14 04:35:48 PM PDT 24 39636443 ps
T1080 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2148830136 Aug 14 04:35:33 PM PDT 24 Aug 14 04:35:39 PM PDT 24 17400180 ps
T1081 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2936531325 Aug 14 04:35:29 PM PDT 24 Aug 14 04:35:31 PM PDT 24 43034197 ps
T1082 /workspace/coverage/cover_reg_top/14.edn_intr_test.318642053 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:01 PM PDT 24 17785683 ps
T1083 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3106005619 Aug 14 04:35:49 PM PDT 24 Aug 14 04:35:51 PM PDT 24 26530212 ps
T1084 /workspace/coverage/cover_reg_top/13.edn_tl_errors.4287558520 Aug 14 04:35:46 PM PDT 24 Aug 14 04:35:50 PM PDT 24 135699680 ps
T1085 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2314968326 Aug 14 04:36:06 PM PDT 24 Aug 14 04:36:07 PM PDT 24 19377849 ps
T1086 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3497839565 Aug 14 04:35:40 PM PDT 24 Aug 14 04:35:42 PM PDT 24 23069796 ps
T1087 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1385744584 Aug 14 04:35:37 PM PDT 24 Aug 14 04:35:38 PM PDT 24 32503718 ps
T1088 /workspace/coverage/cover_reg_top/43.edn_intr_test.1870490646 Aug 14 04:35:51 PM PDT 24 Aug 14 04:35:52 PM PDT 24 35306106 ps
T1089 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1696685891 Aug 14 04:35:18 PM PDT 24 Aug 14 04:35:21 PM PDT 24 92223813 ps
T1090 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1009821619 Aug 14 04:35:20 PM PDT 24 Aug 14 04:35:22 PM PDT 24 31272135 ps
T1091 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2417923920 Aug 14 04:36:01 PM PDT 24 Aug 14 04:36:02 PM PDT 24 121636269 ps
T1092 /workspace/coverage/cover_reg_top/32.edn_intr_test.3382245849 Aug 14 04:35:58 PM PDT 24 Aug 14 04:35:59 PM PDT 24 37441331 ps
T1093 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.547648088 Aug 14 04:35:56 PM PDT 24 Aug 14 04:35:57 PM PDT 24 30296689 ps
T1094 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1522111021 Aug 14 04:35:49 PM PDT 24 Aug 14 04:35:51 PM PDT 24 98442118 ps
T1095 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.908557582 Aug 14 04:36:04 PM PDT 24 Aug 14 04:36:06 PM PDT 24 200633205 ps
T1096 /workspace/coverage/cover_reg_top/23.edn_intr_test.2890066458 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:00 PM PDT 24 13469791 ps
T1097 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1804926484 Aug 14 04:35:20 PM PDT 24 Aug 14 04:35:26 PM PDT 24 508935927 ps
T283 /workspace/coverage/cover_reg_top/18.edn_csr_rw.889024932 Aug 14 04:35:59 PM PDT 24 Aug 14 04:36:00 PM PDT 24 14967640 ps
T1098 /workspace/coverage/cover_reg_top/14.edn_csr_rw.554463476 Aug 14 04:35:38 PM PDT 24 Aug 14 04:35:39 PM PDT 24 12498408 ps
T1099 /workspace/coverage/cover_reg_top/11.edn_tl_errors.657236005 Aug 14 04:35:58 PM PDT 24 Aug 14 04:36:01 PM PDT 24 344223659 ps
T1100 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3147424389 Aug 14 04:35:50 PM PDT 24 Aug 14 04:35:52 PM PDT 24 42664580 ps
T1101 /workspace/coverage/cover_reg_top/15.edn_intr_test.1323589297 Aug 14 04:35:54 PM PDT 24 Aug 14 04:35:55 PM PDT 24 16372563 ps
T1102 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2219492319 Aug 14 04:35:20 PM PDT 24 Aug 14 04:35:22 PM PDT 24 41411051 ps
T1103 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2485621007 Aug 14 04:35:45 PM PDT 24 Aug 14 04:35:47 PM PDT 24 219314735 ps
T1104 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1046996431 Aug 14 04:35:47 PM PDT 24 Aug 14 04:35:48 PM PDT 24 15421985 ps
T1105 /workspace/coverage/cover_reg_top/9.edn_intr_test.497025446 Aug 14 04:35:48 PM PDT 24 Aug 14 04:35:49 PM PDT 24 29040758 ps
T1106 /workspace/coverage/cover_reg_top/4.edn_intr_test.1128158997 Aug 14 04:35:17 PM PDT 24 Aug 14 04:35:18 PM PDT 24 23777111 ps
T284 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1278812745 Aug 14 04:35:26 PM PDT 24 Aug 14 04:35:29 PM PDT 24 467663238 ps
T1107 /workspace/coverage/cover_reg_top/42.edn_intr_test.2587295159 Aug 14 04:35:58 PM PDT 24 Aug 14 04:35:59 PM PDT 24 21081756 ps
T1108 /workspace/coverage/cover_reg_top/33.edn_intr_test.3059147249 Aug 14 04:35:55 PM PDT 24 Aug 14 04:36:01 PM PDT 24 16188974 ps
T1109 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3039120490 Aug 14 04:35:21 PM PDT 24 Aug 14 04:35:22 PM PDT 24 54238206 ps
T1110 /workspace/coverage/cover_reg_top/17.edn_intr_test.3238242697 Aug 14 04:37:02 PM PDT 24 Aug 14 04:37:03 PM PDT 24 68776377 ps
T1111 /workspace/coverage/cover_reg_top/18.edn_intr_test.2959577698 Aug 14 04:35:53 PM PDT 24 Aug 14 04:35:54 PM PDT 24 51542539 ps
T1112 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4287386051 Aug 14 04:35:44 PM PDT 24 Aug 14 04:35:46 PM PDT 24 92395422 ps
T1113 /workspace/coverage/cover_reg_top/35.edn_intr_test.3804811225 Aug 14 04:36:01 PM PDT 24 Aug 14 04:36:02 PM PDT 24 38180139 ps
T1114 /workspace/coverage/cover_reg_top/37.edn_intr_test.1320051829 Aug 14 04:35:48 PM PDT 24 Aug 14 04:35:49 PM PDT 24 15977035 ps
T1115 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3348141773 Aug 14 04:35:50 PM PDT 24 Aug 14 04:35:51 PM PDT 24 78642905 ps

Test location /workspace/coverage/default/78.edn_genbits.968767075
Short name T1
Test name
Test status
Simulation time 47236046 ps
CPU time 1.8 seconds
Started Aug 14 05:33:14 PM PDT 24
Finished Aug 14 05:33:16 PM PDT 24
Peak memory 219076 kb
Host smart-2daa8fd3-4a2a-4cf7-87c9-025e719afc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968767075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.968767075
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.3929979813
Short name T14
Test name
Test status
Simulation time 67751941 ps
CPU time 1.16 seconds
Started Aug 14 05:33:46 PM PDT 24
Finished Aug 14 05:33:47 PM PDT 24
Peak memory 219612 kb
Host smart-debbfd46-67f1-4a95-a976-ceafaf44bc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929979813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3929979813
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1457221140
Short name T44
Test name
Test status
Simulation time 8507876515 ps
CPU time 51.33 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219296 kb
Host smart-d5fab6f1-412a-42dd-ac0f-4847690425ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457221140 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1457221140
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.edn_genbits.4065277646
Short name T25
Test name
Test status
Simulation time 40589810 ps
CPU time 1.51 seconds
Started Aug 14 05:33:24 PM PDT 24
Finished Aug 14 05:33:26 PM PDT 24
Peak memory 220424 kb
Host smart-3b2cc478-9332-48cc-8cff-51b80aee6ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065277646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.4065277646
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.960690950
Short name T19
Test name
Test status
Simulation time 1580730463 ps
CPU time 9.52 seconds
Started Aug 14 05:31:48 PM PDT 24
Finished Aug 14 05:31:58 PM PDT 24
Peak memory 240280 kb
Host smart-d20d84c5-4143-49ff-98d5-0c91c0d216d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960690950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.960690950
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/32.edn_err.3045923125
Short name T6
Test name
Test status
Simulation time 51225048 ps
CPU time 0.94 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 218772 kb
Host smart-cb1fcd12-5086-4793-9f6c-83b808fdc559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045923125 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3045923125
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/13.edn_stress_all.1698798941
Short name T5
Test name
Test status
Simulation time 343748708 ps
CPU time 6.52 seconds
Started Aug 14 05:32:12 PM PDT 24
Finished Aug 14 05:32:19 PM PDT 24
Peak memory 220380 kb
Host smart-784836c0-36fa-4c7e-a338-cba476c986b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698798941 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1698798941
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/65.edn_genbits.2594720459
Short name T22
Test name
Test status
Simulation time 53018305 ps
CPU time 1.94 seconds
Started Aug 14 05:33:09 PM PDT 24
Finished Aug 14 05:33:11 PM PDT 24
Peak memory 220624 kb
Host smart-15432f4e-3818-4f46-b4d3-b5a9314ec38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594720459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2594720459
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1241972235
Short name T91
Test name
Test status
Simulation time 61639252 ps
CPU time 1.11 seconds
Started Aug 14 05:32:37 PM PDT 24
Finished Aug 14 05:32:39 PM PDT 24
Peak memory 219100 kb
Host smart-e6487a55-3e4a-4ee0-92d5-83712b7b0667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241972235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1241972235
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/22.edn_err.306709029
Short name T61
Test name
Test status
Simulation time 102722009 ps
CPU time 0.98 seconds
Started Aug 14 05:32:36 PM PDT 24
Finished Aug 14 05:32:37 PM PDT 24
Peak memory 224040 kb
Host smart-d55b7e0a-9321-45cf-a6db-f6f64f5983e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306709029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.306709029
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/197.edn_alert.168184616
Short name T106
Test name
Test status
Simulation time 98247819 ps
CPU time 1.23 seconds
Started Aug 14 05:34:02 PM PDT 24
Finished Aug 14 05:34:04 PM PDT 24
Peak memory 220064 kb
Host smart-99601b4b-cc26-4595-b4f8-f9c134dc08f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168184616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.168184616
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1901638196
Short name T233
Test name
Test status
Simulation time 18490673857 ps
CPU time 68.63 seconds
Started Aug 14 05:32:45 PM PDT 24
Finished Aug 14 05:33:53 PM PDT 24
Peak memory 219284 kb
Host smart-410c3f97-df0c-4a48-93fa-6f7386b40ae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901638196 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1901638196
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_regwen.1645086611
Short name T415
Test name
Test status
Simulation time 16156677 ps
CPU time 0.98 seconds
Started Aug 14 05:32:02 PM PDT 24
Finished Aug 14 05:32:04 PM PDT 24
Peak memory 207412 kb
Host smart-4e660411-1967-4b25-a1bd-351b84dc0551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645086611 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1645086611
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1805940899
Short name T21
Test name
Test status
Simulation time 33633143 ps
CPU time 1.25 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 217264 kb
Host smart-d6251163-793a-448a-a532-0475675a766e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805940899 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1805940899
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3490675304
Short name T303
Test name
Test status
Simulation time 114699346 ps
CPU time 2.88 seconds
Started Aug 14 04:35:52 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 215280 kb
Host smart-0312a0cf-cb05-43d3-b15d-1c22df525b19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490675304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3490675304
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/198.edn_alert.4106541114
Short name T92
Test name
Test status
Simulation time 27272948 ps
CPU time 1.19 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 218888 kb
Host smart-fee42dfa-3d92-4db5-a55f-3baa0141f59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106541114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.4106541114
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.255067641
Short name T273
Test name
Test status
Simulation time 16432781 ps
CPU time 0.9 seconds
Started Aug 14 04:35:25 PM PDT 24
Finished Aug 14 04:35:26 PM PDT 24
Peak memory 207208 kb
Host smart-cd51b299-4e3a-466e-aecb-4d099576e439
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255067641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.255067641
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/32.edn_disable.3274043795
Short name T87
Test name
Test status
Simulation time 17515619 ps
CPU time 0.86 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 216880 kb
Host smart-95a44dd3-472d-4742-835c-473400b13462
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274043795 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3274043795
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable.1360488884
Short name T208
Test name
Test status
Simulation time 12540802 ps
CPU time 0.88 seconds
Started Aug 14 05:32:24 PM PDT 24
Finished Aug 14 05:32:25 PM PDT 24
Peak memory 217008 kb
Host smart-1cfdbc2c-ae48-45d5-8f7c-697968cfa71f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360488884 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1360488884
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable.2439939488
Short name T214
Test name
Test status
Simulation time 15630404 ps
CPU time 0.84 seconds
Started Aug 14 05:32:22 PM PDT 24
Finished Aug 14 05:32:23 PM PDT 24
Peak memory 216932 kb
Host smart-f4133ee9-48b8-425c-9db5-1ea5bc2672ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439939488 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2439939488
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.75879049
Short name T136
Test name
Test status
Simulation time 28303236 ps
CPU time 1.2 seconds
Started Aug 14 05:32:14 PM PDT 24
Finished Aug 14 05:32:15 PM PDT 24
Peak memory 217124 kb
Host smart-abdf5606-0f42-4ba9-8b98-1e8ecd8062ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75879049 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_dis
able_auto_req_mode.75879049
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.856456261
Short name T160
Test name
Test status
Simulation time 53587534 ps
CPU time 1.15 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:09 PM PDT 24
Peak memory 217232 kb
Host smart-04f8cee8-6fac-486d-9bd5-b9ec44fb7725
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856456261 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.856456261
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/61.edn_err.3067906014
Short name T205
Test name
Test status
Simulation time 20083776 ps
CPU time 1.08 seconds
Started Aug 14 05:33:09 PM PDT 24
Finished Aug 14 05:33:10 PM PDT 24
Peak memory 224224 kb
Host smart-eef8959f-ae2d-46e2-b346-ba3aca68006f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067906014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3067906014
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/0.edn_alert.4152002497
Short name T206
Test name
Test status
Simulation time 131991480 ps
CPU time 1.21 seconds
Started Aug 14 05:32:05 PM PDT 24
Finished Aug 14 05:32:06 PM PDT 24
Peak memory 221064 kb
Host smart-76c689cc-be3b-4b0e-a73c-b80c9f9e17ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152002497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.4152002497
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert.2088000372
Short name T167
Test name
Test status
Simulation time 67961640 ps
CPU time 1.2 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 219028 kb
Host smart-9756d06f-a7b4-4d8f-9935-161544e8a3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088000372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2088000372
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/120.edn_alert.4112388947
Short name T438
Test name
Test status
Simulation time 21676551 ps
CPU time 1.13 seconds
Started Aug 14 05:33:30 PM PDT 24
Finished Aug 14 05:33:31 PM PDT 24
Peak memory 220052 kb
Host smart-abe96d94-2b1e-4b88-a7ae-ea6813350b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112388947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.4112388947
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/3.edn_sec_cm.659280449
Short name T17
Test name
Test status
Simulation time 1528584290 ps
CPU time 4.65 seconds
Started Aug 14 05:31:51 PM PDT 24
Finished Aug 14 05:31:56 PM PDT 24
Peak memory 239276 kb
Host smart-ee85d0da-38bb-4933-a273-b859c849a9e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659280449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.659280449
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/257.edn_genbits.584800481
Short name T11
Test name
Test status
Simulation time 31091019 ps
CPU time 1.36 seconds
Started Aug 14 05:34:30 PM PDT 24
Finished Aug 14 05:34:31 PM PDT 24
Peak memory 217732 kb
Host smart-14bea5c0-5b72-4ec1-ae4a-ee90bf3872e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584800481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.584800481
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2997366614
Short name T155
Test name
Test status
Simulation time 60198906 ps
CPU time 1.07 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 221144 kb
Host smart-fe749990-7242-4a71-a55b-834d98c24d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997366614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2997366614
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/173.edn_alert.1682766895
Short name T524
Test name
Test status
Simulation time 39085858 ps
CPU time 1.23 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 216004 kb
Host smart-8f7972b3-69b2-49ec-88fa-56420ccee5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682766895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1682766895
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/9.edn_stress_all.2832284839
Short name T118
Test name
Test status
Simulation time 868857421 ps
CPU time 5.15 seconds
Started Aug 14 05:32:10 PM PDT 24
Finished Aug 14 05:32:16 PM PDT 24
Peak memory 217540 kb
Host smart-0186eba0-af7f-4950-9dc0-5e1af178fb89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832284839 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2832284839
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/107.edn_alert.1211743947
Short name T161
Test name
Test status
Simulation time 43283614 ps
CPU time 1.17 seconds
Started Aug 14 05:33:29 PM PDT 24
Finished Aug 14 05:33:35 PM PDT 24
Peak memory 218912 kb
Host smart-34234a72-2063-4e16-a57f-f6bcf193bde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211743947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1211743947
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.235555361
Short name T692
Test name
Test status
Simulation time 118315868 ps
CPU time 0.97 seconds
Started Aug 14 05:32:08 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 217184 kb
Host smart-be253d7a-ab54-45e3-9145-e5f97e392d8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235555361 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.235555361
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/124.edn_alert.1904551130
Short name T715
Test name
Test status
Simulation time 35567965 ps
CPU time 1.1 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 220072 kb
Host smart-ea2dd4b7-1e98-4801-9789-688ddc38371c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904551130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1904551130
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/144.edn_alert.517724602
Short name T117
Test name
Test status
Simulation time 84438969 ps
CPU time 1.07 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 219996 kb
Host smart-09c70d34-cfca-4a65-8047-4d7522486ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517724602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.517724602
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/147.edn_alert.3982376377
Short name T644
Test name
Test status
Simulation time 42011620 ps
CPU time 1.1 seconds
Started Aug 14 05:33:37 PM PDT 24
Finished Aug 14 05:33:38 PM PDT 24
Peak memory 218956 kb
Host smart-612c2cbe-19b6-4572-958c-efed1d885649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982376377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3982376377
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/95.edn_alert.3004360902
Short name T149
Test name
Test status
Simulation time 24145328 ps
CPU time 1.24 seconds
Started Aug 14 05:33:25 PM PDT 24
Finished Aug 14 05:33:27 PM PDT 24
Peak memory 220728 kb
Host smart-eba51336-a2e8-489f-92a3-54356a992ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004360902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3004360902
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/41.edn_intr.3222066841
Short name T36
Test name
Test status
Simulation time 24434085 ps
CPU time 0.98 seconds
Started Aug 14 05:32:54 PM PDT 24
Finished Aug 14 05:32:55 PM PDT 24
Peak memory 216112 kb
Host smart-b12e6ca3-4413-4d32-82e2-79ca1815bca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222066841 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3222066841
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/15.edn_intr.3098575067
Short name T109
Test name
Test status
Simulation time 46975746 ps
CPU time 0.84 seconds
Started Aug 14 05:32:19 PM PDT 24
Finished Aug 14 05:32:20 PM PDT 24
Peak memory 215728 kb
Host smart-7598fca5-e05d-444d-8446-b62b120d9926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098575067 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3098575067
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/290.edn_genbits.2319413047
Short name T320
Test name
Test status
Simulation time 240178346 ps
CPU time 3.18 seconds
Started Aug 14 05:35:00 PM PDT 24
Finished Aug 14 05:35:04 PM PDT 24
Peak memory 217924 kb
Host smart-d2062ac6-a591-440a-a03e-6cd927b36387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319413047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2319413047
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.89861761
Short name T193
Test name
Test status
Simulation time 38729776 ps
CPU time 1.2 seconds
Started Aug 14 05:32:19 PM PDT 24
Finished Aug 14 05:32:20 PM PDT 24
Peak memory 220128 kb
Host smart-e9d977aa-5298-4e8b-a010-584bb2890892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89861761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.89861761
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/33.edn_disable.3964419339
Short name T612
Test name
Test status
Simulation time 30040711 ps
CPU time 0.84 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 216828 kb
Host smart-9b03befb-48a1-499f-8a1f-1031d7948209
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964419339 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3964419339
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable.387659716
Short name T199
Test name
Test status
Simulation time 33702723 ps
CPU time 0.85 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 216880 kb
Host smart-db768174-5858-43ae-b0d1-cd1c582e1809
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387659716 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.387659716
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable.1836218675
Short name T3
Test name
Test status
Simulation time 65928218 ps
CPU time 0.85 seconds
Started Aug 14 05:31:53 PM PDT 24
Finished Aug 14 05:31:55 PM PDT 24
Peak memory 219516 kb
Host smart-8da618b5-b475-4496-afff-76252c9e8971
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836218675 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1836218675
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.477093293
Short name T191
Test name
Test status
Simulation time 25364871 ps
CPU time 1.15 seconds
Started Aug 14 05:32:16 PM PDT 24
Finished Aug 14 05:32:17 PM PDT 24
Peak memory 218624 kb
Host smart-4bee61d8-6490-446d-a656-4658d8676a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477093293 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.477093293
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/133.edn_alert.803924222
Short name T202
Test name
Test status
Simulation time 45121287 ps
CPU time 1.14 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 219476 kb
Host smart-fad9f774-862f-48b0-b1b0-7a767913e48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803924222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.803924222
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1262255695
Short name T730
Test name
Test status
Simulation time 371247156 ps
CPU time 1.22 seconds
Started Aug 14 05:32:21 PM PDT 24
Finished Aug 14 05:32:23 PM PDT 24
Peak memory 217240 kb
Host smart-7f8a0b57-a483-42ee-95b3-c871a28592ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262255695 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1262255695
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_disable.587075432
Short name T219
Test name
Test status
Simulation time 163996692 ps
CPU time 0.91 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:32:59 PM PDT 24
Peak memory 216840 kb
Host smart-6db6187c-1628-4c34-835f-316ae898448a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587075432 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.587075432
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.603356619
Short name T207
Test name
Test status
Simulation time 24593339 ps
CPU time 0.93 seconds
Started Aug 14 05:33:04 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 219604 kb
Host smart-cc67e7b7-1f97-43a3-9c4f-ac34f4e99bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603356619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.603356619
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/11.edn_alert_test.2664481317
Short name T367
Test name
Test status
Simulation time 47753455 ps
CPU time 0.92 seconds
Started Aug 14 05:32:11 PM PDT 24
Finished Aug 14 05:32:13 PM PDT 24
Peak memory 207152 kb
Host smart-748bc23b-bae9-43e7-bf39-dbfb2a2a750b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664481317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2664481317
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/207.edn_genbits.3833096624
Short name T48
Test name
Test status
Simulation time 33714132 ps
CPU time 1.39 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 218840 kb
Host smart-bd3d3f5d-8a2e-41bc-a7e2-ee6270a93735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833096624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3833096624
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2604060971
Short name T317
Test name
Test status
Simulation time 87218118 ps
CPU time 1.15 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:53 PM PDT 24
Peak memory 219016 kb
Host smart-6d5bbb6a-1b22-418e-a7ec-db07a7f937b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604060971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2604060971
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.3750880957
Short name T299
Test name
Test status
Simulation time 132457788 ps
CPU time 1.53 seconds
Started Aug 14 05:34:07 PM PDT 24
Finished Aug 14 05:34:09 PM PDT 24
Peak memory 219200 kb
Host smart-9fdc8f6f-75b7-46c8-9015-25e5fac95921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750880957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3750880957
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_stress_all.2826328938
Short name T254
Test name
Test status
Simulation time 143813854 ps
CPU time 3.43 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 215576 kb
Host smart-5d1529e6-f06b-498a-b2e5-27d097e2eaa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826328938 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2826328938
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_intr.389837809
Short name T957
Test name
Test status
Simulation time 26344057 ps
CPU time 1.05 seconds
Started Aug 14 05:32:30 PM PDT 24
Finished Aug 14 05:32:32 PM PDT 24
Peak memory 216032 kb
Host smart-fe7d755b-d5f9-4d34-8742-fb3241996303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389837809 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.389837809
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/13.edn_alert.2554189559
Short name T231
Test name
Test status
Simulation time 44049708 ps
CPU time 1.2 seconds
Started Aug 14 05:32:13 PM PDT 24
Finished Aug 14 05:32:14 PM PDT 24
Peak memory 219092 kb
Host smart-b46e8b32-12d2-442e-92c7-fa31bc1482fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554189559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2554189559
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2729197041
Short name T285
Test name
Test status
Simulation time 31163849 ps
CPU time 0.76 seconds
Started Aug 14 04:35:26 PM PDT 24
Finished Aug 14 04:35:26 PM PDT 24
Peak memory 207032 kb
Host smart-89581efd-43e1-4422-916a-ffc330de5715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729197041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2729197041
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/0.edn_genbits.3055721477
Short name T512
Test name
Test status
Simulation time 71078997 ps
CPU time 2.26 seconds
Started Aug 14 05:31:54 PM PDT 24
Finished Aug 14 05:31:57 PM PDT 24
Peak memory 219608 kb
Host smart-bcef14c3-68ed-480e-898e-8f22ae5dfb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055721477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3055721477
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_stress_all.351036692
Short name T344
Test name
Test status
Simulation time 276643493 ps
CPU time 2.16 seconds
Started Aug 14 05:31:55 PM PDT 24
Finished Aug 14 05:31:57 PM PDT 24
Peak memory 215668 kb
Host smart-33249c71-7169-4bb6-ade3-7c09069c5ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351036692 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.351036692
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all.2337088759
Short name T336
Test name
Test status
Simulation time 932182532 ps
CPU time 3.23 seconds
Started Aug 14 05:32:16 PM PDT 24
Finished Aug 14 05:32:19 PM PDT 24
Peak memory 217780 kb
Host smart-0eab6c06-87c6-4d9b-bafe-b386e664f46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337088759 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2337088759
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/145.edn_genbits.4155421296
Short name T325
Test name
Test status
Simulation time 262005911 ps
CPU time 1.36 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 218924 kb
Host smart-e5e4fc9e-2dc1-4013-8514-c3ff66862eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155421296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4155421296
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2116076742
Short name T343
Test name
Test status
Simulation time 63372172 ps
CPU time 1.41 seconds
Started Aug 14 05:34:28 PM PDT 24
Finished Aug 14 05:34:30 PM PDT 24
Peak memory 218756 kb
Host smart-1bb56c2c-4a64-4b0b-9c89-6affed99473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116076742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2116076742
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_genbits.2018422963
Short name T323
Test name
Test status
Simulation time 80913509 ps
CPU time 3.01 seconds
Started Aug 14 05:32:22 PM PDT 24
Finished Aug 14 05:32:25 PM PDT 24
Peak memory 220404 kb
Host smart-dd97f498-2f04-4d4a-b9f2-386e2a15d771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018422963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2018422963
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2454811719
Short name T328
Test name
Test status
Simulation time 224776165 ps
CPU time 2.83 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 217796 kb
Host smart-f2c9e6bf-65fb-450f-a0cb-5ab4a39fe33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454811719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2454811719
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3706326581
Short name T20
Test name
Test status
Simulation time 21912553 ps
CPU time 1.12 seconds
Started Aug 14 05:32:55 PM PDT 24
Finished Aug 14 05:32:56 PM PDT 24
Peak memory 217224 kb
Host smart-5e65addf-35d2-45e6-8cd5-03a29478aa46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706326581 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3706326581
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/86.edn_genbits.2022035364
Short name T319
Test name
Test status
Simulation time 42594629 ps
CPU time 1.6 seconds
Started Aug 14 05:33:41 PM PDT 24
Finished Aug 14 05:33:43 PM PDT 24
Peak memory 218904 kb
Host smart-79032400-10fb-4f03-b0ad-58bc0ac26af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022035364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2022035364
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3179963011
Short name T112
Test name
Test status
Simulation time 26654130 ps
CPU time 1 seconds
Started Aug 14 05:32:11 PM PDT 24
Finished Aug 14 05:32:13 PM PDT 24
Peak memory 216092 kb
Host smart-1e33d894-5c88-432a-862a-cb03346ba00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179963011 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3179963011
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/1.edn_alert.840265392
Short name T128
Test name
Test status
Simulation time 37581548 ps
CPU time 1.13 seconds
Started Aug 14 05:31:50 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 219104 kb
Host smart-098039a1-ad84-42fc-aeef-3cefb689ee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840265392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.840265392
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/196.edn_alert.579009086
Short name T944
Test name
Test status
Simulation time 66534209 ps
CPU time 1.17 seconds
Started Aug 14 05:34:16 PM PDT 24
Finished Aug 14 05:34:17 PM PDT 24
Peak memory 218840 kb
Host smart-c102154a-0685-489f-835b-399b14323ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579009086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.579009086
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/232.edn_genbits.1114448159
Short name T12
Test name
Test status
Simulation time 90131726 ps
CPU time 1.67 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 215616 kb
Host smart-8a0188f7-e1de-4641-a459-fb1882bd7178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114448159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1114448159
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1860738273
Short name T1049
Test name
Test status
Simulation time 44504685 ps
CPU time 1.13 seconds
Started Aug 14 04:35:45 PM PDT 24
Finished Aug 14 04:35:46 PM PDT 24
Peak memory 207120 kb
Host smart-edc4a988-59ed-47c6-87cf-f7e5cec144ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860738273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1860738273
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1696685891
Short name T1089
Test name
Test status
Simulation time 92223813 ps
CPU time 2.93 seconds
Started Aug 14 04:35:18 PM PDT 24
Finished Aug 14 04:35:21 PM PDT 24
Peak memory 207112 kb
Host smart-9ca71c47-7614-433c-8560-7c6479904434
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696685891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1696685891
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2219492319
Short name T1102
Test name
Test status
Simulation time 41411051 ps
CPU time 1.65 seconds
Started Aug 14 04:35:20 PM PDT 24
Finished Aug 14 04:35:22 PM PDT 24
Peak memory 215392 kb
Host smart-826abc32-d2c3-4ae0-867f-74e77c61296d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219492319 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2219492319
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1890242562
Short name T983
Test name
Test status
Simulation time 24840092 ps
CPU time 0.85 seconds
Started Aug 14 04:35:20 PM PDT 24
Finished Aug 14 04:35:21 PM PDT 24
Peak memory 206944 kb
Host smart-1b7779eb-3a17-4150-bdd6-3a1bbf45b155
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890242562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1890242562
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2148830136
Short name T1080
Test name
Test status
Simulation time 17400180 ps
CPU time 1.14 seconds
Started Aug 14 04:35:33 PM PDT 24
Finished Aug 14 04:35:39 PM PDT 24
Peak memory 207208 kb
Host smart-27206cc3-65b0-4f30-a365-53478cf4b1b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148830136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2148830136
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2602045597
Short name T1053
Test name
Test status
Simulation time 270585290 ps
CPU time 2.73 seconds
Started Aug 14 04:35:48 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 215328 kb
Host smart-1c58ae3d-fd35-450e-a872-eff725227eee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602045597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2602045597
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2047522121
Short name T1063
Test name
Test status
Simulation time 68956972 ps
CPU time 2.08 seconds
Started Aug 14 04:35:20 PM PDT 24
Finished Aug 14 04:35:22 PM PDT 24
Peak memory 215384 kb
Host smart-d63d8005-a659-4380-830b-920967167567
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047522121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2047522121
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.257228815
Short name T998
Test name
Test status
Simulation time 72629607 ps
CPU time 1.19 seconds
Started Aug 14 04:35:45 PM PDT 24
Finished Aug 14 04:35:46 PM PDT 24
Peak memory 207172 kb
Host smart-a783e0cc-2f0c-438d-91ad-a8da0e98d3b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257228815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.257228815
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2750728783
Short name T282
Test name
Test status
Simulation time 231613305 ps
CPU time 3.25 seconds
Started Aug 14 04:35:20 PM PDT 24
Finished Aug 14 04:35:23 PM PDT 24
Peak memory 207140 kb
Host smart-2d6c2cd1-9c66-4a25-a7e4-ecd772c4b3ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750728783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2750728783
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1746160681
Short name T278
Test name
Test status
Simulation time 27717230 ps
CPU time 0.98 seconds
Started Aug 14 04:35:28 PM PDT 24
Finished Aug 14 04:35:29 PM PDT 24
Peak memory 207160 kb
Host smart-e0608b1d-08f9-45c7-8e2b-1e2ddf388918
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746160681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1746160681
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.531752913
Short name T989
Test name
Test status
Simulation time 59676588 ps
CPU time 1.35 seconds
Started Aug 14 04:35:16 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 215348 kb
Host smart-657a9b08-542d-4b2c-a07d-87154fac2867
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531752913 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.531752913
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3144745524
Short name T1073
Test name
Test status
Simulation time 29014568 ps
CPU time 0.83 seconds
Started Aug 14 04:35:20 PM PDT 24
Finished Aug 14 04:35:21 PM PDT 24
Peak memory 207124 kb
Host smart-5859cd23-b699-4886-bd00-3c7d02650066
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144745524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3144745524
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.747629136
Short name T997
Test name
Test status
Simulation time 13329269 ps
CPU time 0.93 seconds
Started Aug 14 04:35:45 PM PDT 24
Finished Aug 14 04:35:46 PM PDT 24
Peak memory 206896 kb
Host smart-f6718ab2-0fe6-40b8-9620-46b0b3b3d83b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747629136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.747629136
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1549432149
Short name T1060
Test name
Test status
Simulation time 62396087 ps
CPU time 1.05 seconds
Started Aug 14 04:35:52 PM PDT 24
Finished Aug 14 04:35:59 PM PDT 24
Peak memory 207204 kb
Host smart-b93de296-17cc-4e86-8896-e8d2c1e58b1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549432149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1549432149
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.123876644
Short name T1065
Test name
Test status
Simulation time 118983066 ps
CPU time 3.93 seconds
Started Aug 14 04:35:41 PM PDT 24
Finished Aug 14 04:35:45 PM PDT 24
Peak memory 215380 kb
Host smart-e40e5705-5d17-4943-96bb-01b8742d0dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123876644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.123876644
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1026351619
Short name T252
Test name
Test status
Simulation time 49474232 ps
CPU time 1.64 seconds
Started Aug 14 04:35:25 PM PDT 24
Finished Aug 14 04:35:27 PM PDT 24
Peak memory 215320 kb
Host smart-3ebb8666-2546-4121-8b49-ec49e8177f97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026351619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1026351619
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4252402200
Short name T991
Test name
Test status
Simulation time 31657085 ps
CPU time 1.37 seconds
Started Aug 14 04:35:46 PM PDT 24
Finished Aug 14 04:35:52 PM PDT 24
Peak memory 218868 kb
Host smart-85e7fd45-b847-4ce4-9033-556c29bec309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252402200 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4252402200
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2049917047
Short name T1061
Test name
Test status
Simulation time 15336751 ps
CPU time 0.92 seconds
Started Aug 14 04:35:36 PM PDT 24
Finished Aug 14 04:35:37 PM PDT 24
Peak memory 207052 kb
Host smart-1a29c2a6-f6c4-4660-9eb5-9d450af0b0da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049917047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2049917047
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3751811908
Short name T1075
Test name
Test status
Simulation time 32179011 ps
CPU time 0.77 seconds
Started Aug 14 04:37:00 PM PDT 24
Finished Aug 14 04:37:01 PM PDT 24
Peak memory 206896 kb
Host smart-ed5731c5-cd92-4a8f-a9b1-9d4bbfadcf41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751811908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3751811908
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.387661411
Short name T1040
Test name
Test status
Simulation time 18520583 ps
CPU time 1.05 seconds
Started Aug 14 04:35:47 PM PDT 24
Finished Aug 14 04:35:48 PM PDT 24
Peak memory 207244 kb
Host smart-3e40d80d-2b16-4ad3-99ae-f62367c898e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387661411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.387661411
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1708903309
Short name T981
Test name
Test status
Simulation time 148533471 ps
CPU time 1.85 seconds
Started Aug 14 04:35:54 PM PDT 24
Finished Aug 14 04:35:56 PM PDT 24
Peak memory 215468 kb
Host smart-51ae368c-364e-4e34-b6a7-e8a74816c846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708903309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1708903309
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3213000380
Short name T296
Test name
Test status
Simulation time 524135297 ps
CPU time 2.08 seconds
Started Aug 14 04:35:53 PM PDT 24
Finished Aug 14 04:35:56 PM PDT 24
Peak memory 207180 kb
Host smart-cae63315-2355-4a80-ad79-515852940876
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213000380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3213000380
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4058115127
Short name T984
Test name
Test status
Simulation time 39855792 ps
CPU time 1.1 seconds
Started Aug 14 04:35:53 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 215376 kb
Host smart-d8292441-6881-44c5-85f7-810deaf68c83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058115127 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.4058115127
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.813240125
Short name T1037
Test name
Test status
Simulation time 13650291 ps
CPU time 0.89 seconds
Started Aug 14 04:35:29 PM PDT 24
Finished Aug 14 04:35:30 PM PDT 24
Peak memory 207028 kb
Host smart-3cfd3281-354e-4748-8fe6-964b39dc190f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813240125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.813240125
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1481209092
Short name T1031
Test name
Test status
Simulation time 30350698 ps
CPU time 0.86 seconds
Started Aug 14 04:35:44 PM PDT 24
Finished Aug 14 04:35:45 PM PDT 24
Peak memory 206944 kb
Host smart-e402e2ab-a3e8-4b3b-a198-e4fc40b3e318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481209092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1481209092
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2940879999
Short name T287
Test name
Test status
Simulation time 166295339 ps
CPU time 0.99 seconds
Started Aug 14 04:35:42 PM PDT 24
Finished Aug 14 04:35:43 PM PDT 24
Peak memory 207180 kb
Host smart-396f0120-ec21-4793-89a9-2e148536ba74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940879999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2940879999
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.657236005
Short name T1099
Test name
Test status
Simulation time 344223659 ps
CPU time 2.85 seconds
Started Aug 14 04:35:58 PM PDT 24
Finished Aug 14 04:36:01 PM PDT 24
Peak memory 215448 kb
Host smart-4b0a2597-1dec-4d3c-b1bf-f321cef85f62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657236005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.657236005
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2936531325
Short name T1081
Test name
Test status
Simulation time 43034197 ps
CPU time 1.54 seconds
Started Aug 14 04:35:29 PM PDT 24
Finished Aug 14 04:35:31 PM PDT 24
Peak memory 215372 kb
Host smart-dc7faf13-6dfb-4670-bb80-5b2c69c98937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936531325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2936531325
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3193624982
Short name T1036
Test name
Test status
Simulation time 45242444 ps
CPU time 1.61 seconds
Started Aug 14 04:35:51 PM PDT 24
Finished Aug 14 04:35:53 PM PDT 24
Peak memory 215448 kb
Host smart-5b547604-c849-425b-8be7-ab50d43bb0a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193624982 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3193624982
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.584263418
Short name T276
Test name
Test status
Simulation time 14397587 ps
CPU time 0.9 seconds
Started Aug 14 04:35:50 PM PDT 24
Finished Aug 14 04:35:51 PM PDT 24
Peak memory 207196 kb
Host smart-abc2eb90-34ed-4785-b51e-8551252f2533
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584263418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.584263418
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3227834515
Short name T1028
Test name
Test status
Simulation time 30650227 ps
CPU time 0.79 seconds
Started Aug 14 04:35:56 PM PDT 24
Finished Aug 14 04:35:57 PM PDT 24
Peak memory 206896 kb
Host smart-e6562f25-c0b4-4bc2-ace2-7722fe3d413b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227834515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3227834515
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2601544226
Short name T289
Test name
Test status
Simulation time 39538964 ps
CPU time 1.01 seconds
Started Aug 14 04:35:54 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 207244 kb
Host smart-77030942-dfb1-4aa5-ad56-56cb118b53ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601544226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2601544226
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.152438195
Short name T1016
Test name
Test status
Simulation time 256514410 ps
CPU time 2.74 seconds
Started Aug 14 04:35:57 PM PDT 24
Finished Aug 14 04:36:00 PM PDT 24
Peak memory 215344 kb
Host smart-de654932-dcd6-48a3-99a3-0a63f930fa01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152438195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.152438195
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.908557582
Short name T1095
Test name
Test status
Simulation time 200633205 ps
CPU time 1.66 seconds
Started Aug 14 04:36:04 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 207272 kb
Host smart-8d2b7e9b-f65b-4fa9-a44c-558ee605e175
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908557582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.908557582
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4058909649
Short name T990
Test name
Test status
Simulation time 72841571 ps
CPU time 1.15 seconds
Started Aug 14 04:35:51 PM PDT 24
Finished Aug 14 04:35:53 PM PDT 24
Peak memory 215424 kb
Host smart-9852f503-fd0f-490d-8d35-0fc0766aaa14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058909649 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.4058909649
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1676564576
Short name T281
Test name
Test status
Simulation time 39636443 ps
CPU time 0.89 seconds
Started Aug 14 04:35:47 PM PDT 24
Finished Aug 14 04:35:48 PM PDT 24
Peak memory 207052 kb
Host smart-1c9bebe9-bac6-4f0d-ace7-cfc36b7f9cf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676564576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1676564576
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2688912994
Short name T987
Test name
Test status
Simulation time 98625508 ps
CPU time 0.82 seconds
Started Aug 14 04:35:45 PM PDT 24
Finished Aug 14 04:35:46 PM PDT 24
Peak memory 207040 kb
Host smart-8c79d915-f14e-40d4-92f3-eae3555b1a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688912994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2688912994
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4289029942
Short name T1070
Test name
Test status
Simulation time 253411234 ps
CPU time 1.11 seconds
Started Aug 14 04:35:45 PM PDT 24
Finished Aug 14 04:35:46 PM PDT 24
Peak memory 207256 kb
Host smart-38b8f683-1bb4-4e43-845a-f7735111fd2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289029942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.4289029942
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.4287558520
Short name T1084
Test name
Test status
Simulation time 135699680 ps
CPU time 3.85 seconds
Started Aug 14 04:35:46 PM PDT 24
Finished Aug 14 04:35:50 PM PDT 24
Peak memory 215428 kb
Host smart-1d6454de-531a-4e7d-848c-f2082f0f8692
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287558520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4287558520
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.377582030
Short name T994
Test name
Test status
Simulation time 216866824 ps
CPU time 2.97 seconds
Started Aug 14 04:35:39 PM PDT 24
Finished Aug 14 04:35:42 PM PDT 24
Peak memory 207236 kb
Host smart-74063c99-1a74-4bb1-b4b1-590fef409e47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377582030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.377582030
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3497839565
Short name T1086
Test name
Test status
Simulation time 23069796 ps
CPU time 1.37 seconds
Started Aug 14 04:35:40 PM PDT 24
Finished Aug 14 04:35:42 PM PDT 24
Peak memory 215516 kb
Host smart-5a643bb5-58c2-474e-ba65-89c02cc4aa5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497839565 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3497839565
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.554463476
Short name T1098
Test name
Test status
Simulation time 12498408 ps
CPU time 0.92 seconds
Started Aug 14 04:35:38 PM PDT 24
Finished Aug 14 04:35:39 PM PDT 24
Peak memory 207124 kb
Host smart-9edff698-e363-4950-aa56-c2b7359b54e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554463476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.554463476
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.318642053
Short name T1082
Test name
Test status
Simulation time 17785683 ps
CPU time 0.89 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:01 PM PDT 24
Peak memory 206844 kb
Host smart-b631a40f-e593-4a71-85a2-b2e594d996fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318642053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.318642053
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1610674514
Short name T1018
Test name
Test status
Simulation time 50611631 ps
CPU time 1.01 seconds
Started Aug 14 04:35:53 PM PDT 24
Finished Aug 14 04:35:54 PM PDT 24
Peak memory 207180 kb
Host smart-20a979ec-d297-4d76-816e-f73290473e7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610674514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1610674514
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2232879201
Short name T1059
Test name
Test status
Simulation time 254687075 ps
CPU time 2.8 seconds
Started Aug 14 04:35:49 PM PDT 24
Finished Aug 14 04:35:52 PM PDT 24
Peak memory 215424 kb
Host smart-3125152e-6b5d-4d5e-9044-4ec553ee3aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232879201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2232879201
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1505580615
Short name T1039
Test name
Test status
Simulation time 92838735 ps
CPU time 2.52 seconds
Started Aug 14 04:35:51 PM PDT 24
Finished Aug 14 04:35:54 PM PDT 24
Peak memory 207148 kb
Host smart-06421942-e539-426c-ba8e-0f4d92a8f4f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505580615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1505580615
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.547648088
Short name T1093
Test name
Test status
Simulation time 30296689 ps
CPU time 0.99 seconds
Started Aug 14 04:35:56 PM PDT 24
Finished Aug 14 04:35:57 PM PDT 24
Peak memory 207168 kb
Host smart-07dddfa7-bae0-4280-b529-0b49261dbb20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547648088 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.547648088
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1208120746
Short name T1071
Test name
Test status
Simulation time 28713076 ps
CPU time 0.76 seconds
Started Aug 14 04:35:47 PM PDT 24
Finished Aug 14 04:35:48 PM PDT 24
Peak memory 206996 kb
Host smart-9d15de9e-8daf-47a2-9bed-6ef1a00f58ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208120746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1208120746
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1323589297
Short name T1101
Test name
Test status
Simulation time 16372563 ps
CPU time 0.9 seconds
Started Aug 14 04:35:54 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 207028 kb
Host smart-00ec203c-c3bc-46a6-a0f6-cf6525c403b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323589297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1323589297
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3468236900
Short name T1014
Test name
Test status
Simulation time 31528890 ps
CPU time 1.12 seconds
Started Aug 14 04:35:56 PM PDT 24
Finished Aug 14 04:35:57 PM PDT 24
Peak memory 207168 kb
Host smart-a4d373cc-d0a8-48f8-b4b5-17fc756dd189
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468236900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3468236900
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1478538822
Short name T1035
Test name
Test status
Simulation time 19257543 ps
CPU time 1.34 seconds
Started Aug 14 04:35:45 PM PDT 24
Finished Aug 14 04:35:47 PM PDT 24
Peak memory 218436 kb
Host smart-bea8f87b-f705-4604-b4b6-2e7b57134b64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478538822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1478538822
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1522111021
Short name T1094
Test name
Test status
Simulation time 98442118 ps
CPU time 1.64 seconds
Started Aug 14 04:35:49 PM PDT 24
Finished Aug 14 04:35:51 PM PDT 24
Peak memory 207116 kb
Host smart-3a983803-ee93-4b0b-a765-1aa9f7924e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522111021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1522111021
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3991854607
Short name T1076
Test name
Test status
Simulation time 22009241 ps
CPU time 1.09 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:35:56 PM PDT 24
Peak memory 215456 kb
Host smart-307867c0-d1c2-4e75-8954-32d05a1271a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991854607 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3991854607
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.358307274
Short name T277
Test name
Test status
Simulation time 28435920 ps
CPU time 0.81 seconds
Started Aug 14 04:35:51 PM PDT 24
Finished Aug 14 04:35:52 PM PDT 24
Peak memory 206808 kb
Host smart-7b7ce4f4-026e-46bc-a478-7f66d51e91be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358307274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.358307274
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.828683094
Short name T1032
Test name
Test status
Simulation time 38612949 ps
CPU time 0.8 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:35:56 PM PDT 24
Peak memory 206808 kb
Host smart-0f763883-875c-4213-9f1b-36d87a335d1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828683094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.828683094
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4287386051
Short name T1112
Test name
Test status
Simulation time 92395422 ps
CPU time 1.27 seconds
Started Aug 14 04:35:44 PM PDT 24
Finished Aug 14 04:35:46 PM PDT 24
Peak memory 207136 kb
Host smart-c055921c-31b4-462b-b78e-8801140ad1bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287386051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.4287386051
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2953440468
Short name T1074
Test name
Test status
Simulation time 52833339 ps
CPU time 1.96 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:35:57 PM PDT 24
Peak memory 219284 kb
Host smart-d2d9eefb-f55d-4a53-b132-1037aad1fd61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953440468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2953440468
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4193403496
Short name T1012
Test name
Test status
Simulation time 86679984 ps
CPU time 2.46 seconds
Started Aug 14 04:35:57 PM PDT 24
Finished Aug 14 04:35:59 PM PDT 24
Peak memory 207248 kb
Host smart-5ef84e41-9457-4891-9efc-4bedacf5425c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193403496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4193403496
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3348141773
Short name T1115
Test name
Test status
Simulation time 78642905 ps
CPU time 1.4 seconds
Started Aug 14 04:35:50 PM PDT 24
Finished Aug 14 04:35:51 PM PDT 24
Peak memory 215516 kb
Host smart-5b871431-9555-4dba-a562-36781fe75cea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348141773 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3348141773
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1046996431
Short name T1104
Test name
Test status
Simulation time 15421985 ps
CPU time 0.94 seconds
Started Aug 14 04:35:47 PM PDT 24
Finished Aug 14 04:35:48 PM PDT 24
Peak memory 207192 kb
Host smart-284a5a8a-92a3-4188-b2d6-7c7b85f202e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046996431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1046996431
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3238242697
Short name T1110
Test name
Test status
Simulation time 68776377 ps
CPU time 0.78 seconds
Started Aug 14 04:37:02 PM PDT 24
Finished Aug 14 04:37:03 PM PDT 24
Peak memory 206888 kb
Host smart-8bc4ee83-284e-4aa1-bc7a-f7453de06781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238242697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3238242697
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1586227165
Short name T1017
Test name
Test status
Simulation time 23211319 ps
CPU time 1.15 seconds
Started Aug 14 04:35:51 PM PDT 24
Finished Aug 14 04:35:52 PM PDT 24
Peak memory 207200 kb
Host smart-10af1969-eecb-4bed-8c35-ae3408a931a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586227165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1586227165
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2717299335
Short name T1026
Test name
Test status
Simulation time 193200540 ps
CPU time 1.9 seconds
Started Aug 14 04:35:56 PM PDT 24
Finished Aug 14 04:35:58 PM PDT 24
Peak memory 215424 kb
Host smart-b032affa-715d-48a9-a010-847cc55f0b34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717299335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2717299335
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3322835110
Short name T1027
Test name
Test status
Simulation time 222508482 ps
CPU time 1.54 seconds
Started Aug 14 04:35:53 PM PDT 24
Finished Aug 14 04:35:54 PM PDT 24
Peak memory 215352 kb
Host smart-180288a4-c56d-4e96-88c5-13f8306aef26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322835110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3322835110
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2040615869
Short name T1079
Test name
Test status
Simulation time 27549285 ps
CPU time 1.2 seconds
Started Aug 14 04:35:57 PM PDT 24
Finished Aug 14 04:35:58 PM PDT 24
Peak memory 217152 kb
Host smart-3abdbfe3-56a8-4b1d-ab73-2ada9767e1e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040615869 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2040615869
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.889024932
Short name T283
Test name
Test status
Simulation time 14967640 ps
CPU time 0.94 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:00 PM PDT 24
Peak memory 207204 kb
Host smart-20408f1e-f63e-42b6-a5b9-9626d21a7a93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889024932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.889024932
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2959577698
Short name T1111
Test name
Test status
Simulation time 51542539 ps
CPU time 0.9 seconds
Started Aug 14 04:35:53 PM PDT 24
Finished Aug 14 04:35:54 PM PDT 24
Peak memory 206976 kb
Host smart-90d2d417-de9a-49bf-b108-83b94e0d6348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959577698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2959577698
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2757141638
Short name T1051
Test name
Test status
Simulation time 16867302 ps
CPU time 1.08 seconds
Started Aug 14 04:35:54 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 207040 kb
Host smart-a82aa983-9df4-4803-a1dc-aa4e4e227dad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757141638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2757141638
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2485621007
Short name T1103
Test name
Test status
Simulation time 219314735 ps
CPU time 2.16 seconds
Started Aug 14 04:35:45 PM PDT 24
Finished Aug 14 04:35:47 PM PDT 24
Peak memory 215376 kb
Host smart-8b21c499-2d93-4b7a-a7fd-cfc601a72dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485621007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2485621007
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3147424389
Short name T1100
Test name
Test status
Simulation time 42664580 ps
CPU time 1.58 seconds
Started Aug 14 04:35:50 PM PDT 24
Finished Aug 14 04:35:52 PM PDT 24
Peak memory 207332 kb
Host smart-ec3b15c5-cc26-4b02-8ee0-744116e09043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147424389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3147424389
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4108192088
Short name T1050
Test name
Test status
Simulation time 66356851 ps
CPU time 1.33 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:00 PM PDT 24
Peak memory 215424 kb
Host smart-0e97e790-7213-43bd-9e80-fd43b634d04a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108192088 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.4108192088
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1104209065
Short name T271
Test name
Test status
Simulation time 12999973 ps
CPU time 0.94 seconds
Started Aug 14 04:35:50 PM PDT 24
Finished Aug 14 04:35:51 PM PDT 24
Peak memory 207112 kb
Host smart-21b33afc-529f-4c33-8211-7c1f1eb0a15c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104209065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1104209065
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2797510037
Short name T980
Test name
Test status
Simulation time 24592219 ps
CPU time 0.85 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:36:01 PM PDT 24
Peak memory 207060 kb
Host smart-dadaa8aa-8a9a-43d6-95c0-00928cfa74b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797510037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2797510037
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.539725982
Short name T290
Test name
Test status
Simulation time 81755554 ps
CPU time 1.34 seconds
Started Aug 14 04:35:44 PM PDT 24
Finished Aug 14 04:35:45 PM PDT 24
Peak memory 207268 kb
Host smart-fe0478ef-6449-4754-a77d-8637e4629bb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539725982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.539725982
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1836138826
Short name T1033
Test name
Test status
Simulation time 92764914 ps
CPU time 3.28 seconds
Started Aug 14 04:35:51 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 215228 kb
Host smart-3172152b-4635-4baa-a262-b2a750953fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836138826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1836138826
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.681087203
Short name T306
Test name
Test status
Simulation time 91746611 ps
CPU time 2.5 seconds
Started Aug 14 04:35:49 PM PDT 24
Finished Aug 14 04:35:51 PM PDT 24
Peak memory 207144 kb
Host smart-61f6a482-0a67-42ed-b1ed-a79e714776c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681087203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.681087203
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3722880968
Short name T1057
Test name
Test status
Simulation time 29259283 ps
CPU time 1.07 seconds
Started Aug 14 04:35:16 PM PDT 24
Finished Aug 14 04:35:17 PM PDT 24
Peak memory 207056 kb
Host smart-0a9db33d-4404-4ef2-93ce-e37073b81d71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722880968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3722880968
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1278812745
Short name T284
Test name
Test status
Simulation time 467663238 ps
CPU time 3.33 seconds
Started Aug 14 04:35:26 PM PDT 24
Finished Aug 14 04:35:29 PM PDT 24
Peak memory 207140 kb
Host smart-13ada54b-51cb-40e3-9bcc-57ed01addcce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278812745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1278812745
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1952027331
Short name T275
Test name
Test status
Simulation time 32967733 ps
CPU time 1 seconds
Started Aug 14 04:35:49 PM PDT 24
Finished Aug 14 04:35:50 PM PDT 24
Peak memory 207080 kb
Host smart-ecc3b742-1c08-4e8e-a8fe-90b3d8938c61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952027331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1952027331
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.291679281
Short name T1044
Test name
Test status
Simulation time 61327557 ps
CPU time 1.36 seconds
Started Aug 14 04:35:33 PM PDT 24
Finished Aug 14 04:35:34 PM PDT 24
Peak memory 215476 kb
Host smart-a7b1d6b6-bc38-404f-8354-f08ebf87f3af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291679281 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.291679281
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.4145897845
Short name T1010
Test name
Test status
Simulation time 14579482 ps
CPU time 0.96 seconds
Started Aug 14 04:35:16 PM PDT 24
Finished Aug 14 04:35:17 PM PDT 24
Peak memory 207076 kb
Host smart-1d606167-d5f0-46ff-b40c-e83846e2d657
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145897845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.4145897845
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1380001104
Short name T1048
Test name
Test status
Simulation time 28164918 ps
CPU time 0.86 seconds
Started Aug 14 04:35:24 PM PDT 24
Finished Aug 14 04:35:25 PM PDT 24
Peak memory 207056 kb
Host smart-f8a80950-b1c4-4ff4-bf96-ec683986e991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380001104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1380001104
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3230652390
Short name T1067
Test name
Test status
Simulation time 77697351 ps
CPU time 1.06 seconds
Started Aug 14 04:35:40 PM PDT 24
Finished Aug 14 04:35:42 PM PDT 24
Peak memory 207260 kb
Host smart-edb684a0-cc77-4177-bf00-66c89f187c2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230652390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3230652390
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2347847589
Short name T1046
Test name
Test status
Simulation time 110564597 ps
CPU time 4.04 seconds
Started Aug 14 04:35:43 PM PDT 24
Finished Aug 14 04:35:47 PM PDT 24
Peak memory 215424 kb
Host smart-5bfc730a-a9a9-4dbd-b3e1-46bc5f8a414b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347847589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2347847589
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1164240188
Short name T297
Test name
Test status
Simulation time 668069098 ps
CPU time 4.45 seconds
Started Aug 14 04:35:18 PM PDT 24
Finished Aug 14 04:35:22 PM PDT 24
Peak memory 207348 kb
Host smart-84768175-29d1-4c43-9f99-2cbc391111ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164240188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1164240188
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2739127247
Short name T995
Test name
Test status
Simulation time 13716233 ps
CPU time 0.93 seconds
Started Aug 14 04:35:51 PM PDT 24
Finished Aug 14 04:35:52 PM PDT 24
Peak memory 206836 kb
Host smart-d8dd9667-533b-4ce4-aa55-f5519fb3d8cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739127247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2739127247
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2641271849
Short name T993
Test name
Test status
Simulation time 25678380 ps
CPU time 0.86 seconds
Started Aug 14 04:35:48 PM PDT 24
Finished Aug 14 04:35:49 PM PDT 24
Peak memory 207060 kb
Host smart-b6ed3a52-67a0-420f-81e6-06bb6011537b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641271849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2641271849
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.504116218
Short name T1021
Test name
Test status
Simulation time 72983387 ps
CPU time 0.9 seconds
Started Aug 14 04:35:54 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 207072 kb
Host smart-510cdd7a-f656-477a-b2b8-eb7c02bc71c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504116218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.504116218
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2890066458
Short name T1096
Test name
Test status
Simulation time 13469791 ps
CPU time 0.88 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:00 PM PDT 24
Peak memory 207060 kb
Host smart-bb26f4ac-649d-4369-9b1c-23aa1db8b081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890066458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2890066458
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1080771138
Short name T992
Test name
Test status
Simulation time 21038949 ps
CPU time 0.84 seconds
Started Aug 14 04:35:53 PM PDT 24
Finished Aug 14 04:35:54 PM PDT 24
Peak memory 207068 kb
Host smart-50b45b92-3e57-414c-bd59-54ab91d497fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080771138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1080771138
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.4009800407
Short name T1003
Test name
Test status
Simulation time 13863649 ps
CPU time 0.86 seconds
Started Aug 14 04:36:01 PM PDT 24
Finished Aug 14 04:36:12 PM PDT 24
Peak memory 206980 kb
Host smart-fae3064f-0990-41ab-9ee2-2f67fc29bc8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009800407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.4009800407
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.30185763
Short name T1069
Test name
Test status
Simulation time 13728992 ps
CPU time 0.86 seconds
Started Aug 14 04:35:36 PM PDT 24
Finished Aug 14 04:35:37 PM PDT 24
Peak memory 206984 kb
Host smart-2f94895d-904f-4fe6-bed6-cea9baa35da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30185763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.30185763
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3097907759
Short name T986
Test name
Test status
Simulation time 14609220 ps
CPU time 0.87 seconds
Started Aug 14 04:35:54 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 206844 kb
Host smart-b7d35dc1-afc5-456d-a73f-19f4baae7fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097907759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3097907759
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.4192937487
Short name T1009
Test name
Test status
Simulation time 12323562 ps
CPU time 0.85 seconds
Started Aug 14 04:36:17 PM PDT 24
Finished Aug 14 04:36:17 PM PDT 24
Peak memory 206984 kb
Host smart-0fcf1fb6-f9d1-44f2-8d87-e76e4942692d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192937487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.4192937487
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1094271942
Short name T1006
Test name
Test status
Simulation time 26913358 ps
CPU time 0.9 seconds
Started Aug 14 04:35:49 PM PDT 24
Finished Aug 14 04:35:50 PM PDT 24
Peak memory 207044 kb
Host smart-d34629ec-9f6f-44df-9eef-61c424acfbfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094271942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1094271942
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3106005619
Short name T1083
Test name
Test status
Simulation time 26530212 ps
CPU time 1.24 seconds
Started Aug 14 04:35:49 PM PDT 24
Finished Aug 14 04:35:51 PM PDT 24
Peak memory 207068 kb
Host smart-700fb73d-9aff-4bba-8121-bc364a28ed93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106005619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3106005619
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1937240196
Short name T1024
Test name
Test status
Simulation time 136006651 ps
CPU time 3.61 seconds
Started Aug 14 04:35:50 PM PDT 24
Finished Aug 14 04:35:53 PM PDT 24
Peak memory 207128 kb
Host smart-4725c89e-3a25-4b3a-ac8b-57f39b2031f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937240196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1937240196
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.4240723955
Short name T280
Test name
Test status
Simulation time 37325440 ps
CPU time 0.81 seconds
Started Aug 14 04:35:34 PM PDT 24
Finished Aug 14 04:35:35 PM PDT 24
Peak memory 207136 kb
Host smart-aa6f6298-81a7-4640-aacc-f148f0c58b72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240723955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.4240723955
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2258357852
Short name T1072
Test name
Test status
Simulation time 259481856 ps
CPU time 1.38 seconds
Started Aug 14 04:35:17 PM PDT 24
Finished Aug 14 04:35:19 PM PDT 24
Peak memory 215516 kb
Host smart-96b3d7c8-d341-42d4-996b-ad5fc2ee245c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258357852 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2258357852
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1472563942
Short name T272
Test name
Test status
Simulation time 12957074 ps
CPU time 0.89 seconds
Started Aug 14 04:35:18 PM PDT 24
Finished Aug 14 04:35:19 PM PDT 24
Peak memory 207204 kb
Host smart-484bd651-5298-4675-84e9-4693c23e223b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472563942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1472563942
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2280968312
Short name T1077
Test name
Test status
Simulation time 39823323 ps
CPU time 0.85 seconds
Started Aug 14 04:35:18 PM PDT 24
Finished Aug 14 04:35:19 PM PDT 24
Peak memory 206808 kb
Host smart-98650807-583c-4a36-860c-5e4ce56d36dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280968312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2280968312
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1708732793
Short name T246
Test name
Test status
Simulation time 128459259 ps
CPU time 1.45 seconds
Started Aug 14 04:35:20 PM PDT 24
Finished Aug 14 04:35:22 PM PDT 24
Peak memory 207176 kb
Host smart-74b3244e-468a-4b00-af1c-a353674f2f37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708732793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1708732793
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3039120490
Short name T1109
Test name
Test status
Simulation time 54238206 ps
CPU time 1.87 seconds
Started Aug 14 04:35:21 PM PDT 24
Finished Aug 14 04:35:22 PM PDT 24
Peak memory 219476 kb
Host smart-3fe75d59-ca2c-4a67-b7b3-a8a5ab694cb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039120490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3039120490
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.841106060
Short name T304
Test name
Test status
Simulation time 990587729 ps
CPU time 2.02 seconds
Started Aug 14 04:35:19 PM PDT 24
Finished Aug 14 04:35:21 PM PDT 24
Peak memory 215396 kb
Host smart-8824df70-117e-4fac-815c-cd0af43edadc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841106060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.841106060
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3085686133
Short name T1004
Test name
Test status
Simulation time 14309321 ps
CPU time 0.85 seconds
Started Aug 14 04:36:00 PM PDT 24
Finished Aug 14 04:36:01 PM PDT 24
Peak memory 206976 kb
Host smart-cd0c8b10-a5b4-4ab4-b7c5-ab3246a49f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085686133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3085686133
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.879636741
Short name T1002
Test name
Test status
Simulation time 15078859 ps
CPU time 0.89 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:00 PM PDT 24
Peak memory 207048 kb
Host smart-646e2940-911e-4427-8609-2930bf46cfe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879636741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.879636741
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3382245849
Short name T1092
Test name
Test status
Simulation time 37441331 ps
CPU time 0.83 seconds
Started Aug 14 04:35:58 PM PDT 24
Finished Aug 14 04:35:59 PM PDT 24
Peak memory 206976 kb
Host smart-d9dd063e-9fa9-4249-8b18-e65485842ad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382245849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3382245849
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3059147249
Short name T1108
Test name
Test status
Simulation time 16188974 ps
CPU time 0.91 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:36:01 PM PDT 24
Peak memory 207124 kb
Host smart-dc82ad9b-f138-4cd4-87f4-9ebbfc9a1dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059147249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3059147249
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2955168589
Short name T1078
Test name
Test status
Simulation time 83019766 ps
CPU time 0.9 seconds
Started Aug 14 04:35:48 PM PDT 24
Finished Aug 14 04:35:49 PM PDT 24
Peak memory 207040 kb
Host smart-5a7cf5e3-b5c1-49fa-b884-bc728ea4db88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955168589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2955168589
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3804811225
Short name T1113
Test name
Test status
Simulation time 38180139 ps
CPU time 0.85 seconds
Started Aug 14 04:36:01 PM PDT 24
Finished Aug 14 04:36:02 PM PDT 24
Peak memory 206840 kb
Host smart-e55f143a-c087-4a34-9baf-598bbcf0a7da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804811225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3804811225
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.569588415
Short name T985
Test name
Test status
Simulation time 45554046 ps
CPU time 0.87 seconds
Started Aug 14 04:35:59 PM PDT 24
Finished Aug 14 04:36:00 PM PDT 24
Peak memory 207060 kb
Host smart-a0a417d7-e718-4a7d-a781-be7d4af45f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569588415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.569588415
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1320051829
Short name T1114
Test name
Test status
Simulation time 15977035 ps
CPU time 0.98 seconds
Started Aug 14 04:35:48 PM PDT 24
Finished Aug 14 04:35:49 PM PDT 24
Peak memory 207012 kb
Host smart-7064ae76-c102-4abb-b4a8-9d7eb0ed1f76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320051829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1320051829
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3105986953
Short name T1000
Test name
Test status
Simulation time 15958973 ps
CPU time 0.86 seconds
Started Aug 14 04:35:54 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 207012 kb
Host smart-1e5cd131-b791-4be9-b30a-6694e84bd3d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105986953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3105986953
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1426428098
Short name T1054
Test name
Test status
Simulation time 31977597 ps
CPU time 0.84 seconds
Started Aug 14 04:35:52 PM PDT 24
Finished Aug 14 04:35:53 PM PDT 24
Peak memory 206764 kb
Host smart-0c68b90b-5233-4468-b2d8-079b4b9859ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426428098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1426428098
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1644985819
Short name T274
Test name
Test status
Simulation time 69597342 ps
CPU time 1.21 seconds
Started Aug 14 04:35:22 PM PDT 24
Finished Aug 14 04:35:23 PM PDT 24
Peak memory 207192 kb
Host smart-879afc12-07a0-4aef-948c-ab9a79f8d02e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644985819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1644985819
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1804926484
Short name T1097
Test name
Test status
Simulation time 508935927 ps
CPU time 6.39 seconds
Started Aug 14 04:35:20 PM PDT 24
Finished Aug 14 04:35:26 PM PDT 24
Peak memory 207108 kb
Host smart-c8123c4c-943c-43cc-8473-c2436addbcc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804926484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1804926484
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2024078007
Short name T1001
Test name
Test status
Simulation time 16458641 ps
CPU time 0.91 seconds
Started Aug 14 04:35:18 PM PDT 24
Finished Aug 14 04:35:19 PM PDT 24
Peak memory 207040 kb
Host smart-aca1ac61-8a0f-478f-a775-f157e1ad7d70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024078007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2024078007
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1009821619
Short name T1090
Test name
Test status
Simulation time 31272135 ps
CPU time 1.34 seconds
Started Aug 14 04:35:20 PM PDT 24
Finished Aug 14 04:35:22 PM PDT 24
Peak memory 217404 kb
Host smart-e3cbc115-5e73-46c9-9be6-58bab2aa3727
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009821619 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1009821619
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.11432465
Short name T279
Test name
Test status
Simulation time 28669900 ps
CPU time 0.84 seconds
Started Aug 14 04:35:19 PM PDT 24
Finished Aug 14 04:35:20 PM PDT 24
Peak memory 207120 kb
Host smart-3c8395a7-c096-43d1-90bb-b45e16f14d04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11432465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.11432465
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1128158997
Short name T1106
Test name
Test status
Simulation time 23777111 ps
CPU time 0.84 seconds
Started Aug 14 04:35:17 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 206892 kb
Host smart-b23afbae-4b0f-4b54-9e9c-eb9cf5ccf750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128158997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1128158997
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2314968326
Short name T1085
Test name
Test status
Simulation time 19377849 ps
CPU time 1.06 seconds
Started Aug 14 04:36:06 PM PDT 24
Finished Aug 14 04:36:07 PM PDT 24
Peak memory 207116 kb
Host smart-c385a995-6f13-46e1-b3ec-ca8c5c25f7b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314968326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2314968326
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1663459621
Short name T1042
Test name
Test status
Simulation time 2299036662 ps
CPU time 4.48 seconds
Started Aug 14 04:35:29 PM PDT 24
Finished Aug 14 04:35:34 PM PDT 24
Peak memory 215472 kb
Host smart-46378fdc-1f76-4aa1-a7e7-190776fd6cba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663459621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1663459621
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.529579137
Short name T1015
Test name
Test status
Simulation time 778545788 ps
CPU time 1.59 seconds
Started Aug 14 04:35:42 PM PDT 24
Finished Aug 14 04:35:44 PM PDT 24
Peak memory 207196 kb
Host smart-ddb14ff6-e731-48b5-847c-b7a637c8a885
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529579137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.529579137
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.135036890
Short name T996
Test name
Test status
Simulation time 23953213 ps
CPU time 0.85 seconds
Started Aug 14 04:35:52 PM PDT 24
Finished Aug 14 04:35:53 PM PDT 24
Peak memory 206908 kb
Host smart-ed33cbe4-e335-4ff7-a59a-65b003c1f1ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135036890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.135036890
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1208218489
Short name T1043
Test name
Test status
Simulation time 63031167 ps
CPU time 0.81 seconds
Started Aug 14 04:36:01 PM PDT 24
Finished Aug 14 04:36:02 PM PDT 24
Peak memory 207028 kb
Host smart-ce493c54-cc96-4d6a-950b-0cd202d75a66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208218489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1208218489
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2587295159
Short name T1107
Test name
Test status
Simulation time 21081756 ps
CPU time 0.84 seconds
Started Aug 14 04:35:58 PM PDT 24
Finished Aug 14 04:35:59 PM PDT 24
Peak memory 206896 kb
Host smart-96a3d76e-b295-441a-959d-c85c0bf0c7f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587295159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2587295159
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1870490646
Short name T1088
Test name
Test status
Simulation time 35306106 ps
CPU time 0.85 seconds
Started Aug 14 04:35:51 PM PDT 24
Finished Aug 14 04:35:52 PM PDT 24
Peak memory 207004 kb
Host smart-ec978399-1da8-4748-9520-64490ec43c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870490646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1870490646
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3627088938
Short name T1007
Test name
Test status
Simulation time 16120345 ps
CPU time 0.95 seconds
Started Aug 14 04:36:05 PM PDT 24
Finished Aug 14 04:36:06 PM PDT 24
Peak memory 207056 kb
Host smart-bdcce4e0-5902-4b2c-a53d-6a59fdefbc90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627088938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3627088938
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3623748465
Short name T1062
Test name
Test status
Simulation time 18899928 ps
CPU time 0.97 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:35:57 PM PDT 24
Peak memory 207024 kb
Host smart-7e5d233b-bc2d-48e9-8031-4e7bc094d4ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623748465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3623748465
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3268811694
Short name T1038
Test name
Test status
Simulation time 12620728 ps
CPU time 0.8 seconds
Started Aug 14 04:35:48 PM PDT 24
Finished Aug 14 04:35:49 PM PDT 24
Peak memory 207072 kb
Host smart-69e70c6b-2256-4c48-9ed8-e587be04348a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268811694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3268811694
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2123243505
Short name T1029
Test name
Test status
Simulation time 23177003 ps
CPU time 0.87 seconds
Started Aug 14 04:35:52 PM PDT 24
Finished Aug 14 04:35:53 PM PDT 24
Peak memory 207060 kb
Host smart-20dbaa81-f8db-4706-a993-781b50f62dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123243505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2123243505
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2291956918
Short name T1064
Test name
Test status
Simulation time 23472500 ps
CPU time 0.83 seconds
Started Aug 14 04:35:57 PM PDT 24
Finished Aug 14 04:35:58 PM PDT 24
Peak memory 206976 kb
Host smart-24fffbf2-f54c-4488-8283-0f11a2211410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291956918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2291956918
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3194108827
Short name T999
Test name
Test status
Simulation time 30684595 ps
CPU time 0.82 seconds
Started Aug 14 04:35:57 PM PDT 24
Finished Aug 14 04:35:57 PM PDT 24
Peak memory 206816 kb
Host smart-2e433811-9bb0-4d76-a45e-676487a559d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194108827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3194108827
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.298564954
Short name T1068
Test name
Test status
Simulation time 43779688 ps
CPU time 1.17 seconds
Started Aug 14 04:35:20 PM PDT 24
Finished Aug 14 04:35:21 PM PDT 24
Peak memory 215524 kb
Host smart-0cd90cf8-bb87-4ea1-ad98-08faf762b9cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298564954 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.298564954
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2162156328
Short name T1045
Test name
Test status
Simulation time 16835988 ps
CPU time 0.93 seconds
Started Aug 14 04:35:19 PM PDT 24
Finished Aug 14 04:35:20 PM PDT 24
Peak memory 207136 kb
Host smart-e88ed942-3d61-49f8-aedb-774507627f98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162156328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2162156328
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1179743290
Short name T1030
Test name
Test status
Simulation time 37177120 ps
CPU time 0.79 seconds
Started Aug 14 04:35:21 PM PDT 24
Finished Aug 14 04:35:22 PM PDT 24
Peak memory 206904 kb
Host smart-3878ddc3-bba5-404d-bd74-729eb6c1aede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179743290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1179743290
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.849182095
Short name T1023
Test name
Test status
Simulation time 75893633 ps
CPU time 0.95 seconds
Started Aug 14 04:35:30 PM PDT 24
Finished Aug 14 04:35:31 PM PDT 24
Peak memory 207152 kb
Host smart-6b9df89d-9e96-436c-b2f4-10f3af0527de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849182095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.849182095
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2645656326
Short name T1055
Test name
Test status
Simulation time 97771093 ps
CPU time 3.18 seconds
Started Aug 14 04:35:18 PM PDT 24
Finished Aug 14 04:35:21 PM PDT 24
Peak memory 223552 kb
Host smart-88ae88f2-8e5a-4477-8675-ff44cc507aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645656326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2645656326
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.352814346
Short name T305
Test name
Test status
Simulation time 101482992 ps
CPU time 2.6 seconds
Started Aug 14 04:35:20 PM PDT 24
Finished Aug 14 04:35:23 PM PDT 24
Peak memory 207044 kb
Host smart-d5e630b6-4bc4-4f11-9fd2-a19e757ef453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352814346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.352814346
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1385744584
Short name T1087
Test name
Test status
Simulation time 32503718 ps
CPU time 1.18 seconds
Started Aug 14 04:35:37 PM PDT 24
Finished Aug 14 04:35:38 PM PDT 24
Peak memory 215532 kb
Host smart-bd3b79b8-e87f-48a6-bf36-12dfa7b53e4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385744584 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1385744584
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.713601820
Short name T1052
Test name
Test status
Simulation time 12156823 ps
CPU time 0.87 seconds
Started Aug 14 04:35:48 PM PDT 24
Finished Aug 14 04:35:49 PM PDT 24
Peak memory 207064 kb
Host smart-f43203ef-c765-4490-8b70-546a61a04ad6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713601820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.713601820
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3032343002
Short name T1020
Test name
Test status
Simulation time 20765163 ps
CPU time 0.87 seconds
Started Aug 14 04:35:49 PM PDT 24
Finished Aug 14 04:35:50 PM PDT 24
Peak memory 207080 kb
Host smart-efcaa934-a8d5-45ac-9510-31a300d6a25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032343002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3032343002
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1742837157
Short name T1034
Test name
Test status
Simulation time 30901018 ps
CPU time 1.27 seconds
Started Aug 14 04:35:37 PM PDT 24
Finished Aug 14 04:35:38 PM PDT 24
Peak memory 207208 kb
Host smart-af2f7752-fb6f-43a7-86e1-a9b962eb123d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742837157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1742837157
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2239418293
Short name T988
Test name
Test status
Simulation time 103399792 ps
CPU time 3.84 seconds
Started Aug 14 04:35:39 PM PDT 24
Finished Aug 14 04:35:43 PM PDT 24
Peak memory 215384 kb
Host smart-fbd892b0-c7ff-411c-a557-9b9b01b8f609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239418293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2239418293
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2726903959
Short name T1025
Test name
Test status
Simulation time 256192966 ps
CPU time 2.24 seconds
Started Aug 14 04:35:58 PM PDT 24
Finished Aug 14 04:36:00 PM PDT 24
Peak memory 215424 kb
Host smart-40fb5a59-cf4c-4326-a629-32eab9185325
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726903959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2726903959
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2664191893
Short name T1022
Test name
Test status
Simulation time 200817250 ps
CPU time 1.2 seconds
Started Aug 14 04:35:55 PM PDT 24
Finished Aug 14 04:35:57 PM PDT 24
Peak memory 215372 kb
Host smart-474e1fb5-8f1d-45ba-900a-9ddb4be3c3a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664191893 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2664191893
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1649991094
Short name T270
Test name
Test status
Simulation time 37279738 ps
CPU time 0.85 seconds
Started Aug 14 04:35:32 PM PDT 24
Finished Aug 14 04:35:33 PM PDT 24
Peak memory 207056 kb
Host smart-00f1140b-e1dc-43cc-b386-30f7744a4a73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649991094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1649991094
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.339878111
Short name T1005
Test name
Test status
Simulation time 41079532 ps
CPU time 0.85 seconds
Started Aug 14 04:35:44 PM PDT 24
Finished Aug 14 04:35:45 PM PDT 24
Peak memory 207244 kb
Host smart-6b84ca0a-c60b-434d-951b-79c2ccf477c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339878111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.339878111
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2417923920
Short name T1091
Test name
Test status
Simulation time 121636269 ps
CPU time 1.42 seconds
Started Aug 14 04:36:01 PM PDT 24
Finished Aug 14 04:36:02 PM PDT 24
Peak memory 207196 kb
Host smart-daaf697f-58ce-4ee9-9c5f-1f8a8f2cb70d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417923920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2417923920
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.834368710
Short name T1011
Test name
Test status
Simulation time 75232940 ps
CPU time 2.59 seconds
Started Aug 14 04:35:52 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 215312 kb
Host smart-d375ecad-a6c0-4499-9f5c-4bc876d3a39e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834368710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.834368710
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3309635227
Short name T1066
Test name
Test status
Simulation time 296117915 ps
CPU time 2.34 seconds
Started Aug 14 04:35:52 PM PDT 24
Finished Aug 14 04:35:55 PM PDT 24
Peak memory 207064 kb
Host smart-dac55920-b5c9-46f1-9dda-7d7538ab0a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309635227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3309635227
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3221409773
Short name T1056
Test name
Test status
Simulation time 32028880 ps
CPU time 1.44 seconds
Started Aug 14 04:35:41 PM PDT 24
Finished Aug 14 04:35:43 PM PDT 24
Peak memory 218200 kb
Host smart-c72e30bb-8b90-4650-a43c-60e8c89ae25a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221409773 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3221409773
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2773042849
Short name T286
Test name
Test status
Simulation time 13590251 ps
CPU time 0.9 seconds
Started Aug 14 04:35:38 PM PDT 24
Finished Aug 14 04:35:39 PM PDT 24
Peak memory 207120 kb
Host smart-7811e725-154c-482d-94fa-608b173fb59c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773042849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2773042849
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2106850934
Short name T1019
Test name
Test status
Simulation time 89303318 ps
CPU time 0.83 seconds
Started Aug 14 04:35:57 PM PDT 24
Finished Aug 14 04:35:58 PM PDT 24
Peak memory 206840 kb
Host smart-d2ff237c-7d34-438b-a0a8-8521d34bb4c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106850934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2106850934
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1484133041
Short name T1047
Test name
Test status
Simulation time 52647615 ps
CPU time 1.11 seconds
Started Aug 14 04:35:44 PM PDT 24
Finished Aug 14 04:35:45 PM PDT 24
Peak memory 207092 kb
Host smart-70178a1f-596b-4942-8d69-ddea3636063e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484133041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1484133041
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3896905692
Short name T982
Test name
Test status
Simulation time 265821985 ps
CPU time 2.73 seconds
Started Aug 14 04:35:48 PM PDT 24
Finished Aug 14 04:35:51 PM PDT 24
Peak memory 215384 kb
Host smart-ce5107ea-de26-41e0-8546-8c419264a92d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896905692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3896905692
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2863170397
Short name T1058
Test name
Test status
Simulation time 371071541 ps
CPU time 2.23 seconds
Started Aug 14 04:35:56 PM PDT 24
Finished Aug 14 04:35:58 PM PDT 24
Peak memory 207268 kb
Host smart-f9d23521-2afc-4e7b-98d1-7ab65ef97599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863170397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2863170397
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.293340894
Short name T1041
Test name
Test status
Simulation time 93060846 ps
CPU time 1.39 seconds
Started Aug 14 04:35:42 PM PDT 24
Finished Aug 14 04:35:44 PM PDT 24
Peak memory 215372 kb
Host smart-71ae1e59-03fc-4c2d-8111-1d98b3e70f5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293340894 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.293340894
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2377090466
Short name T288
Test name
Test status
Simulation time 32313390 ps
CPU time 0.87 seconds
Started Aug 14 04:35:35 PM PDT 24
Finished Aug 14 04:35:36 PM PDT 24
Peak memory 207188 kb
Host smart-06e7ced9-dccc-4129-b5d1-b35a45811c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377090466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2377090466
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.497025446
Short name T1105
Test name
Test status
Simulation time 29040758 ps
CPU time 0.94 seconds
Started Aug 14 04:35:48 PM PDT 24
Finished Aug 14 04:35:49 PM PDT 24
Peak memory 206980 kb
Host smart-3848fb33-fab5-41e3-89d3-d406045943ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497025446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.497025446
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2933416209
Short name T1013
Test name
Test status
Simulation time 52906989 ps
CPU time 0.96 seconds
Started Aug 14 04:35:29 PM PDT 24
Finished Aug 14 04:35:30 PM PDT 24
Peak memory 207120 kb
Host smart-59f9a3f2-f7d9-46d1-8005-470d57110737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933416209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2933416209
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.69937564
Short name T1008
Test name
Test status
Simulation time 102965955 ps
CPU time 2.08 seconds
Started Aug 14 04:35:29 PM PDT 24
Finished Aug 14 04:35:31 PM PDT 24
Peak memory 215376 kb
Host smart-606729fa-cf74-4895-8918-38d1a88c4e2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69937564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.69937564
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/default/0.edn_alert_test.3008024976
Short name T861
Test name
Test status
Simulation time 45904257 ps
CPU time 0.89 seconds
Started Aug 14 05:31:55 PM PDT 24
Finished Aug 14 05:31:56 PM PDT 24
Peak memory 207124 kb
Host smart-937f1e23-ff2d-416a-b897-cf50b3702d28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008024976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3008024976
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2183804608
Short name T594
Test name
Test status
Simulation time 26049780 ps
CPU time 0.91 seconds
Started Aug 14 05:32:09 PM PDT 24
Finished Aug 14 05:32:10 PM PDT 24
Peak memory 216716 kb
Host smart-75396bab-9149-40dc-8ea4-a990dfde3ca8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183804608 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2183804608
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1858049744
Short name T615
Test name
Test status
Simulation time 33748695 ps
CPU time 1.17 seconds
Started Aug 14 05:31:57 PM PDT 24
Finished Aug 14 05:31:58 PM PDT 24
Peak memory 217196 kb
Host smart-df1d8f35-0dab-496b-a6f8-5e0ead7e77f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858049744 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1858049744
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1911860574
Short name T7
Test name
Test status
Simulation time 34810126 ps
CPU time 1.05 seconds
Started Aug 14 05:31:53 PM PDT 24
Finished Aug 14 05:31:54 PM PDT 24
Peak memory 218972 kb
Host smart-edfae44d-faf3-4122-92c8-88d2808dd1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911860574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1911860574
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.336715274
Short name T263
Test name
Test status
Simulation time 26468599 ps
CPU time 0.94 seconds
Started Aug 14 05:31:55 PM PDT 24
Finished Aug 14 05:31:56 PM PDT 24
Peak memory 215800 kb
Host smart-da8a1aec-d2f5-404c-b2c0-ec78ddaf4365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336715274 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.336715274
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_smoke.91738856
Short name T686
Test name
Test status
Simulation time 16496027 ps
CPU time 0.98 seconds
Started Aug 14 05:32:00 PM PDT 24
Finished Aug 14 05:32:01 PM PDT 24
Peak memory 215640 kb
Host smart-d52bcaf8-15c3-4a76-bec4-66447dcc79d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91738856 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.91738856
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.899320914
Short name T577
Test name
Test status
Simulation time 106824568 ps
CPU time 1.75 seconds
Started Aug 14 05:31:50 PM PDT 24
Finished Aug 14 05:31:53 PM PDT 24
Peak memory 217656 kb
Host smart-0e94c7ea-c348-47b1-bc3d-e5fb340b4f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899320914 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.899320914
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert_test.2776341048
Short name T378
Test name
Test status
Simulation time 17672053 ps
CPU time 0.97 seconds
Started Aug 14 05:31:55 PM PDT 24
Finished Aug 14 05:31:56 PM PDT 24
Peak memory 207116 kb
Host smart-e59c370a-10f5-4ea6-b430-9658359c7de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776341048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2776341048
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1385596075
Short name T897
Test name
Test status
Simulation time 60598480 ps
CPU time 1.15 seconds
Started Aug 14 05:32:00 PM PDT 24
Finished Aug 14 05:32:01 PM PDT 24
Peak memory 217168 kb
Host smart-bca896e1-5a5d-4fa7-8354-92f10f08b43f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385596075 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1385596075
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.49568885
Short name T531
Test name
Test status
Simulation time 18998822 ps
CPU time 1.06 seconds
Started Aug 14 05:32:03 PM PDT 24
Finished Aug 14 05:32:04 PM PDT 24
Peak memory 218656 kb
Host smart-559f2209-a7ff-460e-828d-92ee34f02043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49568885 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.49568885
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2294438159
Short name T761
Test name
Test status
Simulation time 58302037 ps
CPU time 1.56 seconds
Started Aug 14 05:31:50 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 218932 kb
Host smart-820280eb-0783-43ab-add4-9852a0eb347c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294438159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2294438159
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1622768570
Short name T114
Test name
Test status
Simulation time 28777739 ps
CPU time 0.87 seconds
Started Aug 14 05:31:59 PM PDT 24
Finished Aug 14 05:32:00 PM PDT 24
Peak memory 216056 kb
Host smart-3256ab66-af94-4a31-8c9a-b0b8d1c07cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622768570 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1622768570
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.852622398
Short name T33
Test name
Test status
Simulation time 22375699 ps
CPU time 1 seconds
Started Aug 14 05:31:50 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 207432 kb
Host smart-b4a42110-a3f3-4963-a882-9a8e53648d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852622398 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.852622398
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3501376803
Short name T69
Test name
Test status
Simulation time 1701282371 ps
CPU time 7.51 seconds
Started Aug 14 05:32:00 PM PDT 24
Finished Aug 14 05:32:08 PM PDT 24
Peak memory 240632 kb
Host smart-6af48ffd-85f6-4955-bfa3-737c2bbb7dff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501376803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3501376803
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.260598969
Short name T943
Test name
Test status
Simulation time 18138503 ps
CPU time 1.02 seconds
Started Aug 14 05:31:50 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 207416 kb
Host smart-9a9f5af3-311e-4c08-b793-6c8155f8e5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260598969 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.260598969
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_alert.3709236743
Short name T712
Test name
Test status
Simulation time 22231364 ps
CPU time 1.13 seconds
Started Aug 14 05:32:15 PM PDT 24
Finished Aug 14 05:32:16 PM PDT 24
Peak memory 219936 kb
Host smart-891adf5b-bee6-4dfb-9a18-43fb528d9e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709236743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3709236743
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.973836695
Short name T624
Test name
Test status
Simulation time 16308193 ps
CPU time 1 seconds
Started Aug 14 05:32:12 PM PDT 24
Finished Aug 14 05:32:13 PM PDT 24
Peak memory 215280 kb
Host smart-e9e1ea86-0f8a-4d01-aa37-fdf8d65c6ff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973836695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.973836695
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2459976136
Short name T590
Test name
Test status
Simulation time 18379425 ps
CPU time 0.9 seconds
Started Aug 14 05:32:07 PM PDT 24
Finished Aug 14 05:32:08 PM PDT 24
Peak memory 216684 kb
Host smart-b06817c0-e2b3-4036-89a9-ae5b48b17ea2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459976136 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2459976136
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3722871988
Short name T528
Test name
Test status
Simulation time 69704472 ps
CPU time 1.09 seconds
Started Aug 14 05:32:09 PM PDT 24
Finished Aug 14 05:32:11 PM PDT 24
Peak memory 218888 kb
Host smart-30f17b5c-d387-4277-98cb-5005e523aecd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722871988 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3722871988
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3511662356
Short name T653
Test name
Test status
Simulation time 26559086 ps
CPU time 0.89 seconds
Started Aug 14 05:32:18 PM PDT 24
Finished Aug 14 05:32:19 PM PDT 24
Peak memory 218256 kb
Host smart-eeec753c-07ac-4f50-8655-deecbbf53148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511662356 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3511662356
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3916582027
Short name T398
Test name
Test status
Simulation time 56039564 ps
CPU time 1.19 seconds
Started Aug 14 05:32:08 PM PDT 24
Finished Aug 14 05:32:10 PM PDT 24
Peak memory 218996 kb
Host smart-5f5b8065-78d7-45ab-81d2-346ab0cc400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916582027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3916582027
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.543328310
Short name T978
Test name
Test status
Simulation time 36916543 ps
CPU time 0.89 seconds
Started Aug 14 05:32:10 PM PDT 24
Finished Aug 14 05:32:11 PM PDT 24
Peak memory 215796 kb
Host smart-00be40c6-6bd5-4531-b08a-f61aa8fa6068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543328310 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.543328310
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.645124795
Short name T791
Test name
Test status
Simulation time 114405227 ps
CPU time 0.98 seconds
Started Aug 14 05:32:14 PM PDT 24
Finished Aug 14 05:32:15 PM PDT 24
Peak memory 215644 kb
Host smart-17df991c-10fd-46f1-a9cc-94241d853dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645124795 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.645124795
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3650022937
Short name T373
Test name
Test status
Simulation time 603439853 ps
CPU time 2.86 seconds
Started Aug 14 05:32:07 PM PDT 24
Finished Aug 14 05:32:11 PM PDT 24
Peak memory 215612 kb
Host smart-3ddff116-15b9-4419-9152-f1ab65f8b315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650022937 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3650022937
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1340271006
Short name T779
Test name
Test status
Simulation time 25548010519 ps
CPU time 63.98 seconds
Started Aug 14 05:32:08 PM PDT 24
Finished Aug 14 05:33:13 PM PDT 24
Peak memory 220156 kb
Host smart-564cbbd9-d560-4307-8e9b-f019bf25b00e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340271006 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1340271006
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.2607093074
Short name T912
Test name
Test status
Simulation time 31063911 ps
CPU time 1.32 seconds
Started Aug 14 05:33:31 PM PDT 24
Finished Aug 14 05:33:32 PM PDT 24
Peak memory 220884 kb
Host smart-58d50c7e-b478-47d0-b72e-88d09beb4db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607093074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2607093074
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.2730901173
Short name T95
Test name
Test status
Simulation time 39108027 ps
CPU time 1.22 seconds
Started Aug 14 05:33:50 PM PDT 24
Finished Aug 14 05:33:51 PM PDT 24
Peak memory 217564 kb
Host smart-221f4210-f89f-42ad-a625-690082652c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730901173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2730901173
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.738573649
Short name T445
Test name
Test status
Simulation time 231137722 ps
CPU time 1.2 seconds
Started Aug 14 05:33:26 PM PDT 24
Finished Aug 14 05:33:28 PM PDT 24
Peak memory 218960 kb
Host smart-d52c13e3-8b7e-4383-9f8e-ecf72e0fb328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738573649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.738573649
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.2745300128
Short name T743
Test name
Test status
Simulation time 33227463 ps
CPU time 1.28 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 218932 kb
Host smart-8e34cd84-c038-47f9-840a-3d55fca6e211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745300128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2745300128
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.1000065535
Short name T856
Test name
Test status
Simulation time 25098878 ps
CPU time 1.19 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:54 PM PDT 24
Peak memory 221212 kb
Host smart-4e48f513-eea8-483c-85f4-08b92468979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000065535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1000065535
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2605143160
Short name T395
Test name
Test status
Simulation time 84706433 ps
CPU time 1.14 seconds
Started Aug 14 05:33:42 PM PDT 24
Finished Aug 14 05:33:43 PM PDT 24
Peak memory 218800 kb
Host smart-c80e1294-77bf-4b25-989f-0f340fc04cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605143160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2605143160
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.136053725
Short name T697
Test name
Test status
Simulation time 67792655 ps
CPU time 1.14 seconds
Started Aug 14 05:33:30 PM PDT 24
Finished Aug 14 05:33:31 PM PDT 24
Peak memory 218836 kb
Host smart-d449e785-ba94-484a-b547-a61c2eacd94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136053725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.136053725
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.3241068371
Short name T459
Test name
Test status
Simulation time 80746067 ps
CPU time 1.33 seconds
Started Aug 14 05:33:54 PM PDT 24
Finished Aug 14 05:33:56 PM PDT 24
Peak memory 219060 kb
Host smart-77d0698a-4493-435a-a6b4-8b1b425214f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241068371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3241068371
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.1132624169
Short name T184
Test name
Test status
Simulation time 92633553 ps
CPU time 1.31 seconds
Started Aug 14 05:33:31 PM PDT 24
Finished Aug 14 05:33:32 PM PDT 24
Peak memory 220328 kb
Host smart-020d25fd-2ab1-494d-a18e-2937ac27e6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132624169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1132624169
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.1186713044
Short name T515
Test name
Test status
Simulation time 62243575 ps
CPU time 1.32 seconds
Started Aug 14 05:33:30 PM PDT 24
Finished Aug 14 05:33:32 PM PDT 24
Peak memory 217808 kb
Host smart-cb09abe6-fbce-4d95-bec3-ef54c475f4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186713044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1186713044
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.558490478
Short name T716
Test name
Test status
Simulation time 84474877 ps
CPU time 1.25 seconds
Started Aug 14 05:33:43 PM PDT 24
Finished Aug 14 05:33:45 PM PDT 24
Peak memory 220244 kb
Host smart-51dc5905-7e21-4562-94b5-8b83ac0bd40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558490478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.558490478
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.4274695481
Short name T566
Test name
Test status
Simulation time 54788003 ps
CPU time 1.26 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 219848 kb
Host smart-7d18e7e8-4a9e-4bf8-9366-5926b03dc87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274695481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.4274695481
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.1360316849
Short name T656
Test name
Test status
Simulation time 51943660 ps
CPU time 1.22 seconds
Started Aug 14 05:33:43 PM PDT 24
Finished Aug 14 05:33:44 PM PDT 24
Peak memory 221704 kb
Host smart-04e9bbb5-914a-4961-a4d9-431b94c95871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360316849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.1360316849
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.370214147
Short name T248
Test name
Test status
Simulation time 21308593 ps
CPU time 1.19 seconds
Started Aug 14 05:33:29 PM PDT 24
Finished Aug 14 05:33:30 PM PDT 24
Peak memory 218108 kb
Host smart-c3bfec3b-4da1-4cdc-8769-f5f08e3393c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370214147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.370214147
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3990666455
Short name T483
Test name
Test status
Simulation time 38647760 ps
CPU time 1.39 seconds
Started Aug 14 05:33:45 PM PDT 24
Finished Aug 14 05:33:46 PM PDT 24
Peak memory 218684 kb
Host smart-88bb3603-33fa-453f-8999-40ce58a92291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990666455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3990666455
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1632332888
Short name T642
Test name
Test status
Simulation time 48532018 ps
CPU time 1.25 seconds
Started Aug 14 05:33:48 PM PDT 24
Finished Aug 14 05:33:49 PM PDT 24
Peak memory 219052 kb
Host smart-e10814d4-2ae2-4c9b-a1dc-bd0bbfcd50d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632332888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1632332888
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.3257870017
Short name T348
Test name
Test status
Simulation time 57065118 ps
CPU time 1.1 seconds
Started Aug 14 05:33:50 PM PDT 24
Finished Aug 14 05:33:51 PM PDT 24
Peak memory 219720 kb
Host smart-1dbda9dd-342e-48ca-aa74-a25acc7ada46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257870017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3257870017
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.1532185003
Short name T679
Test name
Test status
Simulation time 36178619 ps
CPU time 1.11 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219840 kb
Host smart-2b7900ea-ff18-4315-9194-a6105988d748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532185003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.1532185003
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.147114374
Short name T394
Test name
Test status
Simulation time 150243871 ps
CPU time 1.04 seconds
Started Aug 14 05:33:29 PM PDT 24
Finished Aug 14 05:33:31 PM PDT 24
Peak memory 215516 kb
Host smart-b4619063-1cee-475a-965c-63b419d05f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147114374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.147114374
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2680987935
Short name T557
Test name
Test status
Simulation time 27017710 ps
CPU time 1.19 seconds
Started Aug 14 05:32:12 PM PDT 24
Finished Aug 14 05:32:13 PM PDT 24
Peak memory 219080 kb
Host smart-2c2c0e84-e90b-44cd-9998-8d4cfd9fd52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680987935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2680987935
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.2250623994
Short name T901
Test name
Test status
Simulation time 148723936 ps
CPU time 0.84 seconds
Started Aug 14 05:32:11 PM PDT 24
Finished Aug 14 05:32:12 PM PDT 24
Peak memory 216852 kb
Host smart-217b288a-461b-4e2b-b4c1-a567c1f5ed93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250623994 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2250623994
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_genbits.24584655
Short name T947
Test name
Test status
Simulation time 143188444 ps
CPU time 1.36 seconds
Started Aug 14 05:32:18 PM PDT 24
Finished Aug 14 05:32:20 PM PDT 24
Peak memory 218648 kb
Host smart-1919fab6-7848-493a-ae2c-48dcd9c98478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24584655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.24584655
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2325422709
Short name T783
Test name
Test status
Simulation time 41812638 ps
CPU time 0.87 seconds
Started Aug 14 05:32:21 PM PDT 24
Finished Aug 14 05:32:22 PM PDT 24
Peak memory 215460 kb
Host smart-2aba7b7b-54b7-4175-a0c3-5992946a1404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325422709 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2325422709
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2152229260
Short name T563
Test name
Test status
Simulation time 29814833 ps
CPU time 0.98 seconds
Started Aug 14 05:32:10 PM PDT 24
Finished Aug 14 05:32:12 PM PDT 24
Peak memory 215584 kb
Host smart-e3761e34-7700-41c8-bfee-3ef0d99f0dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152229260 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2152229260
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3093622015
Short name T691
Test name
Test status
Simulation time 1226805120 ps
CPU time 31.25 seconds
Started Aug 14 05:32:15 PM PDT 24
Finished Aug 14 05:32:47 PM PDT 24
Peak memory 218936 kb
Host smart-d1b5b007-c191-4cb7-9489-9abf55ba8060
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093622015 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3093622015
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.2576576193
Short name T9
Test name
Test status
Simulation time 56946235 ps
CPU time 1.26 seconds
Started Aug 14 05:33:54 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 216016 kb
Host smart-d366b2e2-0dd4-4d9a-b8b7-895063f8a4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576576193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2576576193
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.3217990629
Short name T408
Test name
Test status
Simulation time 138255303 ps
CPU time 1.76 seconds
Started Aug 14 05:33:51 PM PDT 24
Finished Aug 14 05:33:53 PM PDT 24
Peak memory 219236 kb
Host smart-01b5edd8-9e7b-4fa7-92c5-12059018b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217990629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3217990629
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.2470658334
Short name T772
Test name
Test status
Simulation time 68300158 ps
CPU time 1.16 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:54 PM PDT 24
Peak memory 220440 kb
Host smart-96766c24-0ca2-49c1-b8bd-14a1aeb4dff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470658334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2470658334
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.2195124289
Short name T371
Test name
Test status
Simulation time 85431071 ps
CPU time 2.42 seconds
Started Aug 14 05:33:30 PM PDT 24
Finished Aug 14 05:33:33 PM PDT 24
Peak memory 219420 kb
Host smart-4a73ab95-ecc1-43a5-83db-a4f78b28dc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195124289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2195124289
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.2066441174
Short name T178
Test name
Test status
Simulation time 22714447 ps
CPU time 1.13 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:54 PM PDT 24
Peak memory 218824 kb
Host smart-d7d6aaa2-500e-4f43-857d-a530ebdb51a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066441174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2066441174
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3697620989
Short name T53
Test name
Test status
Simulation time 76535824 ps
CPU time 1.63 seconds
Started Aug 14 05:33:30 PM PDT 24
Finished Aug 14 05:33:31 PM PDT 24
Peak memory 219200 kb
Host smart-e8391d83-e68f-4b05-a54c-95749152bb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697620989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3697620989
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.2275989005
Short name T680
Test name
Test status
Simulation time 55429669 ps
CPU time 1.4 seconds
Started Aug 14 05:33:30 PM PDT 24
Finished Aug 14 05:33:31 PM PDT 24
Peak memory 217448 kb
Host smart-a4d66f89-fb5e-4ae7-b8ac-1300ad0dd587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275989005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2275989005
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.238409766
Short name T516
Test name
Test status
Simulation time 30435214 ps
CPU time 1.36 seconds
Started Aug 14 05:33:29 PM PDT 24
Finished Aug 14 05:33:30 PM PDT 24
Peak memory 219036 kb
Host smart-49287097-9592-49b8-a0bc-37dd378fec67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238409766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.238409766
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3598116559
Short name T885
Test name
Test status
Simulation time 68015435 ps
CPU time 1.35 seconds
Started Aug 14 05:33:49 PM PDT 24
Finished Aug 14 05:33:50 PM PDT 24
Peak memory 217536 kb
Host smart-2c232e14-518f-48d4-9021-c6c11ec72327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598116559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3598116559
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.1542222873
Short name T807
Test name
Test status
Simulation time 33610508 ps
CPU time 1.36 seconds
Started Aug 14 05:33:50 PM PDT 24
Finished Aug 14 05:33:51 PM PDT 24
Peak memory 216112 kb
Host smart-bb14dc34-138b-41f3-a1c1-228a9e30a7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542222873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1542222873
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1813456585
Short name T90
Test name
Test status
Simulation time 67789666 ps
CPU time 1.03 seconds
Started Aug 14 05:33:30 PM PDT 24
Finished Aug 14 05:33:31 PM PDT 24
Peak memory 217396 kb
Host smart-d8bd283d-680c-409a-93d5-116918b6c0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813456585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1813456585
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3323067174
Short name T488
Test name
Test status
Simulation time 26720569 ps
CPU time 1.27 seconds
Started Aug 14 05:33:47 PM PDT 24
Finished Aug 14 05:33:49 PM PDT 24
Peak memory 219028 kb
Host smart-abf46151-4835-49a4-acc1-f04f5247c587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323067174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3323067174
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1310336435
Short name T719
Test name
Test status
Simulation time 76446312 ps
CPU time 1.13 seconds
Started Aug 14 05:33:29 PM PDT 24
Finished Aug 14 05:33:30 PM PDT 24
Peak memory 217660 kb
Host smart-830f4d49-54fc-4e12-abd4-4a81eda56a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310336435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1310336435
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.2621452151
Short name T745
Test name
Test status
Simulation time 23702243 ps
CPU time 1.16 seconds
Started Aug 14 05:33:31 PM PDT 24
Finished Aug 14 05:33:32 PM PDT 24
Peak memory 218820 kb
Host smart-babce203-f9e7-43d0-8eb5-4f3b9cfc6328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621452151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.2621452151
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3878413193
Short name T381
Test name
Test status
Simulation time 55767767 ps
CPU time 1.54 seconds
Started Aug 14 05:33:47 PM PDT 24
Finished Aug 14 05:33:49 PM PDT 24
Peak memory 219176 kb
Host smart-b74d3bca-47c6-4ea1-84ca-193a04999281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878413193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3878413193
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.3575414328
Short name T448
Test name
Test status
Simulation time 76331278 ps
CPU time 1.13 seconds
Started Aug 14 05:33:43 PM PDT 24
Finished Aug 14 05:33:45 PM PDT 24
Peak memory 219028 kb
Host smart-5b0d7131-878a-417f-9aad-1510d8c7ebe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575414328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3575414328
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3681378025
Short name T545
Test name
Test status
Simulation time 155154352 ps
CPU time 3.17 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 220368 kb
Host smart-8a0d57bd-3fae-4893-9786-9f70d33634f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681378025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3681378025
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.4202656705
Short name T23
Test name
Test status
Simulation time 226414903 ps
CPU time 1.21 seconds
Started Aug 14 05:33:49 PM PDT 24
Finished Aug 14 05:33:50 PM PDT 24
Peak memory 218716 kb
Host smart-08248a15-b48a-4a7b-99fb-e8cae9762b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202656705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.4202656705
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.206981991
Short name T852
Test name
Test status
Simulation time 56956018 ps
CPU time 1.41 seconds
Started Aug 14 05:33:32 PM PDT 24
Finished Aug 14 05:33:34 PM PDT 24
Peak memory 217800 kb
Host smart-b8fcade0-07b1-4925-b6a5-03fccf91ed4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206981991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.206981991
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1787278704
Short name T124
Test name
Test status
Simulation time 160393289 ps
CPU time 1.24 seconds
Started Aug 14 05:32:14 PM PDT 24
Finished Aug 14 05:32:16 PM PDT 24
Peak memory 219472 kb
Host smart-c4574eb7-4302-443f-bfeb-2b24f7be088b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787278704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1787278704
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1715896389
Short name T625
Test name
Test status
Simulation time 91277068 ps
CPU time 0.91 seconds
Started Aug 14 05:32:15 PM PDT 24
Finished Aug 14 05:32:16 PM PDT 24
Peak memory 206916 kb
Host smart-9cfb18fe-459b-4467-8df9-4bc37f4e4c3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715896389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1715896389
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.83040663
Short name T434
Test name
Test status
Simulation time 32169918 ps
CPU time 0.85 seconds
Started Aug 14 05:32:14 PM PDT 24
Finished Aug 14 05:32:15 PM PDT 24
Peak memory 207548 kb
Host smart-4d0c6892-1cf4-4640-9769-e0e709fed9e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83040663 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.83040663
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.1354576176
Short name T896
Test name
Test status
Simulation time 31881512 ps
CPU time 1.22 seconds
Started Aug 14 05:32:20 PM PDT 24
Finished Aug 14 05:32:21 PM PDT 24
Peak memory 219684 kb
Host smart-5c0399e5-5f8a-4d32-9a42-c25456e0682b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354576176 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1354576176
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.4070834106
Short name T28
Test name
Test status
Simulation time 54436140 ps
CPU time 1.1 seconds
Started Aug 14 05:32:10 PM PDT 24
Finished Aug 14 05:32:11 PM PDT 24
Peak memory 218676 kb
Host smart-95f975f6-a36f-40fa-bbb8-00dda345c844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070834106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.4070834106
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.1063392309
Short name T387
Test name
Test status
Simulation time 22764518 ps
CPU time 0.97 seconds
Started Aug 14 05:32:11 PM PDT 24
Finished Aug 14 05:32:12 PM PDT 24
Peak memory 207328 kb
Host smart-e64f4174-6082-4f48-ad72-a72b793703f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063392309 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1063392309
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2190872822
Short name T253
Test name
Test status
Simulation time 566619809 ps
CPU time 5.67 seconds
Started Aug 14 05:32:17 PM PDT 24
Finished Aug 14 05:32:23 PM PDT 24
Peak memory 217464 kb
Host smart-94a2785b-3cfa-4fd0-88c5-4e65a6d73388
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190872822 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2190872822
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/120.edn_genbits.839346326
Short name T13
Test name
Test status
Simulation time 108185603 ps
CPU time 1.45 seconds
Started Aug 14 05:33:45 PM PDT 24
Finished Aug 14 05:33:46 PM PDT 24
Peak memory 217800 kb
Host smart-bb0f9fa8-0c88-4458-9eef-585bf35dbf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839346326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.839346326
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3732533771
Short name T393
Test name
Test status
Simulation time 40313375 ps
CPU time 1.12 seconds
Started Aug 14 05:33:54 PM PDT 24
Finished Aug 14 05:33:56 PM PDT 24
Peak memory 220912 kb
Host smart-1e5356b6-3a21-4b71-86a4-7389a8c2f84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732533771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3732533771
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.3773823228
Short name T638
Test name
Test status
Simulation time 41712429 ps
CPU time 1.71 seconds
Started Aug 14 05:33:47 PM PDT 24
Finished Aug 14 05:33:49 PM PDT 24
Peak memory 218880 kb
Host smart-3bb3defd-6c39-4051-a3e3-59d0b0f7301a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773823228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3773823228
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.2374877803
Short name T375
Test name
Test status
Simulation time 96577313 ps
CPU time 1.24 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 219896 kb
Host smart-f361404d-ffd5-4427-8e3b-b104a6bc3c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374877803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2374877803
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.2757428578
Short name T854
Test name
Test status
Simulation time 91355899 ps
CPU time 1.29 seconds
Started Aug 14 05:33:48 PM PDT 24
Finished Aug 14 05:33:49 PM PDT 24
Peak memory 217596 kb
Host smart-b9226e52-9117-49c1-87eb-09f6c1f03a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757428578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2757428578
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.3908108846
Short name T921
Test name
Test status
Simulation time 57810241 ps
CPU time 1.21 seconds
Started Aug 14 05:34:49 PM PDT 24
Finished Aug 14 05:34:55 PM PDT 24
Peak memory 215848 kb
Host smart-6110236f-32e5-41b7-9308-3acafa0f268e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908108846 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.3908108846
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.586004428
Short name T894
Test name
Test status
Simulation time 3187550335 ps
CPU time 80.34 seconds
Started Aug 14 05:33:41 PM PDT 24
Finished Aug 14 05:35:01 PM PDT 24
Peak memory 220980 kb
Host smart-ee628e26-7b3c-4ca1-bc0c-85f6b88bd935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586004428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.586004428
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.3574186964
Short name T777
Test name
Test status
Simulation time 28110660 ps
CPU time 1.23 seconds
Started Aug 14 05:34:02 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 220200 kb
Host smart-c13b34d3-3cab-4f75-b4ed-d12d0f16c8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574186964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3574186964
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.345027463
Short name T24
Test name
Test status
Simulation time 4468409167 ps
CPU time 78.58 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:35:18 PM PDT 24
Peak memory 221080 kb
Host smart-4e77673e-5242-4fcb-b2bf-15e59f6e6bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345027463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.345027463
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.234554974
Short name T409
Test name
Test status
Simulation time 52341645 ps
CPU time 1.19 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:56 PM PDT 24
Peak memory 220488 kb
Host smart-fc7ac248-80da-4650-bbc9-281c2e0be269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234554974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.234554974
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.547924565
Short name T27
Test name
Test status
Simulation time 26800077 ps
CPU time 1.26 seconds
Started Aug 14 05:33:38 PM PDT 24
Finished Aug 14 05:33:39 PM PDT 24
Peak memory 218844 kb
Host smart-3201d58e-efb0-473a-b1a4-2da3a79b59dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547924565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.547924565
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.973412757
Short name T121
Test name
Test status
Simulation time 55311666 ps
CPU time 1.3 seconds
Started Aug 14 05:33:44 PM PDT 24
Finished Aug 14 05:33:46 PM PDT 24
Peak memory 216012 kb
Host smart-702f03cf-e5d2-43b1-a35e-bccaa7cdcd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973412757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.973412757
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1422960706
Short name T116
Test name
Test status
Simulation time 36776642 ps
CPU time 1.13 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:53 PM PDT 24
Peak memory 219016 kb
Host smart-8ad8e0cf-3b39-4afd-870a-73dfe1b89ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422960706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1422960706
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3993948439
Short name T572
Test name
Test status
Simulation time 24098242 ps
CPU time 1.15 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 218752 kb
Host smart-5143c5f9-06ca-4bbf-9180-8485733c7165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993948439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3993948439
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3221586919
Short name T490
Test name
Test status
Simulation time 85614423 ps
CPU time 1.08 seconds
Started Aug 14 05:33:50 PM PDT 24
Finished Aug 14 05:33:51 PM PDT 24
Peak memory 217096 kb
Host smart-9281b299-af16-49cb-9660-a019447b711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221586919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3221586919
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.374585403
Short name T960
Test name
Test status
Simulation time 24856217 ps
CPU time 1.17 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 220904 kb
Host smart-dcdc4980-5c6d-410b-a1a1-d8d78368b991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374585403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.374585403
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.99558762
Short name T877
Test name
Test status
Simulation time 38867604 ps
CPU time 1.51 seconds
Started Aug 14 05:33:40 PM PDT 24
Finished Aug 14 05:33:41 PM PDT 24
Peak memory 218844 kb
Host smart-ec38a0bc-73fd-46c7-b041-9a1ec7b7542b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99558762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.99558762
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.1036486775
Short name T941
Test name
Test status
Simulation time 41047388 ps
CPU time 1.14 seconds
Started Aug 14 05:32:26 PM PDT 24
Finished Aug 14 05:32:27 PM PDT 24
Peak memory 207228 kb
Host smart-3d3a02e7-84e8-477c-b205-cca6c7418e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036486775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1036486775
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1932589404
Short name T228
Test name
Test status
Simulation time 42428515 ps
CPU time 0.84 seconds
Started Aug 14 05:32:11 PM PDT 24
Finished Aug 14 05:32:12 PM PDT 24
Peak memory 215536 kb
Host smart-75024ab2-7b79-455b-bf6c-37c2f7c791be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932589404 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1932589404
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2727729235
Short name T769
Test name
Test status
Simulation time 66266799 ps
CPU time 1.33 seconds
Started Aug 14 05:32:12 PM PDT 24
Finished Aug 14 05:32:14 PM PDT 24
Peak memory 217320 kb
Host smart-70ab9221-7321-4a12-b964-61bf30d650c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727729235 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2727729235
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2320165763
Short name T211
Test name
Test status
Simulation time 54484039 ps
CPU time 1.23 seconds
Started Aug 14 05:32:11 PM PDT 24
Finished Aug 14 05:32:13 PM PDT 24
Peak memory 219640 kb
Host smart-c2272df7-834e-4400-b434-6193ce18bc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320165763 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2320165763
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1173336782
Short name T508
Test name
Test status
Simulation time 260624126 ps
CPU time 1.03 seconds
Started Aug 14 05:32:09 PM PDT 24
Finished Aug 14 05:32:11 PM PDT 24
Peak memory 217352 kb
Host smart-64cec46f-176b-4083-b4fb-3ed049880b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173336782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1173336782
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1054628916
Short name T37
Test name
Test status
Simulation time 19881936 ps
CPU time 1.06 seconds
Started Aug 14 05:32:07 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 216184 kb
Host smart-c86c53c5-6a93-44cb-85a6-8bba230055cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054628916 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1054628916
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.682165268
Short name T466
Test name
Test status
Simulation time 21775164 ps
CPU time 1 seconds
Started Aug 14 05:32:14 PM PDT 24
Finished Aug 14 05:32:15 PM PDT 24
Peak memory 214104 kb
Host smart-0ec8212b-dcd5-40fd-9edc-c68f59ee6626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682165268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.682165268
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/130.edn_alert.959258057
Short name T971
Test name
Test status
Simulation time 150867624 ps
CPU time 1.17 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:54 PM PDT 24
Peak memory 219776 kb
Host smart-afd59ec5-a03e-4c08-bf7a-845cbf94563f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959258057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.959258057
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1952073425
Short name T421
Test name
Test status
Simulation time 99363680 ps
CPU time 1.25 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:53 PM PDT 24
Peak memory 216616 kb
Host smart-5c75c2ea-46c3-4294-87e4-b32888dec3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952073425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1952073425
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.2971519015
Short name T294
Test name
Test status
Simulation time 97629873 ps
CPU time 1.28 seconds
Started Aug 14 05:33:39 PM PDT 24
Finished Aug 14 05:33:41 PM PDT 24
Peak memory 218728 kb
Host smart-0ef9d967-76fa-43ff-86a5-c969fe3932ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971519015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.2971519015
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.82479744
Short name T878
Test name
Test status
Simulation time 41377100 ps
CPU time 1.48 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 220028 kb
Host smart-726c4300-62a6-45fc-94f1-5c883682c900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82479744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.82479744
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.815335330
Short name T755
Test name
Test status
Simulation time 26667605 ps
CPU time 1.26 seconds
Started Aug 14 05:33:40 PM PDT 24
Finished Aug 14 05:33:41 PM PDT 24
Peak memory 220924 kb
Host smart-f349ce97-8fff-4037-904b-0778988036fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815335330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.815335330
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1695864144
Short name T687
Test name
Test status
Simulation time 77356820 ps
CPU time 2.73 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 217916 kb
Host smart-285d0f3f-3687-450a-8aad-85be807fd3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695864144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1695864144
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.551115811
Short name T98
Test name
Test status
Simulation time 49698106 ps
CPU time 1.27 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 217800 kb
Host smart-086a3e21-7269-4b74-81ad-1eadea49ad90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551115811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.551115811
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.3354597905
Short name T842
Test name
Test status
Simulation time 41284543 ps
CPU time 1.2 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219968 kb
Host smart-e509ebfa-2f08-43e6-9059-bfd7377761cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354597905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3354597905
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1615389467
Short name T364
Test name
Test status
Simulation time 288853151 ps
CPU time 1.2 seconds
Started Aug 14 05:33:39 PM PDT 24
Finished Aug 14 05:33:41 PM PDT 24
Peak memory 217644 kb
Host smart-fbd1fa7d-de79-4f98-8e41-0ae828621158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615389467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1615389467
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.4094495071
Short name T492
Test name
Test status
Simulation time 55721324 ps
CPU time 1.16 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 219836 kb
Host smart-5de26fdb-bdb7-4ed6-9c09-9eb6e9e33649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094495071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.4094495071
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.3985089457
Short name T652
Test name
Test status
Simulation time 72784018 ps
CPU time 1.1 seconds
Started Aug 14 05:33:51 PM PDT 24
Finished Aug 14 05:33:53 PM PDT 24
Peak memory 220228 kb
Host smart-90b7fe80-4619-4cec-ab3b-09054faddbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985089457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3985089457
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3095022027
Short name T101
Test name
Test status
Simulation time 46029258 ps
CPU time 1.06 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 220088 kb
Host smart-60a0fdaa-e1e6-42a5-8931-20af57f59c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095022027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3095022027
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2147497579
Short name T860
Test name
Test status
Simulation time 64960933 ps
CPU time 1.65 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:54 PM PDT 24
Peak memory 218960 kb
Host smart-8923d490-3b92-48cf-a2eb-2eec5a08e466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147497579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2147497579
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.663743254
Short name T595
Test name
Test status
Simulation time 75782351 ps
CPU time 1.19 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 218864 kb
Host smart-cfc27a6c-c7ad-40df-ada8-26afd5ab2d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663743254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.663743254
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.3505202329
Short name T331
Test name
Test status
Simulation time 40781392 ps
CPU time 1.62 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 218796 kb
Host smart-de35180b-6288-4c6b-adec-a124660709c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505202329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3505202329
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3435912524
Short name T584
Test name
Test status
Simulation time 37456364 ps
CPU time 1.2 seconds
Started Aug 14 05:33:47 PM PDT 24
Finished Aug 14 05:33:48 PM PDT 24
Peak memory 219992 kb
Host smart-ba60cbc2-5b33-4d10-9040-34ff1d3b0687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435912524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3435912524
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.292159691
Short name T535
Test name
Test status
Simulation time 228888895 ps
CPU time 1.2 seconds
Started Aug 14 05:33:48 PM PDT 24
Finished Aug 14 05:33:50 PM PDT 24
Peak memory 217804 kb
Host smart-038b7a45-fc88-4721-8c5b-f1c49ab62c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292159691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.292159691
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1708001918
Short name T813
Test name
Test status
Simulation time 29571011 ps
CPU time 1.22 seconds
Started Aug 14 05:33:54 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 220128 kb
Host smart-459a8506-352a-4a1f-8fc2-4e00387f0cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708001918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1708001918
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3385680532
Short name T846
Test name
Test status
Simulation time 42305092 ps
CPU time 1.55 seconds
Started Aug 14 05:33:54 PM PDT 24
Finished Aug 14 05:33:56 PM PDT 24
Peak memory 217488 kb
Host smart-515f1aac-53f8-46df-87fa-cf8d223cca8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385680532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3385680532
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2608530320
Short name T862
Test name
Test status
Simulation time 81058720 ps
CPU time 1.1 seconds
Started Aug 14 05:32:24 PM PDT 24
Finished Aug 14 05:32:25 PM PDT 24
Peak memory 220228 kb
Host smart-7892d6ff-6ddc-4cea-8c96-a363df0fbc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608530320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2608530320
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3671263019
Short name T651
Test name
Test status
Simulation time 29045796 ps
CPU time 0.94 seconds
Started Aug 14 05:32:28 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 215136 kb
Host smart-a0432cd1-48ef-41c1-bfaa-7c8d9fcc80bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671263019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3671263019
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3612393622
Short name T760
Test name
Test status
Simulation time 152679606 ps
CPU time 1.11 seconds
Started Aug 14 05:32:24 PM PDT 24
Finished Aug 14 05:32:25 PM PDT 24
Peak memory 217108 kb
Host smart-3c8f5d83-b983-42bd-bace-a1db4a566978
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612393622 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3612393622
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2724996118
Short name T169
Test name
Test status
Simulation time 34835615 ps
CPU time 0.87 seconds
Started Aug 14 05:32:28 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 218544 kb
Host smart-c9b2f47d-140a-43c2-a761-1e59939416d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724996118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2724996118
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2826927415
Short name T47
Test name
Test status
Simulation time 35988125 ps
CPU time 1.58 seconds
Started Aug 14 05:32:21 PM PDT 24
Finished Aug 14 05:32:23 PM PDT 24
Peak memory 218704 kb
Host smart-59a9338d-293d-425c-8188-3c882b60b440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826927415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2826927415
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.951889434
Short name T429
Test name
Test status
Simulation time 20716996 ps
CPU time 1.11 seconds
Started Aug 14 05:32:23 PM PDT 24
Finished Aug 14 05:32:24 PM PDT 24
Peak memory 215680 kb
Host smart-f0d0d87b-a03a-4db9-a29b-23872bb6ba58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951889434 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.951889434
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1343017650
Short name T463
Test name
Test status
Simulation time 42447415 ps
CPU time 0.93 seconds
Started Aug 14 05:32:22 PM PDT 24
Finished Aug 14 05:32:23 PM PDT 24
Peak memory 215588 kb
Host smart-e56a8d71-02b1-4795-abb6-9e7afec5a0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343017650 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1343017650
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3370125763
Short name T527
Test name
Test status
Simulation time 89021413 ps
CPU time 2.23 seconds
Started Aug 14 05:32:22 PM PDT 24
Finished Aug 14 05:32:24 PM PDT 24
Peak memory 218788 kb
Host smart-76c09df7-c2eb-450f-bf11-4f3bf60d871f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370125763 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3370125763
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.984628006
Short name T551
Test name
Test status
Simulation time 12200657648 ps
CPU time 51.66 seconds
Started Aug 14 05:32:21 PM PDT 24
Finished Aug 14 05:33:13 PM PDT 24
Peak memory 218776 kb
Host smart-ba2eb198-e5b6-45b2-8e42-5ad8d831bb84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984628006 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.984628006
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.438983409
Short name T454
Test name
Test status
Simulation time 79214022 ps
CPU time 1.36 seconds
Started Aug 14 05:33:43 PM PDT 24
Finished Aug 14 05:33:45 PM PDT 24
Peak memory 220180 kb
Host smart-99948617-d021-446e-ad88-5b73406e9bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438983409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.438983409
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.393577754
Short name T787
Test name
Test status
Simulation time 52682235 ps
CPU time 1.14 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 219264 kb
Host smart-424a244f-2b49-450d-9131-b5f1b68f8821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393577754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.393577754
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2868874686
Short name T938
Test name
Test status
Simulation time 43046656 ps
CPU time 1.5 seconds
Started Aug 14 05:33:47 PM PDT 24
Finished Aug 14 05:33:49 PM PDT 24
Peak memory 220216 kb
Host smart-0fe1d096-fabd-42b1-a5a8-39643bc4604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868874686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2868874686
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3246630700
Short name T403
Test name
Test status
Simulation time 66950645 ps
CPU time 1.09 seconds
Started Aug 14 05:34:49 PM PDT 24
Finished Aug 14 05:34:55 PM PDT 24
Peak memory 219856 kb
Host smart-0c115e40-0835-478e-b1ab-3f674101e526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246630700 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3246630700
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.727953427
Short name T96
Test name
Test status
Simulation time 32758284 ps
CPU time 1.21 seconds
Started Aug 14 05:34:50 PM PDT 24
Finished Aug 14 05:34:52 PM PDT 24
Peak memory 217416 kb
Host smart-2bd2b52d-3e4e-4376-86ca-4a7b34d8d20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727953427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.727953427
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1604733296
Short name T172
Test name
Test status
Simulation time 26743397 ps
CPU time 1.21 seconds
Started Aug 14 05:33:44 PM PDT 24
Finished Aug 14 05:33:45 PM PDT 24
Peak memory 219388 kb
Host smart-d4c79554-abad-4b64-847b-e2a9a4fd4776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604733296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1604733296
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.319298832
Short name T969
Test name
Test status
Simulation time 49138238 ps
CPU time 1.75 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 218888 kb
Host smart-799c57a0-9578-4987-85aa-c880bbd891a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319298832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.319298832
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.610017902
Short name T465
Test name
Test status
Simulation time 64860059 ps
CPU time 1.53 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 218828 kb
Host smart-5305e2aa-7aa4-4c2b-92fd-796e7629bf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610017902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.610017902
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.540486494
Short name T588
Test name
Test status
Simulation time 79286034 ps
CPU time 1.18 seconds
Started Aug 14 05:33:46 PM PDT 24
Finished Aug 14 05:33:48 PM PDT 24
Peak memory 219048 kb
Host smart-2213c836-0743-4606-94b1-c85a46dae21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540486494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.540486494
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/146.edn_alert.4262430381
Short name T597
Test name
Test status
Simulation time 88963705 ps
CPU time 1.23 seconds
Started Aug 14 05:33:43 PM PDT 24
Finished Aug 14 05:33:44 PM PDT 24
Peak memory 220216 kb
Host smart-e35999e9-7083-43fa-9245-51b61dd0ad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262430381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.4262430381
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.863468053
Short name T905
Test name
Test status
Simulation time 60557062 ps
CPU time 1.4 seconds
Started Aug 14 05:34:49 PM PDT 24
Finished Aug 14 05:34:51 PM PDT 24
Peak memory 218892 kb
Host smart-a3723e46-3420-4b8e-be98-0b357713ddc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863468053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.863468053
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1423833927
Short name T424
Test name
Test status
Simulation time 72014837 ps
CPU time 1.35 seconds
Started Aug 14 05:33:43 PM PDT 24
Finished Aug 14 05:33:45 PM PDT 24
Peak memory 218944 kb
Host smart-41be8cce-03c1-4e34-b5ef-b62619054825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423833927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1423833927
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.2785885372
Short name T188
Test name
Test status
Simulation time 26373233 ps
CPU time 1.18 seconds
Started Aug 14 05:33:43 PM PDT 24
Finished Aug 14 05:33:45 PM PDT 24
Peak memory 220200 kb
Host smart-a46fdc76-6724-4586-ac3e-355a9b52b1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785885372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2785885372
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.214046969
Short name T385
Test name
Test status
Simulation time 36054425 ps
CPU time 1.38 seconds
Started Aug 14 05:34:48 PM PDT 24
Finished Aug 14 05:34:50 PM PDT 24
Peak memory 217624 kb
Host smart-285e5d66-d3f8-436f-bdc9-dc11b2b011ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214046969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.214046969
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.1120761336
Short name T147
Test name
Test status
Simulation time 32420402 ps
CPU time 1.13 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 218832 kb
Host smart-f4246ae6-4d56-4334-a398-0bebb24db6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120761336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1120761336
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2743304824
Short name T835
Test name
Test status
Simulation time 48558293 ps
CPU time 1.79 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 218900 kb
Host smart-b4e8ec17-bd77-42fe-ad63-81ec73053b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743304824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2743304824
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3873175621
Short name T425
Test name
Test status
Simulation time 28863357 ps
CPU time 1.13 seconds
Started Aug 14 05:32:21 PM PDT 24
Finished Aug 14 05:32:23 PM PDT 24
Peak memory 218672 kb
Host smart-dcddbe69-6ea8-4e33-beb5-d46a0ea1137a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873175621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3873175621
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1021027416
Short name T359
Test name
Test status
Simulation time 13019036 ps
CPU time 0.91 seconds
Started Aug 14 05:32:23 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 207340 kb
Host smart-a494121b-5de4-4b19-82f3-46818ca6edda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021027416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1021027416
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.940042165
Short name T170
Test name
Test status
Simulation time 30436680 ps
CPU time 0.88 seconds
Started Aug 14 05:32:20 PM PDT 24
Finished Aug 14 05:32:21 PM PDT 24
Peak memory 215688 kb
Host smart-0143f977-523e-47af-b0e8-b76752816dd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940042165 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.940042165
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.4213167570
Short name T782
Test name
Test status
Simulation time 74586461 ps
CPU time 1.17 seconds
Started Aug 14 05:32:27 PM PDT 24
Finished Aug 14 05:32:28 PM PDT 24
Peak memory 218712 kb
Host smart-1aed8915-28e6-4c67-8053-1c0e709b2db7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213167570 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.4213167570
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.859092783
Short name T522
Test name
Test status
Simulation time 22786147 ps
CPU time 0.99 seconds
Started Aug 14 05:32:20 PM PDT 24
Finished Aug 14 05:32:22 PM PDT 24
Peak memory 218576 kb
Host smart-b1b9d206-29b1-4ae5-9804-5b256d50fd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859092783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.859092783
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3415999944
Short name T567
Test name
Test status
Simulation time 27093397 ps
CPU time 1.26 seconds
Started Aug 14 05:32:17 PM PDT 24
Finished Aug 14 05:32:19 PM PDT 24
Peak memory 219992 kb
Host smart-6522e319-a97e-47df-a02a-536880b66b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415999944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3415999944
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.3867513274
Short name T363
Test name
Test status
Simulation time 44451822 ps
CPU time 0.91 seconds
Started Aug 14 05:32:22 PM PDT 24
Finished Aug 14 05:32:23 PM PDT 24
Peak memory 215628 kb
Host smart-8a158223-113b-4a88-9e03-93176862585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867513274 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3867513274
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.291628079
Short name T475
Test name
Test status
Simulation time 454491018 ps
CPU time 4.93 seconds
Started Aug 14 05:32:24 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 220672 kb
Host smart-7cc74d43-9299-4e66-9158-1966c84a9e75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291628079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.291628079
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3248708254
Short name T242
Test name
Test status
Simulation time 12157815575 ps
CPU time 71.41 seconds
Started Aug 14 05:32:26 PM PDT 24
Finished Aug 14 05:33:37 PM PDT 24
Peak memory 219332 kb
Host smart-5fb4cb35-0ef1-417e-a46a-1c2c3b75f120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248708254 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3248708254
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2663125603
Short name T89
Test name
Test status
Simulation time 43469415 ps
CPU time 1.12 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 218904 kb
Host smart-e1b93839-c7c6-4ce8-bf46-5879c22be407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663125603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2663125603
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2056084976
Short name T476
Test name
Test status
Simulation time 26653505 ps
CPU time 1.29 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 218108 kb
Host smart-65ab1315-a6b0-4799-9cd2-00a6f0c4041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056084976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2056084976
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.447938672
Short name T839
Test name
Test status
Simulation time 46879497 ps
CPU time 1.27 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219644 kb
Host smart-963dfd3d-c790-46f5-a23d-066fc708e063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447938672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.447938672
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.1066709244
Short name T917
Test name
Test status
Simulation time 80512056 ps
CPU time 1 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 217488 kb
Host smart-5ed82681-90bd-4c75-acfb-d4866a6bb1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066709244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1066709244
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3029544142
Short name T143
Test name
Test status
Simulation time 65804681 ps
CPU time 1.19 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 218796 kb
Host smart-f4a9c777-3c0c-4f7e-92e6-1145a999e10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029544142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3029544142
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3025494796
Short name T57
Test name
Test status
Simulation time 203475463 ps
CPU time 1.24 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 217692 kb
Host smart-adbd3170-4f0b-4f55-8326-3fecee9d9bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025494796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3025494796
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2120722686
Short name T443
Test name
Test status
Simulation time 31570663 ps
CPU time 1.31 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 220816 kb
Host smart-92b2a7cd-8a68-412f-9112-eb6435fe5dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120722686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2120722686
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1461290405
Short name T746
Test name
Test status
Simulation time 57082939 ps
CPU time 1.45 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 219160 kb
Host smart-b5f386c9-012e-4e59-b0a7-a3f66e6c5ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461290405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1461290405
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.4266417903
Short name T893
Test name
Test status
Simulation time 30587872 ps
CPU time 1.36 seconds
Started Aug 14 05:34:02 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 220120 kb
Host smart-b6658266-7aef-4131-ac0a-0812c486440b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266417903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.4266417903
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.3807916332
Short name T309
Test name
Test status
Simulation time 144164918 ps
CPU time 1.6 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 215528 kb
Host smart-5bd4aec2-5a45-473c-8d87-78e7532841ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807916332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3807916332
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3567934101
Short name T890
Test name
Test status
Simulation time 139563879 ps
CPU time 1.2 seconds
Started Aug 14 05:33:54 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 220904 kb
Host smart-9b9eda9a-08d1-4192-82b2-dc6d1450a2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567934101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3567934101
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1858474834
Short name T915
Test name
Test status
Simulation time 49251676 ps
CPU time 1.41 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 218988 kb
Host smart-d6eaea14-2a5d-492d-97f8-db8b6920d208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858474834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1858474834
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1989479746
Short name T828
Test name
Test status
Simulation time 242130037 ps
CPU time 1.2 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 218772 kb
Host smart-28b56b1f-548f-495e-9e48-4ac292b9494e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989479746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1989479746
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2575433231
Short name T728
Test name
Test status
Simulation time 99172928 ps
CPU time 2.14 seconds
Started Aug 14 05:34:04 PM PDT 24
Finished Aug 14 05:34:06 PM PDT 24
Peak memory 219204 kb
Host smart-63e40882-2ada-4c62-9901-8d0930be6fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575433231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2575433231
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.2030440943
Short name T268
Test name
Test status
Simulation time 55410977 ps
CPU time 1.23 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 216000 kb
Host smart-c9ea2242-e045-40fd-9d01-3d7907bc57e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030440943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2030440943
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.1352066056
Short name T758
Test name
Test status
Simulation time 50632479 ps
CPU time 1.03 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 220324 kb
Host smart-631082c9-d476-45cd-808b-941144ed928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352066056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1352066056
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.2048055987
Short name T201
Test name
Test status
Simulation time 205854528 ps
CPU time 1.34 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 219732 kb
Host smart-7b3cbc3d-0c09-4dbb-a1a8-f8fac25c6185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048055987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.2048055987
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.1708208902
Short name T383
Test name
Test status
Simulation time 396431174 ps
CPU time 1.24 seconds
Started Aug 14 05:34:02 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 217588 kb
Host smart-7099184d-f41b-427b-bb49-158ecb81babd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708208902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1708208902
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.584344884
Short name T59
Test name
Test status
Simulation time 190440916 ps
CPU time 1.11 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 218848 kb
Host smart-9597186f-69cb-4268-a940-e0226f38e172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584344884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.584344884
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.3956623426
Short name T520
Test name
Test status
Simulation time 32573448 ps
CPU time 1.35 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:54 PM PDT 24
Peak memory 218576 kb
Host smart-a5688a36-a725-46f2-b3df-851ac95fc108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956623426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3956623426
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert_test.4265047638
Short name T399
Test name
Test status
Simulation time 67320002 ps
CPU time 0.9 seconds
Started Aug 14 05:32:24 PM PDT 24
Finished Aug 14 05:32:25 PM PDT 24
Peak memory 206916 kb
Host smart-ebda1836-1e3e-40a5-9ae1-35956a452b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265047638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.4265047638
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_err.4269498473
Short name T131
Test name
Test status
Simulation time 35415154 ps
CPU time 1 seconds
Started Aug 14 05:32:18 PM PDT 24
Finished Aug 14 05:32:19 PM PDT 24
Peak memory 229848 kb
Host smart-69b6f0be-44c4-4a46-94a5-f8c311700f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269498473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.4269498473
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1518857056
Short name T568
Test name
Test status
Simulation time 104103430 ps
CPU time 1.42 seconds
Started Aug 14 05:32:28 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 217844 kb
Host smart-063b81b3-b323-46e6-b961-8e31c91ca5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518857056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1518857056
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2924350738
Short name T113
Test name
Test status
Simulation time 30508855 ps
CPU time 0.86 seconds
Started Aug 14 05:32:23 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 215460 kb
Host smart-84170df1-2d91-4d10-ae2a-5bd4d6f6d292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924350738 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2924350738
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3378633168
Short name T532
Test name
Test status
Simulation time 68742860 ps
CPU time 0.93 seconds
Started Aug 14 05:32:28 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 215396 kb
Host smart-05bdd386-7148-4856-85e0-859f06487795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378633168 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3378633168
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2047878766
Short name T945
Test name
Test status
Simulation time 286786521 ps
CPU time 3.37 seconds
Started Aug 14 05:32:25 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 215588 kb
Host smart-0aa14cd3-df9d-4086-a165-dee3f5f56795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047878766 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2047878766
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_alert.2724058033
Short name T904
Test name
Test status
Simulation time 26416120 ps
CPU time 1.26 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 221280 kb
Host smart-65881115-6e8b-42d9-ae76-34a6ecb66944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724058033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2724058033
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.86968204
Short name T473
Test name
Test status
Simulation time 43099700 ps
CPU time 1.16 seconds
Started Aug 14 05:33:49 PM PDT 24
Finished Aug 14 05:33:50 PM PDT 24
Peak memory 220020 kb
Host smart-2ffc51aa-ef35-4dd7-9528-ce048fc86e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86968204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.86968204
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.202946957
Short name T736
Test name
Test status
Simulation time 73414260 ps
CPU time 1.11 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 219488 kb
Host smart-738ea2bc-a29d-4675-9518-83a3d02d56d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202946957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.202946957
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2855562503
Short name T726
Test name
Test status
Simulation time 45061255 ps
CPU time 1.69 seconds
Started Aug 14 05:33:54 PM PDT 24
Finished Aug 14 05:33:56 PM PDT 24
Peak memory 218948 kb
Host smart-2fde1088-f8a3-48f3-ac61-ca4f6cba985b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855562503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2855562503
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.2166696060
Short name T410
Test name
Test status
Simulation time 186744151 ps
CPU time 1.09 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 220080 kb
Host smart-49b80c8e-cf8a-4393-840e-218dc584d244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166696060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2166696060
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/163.edn_alert.722696018
Short name T952
Test name
Test status
Simulation time 25277315 ps
CPU time 1.19 seconds
Started Aug 14 05:34:10 PM PDT 24
Finished Aug 14 05:34:11 PM PDT 24
Peak memory 220740 kb
Host smart-a98a8822-dd98-4d1e-baa7-86da9d8adb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722696018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.722696018
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1842228441
Short name T903
Test name
Test status
Simulation time 31709281 ps
CPU time 1 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 217644 kb
Host smart-6eda7411-9e75-4ff3-9299-cd46b662f985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842228441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1842228441
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.3010492433
Short name T192
Test name
Test status
Simulation time 43210968 ps
CPU time 1.2 seconds
Started Aug 14 05:34:09 PM PDT 24
Finished Aug 14 05:34:10 PM PDT 24
Peak memory 220704 kb
Host smart-ad361e86-3858-4412-846d-02b42143738a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010492433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3010492433
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1973814610
Short name T647
Test name
Test status
Simulation time 33334177 ps
CPU time 1.31 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 215596 kb
Host smart-9474c4a8-b2d9-4b07-b63f-bb1291c0d1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973814610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1973814610
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2666720624
Short name T500
Test name
Test status
Simulation time 82536569 ps
CPU time 1.1 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 218960 kb
Host smart-b6c08635-bfed-4d8e-a965-4e19c3aaf67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666720624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2666720624
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3267143169
Short name T908
Test name
Test status
Simulation time 33400391 ps
CPU time 1.36 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 217948 kb
Host smart-b8dd3900-8bbb-4a9b-9a8b-d8f6c67fe45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267143169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3267143169
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.925782276
Short name T148
Test name
Test status
Simulation time 40453955 ps
CPU time 1.14 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:53 PM PDT 24
Peak memory 219008 kb
Host smart-8953a7ae-4490-4e82-bb2b-84534e9683fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925782276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.925782276
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.1089881060
Short name T435
Test name
Test status
Simulation time 33816902 ps
CPU time 1.31 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 217616 kb
Host smart-5b118272-fb4d-473f-8373-475fa19f090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089881060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1089881060
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.3211261552
Short name T792
Test name
Test status
Simulation time 21047357 ps
CPU time 1.09 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:56 PM PDT 24
Peak memory 218636 kb
Host smart-b0a5b56b-b2e1-4145-8d1b-a5423d1e14cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211261552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.3211261552
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/168.edn_alert.3957315657
Short name T843
Test name
Test status
Simulation time 111921372 ps
CPU time 1.11 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 218876 kb
Host smart-f39d2b17-3bef-4cd4-933f-b0c5db6077dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957315657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3957315657
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3186419815
Short name T837
Test name
Test status
Simulation time 23870821 ps
CPU time 1.06 seconds
Started Aug 14 05:33:51 PM PDT 24
Finished Aug 14 05:33:52 PM PDT 24
Peak memory 217576 kb
Host smart-5e3d1774-9431-4fc5-810d-8c47aefac82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186419815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3186419815
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.3848677491
Short name T120
Test name
Test status
Simulation time 336653856 ps
CPU time 1.3 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 219708 kb
Host smart-6d62a7e5-e432-4e8c-8486-d5ea0a6c154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848677491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3848677491
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.2710006788
Short name T474
Test name
Test status
Simulation time 77337528 ps
CPU time 1.15 seconds
Started Aug 14 05:33:54 PM PDT 24
Finished Aug 14 05:33:56 PM PDT 24
Peak memory 220236 kb
Host smart-19d214fb-a881-4b5c-8f7e-03bfe806893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710006788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2710006788
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3098590987
Short name T489
Test name
Test status
Simulation time 132861362 ps
CPU time 1.2 seconds
Started Aug 14 05:32:19 PM PDT 24
Finished Aug 14 05:32:20 PM PDT 24
Peak memory 220056 kb
Host smart-ba518fc5-d14d-4b4b-b233-23817586179e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098590987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3098590987
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.4273507256
Short name T869
Test name
Test status
Simulation time 50115737 ps
CPU time 0.91 seconds
Started Aug 14 05:32:24 PM PDT 24
Finished Aug 14 05:32:25 PM PDT 24
Peak memory 215512 kb
Host smart-6a7da6b9-8fe8-467a-bcdf-e63d2c38909c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273507256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.4273507256
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1115093159
Short name T673
Test name
Test status
Simulation time 29324512 ps
CPU time 0.83 seconds
Started Aug 14 05:32:26 PM PDT 24
Finished Aug 14 05:32:27 PM PDT 24
Peak memory 216544 kb
Host smart-4febd83c-2edc-4bc2-a482-78cb266d2240
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115093159 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1115093159
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.408148349
Short name T153
Test name
Test status
Simulation time 59733616 ps
CPU time 1.21 seconds
Started Aug 14 05:32:22 PM PDT 24
Finished Aug 14 05:32:23 PM PDT 24
Peak memory 219052 kb
Host smart-e4a8c374-da8a-4836-b5cd-9421ca870fca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408148349 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.408148349
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.605890117
Short name T552
Test name
Test status
Simulation time 18388781 ps
CPU time 1.04 seconds
Started Aug 14 05:32:19 PM PDT 24
Finished Aug 14 05:32:20 PM PDT 24
Peak memory 218532 kb
Host smart-91e20711-1e47-43c6-815e-e5aa83a33004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605890117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.605890117
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.955123922
Short name T482
Test name
Test status
Simulation time 64500935 ps
CPU time 1.18 seconds
Started Aug 14 05:32:23 PM PDT 24
Finished Aug 14 05:32:25 PM PDT 24
Peak memory 219020 kb
Host smart-1650a5b0-6107-49c5-a145-787620139ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955123922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.955123922
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1461053439
Short name T62
Test name
Test status
Simulation time 32984179 ps
CPU time 1 seconds
Started Aug 14 05:32:22 PM PDT 24
Finished Aug 14 05:32:23 PM PDT 24
Peak memory 224272 kb
Host smart-39922c4d-4e7d-471a-8204-7bc9a9268b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461053439 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1461053439
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.4006233998
Short name T674
Test name
Test status
Simulation time 30959067 ps
CPU time 1.01 seconds
Started Aug 14 05:32:26 PM PDT 24
Finished Aug 14 05:32:27 PM PDT 24
Peak memory 215608 kb
Host smart-b3a9ef1c-69f8-44d6-9645-3f4a0b261c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006233998 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4006233998
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2104821617
Short name T507
Test name
Test status
Simulation time 226329918 ps
CPU time 4.91 seconds
Started Aug 14 05:32:24 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 220544 kb
Host smart-14d4bc7b-e4bc-4641-a6a5-6c29c7912e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104821617 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2104821617
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2043838651
Short name T801
Test name
Test status
Simulation time 17073765480 ps
CPU time 59.58 seconds
Started Aug 14 05:32:28 PM PDT 24
Finished Aug 14 05:33:28 PM PDT 24
Peak memory 218924 kb
Host smart-930f14d9-034b-4188-ac5e-093753df9a71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043838651 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2043838651
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2541689607
Short name T581
Test name
Test status
Simulation time 26976173 ps
CPU time 1.27 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:56 PM PDT 24
Peak memory 220216 kb
Host smart-15eb7e9d-5396-4424-b32e-4f4950b511ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541689607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2541689607
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.3754452614
Short name T830
Test name
Test status
Simulation time 27822747 ps
CPU time 1.34 seconds
Started Aug 14 05:34:05 PM PDT 24
Finished Aug 14 05:34:12 PM PDT 24
Peak memory 217756 kb
Host smart-0a8cf27d-f5bd-4506-bd90-063e06386bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754452614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3754452614
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1021574361
Short name T614
Test name
Test status
Simulation time 23104179 ps
CPU time 1.22 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 218888 kb
Host smart-151398bb-a218-4774-91dc-976e62fbe579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021574361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1021574361
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1302203816
Short name T834
Test name
Test status
Simulation time 53959055 ps
CPU time 1.33 seconds
Started Aug 14 05:34:05 PM PDT 24
Finished Aug 14 05:34:06 PM PDT 24
Peak memory 219176 kb
Host smart-b79518cf-aaa6-4ebe-a312-bfbb3078c5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302203816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1302203816
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.672630086
Short name T933
Test name
Test status
Simulation time 21281275 ps
CPU time 1.08 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 218732 kb
Host smart-5af9572f-df00-4528-a9ac-702080fdd8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672630086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.672630086
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1877196968
Short name T629
Test name
Test status
Simulation time 358451420 ps
CPU time 3.89 seconds
Started Aug 14 05:34:03 PM PDT 24
Finished Aug 14 05:34:07 PM PDT 24
Peak memory 220544 kb
Host smart-f62e74a7-562f-405e-a604-bcd1d3f793bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877196968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1877196968
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3843013073
Short name T339
Test name
Test status
Simulation time 139159527 ps
CPU time 1.95 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 220328 kb
Host smart-2d39ed81-da0d-4b69-bbaf-4b84b7fe795f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843013073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3843013073
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.2914554003
Short name T747
Test name
Test status
Simulation time 37148943 ps
CPU time 1.26 seconds
Started Aug 14 05:33:54 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 219476 kb
Host smart-ed1a027d-d3dd-4b5f-a80e-65093ec0c002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914554003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.2914554003
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.169161583
Short name T298
Test name
Test status
Simulation time 61175093 ps
CPU time 1.38 seconds
Started Aug 14 05:33:50 PM PDT 24
Finished Aug 14 05:33:51 PM PDT 24
Peak memory 218816 kb
Host smart-46a34251-0c23-4d8a-9d5b-739b602676a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169161583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.169161583
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.382487974
Short name T604
Test name
Test status
Simulation time 40194341 ps
CPU time 1.1 seconds
Started Aug 14 05:34:05 PM PDT 24
Finished Aug 14 05:34:06 PM PDT 24
Peak memory 221076 kb
Host smart-e8473f7f-ec1b-479d-92f9-84af1c5ab657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382487974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.382487974
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.1932831037
Short name T232
Test name
Test status
Simulation time 85374584 ps
CPU time 2.02 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219104 kb
Host smart-28d87bcc-1a49-4839-a58d-5dcb501b748d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932831037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1932831037
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.3416300502
Short name T799
Test name
Test status
Simulation time 45501301 ps
CPU time 1.22 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 219544 kb
Host smart-6983c5a4-097f-412b-89c1-ad4230ca8da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416300502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3416300502
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.4214739840
Short name T495
Test name
Test status
Simulation time 46050272 ps
CPU time 1.2 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 220268 kb
Host smart-096bda30-3485-4b5f-a34b-7f9a53eee496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214739840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.4214739840
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.4140178683
Short name T480
Test name
Test status
Simulation time 69614191 ps
CPU time 1.24 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 219448 kb
Host smart-e5b5f183-a14a-4cdd-b1dc-38eeab037ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140178683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.4140178683
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2465891098
Short name T718
Test name
Test status
Simulation time 88634613 ps
CPU time 1.11 seconds
Started Aug 14 05:33:49 PM PDT 24
Finished Aug 14 05:33:50 PM PDT 24
Peak memory 217744 kb
Host smart-5aa2a76a-732f-4a03-bbb5-5633235eddc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465891098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2465891098
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2951950443
Short name T230
Test name
Test status
Simulation time 26975598 ps
CPU time 1.29 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219040 kb
Host smart-3fed4d1f-0d57-452d-acac-977465382838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951950443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2951950443
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.4096601520
Short name T657
Test name
Test status
Simulation time 194833093 ps
CPU time 2.91 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 220672 kb
Host smart-99b16e02-31c4-4f00-8fca-d178b2dacc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096601520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.4096601520
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3865503744
Short name T659
Test name
Test status
Simulation time 29931111 ps
CPU time 1.28 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 220424 kb
Host smart-6d1f1449-ace0-46b1-9b5b-c53f44c57947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865503744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3865503744
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2925186668
Short name T436
Test name
Test status
Simulation time 36387135 ps
CPU time 1.26 seconds
Started Aug 14 05:34:02 PM PDT 24
Finished Aug 14 05:34:04 PM PDT 24
Peak memory 220280 kb
Host smart-d2331178-71fd-4f5c-a8dd-25547eec7970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925186668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2925186668
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.566695818
Short name T565
Test name
Test status
Simulation time 59349072 ps
CPU time 1.21 seconds
Started Aug 14 05:32:23 PM PDT 24
Finished Aug 14 05:32:24 PM PDT 24
Peak memory 219016 kb
Host smart-aefc8df4-addc-4fe7-a2c2-69df538c695c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566695818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.566695818
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.385977690
Short name T766
Test name
Test status
Simulation time 50580620 ps
CPU time 0.85 seconds
Started Aug 14 05:32:23 PM PDT 24
Finished Aug 14 05:32:24 PM PDT 24
Peak memory 206884 kb
Host smart-8e4898bc-21ca-4aaa-a8d1-d61885d29ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385977690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.385977690
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1775416800
Short name T210
Test name
Test status
Simulation time 12099238 ps
CPU time 0.91 seconds
Started Aug 14 05:32:18 PM PDT 24
Finished Aug 14 05:32:19 PM PDT 24
Peak memory 216988 kb
Host smart-290ba9e9-0626-45d4-afe1-5dc52a36b849
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775416800 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1775416800
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2405922847
Short name T870
Test name
Test status
Simulation time 66361347 ps
CPU time 1.1 seconds
Started Aug 14 05:32:26 PM PDT 24
Finished Aug 14 05:32:27 PM PDT 24
Peak memory 217364 kb
Host smart-40222052-5c2d-4ad0-850f-94a5dc2613f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405922847 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2405922847
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.4273775327
Short name T778
Test name
Test status
Simulation time 27952469 ps
CPU time 1.03 seconds
Started Aug 14 05:32:23 PM PDT 24
Finished Aug 14 05:32:24 PM PDT 24
Peak memory 219916 kb
Host smart-f172c5a8-8862-416f-90cd-4e83013198df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273775327 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.4273775327
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.3703330986
Short name T85
Test name
Test status
Simulation time 77620158 ps
CPU time 0.84 seconds
Started Aug 14 05:32:21 PM PDT 24
Finished Aug 14 05:32:22 PM PDT 24
Peak memory 215604 kb
Host smart-36c1ef43-99c8-4b67-9383-336ca3153450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703330986 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3703330986
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1543320036
Short name T748
Test name
Test status
Simulation time 15550793 ps
CPU time 1 seconds
Started Aug 14 05:32:23 PM PDT 24
Finished Aug 14 05:32:24 PM PDT 24
Peak memory 215572 kb
Host smart-72e05454-96e4-44dd-acfe-2ebc95cad1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543320036 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1543320036
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2621200684
Short name T80
Test name
Test status
Simulation time 140465756 ps
CPU time 2.08 seconds
Started Aug 14 05:32:21 PM PDT 24
Finished Aug 14 05:32:23 PM PDT 24
Peak memory 217512 kb
Host smart-2f5f26cc-0881-491d-8021-64f008305b90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621200684 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2621200684
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/180.edn_alert.1648766878
Short name T75
Test name
Test status
Simulation time 49105305 ps
CPU time 1.14 seconds
Started Aug 14 05:34:25 PM PDT 24
Finished Aug 14 05:34:26 PM PDT 24
Peak memory 219176 kb
Host smart-63654384-863b-41d3-b28a-e44ffe36faa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648766878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1648766878
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2578376502
Short name T115
Test name
Test status
Simulation time 125444792 ps
CPU time 1.05 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:54 PM PDT 24
Peak memory 217624 kb
Host smart-fa5a17d8-8ee1-4a71-a870-cdb40123b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578376502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2578376502
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2046688372
Short name T633
Test name
Test status
Simulation time 24729324 ps
CPU time 1.28 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219096 kb
Host smart-2015b6e7-3fea-4a0e-be94-41f961adba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046688372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2046688372
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3502483624
Short name T751
Test name
Test status
Simulation time 52264677 ps
CPU time 1.43 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 218820 kb
Host smart-bd6963db-f63c-49bb-8c2d-3a7362c97331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502483624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3502483624
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.1008585838
Short name T684
Test name
Test status
Simulation time 75061393 ps
CPU time 1.05 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 220256 kb
Host smart-5c8103b3-19e8-411a-bf15-344bab6130fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008585838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.1008585838
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1507418056
Short name T927
Test name
Test status
Simulation time 64552289 ps
CPU time 1.59 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:54 PM PDT 24
Peak memory 218912 kb
Host smart-25411769-ca78-46e5-9f46-0b13c9fdd346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507418056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1507418056
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1710679278
Short name T884
Test name
Test status
Simulation time 28420075 ps
CPU time 1.18 seconds
Started Aug 14 05:34:01 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 218724 kb
Host smart-e5c85df4-40a4-4106-84d6-f440acf7db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710679278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1710679278
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.1914782906
Short name T404
Test name
Test status
Simulation time 86193676 ps
CPU time 0.99 seconds
Started Aug 14 05:34:01 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 217500 kb
Host smart-bed97c7b-7ce6-4e3c-ae37-e369d52da634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914782906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1914782906
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3734017
Short name T471
Test name
Test status
Simulation time 154862470 ps
CPU time 1.17 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219644 kb
Host smart-fa5af6c2-c3cb-473d-a3b1-e4731c1108cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3734017
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.3110742689
Short name T699
Test name
Test status
Simulation time 45285263 ps
CPU time 1.57 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 218768 kb
Host smart-b2be40c2-12d4-4e13-b429-c074340fd221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110742689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3110742689
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.1577872473
Short name T690
Test name
Test status
Simulation time 29483192 ps
CPU time 1.12 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 221076 kb
Host smart-16e949be-f058-44c0-82bb-be799ba4400b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577872473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1577872473
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2832045786
Short name T964
Test name
Test status
Simulation time 35137809 ps
CPU time 1.34 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:53 PM PDT 24
Peak memory 217648 kb
Host smart-c446a58f-b5d5-4bba-a1ac-870a976e1503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832045786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2832045786
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.1264735345
Short name T266
Test name
Test status
Simulation time 45965762 ps
CPU time 1.2 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:54 PM PDT 24
Peak memory 218872 kb
Host smart-7029dd2f-25bb-4906-8ef2-058b10da3109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264735345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.1264735345
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.298822975
Short name T820
Test name
Test status
Simulation time 55119861 ps
CPU time 1.47 seconds
Started Aug 14 05:34:02 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 218852 kb
Host smart-5d99df7f-9b42-42cc-b628-6fc56851eb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298822975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.298822975
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1546253362
Short name T269
Test name
Test status
Simulation time 267769706 ps
CPU time 1.4 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 218932 kb
Host smart-66fc348f-ea30-46d3-9e2e-e76826066167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546253362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1546253362
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3340753801
Short name T580
Test name
Test status
Simulation time 60425745 ps
CPU time 1.14 seconds
Started Aug 14 05:34:07 PM PDT 24
Finished Aug 14 05:34:08 PM PDT 24
Peak memory 217572 kb
Host smart-df4a5ef2-e93f-4bf4-aa79-28624714d757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340753801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3340753801
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.747630977
Short name T668
Test name
Test status
Simulation time 26854149 ps
CPU time 1.24 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219796 kb
Host smart-52c44b16-b956-41eb-bae7-1ca1750c6111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747630977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.747630977
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.881606463
Short name T505
Test name
Test status
Simulation time 40965751 ps
CPU time 1.75 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 218756 kb
Host smart-c9b46e44-9f8b-41a6-8067-6992d23b95c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881606463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.881606463
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2573866231
Short name T52
Test name
Test status
Simulation time 24297623 ps
CPU time 1.13 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 218840 kb
Host smart-9e29cbb1-5a71-47e8-b246-398e0d4b7b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573866231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2573866231
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.3116734615
Short name T366
Test name
Test status
Simulation time 67447440 ps
CPU time 1.64 seconds
Started Aug 14 05:34:01 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 220436 kb
Host smart-6e92b172-098e-486a-8092-f0bc8dd7a494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116734615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3116734615
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2736001226
Short name T259
Test name
Test status
Simulation time 72468111 ps
CPU time 1.14 seconds
Started Aug 14 05:32:43 PM PDT 24
Finished Aug 14 05:32:44 PM PDT 24
Peak memory 220220 kb
Host smart-7569f14a-eac1-49d7-8f19-89d3cfbf429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736001226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2736001226
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.135988306
Short name T965
Test name
Test status
Simulation time 23435276 ps
CPU time 0.87 seconds
Started Aug 14 05:32:39 PM PDT 24
Finished Aug 14 05:32:40 PM PDT 24
Peak memory 206868 kb
Host smart-57439c87-e185-4032-b172-100d1133c0d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135988306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.135988306
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.851199808
Short name T215
Test name
Test status
Simulation time 28053131 ps
CPU time 0.83 seconds
Started Aug 14 05:32:29 PM PDT 24
Finished Aug 14 05:32:30 PM PDT 24
Peak memory 216788 kb
Host smart-ad1214e0-3a7e-443c-90d9-0726fc32785a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851199808 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.851199808
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3906979466
Short name T107
Test name
Test status
Simulation time 26183262 ps
CPU time 1.13 seconds
Started Aug 14 05:32:40 PM PDT 24
Finished Aug 14 05:32:41 PM PDT 24
Peak memory 218788 kb
Host smart-06c1212c-e652-4ec7-87c5-3c261053e865
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906979466 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3906979466
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3439342453
Short name T693
Test name
Test status
Simulation time 19612201 ps
CPU time 1.08 seconds
Started Aug 14 05:32:35 PM PDT 24
Finished Aug 14 05:32:37 PM PDT 24
Peak memory 224160 kb
Host smart-0b4de423-2e38-4fa5-9752-9a3654a658f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439342453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3439342453
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.951567742
Short name T74
Test name
Test status
Simulation time 61979251 ps
CPU time 1.21 seconds
Started Aug 14 05:32:19 PM PDT 24
Finished Aug 14 05:32:20 PM PDT 24
Peak memory 219764 kb
Host smart-10fb2379-1fa8-4449-9aca-8c0a228dfb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951567742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.951567742
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2418641655
Short name T384
Test name
Test status
Simulation time 44499364 ps
CPU time 0.93 seconds
Started Aug 14 05:32:29 PM PDT 24
Finished Aug 14 05:32:30 PM PDT 24
Peak memory 215912 kb
Host smart-d6a8de16-f010-4e9d-a8a4-a34ba3065697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418641655 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2418641655
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2111245703
Short name T592
Test name
Test status
Simulation time 23329828 ps
CPU time 0.93 seconds
Started Aug 14 05:32:24 PM PDT 24
Finished Aug 14 05:32:25 PM PDT 24
Peak memory 215612 kb
Host smart-2f83ccc0-09d2-494f-b7a2-63a4c8f88271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111245703 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2111245703
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3521039880
Short name T2
Test name
Test status
Simulation time 485150162 ps
CPU time 3.8 seconds
Started Aug 14 05:32:29 PM PDT 24
Finished Aug 14 05:32:33 PM PDT 24
Peak memory 217632 kb
Host smart-8b9c78dc-5f6e-40c3-bfd4-846a75e25903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521039880 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3521039880
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1780309120
Short name T245
Test name
Test status
Simulation time 4769535392 ps
CPU time 104.48 seconds
Started Aug 14 05:32:28 PM PDT 24
Finished Aug 14 05:34:13 PM PDT 24
Peak memory 224084 kb
Host smart-a4f56215-ebf1-4055-8192-a90aaddeef8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780309120 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1780309120
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2062810084
Short name T598
Test name
Test status
Simulation time 28581584 ps
CPU time 1.13 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 221056 kb
Host smart-db6fe223-694e-4698-a037-7d19b049829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062810084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2062810084
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3247373599
Short name T740
Test name
Test status
Simulation time 69439857 ps
CPU time 1.47 seconds
Started Aug 14 05:34:01 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 219768 kb
Host smart-0dd10004-d223-4922-8407-aa2968e0770c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247373599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3247373599
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.496057104
Short name T469
Test name
Test status
Simulation time 70814554 ps
CPU time 1.13 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 221120 kb
Host smart-b261138a-d0fa-4f33-8c57-61029ab0a728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496057104 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.496057104
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.1071622359
Short name T873
Test name
Test status
Simulation time 172904513 ps
CPU time 1.04 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 217556 kb
Host smart-84c652c5-ca54-4eb7-9d8c-8ac5c897d79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071622359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1071622359
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2348077333
Short name T724
Test name
Test status
Simulation time 95045045 ps
CPU time 1.27 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 221304 kb
Host smart-188165ba-df78-4402-9980-49127dae64a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348077333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2348077333
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3128646124
Short name T798
Test name
Test status
Simulation time 53107329 ps
CPU time 1.35 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 218924 kb
Host smart-2b742a49-7052-4970-815e-b0feab04a943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128646124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3128646124
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.3376577306
Short name T910
Test name
Test status
Simulation time 112021181 ps
CPU time 1.28 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 216016 kb
Host smart-cdcba0c8-4df2-48e6-8e26-b746914fd39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376577306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.3376577306
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.549875903
Short name T753
Test name
Test status
Simulation time 47595616 ps
CPU time 1.27 seconds
Started Aug 14 05:33:55 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219024 kb
Host smart-8212d95b-b104-41f4-a879-fba931cec9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549875903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.549875903
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.3834683161
Short name T895
Test name
Test status
Simulation time 41102186 ps
CPU time 1.22 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 218972 kb
Host smart-382244ea-4510-4e25-a834-e2ba190c536e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834683161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3834683161
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2276213580
Short name T521
Test name
Test status
Simulation time 395775105 ps
CPU time 3.63 seconds
Started Aug 14 05:33:51 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 220480 kb
Host smart-005546d5-a088-420f-bc74-8f613b75392c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276213580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2276213580
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.4131678677
Short name T451
Test name
Test status
Simulation time 107636870 ps
CPU time 1.11 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 220036 kb
Host smart-0577defd-68a7-4fb0-a811-28b9e02217a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131678677 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.4131678677
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1111041248
Short name T50
Test name
Test status
Simulation time 39013316 ps
CPU time 1.37 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 218820 kb
Host smart-f82a8407-660b-44b3-b6c9-a82a3d03362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111041248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1111041248
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2554775512
Short name T961
Test name
Test status
Simulation time 31613336 ps
CPU time 1.27 seconds
Started Aug 14 05:34:12 PM PDT 24
Finished Aug 14 05:34:14 PM PDT 24
Peak memory 217668 kb
Host smart-0bf95421-117a-446f-9152-a8a8461386cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554775512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2554775512
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.27408269
Short name T422
Test name
Test status
Simulation time 67264783 ps
CPU time 2.29 seconds
Started Aug 14 05:33:50 PM PDT 24
Finished Aug 14 05:33:53 PM PDT 24
Peak memory 220496 kb
Host smart-3f5401fe-eba7-4623-9c9b-fe23856492f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27408269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.27408269
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2704622795
Short name T967
Test name
Test status
Simulation time 96027425 ps
CPU time 1.11 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 219400 kb
Host smart-ad9392cc-69eb-4b95-8f5e-8f22783ebd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704622795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2704622795
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.671796381
Short name T922
Test name
Test status
Simulation time 41815818 ps
CPU time 1.15 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219532 kb
Host smart-2d5259fb-a3b1-4d01-a3eb-8e93585d10ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671796381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.671796381
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1524750868
Short name T882
Test name
Test status
Simulation time 66542996 ps
CPU time 0.99 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 217540 kb
Host smart-218e6e2b-1a80-420e-8f26-165235e1dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524750868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1524750868
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.343167204
Short name T441
Test name
Test status
Simulation time 35405254 ps
CPU time 1.12 seconds
Started Aug 14 05:31:55 PM PDT 24
Finished Aug 14 05:31:57 PM PDT 24
Peak memory 219984 kb
Host smart-f90c5716-83a5-4dbb-86c9-34e46f8ba7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343167204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.343167204
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3163957038
Short name T826
Test name
Test status
Simulation time 17344460 ps
CPU time 0.96 seconds
Started Aug 14 05:31:52 PM PDT 24
Finished Aug 14 05:31:54 PM PDT 24
Peak memory 215468 kb
Host smart-4544c119-8614-4064-82a7-ae2956e577e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163957038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3163957038
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2034729609
Short name T603
Test name
Test status
Simulation time 72448996 ps
CPU time 0.83 seconds
Started Aug 14 05:31:54 PM PDT 24
Finished Aug 14 05:31:55 PM PDT 24
Peak memory 216592 kb
Host smart-8ce770a1-8291-4422-9982-786483dd88fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034729609 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2034729609
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.875555668
Short name T579
Test name
Test status
Simulation time 38366473 ps
CPU time 1.07 seconds
Started Aug 14 05:31:54 PM PDT 24
Finished Aug 14 05:31:55 PM PDT 24
Peak memory 218772 kb
Host smart-8a777ed2-cd78-42b2-9caf-5929b72e21c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875555668 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.875555668
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.4095077162
Short name T130
Test name
Test status
Simulation time 34030378 ps
CPU time 0.94 seconds
Started Aug 14 05:32:03 PM PDT 24
Finished Aug 14 05:32:04 PM PDT 24
Peak memory 220084 kb
Host smart-2b7bed3c-321f-48b0-a209-07dc31344f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095077162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4095077162
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3582025402
Short name T497
Test name
Test status
Simulation time 46018934 ps
CPU time 1.58 seconds
Started Aug 14 05:31:51 PM PDT 24
Finished Aug 14 05:31:53 PM PDT 24
Peak memory 218736 kb
Host smart-25ce1a0f-02a1-4b38-badf-4b4c92aaa1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582025402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3582025402
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1214481107
Short name T786
Test name
Test status
Simulation time 44057697 ps
CPU time 0.93 seconds
Started Aug 14 05:31:50 PM PDT 24
Finished Aug 14 05:31:52 PM PDT 24
Peak memory 215752 kb
Host smart-78ad15f4-840e-439a-ac70-8ef6f6ab61bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214481107 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1214481107
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1191199877
Short name T31
Test name
Test status
Simulation time 16204045 ps
CPU time 0.98 seconds
Started Aug 14 05:31:49 PM PDT 24
Finished Aug 14 05:31:50 PM PDT 24
Peak memory 207352 kb
Host smart-c60c22fe-1936-4c6c-8b15-46b4ee91bec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191199877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1191199877
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2563662761
Short name T70
Test name
Test status
Simulation time 444935264 ps
CPU time 4.16 seconds
Started Aug 14 05:32:00 PM PDT 24
Finished Aug 14 05:32:04 PM PDT 24
Peak memory 239324 kb
Host smart-8d55c952-e2c6-4787-b6ea-636741902f7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563662761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2563662761
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.879215935
Short name T560
Test name
Test status
Simulation time 26875367 ps
CPU time 0.98 seconds
Started Aug 14 05:31:51 PM PDT 24
Finished Aug 14 05:31:52 PM PDT 24
Peak memory 215592 kb
Host smart-0336482c-1ebb-4d21-9a3a-b8de7af6a6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879215935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.879215935
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.4158864210
Short name T847
Test name
Test status
Simulation time 870480414 ps
CPU time 4.96 seconds
Started Aug 14 05:31:54 PM PDT 24
Finished Aug 14 05:32:00 PM PDT 24
Peak memory 217776 kb
Host smart-b5f74eca-c734-4ca8-b212-dd76154f6197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158864210 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.4158864210
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.611795591
Short name T780
Test name
Test status
Simulation time 2451251525 ps
CPU time 57.73 seconds
Started Aug 14 05:31:50 PM PDT 24
Finished Aug 14 05:32:49 PM PDT 24
Peak memory 220860 kb
Host smart-bb53dea7-a31c-48f2-a49f-7c122244eb36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611795591 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.611795591
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1786789816
Short name T942
Test name
Test status
Simulation time 82522622 ps
CPU time 1.08 seconds
Started Aug 14 05:32:28 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 218944 kb
Host smart-f2ce668a-d680-4174-a81b-86da9a70fc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786789816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1786789816
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2520758164
Short name T635
Test name
Test status
Simulation time 30242844 ps
CPU time 0.88 seconds
Started Aug 14 05:32:45 PM PDT 24
Finished Aug 14 05:32:45 PM PDT 24
Peak memory 207084 kb
Host smart-bd302f1c-ac78-4f59-98da-cbf2311310ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520758164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2520758164
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2049620755
Short name T796
Test name
Test status
Simulation time 83772555 ps
CPU time 1.07 seconds
Started Aug 14 05:32:48 PM PDT 24
Finished Aug 14 05:32:50 PM PDT 24
Peak memory 217104 kb
Host smart-27c8a75d-99cb-45f5-825d-e03a2484aca2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049620755 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2049620755
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1519659778
Short name T494
Test name
Test status
Simulation time 28855461 ps
CPU time 0.89 seconds
Started Aug 14 05:32:55 PM PDT 24
Finished Aug 14 05:32:56 PM PDT 24
Peak memory 218524 kb
Host smart-b8966395-e60c-4909-9417-8a673dbd2c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519659778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1519659778
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.381485340
Short name T841
Test name
Test status
Simulation time 112835008 ps
CPU time 1.14 seconds
Started Aug 14 05:32:39 PM PDT 24
Finished Aug 14 05:32:40 PM PDT 24
Peak memory 217472 kb
Host smart-d26f020c-d534-42a2-bd6b-641843733b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381485340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.381485340
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3205805824
Short name T379
Test name
Test status
Simulation time 20768422 ps
CPU time 1.1 seconds
Started Aug 14 05:32:49 PM PDT 24
Finished Aug 14 05:32:50 PM PDT 24
Peak memory 215672 kb
Host smart-9bd5cfc1-0d51-412c-8c85-33f2b7324183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205805824 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3205805824
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.639268830
Short name T672
Test name
Test status
Simulation time 35196977 ps
CPU time 0.95 seconds
Started Aug 14 05:32:30 PM PDT 24
Finished Aug 14 05:32:31 PM PDT 24
Peak memory 215560 kb
Host smart-c8b9dd31-5687-4f89-90b4-196cfe244c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639268830 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.639268830
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3462904973
Short name T975
Test name
Test status
Simulation time 76674304 ps
CPU time 2.06 seconds
Started Aug 14 05:32:37 PM PDT 24
Finished Aug 14 05:32:39 PM PDT 24
Peak memory 217656 kb
Host smart-d5237d31-a54d-41fe-9adb-35966473e40f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462904973 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3462904973
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2770249499
Short name T767
Test name
Test status
Simulation time 20104442697 ps
CPU time 30.97 seconds
Started Aug 14 05:32:29 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 222084 kb
Host smart-cc4f45c0-dad8-4c55-84f2-5d11259298c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770249499 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2770249499
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1109842104
Short name T318
Test name
Test status
Simulation time 73122675 ps
CPU time 1.21 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 217456 kb
Host smart-9fbbf9ac-797d-4ca8-9697-5a31ade97384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109842104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1109842104
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1480793394
Short name T468
Test name
Test status
Simulation time 43238252 ps
CPU time 1.15 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 217784 kb
Host smart-fcf12b33-384e-41ce-8b1b-3ce791948c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480793394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1480793394
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.92848532
Short name T822
Test name
Test status
Simulation time 152761663 ps
CPU time 1.31 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 218944 kb
Host smart-46dfa45f-9d08-4b2b-bf7d-becfc6462b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92848532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.92848532
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2501215969
Short name T899
Test name
Test status
Simulation time 28083287 ps
CPU time 1.32 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 218712 kb
Host smart-32672a9c-951a-41f6-b90d-bcb3f943d701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501215969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2501215969
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.147741762
Short name T701
Test name
Test status
Simulation time 46096204 ps
CPU time 1.26 seconds
Started Aug 14 05:33:51 PM PDT 24
Finished Aug 14 05:33:52 PM PDT 24
Peak memory 220192 kb
Host smart-fb3c642a-de9b-41d4-b5a0-f887b349f397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147741762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.147741762
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1503104615
Short name T634
Test name
Test status
Simulation time 54146065 ps
CPU time 1.3 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 218980 kb
Host smart-06550ef2-a195-40c2-9eca-db5a7da78813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503104615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1503104615
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2421446817
Short name T414
Test name
Test status
Simulation time 54732608 ps
CPU time 1.12 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:53 PM PDT 24
Peak memory 217656 kb
Host smart-d93687f8-5aa4-4781-85f7-5817a1ff4aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421446817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2421446817
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.73934047
Short name T900
Test name
Test status
Simulation time 36080674 ps
CPU time 1.37 seconds
Started Aug 14 05:33:54 PM PDT 24
Finished Aug 14 05:33:56 PM PDT 24
Peak memory 218936 kb
Host smart-f60e6895-dd73-467e-b960-03a3b1560d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73934047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.73934047
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3919904337
Short name T734
Test name
Test status
Simulation time 83430933 ps
CPU time 1.1 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:53 PM PDT 24
Peak memory 217432 kb
Host smart-f3438a23-f875-4433-b64e-718a98207dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919904337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3919904337
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.4058108138
Short name T872
Test name
Test status
Simulation time 35497549 ps
CPU time 1.05 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:32:59 PM PDT 24
Peak memory 219012 kb
Host smart-1c78292f-507d-46b6-b54a-c9a1a0998540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058108138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.4058108138
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2710306855
Short name T628
Test name
Test status
Simulation time 112057266 ps
CPU time 0.79 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 206756 kb
Host smart-aee49961-02e7-49bf-b479-dc2a5c75d94f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710306855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2710306855
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1446902377
Short name T186
Test name
Test status
Simulation time 12860088 ps
CPU time 0.95 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 217096 kb
Host smart-555fb5f1-4253-47c2-80e2-b48660207894
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446902377 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1446902377
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.120985544
Short name T462
Test name
Test status
Simulation time 39963887 ps
CPU time 0.98 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:32:59 PM PDT 24
Peak memory 218744 kb
Host smart-30b6504e-069a-433e-9166-185a3a5596e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120985544 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.120985544
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3282181858
Short name T832
Test name
Test status
Simulation time 56816570 ps
CPU time 1.18 seconds
Started Aug 14 05:32:30 PM PDT 24
Finished Aug 14 05:32:31 PM PDT 24
Peak memory 229820 kb
Host smart-60b3df8e-3734-48f3-8122-9f769a8be7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282181858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3282181858
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2049090804
Short name T676
Test name
Test status
Simulation time 63905969 ps
CPU time 1.21 seconds
Started Aug 14 05:32:35 PM PDT 24
Finished Aug 14 05:32:36 PM PDT 24
Peak memory 219128 kb
Host smart-149074c8-8cac-4908-8fc9-4b2880599995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049090804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2049090804
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3224198693
Short name T902
Test name
Test status
Simulation time 32068105 ps
CPU time 0.88 seconds
Started Aug 14 05:32:31 PM PDT 24
Finished Aug 14 05:32:32 PM PDT 24
Peak memory 215848 kb
Host smart-99bdc653-e900-449f-bbaa-e5db738169f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224198693 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3224198693
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2741151970
Short name T817
Test name
Test status
Simulation time 15266745 ps
CPU time 0.95 seconds
Started Aug 14 05:32:55 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 215600 kb
Host smart-d66ba3bb-7c6b-4f41-9d4c-6690457fb485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741151970 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2741151970
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2676406751
Short name T79
Test name
Test status
Simulation time 501186907 ps
CPU time 4.58 seconds
Started Aug 14 05:32:48 PM PDT 24
Finished Aug 14 05:32:52 PM PDT 24
Peak memory 220920 kb
Host smart-4824ba23-9946-47a0-a6f8-66f705f2dbfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676406751 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2676406751
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.920251703
Short name T827
Test name
Test status
Simulation time 1663374382 ps
CPU time 44.03 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:45 PM PDT 24
Peak memory 218796 kb
Host smart-7b28b48f-0121-4d2e-9de4-85024ad232b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920251703 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.920251703
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1345178589
Short name T539
Test name
Test status
Simulation time 71981895 ps
CPU time 2.27 seconds
Started Aug 14 05:33:53 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 215608 kb
Host smart-3657a7f9-a14a-4fdd-be79-fc934bb9bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345178589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1345178589
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1928064851
Short name T682
Test name
Test status
Simulation time 157037370 ps
CPU time 2.13 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 220764 kb
Host smart-eb40ee6f-a375-4658-b447-6c79eabe9e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928064851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1928064851
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1696845894
Short name T972
Test name
Test status
Simulation time 44486460 ps
CPU time 1.52 seconds
Started Aug 14 05:33:52 PM PDT 24
Finished Aug 14 05:33:54 PM PDT 24
Peak memory 220216 kb
Host smart-af0d2028-22ba-417e-bd42-17628f4b318b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696845894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1696845894
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.79403241
Short name T906
Test name
Test status
Simulation time 37392420 ps
CPU time 1.41 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 219176 kb
Host smart-8812d08e-b9a1-4785-8f1f-4a975fad61fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79403241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.79403241
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.4251789437
Short name T332
Test name
Test status
Simulation time 30740666 ps
CPU time 1.38 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 218996 kb
Host smart-88b76d88-23c7-4244-89fe-6d9d2935133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251789437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.4251789437
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3929631359
Short name T574
Test name
Test status
Simulation time 36285667 ps
CPU time 1.37 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 217576 kb
Host smart-29cae498-a489-418e-8321-c62db0e20da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929631359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3929631359
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4265724278
Short name T479
Test name
Test status
Simulation time 72496654 ps
CPU time 1.71 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 219140 kb
Host smart-ba39f4cd-67a0-47a4-829d-fdc20fc8df68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265724278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4265724278
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.163960124
Short name T374
Test name
Test status
Simulation time 31462268 ps
CPU time 1.17 seconds
Started Aug 14 05:34:19 PM PDT 24
Finished Aug 14 05:34:21 PM PDT 24
Peak memory 217568 kb
Host smart-b86a6a47-65ce-49b1-abfb-a7b875897e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163960124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.163960124
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2471368634
Short name T519
Test name
Test status
Simulation time 82829160 ps
CPU time 1.4 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219172 kb
Host smart-b088ca23-76c9-4bbf-a1c9-2bc6b48794da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471368634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2471368634
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2673980300
Short name T775
Test name
Test status
Simulation time 74569434 ps
CPU time 1.18 seconds
Started Aug 14 05:32:55 PM PDT 24
Finished Aug 14 05:32:56 PM PDT 24
Peak memory 221524 kb
Host smart-a534325d-22b8-4366-89f6-572c00ba2e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673980300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2673980300
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.957600115
Short name T82
Test name
Test status
Simulation time 14441715 ps
CPU time 0.89 seconds
Started Aug 14 05:32:51 PM PDT 24
Finished Aug 14 05:32:52 PM PDT 24
Peak memory 207332 kb
Host smart-f6650cbb-8340-4040-b80b-775d0d54147b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957600115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.957600115
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.133011183
Short name T918
Test name
Test status
Simulation time 15397570 ps
CPU time 0.88 seconds
Started Aug 14 05:32:29 PM PDT 24
Finished Aug 14 05:32:30 PM PDT 24
Peak memory 216672 kb
Host smart-de019bc1-d431-42c0-88f3-850ed62b049c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133011183 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.133011183
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1103230828
Short name T141
Test name
Test status
Simulation time 221196294 ps
CPU time 1.01 seconds
Started Aug 14 05:32:52 PM PDT 24
Finished Aug 14 05:32:53 PM PDT 24
Peak memory 217308 kb
Host smart-71f94bc4-dbdc-4a5b-8304-5e0d6ec84f05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103230828 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1103230828
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_genbits.1055210757
Short name T722
Test name
Test status
Simulation time 37453985 ps
CPU time 1.46 seconds
Started Aug 14 05:32:35 PM PDT 24
Finished Aug 14 05:32:36 PM PDT 24
Peak memory 218904 kb
Host smart-38dab01c-e6a7-4c01-bd7e-970e93928662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055210757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1055210757
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1246458664
Short name T41
Test name
Test status
Simulation time 34362810 ps
CPU time 0.9 seconds
Started Aug 14 05:32:44 PM PDT 24
Finished Aug 14 05:32:45 PM PDT 24
Peak memory 216012 kb
Host smart-bb62250a-5995-46c3-a99a-c23b5155a02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246458664 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1246458664
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3094558097
Short name T836
Test name
Test status
Simulation time 15577946 ps
CPU time 0.97 seconds
Started Aug 14 05:32:47 PM PDT 24
Finished Aug 14 05:32:48 PM PDT 24
Peak memory 215600 kb
Host smart-8c3e9d47-6ed4-462c-9dd7-72b37bf3f6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094558097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3094558097
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2086788510
Short name T855
Test name
Test status
Simulation time 29841482 ps
CPU time 1.2 seconds
Started Aug 14 05:32:53 PM PDT 24
Finished Aug 14 05:32:54 PM PDT 24
Peak memory 207148 kb
Host smart-91b88833-0d3d-4040-8dd0-a39f249c7bce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086788510 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2086788510
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/220.edn_genbits.2522399611
Short name T874
Test name
Test status
Simulation time 55984902 ps
CPU time 1.23 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:57 PM PDT 24
Peak memory 219276 kb
Host smart-e1d674f8-832c-4814-8de0-661e6778dd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522399611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2522399611
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2621846889
Short name T324
Test name
Test status
Simulation time 39392479 ps
CPU time 1.47 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 218704 kb
Host smart-47916ca6-d1f9-49e0-b084-7d895b85bf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621846889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2621846889
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.107606329
Short name T949
Test name
Test status
Simulation time 46006053 ps
CPU time 1.48 seconds
Started Aug 14 05:33:56 PM PDT 24
Finished Aug 14 05:33:58 PM PDT 24
Peak memory 218784 kb
Host smart-40f6f3e9-e4ce-41ed-bb7c-a7bf5b8c476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107606329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.107606329
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2228844754
Short name T962
Test name
Test status
Simulation time 51850297 ps
CPU time 1.61 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 218656 kb
Host smart-0f905d4d-2669-4374-b1a8-7029ff2e6ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228844754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2228844754
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.816774057
Short name T823
Test name
Test status
Simulation time 3219579103 ps
CPU time 70.02 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:35:10 PM PDT 24
Peak memory 221108 kb
Host smart-6f0997bb-982d-4250-8e1f-1e2a389aea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816774057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.816774057
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2013795829
Short name T950
Test name
Test status
Simulation time 91152498 ps
CPU time 2.98 seconds
Started Aug 14 05:34:07 PM PDT 24
Finished Aug 14 05:34:10 PM PDT 24
Peak memory 220500 kb
Host smart-3a627de0-4431-42ec-b80d-2b5f43635f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013795829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2013795829
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2358643544
Short name T544
Test name
Test status
Simulation time 87454953 ps
CPU time 1.23 seconds
Started Aug 14 05:34:08 PM PDT 24
Finished Aug 14 05:34:09 PM PDT 24
Peak memory 218776 kb
Host smart-33de2670-5609-40d4-b8ef-0c17e6528245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358643544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2358643544
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1860287628
Short name T853
Test name
Test status
Simulation time 71587176 ps
CPU time 2.33 seconds
Started Aug 14 05:34:15 PM PDT 24
Finished Aug 14 05:34:17 PM PDT 24
Peak memory 220504 kb
Host smart-90b51e88-e802-4812-a3b9-83cdfec4ce48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860287628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1860287628
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2513487228
Short name T376
Test name
Test status
Simulation time 110844141 ps
CPU time 1.43 seconds
Started Aug 14 05:33:54 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 215608 kb
Host smart-ca8255c4-9e78-410b-820f-6e79816e3867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513487228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2513487228
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3368353797
Short name T616
Test name
Test status
Simulation time 38286220 ps
CPU time 1.36 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 218600 kb
Host smart-113a59b2-1a07-4906-86df-3aea3e8be837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368353797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3368353797
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.739362027
Short name T729
Test name
Test status
Simulation time 45216769 ps
CPU time 1.2 seconds
Started Aug 14 05:32:31 PM PDT 24
Finished Aug 14 05:32:32 PM PDT 24
Peak memory 219028 kb
Host smart-8625a6ad-026c-4fc1-9040-aa7aaa2590b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739362027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.739362027
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.4135773078
Short name T784
Test name
Test status
Simulation time 38426788 ps
CPU time 0.95 seconds
Started Aug 14 05:32:49 PM PDT 24
Finished Aug 14 05:32:50 PM PDT 24
Peak memory 207164 kb
Host smart-6e727858-f1b3-48ff-bd54-5422aed284dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135773078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.4135773078
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.527513193
Short name T677
Test name
Test status
Simulation time 10777696 ps
CPU time 0.87 seconds
Started Aug 14 05:32:30 PM PDT 24
Finished Aug 14 05:32:31 PM PDT 24
Peak memory 215676 kb
Host smart-5d3f0678-ab82-4753-9ab3-873598460664
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527513193 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.527513193
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1260872926
Short name T135
Test name
Test status
Simulation time 82343094 ps
CPU time 1.3 seconds
Started Aug 14 05:32:48 PM PDT 24
Finished Aug 14 05:32:50 PM PDT 24
Peak memory 217320 kb
Host smart-108f4d85-cd56-4e51-b84f-f9ed6dbecf9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260872926 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1260872926
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.209258601
Short name T857
Test name
Test status
Simulation time 35870829 ps
CPU time 1.14 seconds
Started Aug 14 05:32:31 PM PDT 24
Finished Aug 14 05:32:32 PM PDT 24
Peak memory 220036 kb
Host smart-5d6fda98-11bd-4322-b585-e80a4a49e83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209258601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.209258601
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.389049293
Short name T308
Test name
Test status
Simulation time 80293872 ps
CPU time 2.03 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 219184 kb
Host smart-acad39e8-af0e-485c-9213-70a5b8b76907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389049293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.389049293
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.4098974687
Short name T110
Test name
Test status
Simulation time 44703082 ps
CPU time 0.87 seconds
Started Aug 14 05:32:45 PM PDT 24
Finished Aug 14 05:32:46 PM PDT 24
Peak memory 215936 kb
Host smart-a708b929-b2bb-4ba3-92d8-6e4849b4529b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098974687 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.4098974687
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2567045448
Short name T665
Test name
Test status
Simulation time 19850766 ps
CPU time 1.03 seconds
Started Aug 14 05:32:35 PM PDT 24
Finished Aug 14 05:32:36 PM PDT 24
Peak memory 215592 kb
Host smart-408aa010-09fd-4cc1-851c-f5758f244a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567045448 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2567045448
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2011627703
Short name T411
Test name
Test status
Simulation time 140949445 ps
CPU time 3.32 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 217652 kb
Host smart-a85491fe-0568-4e4d-a34d-355f4db712da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011627703 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2011627703
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.119596120
Short name T240
Test name
Test status
Simulation time 5115265153 ps
CPU time 119.56 seconds
Started Aug 14 05:32:39 PM PDT 24
Finished Aug 14 05:34:39 PM PDT 24
Peak memory 218444 kb
Host smart-e6b63abb-99f2-4f7b-bd69-16e4d7f06148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119596120 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.119596120
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2367937730
Short name T591
Test name
Test status
Simulation time 37212341 ps
CPU time 1.35 seconds
Started Aug 14 05:34:05 PM PDT 24
Finished Aug 14 05:34:07 PM PDT 24
Peak memory 217492 kb
Host smart-048f2ebd-9142-462c-a06f-6adf64fc0e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367937730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2367937730
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.4027955724
Short name T749
Test name
Test status
Simulation time 51029217 ps
CPU time 1.18 seconds
Started Aug 14 05:34:02 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 218712 kb
Host smart-5bdf5640-699c-496e-a064-e8bd497b24a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027955724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.4027955724
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1146813073
Short name T391
Test name
Test status
Simulation time 40079600 ps
CPU time 1.72 seconds
Started Aug 14 05:34:07 PM PDT 24
Finished Aug 14 05:34:09 PM PDT 24
Peak memory 218772 kb
Host smart-c9d48098-b6c1-4f6e-a630-54bd8c7fc861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146813073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1146813073
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3847857289
Short name T867
Test name
Test status
Simulation time 314539874 ps
CPU time 2.58 seconds
Started Aug 14 05:34:17 PM PDT 24
Finished Aug 14 05:34:20 PM PDT 24
Peak memory 220688 kb
Host smart-7c821f4b-c34b-48c7-878c-5453f16ad674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847857289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3847857289
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1750398040
Short name T732
Test name
Test status
Simulation time 34298150 ps
CPU time 1.26 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 218764 kb
Host smart-6e7cdece-3748-405a-8415-0cf8bbc6d5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750398040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1750398040
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.632650857
Short name T262
Test name
Test status
Simulation time 60265720 ps
CPU time 1.51 seconds
Started Aug 14 05:34:08 PM PDT 24
Finished Aug 14 05:34:09 PM PDT 24
Peak memory 218992 kb
Host smart-09ed6c79-794d-4234-9645-5d51f4e93495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632650857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.632650857
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.778508095
Short name T804
Test name
Test status
Simulation time 42859696 ps
CPU time 1.46 seconds
Started Aug 14 05:34:10 PM PDT 24
Finished Aug 14 05:34:11 PM PDT 24
Peak memory 218832 kb
Host smart-e6302d4b-30ee-4f36-805c-e270a8f03fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778508095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.778508095
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3067598891
Short name T526
Test name
Test status
Simulation time 67420379 ps
CPU time 1.33 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 217636 kb
Host smart-34ccc58e-1965-4a3b-a477-a1b15782eb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067598891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3067598891
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1078082308
Short name T879
Test name
Test status
Simulation time 9060982752 ps
CPU time 120.28 seconds
Started Aug 14 05:34:06 PM PDT 24
Finished Aug 14 05:36:07 PM PDT 24
Peak memory 220732 kb
Host smart-672b3f14-b71f-4bb7-b42c-8eed135af3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078082308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1078082308
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1932720847
Short name T844
Test name
Test status
Simulation time 83615301 ps
CPU time 1.06 seconds
Started Aug 14 05:32:31 PM PDT 24
Finished Aug 14 05:32:33 PM PDT 24
Peak memory 220228 kb
Host smart-280386f9-72b0-4810-9aa7-d3e729df204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932720847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1932720847
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2196066595
Short name T78
Test name
Test status
Simulation time 36175239 ps
CPU time 0.82 seconds
Started Aug 14 05:32:41 PM PDT 24
Finished Aug 14 05:32:42 PM PDT 24
Peak memory 206872 kb
Host smart-b01e9246-12e2-4bef-8ccd-10d63e46bbed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196066595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2196066595
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2091450036
Short name T649
Test name
Test status
Simulation time 13094530 ps
CPU time 0.91 seconds
Started Aug 14 05:32:32 PM PDT 24
Finished Aug 14 05:32:33 PM PDT 24
Peak memory 215900 kb
Host smart-4fc0f6df-0c68-446f-809c-ee7d73963301
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091450036 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2091450036
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.474903225
Short name T103
Test name
Test status
Simulation time 93018749 ps
CPU time 1.21 seconds
Started Aug 14 05:32:29 PM PDT 24
Finished Aug 14 05:32:31 PM PDT 24
Peak memory 217312 kb
Host smart-66d6a639-d43c-4999-841c-d1e9901011a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474903225 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.474903225
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3775957008
Short name T959
Test name
Test status
Simulation time 20629823 ps
CPU time 1.12 seconds
Started Aug 14 05:32:30 PM PDT 24
Finished Aug 14 05:32:32 PM PDT 24
Peak memory 224164 kb
Host smart-8c0c7316-d08f-45a6-a7ec-cf86d2f87703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775957008 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3775957008
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2570302833
Short name T464
Test name
Test status
Simulation time 103514620 ps
CPU time 1.26 seconds
Started Aug 14 05:32:32 PM PDT 24
Finished Aug 14 05:32:33 PM PDT 24
Peak memory 217628 kb
Host smart-d313bc10-680e-4fc3-9eaa-44c4457139c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570302833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2570302833
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_smoke.720849316
Short name T356
Test name
Test status
Simulation time 65686887 ps
CPU time 0.97 seconds
Started Aug 14 05:32:34 PM PDT 24
Finished Aug 14 05:32:35 PM PDT 24
Peak memory 215624 kb
Host smart-95c43e0b-d7e3-487a-9995-20792c9ed7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720849316 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.720849316
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2129619914
Short name T888
Test name
Test status
Simulation time 21142449 ps
CPU time 1 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 206868 kb
Host smart-499fbef5-e34e-4adf-9d13-134254fd2306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129619914 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2129619914
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1632484091
Short name T829
Test name
Test status
Simulation time 9017067455 ps
CPU time 65.69 seconds
Started Aug 14 05:32:36 PM PDT 24
Finished Aug 14 05:33:42 PM PDT 24
Peak memory 221852 kb
Host smart-8d050805-ae75-41a1-aa58-b99bf6970630
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632484091 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1632484091
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2775569703
Short name T602
Test name
Test status
Simulation time 73262451 ps
CPU time 1.35 seconds
Started Aug 14 05:34:47 PM PDT 24
Finished Aug 14 05:34:48 PM PDT 24
Peak memory 218984 kb
Host smart-1d1a9f45-0e4a-4d6c-9c5f-6e710f69af14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775569703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2775569703
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1525990059
Short name T924
Test name
Test status
Simulation time 71113790 ps
CPU time 1.07 seconds
Started Aug 14 05:34:06 PM PDT 24
Finished Aug 14 05:34:07 PM PDT 24
Peak memory 217748 kb
Host smart-f231a5ab-d138-4f98-be88-420884d8b6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525990059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1525990059
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.860314081
Short name T973
Test name
Test status
Simulation time 41839343 ps
CPU time 1.54 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 218964 kb
Host smart-c2ba70a2-6e32-48bb-9ba1-2426027b117f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860314081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.860314081
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1889431298
Short name T330
Test name
Test status
Simulation time 133390473 ps
CPU time 3.15 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 219804 kb
Host smart-b6805d11-e004-4617-aee5-b8d78c4cf0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889431298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1889431298
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2850169012
Short name T504
Test name
Test status
Simulation time 146536877 ps
CPU time 1 seconds
Started Aug 14 05:34:06 PM PDT 24
Finished Aug 14 05:34:07 PM PDT 24
Peak memory 215628 kb
Host smart-1119dfb6-d969-483f-8a29-f31fe58211bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850169012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2850169012
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2930429260
Short name T417
Test name
Test status
Simulation time 54500369 ps
CPU time 1.01 seconds
Started Aug 14 05:34:02 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 217800 kb
Host smart-5dea7f07-e75c-4318-ad3d-6834cdc69eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930429260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2930429260
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3126163729
Short name T412
Test name
Test status
Simulation time 45018585 ps
CPU time 1.51 seconds
Started Aug 14 05:33:58 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 217792 kb
Host smart-50dc209d-ce10-4e01-a875-2350eba3374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126163729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3126163729
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2671534174
Short name T511
Test name
Test status
Simulation time 47634145 ps
CPU time 1.3 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 219064 kb
Host smart-9d13da04-bea8-4a9c-8cad-17f2a6957274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671534174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2671534174
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3733529593
Short name T976
Test name
Test status
Simulation time 55515876 ps
CPU time 1.36 seconds
Started Aug 14 05:34:11 PM PDT 24
Finished Aug 14 05:34:13 PM PDT 24
Peak memory 218716 kb
Host smart-e8680919-7000-48ad-b147-bc1733ea2019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733529593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3733529593
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2127788782
Short name T589
Test name
Test status
Simulation time 59191510 ps
CPU time 1.74 seconds
Started Aug 14 05:34:04 PM PDT 24
Finished Aug 14 05:34:06 PM PDT 24
Peak memory 218904 kb
Host smart-91095d03-8dfe-40c5-9fee-db9e2f6d876d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127788782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2127788782
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.193500067
Short name T307
Test name
Test status
Simulation time 88681139 ps
CPU time 1.27 seconds
Started Aug 14 05:32:32 PM PDT 24
Finished Aug 14 05:32:34 PM PDT 24
Peak memory 218672 kb
Host smart-cbad3160-a5bd-436e-b90c-300bc1a602bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193500067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.193500067
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3390124524
Short name T541
Test name
Test status
Simulation time 26528612 ps
CPU time 1.06 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 215352 kb
Host smart-df09ce99-2f44-456d-99dd-b18ce0fd01de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390124524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3390124524
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3552504145
Short name T197
Test name
Test status
Simulation time 11034858 ps
CPU time 0.88 seconds
Started Aug 14 05:32:52 PM PDT 24
Finished Aug 14 05:32:53 PM PDT 24
Peak memory 216828 kb
Host smart-594285c8-4f07-49ba-a1c5-8db0d4935b50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552504145 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3552504145
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.691705516
Short name T655
Test name
Test status
Simulation time 33390570 ps
CPU time 1.24 seconds
Started Aug 14 05:32:44 PM PDT 24
Finished Aug 14 05:32:46 PM PDT 24
Peak memory 219548 kb
Host smart-beb2dbcc-a06f-48c8-8e9c-8e7b25799e1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691705516 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.691705516
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.313817595
Short name T8
Test name
Test status
Simulation time 56382358 ps
CPU time 1.11 seconds
Started Aug 14 05:32:47 PM PDT 24
Finished Aug 14 05:32:48 PM PDT 24
Peak memory 229976 kb
Host smart-f8c97aec-9469-4eb5-b9ca-1bd8c19738cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313817595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.313817595
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1046562801
Short name T816
Test name
Test status
Simulation time 99138913 ps
CPU time 1.67 seconds
Started Aug 14 05:32:30 PM PDT 24
Finished Aug 14 05:32:32 PM PDT 24
Peak memory 219240 kb
Host smart-148264b3-4730-49b3-a133-7c3451719175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046562801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1046562801
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.357378408
Short name T40
Test name
Test status
Simulation time 78200185 ps
CPU time 0.83 seconds
Started Aug 14 05:32:32 PM PDT 24
Finished Aug 14 05:32:33 PM PDT 24
Peak memory 215756 kb
Host smart-55299fdc-857f-4caf-ada6-4c6dad533f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357378408 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.357378408
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3764363767
Short name T439
Test name
Test status
Simulation time 32597217 ps
CPU time 0.96 seconds
Started Aug 14 05:32:45 PM PDT 24
Finished Aug 14 05:32:47 PM PDT 24
Peak memory 215600 kb
Host smart-a76b8761-ada3-4261-b7bf-94f0688d3ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764363767 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3764363767
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1706931756
Short name T609
Test name
Test status
Simulation time 99685081 ps
CPU time 2.44 seconds
Started Aug 14 05:32:55 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 217408 kb
Host smart-aafd3779-2c53-481f-a949-9b4bd989f2cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706931756 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1706931756
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.4072047168
Short name T576
Test name
Test status
Simulation time 4525707253 ps
CPU time 123.23 seconds
Started Aug 14 05:32:32 PM PDT 24
Finished Aug 14 05:34:35 PM PDT 24
Peak memory 218380 kb
Host smart-82a6fad7-7bb5-4411-8bfb-001123445a6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072047168 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.4072047168
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1035125218
Short name T622
Test name
Test status
Simulation time 66944181 ps
CPU time 1.15 seconds
Started Aug 14 05:34:06 PM PDT 24
Finished Aug 14 05:34:07 PM PDT 24
Peak memory 215620 kb
Host smart-302e9daf-478a-43be-b575-7127b3fc528c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035125218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1035125218
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3252967144
Short name T402
Test name
Test status
Simulation time 52794281 ps
CPU time 1.32 seconds
Started Aug 14 05:34:32 PM PDT 24
Finished Aug 14 05:34:34 PM PDT 24
Peak memory 217580 kb
Host smart-53ca0927-d7c8-4c03-a8e4-203ab84a7ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252967144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3252967144
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3089134943
Short name T974
Test name
Test status
Simulation time 51244053 ps
CPU time 1.64 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 218856 kb
Host smart-d6d7f9a9-fede-4019-9a42-459e29d708ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089134943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3089134943
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3786495576
Short name T360
Test name
Test status
Simulation time 62095081 ps
CPU time 1.32 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 220280 kb
Host smart-0024c8a7-aa74-48c1-aff5-72328d2175f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786495576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3786495576
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2921197967
Short name T346
Test name
Test status
Simulation time 48544089 ps
CPU time 1.16 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 217576 kb
Host smart-8baa0731-5b8f-4e1e-b120-4c756f8d95d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921197967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2921197967
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.796686234
Short name T553
Test name
Test status
Simulation time 34560096 ps
CPU time 1.24 seconds
Started Aug 14 05:34:04 PM PDT 24
Finished Aug 14 05:34:05 PM PDT 24
Peak memory 217652 kb
Host smart-deb5f6b1-6583-4ae4-b37d-e3033c8db028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796686234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.796686234
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3789106119
Short name T467
Test name
Test status
Simulation time 39716019 ps
CPU time 1.37 seconds
Started Aug 14 05:34:03 PM PDT 24
Finished Aug 14 05:34:04 PM PDT 24
Peak memory 217532 kb
Host smart-c075e514-dc5d-4528-b4fb-8b87359525f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789106119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3789106119
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2292037018
Short name T302
Test name
Test status
Simulation time 42045573 ps
CPU time 1.6 seconds
Started Aug 14 05:34:12 PM PDT 24
Finished Aug 14 05:34:13 PM PDT 24
Peak memory 218616 kb
Host smart-c4095946-0ad5-47ca-853a-f40798ee5b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292037018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2292037018
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1875124244
Short name T54
Test name
Test status
Simulation time 88229979 ps
CPU time 1.21 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 218852 kb
Host smart-6cd2fdfd-4dc1-4dfc-9929-6e58c32afd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875124244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1875124244
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2544610921
Short name T744
Test name
Test status
Simulation time 236770564 ps
CPU time 1.21 seconds
Started Aug 14 05:32:31 PM PDT 24
Finished Aug 14 05:32:32 PM PDT 24
Peak memory 219832 kb
Host smart-6aaf4a29-8863-4831-9f15-e5c18d2ff886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544610921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2544610921
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.195741571
Short name T702
Test name
Test status
Simulation time 79805593 ps
CPU time 0.95 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 207112 kb
Host smart-d038e868-d37c-4824-9907-b8de3ecf8b4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195741571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.195741571
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1288751545
Short name T695
Test name
Test status
Simulation time 33642964 ps
CPU time 0.87 seconds
Started Aug 14 05:32:32 PM PDT 24
Finished Aug 14 05:32:33 PM PDT 24
Peak memory 216864 kb
Host smart-216341e9-c9ca-4261-95fc-13be2383d3ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288751545 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1288751545
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3609858487
Short name T542
Test name
Test status
Simulation time 49708198 ps
CPU time 1.09 seconds
Started Aug 14 05:32:33 PM PDT 24
Finished Aug 14 05:32:34 PM PDT 24
Peak memory 217076 kb
Host smart-e45d245d-8c17-4204-a274-32b9b7a7c4fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609858487 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3609858487
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3730555977
Short name T150
Test name
Test status
Simulation time 35127057 ps
CPU time 0.95 seconds
Started Aug 14 05:32:32 PM PDT 24
Finished Aug 14 05:32:33 PM PDT 24
Peak memory 220044 kb
Host smart-5704e387-55cc-4a17-a189-c77f17b5a005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730555977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3730555977
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.249976822
Short name T578
Test name
Test status
Simulation time 147474152 ps
CPU time 1.2 seconds
Started Aug 14 05:32:46 PM PDT 24
Finished Aug 14 05:32:48 PM PDT 24
Peak memory 219456 kb
Host smart-47aedd66-4bf4-4d95-8f30-f7d1f69697f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249976822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.249976822
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2666174742
Short name T56
Test name
Test status
Simulation time 25251097 ps
CPU time 1.02 seconds
Started Aug 14 05:32:38 PM PDT 24
Finished Aug 14 05:32:44 PM PDT 24
Peak memory 224260 kb
Host smart-a02a0b7f-c17a-4684-862f-9caaaddc909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666174742 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2666174742
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.938488684
Short name T491
Test name
Test status
Simulation time 23405808 ps
CPU time 0.96 seconds
Started Aug 14 05:32:32 PM PDT 24
Finished Aug 14 05:32:33 PM PDT 24
Peak memory 215612 kb
Host smart-683ef40d-3c1f-467e-9422-7eff25a8226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938488684 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.938488684
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3342233948
Short name T255
Test name
Test status
Simulation time 123418051 ps
CPU time 1.8 seconds
Started Aug 14 05:32:49 PM PDT 24
Finished Aug 14 05:32:51 PM PDT 24
Peak memory 215520 kb
Host smart-a0e14550-8f3c-4840-8fab-0028925cd6c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342233948 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3342233948
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/260.edn_genbits.2708238576
Short name T911
Test name
Test status
Simulation time 20192137 ps
CPU time 1.02 seconds
Started Aug 14 05:34:49 PM PDT 24
Finished Aug 14 05:34:50 PM PDT 24
Peak memory 217368 kb
Host smart-4d2740c6-de00-4b26-ad6c-40cfbcda785a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708238576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2708238576
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.185846640
Short name T397
Test name
Test status
Simulation time 62995899 ps
CPU time 2.49 seconds
Started Aug 14 05:34:10 PM PDT 24
Finished Aug 14 05:34:13 PM PDT 24
Peak memory 220464 kb
Host smart-fed47cfe-1427-4139-a323-2796698c40b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185846640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.185846640
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2245641564
Short name T570
Test name
Test status
Simulation time 95146668 ps
CPU time 1.41 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 218976 kb
Host smart-616d37d5-46d3-48be-b2ab-9eb4baa8e2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245641564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2245641564
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3586872714
Short name T334
Test name
Test status
Simulation time 879540940 ps
CPU time 4.17 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 220164 kb
Host smart-f88bb12b-17b5-4b75-9d8a-3ec835d4f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586872714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3586872714
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1031474244
Short name T575
Test name
Test status
Simulation time 85734667 ps
CPU time 1.07 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 218096 kb
Host smart-a4be1fa7-7d08-40ca-b379-81a235cbf801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031474244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1031474244
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3501577636
Short name T389
Test name
Test status
Simulation time 30445701 ps
CPU time 1.24 seconds
Started Aug 14 05:34:05 PM PDT 24
Finished Aug 14 05:34:07 PM PDT 24
Peak memory 217572 kb
Host smart-61464893-7d2c-4ea7-bd8b-c15ae3b9a67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501577636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3501577636
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1207614126
Short name T347
Test name
Test status
Simulation time 24605853 ps
CPU time 1.15 seconds
Started Aug 14 05:34:07 PM PDT 24
Finished Aug 14 05:34:08 PM PDT 24
Peak memory 217548 kb
Host smart-c00cdae0-d257-4b96-9598-44eb5f46354a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207614126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1207614126
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3455138098
Short name T871
Test name
Test status
Simulation time 303026568 ps
CPU time 3.34 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 219228 kb
Host smart-638bb9f5-c7a5-438e-8a7d-b3ee0a25fafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455138098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3455138098
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.223250258
Short name T970
Test name
Test status
Simulation time 36478338 ps
CPU time 1.33 seconds
Started Aug 14 05:34:17 PM PDT 24
Finished Aug 14 05:34:19 PM PDT 24
Peak memory 218848 kb
Host smart-a78d9842-2fbc-4a01-9826-c57b93f81160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223250258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.223250258
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3378047250
Short name T382
Test name
Test status
Simulation time 206123156 ps
CPU time 2.92 seconds
Started Aug 14 05:34:26 PM PDT 24
Finished Aug 14 05:34:29 PM PDT 24
Peak memory 220500 kb
Host smart-528765b9-d842-4140-9f62-bf9c9e37d15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378047250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3378047250
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1037861732
Short name T265
Test name
Test status
Simulation time 60208845 ps
CPU time 1.08 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 218660 kb
Host smart-84e59bfa-ea86-46d1-b6cd-802e8c3d197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037861732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1037861732
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.115964773
Short name T731
Test name
Test status
Simulation time 23280780 ps
CPU time 0.97 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 207096 kb
Host smart-60aa2b7f-00a6-467b-b69e-a1ae7eb39970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115964773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.115964773
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.417191649
Short name T423
Test name
Test status
Simulation time 21711498 ps
CPU time 0.85 seconds
Started Aug 14 05:32:39 PM PDT 24
Finished Aug 14 05:32:40 PM PDT 24
Peak memory 215748 kb
Host smart-58b8cb00-04b7-41c0-bc64-4d9b91000ffc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417191649 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.417191649
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3158491562
Short name T460
Test name
Test status
Simulation time 312685260 ps
CPU time 1.16 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:59 PM PDT 24
Peak memory 217388 kb
Host smart-bb89a43b-7394-4313-8dbc-54f2f09212f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158491562 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3158491562
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2145197480
Short name T86
Test name
Test status
Simulation time 23806311 ps
CPU time 0.93 seconds
Started Aug 14 05:32:56 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 218568 kb
Host smart-584de22d-9e7b-4b3e-9ddd-532dc6833907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145197480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2145197480
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3693808206
Short name T326
Test name
Test status
Simulation time 79365561 ps
CPU time 1.45 seconds
Started Aug 14 05:32:51 PM PDT 24
Finished Aug 14 05:32:52 PM PDT 24
Peak memory 219112 kb
Host smart-851a1de1-300c-4076-b81d-8d7365b18ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693808206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3693808206
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.787853664
Short name T42
Test name
Test status
Simulation time 20428208 ps
CPU time 1.17 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 216088 kb
Host smart-ffd7e0ed-5588-46fb-b428-5df094638411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787853664 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.787853664
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2990853033
Short name T948
Test name
Test status
Simulation time 15785449 ps
CPU time 0.99 seconds
Started Aug 14 05:32:39 PM PDT 24
Finished Aug 14 05:32:40 PM PDT 24
Peak memory 215640 kb
Host smart-02dbd7a0-6f21-423f-b6c6-6dbb396e4614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990853033 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2990853033
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1659429013
Short name T723
Test name
Test status
Simulation time 375141864 ps
CPU time 1.67 seconds
Started Aug 14 05:34:13 PM PDT 24
Finished Aug 14 05:34:15 PM PDT 24
Peak memory 215612 kb
Host smart-18420377-3135-46c3-a0f6-8881d4716542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659429013 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1659429013
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.307706332
Short name T234
Test name
Test status
Simulation time 1493711831 ps
CPU time 30.11 seconds
Started Aug 14 05:32:36 PM PDT 24
Finished Aug 14 05:33:07 PM PDT 24
Peak memory 218796 kb
Host smart-03399847-4183-490e-8bb3-88808c6b384d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307706332 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.307706332
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1906236577
Short name T413
Test name
Test status
Simulation time 44424438 ps
CPU time 1.65 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 218900 kb
Host smart-8f1c8ad5-4731-459d-919c-0af007abb7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906236577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1906236577
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2288383698
Short name T923
Test name
Test status
Simulation time 34332002 ps
CPU time 1.35 seconds
Started Aug 14 05:34:06 PM PDT 24
Finished Aug 14 05:34:08 PM PDT 24
Peak memory 219084 kb
Host smart-80d68558-cd70-4815-a38c-4e893237f2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288383698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2288383698
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1521041782
Short name T502
Test name
Test status
Simulation time 36152447 ps
CPU time 1.13 seconds
Started Aug 14 05:34:15 PM PDT 24
Finished Aug 14 05:34:16 PM PDT 24
Peak memory 218852 kb
Host smart-f7c3b0d7-d1cb-4ca9-b7d5-72536565a620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521041782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1521041782
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2038212996
Short name T637
Test name
Test status
Simulation time 46119633 ps
CPU time 1.58 seconds
Started Aug 14 05:34:21 PM PDT 24
Finished Aug 14 05:34:23 PM PDT 24
Peak memory 218784 kb
Host smart-388b2af6-b232-4446-b177-153a73e23c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038212996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2038212996
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3093676193
Short name T824
Test name
Test status
Simulation time 440426567 ps
CPU time 2.93 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 220376 kb
Host smart-66470f8e-2e65-4d5d-80c3-4fdd3dfd3862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093676193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3093676193
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.883009966
Short name T781
Test name
Test status
Simulation time 47239393 ps
CPU time 1.33 seconds
Started Aug 14 05:34:15 PM PDT 24
Finished Aug 14 05:34:16 PM PDT 24
Peak memory 217608 kb
Host smart-8d8ba877-b377-4111-a72a-5096b676b3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883009966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.883009966
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2563242061
Short name T966
Test name
Test status
Simulation time 222408691 ps
CPU time 2.7 seconds
Started Aug 14 05:34:10 PM PDT 24
Finished Aug 14 05:34:13 PM PDT 24
Peak memory 217776 kb
Host smart-002a41f8-aa82-4dc3-8d37-2dfd4d02f070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563242061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2563242061
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.409708367
Short name T449
Test name
Test status
Simulation time 41052145 ps
CPU time 1.69 seconds
Started Aug 14 05:34:10 PM PDT 24
Finished Aug 14 05:34:12 PM PDT 24
Peak memory 218876 kb
Host smart-421f1d9a-8c01-431e-a3d0-729304100c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409708367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.409708367
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1025245096
Short name T523
Test name
Test status
Simulation time 37684988 ps
CPU time 1.07 seconds
Started Aug 14 05:34:02 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 217624 kb
Host smart-4b353eb5-f52a-429e-be50-1eec7db0b99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025245096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1025245096
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2012718570
Short name T812
Test name
Test status
Simulation time 156550906 ps
CPU time 1.59 seconds
Started Aug 14 05:34:01 PM PDT 24
Finished Aug 14 05:34:03 PM PDT 24
Peak memory 219088 kb
Host smart-3f72fa68-eb8f-4edc-867b-2e27111a29a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012718570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2012718570
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.1233481869
Short name T561
Test name
Test status
Simulation time 37587966 ps
CPU time 0.82 seconds
Started Aug 14 05:32:39 PM PDT 24
Finished Aug 14 05:32:40 PM PDT 24
Peak memory 207128 kb
Host smart-6231cf2f-e5f2-4708-ad5e-2c21ce66ff70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233481869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1233481869
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3030666708
Short name T55
Test name
Test status
Simulation time 130665841 ps
CPU time 0.88 seconds
Started Aug 14 05:32:50 PM PDT 24
Finished Aug 14 05:32:51 PM PDT 24
Peak memory 215596 kb
Host smart-a7d8ef99-3036-4292-92de-eeb5b000f905
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030666708 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3030666708
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.1781843721
Short name T891
Test name
Test status
Simulation time 57132648 ps
CPU time 0.86 seconds
Started Aug 14 05:32:40 PM PDT 24
Finished Aug 14 05:32:41 PM PDT 24
Peak memory 215568 kb
Host smart-1861fb5d-bf0b-4ebd-8da2-31fcf7180d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781843721 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1781843721
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2789739770
Short name T549
Test name
Test status
Simulation time 45354712 ps
CPU time 1.48 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 218776 kb
Host smart-ec4a808b-6f4d-47f0-b371-0c197bd85367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789739770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2789739770
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.837968512
Short name T626
Test name
Test status
Simulation time 19625047 ps
CPU time 1.06 seconds
Started Aug 14 05:32:41 PM PDT 24
Finished Aug 14 05:32:42 PM PDT 24
Peak memory 216072 kb
Host smart-b6944415-1bd1-4a19-91c3-a35b13dc8584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837968512 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.837968512
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3974149948
Short name T428
Test name
Test status
Simulation time 15119445 ps
CPU time 0.96 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:32:59 PM PDT 24
Peak memory 215572 kb
Host smart-42e1d4ca-9873-4ef3-90a0-648cc5bfae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974149948 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3974149948
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3556004531
Short name T797
Test name
Test status
Simulation time 285081840 ps
CPU time 3.18 seconds
Started Aug 14 05:32:55 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 217612 kb
Host smart-d8ff7ed0-03af-4604-b9fe-08d801a32648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556004531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3556004531
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/280.edn_genbits.3694818615
Short name T260
Test name
Test status
Simulation time 72939463 ps
CPU time 1.15 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:02 PM PDT 24
Peak memory 219312 kb
Host smart-c36f4433-0a1f-4ce7-a8bc-34eb209eae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694818615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3694818615
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1746549015
Short name T678
Test name
Test status
Simulation time 78693819 ps
CPU time 1.12 seconds
Started Aug 14 05:34:06 PM PDT 24
Finished Aug 14 05:34:07 PM PDT 24
Peak memory 217496 kb
Host smart-7e0e6f28-2342-465d-ac16-25c00c7ac221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746549015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1746549015
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1928692693
Short name T338
Test name
Test status
Simulation time 134721310 ps
CPU time 1.13 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 219888 kb
Host smart-8bf20f16-9c35-4ed4-a8bb-85beef1d4aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928692693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1928692693
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2590905429
Short name T795
Test name
Test status
Simulation time 35672029 ps
CPU time 1.29 seconds
Started Aug 14 05:33:59 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 217532 kb
Host smart-6920dc37-08ee-4dd0-bc29-21bda4a73808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590905429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2590905429
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3809712869
Short name T301
Test name
Test status
Simulation time 38840450 ps
CPU time 1.65 seconds
Started Aug 14 05:34:05 PM PDT 24
Finished Aug 14 05:34:11 PM PDT 24
Peak memory 217668 kb
Host smart-46dbabb0-d6c3-4613-80db-11f64ecf8165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809712869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3809712869
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1404542096
Short name T345
Test name
Test status
Simulation time 189575130 ps
CPU time 1.02 seconds
Started Aug 14 05:34:00 PM PDT 24
Finished Aug 14 05:34:01 PM PDT 24
Peak memory 217712 kb
Host smart-7355ebb7-c3db-46fb-981b-f3e6b2f44ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404542096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1404542096
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.4270411937
Short name T818
Test name
Test status
Simulation time 64064425 ps
CPU time 1.1 seconds
Started Aug 14 05:34:13 PM PDT 24
Finished Aug 14 05:34:14 PM PDT 24
Peak memory 217684 kb
Host smart-a6a8438f-734f-4cab-aad7-53a5ce9dca5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270411937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.4270411937
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3861283630
Short name T929
Test name
Test status
Simulation time 84854379 ps
CPU time 1.05 seconds
Started Aug 14 05:34:12 PM PDT 24
Finished Aug 14 05:34:13 PM PDT 24
Peak memory 217772 kb
Host smart-4f40e140-94ce-40ca-b6e9-82ec21bb9cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861283630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3861283630
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3100222291
Short name T342
Test name
Test status
Simulation time 37400411 ps
CPU time 1.4 seconds
Started Aug 14 05:34:16 PM PDT 24
Finished Aug 14 05:34:18 PM PDT 24
Peak memory 217676 kb
Host smart-b5a82e69-de4e-4978-b299-02c8b211169f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100222291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3100222291
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.788233886
Short name T721
Test name
Test status
Simulation time 42258454 ps
CPU time 1.12 seconds
Started Aug 14 05:34:07 PM PDT 24
Finished Aug 14 05:34:09 PM PDT 24
Peak memory 217608 kb
Host smart-d16902d0-4a5d-4972-81d8-c0ef8823d7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788233886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.788233886
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.282068137
Short name T291
Test name
Test status
Simulation time 94702743 ps
CPU time 1.28 seconds
Started Aug 14 05:32:53 PM PDT 24
Finished Aug 14 05:32:55 PM PDT 24
Peak memory 220276 kb
Host smart-5f14690c-2193-480b-b41b-74423ff9512f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282068137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.282068137
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.335371576
Short name T396
Test name
Test status
Simulation time 18179801 ps
CPU time 0.97 seconds
Started Aug 14 05:32:49 PM PDT 24
Finished Aug 14 05:32:50 PM PDT 24
Peak memory 207028 kb
Host smart-9a73c060-35b9-4a4f-a95c-5e5907a10ec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335371576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.335371576
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1463358659
Short name T216
Test name
Test status
Simulation time 12829545 ps
CPU time 0.92 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 217012 kb
Host smart-fe23e2b0-2752-4dbb-a45e-19c049b1f1a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463358659 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1463358659
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2339451961
Short name T543
Test name
Test status
Simulation time 102794946 ps
CPU time 1.11 seconds
Started Aug 14 05:32:56 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 216984 kb
Host smart-42368c3c-f128-43ff-bd97-9a75a1c0b898
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339451961 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2339451961
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2780190710
Short name T217
Test name
Test status
Simulation time 50606624 ps
CPU time 1.13 seconds
Started Aug 14 05:32:37 PM PDT 24
Finished Aug 14 05:32:38 PM PDT 24
Peak memory 219700 kb
Host smart-93075eb1-a4af-46c9-a6da-891b671b227a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780190710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2780190710
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.280689786
Short name T667
Test name
Test status
Simulation time 69082503 ps
CPU time 1.08 seconds
Started Aug 14 05:32:47 PM PDT 24
Finished Aug 14 05:32:48 PM PDT 24
Peak memory 217636 kb
Host smart-d0f380fe-9e9f-423d-a066-af08ce3fadb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280689786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.280689786
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2057334641
Short name T654
Test name
Test status
Simulation time 22893299 ps
CPU time 0.95 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:32:59 PM PDT 24
Peak memory 216016 kb
Host smart-c16b73e2-86ac-4e29-8518-be5748e63982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057334641 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2057334641
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1484178001
Short name T65
Test name
Test status
Simulation time 15587185 ps
CPU time 0.95 seconds
Started Aug 14 05:32:50 PM PDT 24
Finished Aug 14 05:32:51 PM PDT 24
Peak memory 215576 kb
Host smart-42a86005-c45c-440a-ac96-eb59ed312d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484178001 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1484178001
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.658542124
Short name T351
Test name
Test status
Simulation time 75720026 ps
CPU time 1.04 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 215632 kb
Host smart-3119eedd-2aa4-4647-bf30-517f7c518265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658542124 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.658542124
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2472664860
Short name T790
Test name
Test status
Simulation time 3037675081 ps
CPU time 73.98 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:34:11 PM PDT 24
Peak memory 218892 kb
Host smart-f5bc281c-179c-41bc-993b-17c1526cda89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472664860 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2472664860
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/291.edn_genbits.3196100570
Short name T664
Test name
Test status
Simulation time 43973040 ps
CPU time 1.71 seconds
Started Aug 14 05:33:57 PM PDT 24
Finished Aug 14 05:33:59 PM PDT 24
Peak memory 217832 kb
Host smart-500e5a60-d495-46d3-8691-8efc6bcf01bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196100570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3196100570
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.544198626
Short name T341
Test name
Test status
Simulation time 28459429 ps
CPU time 1.17 seconds
Started Aug 14 05:34:22 PM PDT 24
Finished Aug 14 05:34:23 PM PDT 24
Peak memory 217656 kb
Host smart-337e39fc-2cb4-4841-9da7-3db1a0d0db82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544198626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.544198626
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.612797145
Short name T618
Test name
Test status
Simulation time 29366488 ps
CPU time 1.37 seconds
Started Aug 14 05:34:25 PM PDT 24
Finished Aug 14 05:34:26 PM PDT 24
Peak memory 218916 kb
Host smart-305c8d2a-3bc0-4c73-b285-0fa1ce1b489e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612797145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.612797145
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.355960136
Short name T94
Test name
Test status
Simulation time 32569056 ps
CPU time 1.35 seconds
Started Aug 14 05:34:28 PM PDT 24
Finished Aug 14 05:34:30 PM PDT 24
Peak memory 218908 kb
Host smart-19357b78-bb24-4ad0-acc5-7469ae4bce9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355960136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.355960136
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2401181473
Short name T926
Test name
Test status
Simulation time 59804700 ps
CPU time 1.04 seconds
Started Aug 14 05:34:15 PM PDT 24
Finished Aug 14 05:34:17 PM PDT 24
Peak memory 217912 kb
Host smart-39dcae1c-27f5-4e41-914c-a66a04763059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401181473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2401181473
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2298942211
Short name T405
Test name
Test status
Simulation time 54352861 ps
CPU time 1.1 seconds
Started Aug 14 05:34:07 PM PDT 24
Finished Aug 14 05:34:08 PM PDT 24
Peak memory 219076 kb
Host smart-8e833fd5-e8da-4338-919a-a6b3930b1978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298942211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2298942211
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3757471803
Short name T337
Test name
Test status
Simulation time 46416351 ps
CPU time 1.45 seconds
Started Aug 14 05:34:30 PM PDT 24
Finished Aug 14 05:34:32 PM PDT 24
Peak memory 217784 kb
Host smart-1cb73fce-d2e7-4790-a648-4bd404117f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757471803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3757471803
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.4282895428
Short name T863
Test name
Test status
Simulation time 34663146 ps
CPU time 1.39 seconds
Started Aug 14 05:34:13 PM PDT 24
Finished Aug 14 05:34:14 PM PDT 24
Peak memory 220428 kb
Host smart-e1327315-b475-4068-9540-6dc0a45ac546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282895428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.4282895428
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2732344838
Short name T898
Test name
Test status
Simulation time 202947478 ps
CPU time 2.96 seconds
Started Aug 14 05:34:41 PM PDT 24
Finished Aug 14 05:34:44 PM PDT 24
Peak memory 220808 kb
Host smart-5704f3a8-4f6b-4959-a641-58cd85c30373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732344838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2732344838
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3976061726
Short name T548
Test name
Test status
Simulation time 73506519 ps
CPU time 1.35 seconds
Started Aug 14 05:31:55 PM PDT 24
Finished Aug 14 05:31:56 PM PDT 24
Peak memory 215932 kb
Host smart-d093b944-272e-41b3-88e6-89beba10a2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976061726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3976061726
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2755054693
Short name T925
Test name
Test status
Simulation time 67590132 ps
CPU time 0.95 seconds
Started Aug 14 05:31:50 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 207156 kb
Host smart-8c5df16c-a2c2-4251-9a06-2d04c786f2d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755054693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2755054693
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.409458693
Short name T175
Test name
Test status
Simulation time 92718391 ps
CPU time 0.81 seconds
Started Aug 14 05:31:50 PM PDT 24
Finished Aug 14 05:31:52 PM PDT 24
Peak memory 215648 kb
Host smart-3a6ead13-cfac-4977-8feb-242470641e8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409458693 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.409458693
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3272295472
Short name T754
Test name
Test status
Simulation time 32148956 ps
CPU time 1.21 seconds
Started Aug 14 05:31:55 PM PDT 24
Finished Aug 14 05:31:56 PM PDT 24
Peak memory 217148 kb
Host smart-245690e9-ad0e-4e95-b26e-2da286d28b0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272295472 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3272295472
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2403228440
Short name T955
Test name
Test status
Simulation time 56400119 ps
CPU time 1.03 seconds
Started Aug 14 05:31:56 PM PDT 24
Finished Aug 14 05:31:57 PM PDT 24
Peak memory 218824 kb
Host smart-62c1a428-ca9b-42da-a002-78010de93151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403228440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2403228440
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.171790970
Short name T951
Test name
Test status
Simulation time 129919045 ps
CPU time 1.28 seconds
Started Aug 14 05:31:54 PM PDT 24
Finished Aug 14 05:31:55 PM PDT 24
Peak memory 219256 kb
Host smart-37e61819-9812-4296-a67f-d522b4baff4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171790970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.171790970
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2209783790
Short name T105
Test name
Test status
Simulation time 38337313 ps
CPU time 0.83 seconds
Started Aug 14 05:31:57 PM PDT 24
Finished Aug 14 05:31:58 PM PDT 24
Peak memory 215880 kb
Host smart-5ed6b94e-ddf1-4aea-8d92-f2a0ad873226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209783790 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2209783790
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.81496848
Short name T639
Test name
Test status
Simulation time 16024050 ps
CPU time 0.97 seconds
Started Aug 14 05:32:00 PM PDT 24
Finished Aug 14 05:32:01 PM PDT 24
Peak memory 207436 kb
Host smart-49aa40e7-6fc3-4688-abf0-fb8bcd11d071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81496848 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.81496848
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.284538614
Short name T866
Test name
Test status
Simulation time 121613399 ps
CPU time 0.88 seconds
Started Aug 14 05:31:55 PM PDT 24
Finished Aug 14 05:31:56 PM PDT 24
Peak memory 215376 kb
Host smart-08c0afff-4cb3-489d-ab52-1994afa8725a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284538614 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.284538614
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.98029824
Short name T340
Test name
Test status
Simulation time 201414410 ps
CPU time 4.12 seconds
Started Aug 14 05:31:54 PM PDT 24
Finished Aug 14 05:31:58 PM PDT 24
Peak memory 215632 kb
Host smart-1ac55929-e64c-4092-9384-df5b00c6fe2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98029824 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.98029824
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3080024118
Short name T713
Test name
Test status
Simulation time 2809422486 ps
CPU time 24.51 seconds
Started Aug 14 05:31:54 PM PDT 24
Finished Aug 14 05:32:18 PM PDT 24
Peak memory 219796 kb
Host smart-d7767abe-1afd-48ea-83e6-41d644671348
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080024118 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3080024118
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3208744994
Short name T946
Test name
Test status
Simulation time 28529101 ps
CPU time 1.33 seconds
Started Aug 14 05:32:55 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 218948 kb
Host smart-0c92a76b-2b24-4dfc-a458-1d6bd2a3c823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208744994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3208744994
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3841371262
Short name T658
Test name
Test status
Simulation time 20548313 ps
CPU time 0.87 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 207104 kb
Host smart-4e976277-407c-4028-aa83-82ce62711c34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841371262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3841371262
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.602092369
Short name T221
Test name
Test status
Simulation time 24088189 ps
CPU time 0.88 seconds
Started Aug 14 05:32:42 PM PDT 24
Finished Aug 14 05:32:43 PM PDT 24
Peak memory 217056 kb
Host smart-02bcbf60-436b-4bd9-bbf3-8fb37769a76e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602092369 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.602092369
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.133291694
Short name T708
Test name
Test status
Simulation time 115869263 ps
CPU time 1.22 seconds
Started Aug 14 05:32:54 PM PDT 24
Finished Aug 14 05:32:56 PM PDT 24
Peak memory 217176 kb
Host smart-3a974dca-a7f1-44b0-a652-d55996873434
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133291694 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.133291694
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3980076414
Short name T643
Test name
Test status
Simulation time 22749479 ps
CPU time 0.95 seconds
Started Aug 14 05:32:54 PM PDT 24
Finished Aug 14 05:32:55 PM PDT 24
Peak memory 219880 kb
Host smart-edc0e7eb-5035-4d92-b369-f7b43de7971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980076414 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3980076414
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.4075155854
Short name T954
Test name
Test status
Simulation time 59560578 ps
CPU time 1.55 seconds
Started Aug 14 05:32:41 PM PDT 24
Finished Aug 14 05:32:43 PM PDT 24
Peak memory 219120 kb
Host smart-860a4a8e-9cf4-492b-ba5f-c7d5b9039d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075155854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.4075155854
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3574947203
Short name T646
Test name
Test status
Simulation time 21177096 ps
CPU time 1.09 seconds
Started Aug 14 05:32:39 PM PDT 24
Finished Aug 14 05:32:40 PM PDT 24
Peak memory 215796 kb
Host smart-73ec2cc0-a7ee-4212-9206-b80e49737b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574947203 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3574947203
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3289909686
Short name T610
Test name
Test status
Simulation time 27508876 ps
CPU time 1.02 seconds
Started Aug 14 05:32:55 PM PDT 24
Finished Aug 14 05:32:56 PM PDT 24
Peak memory 207420 kb
Host smart-1b1b270d-6c90-4983-8976-fee95a932963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289909686 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3289909686
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2509053861
Short name T119
Test name
Test status
Simulation time 390584056 ps
CPU time 5.02 seconds
Started Aug 14 05:32:48 PM PDT 24
Finished Aug 14 05:32:53 PM PDT 24
Peak memory 219964 kb
Host smart-078dfbc4-e862-471f-bb6a-4e701d999e59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509053861 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2509053861
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2221488458
Short name T238
Test name
Test status
Simulation time 5546757835 ps
CPU time 68.2 seconds
Started Aug 14 05:32:36 PM PDT 24
Finished Aug 14 05:33:45 PM PDT 24
Peak memory 221636 kb
Host smart-c0bf2117-bf60-4fd3-89d4-a2d98492b6f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221488458 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2221488458
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.983588877
Short name T227
Test name
Test status
Simulation time 66516029 ps
CPU time 1.11 seconds
Started Aug 14 05:32:56 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 220640 kb
Host smart-58838b65-b3d0-45f5-83bb-1e75bca18ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983588877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.983588877
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2407196471
Short name T368
Test name
Test status
Simulation time 15312818 ps
CPU time 0.92 seconds
Started Aug 14 05:32:50 PM PDT 24
Finished Aug 14 05:32:51 PM PDT 24
Peak memory 207056 kb
Host smart-90907998-d446-421e-acce-a46cb8571f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407196471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2407196471
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3935370750
Short name T833
Test name
Test status
Simulation time 63357235 ps
CPU time 0.8 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 219352 kb
Host smart-671ffdf9-4597-4790-bf0f-bd7ec29280e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935370750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3935370750
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3012019232
Short name T503
Test name
Test status
Simulation time 101835038 ps
CPU time 1.19 seconds
Started Aug 14 05:32:41 PM PDT 24
Finished Aug 14 05:32:43 PM PDT 24
Peak memory 217296 kb
Host smart-0b4a51b0-7856-42d7-8664-e9f501f1c09b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012019232 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3012019232
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.91077296
Short name T558
Test name
Test status
Simulation time 56237514 ps
CPU time 0.84 seconds
Started Aug 14 05:32:46 PM PDT 24
Finished Aug 14 05:32:47 PM PDT 24
Peak memory 218448 kb
Host smart-b2f6f3e2-347a-4012-9ee2-3cc1fd735648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91077296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.91077296
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1722438419
Short name T51
Test name
Test status
Simulation time 68462238 ps
CPU time 1.76 seconds
Started Aug 14 05:32:42 PM PDT 24
Finished Aug 14 05:32:44 PM PDT 24
Peak memory 217860 kb
Host smart-61d7237d-8280-4d00-b155-c4f86692dd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722438419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1722438419
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3662666677
Short name T555
Test name
Test status
Simulation time 26375399 ps
CPU time 0.99 seconds
Started Aug 14 05:32:56 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 215772 kb
Host smart-2f6f7014-90d0-4eaa-af4e-dd66361eee5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662666677 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3662666677
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2013829504
Short name T698
Test name
Test status
Simulation time 31936177 ps
CPU time 0.89 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:32:59 PM PDT 24
Peak memory 215560 kb
Host smart-f000a416-b052-4718-b7bb-bca53f841f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013829504 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2013829504
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.210113809
Short name T456
Test name
Test status
Simulation time 67307607 ps
CPU time 1.3 seconds
Started Aug 14 05:32:39 PM PDT 24
Finished Aug 14 05:32:40 PM PDT 24
Peak memory 217684 kb
Host smart-bc8edf1b-aa13-4357-8742-8f2e7200745a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210113809 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.210113809
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2989329780
Short name T564
Test name
Test status
Simulation time 4124556387 ps
CPU time 111.4 seconds
Started Aug 14 05:32:53 PM PDT 24
Finished Aug 14 05:34:44 PM PDT 24
Peak memory 220976 kb
Host smart-3887c36e-792e-4855-b6b9-23b3e888e1a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989329780 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2989329780
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2647690017
Short name T739
Test name
Test status
Simulation time 69923991 ps
CPU time 1.14 seconds
Started Aug 14 05:32:47 PM PDT 24
Finished Aug 14 05:32:48 PM PDT 24
Peak memory 220276 kb
Host smart-aa47e3d5-a838-4ff3-9818-f5b41fb34008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647690017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2647690017
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1467745755
Short name T355
Test name
Test status
Simulation time 122685256 ps
CPU time 0.85 seconds
Started Aug 14 05:32:38 PM PDT 24
Finished Aug 14 05:32:39 PM PDT 24
Peak memory 206452 kb
Host smart-b0c350c9-2da5-454a-bbb6-57d6790421bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467745755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1467745755
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3240319451
Short name T763
Test name
Test status
Simulation time 25709413 ps
CPU time 0.92 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 218708 kb
Host smart-8f46b307-d5b2-458d-8460-d96437759062
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240319451 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3240319451
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_genbits.1931644820
Short name T648
Test name
Test status
Simulation time 203970459 ps
CPU time 1.53 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 219020 kb
Host smart-6f47c32d-d5ec-4169-bf05-41a1807c4994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931644820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1931644820
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2794393494
Short name T757
Test name
Test status
Simulation time 38758787 ps
CPU time 0.88 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 215672 kb
Host smart-2d7bbc2c-a2ce-4e5f-9bd6-f3b6583b2fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794393494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2794393494
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.946411486
Short name T537
Test name
Test status
Simulation time 28302786 ps
CPU time 0.95 seconds
Started Aug 14 05:32:40 PM PDT 24
Finished Aug 14 05:32:41 PM PDT 24
Peak memory 215584 kb
Host smart-3e824e30-ca74-4e63-9c24-06cae527b976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946411486 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.946411486
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1209006491
Short name T72
Test name
Test status
Simulation time 144708208 ps
CPU time 2.23 seconds
Started Aug 14 05:32:45 PM PDT 24
Finished Aug 14 05:32:48 PM PDT 24
Peak memory 217600 kb
Host smart-0705cf83-31cb-4e23-a828-cf42fab59908
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209006491 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1209006491
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_alert.3089426623
Short name T194
Test name
Test status
Simulation time 44829381 ps
CPU time 1.16 seconds
Started Aug 14 05:32:56 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 221272 kb
Host smart-d184b812-3cad-4b0c-8e09-5d9cc7c93c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089426623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3089426623
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1997138451
Short name T81
Test name
Test status
Simulation time 61451561 ps
CPU time 0.87 seconds
Started Aug 14 05:32:56 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 207172 kb
Host smart-797a0970-dec3-4022-ac0c-c4d028eaa9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997138451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1997138451
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1248553628
Short name T427
Test name
Test status
Simulation time 62119810 ps
CPU time 1.65 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 217236 kb
Host smart-6cd2d512-a0eb-4c86-a0aa-75a58532fc3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248553628 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1248553628
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3290585174
Short name T800
Test name
Test status
Simulation time 50445747 ps
CPU time 0.95 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 224040 kb
Host smart-628a00be-b392-4691-bc1e-3d7693535dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290585174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3290585174
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1785665185
Short name T517
Test name
Test status
Simulation time 325749519 ps
CPU time 2.21 seconds
Started Aug 14 05:32:53 PM PDT 24
Finished Aug 14 05:32:56 PM PDT 24
Peak memory 219116 kb
Host smart-3e71f583-9339-4101-94ad-140a6328534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785665185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1785665185
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2141784322
Short name T785
Test name
Test status
Simulation time 26202892 ps
CPU time 1 seconds
Started Aug 14 05:32:43 PM PDT 24
Finished Aug 14 05:32:44 PM PDT 24
Peak memory 216140 kb
Host smart-b05d28d1-b93c-4f74-9036-6e6cde98749b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141784322 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2141784322
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3742583346
Short name T538
Test name
Test status
Simulation time 39205650 ps
CPU time 0.92 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 215600 kb
Host smart-0a2ebbcc-7ac8-4fdc-a31d-3ab7473dadd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742583346 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3742583346
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3700031224
Short name T30
Test name
Test status
Simulation time 323514938 ps
CPU time 6.23 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 217476 kb
Host smart-b780f184-dd09-4d82-888b-35dfce9b86c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700031224 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3700031224
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.71969722
Short name T239
Test name
Test status
Simulation time 2704581977 ps
CPU time 67.05 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:34:05 PM PDT 24
Peak memory 216840 kb
Host smart-4e252649-3266-430d-a386-474bc2c245e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71969722 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.71969722
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1601080068
Short name T478
Test name
Test status
Simulation time 43245660 ps
CPU time 1.09 seconds
Started Aug 14 05:32:45 PM PDT 24
Finished Aug 14 05:32:46 PM PDT 24
Peak memory 219996 kb
Host smart-8edf1a61-c1f3-4f29-9a28-4ba84a89b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601080068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1601080068
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1913822356
Short name T426
Test name
Test status
Simulation time 40196341 ps
CPU time 0.92 seconds
Started Aug 14 05:32:55 PM PDT 24
Finished Aug 14 05:32:56 PM PDT 24
Peak memory 207116 kb
Host smart-498f9569-8d0c-4412-b5fd-2d13488a55a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913822356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1913822356
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2799530658
Short name T180
Test name
Test status
Simulation time 19676872 ps
CPU time 0.86 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 216788 kb
Host smart-a4f16e32-3118-4036-9d14-22b04230d2ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799530658 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2799530658
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3134635449
Short name T762
Test name
Test status
Simulation time 53720916 ps
CPU time 1.1 seconds
Started Aug 14 05:32:49 PM PDT 24
Finished Aug 14 05:32:50 PM PDT 24
Peak memory 217240 kb
Host smart-a08649e3-8865-4174-9ca7-83d5d56e0c50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134635449 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3134635449
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3141194426
Short name T176
Test name
Test status
Simulation time 57083066 ps
CPU time 1.2 seconds
Started Aug 14 05:32:47 PM PDT 24
Finished Aug 14 05:32:48 PM PDT 24
Peak memory 226000 kb
Host smart-a2f75250-9a5f-49be-b43b-a8949281771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141194426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3141194426
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2666070725
Short name T392
Test name
Test status
Simulation time 46118701 ps
CPU time 1.68 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 218976 kb
Host smart-bc8b9dd0-3370-4fdc-9d6b-e7d69a42639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666070725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2666070725
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1023439724
Short name T38
Test name
Test status
Simulation time 21371144 ps
CPU time 1.11 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 216196 kb
Host smart-dbe48be6-0707-4d9e-9255-c5aadcbe0c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023439724 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1023439724
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3410025139
Short name T352
Test name
Test status
Simulation time 18838381 ps
CPU time 0.98 seconds
Started Aug 14 05:32:40 PM PDT 24
Finished Aug 14 05:32:41 PM PDT 24
Peak memory 215556 kb
Host smart-a5c49573-3aa8-4d5f-87ac-75c123ba132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410025139 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3410025139
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4042649731
Short name T457
Test name
Test status
Simulation time 368234575 ps
CPU time 7.39 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:06 PM PDT 24
Peak memory 217744 kb
Host smart-a8ec91a6-473c-482f-af72-4b226983b7ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042649731 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4042649731
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_alert.1323193053
Short name T472
Test name
Test status
Simulation time 80788055 ps
CPU time 1.21 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 218668 kb
Host smart-9b7ca8e3-6542-4cff-9dd3-fd6347dbf90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323193053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1323193053
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.418260130
Short name T390
Test name
Test status
Simulation time 54059570 ps
CPU time 0.86 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 206956 kb
Host smart-682a9d99-62fe-4949-8dfc-46c057684508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418260130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.418260130
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1324616441
Short name T212
Test name
Test status
Simulation time 21221140 ps
CPU time 0.87 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 216820 kb
Host smart-0a9df1d7-0c7a-45be-a025-c7d5e4b23f35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324616441 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1324616441
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2257633585
Short name T152
Test name
Test status
Simulation time 41917609 ps
CPU time 1.04 seconds
Started Aug 14 05:32:56 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 218436 kb
Host smart-77a3cde6-7aa9-47e6-a54c-b33d413c5468
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257633585 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2257633585
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.677433077
Short name T158
Test name
Test status
Simulation time 25088958 ps
CPU time 1.31 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:59 PM PDT 24
Peak memory 230064 kb
Host smart-c4f75f8e-88d5-4276-9565-7aa7750faf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677433077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.677433077
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3462142635
Short name T104
Test name
Test status
Simulation time 62925303 ps
CPU time 1.35 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:32:59 PM PDT 24
Peak memory 218612 kb
Host smart-428f8a1a-6717-4a7b-af8f-a45e6c9490ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462142635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3462142635
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.174342485
Short name T43
Test name
Test status
Simulation time 22617088 ps
CPU time 1.01 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 216048 kb
Host smart-a1fe6a22-4d15-450f-9439-063b2ef1b0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174342485 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.174342485
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.4060167560
Short name T353
Test name
Test status
Simulation time 40682994 ps
CPU time 0.9 seconds
Started Aug 14 05:32:48 PM PDT 24
Finished Aug 14 05:32:49 PM PDT 24
Peak memory 215716 kb
Host smart-85fa1c9a-b23f-4518-ba13-160055bffe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060167560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.4060167560
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.395353217
Short name T485
Test name
Test status
Simulation time 846465860 ps
CPU time 1.58 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 215576 kb
Host smart-8ede18ad-c666-412f-b669-d9304bc6f09f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395353217 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.395353217
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1129877822
Short name T241
Test name
Test status
Simulation time 11009621876 ps
CPU time 63.15 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:34:00 PM PDT 24
Peak memory 223972 kb
Host smart-090d78e4-05df-4dbb-8c1e-4c8912e1a2e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129877822 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1129877822
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1107534555
Short name T509
Test name
Test status
Simulation time 44233527 ps
CPU time 1.2 seconds
Started Aug 14 05:32:41 PM PDT 24
Finished Aug 14 05:32:43 PM PDT 24
Peak memory 220148 kb
Host smart-2b91aa76-3df1-45d3-a63b-3dcbb0b193a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107534555 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1107534555
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1853064075
Short name T710
Test name
Test status
Simulation time 15400423 ps
CPU time 0.96 seconds
Started Aug 14 05:32:41 PM PDT 24
Finished Aug 14 05:32:42 PM PDT 24
Peak memory 215236 kb
Host smart-9bda4d29-ce60-4aee-b648-90ed85d6e17a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853064075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1853064075
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3121110829
Short name T788
Test name
Test status
Simulation time 17080932 ps
CPU time 0.85 seconds
Started Aug 14 05:32:42 PM PDT 24
Finished Aug 14 05:32:43 PM PDT 24
Peak memory 216576 kb
Host smart-597744ec-5ac9-4041-96e0-612a3ae313bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121110829 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3121110829
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1154053665
Short name T666
Test name
Test status
Simulation time 45276648 ps
CPU time 1.13 seconds
Started Aug 14 05:32:39 PM PDT 24
Finished Aug 14 05:32:40 PM PDT 24
Peak memory 217184 kb
Host smart-019419d6-6533-480c-bb2a-164eadf43c25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154053665 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1154053665
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1720531934
Short name T819
Test name
Test status
Simulation time 22725476 ps
CPU time 0.94 seconds
Started Aug 14 05:32:42 PM PDT 24
Finished Aug 14 05:32:43 PM PDT 24
Peak memory 218620 kb
Host smart-14fbe46f-02e2-4cfd-974b-feb3c1463450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720531934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1720531934
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.37907949
Short name T380
Test name
Test status
Simulation time 26150612 ps
CPU time 1.12 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 217340 kb
Host smart-7e455a85-0e74-4a38-99a9-255885a6fd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37907949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.37907949
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1493281114
Short name T361
Test name
Test status
Simulation time 40956078 ps
CPU time 0.93 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 215776 kb
Host smart-2166b7af-74df-453a-ad4a-00c6d650921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493281114 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1493281114
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2077990060
Short name T249
Test name
Test status
Simulation time 15915801 ps
CPU time 0.96 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 215740 kb
Host smart-6b5432f5-9079-487b-a124-96bc9dae71f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077990060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2077990060
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1756385851
Short name T831
Test name
Test status
Simulation time 810147886 ps
CPU time 4.47 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:06 PM PDT 24
Peak memory 215620 kb
Host smart-6872914c-849e-4c09-8943-c1d2cce9d72f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756385851 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1756385851
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert.315023223
Short name T953
Test name
Test status
Simulation time 21742303 ps
CPU time 1.16 seconds
Started Aug 14 05:32:52 PM PDT 24
Finished Aug 14 05:32:54 PM PDT 24
Peak memory 219004 kb
Host smart-fb8284f2-cce6-415a-8db0-d7dd34d0aa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315023223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.315023223
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3232889476
Short name T419
Test name
Test status
Simulation time 56696818 ps
CPU time 0.89 seconds
Started Aug 14 05:32:53 PM PDT 24
Finished Aug 14 05:32:54 PM PDT 24
Peak memory 215284 kb
Host smart-10697260-d194-4fd2-a6f9-27b36d9cb5bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232889476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3232889476
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1179754239
Short name T735
Test name
Test status
Simulation time 15421531 ps
CPU time 1 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:06 PM PDT 24
Peak memory 216672 kb
Host smart-63815d3f-e68a-4f60-b1b4-cd8b651f752f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179754239 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1179754239
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.781966493
Short name T774
Test name
Test status
Simulation time 38602005 ps
CPU time 1.01 seconds
Started Aug 14 05:32:50 PM PDT 24
Finished Aug 14 05:32:51 PM PDT 24
Peak memory 218888 kb
Host smart-a17520d4-8f67-4b4f-837c-1b9c31719c94
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781966493 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.781966493
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2092316178
Short name T179
Test name
Test status
Simulation time 74868779 ps
CPU time 1.2 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 225784 kb
Host smart-121e43f0-eb22-49b3-ae71-c0330e971120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092316178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2092316178
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.4033249473
Short name T671
Test name
Test status
Simulation time 55347889 ps
CPU time 1.55 seconds
Started Aug 14 05:33:04 PM PDT 24
Finished Aug 14 05:33:06 PM PDT 24
Peak memory 220040 kb
Host smart-465a5b82-bb1d-411d-9bc0-bdf7547b8cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033249473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.4033249473
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2872548102
Short name T681
Test name
Test status
Simulation time 26290352 ps
CPU time 1.08 seconds
Started Aug 14 05:32:56 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 224268 kb
Host smart-67523fe3-680b-49e4-814a-97f3ca05377f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872548102 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2872548102
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.593572132
Short name T630
Test name
Test status
Simulation time 14203392 ps
CPU time 0.93 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:06 PM PDT 24
Peak memory 215608 kb
Host smart-e43ee243-92ac-46d3-9afd-130b3b1ffb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593572132 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.593572132
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3321018480
Short name T498
Test name
Test status
Simulation time 1750009552 ps
CPU time 3.29 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:07 PM PDT 24
Peak memory 217524 kb
Host smart-0d83d7cb-61fd-4276-83e0-f52fef4270e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321018480 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3321018480
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3802109047
Short name T717
Test name
Test status
Simulation time 16399353827 ps
CPU time 76.92 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:34:18 PM PDT 24
Peak memory 217472 kb
Host smart-063198ff-cdfa-4eac-b362-89cc03946d4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802109047 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3802109047
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1447972418
Short name T683
Test name
Test status
Simulation time 25240040 ps
CPU time 1.24 seconds
Started Aug 14 05:32:51 PM PDT 24
Finished Aug 14 05:32:52 PM PDT 24
Peak memory 220036 kb
Host smart-e9b07346-0984-4fca-99bc-226b7a47e313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447972418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1447972418
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1557308601
Short name T250
Test name
Test status
Simulation time 35890084 ps
CPU time 1.02 seconds
Started Aug 14 05:32:56 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 215472 kb
Host smart-84d91a46-93a8-45b4-9d18-3810ccb9fd1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557308601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1557308601
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.424614205
Short name T198
Test name
Test status
Simulation time 33375386 ps
CPU time 0.9 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 216880 kb
Host smart-e735f8e4-69b4-4a36-86d7-ea24e974e168
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424614205 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.424614205
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.2174322955
Short name T60
Test name
Test status
Simulation time 90554648 ps
CPU time 1.28 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 225892 kb
Host smart-195e0c6c-3962-4852-84bb-d3f917b8a0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174322955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2174322955
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1870083219
Short name T773
Test name
Test status
Simulation time 88638201 ps
CPU time 1.13 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 217680 kb
Host smart-997dd3cb-9db0-48bd-a386-00d7b9b4f8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870083219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1870083219
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2974415977
Short name T806
Test name
Test status
Simulation time 49710611 ps
CPU time 0.84 seconds
Started Aug 14 05:32:56 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 214820 kb
Host smart-5b0f7257-be14-4f6f-9666-761d4806b2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974415977 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2974415977
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.263885280
Short name T350
Test name
Test status
Simulation time 28584642 ps
CPU time 0.92 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 215636 kb
Host smart-9ab48c23-fa01-4c0c-b99d-6714120a27d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263885280 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.263885280
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3527624754
Short name T256
Test name
Test status
Simulation time 42864668 ps
CPU time 1.46 seconds
Started Aug 14 05:32:56 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 205796 kb
Host smart-9607d456-16c6-4690-910b-41aef657cff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527624754 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3527624754
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2647728043
Short name T243
Test name
Test status
Simulation time 37625903806 ps
CPU time 90.67 seconds
Started Aug 14 05:32:55 PM PDT 24
Finished Aug 14 05:34:26 PM PDT 24
Peak memory 218692 kb
Host smart-4f7004df-8f7f-4d5d-95ce-4c06a05710d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647728043 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2647728043
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1201227108
Short name T267
Test name
Test status
Simulation time 47651035 ps
CPU time 1.21 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 219588 kb
Host smart-ff95d200-e08f-4a86-a28f-ef7bd98a49b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201227108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1201227108
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1503398099
Short name T525
Test name
Test status
Simulation time 14120256 ps
CPU time 0.94 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 215280 kb
Host smart-cfceaab7-a8aa-4611-9ea4-9e44f74e0a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503398099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1503398099
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.546613355
Short name T247
Test name
Test status
Simulation time 40587404 ps
CPU time 1.35 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 216064 kb
Host smart-4254659e-8acb-48f6-9a87-708bfbd37923
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546613355 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.546613355
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2735733611
Short name T627
Test name
Test status
Simulation time 32220144 ps
CPU time 0.88 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 218692 kb
Host smart-526919f4-5744-427a-a7df-75f6bf00272a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735733611 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2735733611
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1657086919
Short name T437
Test name
Test status
Simulation time 33229280 ps
CPU time 1.5 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 218840 kb
Host smart-66648f76-ccc2-4f18-ac0c-adb67395d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657086919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1657086919
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3790244195
Short name T35
Test name
Test status
Simulation time 28957877 ps
CPU time 0.88 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:32:59 PM PDT 24
Peak memory 216000 kb
Host smart-5ed2850c-9087-4f23-a760-2dd549ed2f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790244195 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3790244195
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.4040710261
Short name T585
Test name
Test status
Simulation time 17044398 ps
CPU time 1.03 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 215728 kb
Host smart-f9aaadea-a4d7-4567-bce0-c11b018c658b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040710261 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.4040710261
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2526682796
Short name T848
Test name
Test status
Simulation time 226695907 ps
CPU time 4.82 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:07 PM PDT 24
Peak memory 215568 kb
Host smart-99720d91-a3f2-49a2-ac0e-4e97a66b9a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526682796 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2526682796
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1747127627
Short name T45
Test name
Test status
Simulation time 6528478813 ps
CPU time 23.02 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:25 PM PDT 24
Peak memory 218084 kb
Host smart-5cac9719-0a4a-4c1b-b4ba-f12f1045089f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747127627 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1747127627
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.279246418
Short name T849
Test name
Test status
Simulation time 28259072 ps
CPU time 1.25 seconds
Started Aug 14 05:32:03 PM PDT 24
Finished Aug 14 05:32:05 PM PDT 24
Peak memory 220172 kb
Host smart-49736052-5d75-41d7-965e-6a192ceb1552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279246418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.279246418
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3395244587
Short name T571
Test name
Test status
Simulation time 23164296 ps
CPU time 0.89 seconds
Started Aug 14 05:32:11 PM PDT 24
Finished Aug 14 05:32:12 PM PDT 24
Peak memory 207020 kb
Host smart-2b618034-2a42-403c-b9c8-9737b6ac9381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395244587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3395244587
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.637202584
Short name T407
Test name
Test status
Simulation time 12782881 ps
CPU time 0.87 seconds
Started Aug 14 05:32:17 PM PDT 24
Finished Aug 14 05:32:18 PM PDT 24
Peak memory 216764 kb
Host smart-fd643d6e-2512-4d30-9f9e-93d833ce0f23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637202584 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.637202584
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1819907201
Short name T741
Test name
Test status
Simulation time 137531470 ps
CPU time 1.13 seconds
Started Aug 14 05:31:59 PM PDT 24
Finished Aug 14 05:32:00 PM PDT 24
Peak memory 217252 kb
Host smart-e51fe8f6-f11f-4d9f-a1de-75efabbf4736
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819907201 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1819907201
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1563136540
Short name T209
Test name
Test status
Simulation time 24494384 ps
CPU time 0.95 seconds
Started Aug 14 05:31:58 PM PDT 24
Finished Aug 14 05:31:59 PM PDT 24
Peak memory 218648 kb
Host smart-8a5983cf-2d45-42eb-9770-f84cc5ba4c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563136540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1563136540
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.4025577362
Short name T707
Test name
Test status
Simulation time 31019184 ps
CPU time 1.34 seconds
Started Aug 14 05:32:02 PM PDT 24
Finished Aug 14 05:32:03 PM PDT 24
Peak memory 217720 kb
Host smart-cde20a16-9671-4136-8931-8f45142cb79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025577362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.4025577362
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3052933025
Short name T4
Test name
Test status
Simulation time 21005448 ps
CPU time 1.06 seconds
Started Aug 14 05:32:08 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 215744 kb
Host smart-3d9c0bb2-6ed3-4e77-b3e4-078d49faedbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052933025 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3052933025
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.324892542
Short name T313
Test name
Test status
Simulation time 18766189 ps
CPU time 1 seconds
Started Aug 14 05:31:53 PM PDT 24
Finished Aug 14 05:31:54 PM PDT 24
Peak memory 207436 kb
Host smart-ebcd8e0f-5407-4b6d-a678-03636b3784b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324892542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.324892542
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.486308043
Short name T18
Test name
Test status
Simulation time 933975990 ps
CPU time 4.65 seconds
Started Aug 14 05:32:05 PM PDT 24
Finished Aug 14 05:32:10 PM PDT 24
Peak memory 243152 kb
Host smart-268d8958-59e9-4b5c-956f-a37a540fc2e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486308043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.486308043
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3320889055
Short name T354
Test name
Test status
Simulation time 18475923 ps
CPU time 0.99 seconds
Started Aug 14 05:31:54 PM PDT 24
Finished Aug 14 05:31:55 PM PDT 24
Peak memory 215628 kb
Host smart-44a1f805-b023-4c11-a24b-17ff00aa3d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320889055 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3320889055
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3176677384
Short name T601
Test name
Test status
Simulation time 1638369841 ps
CPU time 2.84 seconds
Started Aug 14 05:32:03 PM PDT 24
Finished Aug 14 05:32:06 PM PDT 24
Peak memory 217532 kb
Host smart-90c629db-49d8-4a73-8f38-b848b7a34e0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176677384 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3176677384
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_alert.2671098714
Short name T314
Test name
Test status
Simulation time 73570344 ps
CPU time 1.15 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 221008 kb
Host smart-fe472d5f-dd82-4cf3-a107-5856673be3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671098714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2671098714
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.588862462
Short name T481
Test name
Test status
Simulation time 41832882 ps
CPU time 0.87 seconds
Started Aug 14 05:32:49 PM PDT 24
Finished Aug 14 05:32:50 PM PDT 24
Peak memory 215296 kb
Host smart-b7e530f1-14f2-439e-9ebe-71f6e2f90856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588862462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.588862462
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1480485474
Short name T218
Test name
Test status
Simulation time 35384897 ps
CPU time 0.88 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 216720 kb
Host smart-30e6aa72-934e-4c67-be19-3d2bed9a67b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480485474 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1480485474
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3619115067
Short name T166
Test name
Test status
Simulation time 187466240 ps
CPU time 1.04 seconds
Started Aug 14 05:32:55 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 217112 kb
Host smart-5590fabe-3503-4d73-95f6-333a3e56cfb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619115067 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3619115067
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1335139992
Short name T156
Test name
Test status
Simulation time 22969056 ps
CPU time 1.06 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:06 PM PDT 24
Peak memory 224176 kb
Host smart-3825cd1c-b6f0-46b1-b9fc-da2bfa235fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335139992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1335139992
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2094058354
Short name T388
Test name
Test status
Simulation time 40721993 ps
CPU time 1.49 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 218888 kb
Host smart-e07284bf-5d9b-447c-bfe6-182c01523371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094058354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2094058354
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2444867917
Short name T108
Test name
Test status
Simulation time 30422504 ps
CPU time 0.84 seconds
Started Aug 14 05:32:56 PM PDT 24
Finished Aug 14 05:32:57 PM PDT 24
Peak memory 215816 kb
Host smart-5622f036-e62b-45d1-9abb-0ddc87ecc043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444867917 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2444867917
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1958503359
Short name T765
Test name
Test status
Simulation time 29713661 ps
CPU time 0.92 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 215600 kb
Host smart-118143d4-1fe7-4733-985e-cae2dbd14681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958503359 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1958503359
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1564919400
Short name T73
Test name
Test status
Simulation time 700427853 ps
CPU time 4.1 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 217452 kb
Host smart-42d4981f-26f7-47d0-ab76-67dbd9595e4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564919400 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1564919400
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2432470852
Short name T636
Test name
Test status
Simulation time 1554963753 ps
CPU time 41.35 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:33:40 PM PDT 24
Peak memory 218640 kb
Host smart-2e173eba-a095-49d5-8655-c2c8bf1c0e70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432470852 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2432470852
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1720332082
Short name T144
Test name
Test status
Simulation time 31392280 ps
CPU time 1.37 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:59 PM PDT 24
Peak memory 220512 kb
Host smart-0f9c575f-1b10-4830-bda2-4c09610d2b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720332082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1720332082
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.427572132
Short name T742
Test name
Test status
Simulation time 17419850 ps
CPU time 0.82 seconds
Started Aug 14 05:33:04 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 207140 kb
Host smart-06c1509d-f8f7-406a-bdab-831c610eb4ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427572132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.427572132
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3978910739
Short name T711
Test name
Test status
Simulation time 18295487 ps
CPU time 0.89 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 216508 kb
Host smart-da18ad22-7427-4021-ae7e-1d9e8e13dd2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978910739 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3978910739
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.3137018309
Short name T168
Test name
Test status
Simulation time 22536694 ps
CPU time 0.93 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 218640 kb
Host smart-bfbd7335-1977-4851-be60-db06edf8b5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137018309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3137018309
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.793567527
Short name T802
Test name
Test status
Simulation time 107297096 ps
CPU time 2.35 seconds
Started Aug 14 05:32:46 PM PDT 24
Finished Aug 14 05:32:49 PM PDT 24
Peak memory 220548 kb
Host smart-53f6680c-409e-4485-ae46-435c88b60c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793567527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.793567527
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_smoke.1796802774
Short name T26
Test name
Test status
Simulation time 26052656 ps
CPU time 0.96 seconds
Started Aug 14 05:32:53 PM PDT 24
Finished Aug 14 05:32:54 PM PDT 24
Peak memory 215716 kb
Host smart-435b2e61-bd21-4374-8301-35df73401dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796802774 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1796802774
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.945412545
Short name T470
Test name
Test status
Simulation time 234510304 ps
CPU time 2.59 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 215692 kb
Host smart-9e415f11-df0c-4920-a924-f81d7390b769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945412545 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.945412545
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1196528964
Short name T913
Test name
Test status
Simulation time 2096332664 ps
CPU time 30.56 seconds
Started Aug 14 05:33:04 PM PDT 24
Finished Aug 14 05:33:35 PM PDT 24
Peak memory 217768 kb
Host smart-cfe595d1-40d6-4d71-bf77-54fe2f9a7a83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196528964 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1196528964
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2434066185
Short name T420
Test name
Test status
Simulation time 99702158 ps
CPU time 1.27 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 215948 kb
Host smart-b8425257-d58f-453e-93cb-268be2cb549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434066185 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2434066185
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.893033652
Short name T400
Test name
Test status
Simulation time 21396743 ps
CPU time 0.82 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 207172 kb
Host smart-d0868166-9463-4283-b459-7bd7751e68a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893033652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.893033652
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1834382306
Short name T617
Test name
Test status
Simulation time 13674396 ps
CPU time 0.9 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 216752 kb
Host smart-493cf693-71c4-4233-8177-0847f9b26715
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834382306 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1834382306
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.669964023
Short name T440
Test name
Test status
Simulation time 43600658 ps
CPU time 1.29 seconds
Started Aug 14 05:32:48 PM PDT 24
Finished Aug 14 05:32:50 PM PDT 24
Peak memory 217252 kb
Host smart-bc580ec8-04af-4f31-a65a-de09f4250684
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669964023 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.669964023
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1443980329
Short name T134
Test name
Test status
Simulation time 28165069 ps
CPU time 1.23 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 216436 kb
Host smart-7cd9d315-b875-4379-9fa8-f7756f0a0b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443980329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1443980329
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2815249853
Short name T333
Test name
Test status
Simulation time 121601688 ps
CPU time 1.87 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 220356 kb
Host smart-e2606ea7-8b11-41c0-b4d4-ced796abf370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815249853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2815249853
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3738864781
Short name T39
Test name
Test status
Simulation time 33180023 ps
CPU time 0.98 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 215784 kb
Host smart-dfc14792-a995-479e-a2a9-6da764709f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738864781 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3738864781
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1557632257
Short name T810
Test name
Test status
Simulation time 26075291 ps
CPU time 0.93 seconds
Started Aug 14 05:32:51 PM PDT 24
Finished Aug 14 05:32:52 PM PDT 24
Peak memory 215596 kb
Host smart-b7ccb562-ab96-4609-a40e-493dba5a1963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557632257 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1557632257
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2763018190
Short name T919
Test name
Test status
Simulation time 327456355 ps
CPU time 2.39 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 217668 kb
Host smart-e9618e09-02cc-4606-912f-0510f0d49c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763018190 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2763018190
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3705466741
Short name T599
Test name
Test status
Simulation time 487873992 ps
CPU time 14.09 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:19 PM PDT 24
Peak memory 217888 kb
Host smart-402440f8-e20c-4829-834b-b1a90b392a47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705466741 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3705466741
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1992857564
Short name T662
Test name
Test status
Simulation time 35310792 ps
CPU time 1.14 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 219876 kb
Host smart-544a8552-bf4c-4d5a-8789-ce04209da14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992857564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1992857564
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1692269095
Short name T261
Test name
Test status
Simulation time 46151211 ps
CPU time 0.84 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 207300 kb
Host smart-b574f4c9-1f3a-4d70-ad55-b24aee0537f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692269095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1692269095
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.4244726311
Short name T738
Test name
Test status
Simulation time 19887432 ps
CPU time 0.85 seconds
Started Aug 14 05:33:20 PM PDT 24
Finished Aug 14 05:33:21 PM PDT 24
Peak memory 216720 kb
Host smart-39d528eb-058c-47ab-b414-57340c5e51ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244726311 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.4244726311
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3165448084
Short name T851
Test name
Test status
Simulation time 32538267 ps
CPU time 1.05 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 218792 kb
Host smart-be46cb02-954e-4d15-be68-2b0e9cbb1726
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165448084 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3165448084
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.4219294597
Short name T224
Test name
Test status
Simulation time 69941198 ps
CPU time 1.14 seconds
Started Aug 14 05:33:08 PM PDT 24
Finished Aug 14 05:33:09 PM PDT 24
Peak memory 226000 kb
Host smart-3dc0ff8e-1ec5-4117-92d6-eef6b1a530f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219294597 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.4219294597
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.284708616
Short name T733
Test name
Test status
Simulation time 78694645 ps
CPU time 1.14 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 217564 kb
Host smart-91e448cf-4ba3-4669-8b6c-094b0471240b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284708616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.284708616
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3603113644
Short name T770
Test name
Test status
Simulation time 20125768 ps
CPU time 1.11 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:07 PM PDT 24
Peak memory 216228 kb
Host smart-e85483ed-11b7-4cea-b8f2-98ae7aeb39c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603113644 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3603113644
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1771954134
Short name T84
Test name
Test status
Simulation time 18315517 ps
CPU time 1.07 seconds
Started Aug 14 05:32:54 PM PDT 24
Finished Aug 14 05:32:55 PM PDT 24
Peak memory 215532 kb
Host smart-227d4a69-edfc-4869-9cbd-35078f13e4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771954134 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1771954134
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3381495365
Short name T100
Test name
Test status
Simulation time 239902742 ps
CPU time 4.66 seconds
Started Aug 14 05:33:06 PM PDT 24
Finished Aug 14 05:33:13 PM PDT 24
Peak memory 215612 kb
Host smart-b1b82564-849a-4de1-963b-41df40650fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381495365 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3381495365
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_alert.1966508007
Short name T137
Test name
Test status
Simulation time 100617636 ps
CPU time 1.2 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 220156 kb
Host smart-4630676e-6f3f-473d-b55d-e8995d6967b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966508007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1966508007
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3859766456
Short name T696
Test name
Test status
Simulation time 46447694 ps
CPU time 0.87 seconds
Started Aug 14 05:33:17 PM PDT 24
Finished Aug 14 05:33:18 PM PDT 24
Peak memory 215276 kb
Host smart-b33be29c-cf9d-4826-a8ec-3368214c8acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859766456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3859766456
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2289281283
Short name T222
Test name
Test status
Simulation time 22513932 ps
CPU time 0.83 seconds
Started Aug 14 05:33:06 PM PDT 24
Finished Aug 14 05:33:07 PM PDT 24
Peak memory 216820 kb
Host smart-3b39b5ff-cef4-4392-83c1-e9fea6b9bfe5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289281283 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2289281283
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2940918627
Short name T569
Test name
Test status
Simulation time 28926930 ps
CPU time 1.17 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 215976 kb
Host smart-7419e76a-23e1-4caf-b838-6a8cfea5284c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940918627 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2940918627
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1929948805
Short name T177
Test name
Test status
Simulation time 23987382 ps
CPU time 1.01 seconds
Started Aug 14 05:33:04 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 224212 kb
Host smart-4027e154-1515-43ca-a7d8-6cb6678ab40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929948805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1929948805
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.69810573
Short name T329
Test name
Test status
Simulation time 313850118 ps
CPU time 1.11 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 220384 kb
Host smart-f28ba0c2-ae92-4233-8f66-394ba5f271dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69810573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.69810573
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1579527898
Short name T15
Test name
Test status
Simulation time 56187682 ps
CPU time 1.02 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 224116 kb
Host smart-427a6f82-feae-404b-bd49-8c48aca46bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579527898 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1579527898
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3726610352
Short name T720
Test name
Test status
Simulation time 15581830 ps
CPU time 0.95 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:06 PM PDT 24
Peak memory 215620 kb
Host smart-04270a46-ae9e-47ed-8661-506da83f29b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726610352 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3726610352
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1215876856
Short name T685
Test name
Test status
Simulation time 218252542 ps
CPU time 2.58 seconds
Started Aug 14 05:33:08 PM PDT 24
Finished Aug 14 05:33:11 PM PDT 24
Peak memory 217600 kb
Host smart-52df6136-b6bd-47e9-b0a7-667802e85a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215876856 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1215876856
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3550747336
Short name T237
Test name
Test status
Simulation time 4339796193 ps
CPU time 114.87 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:35:00 PM PDT 24
Peak memory 221864 kb
Host smart-d7956094-396e-4c4e-ae9e-e5e71b5a4006
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550747336 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3550747336
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert_test.3929439440
Short name T496
Test name
Test status
Simulation time 44948436 ps
CPU time 0.87 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 207120 kb
Host smart-75cf274c-06cd-4ae3-9870-48701eb51dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929439440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3929439440
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3792402208
Short name T850
Test name
Test status
Simulation time 46432422 ps
CPU time 0.94 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 216816 kb
Host smart-0daf2751-99f8-44fb-bfdf-3132f8e6297a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792402208 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3792402208
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3277575566
Short name T700
Test name
Test status
Simulation time 62290736 ps
CPU time 1.03 seconds
Started Aug 14 05:34:12 PM PDT 24
Finished Aug 14 05:34:14 PM PDT 24
Peak memory 218828 kb
Host smart-a3cd6dac-ef2c-4c70-bc4a-5c7cf0421e51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277575566 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3277575566
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1198828404
Short name T750
Test name
Test status
Simulation time 31283951 ps
CPU time 0.89 seconds
Started Aug 14 05:33:20 PM PDT 24
Finished Aug 14 05:33:21 PM PDT 24
Peak memory 218644 kb
Host smart-d4c4c0b7-624d-45ce-80c8-2ba6a398c72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198828404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1198828404
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2372275030
Short name T936
Test name
Test status
Simulation time 60184897 ps
CPU time 1.38 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 217484 kb
Host smart-b6898627-0a52-4c09-9840-a381703cf364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372275030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2372275030
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2719377984
Short name T513
Test name
Test status
Simulation time 20684942 ps
CPU time 1.09 seconds
Started Aug 14 05:33:09 PM PDT 24
Finished Aug 14 05:33:10 PM PDT 24
Peak memory 215784 kb
Host smart-70304cd6-9c9f-48f9-81e9-166ce2844606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719377984 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2719377984
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1119901073
Short name T573
Test name
Test status
Simulation time 48186273 ps
CPU time 0.9 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 215624 kb
Host smart-6fe25cf1-76e3-4739-8cfd-6cdca8872798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119901073 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1119901073
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3561912257
Short name T640
Test name
Test status
Simulation time 368840532 ps
CPU time 6.79 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:11 PM PDT 24
Peak memory 220496 kb
Host smart-1c8462ae-976c-4ad4-9d1f-953e1a3c38ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561912257 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3561912257
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1676694716
Short name T335
Test name
Test status
Simulation time 1123243997 ps
CPU time 27.07 seconds
Started Aug 14 05:33:08 PM PDT 24
Finished Aug 14 05:33:36 PM PDT 24
Peak memory 217796 kb
Host smart-4869630b-1b21-4b90-a8b1-09fae4440b51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676694716 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1676694716
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2928415482
Short name T447
Test name
Test status
Simulation time 45950353 ps
CPU time 1.21 seconds
Started Aug 14 05:33:04 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 220792 kb
Host smart-b474e07d-bc6b-4750-9e45-6fbe754fe175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928415482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2928415482
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2469124790
Short name T840
Test name
Test status
Simulation time 25103298 ps
CPU time 1.07 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 207208 kb
Host smart-181f61d9-fd18-41ed-b5db-9c755627b733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469124790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2469124790
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3116686357
Short name T223
Test name
Test status
Simulation time 15672852 ps
CPU time 0.87 seconds
Started Aug 14 05:33:07 PM PDT 24
Finished Aug 14 05:33:08 PM PDT 24
Peak memory 216856 kb
Host smart-c01801d4-9135-4ab4-8cad-fe50a6cf683b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116686357 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3116686357
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3926292002
Short name T369
Test name
Test status
Simulation time 61043973 ps
CPU time 1.04 seconds
Started Aug 14 05:34:13 PM PDT 24
Finished Aug 14 05:34:14 PM PDT 24
Peak memory 217244 kb
Host smart-5b16e422-a395-4712-8072-522d8350a298
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926292002 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3926292002
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.564621753
Short name T145
Test name
Test status
Simulation time 99757607 ps
CPU time 1.02 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 229952 kb
Host smart-1c0a3c67-d29d-42b2-a5ab-4c6be01ac389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564621753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.564621753
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3990781746
Short name T650
Test name
Test status
Simulation time 105273457 ps
CPU time 1.38 seconds
Started Aug 14 05:33:18 PM PDT 24
Finished Aug 14 05:33:19 PM PDT 24
Peak memory 219380 kb
Host smart-e1fd94dd-0664-411a-a114-d8fc07e342cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990781746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3990781746
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1749354084
Short name T126
Test name
Test status
Simulation time 39751628 ps
CPU time 0.87 seconds
Started Aug 14 05:33:06 PM PDT 24
Finished Aug 14 05:33:07 PM PDT 24
Peak memory 215836 kb
Host smart-1bbd1cf7-f88b-4e01-a57d-aa8775c249fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749354084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1749354084
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3152435823
Short name T706
Test name
Test status
Simulation time 25679687 ps
CPU time 0.91 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 215600 kb
Host smart-257769b0-2687-4cc1-bb95-47380bca61f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152435823 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3152435823
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2646420279
Short name T688
Test name
Test status
Simulation time 341991220 ps
CPU time 4.99 seconds
Started Aug 14 05:33:06 PM PDT 24
Finished Aug 14 05:33:11 PM PDT 24
Peak memory 215624 kb
Host smart-fc321cb7-7e7f-47af-b6f4-ab8a8aa69ea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646420279 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2646420279
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1336878269
Short name T46
Test name
Test status
Simulation time 1750149374 ps
CPU time 41.74 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:43 PM PDT 24
Peak memory 217948 kb
Host smart-5737c32c-3b3d-44fa-990b-705bdbcdcbdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336878269 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1336878269
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3086092197
Short name T477
Test name
Test status
Simulation time 29320747 ps
CPU time 1.38 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:06 PM PDT 24
Peak memory 218972 kb
Host smart-6e1f1fdc-3a81-4553-bfb2-301f46e9e601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086092197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3086092197
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.510301313
Short name T506
Test name
Test status
Simulation time 78079966 ps
CPU time 0.93 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 215308 kb
Host smart-ac977431-fe46-4b62-a4f6-d70deb04cd2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510301313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.510301313
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1502375418
Short name T979
Test name
Test status
Simulation time 18524947 ps
CPU time 0.85 seconds
Started Aug 14 05:33:06 PM PDT 24
Finished Aug 14 05:33:07 PM PDT 24
Peak memory 215736 kb
Host smart-22e9fc45-37e1-431d-95a6-fa5e2ff51803
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502375418 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1502375418
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2838806245
Short name T83
Test name
Test status
Simulation time 36227364 ps
CPU time 1.27 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 217216 kb
Host smart-13ca2772-a9a6-423f-b17f-56050d325a4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838806245 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2838806245
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_genbits.1918229312
Short name T764
Test name
Test status
Simulation time 84616652 ps
CPU time 2.71 seconds
Started Aug 14 05:33:06 PM PDT 24
Finished Aug 14 05:33:08 PM PDT 24
Peak memory 215600 kb
Host smart-8936716b-348c-4f6f-ad85-9086d228b63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918229312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1918229312
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3797038767
Short name T632
Test name
Test status
Simulation time 44963042 ps
CPU time 0.88 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 215772 kb
Host smart-8c1c1c7d-2f73-4b5c-9837-84f5089a3153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797038767 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3797038767
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2205656245
Short name T930
Test name
Test status
Simulation time 23811524 ps
CPU time 0.97 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 215568 kb
Host smart-31ff2c3e-73fd-426b-b8fc-f107f6672f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205656245 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2205656245
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_alert.3881797020
Short name T499
Test name
Test status
Simulation time 25196237 ps
CPU time 1.17 seconds
Started Aug 14 05:33:01 PM PDT 24
Finished Aug 14 05:33:02 PM PDT 24
Peak memory 219896 kb
Host smart-af4a6609-1d87-4639-972f-66ed36636c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881797020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3881797020
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1728460205
Short name T518
Test name
Test status
Simulation time 42548660 ps
CPU time 0.89 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 207068 kb
Host smart-9b4b30bc-fbcb-4030-8944-7a8e3450adcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728460205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1728460205
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2223927849
Short name T213
Test name
Test status
Simulation time 11293482 ps
CPU time 0.85 seconds
Started Aug 14 05:33:20 PM PDT 24
Finished Aug 14 05:33:21 PM PDT 24
Peak memory 216832 kb
Host smart-e97510ee-2a4c-43e9-90c0-f7ce97241593
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223927849 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2223927849
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2232420483
Short name T714
Test name
Test status
Simulation time 96747742 ps
CPU time 1.16 seconds
Started Aug 14 05:33:08 PM PDT 24
Finished Aug 14 05:33:09 PM PDT 24
Peak memory 217124 kb
Host smart-7a0e6095-4166-4838-966e-8f9e028c16a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232420483 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2232420483
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1136564517
Short name T809
Test name
Test status
Simulation time 20664886 ps
CPU time 1.11 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 219696 kb
Host smart-8f129f59-3d5b-4b92-8729-fca4dac31783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136564517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1136564517
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1380947918
Short name T752
Test name
Test status
Simulation time 89220902 ps
CPU time 3.12 seconds
Started Aug 14 05:33:23 PM PDT 24
Finished Aug 14 05:33:26 PM PDT 24
Peak memory 220716 kb
Host smart-235b5145-4415-4299-8afe-badeb442cfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380947918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1380947918
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.510488638
Short name T605
Test name
Test status
Simulation time 28983640 ps
CPU time 0.99 seconds
Started Aug 14 05:33:04 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 215720 kb
Host smart-a9edf8fb-7010-47b9-aa5d-6fd57edf2bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510488638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.510488638
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1858214497
Short name T868
Test name
Test status
Simulation time 22109291 ps
CPU time 0.94 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 215616 kb
Host smart-9ff0c87c-e3c3-4de8-8263-a2d00e653064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858214497 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1858214497
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2475591192
Short name T641
Test name
Test status
Simulation time 140418661 ps
CPU time 2.01 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 217588 kb
Host smart-9ce3a1b3-b5ce-4a17-a947-90680a1c8205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475591192 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2475591192
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2250349912
Short name T244
Test name
Test status
Simulation time 7297227527 ps
CPU time 70.05 seconds
Started Aug 14 05:33:08 PM PDT 24
Finished Aug 14 05:34:18 PM PDT 24
Peak memory 218076 kb
Host smart-318b4daf-29e9-440c-b0f4-f1f6bcac34ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250349912 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2250349912
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3553597251
Short name T34
Test name
Test status
Simulation time 79793647 ps
CPU time 1.14 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 218872 kb
Host smart-2ed90a42-10cf-433c-b686-dce333313072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553597251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3553597251
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1872931648
Short name T909
Test name
Test status
Simulation time 11831172 ps
CPU time 0.87 seconds
Started Aug 14 05:33:04 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 207084 kb
Host smart-c6f93274-8a22-44e5-a084-846b96f2c3fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872931648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1872931648
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1778463919
Short name T600
Test name
Test status
Simulation time 23066244 ps
CPU time 0.89 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 215660 kb
Host smart-165fe60a-0644-469e-aa4b-00a6a0895235
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778463919 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1778463919
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.4196578595
Short name T154
Test name
Test status
Simulation time 66769497 ps
CPU time 1 seconds
Started Aug 14 05:32:59 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 218860 kb
Host smart-f0f616bd-c41f-4c53-a7c3-6ce8a96e628a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196578595 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.4196578595
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3567402860
Short name T164
Test name
Test status
Simulation time 37132239 ps
CPU time 1.22 seconds
Started Aug 14 05:33:07 PM PDT 24
Finished Aug 14 05:33:09 PM PDT 24
Peak memory 230000 kb
Host smart-58072750-4917-4aa5-a97a-6d9706a159c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567402860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3567402860
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3458686447
Short name T442
Test name
Test status
Simulation time 61753540 ps
CPU time 1.49 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 219032 kb
Host smart-33b20c2c-fde2-4ce0-acbe-dc730f315afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458686447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3458686447
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.4052197707
Short name T111
Test name
Test status
Simulation time 22029700 ps
CPU time 1.07 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 215996 kb
Host smart-27e3930e-ef38-42b5-abf6-1512621c2fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052197707 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.4052197707
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.677433168
Short name T251
Test name
Test status
Simulation time 18849164 ps
CPU time 1.03 seconds
Started Aug 14 05:32:57 PM PDT 24
Finished Aug 14 05:32:58 PM PDT 24
Peak memory 215624 kb
Host smart-567a3213-f0b1-49cc-adc0-c25301c19f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677433168 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.677433168
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2681035014
Short name T257
Test name
Test status
Simulation time 31608856 ps
CPU time 0.94 seconds
Started Aug 14 05:33:08 PM PDT 24
Finished Aug 14 05:33:09 PM PDT 24
Peak memory 206888 kb
Host smart-e3af41fd-1e15-4642-8f56-ce5640cda086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681035014 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2681035014
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.4112922019
Short name T803
Test name
Test status
Simulation time 7351310970 ps
CPU time 75.7 seconds
Started Aug 14 05:33:04 PM PDT 24
Finished Aug 14 05:34:20 PM PDT 24
Peak memory 218576 kb
Host smart-c7cc0881-c96e-41d1-88ee-3fb363bcb892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112922019 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.4112922019
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2570516449
Short name T593
Test name
Test status
Simulation time 69193439 ps
CPU time 1.14 seconds
Started Aug 14 05:32:05 PM PDT 24
Finished Aug 14 05:32:06 PM PDT 24
Peak memory 221108 kb
Host smart-1731a3c2-3fae-4962-b7f3-2316e5d047d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570516449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2570516449
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3814164454
Short name T370
Test name
Test status
Simulation time 31456749 ps
CPU time 0.81 seconds
Started Aug 14 05:32:04 PM PDT 24
Finished Aug 14 05:32:05 PM PDT 24
Peak memory 206424 kb
Host smart-8dd11ff3-4c4d-41e1-9f9f-aed35d2df7bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814164454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3814164454
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3676711090
Short name T932
Test name
Test status
Simulation time 52383196 ps
CPU time 0.81 seconds
Started Aug 14 05:32:06 PM PDT 24
Finished Aug 14 05:32:07 PM PDT 24
Peak memory 216836 kb
Host smart-c6a0439a-1665-46fe-ae8d-b630b5dd0477
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676711090 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3676711090
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.292169446
Short name T159
Test name
Test status
Simulation time 64989981 ps
CPU time 1.31 seconds
Started Aug 14 05:32:06 PM PDT 24
Finished Aug 14 05:32:08 PM PDT 24
Peak memory 217152 kb
Host smart-ecc0ee43-804c-483f-b99d-804f3110f533
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292169446 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.292169446
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3795172870
Short name T71
Test name
Test status
Simulation time 23481023 ps
CPU time 1.02 seconds
Started Aug 14 05:32:01 PM PDT 24
Finished Aug 14 05:32:02 PM PDT 24
Peak memory 218624 kb
Host smart-57e3da92-4c81-44d8-a552-a3d79ef76c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795172870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3795172870
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2153053097
Short name T977
Test name
Test status
Simulation time 69518252 ps
CPU time 1.18 seconds
Started Aug 14 05:32:03 PM PDT 24
Finished Aug 14 05:32:05 PM PDT 24
Peak memory 217488 kb
Host smart-319d01e0-e46d-47f3-80ea-a164f686e45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153053097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2153053097
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1180381705
Short name T455
Test name
Test status
Simulation time 24487967 ps
CPU time 0.94 seconds
Started Aug 14 05:32:06 PM PDT 24
Finished Aug 14 05:32:07 PM PDT 24
Peak memory 215792 kb
Host smart-49ac3028-4fd2-4191-b450-0ebbe6a4bc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180381705 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1180381705
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1535816506
Short name T916
Test name
Test status
Simulation time 18284141 ps
CPU time 1.03 seconds
Started Aug 14 05:32:09 PM PDT 24
Finished Aug 14 05:32:10 PM PDT 24
Peak memory 207420 kb
Host smart-80e603fa-a019-42dc-8220-38146b870023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535816506 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1535816506
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2598258480
Short name T501
Test name
Test status
Simulation time 29320233 ps
CPU time 0.92 seconds
Started Aug 14 05:32:08 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 215616 kb
Host smart-b55955fc-8034-4fb6-8254-6a5cf4319fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598258480 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2598258480
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3383336885
Short name T814
Test name
Test status
Simulation time 223279622 ps
CPU time 2.81 seconds
Started Aug 14 05:31:58 PM PDT 24
Finished Aug 14 05:32:01 PM PDT 24
Peak memory 219792 kb
Host smart-50c9671a-a649-48be-a4e1-c1b0d4628c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383336885 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3383336885
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.4063147941
Short name T705
Test name
Test status
Simulation time 3091384682 ps
CPU time 88.15 seconds
Started Aug 14 05:32:05 PM PDT 24
Finished Aug 14 05:33:33 PM PDT 24
Peak memory 218136 kb
Host smart-f07f2cce-b970-4ea8-9629-87a33ccb45d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063147941 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.4063147941
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.1264472720
Short name T315
Test name
Test status
Simulation time 89815635 ps
CPU time 1.31 seconds
Started Aug 14 05:32:58 PM PDT 24
Finished Aug 14 05:33:00 PM PDT 24
Peak memory 218756 kb
Host smart-e1687044-799b-4a45-bb35-5aabcfc11b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264472720 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.1264472720
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.2977578628
Short name T132
Test name
Test status
Simulation time 32986266 ps
CPU time 0.95 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:06 PM PDT 24
Peak memory 219992 kb
Host smart-3b7786a2-6b31-4b44-a84e-e99b353b367d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977578628 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2977578628
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.810144291
Short name T321
Test name
Test status
Simulation time 71278561 ps
CPU time 1.65 seconds
Started Aug 14 05:33:00 PM PDT 24
Finished Aug 14 05:33:01 PM PDT 24
Peak memory 220308 kb
Host smart-30ea6154-00ad-480e-ae08-7f7e5021d9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810144291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.810144291
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1751981149
Short name T935
Test name
Test status
Simulation time 73177170 ps
CPU time 1.09 seconds
Started Aug 14 05:33:07 PM PDT 24
Finished Aug 14 05:33:10 PM PDT 24
Peak memory 220356 kb
Host smart-f01e7f41-9760-447c-a74d-953a89efe46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751981149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1751981149
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2294953957
Short name T64
Test name
Test status
Simulation time 22411850 ps
CPU time 1.22 seconds
Started Aug 14 05:33:08 PM PDT 24
Finished Aug 14 05:33:09 PM PDT 24
Peak memory 224212 kb
Host smart-3d5c9f7b-a395-44b3-adf0-3152fe22898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294953957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2294953957
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1401005679
Short name T97
Test name
Test status
Simulation time 218755084 ps
CPU time 2.89 seconds
Started Aug 14 05:33:08 PM PDT 24
Finished Aug 14 05:33:11 PM PDT 24
Peak memory 219112 kb
Host smart-a8d8881a-442d-475a-998a-67578d040f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401005679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1401005679
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1180962432
Short name T596
Test name
Test status
Simulation time 30770128 ps
CPU time 1.32 seconds
Started Aug 14 05:33:02 PM PDT 24
Finished Aug 14 05:33:03 PM PDT 24
Peak memory 221016 kb
Host smart-92d1823a-716f-4310-9fc7-7bf33c3815ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180962432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1180962432
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3994265798
Short name T794
Test name
Test status
Simulation time 41282051 ps
CPU time 1.06 seconds
Started Aug 14 05:34:13 PM PDT 24
Finished Aug 14 05:34:14 PM PDT 24
Peak memory 224180 kb
Host smart-16ac5369-dfb2-4967-9a8d-33499d7cdfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994265798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3994265798
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.652312165
Short name T432
Test name
Test status
Simulation time 80101693 ps
CPU time 1.07 seconds
Started Aug 14 05:33:07 PM PDT 24
Finished Aug 14 05:33:08 PM PDT 24
Peak memory 217504 kb
Host smart-54a2c5df-3a50-46dd-b228-5ff607341243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652312165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.652312165
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1175908363
Short name T312
Test name
Test status
Simulation time 44378506 ps
CPU time 1.13 seconds
Started Aug 14 05:33:40 PM PDT 24
Finished Aug 14 05:33:42 PM PDT 24
Peak memory 218752 kb
Host smart-754f873c-9eff-4043-8864-4bfd43155d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175908363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1175908363
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2185429133
Short name T444
Test name
Test status
Simulation time 32208290 ps
CPU time 0.78 seconds
Started Aug 14 05:33:09 PM PDT 24
Finished Aug 14 05:33:10 PM PDT 24
Peak memory 218472 kb
Host smart-9cb8f62a-f1eb-4d0b-a70a-a665471c62c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185429133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2185429133
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2133016739
Short name T461
Test name
Test status
Simulation time 29383703 ps
CPU time 1.21 seconds
Started Aug 14 05:33:16 PM PDT 24
Finished Aug 14 05:33:18 PM PDT 24
Peak memory 220212 kb
Host smart-264784ea-73cb-405a-859d-ebc1b2e1d3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133016739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2133016739
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.357551550
Short name T200
Test name
Test status
Simulation time 93977833 ps
CPU time 1.21 seconds
Started Aug 14 05:33:47 PM PDT 24
Finished Aug 14 05:33:49 PM PDT 24
Peak memory 220880 kb
Host smart-65ed4034-778b-4fb3-b148-214bd4727fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357551550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.357551550
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.1157712055
Short name T458
Test name
Test status
Simulation time 35090998 ps
CPU time 0.98 seconds
Started Aug 14 05:34:35 PM PDT 24
Finished Aug 14 05:34:37 PM PDT 24
Peak memory 223800 kb
Host smart-44c1eca4-4163-43cd-8efb-32d7dafc56d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157712055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1157712055
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2134998941
Short name T881
Test name
Test status
Simulation time 203553162 ps
CPU time 1.09 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:04 PM PDT 24
Peak memory 217372 kb
Host smart-3b3e9abf-5a34-455f-99ef-d07dc977cd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134998941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2134998941
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1134782207
Short name T703
Test name
Test status
Simulation time 51570303 ps
CPU time 1.25 seconds
Started Aug 14 05:33:09 PM PDT 24
Finished Aug 14 05:33:10 PM PDT 24
Peak memory 218868 kb
Host smart-576d4417-b46e-4df5-b1d9-fbf8849d4596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134782207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1134782207
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.382242802
Short name T709
Test name
Test status
Simulation time 29623839 ps
CPU time 1.27 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:07 PM PDT 24
Peak memory 220056 kb
Host smart-074239d2-ab3e-435c-b491-4970144f7d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382242802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.382242802
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3400152167
Short name T623
Test name
Test status
Simulation time 57788993 ps
CPU time 1.19 seconds
Started Aug 14 05:33:43 PM PDT 24
Finished Aug 14 05:33:45 PM PDT 24
Peak memory 219012 kb
Host smart-262816d5-45fd-42a3-8f6e-c1f2a41909fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400152167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3400152167
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.564568332
Short name T162
Test name
Test status
Simulation time 149534964 ps
CPU time 1.16 seconds
Started Aug 14 05:33:06 PM PDT 24
Finished Aug 14 05:33:07 PM PDT 24
Peak memory 218908 kb
Host smart-86c963c1-f2ee-4678-8f4c-83c72c33832b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564568332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.564568332
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1127105692
Short name T310
Test name
Test status
Simulation time 42295853 ps
CPU time 1.28 seconds
Started Aug 14 05:33:04 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 225676 kb
Host smart-1a46a115-ba7e-4a68-953d-c27b23a53e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127105692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1127105692
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3973891401
Short name T859
Test name
Test status
Simulation time 62339062 ps
CPU time 1.03 seconds
Started Aug 14 05:33:14 PM PDT 24
Finished Aug 14 05:33:15 PM PDT 24
Peak memory 219384 kb
Host smart-ff260c17-1f95-42b2-a965-fd4d9fe83d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973891401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3973891401
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.1528085685
Short name T401
Test name
Test status
Simulation time 30334374 ps
CPU time 1.33 seconds
Started Aug 14 05:33:09 PM PDT 24
Finished Aug 14 05:33:10 PM PDT 24
Peak memory 220028 kb
Host smart-b2cb36c8-8725-484c-b7c5-e5d8fe228e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528085685 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1528085685
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1079745860
Short name T418
Test name
Test status
Simulation time 24332363 ps
CPU time 0.99 seconds
Started Aug 14 05:33:04 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 218700 kb
Host smart-734da26e-4de4-4a3a-9939-fc3edff0b0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079745860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1079745860
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1118182497
Short name T805
Test name
Test status
Simulation time 47183186 ps
CPU time 1.4 seconds
Started Aug 14 05:33:18 PM PDT 24
Finished Aug 14 05:33:19 PM PDT 24
Peak memory 219012 kb
Host smart-ffb682bc-0611-47dc-9079-74df5bb3c6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118182497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1118182497
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1838532301
Short name T229
Test name
Test status
Simulation time 24572866 ps
CPU time 1.15 seconds
Started Aug 14 05:33:13 PM PDT 24
Finished Aug 14 05:33:14 PM PDT 24
Peak memory 218944 kb
Host smart-4f5dfc08-aacb-4c13-a836-d50645486fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838532301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1838532301
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.1702179128
Short name T133
Test name
Test status
Simulation time 95694459 ps
CPU time 0.91 seconds
Started Aug 14 05:33:19 PM PDT 24
Finished Aug 14 05:33:20 PM PDT 24
Peak memory 220044 kb
Host smart-54362404-3aa7-4528-8bee-354b6c379495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702179128 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1702179128
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.460633165
Short name T737
Test name
Test status
Simulation time 96293905 ps
CPU time 1.51 seconds
Started Aug 14 05:33:44 PM PDT 24
Finished Aug 14 05:33:45 PM PDT 24
Peak memory 219276 kb
Host smart-067dfb47-a183-42af-b16a-cde2005b1c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460633165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.460633165
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3558251859
Short name T887
Test name
Test status
Simulation time 26722167 ps
CPU time 1.24 seconds
Started Aug 14 05:33:07 PM PDT 24
Finished Aug 14 05:33:14 PM PDT 24
Peak memory 219704 kb
Host smart-86573b50-0935-47b7-8865-f5afffdec0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558251859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3558251859
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3243728260
Short name T204
Test name
Test status
Simulation time 18642608 ps
CPU time 1.08 seconds
Started Aug 14 05:33:16 PM PDT 24
Finished Aug 14 05:33:18 PM PDT 24
Peak memory 218784 kb
Host smart-2cf91083-6686-41b6-9c1e-4a16ed33a565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243728260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3243728260
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3840527909
Short name T510
Test name
Test status
Simulation time 61509455 ps
CPU time 2.25 seconds
Started Aug 14 05:33:36 PM PDT 24
Finished Aug 14 05:33:38 PM PDT 24
Peak memory 217932 kb
Host smart-adf9b8a2-c726-40eb-99a7-48b2d6624cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840527909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3840527909
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3258393927
Short name T77
Test name
Test status
Simulation time 26179644 ps
CPU time 1.22 seconds
Started Aug 14 05:32:04 PM PDT 24
Finished Aug 14 05:32:06 PM PDT 24
Peak memory 218908 kb
Host smart-77dfc89f-f886-4964-9bfb-a34d7413fe04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258393927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3258393927
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2498570275
Short name T67
Test name
Test status
Simulation time 27847122 ps
CPU time 1.09 seconds
Started Aug 14 05:32:06 PM PDT 24
Finished Aug 14 05:32:08 PM PDT 24
Peak memory 207024 kb
Host smart-ffc785f3-c1c7-4676-b938-b2c669a235bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498570275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2498570275
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.4052936893
Short name T486
Test name
Test status
Simulation time 37520762 ps
CPU time 0.86 seconds
Started Aug 14 05:31:58 PM PDT 24
Finished Aug 14 05:31:59 PM PDT 24
Peak memory 219496 kb
Host smart-fbffb8cb-a8f5-4082-88b8-b94c6d60ae55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052936893 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.4052936893
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3898949644
Short name T76
Test name
Test status
Simulation time 70385514 ps
CPU time 0.99 seconds
Started Aug 14 05:32:06 PM PDT 24
Finished Aug 14 05:32:07 PM PDT 24
Peak memory 217124 kb
Host smart-eb11ce86-d625-48da-a8a5-226691d11ec2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898949644 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3898949644
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.4047494191
Short name T138
Test name
Test status
Simulation time 26989948 ps
CPU time 1.36 seconds
Started Aug 14 05:31:58 PM PDT 24
Finished Aug 14 05:32:00 PM PDT 24
Peak memory 217628 kb
Host smart-276e208b-15b1-4164-8416-f3605124b3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047494191 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.4047494191
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.669584202
Short name T914
Test name
Test status
Simulation time 32234120 ps
CPU time 1.49 seconds
Started Aug 14 05:32:06 PM PDT 24
Finished Aug 14 05:32:08 PM PDT 24
Peak memory 218748 kb
Host smart-d9c0ce3d-424e-4aff-b7ac-c540ab057f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669584202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.669584202
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2859687360
Short name T562
Test name
Test status
Simulation time 50349485 ps
CPU time 0.84 seconds
Started Aug 14 05:32:08 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 215604 kb
Host smart-d2b3eaf4-99ac-45e4-ac48-f319d2ca2951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859687360 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2859687360
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.37503770
Short name T311
Test name
Test status
Simulation time 28920740 ps
CPU time 0.98 seconds
Started Aug 14 05:32:03 PM PDT 24
Finished Aug 14 05:32:04 PM PDT 24
Peak memory 207360 kb
Host smart-b75a84eb-fbfb-4337-902f-b35f22347ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37503770 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.37503770
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.764544464
Short name T493
Test name
Test status
Simulation time 16777199 ps
CPU time 1.03 seconds
Started Aug 14 05:32:03 PM PDT 24
Finished Aug 14 05:32:04 PM PDT 24
Peak memory 215604 kb
Host smart-d47f101f-94b7-4d5f-940e-f8df0b9d92e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764544464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.764544464
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2759146260
Short name T694
Test name
Test status
Simulation time 667369106 ps
CPU time 4.35 seconds
Started Aug 14 05:32:01 PM PDT 24
Finished Aug 14 05:32:06 PM PDT 24
Peak memory 217720 kb
Host smart-1864dd45-0425-4dc2-814a-db440a56032a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759146260 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2759146260
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1511176590
Short name T236
Test name
Test status
Simulation time 4467593449 ps
CPU time 85.91 seconds
Started Aug 14 05:32:12 PM PDT 24
Finished Aug 14 05:33:38 PM PDT 24
Peak memory 224184 kb
Host smart-858515f1-153b-468c-abfa-d406dd9f9917
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511176590 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1511176590
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.556542280
Short name T645
Test name
Test status
Simulation time 28703013 ps
CPU time 1.3 seconds
Started Aug 14 05:33:11 PM PDT 24
Finished Aug 14 05:33:12 PM PDT 24
Peak memory 217056 kb
Host smart-64ec3e69-6e9a-4ba9-9cca-451822a0a382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556542280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.556542280
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.524780727
Short name T185
Test name
Test status
Simulation time 22976496 ps
CPU time 1.14 seconds
Started Aug 14 05:33:06 PM PDT 24
Finished Aug 14 05:33:08 PM PDT 24
Peak memory 224308 kb
Host smart-5790847b-ef3d-45b6-bfe2-59b777ba8eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524780727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.524780727
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2032824545
Short name T621
Test name
Test status
Simulation time 57590832 ps
CPU time 1.45 seconds
Started Aug 14 05:33:09 PM PDT 24
Finished Aug 14 05:33:11 PM PDT 24
Peak memory 219004 kb
Host smart-363509ac-b54e-4a27-a213-f9cbb4a8ae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032824545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2032824545
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.3068400928
Short name T68
Test name
Test status
Simulation time 80610177 ps
CPU time 1.12 seconds
Started Aug 14 05:33:40 PM PDT 24
Finished Aug 14 05:33:42 PM PDT 24
Peak memory 219280 kb
Host smart-f25472f8-6ef5-4492-b700-580b7d080f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068400928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.3068400928
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_genbits.301051708
Short name T611
Test name
Test status
Simulation time 34207276 ps
CPU time 1.15 seconds
Started Aug 14 05:34:41 PM PDT 24
Finished Aug 14 05:34:43 PM PDT 24
Peak memory 219048 kb
Host smart-b8ab1c8e-4989-4a5e-bb65-52789deefb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301051708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.301051708
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.903825182
Short name T689
Test name
Test status
Simulation time 346774193 ps
CPU time 1.18 seconds
Started Aug 14 05:33:10 PM PDT 24
Finished Aug 14 05:33:11 PM PDT 24
Peak memory 218620 kb
Host smart-f681c7a1-bbab-44e4-9be7-29006fc3a517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903825182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.903825182
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1036684916
Short name T173
Test name
Test status
Simulation time 19851980 ps
CPU time 0.99 seconds
Started Aug 14 05:33:30 PM PDT 24
Finished Aug 14 05:33:31 PM PDT 24
Peak memory 218700 kb
Host smart-772a5aff-a995-405d-b585-0ba8e93e4f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036684916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1036684916
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2716764598
Short name T431
Test name
Test status
Simulation time 95783716 ps
CPU time 1.22 seconds
Started Aug 14 05:33:03 PM PDT 24
Finished Aug 14 05:33:05 PM PDT 24
Peak memory 217656 kb
Host smart-d16e1af8-8b8c-4747-a1bd-c805784ad7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716764598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2716764598
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.1015104022
Short name T880
Test name
Test status
Simulation time 90399549 ps
CPU time 1.1 seconds
Started Aug 14 05:33:40 PM PDT 24
Finished Aug 14 05:33:41 PM PDT 24
Peak memory 220084 kb
Host smart-a251df05-964d-4c29-ad67-85eb32592ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015104022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.1015104022
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.2731291372
Short name T452
Test name
Test status
Simulation time 36850291 ps
CPU time 0.86 seconds
Started Aug 14 05:33:07 PM PDT 24
Finished Aug 14 05:33:08 PM PDT 24
Peak memory 218508 kb
Host smart-63c82ab5-52ef-40ab-96b5-e09269972086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731291372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2731291372
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2975532374
Short name T815
Test name
Test status
Simulation time 82337164 ps
CPU time 1.13 seconds
Started Aug 14 05:34:42 PM PDT 24
Finished Aug 14 05:34:43 PM PDT 24
Peak memory 217372 kb
Host smart-70cf37a2-6e47-442b-84ce-9c32af3be0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975532374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2975532374
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2398803603
Short name T825
Test name
Test status
Simulation time 101527060 ps
CPU time 1.22 seconds
Started Aug 14 05:33:44 PM PDT 24
Finished Aug 14 05:33:45 PM PDT 24
Peak memory 215948 kb
Host smart-7a95f572-8395-4a42-a8f2-1060e4d8eb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398803603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2398803603
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2772963694
Short name T540
Test name
Test status
Simulation time 42845312 ps
CPU time 0.92 seconds
Started Aug 14 05:33:13 PM PDT 24
Finished Aug 14 05:33:14 PM PDT 24
Peak memory 218544 kb
Host smart-f7f3b67a-59c5-40df-be9a-a111e5b4e62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772963694 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2772963694
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2420365377
Short name T536
Test name
Test status
Simulation time 50748017 ps
CPU time 1.59 seconds
Started Aug 14 05:33:08 PM PDT 24
Finished Aug 14 05:33:10 PM PDT 24
Peak memory 218904 kb
Host smart-dd937770-4f92-45cc-9ad8-3c8929065b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420365377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2420365377
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3020522287
Short name T559
Test name
Test status
Simulation time 36625794 ps
CPU time 1.15 seconds
Started Aug 14 05:33:06 PM PDT 24
Finished Aug 14 05:33:08 PM PDT 24
Peak memory 220112 kb
Host smart-5edee93c-2711-4e5d-ba8c-8650369b64b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020522287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3020522287
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.3871601661
Short name T920
Test name
Test status
Simulation time 18182158 ps
CPU time 1.08 seconds
Started Aug 14 05:33:18 PM PDT 24
Finished Aug 14 05:33:19 PM PDT 24
Peak memory 218820 kb
Host smart-02859a42-5620-48d5-9ed1-ac8a42076d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871601661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3871601661
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/66.edn_alert.1211439908
Short name T187
Test name
Test status
Simulation time 28400250 ps
CPU time 1.25 seconds
Started Aug 14 05:33:11 PM PDT 24
Finished Aug 14 05:33:12 PM PDT 24
Peak memory 216008 kb
Host smart-04c69c50-bcf2-4d9c-82af-dd299497b018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211439908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1211439908
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1559388400
Short name T139
Test name
Test status
Simulation time 52279344 ps
CPU time 1.04 seconds
Started Aug 14 05:33:43 PM PDT 24
Finished Aug 14 05:33:44 PM PDT 24
Peak memory 220816 kb
Host smart-e2d2fae8-2f67-4699-a5b3-7fc47e701acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559388400 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1559388400
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2401127364
Short name T793
Test name
Test status
Simulation time 33463911 ps
CPU time 1.3 seconds
Started Aug 14 05:33:34 PM PDT 24
Finished Aug 14 05:33:35 PM PDT 24
Peak memory 217760 kb
Host smart-fd069131-484d-4d48-bb72-49af67b728dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401127364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2401127364
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2162274274
Short name T606
Test name
Test status
Simulation time 27448621 ps
CPU time 1.2 seconds
Started Aug 14 05:33:05 PM PDT 24
Finished Aug 14 05:33:07 PM PDT 24
Peak memory 218900 kb
Host smart-5642626f-3e5a-4d83-9821-449456236f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162274274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2162274274
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1361325484
Short name T876
Test name
Test status
Simulation time 33552252 ps
CPU time 0.93 seconds
Started Aug 14 05:33:07 PM PDT 24
Finished Aug 14 05:33:08 PM PDT 24
Peak memory 219924 kb
Host smart-0cec028e-9f24-4f57-9367-f307f3e5b9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361325484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1361325484
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.920944333
Short name T963
Test name
Test status
Simulation time 86158649 ps
CPU time 1.16 seconds
Started Aug 14 05:33:43 PM PDT 24
Finished Aug 14 05:33:44 PM PDT 24
Peak memory 218952 kb
Host smart-ae43365c-053c-4d95-99c3-fd0417da64e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920944333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.920944333
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1515948009
Short name T10
Test name
Test status
Simulation time 104363589 ps
CPU time 1.2 seconds
Started Aug 14 05:33:29 PM PDT 24
Finished Aug 14 05:33:30 PM PDT 24
Peak memory 220152 kb
Host smart-9c99ccbe-7c6c-4729-9f62-4d644950ea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515948009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1515948009
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.142643710
Short name T190
Test name
Test status
Simulation time 19673458 ps
CPU time 1.06 seconds
Started Aug 14 05:33:45 PM PDT 24
Finished Aug 14 05:33:46 PM PDT 24
Peak memory 218704 kb
Host smart-aa82dd28-ebc2-40e6-881e-9f2b1f1b554e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142643710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.142643710
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.922606162
Short name T660
Test name
Test status
Simulation time 43432442 ps
CPU time 1.75 seconds
Started Aug 14 05:33:08 PM PDT 24
Finished Aug 14 05:33:09 PM PDT 24
Peak memory 219048 kb
Host smart-c6834b53-8f83-4202-b304-9811d71a9395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922606162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.922606162
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.4079719175
Short name T122
Test name
Test status
Simulation time 25177382 ps
CPU time 1.28 seconds
Started Aug 14 05:33:16 PM PDT 24
Finished Aug 14 05:33:18 PM PDT 24
Peak memory 220120 kb
Host smart-367b378c-0eb8-48af-b84a-3ea12338e61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079719175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.4079719175
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.732919488
Short name T196
Test name
Test status
Simulation time 24961577 ps
CPU time 0.9 seconds
Started Aug 14 05:33:16 PM PDT 24
Finished Aug 14 05:33:18 PM PDT 24
Peak memory 218464 kb
Host smart-50b45257-b3b9-4609-9920-add307b2fdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732919488 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.732919488
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3184757171
Short name T29
Test name
Test status
Simulation time 79049860 ps
CPU time 1.23 seconds
Started Aug 14 05:33:08 PM PDT 24
Finished Aug 14 05:33:09 PM PDT 24
Peak memory 215612 kb
Host smart-6b94cffd-675d-4be3-a6b0-a406305c75b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184757171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3184757171
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.707176608
Short name T49
Test name
Test status
Simulation time 45882691 ps
CPU time 1.02 seconds
Started Aug 14 05:32:08 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 218884 kb
Host smart-751c3a04-1b5e-44b5-bc89-82cbd593d5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707176608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.707176608
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.109864429
Short name T931
Test name
Test status
Simulation time 39932269 ps
CPU time 0.83 seconds
Started Aug 14 05:32:08 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 215540 kb
Host smart-403ad528-083a-4556-bb44-9ef3aeaf5d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109864429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.109864429
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1295744463
Short name T670
Test name
Test status
Simulation time 19042865 ps
CPU time 0.99 seconds
Started Aug 14 05:32:07 PM PDT 24
Finished Aug 14 05:32:08 PM PDT 24
Peak memory 215720 kb
Host smart-862e571e-c2bf-4339-ab91-ddfbd38405b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295744463 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1295744463
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3659436126
Short name T292
Test name
Test status
Simulation time 34390174 ps
CPU time 1.26 seconds
Started Aug 14 05:32:06 PM PDT 24
Finished Aug 14 05:32:08 PM PDT 24
Peak memory 218764 kb
Host smart-d58e4317-f2fa-49fa-9f6e-aa8d6ca260c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659436126 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3659436126
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1208871327
Short name T220
Test name
Test status
Simulation time 58484838 ps
CPU time 1.12 seconds
Started Aug 14 05:32:08 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 224328 kb
Host smart-8fda7952-b113-468e-a986-aef302cfa8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208871327 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1208871327
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1944959870
Short name T102
Test name
Test status
Simulation time 34855824 ps
CPU time 1.49 seconds
Started Aug 14 05:32:03 PM PDT 24
Finished Aug 14 05:32:04 PM PDT 24
Peak memory 220232 kb
Host smart-266106f2-e133-4db8-bb95-f2963531e7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944959870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1944959870
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2406166373
Short name T889
Test name
Test status
Simulation time 42711439 ps
CPU time 0.91 seconds
Started Aug 14 05:32:06 PM PDT 24
Finished Aug 14 05:32:07 PM PDT 24
Peak memory 215608 kb
Host smart-1a8930c8-b286-44a7-bdaf-83d71cd79877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406166373 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2406166373
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.4034884841
Short name T776
Test name
Test status
Simulation time 140422887 ps
CPU time 0.88 seconds
Started Aug 14 05:32:05 PM PDT 24
Finished Aug 14 05:32:06 PM PDT 24
Peak memory 207368 kb
Host smart-2dd19746-9354-4fd1-8fcf-4470da207b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034884841 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4034884841
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2489954525
Short name T372
Test name
Test status
Simulation time 48395902 ps
CPU time 0.92 seconds
Started Aug 14 05:32:14 PM PDT 24
Finished Aug 14 05:32:15 PM PDT 24
Peak memory 215604 kb
Host smart-755db571-9892-4b28-a06d-862675989777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489954525 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2489954525
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3186653557
Short name T556
Test name
Test status
Simulation time 18439909 ps
CPU time 0.93 seconds
Started Aug 14 05:31:59 PM PDT 24
Finished Aug 14 05:32:00 PM PDT 24
Peak memory 206764 kb
Host smart-014a22b5-27f5-4d16-a784-70d2c8cc0881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186653557 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3186653557
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/70.edn_alert.811077835
Short name T293
Test name
Test status
Simulation time 31445709 ps
CPU time 1.41 seconds
Started Aug 14 05:34:04 PM PDT 24
Finished Aug 14 05:34:06 PM PDT 24
Peak memory 214996 kb
Host smart-796bf8cb-a8e3-491c-b7d2-386ef78cc09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811077835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.811077835
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.3289848874
Short name T358
Test name
Test status
Simulation time 37771990 ps
CPU time 1.2 seconds
Started Aug 14 05:33:21 PM PDT 24
Finished Aug 14 05:33:22 PM PDT 24
Peak memory 219920 kb
Host smart-63fded74-158e-4914-b887-02615c996162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289848874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3289848874
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.4035699148
Short name T727
Test name
Test status
Simulation time 83579182 ps
CPU time 1.34 seconds
Started Aug 14 05:33:12 PM PDT 24
Finished Aug 14 05:33:13 PM PDT 24
Peak memory 219392 kb
Host smart-e4fcc0e4-8f17-4a9b-8867-9e160ac66d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035699148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.4035699148
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2976503180
Short name T450
Test name
Test status
Simulation time 51665426 ps
CPU time 1.2 seconds
Started Aug 14 05:33:24 PM PDT 24
Finished Aug 14 05:33:26 PM PDT 24
Peak memory 219516 kb
Host smart-6d314f4b-f2d6-4d31-a123-b1edf688684b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976503180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2976503180
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.3408553247
Short name T181
Test name
Test status
Simulation time 24195976 ps
CPU time 0.91 seconds
Started Aug 14 05:33:15 PM PDT 24
Finished Aug 14 05:33:16 PM PDT 24
Peak memory 218884 kb
Host smart-a50345cd-ee08-4fa1-9833-c4b6fc4a7eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408553247 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3408553247
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1220549777
Short name T771
Test name
Test status
Simulation time 151583579 ps
CPU time 1.47 seconds
Started Aug 14 05:33:13 PM PDT 24
Finished Aug 14 05:33:15 PM PDT 24
Peak memory 219348 kb
Host smart-cc2829fa-994b-40fb-8e42-170ec8475ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220549777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1220549777
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.521696546
Short name T958
Test name
Test status
Simulation time 140171915 ps
CPU time 1.2 seconds
Started Aug 14 05:33:19 PM PDT 24
Finished Aug 14 05:33:21 PM PDT 24
Peak memory 218616 kb
Host smart-f324d20d-f20e-4bd9-99ec-ac4db9556499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521696546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.521696546
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3339198819
Short name T875
Test name
Test status
Simulation time 29738713 ps
CPU time 1.33 seconds
Started Aug 14 05:33:23 PM PDT 24
Finished Aug 14 05:33:24 PM PDT 24
Peak memory 225944 kb
Host smart-ab2e0dc5-9493-47cf-9ee4-9f3792de4207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339198819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3339198819
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.393726955
Short name T907
Test name
Test status
Simulation time 60807725 ps
CPU time 1.44 seconds
Started Aug 14 05:33:28 PM PDT 24
Finished Aug 14 05:33:29 PM PDT 24
Peak memory 220312 kb
Host smart-33a5d193-e9cb-40d1-ab2b-0786f6ed2226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393726955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.393726955
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.1661363681
Short name T845
Test name
Test status
Simulation time 83947793 ps
CPU time 1.2 seconds
Started Aug 14 05:33:18 PM PDT 24
Finished Aug 14 05:33:19 PM PDT 24
Peak memory 219980 kb
Host smart-59c33830-18e1-4a84-96d6-5ffed5078dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661363681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.1661363681
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.909408029
Short name T182
Test name
Test status
Simulation time 19116576 ps
CPU time 1.06 seconds
Started Aug 14 05:33:40 PM PDT 24
Finished Aug 14 05:33:41 PM PDT 24
Peak memory 218772 kb
Host smart-7c56f757-5eb1-457f-8fd3-2e17e429f74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909408029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.909408029
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3217538461
Short name T362
Test name
Test status
Simulation time 76166457 ps
CPU time 1.15 seconds
Started Aug 14 05:33:26 PM PDT 24
Finished Aug 14 05:33:28 PM PDT 24
Peak memory 217644 kb
Host smart-994ff6ec-e546-455a-ae76-2466934614e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217538461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3217538461
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.3749460228
Short name T125
Test name
Test status
Simulation time 85469863 ps
CPU time 1.22 seconds
Started Aug 14 05:33:20 PM PDT 24
Finished Aug 14 05:33:21 PM PDT 24
Peak memory 220228 kb
Host smart-d1d4c303-d3dc-4534-8d79-83aa70951a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749460228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.3749460228
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3271687733
Short name T663
Test name
Test status
Simulation time 38139572 ps
CPU time 0.95 seconds
Started Aug 14 05:33:10 PM PDT 24
Finished Aug 14 05:33:11 PM PDT 24
Peak memory 223988 kb
Host smart-145650ed-e607-40c3-88d3-0ff78c7e67b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271687733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3271687733
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2265904406
Short name T582
Test name
Test status
Simulation time 116060200 ps
CPU time 1.11 seconds
Started Aug 14 05:33:17 PM PDT 24
Finished Aug 14 05:33:19 PM PDT 24
Peak memory 217540 kb
Host smart-9e2c057e-d009-47db-95d8-28ba8c542ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265904406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2265904406
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.3703493617
Short name T300
Test name
Test status
Simulation time 45409729 ps
CPU time 1.18 seconds
Started Aug 14 05:33:17 PM PDT 24
Finished Aug 14 05:33:18 PM PDT 24
Peak memory 219456 kb
Host smart-4d03ddb8-30e4-4536-a7e6-cb587eb17125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703493617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.3703493617
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2270473785
Short name T129
Test name
Test status
Simulation time 49834214 ps
CPU time 1.06 seconds
Started Aug 14 05:33:21 PM PDT 24
Finished Aug 14 05:33:22 PM PDT 24
Peak memory 229648 kb
Host smart-214900aa-477d-43b0-95b8-4b2a6bef4137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270473785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2270473785
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.747010920
Short name T550
Test name
Test status
Simulation time 28813945 ps
CPU time 1.09 seconds
Started Aug 14 05:33:15 PM PDT 24
Finished Aug 14 05:33:16 PM PDT 24
Peak memory 218824 kb
Host smart-fc4dc916-5f66-42dc-9ca3-d9e22fe044f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747010920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.747010920
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1508313341
Short name T357
Test name
Test status
Simulation time 27238030 ps
CPU time 1.17 seconds
Started Aug 14 05:33:23 PM PDT 24
Finished Aug 14 05:33:24 PM PDT 24
Peak memory 220868 kb
Host smart-bfa05587-4d42-444b-a91e-b9fcbc6f894d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508313341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1508313341
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.2071278281
Short name T864
Test name
Test status
Simulation time 24742246 ps
CPU time 0.94 seconds
Started Aug 14 05:33:36 PM PDT 24
Finished Aug 14 05:33:37 PM PDT 24
Peak memory 218644 kb
Host smart-b23c4225-2950-49b8-a1bf-276755783495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071278281 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2071278281
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2208337470
Short name T386
Test name
Test status
Simulation time 131486430 ps
CPU time 2.68 seconds
Started Aug 14 05:33:26 PM PDT 24
Finished Aug 14 05:33:29 PM PDT 24
Peak memory 219040 kb
Host smart-c28b7e02-fe4a-4931-8c37-54e35672b526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208337470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2208337470
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.3904905851
Short name T142
Test name
Test status
Simulation time 27732941 ps
CPU time 1.26 seconds
Started Aug 14 05:33:38 PM PDT 24
Finished Aug 14 05:33:39 PM PDT 24
Peak memory 218840 kb
Host smart-b3c25782-d6c9-407e-b59f-a012714b7530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904905851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3904905851
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3372371551
Short name T165
Test name
Test status
Simulation time 32103705 ps
CPU time 1.26 seconds
Started Aug 14 05:33:19 PM PDT 24
Finished Aug 14 05:33:21 PM PDT 24
Peak memory 215676 kb
Host smart-873520bb-a4e7-4940-b065-a4e0e9abed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372371551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3372371551
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1470272245
Short name T675
Test name
Test status
Simulation time 718726082 ps
CPU time 6.09 seconds
Started Aug 14 05:33:16 PM PDT 24
Finished Aug 14 05:33:22 PM PDT 24
Peak memory 220476 kb
Host smart-f6f71082-b4a6-45eb-8a49-d33b58999d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470272245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1470272245
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.568814281
Short name T127
Test name
Test status
Simulation time 69763971 ps
CPU time 1.16 seconds
Started Aug 14 05:33:17 PM PDT 24
Finished Aug 14 05:33:18 PM PDT 24
Peak memory 218912 kb
Host smart-864fd929-712f-4180-bf8d-c9aa34d7b3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568814281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.568814281
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2635360021
Short name T968
Test name
Test status
Simulation time 44905537 ps
CPU time 1.09 seconds
Started Aug 14 05:33:11 PM PDT 24
Finished Aug 14 05:33:12 PM PDT 24
Peak memory 219992 kb
Host smart-1b69e456-790d-4833-ae42-977a1e359bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635360021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2635360021
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_alert.1301215664
Short name T583
Test name
Test status
Simulation time 87447922 ps
CPU time 1.26 seconds
Started Aug 14 05:33:18 PM PDT 24
Finished Aug 14 05:33:19 PM PDT 24
Peak memory 218892 kb
Host smart-039f17ca-e317-410d-a987-0a41488008fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301215664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1301215664
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.1981450739
Short name T620
Test name
Test status
Simulation time 20883461 ps
CPU time 0.91 seconds
Started Aug 14 05:33:38 PM PDT 24
Finished Aug 14 05:33:39 PM PDT 24
Peak memory 215756 kb
Host smart-4ad5bc42-4cac-44c2-addd-ddcb1a3d2c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981450739 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1981450739
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.551910761
Short name T704
Test name
Test status
Simulation time 181535242 ps
CPU time 0.91 seconds
Started Aug 14 05:33:14 PM PDT 24
Finished Aug 14 05:33:15 PM PDT 24
Peak memory 215668 kb
Host smart-9959d80a-6c98-42d8-91e2-1c37f25cb60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551910761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.551910761
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.265983426
Short name T295
Test name
Test status
Simulation time 101913465 ps
CPU time 1.18 seconds
Started Aug 14 05:32:14 PM PDT 24
Finished Aug 14 05:32:15 PM PDT 24
Peak memory 218824 kb
Host smart-b9783d72-baab-4751-8939-bda0755052e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265983426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.265983426
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.262380406
Short name T608
Test name
Test status
Simulation time 27480393 ps
CPU time 0.93 seconds
Started Aug 14 05:32:03 PM PDT 24
Finished Aug 14 05:32:04 PM PDT 24
Peak memory 215220 kb
Host smart-ff69d2e1-ddc1-4653-a0ee-e882cc94d6f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262380406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.262380406
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1203313540
Short name T93
Test name
Test status
Simulation time 17025425 ps
CPU time 0.81 seconds
Started Aug 14 05:32:07 PM PDT 24
Finished Aug 14 05:32:08 PM PDT 24
Peak memory 215728 kb
Host smart-141b7496-9db9-4fad-a0e1-1bc98be4b39b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203313540 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1203313540
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.961325167
Short name T669
Test name
Test status
Simulation time 75643578 ps
CPU time 1.04 seconds
Started Aug 14 05:32:13 PM PDT 24
Finished Aug 14 05:32:14 PM PDT 24
Peak memory 219152 kb
Host smart-74d33690-2853-44ff-ac33-444300aafd16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961325167 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.961325167
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2283265207
Short name T203
Test name
Test status
Simulation time 20185153 ps
CPU time 1.17 seconds
Started Aug 14 05:32:06 PM PDT 24
Finished Aug 14 05:32:07 PM PDT 24
Peak memory 224192 kb
Host smart-f91b7699-c8c5-4de1-b114-4727fd55d73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283265207 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2283265207
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2394556607
Short name T811
Test name
Test status
Simulation time 41284131 ps
CPU time 1.75 seconds
Started Aug 14 05:31:59 PM PDT 24
Finished Aug 14 05:32:01 PM PDT 24
Peak memory 218964 kb
Host smart-e7109cfa-a9ad-4fa4-80ff-4509321f56af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394556607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2394556607
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3003750861
Short name T433
Test name
Test status
Simulation time 21864490 ps
CPU time 1 seconds
Started Aug 14 05:32:00 PM PDT 24
Finished Aug 14 05:32:01 PM PDT 24
Peak memory 216020 kb
Host smart-bb4e4398-031c-41dd-89ce-8604a1fb3638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003750861 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3003750861
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3235001441
Short name T937
Test name
Test status
Simulation time 16656294 ps
CPU time 0.98 seconds
Started Aug 14 05:32:14 PM PDT 24
Finished Aug 14 05:32:15 PM PDT 24
Peak memory 207368 kb
Host smart-3e207d08-3838-4549-9f4b-7d95d816f359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235001441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3235001441
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.985984071
Short name T66
Test name
Test status
Simulation time 19549460 ps
CPU time 0.97 seconds
Started Aug 14 05:32:03 PM PDT 24
Finished Aug 14 05:32:04 PM PDT 24
Peak memory 215620 kb
Host smart-c65d169f-9787-4e5a-9b50-e61731e1e5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985984071 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.985984071
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.549517151
Short name T453
Test name
Test status
Simulation time 628413752 ps
CPU time 2.2 seconds
Started Aug 14 05:32:13 PM PDT 24
Finished Aug 14 05:32:15 PM PDT 24
Peak memory 215712 kb
Host smart-6c0c47e0-f5f1-4e87-8a1f-f76e77fb34e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549517151 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.549517151
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3640934764
Short name T235
Test name
Test status
Simulation time 8605375057 ps
CPU time 58 seconds
Started Aug 14 05:32:09 PM PDT 24
Finished Aug 14 05:33:07 PM PDT 24
Peak memory 218416 kb
Host smart-ec82a2cf-be93-4ccc-ae84-5a31a412105d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640934764 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3640934764
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.249956605
Short name T554
Test name
Test status
Simulation time 125178545 ps
CPU time 1.17 seconds
Started Aug 14 05:33:18 PM PDT 24
Finished Aug 14 05:33:19 PM PDT 24
Peak memory 220664 kb
Host smart-41c9d49f-55a2-4a43-a867-84aca51b8b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249956605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.249956605
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3556136022
Short name T226
Test name
Test status
Simulation time 41070252 ps
CPU time 1.19 seconds
Started Aug 14 05:33:35 PM PDT 24
Finished Aug 14 05:33:37 PM PDT 24
Peak memory 225892 kb
Host smart-92a0d75b-3892-4d70-9a62-f01751a4aaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556136022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3556136022
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.117864738
Short name T264
Test name
Test status
Simulation time 92869750 ps
CPU time 2.01 seconds
Started Aug 14 05:33:22 PM PDT 24
Finished Aug 14 05:33:24 PM PDT 24
Peak memory 217796 kb
Host smart-5be19a28-81b4-4b1a-89b0-78ee62938ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117864738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.117864738
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2748057364
Short name T789
Test name
Test status
Simulation time 48177809 ps
CPU time 1.22 seconds
Started Aug 14 05:33:17 PM PDT 24
Finished Aug 14 05:33:19 PM PDT 24
Peak memory 221276 kb
Host smart-bb817f20-9b40-481e-8feb-f209e1d19e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748057364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2748057364
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2795377744
Short name T63
Test name
Test status
Simulation time 41315809 ps
CPU time 1.23 seconds
Started Aug 14 05:33:35 PM PDT 24
Finished Aug 14 05:33:36 PM PDT 24
Peak memory 225988 kb
Host smart-5d4f556e-f940-4a66-a1a0-aa544882b88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795377744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2795377744
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3625903520
Short name T934
Test name
Test status
Simulation time 50297864 ps
CPU time 1.21 seconds
Started Aug 14 05:33:08 PM PDT 24
Finished Aug 14 05:33:10 PM PDT 24
Peak memory 219088 kb
Host smart-28dcf122-836c-4368-8a95-430eccce0985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625903520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3625903520
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3718800188
Short name T547
Test name
Test status
Simulation time 32824527 ps
CPU time 1.18 seconds
Started Aug 14 05:33:22 PM PDT 24
Finished Aug 14 05:33:23 PM PDT 24
Peak memory 218924 kb
Host smart-d6bc7210-cb17-4091-bcf7-2adefe2c6c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718800188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3718800188
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3037154417
Short name T756
Test name
Test status
Simulation time 27492655 ps
CPU time 0.9 seconds
Started Aug 14 05:33:16 PM PDT 24
Finished Aug 14 05:33:17 PM PDT 24
Peak memory 218508 kb
Host smart-a070f7b5-bf3d-4435-a9df-ed9eb05bd3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037154417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3037154417
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.4199609048
Short name T613
Test name
Test status
Simulation time 113301507 ps
CPU time 1.39 seconds
Started Aug 14 05:33:19 PM PDT 24
Finished Aug 14 05:33:20 PM PDT 24
Peak memory 220168 kb
Host smart-916f6fcd-9152-4701-970b-ddb86b7fb2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199609048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.4199609048
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.611621736
Short name T316
Test name
Test status
Simulation time 40462738 ps
CPU time 1.15 seconds
Started Aug 14 05:33:21 PM PDT 24
Finished Aug 14 05:33:22 PM PDT 24
Peak memory 218868 kb
Host smart-cff767ea-9041-40ed-b617-201e6d36fa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611621736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.611621736
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.1123930605
Short name T195
Test name
Test status
Simulation time 19582734 ps
CPU time 1.2 seconds
Started Aug 14 05:33:26 PM PDT 24
Finished Aug 14 05:33:27 PM PDT 24
Peak memory 224152 kb
Host smart-6eda55a9-1b44-4056-a9c6-181ca282db4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123930605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1123930605
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1865775178
Short name T365
Test name
Test status
Simulation time 35360927 ps
CPU time 1.33 seconds
Started Aug 14 05:33:30 PM PDT 24
Finished Aug 14 05:33:32 PM PDT 24
Peak memory 217516 kb
Host smart-bfb8f20f-b3c7-4855-b17b-12e86fed3e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865775178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1865775178
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1262253872
Short name T858
Test name
Test status
Simulation time 24279493 ps
CPU time 1.22 seconds
Started Aug 14 05:33:15 PM PDT 24
Finished Aug 14 05:33:16 PM PDT 24
Peak memory 218768 kb
Host smart-47289450-2e20-4644-832e-597bb3e6faa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262253872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1262253872
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1661889908
Short name T151
Test name
Test status
Simulation time 30622472 ps
CPU time 1.07 seconds
Started Aug 14 05:33:18 PM PDT 24
Finished Aug 14 05:33:20 PM PDT 24
Peak memory 219924 kb
Host smart-56d5c11f-3db0-4758-b447-47ac4d47e07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661889908 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1661889908
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3554376894
Short name T484
Test name
Test status
Simulation time 69526072 ps
CPU time 1.3 seconds
Started Aug 14 05:33:10 PM PDT 24
Finished Aug 14 05:33:11 PM PDT 24
Peak memory 219292 kb
Host smart-7a526c5e-3012-4150-898d-8dc90535845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554376894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3554376894
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.26027867
Short name T88
Test name
Test status
Simulation time 28147657 ps
CPU time 1.3 seconds
Started Aug 14 05:33:24 PM PDT 24
Finished Aug 14 05:33:25 PM PDT 24
Peak memory 218948 kb
Host smart-49e0364e-5b5a-4c0f-8295-f82ad5f24449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26027867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.26027867
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1012049520
Short name T123
Test name
Test status
Simulation time 20563380 ps
CPU time 1.32 seconds
Started Aug 14 05:33:41 PM PDT 24
Finished Aug 14 05:33:42 PM PDT 24
Peak memory 229924 kb
Host smart-88aea4ef-0362-4fb4-9de6-9d4aaa5ffd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012049520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1012049520
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1065795454
Short name T534
Test name
Test status
Simulation time 51975116 ps
CPU time 1.25 seconds
Started Aug 14 05:33:35 PM PDT 24
Finished Aug 14 05:33:36 PM PDT 24
Peak memory 217688 kb
Host smart-1c92e42f-9f21-41eb-9c49-e354bee4853c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065795454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1065795454
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.3681025845
Short name T446
Test name
Test status
Simulation time 90559703 ps
CPU time 1.15 seconds
Started Aug 14 05:33:25 PM PDT 24
Finished Aug 14 05:33:26 PM PDT 24
Peak memory 218900 kb
Host smart-d21b7ada-edb6-402e-aaa5-6c4d365dd38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681025845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.3681025845
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2803589440
Short name T146
Test name
Test status
Simulation time 25632206 ps
CPU time 1.1 seconds
Started Aug 14 05:33:16 PM PDT 24
Finished Aug 14 05:33:18 PM PDT 24
Peak memory 229484 kb
Host smart-2430f957-2063-4e56-bd9b-b59b699d41c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803589440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2803589440
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/87.edn_alert.3455990700
Short name T759
Test name
Test status
Simulation time 24488643 ps
CPU time 1.22 seconds
Started Aug 14 05:33:36 PM PDT 24
Finished Aug 14 05:33:37 PM PDT 24
Peak memory 219928 kb
Host smart-37f0e9e9-d123-451d-8b59-b18f6aa42bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455990700 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3455990700
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.4291681678
Short name T183
Test name
Test status
Simulation time 32837406 ps
CPU time 0.92 seconds
Started Aug 14 05:33:21 PM PDT 24
Finished Aug 14 05:33:22 PM PDT 24
Peak memory 218408 kb
Host smart-148e4689-e299-4bca-9a5a-25e23360de00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291681678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.4291681678
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/88.edn_alert.492447205
Short name T661
Test name
Test status
Simulation time 105238250 ps
CPU time 1.17 seconds
Started Aug 14 05:33:25 PM PDT 24
Finished Aug 14 05:33:26 PM PDT 24
Peak memory 219024 kb
Host smart-520efdd7-060f-4c3d-9ba6-38191b794528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492447205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.492447205
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1184362208
Short name T607
Test name
Test status
Simulation time 29553291 ps
CPU time 0.86 seconds
Started Aug 14 05:33:46 PM PDT 24
Finished Aug 14 05:33:47 PM PDT 24
Peak memory 218280 kb
Host smart-a4eb4b8e-7168-480e-8522-986252f72c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184362208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1184362208
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1285049624
Short name T886
Test name
Test status
Simulation time 72253922 ps
CPU time 1.72 seconds
Started Aug 14 05:33:36 PM PDT 24
Finished Aug 14 05:33:37 PM PDT 24
Peak memory 219012 kb
Host smart-124b4aca-8307-4126-bb55-4aa8811b5bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285049624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1285049624
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.3772399293
Short name T58
Test name
Test status
Simulation time 24981995 ps
CPU time 1.24 seconds
Started Aug 14 05:33:37 PM PDT 24
Finished Aug 14 05:33:39 PM PDT 24
Peak memory 219228 kb
Host smart-86ddf539-b940-491f-a396-1121f16a52b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772399293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3772399293
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1203758202
Short name T546
Test name
Test status
Simulation time 18107833 ps
CPU time 1.06 seconds
Started Aug 14 05:33:28 PM PDT 24
Finished Aug 14 05:33:29 PM PDT 24
Peak memory 218768 kb
Host smart-40c3849c-8d5e-4caf-9597-e2c81f2078ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203758202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1203758202
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.573259403
Short name T514
Test name
Test status
Simulation time 41447382 ps
CPU time 1.41 seconds
Started Aug 14 05:33:24 PM PDT 24
Finished Aug 14 05:33:26 PM PDT 24
Peak memory 217644 kb
Host smart-d54a5239-ce4c-443d-935a-1dbe5e46fd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573259403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.573259403
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1591466224
Short name T956
Test name
Test status
Simulation time 24471417 ps
CPU time 1.17 seconds
Started Aug 14 05:32:15 PM PDT 24
Finished Aug 14 05:32:16 PM PDT 24
Peak memory 221044 kb
Host smart-4783556f-cf88-4575-a49b-05659798d4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591466224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1591466224
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3918023785
Short name T530
Test name
Test status
Simulation time 13587691 ps
CPU time 0.93 seconds
Started Aug 14 05:32:17 PM PDT 24
Finished Aug 14 05:32:17 PM PDT 24
Peak memory 207088 kb
Host smart-bb4bc0f4-00f2-410b-a4e7-9f29fbafa6b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918023785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3918023785
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2714838743
Short name T865
Test name
Test status
Simulation time 71989600 ps
CPU time 0.88 seconds
Started Aug 14 05:32:10 PM PDT 24
Finished Aug 14 05:32:11 PM PDT 24
Peak memory 216516 kb
Host smart-89eba782-7d34-441d-9bb6-d9f38440dca8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714838743 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2714838743
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.294822380
Short name T768
Test name
Test status
Simulation time 452275944 ps
CPU time 1.11 seconds
Started Aug 14 05:32:08 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 219836 kb
Host smart-00357deb-bc5f-4714-aa6e-8ac69009d1fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294822380 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.294822380
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2516562980
Short name T406
Test name
Test status
Simulation time 47488716 ps
CPU time 0.93 seconds
Started Aug 14 05:32:10 PM PDT 24
Finished Aug 14 05:32:11 PM PDT 24
Peak memory 219816 kb
Host smart-412a683b-8e5c-405e-b4d1-1d163733d9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516562980 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2516562980
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.603044862
Short name T416
Test name
Test status
Simulation time 163040850 ps
CPU time 1.17 seconds
Started Aug 14 05:32:17 PM PDT 24
Finished Aug 14 05:32:18 PM PDT 24
Peak memory 217576 kb
Host smart-fc3923b1-ae42-4732-bdd9-56fcc4e56ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603044862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.603044862
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3784962385
Short name T631
Test name
Test status
Simulation time 21999278 ps
CPU time 0.92 seconds
Started Aug 14 05:32:21 PM PDT 24
Finished Aug 14 05:32:22 PM PDT 24
Peak memory 216020 kb
Host smart-dfe5d93a-9682-4b84-8d35-d26365d5c306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784962385 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3784962385
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2215092204
Short name T32
Test name
Test status
Simulation time 18293231 ps
CPU time 1.03 seconds
Started Aug 14 05:32:05 PM PDT 24
Finished Aug 14 05:32:07 PM PDT 24
Peak memory 207448 kb
Host smart-0a212a78-29f0-4b04-b71c-4e50abe417a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215092204 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2215092204
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3811004325
Short name T349
Test name
Test status
Simulation time 18920207 ps
CPU time 1.03 seconds
Started Aug 14 05:32:14 PM PDT 24
Finished Aug 14 05:32:15 PM PDT 24
Peak memory 213920 kb
Host smart-91f31559-b0bf-4be5-bdae-137a22c1d886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811004325 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3811004325
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/90.edn_alert.796952359
Short name T157
Test name
Test status
Simulation time 27134287 ps
CPU time 1.2 seconds
Started Aug 14 05:33:43 PM PDT 24
Finished Aug 14 05:33:45 PM PDT 24
Peak memory 220040 kb
Host smart-6ed9ffa9-f05a-4fd9-960c-cde477d63880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796952359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.796952359
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.4164973037
Short name T377
Test name
Test status
Simulation time 32310406 ps
CPU time 1.02 seconds
Started Aug 14 05:33:26 PM PDT 24
Finished Aug 14 05:33:27 PM PDT 24
Peak memory 218844 kb
Host smart-5e98964b-8b03-423e-bf19-c508f8d2d88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164973037 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.4164973037
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3576609224
Short name T928
Test name
Test status
Simulation time 68557659 ps
CPU time 1.19 seconds
Started Aug 14 05:33:33 PM PDT 24
Finished Aug 14 05:33:34 PM PDT 24
Peak memory 220580 kb
Host smart-14e50a91-3287-4e2c-b578-f4e872811a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576609224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3576609224
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.843610844
Short name T171
Test name
Test status
Simulation time 54074938 ps
CPU time 1.22 seconds
Started Aug 14 05:33:46 PM PDT 24
Finished Aug 14 05:33:48 PM PDT 24
Peak memory 220172 kb
Host smart-9a4bfe63-c6d2-40a1-9ae1-74416c520df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843610844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.843610844
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.1296160631
Short name T16
Test name
Test status
Simulation time 25816733 ps
CPU time 1.08 seconds
Started Aug 14 05:33:22 PM PDT 24
Finished Aug 14 05:33:23 PM PDT 24
Peak memory 229832 kb
Host smart-52005843-b86c-45f6-8d88-06a67c800152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296160631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1296160631
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3274976921
Short name T327
Test name
Test status
Simulation time 91170182 ps
CPU time 1.52 seconds
Started Aug 14 05:33:20 PM PDT 24
Finished Aug 14 05:33:22 PM PDT 24
Peak memory 218700 kb
Host smart-097a0f57-a6ce-4c57-9d96-05a8c1125084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274976921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3274976921
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.399165086
Short name T883
Test name
Test status
Simulation time 80524917 ps
CPU time 1.12 seconds
Started Aug 14 05:33:41 PM PDT 24
Finished Aug 14 05:33:43 PM PDT 24
Peak memory 220956 kb
Host smart-47b3819f-c85e-4b47-bf2c-c4f19d4ca3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399165086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.399165086
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3994969015
Short name T140
Test name
Test status
Simulation time 74118446 ps
CPU time 0.93 seconds
Started Aug 14 05:33:24 PM PDT 24
Finished Aug 14 05:33:25 PM PDT 24
Peak memory 219856 kb
Host smart-3a6f0ed5-649d-4c7b-8556-530f7eeb6b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994969015 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3994969015
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1208508367
Short name T940
Test name
Test status
Simulation time 71426917 ps
CPU time 1.21 seconds
Started Aug 14 05:33:24 PM PDT 24
Finished Aug 14 05:33:25 PM PDT 24
Peak memory 220044 kb
Host smart-5f0589c9-d4e0-4519-9ab9-a96c5946daf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208508367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1208508367
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.408515149
Short name T619
Test name
Test status
Simulation time 44690051 ps
CPU time 1.15 seconds
Started Aug 14 05:33:46 PM PDT 24
Finished Aug 14 05:33:48 PM PDT 24
Peak memory 219120 kb
Host smart-b6ab7793-3842-462a-8b75-3b92ecc7cae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408515149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.408515149
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.863437730
Short name T189
Test name
Test status
Simulation time 19203506 ps
CPU time 1.14 seconds
Started Aug 14 05:33:26 PM PDT 24
Finished Aug 14 05:33:27 PM PDT 24
Peak memory 224216 kb
Host smart-ed57cdca-01f2-4f77-9dbd-2b3fa2497b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863437730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.863437730
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2261224361
Short name T529
Test name
Test status
Simulation time 52032521 ps
CPU time 1.67 seconds
Started Aug 14 05:33:45 PM PDT 24
Finished Aug 14 05:33:47 PM PDT 24
Peak memory 215608 kb
Host smart-cf573842-1732-411c-b337-89e273d9b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261224361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2261224361
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1175976594
Short name T99
Test name
Test status
Simulation time 75070580 ps
CPU time 1.07 seconds
Started Aug 14 05:33:54 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 220024 kb
Host smart-7323ee52-7806-449f-9c62-7b4a21906030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175976594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1175976594
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.154962322
Short name T487
Test name
Test status
Simulation time 32924363 ps
CPU time 0.92 seconds
Started Aug 14 05:33:36 PM PDT 24
Finished Aug 14 05:33:36 PM PDT 24
Peak memory 218468 kb
Host smart-078e35bc-ac1d-4944-b254-8e48d04318b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154962322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.154962322
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3539617070
Short name T322
Test name
Test status
Simulation time 47846918 ps
CPU time 1.84 seconds
Started Aug 14 05:33:41 PM PDT 24
Finished Aug 14 05:33:42 PM PDT 24
Peak memory 217800 kb
Host smart-05069554-38ad-4250-aab2-cdcc3cf73590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539617070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3539617070
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1088822061
Short name T163
Test name
Test status
Simulation time 33821015 ps
CPU time 0.93 seconds
Started Aug 14 05:33:26 PM PDT 24
Finished Aug 14 05:33:27 PM PDT 24
Peak memory 219988 kb
Host smart-8ba4126d-9f5c-4d89-9d74-61b0dd0dba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088822061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1088822061
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2408232242
Short name T430
Test name
Test status
Simulation time 48940464 ps
CPU time 1.8 seconds
Started Aug 14 05:33:23 PM PDT 24
Finished Aug 14 05:33:25 PM PDT 24
Peak memory 218816 kb
Host smart-349d24df-c294-46f0-9824-ffcea96d1de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408232242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2408232242
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.3987552746
Short name T258
Test name
Test status
Simulation time 47427686 ps
CPU time 1.19 seconds
Started Aug 14 05:33:27 PM PDT 24
Finished Aug 14 05:33:28 PM PDT 24
Peak memory 220912 kb
Host smart-3b9d18ee-84a7-42a2-a7da-cf4c0e9ea9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987552746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.3987552746
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.339714588
Short name T821
Test name
Test status
Simulation time 25089892 ps
CPU time 0.93 seconds
Started Aug 14 05:33:26 PM PDT 24
Finished Aug 14 05:33:27 PM PDT 24
Peak memory 218596 kb
Host smart-2adb8005-3a74-4894-8f93-3d3cd1e31825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339714588 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.339714588
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3675303077
Short name T808
Test name
Test status
Simulation time 55419271 ps
CPU time 1.22 seconds
Started Aug 14 05:33:28 PM PDT 24
Finished Aug 14 05:33:29 PM PDT 24
Peak memory 218844 kb
Host smart-180f0ba4-b0f9-48fe-8075-382bf06bbbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675303077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3675303077
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3337791455
Short name T892
Test name
Test status
Simulation time 45941430 ps
CPU time 1.25 seconds
Started Aug 14 05:33:48 PM PDT 24
Finished Aug 14 05:33:50 PM PDT 24
Peak memory 216004 kb
Host smart-9e8e65b0-325b-4499-a0f7-500d327c3911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337791455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3337791455
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.3798965196
Short name T838
Test name
Test status
Simulation time 28442830 ps
CPU time 1.1 seconds
Started Aug 14 05:33:20 PM PDT 24
Finished Aug 14 05:33:22 PM PDT 24
Peak memory 218908 kb
Host smart-acac9712-f8ba-4d92-894e-427d34679e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798965196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3798965196
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1401921086
Short name T725
Test name
Test status
Simulation time 62134109 ps
CPU time 1.17 seconds
Started Aug 14 05:33:27 PM PDT 24
Finished Aug 14 05:33:29 PM PDT 24
Peak memory 217656 kb
Host smart-e30ceecf-ccd5-4165-bd73-60cc22644a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401921086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1401921086
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.1784086357
Short name T587
Test name
Test status
Simulation time 30705140 ps
CPU time 1.21 seconds
Started Aug 14 05:33:49 PM PDT 24
Finished Aug 14 05:33:50 PM PDT 24
Peak memory 220036 kb
Host smart-ac1903ed-1b2d-4f7f-acb3-6a5d1164cf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784086357 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.1784086357
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.929001017
Short name T174
Test name
Test status
Simulation time 29445467 ps
CPU time 0.86 seconds
Started Aug 14 05:33:43 PM PDT 24
Finished Aug 14 05:33:44 PM PDT 24
Peak memory 218292 kb
Host smart-d6ac70d0-a213-4b81-9139-5a584239db1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929001017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.929001017
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3818509266
Short name T533
Test name
Test status
Simulation time 253057062 ps
CPU time 1.12 seconds
Started Aug 14 05:33:24 PM PDT 24
Finished Aug 14 05:33:25 PM PDT 24
Peak memory 217456 kb
Host smart-a97bd04d-edd2-4637-87b0-d50f83355b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818509266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3818509266
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3789894665
Short name T939
Test name
Test status
Simulation time 25853346 ps
CPU time 1.2 seconds
Started Aug 14 05:34:13 PM PDT 24
Finished Aug 14 05:34:14 PM PDT 24
Peak memory 219984 kb
Host smart-55264a42-4f9f-42c9-aeb2-5da9a78a0735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789894665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3789894665
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3003474830
Short name T225
Test name
Test status
Simulation time 101680440 ps
CPU time 0.96 seconds
Started Aug 14 05:33:32 PM PDT 24
Finished Aug 14 05:33:33 PM PDT 24
Peak memory 223980 kb
Host smart-6bf45620-793c-4389-9dec-cc1eaa9ecef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003474830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3003474830
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2002744991
Short name T586
Test name
Test status
Simulation time 38901225 ps
CPU time 1.44 seconds
Started Aug 14 05:33:27 PM PDT 24
Finished Aug 14 05:33:29 PM PDT 24
Peak memory 218728 kb
Host smart-792e2b0c-ecd7-4895-ba84-16a9cbefc415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002744991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2002744991
Directory /workspace/99.edn_genbits/latest
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